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drm/exynos: restore parallel output interface support
[deliverable/linux.git] / drivers / gpu / drm / exynos / exynos_drm_fimd.c
1 /* exynos_drm_fimd.c
2 *
3 * Copyright (C) 2011 Samsung Electronics Co.Ltd
4 * Authors:
5 * Joonyoung Shim <jy0922.shim@samsung.com>
6 * Inki Dae <inki.dae@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14 #include <drm/drmP.h>
15
16 #include <linux/kernel.h>
17 #include <linux/platform_device.h>
18 #include <linux/clk.h>
19 #include <linux/of.h>
20 #include <linux/of_device.h>
21 #include <linux/pm_runtime.h>
22
23 #include <video/of_display_timing.h>
24 #include <video/of_videomode.h>
25 #include <video/samsung_fimd.h>
26 #include <drm/exynos_drm.h>
27
28 #include "exynos_drm_drv.h"
29 #include "exynos_drm_fbdev.h"
30 #include "exynos_drm_crtc.h"
31 #include "exynos_drm_iommu.h"
32
33 /*
34 * FIMD stands for Fully Interactive Mobile Display and
35 * as a display controller, it transfers contents drawn on memory
36 * to a LCD Panel through Display Interfaces such as RGB or
37 * CPU Interface.
38 */
39
40 #define FIMD_DEFAULT_FRAMERATE 60
41
42 /* position control register for hardware window 0, 2 ~ 4.*/
43 #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
44 #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
45 /*
46 * size control register for hardware windows 0 and alpha control register
47 * for hardware windows 1 ~ 4
48 */
49 #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16)
50 /* size control register for hardware windows 1 ~ 2. */
51 #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
52
53 #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
54 #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8)
55 #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
56
57 /* color key control register for hardware window 1 ~ 4. */
58 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8))
59 /* color key value register for hardware window 1 ~ 4. */
60 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
61
62 /* FIMD has totally five hardware windows. */
63 #define WINDOWS_NR 5
64
65 #define get_fimd_manager(mgr) platform_get_drvdata(to_platform_device(dev))
66
67 struct fimd_driver_data {
68 unsigned int timing_base;
69
70 unsigned int has_shadowcon:1;
71 unsigned int has_clksel:1;
72 unsigned int has_limited_fmt:1;
73 };
74
75 static struct fimd_driver_data s3c64xx_fimd_driver_data = {
76 .timing_base = 0x0,
77 .has_clksel = 1,
78 .has_limited_fmt = 1,
79 };
80
81 static struct fimd_driver_data exynos4_fimd_driver_data = {
82 .timing_base = 0x0,
83 .has_shadowcon = 1,
84 };
85
86 static struct fimd_driver_data exynos5_fimd_driver_data = {
87 .timing_base = 0x20000,
88 .has_shadowcon = 1,
89 };
90
91 struct fimd_win_data {
92 unsigned int offset_x;
93 unsigned int offset_y;
94 unsigned int ovl_width;
95 unsigned int ovl_height;
96 unsigned int fb_width;
97 unsigned int fb_height;
98 unsigned int bpp;
99 unsigned int pixel_format;
100 dma_addr_t dma_addr;
101 unsigned int buf_offsize;
102 unsigned int line_size; /* bytes */
103 bool enabled;
104 bool resume;
105 };
106
107 struct fimd_context {
108 struct device *dev;
109 struct drm_device *drm_dev;
110 struct clk *bus_clk;
111 struct clk *lcd_clk;
112 void __iomem *regs;
113 struct drm_display_mode mode;
114 struct fimd_win_data win_data[WINDOWS_NR];
115 unsigned int default_win;
116 unsigned long irq_flags;
117 u32 vidcon0;
118 u32 vidcon1;
119 bool suspended;
120 int pipe;
121 wait_queue_head_t wait_vsync_queue;
122 atomic_t wait_vsync_event;
123
124 struct exynos_drm_panel_info panel;
125 struct fimd_driver_data *driver_data;
126 };
127
128 static const struct of_device_id fimd_driver_dt_match[] = {
129 { .compatible = "samsung,s3c6400-fimd",
130 .data = &s3c64xx_fimd_driver_data },
131 { .compatible = "samsung,exynos4210-fimd",
132 .data = &exynos4_fimd_driver_data },
133 { .compatible = "samsung,exynos5250-fimd",
134 .data = &exynos5_fimd_driver_data },
135 {},
136 };
137
138 static inline struct fimd_driver_data *drm_fimd_get_driver_data(
139 struct platform_device *pdev)
140 {
141 const struct of_device_id *of_id =
142 of_match_device(fimd_driver_dt_match, &pdev->dev);
143
144 return (struct fimd_driver_data *)of_id->data;
145 }
146
147 static int fimd_mgr_initialize(struct exynos_drm_manager *mgr,
148 struct drm_device *drm_dev, int pipe)
149 {
150 struct fimd_context *ctx = mgr->ctx;
151
152 ctx->drm_dev = drm_dev;
153 ctx->pipe = pipe;
154
155 /*
156 * enable drm irq mode.
157 * - with irq_enabled = true, we can use the vblank feature.
158 *
159 * P.S. note that we wouldn't use drm irq handler but
160 * just specific driver own one instead because
161 * drm framework supports only one irq handler.
162 */
163 drm_dev->irq_enabled = true;
164
165 /*
166 * with vblank_disable_allowed = true, vblank interrupt will be disabled
167 * by drm timer once a current process gives up ownership of
168 * vblank event.(after drm_vblank_put function is called)
169 */
170 drm_dev->vblank_disable_allowed = true;
171
172 /* attach this sub driver to iommu mapping if supported. */
173 if (is_drm_iommu_supported(ctx->drm_dev))
174 drm_iommu_attach_device(ctx->drm_dev, ctx->dev);
175
176 return 0;
177 }
178
179 static void fimd_mgr_remove(struct exynos_drm_manager *mgr)
180 {
181 struct fimd_context *ctx = mgr->ctx;
182
183 /* detach this sub driver from iommu mapping if supported. */
184 if (is_drm_iommu_supported(ctx->drm_dev))
185 drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
186 }
187
188 static u32 fimd_calc_clkdiv(struct fimd_context *ctx,
189 const struct drm_display_mode *mode)
190 {
191 unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
192 u32 clkdiv;
193
194 /* Find the clock divider value that gets us closest to ideal_clk */
195 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->lcd_clk), ideal_clk);
196
197 return (clkdiv < 0x100) ? clkdiv : 0xff;
198 }
199
200 static bool fimd_mode_fixup(struct exynos_drm_manager *mgr,
201 const struct drm_display_mode *mode,
202 struct drm_display_mode *adjusted_mode)
203 {
204 if (adjusted_mode->vrefresh == 0)
205 adjusted_mode->vrefresh = FIMD_DEFAULT_FRAMERATE;
206
207 return true;
208 }
209
210 static void fimd_mode_set(struct exynos_drm_manager *mgr,
211 const struct drm_display_mode *in_mode)
212 {
213 struct fimd_context *ctx = mgr->ctx;
214
215 drm_mode_copy(&ctx->mode, in_mode);
216 }
217
218 static void fimd_commit(struct exynos_drm_manager *mgr)
219 {
220 struct fimd_context *ctx = mgr->ctx;
221 struct drm_display_mode *mode = &ctx->mode;
222 struct fimd_driver_data *driver_data;
223 u32 val, clkdiv, vidcon1;
224 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
225
226 driver_data = ctx->driver_data;
227 if (ctx->suspended)
228 return;
229
230 /* nothing to do if we haven't set the mode yet */
231 if (mode->htotal == 0 || mode->vtotal == 0)
232 return;
233
234 /* setup polarity values */
235 vidcon1 = ctx->vidcon1;
236 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
237 vidcon1 |= VIDCON1_INV_VSYNC;
238 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
239 vidcon1 |= VIDCON1_INV_HSYNC;
240 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
241
242 /* setup vertical timing values. */
243 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
244 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
245 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
246
247 val = VIDTCON0_VBPD(vbpd - 1) |
248 VIDTCON0_VFPD(vfpd - 1) |
249 VIDTCON0_VSPW(vsync_len - 1);
250 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
251
252 /* setup horizontal timing values. */
253 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
254 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
255 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
256
257 val = VIDTCON1_HBPD(hbpd - 1) |
258 VIDTCON1_HFPD(hfpd - 1) |
259 VIDTCON1_HSPW(hsync_len - 1);
260 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
261
262 /* setup horizontal and vertical display size. */
263 val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
264 VIDTCON2_HOZVAL(mode->hdisplay - 1) |
265 VIDTCON2_LINEVAL_E(mode->vdisplay - 1) |
266 VIDTCON2_HOZVAL_E(mode->hdisplay - 1);
267 writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
268
269 /* setup clock source, clock divider, enable dma. */
270 val = ctx->vidcon0;
271 val &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR);
272
273 if (ctx->driver_data->has_clksel) {
274 val &= ~VIDCON0_CLKSEL_MASK;
275 val |= VIDCON0_CLKSEL_LCD;
276 }
277
278 clkdiv = fimd_calc_clkdiv(ctx, mode);
279 if (clkdiv > 1)
280 val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR;
281 else
282 val &= ~VIDCON0_CLKDIR; /* 1:1 clock */
283
284 /*
285 * fields of register with prefix '_F' would be updated
286 * at vsync(same as dma start)
287 */
288 val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
289 writel(val, ctx->regs + VIDCON0);
290 }
291
292 static int fimd_enable_vblank(struct exynos_drm_manager *mgr)
293 {
294 struct fimd_context *ctx = mgr->ctx;
295 u32 val;
296
297 if (ctx->suspended)
298 return -EPERM;
299
300 if (!test_and_set_bit(0, &ctx->irq_flags)) {
301 val = readl(ctx->regs + VIDINTCON0);
302
303 val |= VIDINTCON0_INT_ENABLE;
304 val |= VIDINTCON0_INT_FRAME;
305
306 val &= ~VIDINTCON0_FRAMESEL0_MASK;
307 val |= VIDINTCON0_FRAMESEL0_VSYNC;
308 val &= ~VIDINTCON0_FRAMESEL1_MASK;
309 val |= VIDINTCON0_FRAMESEL1_NONE;
310
311 writel(val, ctx->regs + VIDINTCON0);
312 }
313
314 return 0;
315 }
316
317 static void fimd_disable_vblank(struct exynos_drm_manager *mgr)
318 {
319 struct fimd_context *ctx = mgr->ctx;
320 u32 val;
321
322 if (ctx->suspended)
323 return;
324
325 if (test_and_clear_bit(0, &ctx->irq_flags)) {
326 val = readl(ctx->regs + VIDINTCON0);
327
328 val &= ~VIDINTCON0_INT_FRAME;
329 val &= ~VIDINTCON0_INT_ENABLE;
330
331 writel(val, ctx->regs + VIDINTCON0);
332 }
333 }
334
335 static void fimd_wait_for_vblank(struct exynos_drm_manager *mgr)
336 {
337 struct fimd_context *ctx = mgr->ctx;
338
339 if (ctx->suspended)
340 return;
341
342 atomic_set(&ctx->wait_vsync_event, 1);
343
344 /*
345 * wait for FIMD to signal VSYNC interrupt or return after
346 * timeout which is set to 50ms (refresh rate of 20).
347 */
348 if (!wait_event_timeout(ctx->wait_vsync_queue,
349 !atomic_read(&ctx->wait_vsync_event),
350 HZ/20))
351 DRM_DEBUG_KMS("vblank wait timed out.\n");
352 }
353
354 static void fimd_win_mode_set(struct exynos_drm_manager *mgr,
355 struct exynos_drm_overlay *overlay)
356 {
357 struct fimd_context *ctx = mgr->ctx;
358 struct fimd_win_data *win_data;
359 int win;
360 unsigned long offset;
361
362 if (!overlay) {
363 DRM_ERROR("overlay is NULL\n");
364 return;
365 }
366
367 win = overlay->zpos;
368 if (win == DEFAULT_ZPOS)
369 win = ctx->default_win;
370
371 if (win < 0 || win >= WINDOWS_NR)
372 return;
373
374 offset = overlay->fb_x * (overlay->bpp >> 3);
375 offset += overlay->fb_y * overlay->pitch;
376
377 DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, overlay->pitch);
378
379 win_data = &ctx->win_data[win];
380
381 win_data->offset_x = overlay->crtc_x;
382 win_data->offset_y = overlay->crtc_y;
383 win_data->ovl_width = overlay->crtc_width;
384 win_data->ovl_height = overlay->crtc_height;
385 win_data->fb_width = overlay->fb_width;
386 win_data->fb_height = overlay->fb_height;
387 win_data->dma_addr = overlay->dma_addr[0] + offset;
388 win_data->bpp = overlay->bpp;
389 win_data->pixel_format = overlay->pixel_format;
390 win_data->buf_offsize = (overlay->fb_width - overlay->crtc_width) *
391 (overlay->bpp >> 3);
392 win_data->line_size = overlay->crtc_width * (overlay->bpp >> 3);
393
394 DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n",
395 win_data->offset_x, win_data->offset_y);
396 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
397 win_data->ovl_width, win_data->ovl_height);
398 DRM_DEBUG_KMS("paddr = 0x%lx\n", (unsigned long)win_data->dma_addr);
399 DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n",
400 overlay->fb_width, overlay->crtc_width);
401 }
402
403 static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win)
404 {
405 struct fimd_win_data *win_data = &ctx->win_data[win];
406 unsigned long val;
407
408 val = WINCONx_ENWIN;
409
410 /*
411 * In case of s3c64xx, window 0 doesn't support alpha channel.
412 * So the request format is ARGB8888 then change it to XRGB8888.
413 */
414 if (ctx->driver_data->has_limited_fmt && !win) {
415 if (win_data->pixel_format == DRM_FORMAT_ARGB8888)
416 win_data->pixel_format = DRM_FORMAT_XRGB8888;
417 }
418
419 switch (win_data->pixel_format) {
420 case DRM_FORMAT_C8:
421 val |= WINCON0_BPPMODE_8BPP_PALETTE;
422 val |= WINCONx_BURSTLEN_8WORD;
423 val |= WINCONx_BYTSWP;
424 break;
425 case DRM_FORMAT_XRGB1555:
426 val |= WINCON0_BPPMODE_16BPP_1555;
427 val |= WINCONx_HAWSWP;
428 val |= WINCONx_BURSTLEN_16WORD;
429 break;
430 case DRM_FORMAT_RGB565:
431 val |= WINCON0_BPPMODE_16BPP_565;
432 val |= WINCONx_HAWSWP;
433 val |= WINCONx_BURSTLEN_16WORD;
434 break;
435 case DRM_FORMAT_XRGB8888:
436 val |= WINCON0_BPPMODE_24BPP_888;
437 val |= WINCONx_WSWP;
438 val |= WINCONx_BURSTLEN_16WORD;
439 break;
440 case DRM_FORMAT_ARGB8888:
441 val |= WINCON1_BPPMODE_25BPP_A1888
442 | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
443 val |= WINCONx_WSWP;
444 val |= WINCONx_BURSTLEN_16WORD;
445 break;
446 default:
447 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
448
449 val |= WINCON0_BPPMODE_24BPP_888;
450 val |= WINCONx_WSWP;
451 val |= WINCONx_BURSTLEN_16WORD;
452 break;
453 }
454
455 DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp);
456
457 writel(val, ctx->regs + WINCON(win));
458 }
459
460 static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win)
461 {
462 unsigned int keycon0 = 0, keycon1 = 0;
463
464 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
465 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
466
467 keycon1 = WxKEYCON1_COLVAL(0xffffffff);
468
469 writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
470 writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
471 }
472
473 /**
474 * shadow_protect_win() - disable updating values from shadow registers at vsync
475 *
476 * @win: window to protect registers for
477 * @protect: 1 to protect (disable updates)
478 */
479 static void fimd_shadow_protect_win(struct fimd_context *ctx,
480 int win, bool protect)
481 {
482 u32 reg, bits, val;
483
484 if (ctx->driver_data->has_shadowcon) {
485 reg = SHADOWCON;
486 bits = SHADOWCON_WINx_PROTECT(win);
487 } else {
488 reg = PRTCON;
489 bits = PRTCON_PROTECT;
490 }
491
492 val = readl(ctx->regs + reg);
493 if (protect)
494 val |= bits;
495 else
496 val &= ~bits;
497 writel(val, ctx->regs + reg);
498 }
499
500 static void fimd_win_commit(struct exynos_drm_manager *mgr, int zpos)
501 {
502 struct fimd_context *ctx = mgr->ctx;
503 struct fimd_win_data *win_data;
504 int win = zpos;
505 unsigned long val, alpha, size;
506 unsigned int last_x;
507 unsigned int last_y;
508
509 if (ctx->suspended)
510 return;
511
512 if (win == DEFAULT_ZPOS)
513 win = ctx->default_win;
514
515 if (win < 0 || win >= WINDOWS_NR)
516 return;
517
518 win_data = &ctx->win_data[win];
519
520 /* If suspended, enable this on resume */
521 if (ctx->suspended) {
522 win_data->resume = true;
523 return;
524 }
525
526 /*
527 * SHADOWCON/PRTCON register is used for enabling timing.
528 *
529 * for example, once only width value of a register is set,
530 * if the dma is started then fimd hardware could malfunction so
531 * with protect window setting, the register fields with prefix '_F'
532 * wouldn't be updated at vsync also but updated once unprotect window
533 * is set.
534 */
535
536 /* protect windows */
537 fimd_shadow_protect_win(ctx, win, true);
538
539 /* buffer start address */
540 val = (unsigned long)win_data->dma_addr;
541 writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
542
543 /* buffer end address */
544 size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3);
545 val = (unsigned long)(win_data->dma_addr + size);
546 writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
547
548 DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
549 (unsigned long)win_data->dma_addr, val, size);
550 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
551 win_data->ovl_width, win_data->ovl_height);
552
553 /* buffer size */
554 val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) |
555 VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size) |
556 VIDW_BUF_SIZE_OFFSET_E(win_data->buf_offsize) |
557 VIDW_BUF_SIZE_PAGEWIDTH_E(win_data->line_size);
558 writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
559
560 /* OSD position */
561 val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) |
562 VIDOSDxA_TOPLEFT_Y(win_data->offset_y) |
563 VIDOSDxA_TOPLEFT_X_E(win_data->offset_x) |
564 VIDOSDxA_TOPLEFT_Y_E(win_data->offset_y);
565 writel(val, ctx->regs + VIDOSD_A(win));
566
567 last_x = win_data->offset_x + win_data->ovl_width;
568 if (last_x)
569 last_x--;
570 last_y = win_data->offset_y + win_data->ovl_height;
571 if (last_y)
572 last_y--;
573
574 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
575 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);
576
577 writel(val, ctx->regs + VIDOSD_B(win));
578
579 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
580 win_data->offset_x, win_data->offset_y, last_x, last_y);
581
582 /* hardware window 0 doesn't support alpha channel. */
583 if (win != 0) {
584 /* OSD alpha */
585 alpha = VIDISD14C_ALPHA1_R(0xf) |
586 VIDISD14C_ALPHA1_G(0xf) |
587 VIDISD14C_ALPHA1_B(0xf);
588
589 writel(alpha, ctx->regs + VIDOSD_C(win));
590 }
591
592 /* OSD size */
593 if (win != 3 && win != 4) {
594 u32 offset = VIDOSD_D(win);
595 if (win == 0)
596 offset = VIDOSD_C(win);
597 val = win_data->ovl_width * win_data->ovl_height;
598 writel(val, ctx->regs + offset);
599
600 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
601 }
602
603 fimd_win_set_pixfmt(ctx, win);
604
605 /* hardware window 0 doesn't support color key. */
606 if (win != 0)
607 fimd_win_set_colkey(ctx, win);
608
609 /* wincon */
610 val = readl(ctx->regs + WINCON(win));
611 val |= WINCONx_ENWIN;
612 writel(val, ctx->regs + WINCON(win));
613
614 /* Enable DMA channel and unprotect windows */
615 fimd_shadow_protect_win(ctx, win, false);
616
617 if (ctx->driver_data->has_shadowcon) {
618 val = readl(ctx->regs + SHADOWCON);
619 val |= SHADOWCON_CHx_ENABLE(win);
620 writel(val, ctx->regs + SHADOWCON);
621 }
622
623 win_data->enabled = true;
624 }
625
626 static void fimd_win_disable(struct exynos_drm_manager *mgr, int zpos)
627 {
628 struct fimd_context *ctx = mgr->ctx;
629 struct fimd_win_data *win_data;
630 int win = zpos;
631 u32 val;
632
633 if (win == DEFAULT_ZPOS)
634 win = ctx->default_win;
635
636 if (win < 0 || win >= WINDOWS_NR)
637 return;
638
639 win_data = &ctx->win_data[win];
640
641 if (ctx->suspended) {
642 /* do not resume this window*/
643 win_data->resume = false;
644 return;
645 }
646
647 /* protect windows */
648 fimd_shadow_protect_win(ctx, win, true);
649
650 /* wincon */
651 val = readl(ctx->regs + WINCON(win));
652 val &= ~WINCONx_ENWIN;
653 writel(val, ctx->regs + WINCON(win));
654
655 /* unprotect windows */
656 if (ctx->driver_data->has_shadowcon) {
657 val = readl(ctx->regs + SHADOWCON);
658 val &= ~SHADOWCON_CHx_ENABLE(win);
659 writel(val, ctx->regs + SHADOWCON);
660 }
661
662 fimd_shadow_protect_win(ctx, win, false);
663
664 win_data->enabled = false;
665 }
666
667 static void fimd_clear_win(struct fimd_context *ctx, int win)
668 {
669 writel(0, ctx->regs + WINCON(win));
670 writel(0, ctx->regs + VIDOSD_A(win));
671 writel(0, ctx->regs + VIDOSD_B(win));
672 writel(0, ctx->regs + VIDOSD_C(win));
673
674 if (win == 1 || win == 2)
675 writel(0, ctx->regs + VIDOSD_D(win));
676
677 fimd_shadow_protect_win(ctx, win, false);
678 }
679
680 static void fimd_window_suspend(struct exynos_drm_manager *mgr)
681 {
682 struct fimd_context *ctx = mgr->ctx;
683 struct fimd_win_data *win_data;
684 int i;
685
686 for (i = 0; i < WINDOWS_NR; i++) {
687 win_data = &ctx->win_data[i];
688 win_data->resume = win_data->enabled;
689 if (win_data->enabled)
690 fimd_win_disable(mgr, i);
691 }
692 fimd_wait_for_vblank(mgr);
693 }
694
695 static void fimd_window_resume(struct exynos_drm_manager *mgr)
696 {
697 struct fimd_context *ctx = mgr->ctx;
698 struct fimd_win_data *win_data;
699 int i;
700
701 for (i = 0; i < WINDOWS_NR; i++) {
702 win_data = &ctx->win_data[i];
703 win_data->enabled = win_data->resume;
704 win_data->resume = false;
705 }
706 }
707
708 static void fimd_apply(struct exynos_drm_manager *mgr)
709 {
710 struct fimd_context *ctx = mgr->ctx;
711 struct fimd_win_data *win_data;
712 int i;
713
714 for (i = 0; i < WINDOWS_NR; i++) {
715 win_data = &ctx->win_data[i];
716 if (win_data->enabled)
717 fimd_win_commit(mgr, i);
718 }
719
720 fimd_commit(mgr);
721 }
722
723 static int fimd_poweron(struct exynos_drm_manager *mgr)
724 {
725 struct fimd_context *ctx = mgr->ctx;
726 int ret;
727
728 if (!ctx->suspended)
729 return 0;
730
731 ctx->suspended = false;
732
733 pm_runtime_get_sync(ctx->dev);
734
735 ret = clk_prepare_enable(ctx->bus_clk);
736 if (ret < 0) {
737 DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret);
738 goto bus_clk_err;
739 }
740
741 ret = clk_prepare_enable(ctx->lcd_clk);
742 if (ret < 0) {
743 DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret);
744 goto lcd_clk_err;
745 }
746
747 /* if vblank was enabled status, enable it again. */
748 if (test_and_clear_bit(0, &ctx->irq_flags)) {
749 ret = fimd_enable_vblank(mgr);
750 if (ret) {
751 DRM_ERROR("Failed to re-enable vblank [%d]\n", ret);
752 goto enable_vblank_err;
753 }
754 }
755
756 fimd_window_resume(mgr);
757
758 fimd_apply(mgr);
759
760 return 0;
761
762 enable_vblank_err:
763 clk_disable_unprepare(ctx->lcd_clk);
764 lcd_clk_err:
765 clk_disable_unprepare(ctx->bus_clk);
766 bus_clk_err:
767 ctx->suspended = true;
768 return ret;
769 }
770
771 static int fimd_poweroff(struct exynos_drm_manager *mgr)
772 {
773 struct fimd_context *ctx = mgr->ctx;
774
775 if (ctx->suspended)
776 return 0;
777
778 /*
779 * We need to make sure that all windows are disabled before we
780 * suspend that connector. Otherwise we might try to scan from
781 * a destroyed buffer later.
782 */
783 fimd_window_suspend(mgr);
784
785 clk_disable_unprepare(ctx->lcd_clk);
786 clk_disable_unprepare(ctx->bus_clk);
787
788 pm_runtime_put_sync(ctx->dev);
789
790 ctx->suspended = true;
791 return 0;
792 }
793
794 static void fimd_dpms(struct exynos_drm_manager *mgr, int mode)
795 {
796 DRM_DEBUG_KMS("%s, %d\n", __FILE__, mode);
797
798 switch (mode) {
799 case DRM_MODE_DPMS_ON:
800 fimd_poweron(mgr);
801 break;
802 case DRM_MODE_DPMS_STANDBY:
803 case DRM_MODE_DPMS_SUSPEND:
804 case DRM_MODE_DPMS_OFF:
805 fimd_poweroff(mgr);
806 break;
807 default:
808 DRM_DEBUG_KMS("unspecified mode %d\n", mode);
809 break;
810 }
811 }
812
813 static struct exynos_drm_manager_ops fimd_manager_ops = {
814 .initialize = fimd_mgr_initialize,
815 .remove = fimd_mgr_remove,
816 .dpms = fimd_dpms,
817 .mode_fixup = fimd_mode_fixup,
818 .mode_set = fimd_mode_set,
819 .commit = fimd_commit,
820 .enable_vblank = fimd_enable_vblank,
821 .disable_vblank = fimd_disable_vblank,
822 .wait_for_vblank = fimd_wait_for_vblank,
823 .win_mode_set = fimd_win_mode_set,
824 .win_commit = fimd_win_commit,
825 .win_disable = fimd_win_disable,
826 };
827
828 static struct exynos_drm_manager fimd_manager = {
829 .type = EXYNOS_DISPLAY_TYPE_LCD,
830 .ops = &fimd_manager_ops,
831 };
832
833 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
834 {
835 struct fimd_context *ctx = (struct fimd_context *)dev_id;
836 u32 val;
837
838 val = readl(ctx->regs + VIDINTCON1);
839
840 if (val & VIDINTCON1_INT_FRAME)
841 /* VSYNC interrupt */
842 writel(VIDINTCON1_INT_FRAME, ctx->regs + VIDINTCON1);
843
844 /* check the crtc is detached already from encoder */
845 if (ctx->pipe < 0 || !ctx->drm_dev)
846 goto out;
847
848 drm_handle_vblank(ctx->drm_dev, ctx->pipe);
849 exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
850
851 /* set wait vsync event to zero and wake up queue. */
852 if (atomic_read(&ctx->wait_vsync_event)) {
853 atomic_set(&ctx->wait_vsync_event, 0);
854 wake_up(&ctx->wait_vsync_queue);
855 }
856 out:
857 return IRQ_HANDLED;
858 }
859
860 static int fimd_probe(struct platform_device *pdev)
861 {
862 struct device *dev = &pdev->dev;
863 struct fimd_context *ctx;
864 struct resource *res;
865 int win;
866 int ret = -EINVAL;
867
868 if (!dev->of_node)
869 return -ENODEV;
870
871 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
872 if (!ctx)
873 return -ENOMEM;
874
875 ctx->dev = dev;
876 ctx->suspended = true;
877
878 if (of_property_read_bool(dev->of_node, "samsung,invert-vden"))
879 ctx->vidcon1 |= VIDCON1_INV_VDEN;
880 if (of_property_read_bool(dev->of_node, "samsung,invert-vclk"))
881 ctx->vidcon1 |= VIDCON1_INV_VCLK;
882
883 ctx->bus_clk = devm_clk_get(dev, "fimd");
884 if (IS_ERR(ctx->bus_clk)) {
885 dev_err(dev, "failed to get bus clock\n");
886 return PTR_ERR(ctx->bus_clk);
887 }
888
889 ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
890 if (IS_ERR(ctx->lcd_clk)) {
891 dev_err(dev, "failed to get lcd clock\n");
892 return PTR_ERR(ctx->lcd_clk);
893 }
894
895 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
896
897 ctx->regs = devm_ioremap_resource(dev, res);
898 if (IS_ERR(ctx->regs))
899 return PTR_ERR(ctx->regs);
900
901 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "vsync");
902 if (!res) {
903 dev_err(dev, "irq request failed.\n");
904 return -ENXIO;
905 }
906
907 ret = devm_request_irq(dev, res->start, fimd_irq_handler,
908 0, "drm_fimd", ctx);
909 if (ret) {
910 dev_err(dev, "irq request failed.\n");
911 return ret;
912 }
913
914 ctx->driver_data = drm_fimd_get_driver_data(pdev);
915 init_waitqueue_head(&ctx->wait_vsync_queue);
916 atomic_set(&ctx->wait_vsync_event, 0);
917
918 platform_set_drvdata(pdev, &fimd_manager);
919
920 fimd_manager.ctx = ctx;
921 exynos_drm_manager_register(&fimd_manager);
922
923 exynos_dpi_probe(ctx->dev);
924
925 pm_runtime_enable(dev);
926
927 for (win = 0; win < WINDOWS_NR; win++)
928 fimd_clear_win(ctx, win);
929
930 return 0;
931 }
932
933 static int fimd_remove(struct platform_device *pdev)
934 {
935 struct exynos_drm_manager *mgr = platform_get_drvdata(pdev);
936
937 exynos_dpi_remove(&pdev->dev);
938
939 exynos_drm_manager_unregister(&fimd_manager);
940
941 fimd_dpms(mgr, DRM_MODE_DPMS_OFF);
942
943 pm_runtime_disable(&pdev->dev);
944
945 return 0;
946 }
947
948 struct platform_driver fimd_driver = {
949 .probe = fimd_probe,
950 .remove = fimd_remove,
951 .driver = {
952 .name = "exynos4-fb",
953 .owner = THIS_MODULE,
954 .of_match_table = fimd_driver_dt_match,
955 },
956 };
Linux kernel - Deliverables
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