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[deliverable/linux.git] / drivers / gpu / drm / exynos / exynos_drm_fimd.c
1 /* exynos_drm_fimd.c
2 *
3 * Copyright (C) 2011 Samsung Electronics Co.Ltd
4 * Authors:
5 * Joonyoung Shim <jy0922.shim@samsung.com>
6 * Inki Dae <inki.dae@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14 #include <drm/drmP.h>
15
16 #include <linux/kernel.h>
17 #include <linux/platform_device.h>
18 #include <linux/clk.h>
19 #include <linux/of.h>
20 #include <linux/of_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/component.h>
23 #include <linux/mfd/syscon.h>
24 #include <linux/regmap.h>
25
26 #include <video/of_display_timing.h>
27 #include <video/of_videomode.h>
28 #include <video/samsung_fimd.h>
29 #include <drm/exynos_drm.h>
30
31 #include "exynos_drm_drv.h"
32 #include "exynos_drm_fbdev.h"
33 #include "exynos_drm_crtc.h"
34 #include "exynos_drm_plane.h"
35 #include "exynos_drm_iommu.h"
36
37 /*
38 * FIMD stands for Fully Interactive Mobile Display and
39 * as a display controller, it transfers contents drawn on memory
40 * to a LCD Panel through Display Interfaces such as RGB or
41 * CPU Interface.
42 */
43
44 #define FIMD_DEFAULT_FRAMERATE 60
45 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
46
47 /* position control register for hardware window 0, 2 ~ 4.*/
48 #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
49 #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
50 /*
51 * size control register for hardware windows 0 and alpha control register
52 * for hardware windows 1 ~ 4
53 */
54 #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16)
55 /* size control register for hardware windows 1 ~ 2. */
56 #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
57
58 #define VIDWnALPHA0(win) (VIDW_ALPHA + 0x00 + (win) * 8)
59 #define VIDWnALPHA1(win) (VIDW_ALPHA + 0x04 + (win) * 8)
60
61 #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
62 #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8)
63 #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
64
65 /* color key control register for hardware window 1 ~ 4. */
66 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8))
67 /* color key value register for hardware window 1 ~ 4. */
68 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
69
70 /* I80 / RGB trigger control register */
71 #define TRIGCON 0x1A4
72 #define TRGMODE_I80_RGB_ENABLE_I80 (1 << 0)
73 #define SWTRGCMD_I80_RGB_ENABLE (1 << 1)
74
75 /* display mode change control register except exynos4 */
76 #define VIDOUT_CON 0x000
77 #define VIDOUT_CON_F_I80_LDI0 (0x2 << 8)
78
79 /* I80 interface control for main LDI register */
80 #define I80IFCONFAx(x) (0x1B0 + (x) * 4)
81 #define I80IFCONFBx(x) (0x1B8 + (x) * 4)
82 #define LCD_CS_SETUP(x) ((x) << 16)
83 #define LCD_WR_SETUP(x) ((x) << 12)
84 #define LCD_WR_ACTIVE(x) ((x) << 8)
85 #define LCD_WR_HOLD(x) ((x) << 4)
86 #define I80IFEN_ENABLE (1 << 0)
87
88 /* FIMD has totally five hardware windows. */
89 #define WINDOWS_NR 5
90
91 struct fimd_driver_data {
92 unsigned int timing_base;
93 unsigned int lcdblk_offset;
94 unsigned int lcdblk_vt_shift;
95 unsigned int lcdblk_bypass_shift;
96
97 unsigned int has_shadowcon:1;
98 unsigned int has_clksel:1;
99 unsigned int has_limited_fmt:1;
100 unsigned int has_vidoutcon:1;
101 unsigned int has_vtsel:1;
102 };
103
104 static struct fimd_driver_data s3c64xx_fimd_driver_data = {
105 .timing_base = 0x0,
106 .has_clksel = 1,
107 .has_limited_fmt = 1,
108 };
109
110 static struct fimd_driver_data exynos3_fimd_driver_data = {
111 .timing_base = 0x20000,
112 .lcdblk_offset = 0x210,
113 .lcdblk_bypass_shift = 1,
114 .has_shadowcon = 1,
115 .has_vidoutcon = 1,
116 };
117
118 static struct fimd_driver_data exynos4_fimd_driver_data = {
119 .timing_base = 0x0,
120 .lcdblk_offset = 0x210,
121 .lcdblk_vt_shift = 10,
122 .lcdblk_bypass_shift = 1,
123 .has_shadowcon = 1,
124 .has_vtsel = 1,
125 };
126
127 static struct fimd_driver_data exynos4415_fimd_driver_data = {
128 .timing_base = 0x20000,
129 .lcdblk_offset = 0x210,
130 .lcdblk_vt_shift = 10,
131 .lcdblk_bypass_shift = 1,
132 .has_shadowcon = 1,
133 .has_vidoutcon = 1,
134 .has_vtsel = 1,
135 };
136
137 static struct fimd_driver_data exynos5_fimd_driver_data = {
138 .timing_base = 0x20000,
139 .lcdblk_offset = 0x214,
140 .lcdblk_vt_shift = 24,
141 .lcdblk_bypass_shift = 15,
142 .has_shadowcon = 1,
143 .has_vidoutcon = 1,
144 .has_vtsel = 1,
145 };
146
147 struct fimd_context {
148 struct device *dev;
149 struct drm_device *drm_dev;
150 struct exynos_drm_crtc *crtc;
151 struct exynos_drm_plane planes[WINDOWS_NR];
152 struct clk *bus_clk;
153 struct clk *lcd_clk;
154 void __iomem *regs;
155 struct regmap *sysreg;
156 unsigned int default_win;
157 unsigned long irq_flags;
158 u32 vidcon0;
159 u32 vidcon1;
160 u32 vidout_con;
161 u32 i80ifcon;
162 bool i80_if;
163 bool suspended;
164 int pipe;
165 wait_queue_head_t wait_vsync_queue;
166 atomic_t wait_vsync_event;
167 atomic_t win_updated;
168 atomic_t triggering;
169
170 struct exynos_drm_panel_info panel;
171 struct fimd_driver_data *driver_data;
172 struct exynos_drm_display *display;
173 };
174
175 static const struct of_device_id fimd_driver_dt_match[] = {
176 { .compatible = "samsung,s3c6400-fimd",
177 .data = &s3c64xx_fimd_driver_data },
178 { .compatible = "samsung,exynos3250-fimd",
179 .data = &exynos3_fimd_driver_data },
180 { .compatible = "samsung,exynos4210-fimd",
181 .data = &exynos4_fimd_driver_data },
182 { .compatible = "samsung,exynos4415-fimd",
183 .data = &exynos4415_fimd_driver_data },
184 { .compatible = "samsung,exynos5250-fimd",
185 .data = &exynos5_fimd_driver_data },
186 {},
187 };
188 MODULE_DEVICE_TABLE(of, fimd_driver_dt_match);
189
190 static inline struct fimd_driver_data *drm_fimd_get_driver_data(
191 struct platform_device *pdev)
192 {
193 const struct of_device_id *of_id =
194 of_match_device(fimd_driver_dt_match, &pdev->dev);
195
196 return (struct fimd_driver_data *)of_id->data;
197 }
198
199 static int fimd_enable_vblank(struct exynos_drm_crtc *crtc)
200 {
201 struct fimd_context *ctx = crtc->ctx;
202 u32 val;
203
204 if (ctx->suspended)
205 return -EPERM;
206
207 if (!test_and_set_bit(0, &ctx->irq_flags)) {
208 val = readl(ctx->regs + VIDINTCON0);
209
210 val |= VIDINTCON0_INT_ENABLE;
211
212 if (ctx->i80_if) {
213 val |= VIDINTCON0_INT_I80IFDONE;
214 val |= VIDINTCON0_INT_SYSMAINCON;
215 val &= ~VIDINTCON0_INT_SYSSUBCON;
216 } else {
217 val |= VIDINTCON0_INT_FRAME;
218
219 val &= ~VIDINTCON0_FRAMESEL0_MASK;
220 val |= VIDINTCON0_FRAMESEL0_VSYNC;
221 val &= ~VIDINTCON0_FRAMESEL1_MASK;
222 val |= VIDINTCON0_FRAMESEL1_NONE;
223 }
224
225 writel(val, ctx->regs + VIDINTCON0);
226 }
227
228 return 0;
229 }
230
231 static void fimd_disable_vblank(struct exynos_drm_crtc *crtc)
232 {
233 struct fimd_context *ctx = crtc->ctx;
234 u32 val;
235
236 if (ctx->suspended)
237 return;
238
239 if (test_and_clear_bit(0, &ctx->irq_flags)) {
240 val = readl(ctx->regs + VIDINTCON0);
241
242 val &= ~VIDINTCON0_INT_ENABLE;
243
244 if (ctx->i80_if) {
245 val &= ~VIDINTCON0_INT_I80IFDONE;
246 val &= ~VIDINTCON0_INT_SYSMAINCON;
247 val &= ~VIDINTCON0_INT_SYSSUBCON;
248 } else
249 val &= ~VIDINTCON0_INT_FRAME;
250
251 writel(val, ctx->regs + VIDINTCON0);
252 }
253 }
254
255 static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc)
256 {
257 struct fimd_context *ctx = crtc->ctx;
258
259 if (ctx->suspended)
260 return;
261
262 atomic_set(&ctx->wait_vsync_event, 1);
263
264 /*
265 * wait for FIMD to signal VSYNC interrupt or return after
266 * timeout which is set to 50ms (refresh rate of 20).
267 */
268 if (!wait_event_timeout(ctx->wait_vsync_queue,
269 !atomic_read(&ctx->wait_vsync_event),
270 HZ/20))
271 DRM_DEBUG_KMS("vblank wait timed out.\n");
272 }
273
274 static void fimd_enable_video_output(struct fimd_context *ctx, unsigned int win,
275 bool enable)
276 {
277 u32 val = readl(ctx->regs + WINCON(win));
278
279 if (enable)
280 val |= WINCONx_ENWIN;
281 else
282 val &= ~WINCONx_ENWIN;
283
284 writel(val, ctx->regs + WINCON(win));
285 }
286
287 static void fimd_enable_shadow_channel_path(struct fimd_context *ctx,
288 unsigned int win,
289 bool enable)
290 {
291 u32 val = readl(ctx->regs + SHADOWCON);
292
293 if (enable)
294 val |= SHADOWCON_CHx_ENABLE(win);
295 else
296 val &= ~SHADOWCON_CHx_ENABLE(win);
297
298 writel(val, ctx->regs + SHADOWCON);
299 }
300
301 static void fimd_clear_channel(struct fimd_context *ctx)
302 {
303 unsigned int win, ch_enabled = 0;
304
305 DRM_DEBUG_KMS("%s\n", __FILE__);
306
307 /* Hardware is in unknown state, so ensure it gets enabled properly */
308 pm_runtime_get_sync(ctx->dev);
309
310 clk_prepare_enable(ctx->bus_clk);
311 clk_prepare_enable(ctx->lcd_clk);
312
313 /* Check if any channel is enabled. */
314 for (win = 0; win < WINDOWS_NR; win++) {
315 u32 val = readl(ctx->regs + WINCON(win));
316
317 if (val & WINCONx_ENWIN) {
318 fimd_enable_video_output(ctx, win, false);
319
320 if (ctx->driver_data->has_shadowcon)
321 fimd_enable_shadow_channel_path(ctx, win,
322 false);
323
324 ch_enabled = 1;
325 }
326 }
327
328 /* Wait for vsync, as disable channel takes effect at next vsync */
329 if (ch_enabled) {
330 int pipe = ctx->pipe;
331
332 /* ensure that vblank interrupt won't be reported to core */
333 ctx->suspended = false;
334 ctx->pipe = -1;
335
336 fimd_enable_vblank(ctx->crtc);
337 fimd_wait_for_vblank(ctx->crtc);
338 fimd_disable_vblank(ctx->crtc);
339
340 ctx->suspended = true;
341 ctx->pipe = pipe;
342 }
343
344 clk_disable_unprepare(ctx->lcd_clk);
345 clk_disable_unprepare(ctx->bus_clk);
346
347 pm_runtime_put(ctx->dev);
348 }
349
350 static int fimd_iommu_attach_devices(struct fimd_context *ctx,
351 struct drm_device *drm_dev)
352 {
353
354 /* attach this sub driver to iommu mapping if supported. */
355 if (is_drm_iommu_supported(ctx->drm_dev)) {
356 int ret;
357
358 /*
359 * If any channel is already active, iommu will throw
360 * a PAGE FAULT when enabled. So clear any channel if enabled.
361 */
362 fimd_clear_channel(ctx);
363 ret = drm_iommu_attach_device(ctx->drm_dev, ctx->dev);
364 if (ret) {
365 DRM_ERROR("drm_iommu_attach failed.\n");
366 return ret;
367 }
368
369 }
370
371 return 0;
372 }
373
374 static void fimd_iommu_detach_devices(struct fimd_context *ctx)
375 {
376 /* detach this sub driver from iommu mapping if supported. */
377 if (is_drm_iommu_supported(ctx->drm_dev))
378 drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
379 }
380
381 static u32 fimd_calc_clkdiv(struct fimd_context *ctx,
382 const struct drm_display_mode *mode)
383 {
384 unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
385 u32 clkdiv;
386
387 if (ctx->i80_if) {
388 /*
389 * The frame done interrupt should be occurred prior to the
390 * next TE signal.
391 */
392 ideal_clk *= 2;
393 }
394
395 /* Find the clock divider value that gets us closest to ideal_clk */
396 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->lcd_clk), ideal_clk);
397
398 return (clkdiv < 0x100) ? clkdiv : 0xff;
399 }
400
401 static bool fimd_mode_fixup(struct exynos_drm_crtc *crtc,
402 const struct drm_display_mode *mode,
403 struct drm_display_mode *adjusted_mode)
404 {
405 if (adjusted_mode->vrefresh == 0)
406 adjusted_mode->vrefresh = FIMD_DEFAULT_FRAMERATE;
407
408 return true;
409 }
410
411 static void fimd_commit(struct exynos_drm_crtc *crtc)
412 {
413 struct fimd_context *ctx = crtc->ctx;
414 struct drm_display_mode *mode = &crtc->base.state->adjusted_mode;
415 struct fimd_driver_data *driver_data = ctx->driver_data;
416 void *timing_base = ctx->regs + driver_data->timing_base;
417 u32 val, clkdiv;
418
419 if (ctx->suspended)
420 return;
421
422 /* nothing to do if we haven't set the mode yet */
423 if (mode->htotal == 0 || mode->vtotal == 0)
424 return;
425
426 if (ctx->i80_if) {
427 val = ctx->i80ifcon | I80IFEN_ENABLE;
428 writel(val, timing_base + I80IFCONFAx(0));
429
430 /* disable auto frame rate */
431 writel(0, timing_base + I80IFCONFBx(0));
432
433 /* set video type selection to I80 interface */
434 if (driver_data->has_vtsel && ctx->sysreg &&
435 regmap_update_bits(ctx->sysreg,
436 driver_data->lcdblk_offset,
437 0x3 << driver_data->lcdblk_vt_shift,
438 0x1 << driver_data->lcdblk_vt_shift)) {
439 DRM_ERROR("Failed to update sysreg for I80 i/f.\n");
440 return;
441 }
442 } else {
443 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
444 u32 vidcon1;
445
446 /* setup polarity values */
447 vidcon1 = ctx->vidcon1;
448 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
449 vidcon1 |= VIDCON1_INV_VSYNC;
450 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
451 vidcon1 |= VIDCON1_INV_HSYNC;
452 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
453
454 /* setup vertical timing values. */
455 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
456 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
457 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
458
459 val = VIDTCON0_VBPD(vbpd - 1) |
460 VIDTCON0_VFPD(vfpd - 1) |
461 VIDTCON0_VSPW(vsync_len - 1);
462 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
463
464 /* setup horizontal timing values. */
465 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
466 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
467 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
468
469 val = VIDTCON1_HBPD(hbpd - 1) |
470 VIDTCON1_HFPD(hfpd - 1) |
471 VIDTCON1_HSPW(hsync_len - 1);
472 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
473 }
474
475 if (driver_data->has_vidoutcon)
476 writel(ctx->vidout_con, timing_base + VIDOUT_CON);
477
478 /* set bypass selection */
479 if (ctx->sysreg && regmap_update_bits(ctx->sysreg,
480 driver_data->lcdblk_offset,
481 0x1 << driver_data->lcdblk_bypass_shift,
482 0x1 << driver_data->lcdblk_bypass_shift)) {
483 DRM_ERROR("Failed to update sysreg for bypass setting.\n");
484 return;
485 }
486
487 /* setup horizontal and vertical display size. */
488 val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
489 VIDTCON2_HOZVAL(mode->hdisplay - 1) |
490 VIDTCON2_LINEVAL_E(mode->vdisplay - 1) |
491 VIDTCON2_HOZVAL_E(mode->hdisplay - 1);
492 writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
493
494 /*
495 * fields of register with prefix '_F' would be updated
496 * at vsync(same as dma start)
497 */
498 val = ctx->vidcon0;
499 val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
500
501 if (ctx->driver_data->has_clksel)
502 val |= VIDCON0_CLKSEL_LCD;
503
504 clkdiv = fimd_calc_clkdiv(ctx, mode);
505 if (clkdiv > 1)
506 val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR;
507
508 writel(val, ctx->regs + VIDCON0);
509 }
510
511
512 static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win)
513 {
514 struct exynos_drm_plane *plane = &ctx->planes[win];
515 unsigned long val;
516
517 val = WINCONx_ENWIN;
518
519 /*
520 * In case of s3c64xx, window 0 doesn't support alpha channel.
521 * So the request format is ARGB8888 then change it to XRGB8888.
522 */
523 if (ctx->driver_data->has_limited_fmt && !win) {
524 if (plane->pixel_format == DRM_FORMAT_ARGB8888)
525 plane->pixel_format = DRM_FORMAT_XRGB8888;
526 }
527
528 switch (plane->pixel_format) {
529 case DRM_FORMAT_C8:
530 val |= WINCON0_BPPMODE_8BPP_PALETTE;
531 val |= WINCONx_BURSTLEN_8WORD;
532 val |= WINCONx_BYTSWP;
533 break;
534 case DRM_FORMAT_XRGB1555:
535 val |= WINCON0_BPPMODE_16BPP_1555;
536 val |= WINCONx_HAWSWP;
537 val |= WINCONx_BURSTLEN_16WORD;
538 break;
539 case DRM_FORMAT_RGB565:
540 val |= WINCON0_BPPMODE_16BPP_565;
541 val |= WINCONx_HAWSWP;
542 val |= WINCONx_BURSTLEN_16WORD;
543 break;
544 case DRM_FORMAT_XRGB8888:
545 val |= WINCON0_BPPMODE_24BPP_888;
546 val |= WINCONx_WSWP;
547 val |= WINCONx_BURSTLEN_16WORD;
548 break;
549 case DRM_FORMAT_ARGB8888:
550 val |= WINCON1_BPPMODE_25BPP_A1888
551 | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
552 val |= WINCONx_WSWP;
553 val |= WINCONx_BURSTLEN_16WORD;
554 break;
555 default:
556 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
557
558 val |= WINCON0_BPPMODE_24BPP_888;
559 val |= WINCONx_WSWP;
560 val |= WINCONx_BURSTLEN_16WORD;
561 break;
562 }
563
564 DRM_DEBUG_KMS("bpp = %d\n", plane->bpp);
565
566 /*
567 * In case of exynos, setting dma-burst to 16Word causes permanent
568 * tearing for very small buffers, e.g. cursor buffer. Burst Mode
569 * switching which is based on plane size is not recommended as
570 * plane size varies alot towards the end of the screen and rapid
571 * movement causes unstable DMA which results into iommu crash/tear.
572 */
573
574 if (plane->fb_width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
575 val &= ~WINCONx_BURSTLEN_MASK;
576 val |= WINCONx_BURSTLEN_4WORD;
577 }
578
579 writel(val, ctx->regs + WINCON(win));
580
581 /* hardware window 0 doesn't support alpha channel. */
582 if (win != 0) {
583 /* OSD alpha */
584 val = VIDISD14C_ALPHA0_R(0xf) |
585 VIDISD14C_ALPHA0_G(0xf) |
586 VIDISD14C_ALPHA0_B(0xf) |
587 VIDISD14C_ALPHA1_R(0xf) |
588 VIDISD14C_ALPHA1_G(0xf) |
589 VIDISD14C_ALPHA1_B(0xf);
590
591 writel(val, ctx->regs + VIDOSD_C(win));
592
593 val = VIDW_ALPHA_R(0xf) | VIDW_ALPHA_G(0xf) |
594 VIDW_ALPHA_G(0xf);
595 writel(val, ctx->regs + VIDWnALPHA0(win));
596 writel(val, ctx->regs + VIDWnALPHA1(win));
597 }
598 }
599
600 static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win)
601 {
602 unsigned int keycon0 = 0, keycon1 = 0;
603
604 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
605 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
606
607 keycon1 = WxKEYCON1_COLVAL(0xffffffff);
608
609 writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
610 writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
611 }
612
613 /**
614 * shadow_protect_win() - disable updating values from shadow registers at vsync
615 *
616 * @win: window to protect registers for
617 * @protect: 1 to protect (disable updates)
618 */
619 static void fimd_shadow_protect_win(struct fimd_context *ctx,
620 unsigned int win, bool protect)
621 {
622 u32 reg, bits, val;
623
624 if (ctx->driver_data->has_shadowcon) {
625 reg = SHADOWCON;
626 bits = SHADOWCON_WINx_PROTECT(win);
627 } else {
628 reg = PRTCON;
629 bits = PRTCON_PROTECT;
630 }
631
632 val = readl(ctx->regs + reg);
633 if (protect)
634 val |= bits;
635 else
636 val &= ~bits;
637 writel(val, ctx->regs + reg);
638 }
639
640 static void fimd_win_commit(struct exynos_drm_crtc *crtc, unsigned int win)
641 {
642 struct fimd_context *ctx = crtc->ctx;
643 struct exynos_drm_plane *plane;
644 dma_addr_t dma_addr;
645 unsigned long val, size, offset;
646 unsigned int last_x, last_y, buf_offsize, line_size;
647
648 if (ctx->suspended)
649 return;
650
651 if (win < 0 || win >= WINDOWS_NR)
652 return;
653
654 plane = &ctx->planes[win];
655
656 if (ctx->suspended)
657 return;
658
659 /*
660 * SHADOWCON/PRTCON register is used for enabling timing.
661 *
662 * for example, once only width value of a register is set,
663 * if the dma is started then fimd hardware could malfunction so
664 * with protect window setting, the register fields with prefix '_F'
665 * wouldn't be updated at vsync also but updated once unprotect window
666 * is set.
667 */
668
669 /* protect windows */
670 fimd_shadow_protect_win(ctx, win, true);
671
672
673 offset = plane->src_x * (plane->bpp >> 3);
674 offset += plane->src_y * plane->pitch;
675
676 /* buffer start address */
677 dma_addr = plane->dma_addr[0] + offset;
678 val = (unsigned long)dma_addr;
679 writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
680
681 /* buffer end address */
682 size = plane->pitch * plane->crtc_height;
683 val = (unsigned long)(dma_addr + size);
684 writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
685
686 DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
687 (unsigned long)dma_addr, val, size);
688 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
689 plane->crtc_width, plane->crtc_height);
690
691 /* buffer size */
692 buf_offsize = plane->pitch - (plane->crtc_width * (plane->bpp >> 3));
693 line_size = plane->crtc_width * (plane->bpp >> 3);
694 val = VIDW_BUF_SIZE_OFFSET(buf_offsize) |
695 VIDW_BUF_SIZE_PAGEWIDTH(line_size) |
696 VIDW_BUF_SIZE_OFFSET_E(buf_offsize) |
697 VIDW_BUF_SIZE_PAGEWIDTH_E(line_size);
698 writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
699
700 /* OSD position */
701 val = VIDOSDxA_TOPLEFT_X(plane->crtc_x) |
702 VIDOSDxA_TOPLEFT_Y(plane->crtc_y) |
703 VIDOSDxA_TOPLEFT_X_E(plane->crtc_x) |
704 VIDOSDxA_TOPLEFT_Y_E(plane->crtc_y);
705 writel(val, ctx->regs + VIDOSD_A(win));
706
707 last_x = plane->crtc_x + plane->crtc_width;
708 if (last_x)
709 last_x--;
710 last_y = plane->crtc_y + plane->crtc_height;
711 if (last_y)
712 last_y--;
713
714 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
715 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);
716
717 writel(val, ctx->regs + VIDOSD_B(win));
718
719 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
720 plane->crtc_x, plane->crtc_y, last_x, last_y);
721
722 /* OSD size */
723 if (win != 3 && win != 4) {
724 u32 offset = VIDOSD_D(win);
725 if (win == 0)
726 offset = VIDOSD_C(win);
727 val = plane->crtc_width * plane->crtc_height;
728 writel(val, ctx->regs + offset);
729
730 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
731 }
732
733 fimd_win_set_pixfmt(ctx, win);
734
735 /* hardware window 0 doesn't support color key. */
736 if (win != 0)
737 fimd_win_set_colkey(ctx, win);
738
739 fimd_enable_video_output(ctx, win, true);
740
741 if (ctx->driver_data->has_shadowcon)
742 fimd_enable_shadow_channel_path(ctx, win, true);
743
744 /* Enable DMA channel and unprotect windows */
745 fimd_shadow_protect_win(ctx, win, false);
746
747 if (ctx->i80_if)
748 atomic_set(&ctx->win_updated, 1);
749 }
750
751 static void fimd_win_disable(struct exynos_drm_crtc *crtc, unsigned int win)
752 {
753 struct fimd_context *ctx = crtc->ctx;
754 struct exynos_drm_plane *plane;
755
756 if (win < 0 || win >= WINDOWS_NR)
757 return;
758
759 plane = &ctx->planes[win];
760
761 if (ctx->suspended)
762 return;
763
764 /* protect windows */
765 fimd_shadow_protect_win(ctx, win, true);
766
767 fimd_enable_video_output(ctx, win, false);
768
769 if (ctx->driver_data->has_shadowcon)
770 fimd_enable_shadow_channel_path(ctx, win, false);
771
772 /* unprotect windows */
773 fimd_shadow_protect_win(ctx, win, false);
774 }
775
776 static void fimd_enable(struct exynos_drm_crtc *crtc)
777 {
778 struct fimd_context *ctx = crtc->ctx;
779 int ret;
780
781 if (!ctx->suspended)
782 return;
783
784 ctx->suspended = false;
785
786 pm_runtime_get_sync(ctx->dev);
787
788 ret = clk_prepare_enable(ctx->bus_clk);
789 if (ret < 0) {
790 DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret);
791 return;
792 }
793
794 ret = clk_prepare_enable(ctx->lcd_clk);
795 if (ret < 0) {
796 DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret);
797 return;
798 }
799
800 /* if vblank was enabled status, enable it again. */
801 if (test_and_clear_bit(0, &ctx->irq_flags))
802 fimd_enable_vblank(ctx->crtc);
803
804 fimd_commit(ctx->crtc);
805 }
806
807 static void fimd_disable(struct exynos_drm_crtc *crtc)
808 {
809 struct fimd_context *ctx = crtc->ctx;
810 int i;
811
812 if (ctx->suspended)
813 return;
814
815 /*
816 * We need to make sure that all windows are disabled before we
817 * suspend that connector. Otherwise we might try to scan from
818 * a destroyed buffer later.
819 */
820 for (i = 0; i < WINDOWS_NR; i++)
821 fimd_win_disable(crtc, i);
822
823 fimd_enable_vblank(crtc);
824 fimd_wait_for_vblank(crtc);
825 fimd_disable_vblank(crtc);
826
827 writel(0, ctx->regs + VIDCON0);
828
829 clk_disable_unprepare(ctx->lcd_clk);
830 clk_disable_unprepare(ctx->bus_clk);
831
832 pm_runtime_put_sync(ctx->dev);
833
834 ctx->suspended = true;
835 }
836
837 static void fimd_trigger(struct device *dev)
838 {
839 struct fimd_context *ctx = dev_get_drvdata(dev);
840 struct fimd_driver_data *driver_data = ctx->driver_data;
841 void *timing_base = ctx->regs + driver_data->timing_base;
842 u32 reg;
843
844 /*
845 * Skips triggering if in triggering state, because multiple triggering
846 * requests can cause panel reset.
847 */
848 if (atomic_read(&ctx->triggering))
849 return;
850
851 /* Enters triggering mode */
852 atomic_set(&ctx->triggering, 1);
853
854 reg = readl(timing_base + TRIGCON);
855 reg |= (TRGMODE_I80_RGB_ENABLE_I80 | SWTRGCMD_I80_RGB_ENABLE);
856 writel(reg, timing_base + TRIGCON);
857
858 /*
859 * Exits triggering mode if vblank is not enabled yet, because when the
860 * VIDINTCON0 register is not set, it can not exit from triggering mode.
861 */
862 if (!test_bit(0, &ctx->irq_flags))
863 atomic_set(&ctx->triggering, 0);
864 }
865
866 static void fimd_te_handler(struct exynos_drm_crtc *crtc)
867 {
868 struct fimd_context *ctx = crtc->ctx;
869
870 /* Checks the crtc is detached already from encoder */
871 if (ctx->pipe < 0 || !ctx->drm_dev)
872 return;
873
874 /*
875 * If there is a page flip request, triggers and handles the page flip
876 * event so that current fb can be updated into panel GRAM.
877 */
878 if (atomic_add_unless(&ctx->win_updated, -1, 0))
879 fimd_trigger(ctx->dev);
880
881 /* Wakes up vsync event queue */
882 if (atomic_read(&ctx->wait_vsync_event)) {
883 atomic_set(&ctx->wait_vsync_event, 0);
884 wake_up(&ctx->wait_vsync_queue);
885 }
886
887 if (test_bit(0, &ctx->irq_flags))
888 drm_handle_vblank(ctx->drm_dev, ctx->pipe);
889 }
890
891 static void fimd_dp_clock_enable(struct exynos_drm_crtc *crtc, bool enable)
892 {
893 struct fimd_context *ctx = crtc->ctx;
894 u32 val;
895
896 /*
897 * Only Exynos 5250, 5260, 5410 and 542x requires enabling DP/MIE
898 * clock. On these SoCs the bootloader may enable it but any
899 * power domain off/on will reset it to disable state.
900 */
901 if (ctx->driver_data != &exynos5_fimd_driver_data)
902 return;
903
904 val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE;
905 writel(DP_MIE_CLK_DP_ENABLE, ctx->regs + DP_MIE_CLKCON);
906 }
907
908 static const struct exynos_drm_crtc_ops fimd_crtc_ops = {
909 .enable = fimd_enable,
910 .disable = fimd_disable,
911 .mode_fixup = fimd_mode_fixup,
912 .commit = fimd_commit,
913 .enable_vblank = fimd_enable_vblank,
914 .disable_vblank = fimd_disable_vblank,
915 .wait_for_vblank = fimd_wait_for_vblank,
916 .win_commit = fimd_win_commit,
917 .win_disable = fimd_win_disable,
918 .te_handler = fimd_te_handler,
919 .clock_enable = fimd_dp_clock_enable,
920 };
921
922 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
923 {
924 struct fimd_context *ctx = (struct fimd_context *)dev_id;
925 u32 val, clear_bit;
926
927 val = readl(ctx->regs + VIDINTCON1);
928
929 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
930 if (val & clear_bit)
931 writel(clear_bit, ctx->regs + VIDINTCON1);
932
933 /* check the crtc is detached already from encoder */
934 if (ctx->pipe < 0 || !ctx->drm_dev)
935 goto out;
936
937 if (ctx->i80_if) {
938 exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
939
940 /* Exits triggering mode */
941 atomic_set(&ctx->triggering, 0);
942 } else {
943 drm_handle_vblank(ctx->drm_dev, ctx->pipe);
944 exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
945
946 /* set wait vsync event to zero and wake up queue. */
947 if (atomic_read(&ctx->wait_vsync_event)) {
948 atomic_set(&ctx->wait_vsync_event, 0);
949 wake_up(&ctx->wait_vsync_queue);
950 }
951 }
952
953 out:
954 return IRQ_HANDLED;
955 }
956
957 static int fimd_bind(struct device *dev, struct device *master, void *data)
958 {
959 struct fimd_context *ctx = dev_get_drvdata(dev);
960 struct drm_device *drm_dev = data;
961 struct exynos_drm_private *priv = drm_dev->dev_private;
962 struct exynos_drm_plane *exynos_plane;
963 enum drm_plane_type type;
964 unsigned int zpos;
965 int ret;
966
967 ctx->drm_dev = drm_dev;
968 ctx->pipe = priv->pipe++;
969
970 for (zpos = 0; zpos < WINDOWS_NR; zpos++) {
971 type = (zpos == ctx->default_win) ? DRM_PLANE_TYPE_PRIMARY :
972 DRM_PLANE_TYPE_OVERLAY;
973 ret = exynos_plane_init(drm_dev, &ctx->planes[zpos],
974 1 << ctx->pipe, type, zpos);
975 if (ret)
976 return ret;
977 }
978
979 exynos_plane = &ctx->planes[ctx->default_win];
980 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
981 ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD,
982 &fimd_crtc_ops, ctx);
983 if (IS_ERR(ctx->crtc))
984 return PTR_ERR(ctx->crtc);
985
986 if (ctx->display)
987 exynos_drm_create_enc_conn(drm_dev, ctx->display);
988
989 return fimd_iommu_attach_devices(ctx, drm_dev);
990 }
991
992 static void fimd_unbind(struct device *dev, struct device *master,
993 void *data)
994 {
995 struct fimd_context *ctx = dev_get_drvdata(dev);
996
997 fimd_disable(ctx->crtc);
998
999 fimd_iommu_detach_devices(ctx);
1000
1001 if (ctx->display)
1002 exynos_dpi_remove(ctx->display);
1003 }
1004
1005 static const struct component_ops fimd_component_ops = {
1006 .bind = fimd_bind,
1007 .unbind = fimd_unbind,
1008 };
1009
1010 static int fimd_probe(struct platform_device *pdev)
1011 {
1012 struct device *dev = &pdev->dev;
1013 struct fimd_context *ctx;
1014 struct device_node *i80_if_timings;
1015 struct resource *res;
1016 int ret;
1017
1018 if (!dev->of_node)
1019 return -ENODEV;
1020
1021 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1022 if (!ctx)
1023 return -ENOMEM;
1024
1025 ctx->dev = dev;
1026 ctx->suspended = true;
1027 ctx->driver_data = drm_fimd_get_driver_data(pdev);
1028
1029 if (of_property_read_bool(dev->of_node, "samsung,invert-vden"))
1030 ctx->vidcon1 |= VIDCON1_INV_VDEN;
1031 if (of_property_read_bool(dev->of_node, "samsung,invert-vclk"))
1032 ctx->vidcon1 |= VIDCON1_INV_VCLK;
1033
1034 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
1035 if (i80_if_timings) {
1036 u32 val;
1037
1038 ctx->i80_if = true;
1039
1040 if (ctx->driver_data->has_vidoutcon)
1041 ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0;
1042 else
1043 ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0;
1044 /*
1045 * The user manual describes that this "DSI_EN" bit is required
1046 * to enable I80 24-bit data interface.
1047 */
1048 ctx->vidcon0 |= VIDCON0_DSI_EN;
1049
1050 if (of_property_read_u32(i80_if_timings, "cs-setup", &val))
1051 val = 0;
1052 ctx->i80ifcon = LCD_CS_SETUP(val);
1053 if (of_property_read_u32(i80_if_timings, "wr-setup", &val))
1054 val = 0;
1055 ctx->i80ifcon |= LCD_WR_SETUP(val);
1056 if (of_property_read_u32(i80_if_timings, "wr-active", &val))
1057 val = 1;
1058 ctx->i80ifcon |= LCD_WR_ACTIVE(val);
1059 if (of_property_read_u32(i80_if_timings, "wr-hold", &val))
1060 val = 0;
1061 ctx->i80ifcon |= LCD_WR_HOLD(val);
1062 }
1063 of_node_put(i80_if_timings);
1064
1065 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1066 "samsung,sysreg");
1067 if (IS_ERR(ctx->sysreg)) {
1068 dev_warn(dev, "failed to get system register.\n");
1069 ctx->sysreg = NULL;
1070 }
1071
1072 ctx->bus_clk = devm_clk_get(dev, "fimd");
1073 if (IS_ERR(ctx->bus_clk)) {
1074 dev_err(dev, "failed to get bus clock\n");
1075 return PTR_ERR(ctx->bus_clk);
1076 }
1077
1078 ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
1079 if (IS_ERR(ctx->lcd_clk)) {
1080 dev_err(dev, "failed to get lcd clock\n");
1081 return PTR_ERR(ctx->lcd_clk);
1082 }
1083
1084 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1085
1086 ctx->regs = devm_ioremap_resource(dev, res);
1087 if (IS_ERR(ctx->regs))
1088 return PTR_ERR(ctx->regs);
1089
1090 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1091 ctx->i80_if ? "lcd_sys" : "vsync");
1092 if (!res) {
1093 dev_err(dev, "irq request failed.\n");
1094 return -ENXIO;
1095 }
1096
1097 ret = devm_request_irq(dev, res->start, fimd_irq_handler,
1098 0, "drm_fimd", ctx);
1099 if (ret) {
1100 dev_err(dev, "irq request failed.\n");
1101 return ret;
1102 }
1103
1104 init_waitqueue_head(&ctx->wait_vsync_queue);
1105 atomic_set(&ctx->wait_vsync_event, 0);
1106
1107 platform_set_drvdata(pdev, ctx);
1108
1109 ctx->display = exynos_dpi_probe(dev);
1110 if (IS_ERR(ctx->display)) {
1111 return PTR_ERR(ctx->display);
1112 }
1113
1114 pm_runtime_enable(dev);
1115
1116 ret = component_add(dev, &fimd_component_ops);
1117 if (ret)
1118 goto err_disable_pm_runtime;
1119
1120 return ret;
1121
1122 err_disable_pm_runtime:
1123 pm_runtime_disable(dev);
1124
1125 return ret;
1126 }
1127
1128 static int fimd_remove(struct platform_device *pdev)
1129 {
1130 pm_runtime_disable(&pdev->dev);
1131
1132 component_del(&pdev->dev, &fimd_component_ops);
1133
1134 return 0;
1135 }
1136
1137 struct platform_driver fimd_driver = {
1138 .probe = fimd_probe,
1139 .remove = fimd_remove,
1140 .driver = {
1141 .name = "exynos4-fb",
1142 .owner = THIS_MODULE,
1143 .of_match_table = fimd_driver_dt_match,
1144 },
1145 };
Linux kernel - Deliverables
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