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drm/exynos: Remove tracking log functions
[deliverable/linux.git] / drivers / gpu / drm / exynos / exynos_drm_fimd.c
1 /* exynos_drm_fimd.c
2 *
3 * Copyright (C) 2011 Samsung Electronics Co.Ltd
4 * Authors:
5 * Joonyoung Shim <jy0922.shim@samsung.com>
6 * Inki Dae <inki.dae@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14 #include <drm/drmP.h>
15
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/clk.h>
20 #include <linux/of_device.h>
21 #include <linux/pm_runtime.h>
22
23 #include <video/of_display_timing.h>
24 #include <video/samsung_fimd.h>
25 #include <drm/exynos_drm.h>
26
27 #include "exynos_drm_drv.h"
28 #include "exynos_drm_fbdev.h"
29 #include "exynos_drm_crtc.h"
30 #include "exynos_drm_iommu.h"
31
32 /*
33 * FIMD is stand for Fully Interactive Mobile Display and
34 * as a display controller, it transfers contents drawn on memory
35 * to a LCD Panel through Display Interfaces such as RGB or
36 * CPU Interface.
37 */
38
39 /* position control register for hardware window 0, 2 ~ 4.*/
40 #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
41 #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
42 /*
43 * size control register for hardware windows 0 and alpha control register
44 * for hardware windows 1 ~ 4
45 */
46 #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16)
47 /* size control register for hardware windows 1 ~ 2. */
48 #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
49
50 #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
51 #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8)
52 #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
53
54 /* color key control register for hardware window 1 ~ 4. */
55 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8))
56 /* color key value register for hardware window 1 ~ 4. */
57 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
58
59 /* FIMD has totally five hardware windows. */
60 #define WINDOWS_NR 5
61
62 #define get_fimd_context(dev) platform_get_drvdata(to_platform_device(dev))
63
64 struct fimd_driver_data {
65 unsigned int timing_base;
66
67 unsigned int has_shadowcon:1;
68 unsigned int has_clksel:1;
69 };
70
71 static struct fimd_driver_data s3c64xx_fimd_driver_data = {
72 .timing_base = 0x0,
73 .has_clksel = 1,
74 };
75
76 static struct fimd_driver_data exynos4_fimd_driver_data = {
77 .timing_base = 0x0,
78 .has_shadowcon = 1,
79 };
80
81 static struct fimd_driver_data exynos5_fimd_driver_data = {
82 .timing_base = 0x20000,
83 .has_shadowcon = 1,
84 };
85
86 struct fimd_win_data {
87 unsigned int offset_x;
88 unsigned int offset_y;
89 unsigned int ovl_width;
90 unsigned int ovl_height;
91 unsigned int fb_width;
92 unsigned int fb_height;
93 unsigned int bpp;
94 dma_addr_t dma_addr;
95 unsigned int buf_offsize;
96 unsigned int line_size; /* bytes */
97 bool enabled;
98 bool resume;
99 };
100
101 struct fimd_context {
102 struct exynos_drm_subdrv subdrv;
103 int irq;
104 struct drm_crtc *crtc;
105 struct clk *bus_clk;
106 struct clk *lcd_clk;
107 void __iomem *regs;
108 struct fimd_win_data win_data[WINDOWS_NR];
109 unsigned int clkdiv;
110 unsigned int default_win;
111 unsigned long irq_flags;
112 u32 vidcon0;
113 u32 vidcon1;
114 bool suspended;
115 struct mutex lock;
116 wait_queue_head_t wait_vsync_queue;
117 atomic_t wait_vsync_event;
118
119 struct exynos_drm_panel_info *panel;
120 struct fimd_driver_data *driver_data;
121 };
122
123 #ifdef CONFIG_OF
124 static const struct of_device_id fimd_driver_dt_match[] = {
125 { .compatible = "samsung,s3c6400-fimd",
126 .data = &s3c64xx_fimd_driver_data },
127 { .compatible = "samsung,exynos4210-fimd",
128 .data = &exynos4_fimd_driver_data },
129 { .compatible = "samsung,exynos5250-fimd",
130 .data = &exynos5_fimd_driver_data },
131 {},
132 };
133 MODULE_DEVICE_TABLE(of, fimd_driver_dt_match);
134 #endif
135
136 static inline struct fimd_driver_data *drm_fimd_get_driver_data(
137 struct platform_device *pdev)
138 {
139 #ifdef CONFIG_OF
140 const struct of_device_id *of_id =
141 of_match_device(fimd_driver_dt_match, &pdev->dev);
142
143 if (of_id)
144 return (struct fimd_driver_data *)of_id->data;
145 #endif
146
147 return (struct fimd_driver_data *)
148 platform_get_device_id(pdev)->driver_data;
149 }
150
151 static bool fimd_display_is_connected(struct device *dev)
152 {
153 /* TODO. */
154
155 return true;
156 }
157
158 static void *fimd_get_panel(struct device *dev)
159 {
160 struct fimd_context *ctx = get_fimd_context(dev);
161
162 return ctx->panel;
163 }
164
165 static int fimd_check_mode(struct device *dev, struct drm_display_mode *mode)
166 {
167 /* TODO. */
168
169 return 0;
170 }
171
172 static int fimd_display_power_on(struct device *dev, int mode)
173 {
174 /* TODO */
175
176 return 0;
177 }
178
179 static struct exynos_drm_display_ops fimd_display_ops = {
180 .type = EXYNOS_DISPLAY_TYPE_LCD,
181 .is_connected = fimd_display_is_connected,
182 .get_panel = fimd_get_panel,
183 .check_mode = fimd_check_mode,
184 .power_on = fimd_display_power_on,
185 };
186
187 static void fimd_dpms(struct device *subdrv_dev, int mode)
188 {
189 struct fimd_context *ctx = get_fimd_context(subdrv_dev);
190
191 DRM_DEBUG_KMS("%d\n", mode);
192
193 mutex_lock(&ctx->lock);
194
195 switch (mode) {
196 case DRM_MODE_DPMS_ON:
197 /*
198 * enable fimd hardware only if suspended status.
199 *
200 * P.S. fimd_dpms function would be called at booting time so
201 * clk_enable could be called double time.
202 */
203 if (ctx->suspended)
204 pm_runtime_get_sync(subdrv_dev);
205 break;
206 case DRM_MODE_DPMS_STANDBY:
207 case DRM_MODE_DPMS_SUSPEND:
208 case DRM_MODE_DPMS_OFF:
209 if (!ctx->suspended)
210 pm_runtime_put_sync(subdrv_dev);
211 break;
212 default:
213 DRM_DEBUG_KMS("unspecified mode %d\n", mode);
214 break;
215 }
216
217 mutex_unlock(&ctx->lock);
218 }
219
220 static void fimd_apply(struct device *subdrv_dev)
221 {
222 struct fimd_context *ctx = get_fimd_context(subdrv_dev);
223 struct exynos_drm_manager *mgr = ctx->subdrv.manager;
224 struct exynos_drm_manager_ops *mgr_ops = mgr->ops;
225 struct exynos_drm_overlay_ops *ovl_ops = mgr->overlay_ops;
226 struct fimd_win_data *win_data;
227 int i;
228
229 for (i = 0; i < WINDOWS_NR; i++) {
230 win_data = &ctx->win_data[i];
231 if (win_data->enabled && (ovl_ops && ovl_ops->commit))
232 ovl_ops->commit(subdrv_dev, i);
233 }
234
235 if (mgr_ops && mgr_ops->commit)
236 mgr_ops->commit(subdrv_dev);
237 }
238
239 static void fimd_commit(struct device *dev)
240 {
241 struct fimd_context *ctx = get_fimd_context(dev);
242 struct exynos_drm_panel_info *panel = ctx->panel;
243 struct fb_videomode *timing = &panel->timing;
244 struct fimd_driver_data *driver_data;
245 u32 val;
246
247 driver_data = ctx->driver_data;
248 if (ctx->suspended)
249 return;
250
251 /* setup polarity values from machine code. */
252 writel(ctx->vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
253
254 /* setup vertical timing values. */
255 val = VIDTCON0_VBPD(timing->upper_margin - 1) |
256 VIDTCON0_VFPD(timing->lower_margin - 1) |
257 VIDTCON0_VSPW(timing->vsync_len - 1);
258 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
259
260 /* setup horizontal timing values. */
261 val = VIDTCON1_HBPD(timing->left_margin - 1) |
262 VIDTCON1_HFPD(timing->right_margin - 1) |
263 VIDTCON1_HSPW(timing->hsync_len - 1);
264 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
265
266 /* setup horizontal and vertical display size. */
267 val = VIDTCON2_LINEVAL(timing->yres - 1) |
268 VIDTCON2_HOZVAL(timing->xres - 1) |
269 VIDTCON2_LINEVAL_E(timing->yres - 1) |
270 VIDTCON2_HOZVAL_E(timing->xres - 1);
271 writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
272
273 /* setup clock source, clock divider, enable dma. */
274 val = ctx->vidcon0;
275 val &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR);
276
277 if (ctx->driver_data->has_clksel) {
278 val &= ~VIDCON0_CLKSEL_MASK;
279 val |= VIDCON0_CLKSEL_LCD;
280 }
281
282 if (ctx->clkdiv > 1)
283 val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR;
284 else
285 val &= ~VIDCON0_CLKDIR; /* 1:1 clock */
286
287 /*
288 * fields of register with prefix '_F' would be updated
289 * at vsync(same as dma start)
290 */
291 val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
292 writel(val, ctx->regs + VIDCON0);
293 }
294
295 static int fimd_enable_vblank(struct device *dev)
296 {
297 struct fimd_context *ctx = get_fimd_context(dev);
298 u32 val;
299
300 if (ctx->suspended)
301 return -EPERM;
302
303 if (!test_and_set_bit(0, &ctx->irq_flags)) {
304 val = readl(ctx->regs + VIDINTCON0);
305
306 val |= VIDINTCON0_INT_ENABLE;
307 val |= VIDINTCON0_INT_FRAME;
308
309 val &= ~VIDINTCON0_FRAMESEL0_MASK;
310 val |= VIDINTCON0_FRAMESEL0_VSYNC;
311 val &= ~VIDINTCON0_FRAMESEL1_MASK;
312 val |= VIDINTCON0_FRAMESEL1_NONE;
313
314 writel(val, ctx->regs + VIDINTCON0);
315 }
316
317 return 0;
318 }
319
320 static void fimd_disable_vblank(struct device *dev)
321 {
322 struct fimd_context *ctx = get_fimd_context(dev);
323 u32 val;
324
325 if (ctx->suspended)
326 return;
327
328 if (test_and_clear_bit(0, &ctx->irq_flags)) {
329 val = readl(ctx->regs + VIDINTCON0);
330
331 val &= ~VIDINTCON0_INT_FRAME;
332 val &= ~VIDINTCON0_INT_ENABLE;
333
334 writel(val, ctx->regs + VIDINTCON0);
335 }
336 }
337
338 static void fimd_wait_for_vblank(struct device *dev)
339 {
340 struct fimd_context *ctx = get_fimd_context(dev);
341
342 if (ctx->suspended)
343 return;
344
345 atomic_set(&ctx->wait_vsync_event, 1);
346
347 /*
348 * wait for FIMD to signal VSYNC interrupt or return after
349 * timeout which is set to 50ms (refresh rate of 20).
350 */
351 if (!wait_event_timeout(ctx->wait_vsync_queue,
352 !atomic_read(&ctx->wait_vsync_event),
353 DRM_HZ/20))
354 DRM_DEBUG_KMS("vblank wait timed out.\n");
355 }
356
357 static struct exynos_drm_manager_ops fimd_manager_ops = {
358 .dpms = fimd_dpms,
359 .apply = fimd_apply,
360 .commit = fimd_commit,
361 .enable_vblank = fimd_enable_vblank,
362 .disable_vblank = fimd_disable_vblank,
363 .wait_for_vblank = fimd_wait_for_vblank,
364 };
365
366 static void fimd_win_mode_set(struct device *dev,
367 struct exynos_drm_overlay *overlay)
368 {
369 struct fimd_context *ctx = get_fimd_context(dev);
370 struct fimd_win_data *win_data;
371 int win;
372 unsigned long offset;
373
374 if (!overlay) {
375 dev_err(dev, "overlay is NULL\n");
376 return;
377 }
378
379 win = overlay->zpos;
380 if (win == DEFAULT_ZPOS)
381 win = ctx->default_win;
382
383 if (win < 0 || win >= WINDOWS_NR)
384 return;
385
386 offset = overlay->fb_x * (overlay->bpp >> 3);
387 offset += overlay->fb_y * overlay->pitch;
388
389 DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, overlay->pitch);
390
391 win_data = &ctx->win_data[win];
392
393 win_data->offset_x = overlay->crtc_x;
394 win_data->offset_y = overlay->crtc_y;
395 win_data->ovl_width = overlay->crtc_width;
396 win_data->ovl_height = overlay->crtc_height;
397 win_data->fb_width = overlay->fb_width;
398 win_data->fb_height = overlay->fb_height;
399 win_data->dma_addr = overlay->dma_addr[0] + offset;
400 win_data->bpp = overlay->bpp;
401 win_data->buf_offsize = (overlay->fb_width - overlay->crtc_width) *
402 (overlay->bpp >> 3);
403 win_data->line_size = overlay->crtc_width * (overlay->bpp >> 3);
404
405 DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n",
406 win_data->offset_x, win_data->offset_y);
407 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
408 win_data->ovl_width, win_data->ovl_height);
409 DRM_DEBUG_KMS("paddr = 0x%lx\n", (unsigned long)win_data->dma_addr);
410 DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n",
411 overlay->fb_width, overlay->crtc_width);
412 }
413
414 static void fimd_win_set_pixfmt(struct device *dev, unsigned int win)
415 {
416 struct fimd_context *ctx = get_fimd_context(dev);
417 struct fimd_win_data *win_data = &ctx->win_data[win];
418 unsigned long val;
419
420 val = WINCONx_ENWIN;
421
422 switch (win_data->bpp) {
423 case 1:
424 val |= WINCON0_BPPMODE_1BPP;
425 val |= WINCONx_BITSWP;
426 val |= WINCONx_BURSTLEN_4WORD;
427 break;
428 case 2:
429 val |= WINCON0_BPPMODE_2BPP;
430 val |= WINCONx_BITSWP;
431 val |= WINCONx_BURSTLEN_8WORD;
432 break;
433 case 4:
434 val |= WINCON0_BPPMODE_4BPP;
435 val |= WINCONx_BITSWP;
436 val |= WINCONx_BURSTLEN_8WORD;
437 break;
438 case 8:
439 val |= WINCON0_BPPMODE_8BPP_PALETTE;
440 val |= WINCONx_BURSTLEN_8WORD;
441 val |= WINCONx_BYTSWP;
442 break;
443 case 16:
444 val |= WINCON0_BPPMODE_16BPP_565;
445 val |= WINCONx_HAWSWP;
446 val |= WINCONx_BURSTLEN_16WORD;
447 break;
448 case 24:
449 val |= WINCON0_BPPMODE_24BPP_888;
450 val |= WINCONx_WSWP;
451 val |= WINCONx_BURSTLEN_16WORD;
452 break;
453 case 32:
454 val |= WINCON1_BPPMODE_28BPP_A4888
455 | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
456 val |= WINCONx_WSWP;
457 val |= WINCONx_BURSTLEN_16WORD;
458 break;
459 default:
460 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
461
462 val |= WINCON0_BPPMODE_24BPP_888;
463 val |= WINCONx_WSWP;
464 val |= WINCONx_BURSTLEN_16WORD;
465 break;
466 }
467
468 DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp);
469
470 writel(val, ctx->regs + WINCON(win));
471 }
472
473 static void fimd_win_set_colkey(struct device *dev, unsigned int win)
474 {
475 struct fimd_context *ctx = get_fimd_context(dev);
476 unsigned int keycon0 = 0, keycon1 = 0;
477
478 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
479 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
480
481 keycon1 = WxKEYCON1_COLVAL(0xffffffff);
482
483 writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
484 writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
485 }
486
487 /**
488 * shadow_protect_win() - disable updating values from shadow registers at vsync
489 *
490 * @win: window to protect registers for
491 * @protect: 1 to protect (disable updates)
492 */
493 static void fimd_shadow_protect_win(struct fimd_context *ctx,
494 int win, bool protect)
495 {
496 u32 reg, bits, val;
497
498 if (ctx->driver_data->has_shadowcon) {
499 reg = SHADOWCON;
500 bits = SHADOWCON_WINx_PROTECT(win);
501 } else {
502 reg = PRTCON;
503 bits = PRTCON_PROTECT;
504 }
505
506 val = readl(ctx->regs + reg);
507 if (protect)
508 val |= bits;
509 else
510 val &= ~bits;
511 writel(val, ctx->regs + reg);
512 }
513
514 static void fimd_win_commit(struct device *dev, int zpos)
515 {
516 struct fimd_context *ctx = get_fimd_context(dev);
517 struct fimd_win_data *win_data;
518 int win = zpos;
519 unsigned long val, alpha, size;
520 unsigned int last_x;
521 unsigned int last_y;
522
523 if (ctx->suspended)
524 return;
525
526 if (win == DEFAULT_ZPOS)
527 win = ctx->default_win;
528
529 if (win < 0 || win >= WINDOWS_NR)
530 return;
531
532 win_data = &ctx->win_data[win];
533
534 /*
535 * SHADOWCON/PRTCON register is used for enabling timing.
536 *
537 * for example, once only width value of a register is set,
538 * if the dma is started then fimd hardware could malfunction so
539 * with protect window setting, the register fields with prefix '_F'
540 * wouldn't be updated at vsync also but updated once unprotect window
541 * is set.
542 */
543
544 /* protect windows */
545 fimd_shadow_protect_win(ctx, win, true);
546
547 /* buffer start address */
548 val = (unsigned long)win_data->dma_addr;
549 writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
550
551 /* buffer end address */
552 size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3);
553 val = (unsigned long)(win_data->dma_addr + size);
554 writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
555
556 DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
557 (unsigned long)win_data->dma_addr, val, size);
558 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
559 win_data->ovl_width, win_data->ovl_height);
560
561 /* buffer size */
562 val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) |
563 VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size) |
564 VIDW_BUF_SIZE_OFFSET_E(win_data->buf_offsize) |
565 VIDW_BUF_SIZE_PAGEWIDTH_E(win_data->line_size);
566 writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
567
568 /* OSD position */
569 val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) |
570 VIDOSDxA_TOPLEFT_Y(win_data->offset_y) |
571 VIDOSDxA_TOPLEFT_X_E(win_data->offset_x) |
572 VIDOSDxA_TOPLEFT_Y_E(win_data->offset_y);
573 writel(val, ctx->regs + VIDOSD_A(win));
574
575 last_x = win_data->offset_x + win_data->ovl_width;
576 if (last_x)
577 last_x--;
578 last_y = win_data->offset_y + win_data->ovl_height;
579 if (last_y)
580 last_y--;
581
582 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
583 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);
584
585 writel(val, ctx->regs + VIDOSD_B(win));
586
587 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
588 win_data->offset_x, win_data->offset_y, last_x, last_y);
589
590 /* hardware window 0 doesn't support alpha channel. */
591 if (win != 0) {
592 /* OSD alpha */
593 alpha = VIDISD14C_ALPHA1_R(0xf) |
594 VIDISD14C_ALPHA1_G(0xf) |
595 VIDISD14C_ALPHA1_B(0xf);
596
597 writel(alpha, ctx->regs + VIDOSD_C(win));
598 }
599
600 /* OSD size */
601 if (win != 3 && win != 4) {
602 u32 offset = VIDOSD_D(win);
603 if (win == 0)
604 offset = VIDOSD_C(win);
605 val = win_data->ovl_width * win_data->ovl_height;
606 writel(val, ctx->regs + offset);
607
608 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
609 }
610
611 fimd_win_set_pixfmt(dev, win);
612
613 /* hardware window 0 doesn't support color key. */
614 if (win != 0)
615 fimd_win_set_colkey(dev, win);
616
617 /* wincon */
618 val = readl(ctx->regs + WINCON(win));
619 val |= WINCONx_ENWIN;
620 writel(val, ctx->regs + WINCON(win));
621
622 /* Enable DMA channel and unprotect windows */
623 fimd_shadow_protect_win(ctx, win, false);
624
625 if (ctx->driver_data->has_shadowcon) {
626 val = readl(ctx->regs + SHADOWCON);
627 val |= SHADOWCON_CHx_ENABLE(win);
628 writel(val, ctx->regs + SHADOWCON);
629 }
630
631 win_data->enabled = true;
632 }
633
634 static void fimd_win_disable(struct device *dev, int zpos)
635 {
636 struct fimd_context *ctx = get_fimd_context(dev);
637 struct fimd_win_data *win_data;
638 int win = zpos;
639 u32 val;
640
641 if (win == DEFAULT_ZPOS)
642 win = ctx->default_win;
643
644 if (win < 0 || win >= WINDOWS_NR)
645 return;
646
647 win_data = &ctx->win_data[win];
648
649 if (ctx->suspended) {
650 /* do not resume this window*/
651 win_data->resume = false;
652 return;
653 }
654
655 /* protect windows */
656 fimd_shadow_protect_win(ctx, win, true);
657
658 /* wincon */
659 val = readl(ctx->regs + WINCON(win));
660 val &= ~WINCONx_ENWIN;
661 writel(val, ctx->regs + WINCON(win));
662
663 /* unprotect windows */
664 if (ctx->driver_data->has_shadowcon) {
665 val = readl(ctx->regs + SHADOWCON);
666 val &= ~SHADOWCON_CHx_ENABLE(win);
667 writel(val, ctx->regs + SHADOWCON);
668 }
669
670 fimd_shadow_protect_win(ctx, win, false);
671
672 win_data->enabled = false;
673 }
674
675 static struct exynos_drm_overlay_ops fimd_overlay_ops = {
676 .mode_set = fimd_win_mode_set,
677 .commit = fimd_win_commit,
678 .disable = fimd_win_disable,
679 };
680
681 static struct exynos_drm_manager fimd_manager = {
682 .pipe = -1,
683 .ops = &fimd_manager_ops,
684 .overlay_ops = &fimd_overlay_ops,
685 .display_ops = &fimd_display_ops,
686 };
687
688 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
689 {
690 struct fimd_context *ctx = (struct fimd_context *)dev_id;
691 struct exynos_drm_subdrv *subdrv = &ctx->subdrv;
692 struct drm_device *drm_dev = subdrv->drm_dev;
693 struct exynos_drm_manager *manager = subdrv->manager;
694 u32 val;
695
696 val = readl(ctx->regs + VIDINTCON1);
697
698 if (val & VIDINTCON1_INT_FRAME)
699 /* VSYNC interrupt */
700 writel(VIDINTCON1_INT_FRAME, ctx->regs + VIDINTCON1);
701
702 /* check the crtc is detached already from encoder */
703 if (manager->pipe < 0)
704 goto out;
705
706 drm_handle_vblank(drm_dev, manager->pipe);
707 exynos_drm_crtc_finish_pageflip(drm_dev, manager->pipe);
708
709 /* set wait vsync event to zero and wake up queue. */
710 if (atomic_read(&ctx->wait_vsync_event)) {
711 atomic_set(&ctx->wait_vsync_event, 0);
712 DRM_WAKEUP(&ctx->wait_vsync_queue);
713 }
714 out:
715 return IRQ_HANDLED;
716 }
717
718 static int fimd_subdrv_probe(struct drm_device *drm_dev, struct device *dev)
719 {
720 /*
721 * enable drm irq mode.
722 * - with irq_enabled = 1, we can use the vblank feature.
723 *
724 * P.S. note that we wouldn't use drm irq handler but
725 * just specific driver own one instead because
726 * drm framework supports only one irq handler.
727 */
728 drm_dev->irq_enabled = 1;
729
730 /*
731 * with vblank_disable_allowed = 1, vblank interrupt will be disabled
732 * by drm timer once a current process gives up ownership of
733 * vblank event.(after drm_vblank_put function is called)
734 */
735 drm_dev->vblank_disable_allowed = 1;
736
737 /* attach this sub driver to iommu mapping if supported. */
738 if (is_drm_iommu_supported(drm_dev))
739 drm_iommu_attach_device(drm_dev, dev);
740
741 return 0;
742 }
743
744 static void fimd_subdrv_remove(struct drm_device *drm_dev, struct device *dev)
745 {
746 /* detach this sub driver from iommu mapping if supported. */
747 if (is_drm_iommu_supported(drm_dev))
748 drm_iommu_detach_device(drm_dev, dev);
749 }
750
751 static int fimd_calc_clkdiv(struct fimd_context *ctx,
752 struct fb_videomode *timing)
753 {
754 unsigned long clk = clk_get_rate(ctx->lcd_clk);
755 u32 retrace;
756 u32 clkdiv;
757 u32 best_framerate = 0;
758 u32 framerate;
759
760 retrace = timing->left_margin + timing->hsync_len +
761 timing->right_margin + timing->xres;
762 retrace *= timing->upper_margin + timing->vsync_len +
763 timing->lower_margin + timing->yres;
764
765 /* default framerate is 60Hz */
766 if (!timing->refresh)
767 timing->refresh = 60;
768
769 clk /= retrace;
770
771 for (clkdiv = 1; clkdiv < 0x100; clkdiv++) {
772 int tmp;
773
774 /* get best framerate */
775 framerate = clk / clkdiv;
776 tmp = timing->refresh - framerate;
777 if (tmp < 0) {
778 best_framerate = framerate;
779 continue;
780 } else {
781 if (!best_framerate)
782 best_framerate = framerate;
783 else if (tmp < (best_framerate - framerate))
784 best_framerate = framerate;
785 break;
786 }
787 }
788
789 return clkdiv;
790 }
791
792 static void fimd_clear_win(struct fimd_context *ctx, int win)
793 {
794 writel(0, ctx->regs + WINCON(win));
795 writel(0, ctx->regs + VIDOSD_A(win));
796 writel(0, ctx->regs + VIDOSD_B(win));
797 writel(0, ctx->regs + VIDOSD_C(win));
798
799 if (win == 1 || win == 2)
800 writel(0, ctx->regs + VIDOSD_D(win));
801
802 fimd_shadow_protect_win(ctx, win, false);
803 }
804
805 static int fimd_clock(struct fimd_context *ctx, bool enable)
806 {
807 if (enable) {
808 int ret;
809
810 ret = clk_prepare_enable(ctx->bus_clk);
811 if (ret < 0)
812 return ret;
813
814 ret = clk_prepare_enable(ctx->lcd_clk);
815 if (ret < 0) {
816 clk_disable_unprepare(ctx->bus_clk);
817 return ret;
818 }
819 } else {
820 clk_disable_unprepare(ctx->lcd_clk);
821 clk_disable_unprepare(ctx->bus_clk);
822 }
823
824 return 0;
825 }
826
827 static void fimd_window_suspend(struct device *dev)
828 {
829 struct fimd_context *ctx = get_fimd_context(dev);
830 struct fimd_win_data *win_data;
831 int i;
832
833 for (i = 0; i < WINDOWS_NR; i++) {
834 win_data = &ctx->win_data[i];
835 win_data->resume = win_data->enabled;
836 fimd_win_disable(dev, i);
837 }
838 fimd_wait_for_vblank(dev);
839 }
840
841 static void fimd_window_resume(struct device *dev)
842 {
843 struct fimd_context *ctx = get_fimd_context(dev);
844 struct fimd_win_data *win_data;
845 int i;
846
847 for (i = 0; i < WINDOWS_NR; i++) {
848 win_data = &ctx->win_data[i];
849 win_data->enabled = win_data->resume;
850 win_data->resume = false;
851 }
852 }
853
854 static int fimd_activate(struct fimd_context *ctx, bool enable)
855 {
856 struct device *dev = ctx->subdrv.dev;
857 if (enable) {
858 int ret;
859
860 ret = fimd_clock(ctx, true);
861 if (ret < 0)
862 return ret;
863
864 ctx->suspended = false;
865
866 /* if vblank was enabled status, enable it again. */
867 if (test_and_clear_bit(0, &ctx->irq_flags))
868 fimd_enable_vblank(dev);
869
870 fimd_window_resume(dev);
871 } else {
872 fimd_window_suspend(dev);
873
874 fimd_clock(ctx, false);
875 ctx->suspended = true;
876 }
877
878 return 0;
879 }
880
881 static int fimd_probe(struct platform_device *pdev)
882 {
883 struct device *dev = &pdev->dev;
884 struct fimd_context *ctx;
885 struct exynos_drm_subdrv *subdrv;
886 struct exynos_drm_fimd_pdata *pdata;
887 struct exynos_drm_panel_info *panel;
888 struct resource *res;
889 int win;
890 int ret = -EINVAL;
891
892 if (dev->of_node) {
893 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
894 if (!pdata) {
895 DRM_ERROR("memory allocation for pdata failed\n");
896 return -ENOMEM;
897 }
898
899 ret = of_get_fb_videomode(dev->of_node, &pdata->panel.timing,
900 OF_USE_NATIVE_MODE);
901 if (ret) {
902 DRM_ERROR("failed: of_get_fb_videomode() : %d\n", ret);
903 return ret;
904 }
905 } else {
906 pdata = dev->platform_data;
907 if (!pdata) {
908 DRM_ERROR("no platform data specified\n");
909 return -EINVAL;
910 }
911 }
912
913 panel = &pdata->panel;
914 if (!panel) {
915 dev_err(dev, "panel is null.\n");
916 return -EINVAL;
917 }
918
919 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
920 if (!ctx)
921 return -ENOMEM;
922
923 ctx->bus_clk = devm_clk_get(dev, "fimd");
924 if (IS_ERR(ctx->bus_clk)) {
925 dev_err(dev, "failed to get bus clock\n");
926 return PTR_ERR(ctx->bus_clk);
927 }
928
929 ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
930 if (IS_ERR(ctx->lcd_clk)) {
931 dev_err(dev, "failed to get lcd clock\n");
932 return PTR_ERR(ctx->lcd_clk);
933 }
934
935 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
936
937 ctx->regs = devm_ioremap_resource(dev, res);
938 if (IS_ERR(ctx->regs))
939 return PTR_ERR(ctx->regs);
940
941 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "vsync");
942 if (!res) {
943 dev_err(dev, "irq request failed.\n");
944 return -ENXIO;
945 }
946
947 ctx->irq = res->start;
948
949 ret = devm_request_irq(dev, ctx->irq, fimd_irq_handler,
950 0, "drm_fimd", ctx);
951 if (ret) {
952 dev_err(dev, "irq request failed.\n");
953 return ret;
954 }
955
956 ctx->driver_data = drm_fimd_get_driver_data(pdev);
957 ctx->vidcon0 = pdata->vidcon0;
958 ctx->vidcon1 = pdata->vidcon1;
959 ctx->default_win = pdata->default_win;
960 ctx->panel = panel;
961 DRM_INIT_WAITQUEUE(&ctx->wait_vsync_queue);
962 atomic_set(&ctx->wait_vsync_event, 0);
963
964 subdrv = &ctx->subdrv;
965
966 subdrv->dev = dev;
967 subdrv->manager = &fimd_manager;
968 subdrv->probe = fimd_subdrv_probe;
969 subdrv->remove = fimd_subdrv_remove;
970
971 mutex_init(&ctx->lock);
972
973 platform_set_drvdata(pdev, ctx);
974
975 pm_runtime_enable(dev);
976 pm_runtime_get_sync(dev);
977
978 ctx->clkdiv = fimd_calc_clkdiv(ctx, &panel->timing);
979 panel->timing.pixclock = clk_get_rate(ctx->lcd_clk) / ctx->clkdiv;
980
981 DRM_DEBUG_KMS("pixel clock = %d, clkdiv = %d\n",
982 panel->timing.pixclock, ctx->clkdiv);
983
984 for (win = 0; win < WINDOWS_NR; win++)
985 fimd_clear_win(ctx, win);
986
987 exynos_drm_subdrv_register(subdrv);
988
989 return 0;
990 }
991
992 static int fimd_remove(struct platform_device *pdev)
993 {
994 struct device *dev = &pdev->dev;
995 struct fimd_context *ctx = platform_get_drvdata(pdev);
996
997 exynos_drm_subdrv_unregister(&ctx->subdrv);
998
999 if (ctx->suspended)
1000 goto out;
1001
1002 pm_runtime_set_suspended(dev);
1003 pm_runtime_put_sync(dev);
1004
1005 out:
1006 pm_runtime_disable(dev);
1007
1008 return 0;
1009 }
1010
1011 #ifdef CONFIG_PM_SLEEP
1012 static int fimd_suspend(struct device *dev)
1013 {
1014 struct fimd_context *ctx = get_fimd_context(dev);
1015
1016 /*
1017 * do not use pm_runtime_suspend(). if pm_runtime_suspend() is
1018 * called here, an error would be returned by that interface
1019 * because the usage_count of pm runtime is more than 1.
1020 */
1021 if (!pm_runtime_suspended(dev))
1022 return fimd_activate(ctx, false);
1023
1024 return 0;
1025 }
1026
1027 static int fimd_resume(struct device *dev)
1028 {
1029 struct fimd_context *ctx = get_fimd_context(dev);
1030
1031 /*
1032 * if entered to sleep when lcd panel was on, the usage_count
1033 * of pm runtime would still be 1 so in this case, fimd driver
1034 * should be on directly not drawing on pm runtime interface.
1035 */
1036 if (!pm_runtime_suspended(dev)) {
1037 int ret;
1038
1039 ret = fimd_activate(ctx, true);
1040 if (ret < 0)
1041 return ret;
1042
1043 /*
1044 * in case of dpms on(standby), fimd_apply function will
1045 * be called by encoder's dpms callback to update fimd's
1046 * registers but in case of sleep wakeup, it's not.
1047 * so fimd_apply function should be called at here.
1048 */
1049 fimd_apply(dev);
1050 }
1051
1052 return 0;
1053 }
1054 #endif
1055
1056 #ifdef CONFIG_PM_RUNTIME
1057 static int fimd_runtime_suspend(struct device *dev)
1058 {
1059 struct fimd_context *ctx = get_fimd_context(dev);
1060
1061 return fimd_activate(ctx, false);
1062 }
1063
1064 static int fimd_runtime_resume(struct device *dev)
1065 {
1066 struct fimd_context *ctx = get_fimd_context(dev);
1067
1068 return fimd_activate(ctx, true);
1069 }
1070 #endif
1071
1072 static struct platform_device_id fimd_driver_ids[] = {
1073 {
1074 .name = "s3c64xx-fb",
1075 .driver_data = (unsigned long)&s3c64xx_fimd_driver_data,
1076 }, {
1077 .name = "exynos4-fb",
1078 .driver_data = (unsigned long)&exynos4_fimd_driver_data,
1079 }, {
1080 .name = "exynos5-fb",
1081 .driver_data = (unsigned long)&exynos5_fimd_driver_data,
1082 },
1083 {},
1084 };
1085 MODULE_DEVICE_TABLE(platform, fimd_driver_ids);
1086
1087 static const struct dev_pm_ops fimd_pm_ops = {
1088 SET_SYSTEM_SLEEP_PM_OPS(fimd_suspend, fimd_resume)
1089 SET_RUNTIME_PM_OPS(fimd_runtime_suspend, fimd_runtime_resume, NULL)
1090 };
1091
1092 struct platform_driver fimd_driver = {
1093 .probe = fimd_probe,
1094 .remove = fimd_remove,
1095 .id_table = fimd_driver_ids,
1096 .driver = {
1097 .name = "exynos4-fb",
1098 .owner = THIS_MODULE,
1099 .pm = &fimd_pm_ops,
1100 .of_match_table = of_match_ptr(fimd_driver_dt_match),
1101 },
1102 };
Linux kernel - Deliverables
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