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Merge tag 'pwm/for-4.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry...
[deliverable/linux.git] / drivers / gpu / drm / exynos / exynos_drm_fimd.c
1 /* exynos_drm_fimd.c
2 *
3 * Copyright (C) 2011 Samsung Electronics Co.Ltd
4 * Authors:
5 * Joonyoung Shim <jy0922.shim@samsung.com>
6 * Inki Dae <inki.dae@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14 #include <drm/drmP.h>
15
16 #include <linux/kernel.h>
17 #include <linux/platform_device.h>
18 #include <linux/clk.h>
19 #include <linux/of.h>
20 #include <linux/of_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/component.h>
23 #include <linux/mfd/syscon.h>
24 #include <linux/regmap.h>
25
26 #include <video/of_display_timing.h>
27 #include <video/of_videomode.h>
28 #include <video/samsung_fimd.h>
29 #include <drm/exynos_drm.h>
30
31 #include "exynos_drm_drv.h"
32 #include "exynos_drm_fb.h"
33 #include "exynos_drm_fbdev.h"
34 #include "exynos_drm_crtc.h"
35 #include "exynos_drm_plane.h"
36 #include "exynos_drm_iommu.h"
37
38 /*
39 * FIMD stands for Fully Interactive Mobile Display and
40 * as a display controller, it transfers contents drawn on memory
41 * to a LCD Panel through Display Interfaces such as RGB or
42 * CPU Interface.
43 */
44
45 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
46
47 /* position control register for hardware window 0, 2 ~ 4.*/
48 #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
49 #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
50 /*
51 * size control register for hardware windows 0 and alpha control register
52 * for hardware windows 1 ~ 4
53 */
54 #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16)
55 /* size control register for hardware windows 1 ~ 2. */
56 #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
57
58 #define VIDWnALPHA0(win) (VIDW_ALPHA + 0x00 + (win) * 8)
59 #define VIDWnALPHA1(win) (VIDW_ALPHA + 0x04 + (win) * 8)
60
61 #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
62 #define VIDWx_BUF_START_S(win, buf) (VIDW_BUF_START_S(buf) + (win) * 8)
63 #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8)
64 #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
65
66 /* color key control register for hardware window 1 ~ 4. */
67 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8))
68 /* color key value register for hardware window 1 ~ 4. */
69 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
70
71 /* I80 trigger control register */
72 #define TRIGCON 0x1A4
73 #define TRGMODE_ENABLE (1 << 0)
74 #define SWTRGCMD_ENABLE (1 << 1)
75 /* Exynos3250, 3472, 4415, 5260 5410, 5420 and 5422 only supported. */
76 #define HWTRGEN_ENABLE (1 << 3)
77 #define HWTRGMASK_ENABLE (1 << 4)
78 /* Exynos3250, 3472, 4415, 5260, 5420 and 5422 only supported. */
79 #define HWTRIGEN_PER_ENABLE (1 << 31)
80
81 /* display mode change control register except exynos4 */
82 #define VIDOUT_CON 0x000
83 #define VIDOUT_CON_F_I80_LDI0 (0x2 << 8)
84
85 /* I80 interface control for main LDI register */
86 #define I80IFCONFAx(x) (0x1B0 + (x) * 4)
87 #define I80IFCONFBx(x) (0x1B8 + (x) * 4)
88 #define LCD_CS_SETUP(x) ((x) << 16)
89 #define LCD_WR_SETUP(x) ((x) << 12)
90 #define LCD_WR_ACTIVE(x) ((x) << 8)
91 #define LCD_WR_HOLD(x) ((x) << 4)
92 #define I80IFEN_ENABLE (1 << 0)
93
94 /* FIMD has totally five hardware windows. */
95 #define WINDOWS_NR 5
96
97 /* HW trigger flag on i80 panel. */
98 #define I80_HW_TRG (1 << 1)
99
100 struct fimd_driver_data {
101 unsigned int timing_base;
102 unsigned int lcdblk_offset;
103 unsigned int lcdblk_vt_shift;
104 unsigned int lcdblk_bypass_shift;
105 unsigned int lcdblk_mic_bypass_shift;
106 unsigned int trg_type;
107
108 unsigned int has_shadowcon:1;
109 unsigned int has_clksel:1;
110 unsigned int has_limited_fmt:1;
111 unsigned int has_vidoutcon:1;
112 unsigned int has_vtsel:1;
113 unsigned int has_mic_bypass:1;
114 unsigned int has_dp_clk:1;
115 unsigned int has_hw_trigger:1;
116 unsigned int has_trigger_per_te:1;
117 };
118
119 static struct fimd_driver_data s3c64xx_fimd_driver_data = {
120 .timing_base = 0x0,
121 .has_clksel = 1,
122 .has_limited_fmt = 1,
123 .has_hw_trigger = 1,
124 };
125
126 static struct fimd_driver_data exynos3_fimd_driver_data = {
127 .timing_base = 0x20000,
128 .lcdblk_offset = 0x210,
129 .lcdblk_bypass_shift = 1,
130 .trg_type = I80_HW_TRG,
131 .has_shadowcon = 1,
132 .has_vidoutcon = 1,
133 .has_trigger_per_te = 1,
134 };
135
136 static struct fimd_driver_data exynos4_fimd_driver_data = {
137 .timing_base = 0x0,
138 .lcdblk_offset = 0x210,
139 .lcdblk_vt_shift = 10,
140 .lcdblk_bypass_shift = 1,
141 .has_shadowcon = 1,
142 .has_vtsel = 1,
143 };
144
145 static struct fimd_driver_data exynos4415_fimd_driver_data = {
146 .timing_base = 0x20000,
147 .lcdblk_offset = 0x210,
148 .lcdblk_vt_shift = 10,
149 .lcdblk_bypass_shift = 1,
150 .trg_type = I80_HW_TRG,
151 .has_shadowcon = 1,
152 .has_vidoutcon = 1,
153 .has_vtsel = 1,
154 .has_trigger_per_te = 1,
155 };
156
157 static struct fimd_driver_data exynos5_fimd_driver_data = {
158 .timing_base = 0x20000,
159 .lcdblk_offset = 0x214,
160 .lcdblk_vt_shift = 24,
161 .lcdblk_bypass_shift = 15,
162 .has_shadowcon = 1,
163 .has_vidoutcon = 1,
164 .has_vtsel = 1,
165 .has_dp_clk = 1,
166 };
167
168 static struct fimd_driver_data exynos5420_fimd_driver_data = {
169 .timing_base = 0x20000,
170 .lcdblk_offset = 0x214,
171 .lcdblk_vt_shift = 24,
172 .lcdblk_bypass_shift = 15,
173 .lcdblk_mic_bypass_shift = 11,
174 .trg_type = I80_HW_TRG,
175 .has_shadowcon = 1,
176 .has_vidoutcon = 1,
177 .has_vtsel = 1,
178 .has_mic_bypass = 1,
179 .has_dp_clk = 1,
180 .has_hw_trigger = 1,
181 .has_trigger_per_te = 1,
182 };
183
184 struct fimd_context {
185 struct device *dev;
186 struct drm_device *drm_dev;
187 struct exynos_drm_crtc *crtc;
188 struct exynos_drm_plane planes[WINDOWS_NR];
189 struct exynos_drm_plane_config configs[WINDOWS_NR];
190 struct clk *bus_clk;
191 struct clk *lcd_clk;
192 void __iomem *regs;
193 struct regmap *sysreg;
194 unsigned long irq_flags;
195 u32 vidcon0;
196 u32 vidcon1;
197 u32 vidout_con;
198 u32 i80ifcon;
199 bool i80_if;
200 bool suspended;
201 int pipe;
202 wait_queue_head_t wait_vsync_queue;
203 atomic_t wait_vsync_event;
204 atomic_t win_updated;
205 atomic_t triggering;
206
207 const struct fimd_driver_data *driver_data;
208 struct drm_encoder *encoder;
209 struct exynos_drm_clk dp_clk;
210 };
211
212 static const struct of_device_id fimd_driver_dt_match[] = {
213 { .compatible = "samsung,s3c6400-fimd",
214 .data = &s3c64xx_fimd_driver_data },
215 { .compatible = "samsung,exynos3250-fimd",
216 .data = &exynos3_fimd_driver_data },
217 { .compatible = "samsung,exynos4210-fimd",
218 .data = &exynos4_fimd_driver_data },
219 { .compatible = "samsung,exynos4415-fimd",
220 .data = &exynos4415_fimd_driver_data },
221 { .compatible = "samsung,exynos5250-fimd",
222 .data = &exynos5_fimd_driver_data },
223 { .compatible = "samsung,exynos5420-fimd",
224 .data = &exynos5420_fimd_driver_data },
225 {},
226 };
227 MODULE_DEVICE_TABLE(of, fimd_driver_dt_match);
228
229 static const enum drm_plane_type fimd_win_types[WINDOWS_NR] = {
230 DRM_PLANE_TYPE_PRIMARY,
231 DRM_PLANE_TYPE_OVERLAY,
232 DRM_PLANE_TYPE_OVERLAY,
233 DRM_PLANE_TYPE_OVERLAY,
234 DRM_PLANE_TYPE_CURSOR,
235 };
236
237 static const uint32_t fimd_formats[] = {
238 DRM_FORMAT_C8,
239 DRM_FORMAT_XRGB1555,
240 DRM_FORMAT_RGB565,
241 DRM_FORMAT_XRGB8888,
242 DRM_FORMAT_ARGB8888,
243 };
244
245 static int fimd_enable_vblank(struct exynos_drm_crtc *crtc)
246 {
247 struct fimd_context *ctx = crtc->ctx;
248 u32 val;
249
250 if (ctx->suspended)
251 return -EPERM;
252
253 if (!test_and_set_bit(0, &ctx->irq_flags)) {
254 val = readl(ctx->regs + VIDINTCON0);
255
256 val |= VIDINTCON0_INT_ENABLE;
257
258 if (ctx->i80_if) {
259 val |= VIDINTCON0_INT_I80IFDONE;
260 val |= VIDINTCON0_INT_SYSMAINCON;
261 val &= ~VIDINTCON0_INT_SYSSUBCON;
262 } else {
263 val |= VIDINTCON0_INT_FRAME;
264
265 val &= ~VIDINTCON0_FRAMESEL0_MASK;
266 val |= VIDINTCON0_FRAMESEL0_VSYNC;
267 val &= ~VIDINTCON0_FRAMESEL1_MASK;
268 val |= VIDINTCON0_FRAMESEL1_NONE;
269 }
270
271 writel(val, ctx->regs + VIDINTCON0);
272 }
273
274 return 0;
275 }
276
277 static void fimd_disable_vblank(struct exynos_drm_crtc *crtc)
278 {
279 struct fimd_context *ctx = crtc->ctx;
280 u32 val;
281
282 if (ctx->suspended)
283 return;
284
285 if (test_and_clear_bit(0, &ctx->irq_flags)) {
286 val = readl(ctx->regs + VIDINTCON0);
287
288 val &= ~VIDINTCON0_INT_ENABLE;
289
290 if (ctx->i80_if) {
291 val &= ~VIDINTCON0_INT_I80IFDONE;
292 val &= ~VIDINTCON0_INT_SYSMAINCON;
293 val &= ~VIDINTCON0_INT_SYSSUBCON;
294 } else
295 val &= ~VIDINTCON0_INT_FRAME;
296
297 writel(val, ctx->regs + VIDINTCON0);
298 }
299 }
300
301 static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc)
302 {
303 struct fimd_context *ctx = crtc->ctx;
304
305 if (ctx->suspended)
306 return;
307
308 atomic_set(&ctx->wait_vsync_event, 1);
309
310 /*
311 * wait for FIMD to signal VSYNC interrupt or return after
312 * timeout which is set to 50ms (refresh rate of 20).
313 */
314 if (!wait_event_timeout(ctx->wait_vsync_queue,
315 !atomic_read(&ctx->wait_vsync_event),
316 HZ/20))
317 DRM_DEBUG_KMS("vblank wait timed out.\n");
318 }
319
320 static void fimd_enable_video_output(struct fimd_context *ctx, unsigned int win,
321 bool enable)
322 {
323 u32 val = readl(ctx->regs + WINCON(win));
324
325 if (enable)
326 val |= WINCONx_ENWIN;
327 else
328 val &= ~WINCONx_ENWIN;
329
330 writel(val, ctx->regs + WINCON(win));
331 }
332
333 static void fimd_enable_shadow_channel_path(struct fimd_context *ctx,
334 unsigned int win,
335 bool enable)
336 {
337 u32 val = readl(ctx->regs + SHADOWCON);
338
339 if (enable)
340 val |= SHADOWCON_CHx_ENABLE(win);
341 else
342 val &= ~SHADOWCON_CHx_ENABLE(win);
343
344 writel(val, ctx->regs + SHADOWCON);
345 }
346
347 static void fimd_clear_channels(struct exynos_drm_crtc *crtc)
348 {
349 struct fimd_context *ctx = crtc->ctx;
350 unsigned int win, ch_enabled = 0;
351
352 DRM_DEBUG_KMS("%s\n", __FILE__);
353
354 /* Hardware is in unknown state, so ensure it gets enabled properly */
355 pm_runtime_get_sync(ctx->dev);
356
357 clk_prepare_enable(ctx->bus_clk);
358 clk_prepare_enable(ctx->lcd_clk);
359
360 /* Check if any channel is enabled. */
361 for (win = 0; win < WINDOWS_NR; win++) {
362 u32 val = readl(ctx->regs + WINCON(win));
363
364 if (val & WINCONx_ENWIN) {
365 fimd_enable_video_output(ctx, win, false);
366
367 if (ctx->driver_data->has_shadowcon)
368 fimd_enable_shadow_channel_path(ctx, win,
369 false);
370
371 ch_enabled = 1;
372 }
373 }
374
375 /* Wait for vsync, as disable channel takes effect at next vsync */
376 if (ch_enabled) {
377 int pipe = ctx->pipe;
378
379 /* ensure that vblank interrupt won't be reported to core */
380 ctx->suspended = false;
381 ctx->pipe = -1;
382
383 fimd_enable_vblank(ctx->crtc);
384 fimd_wait_for_vblank(ctx->crtc);
385 fimd_disable_vblank(ctx->crtc);
386
387 ctx->suspended = true;
388 ctx->pipe = pipe;
389 }
390
391 clk_disable_unprepare(ctx->lcd_clk);
392 clk_disable_unprepare(ctx->bus_clk);
393
394 pm_runtime_put(ctx->dev);
395 }
396
397 static u32 fimd_calc_clkdiv(struct fimd_context *ctx,
398 const struct drm_display_mode *mode)
399 {
400 unsigned long ideal_clk;
401 u32 clkdiv;
402
403 if (mode->clock == 0) {
404 DRM_ERROR("Mode has zero clock value.\n");
405 return 0xff;
406 }
407
408 ideal_clk = mode->clock * 1000;
409
410 if (ctx->i80_if) {
411 /*
412 * The frame done interrupt should be occurred prior to the
413 * next TE signal.
414 */
415 ideal_clk *= 2;
416 }
417
418 /* Find the clock divider value that gets us closest to ideal_clk */
419 clkdiv = DIV_ROUND_CLOSEST(clk_get_rate(ctx->lcd_clk), ideal_clk);
420
421 return (clkdiv < 0x100) ? clkdiv : 0xff;
422 }
423
424 static void fimd_setup_trigger(struct fimd_context *ctx)
425 {
426 void __iomem *timing_base = ctx->regs + ctx->driver_data->timing_base;
427 u32 trg_type = ctx->driver_data->trg_type;
428 u32 val = readl(timing_base + TRIGCON);
429
430 val &= ~(TRGMODE_ENABLE);
431
432 if (trg_type == I80_HW_TRG) {
433 if (ctx->driver_data->has_hw_trigger)
434 val |= HWTRGEN_ENABLE | HWTRGMASK_ENABLE;
435 if (ctx->driver_data->has_trigger_per_te)
436 val |= HWTRIGEN_PER_ENABLE;
437 } else {
438 val |= TRGMODE_ENABLE;
439 }
440
441 writel(val, timing_base + TRIGCON);
442 }
443
444 static void fimd_commit(struct exynos_drm_crtc *crtc)
445 {
446 struct fimd_context *ctx = crtc->ctx;
447 struct drm_display_mode *mode = &crtc->base.state->adjusted_mode;
448 const struct fimd_driver_data *driver_data = ctx->driver_data;
449 void *timing_base = ctx->regs + driver_data->timing_base;
450 u32 val, clkdiv;
451
452 if (ctx->suspended)
453 return;
454
455 /* nothing to do if we haven't set the mode yet */
456 if (mode->htotal == 0 || mode->vtotal == 0)
457 return;
458
459 if (ctx->i80_if) {
460 val = ctx->i80ifcon | I80IFEN_ENABLE;
461 writel(val, timing_base + I80IFCONFAx(0));
462
463 /* disable auto frame rate */
464 writel(0, timing_base + I80IFCONFBx(0));
465
466 /* set video type selection to I80 interface */
467 if (driver_data->has_vtsel && ctx->sysreg &&
468 regmap_update_bits(ctx->sysreg,
469 driver_data->lcdblk_offset,
470 0x3 << driver_data->lcdblk_vt_shift,
471 0x1 << driver_data->lcdblk_vt_shift)) {
472 DRM_ERROR("Failed to update sysreg for I80 i/f.\n");
473 return;
474 }
475 } else {
476 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
477 u32 vidcon1;
478
479 /* setup polarity values */
480 vidcon1 = ctx->vidcon1;
481 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
482 vidcon1 |= VIDCON1_INV_VSYNC;
483 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
484 vidcon1 |= VIDCON1_INV_HSYNC;
485 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
486
487 /* setup vertical timing values. */
488 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
489 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
490 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
491
492 val = VIDTCON0_VBPD(vbpd - 1) |
493 VIDTCON0_VFPD(vfpd - 1) |
494 VIDTCON0_VSPW(vsync_len - 1);
495 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
496
497 /* setup horizontal timing values. */
498 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
499 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
500 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
501
502 val = VIDTCON1_HBPD(hbpd - 1) |
503 VIDTCON1_HFPD(hfpd - 1) |
504 VIDTCON1_HSPW(hsync_len - 1);
505 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
506 }
507
508 if (driver_data->has_vidoutcon)
509 writel(ctx->vidout_con, timing_base + VIDOUT_CON);
510
511 /* set bypass selection */
512 if (ctx->sysreg && regmap_update_bits(ctx->sysreg,
513 driver_data->lcdblk_offset,
514 0x1 << driver_data->lcdblk_bypass_shift,
515 0x1 << driver_data->lcdblk_bypass_shift)) {
516 DRM_ERROR("Failed to update sysreg for bypass setting.\n");
517 return;
518 }
519
520 /* TODO: When MIC is enabled for display path, the lcdblk_mic_bypass
521 * bit should be cleared.
522 */
523 if (driver_data->has_mic_bypass && ctx->sysreg &&
524 regmap_update_bits(ctx->sysreg,
525 driver_data->lcdblk_offset,
526 0x1 << driver_data->lcdblk_mic_bypass_shift,
527 0x1 << driver_data->lcdblk_mic_bypass_shift)) {
528 DRM_ERROR("Failed to update sysreg for bypass mic.\n");
529 return;
530 }
531
532 /* setup horizontal and vertical display size. */
533 val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
534 VIDTCON2_HOZVAL(mode->hdisplay - 1) |
535 VIDTCON2_LINEVAL_E(mode->vdisplay - 1) |
536 VIDTCON2_HOZVAL_E(mode->hdisplay - 1);
537 writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
538
539 fimd_setup_trigger(ctx);
540
541 /*
542 * fields of register with prefix '_F' would be updated
543 * at vsync(same as dma start)
544 */
545 val = ctx->vidcon0;
546 val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
547
548 if (ctx->driver_data->has_clksel)
549 val |= VIDCON0_CLKSEL_LCD;
550
551 clkdiv = fimd_calc_clkdiv(ctx, mode);
552 if (clkdiv > 1)
553 val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR;
554
555 writel(val, ctx->regs + VIDCON0);
556 }
557
558
559 static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win,
560 uint32_t pixel_format, int width)
561 {
562 unsigned long val;
563
564 val = WINCONx_ENWIN;
565
566 /*
567 * In case of s3c64xx, window 0 doesn't support alpha channel.
568 * So the request format is ARGB8888 then change it to XRGB8888.
569 */
570 if (ctx->driver_data->has_limited_fmt && !win) {
571 if (pixel_format == DRM_FORMAT_ARGB8888)
572 pixel_format = DRM_FORMAT_XRGB8888;
573 }
574
575 switch (pixel_format) {
576 case DRM_FORMAT_C8:
577 val |= WINCON0_BPPMODE_8BPP_PALETTE;
578 val |= WINCONx_BURSTLEN_8WORD;
579 val |= WINCONx_BYTSWP;
580 break;
581 case DRM_FORMAT_XRGB1555:
582 val |= WINCON0_BPPMODE_16BPP_1555;
583 val |= WINCONx_HAWSWP;
584 val |= WINCONx_BURSTLEN_16WORD;
585 break;
586 case DRM_FORMAT_RGB565:
587 val |= WINCON0_BPPMODE_16BPP_565;
588 val |= WINCONx_HAWSWP;
589 val |= WINCONx_BURSTLEN_16WORD;
590 break;
591 case DRM_FORMAT_XRGB8888:
592 val |= WINCON0_BPPMODE_24BPP_888;
593 val |= WINCONx_WSWP;
594 val |= WINCONx_BURSTLEN_16WORD;
595 break;
596 case DRM_FORMAT_ARGB8888:
597 val |= WINCON1_BPPMODE_25BPP_A1888
598 | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
599 val |= WINCONx_WSWP;
600 val |= WINCONx_BURSTLEN_16WORD;
601 break;
602 default:
603 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
604
605 val |= WINCON0_BPPMODE_24BPP_888;
606 val |= WINCONx_WSWP;
607 val |= WINCONx_BURSTLEN_16WORD;
608 break;
609 }
610
611 /*
612 * Setting dma-burst to 16Word causes permanent tearing for very small
613 * buffers, e.g. cursor buffer. Burst Mode switching which based on
614 * plane size is not recommended as plane size varies alot towards the
615 * end of the screen and rapid movement causes unstable DMA, but it is
616 * still better to change dma-burst than displaying garbage.
617 */
618
619 if (width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
620 val &= ~WINCONx_BURSTLEN_MASK;
621 val |= WINCONx_BURSTLEN_4WORD;
622 }
623
624 writel(val, ctx->regs + WINCON(win));
625
626 /* hardware window 0 doesn't support alpha channel. */
627 if (win != 0) {
628 /* OSD alpha */
629 val = VIDISD14C_ALPHA0_R(0xf) |
630 VIDISD14C_ALPHA0_G(0xf) |
631 VIDISD14C_ALPHA0_B(0xf) |
632 VIDISD14C_ALPHA1_R(0xf) |
633 VIDISD14C_ALPHA1_G(0xf) |
634 VIDISD14C_ALPHA1_B(0xf);
635
636 writel(val, ctx->regs + VIDOSD_C(win));
637
638 val = VIDW_ALPHA_R(0xf) | VIDW_ALPHA_G(0xf) |
639 VIDW_ALPHA_G(0xf);
640 writel(val, ctx->regs + VIDWnALPHA0(win));
641 writel(val, ctx->regs + VIDWnALPHA1(win));
642 }
643 }
644
645 static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win)
646 {
647 unsigned int keycon0 = 0, keycon1 = 0;
648
649 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
650 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
651
652 keycon1 = WxKEYCON1_COLVAL(0xffffffff);
653
654 writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
655 writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
656 }
657
658 /**
659 * shadow_protect_win() - disable updating values from shadow registers at vsync
660 *
661 * @win: window to protect registers for
662 * @protect: 1 to protect (disable updates)
663 */
664 static void fimd_shadow_protect_win(struct fimd_context *ctx,
665 unsigned int win, bool protect)
666 {
667 u32 reg, bits, val;
668
669 /*
670 * SHADOWCON/PRTCON register is used for enabling timing.
671 *
672 * for example, once only width value of a register is set,
673 * if the dma is started then fimd hardware could malfunction so
674 * with protect window setting, the register fields with prefix '_F'
675 * wouldn't be updated at vsync also but updated once unprotect window
676 * is set.
677 */
678
679 if (ctx->driver_data->has_shadowcon) {
680 reg = SHADOWCON;
681 bits = SHADOWCON_WINx_PROTECT(win);
682 } else {
683 reg = PRTCON;
684 bits = PRTCON_PROTECT;
685 }
686
687 val = readl(ctx->regs + reg);
688 if (protect)
689 val |= bits;
690 else
691 val &= ~bits;
692 writel(val, ctx->regs + reg);
693 }
694
695 static void fimd_atomic_begin(struct exynos_drm_crtc *crtc)
696 {
697 struct fimd_context *ctx = crtc->ctx;
698 int i;
699
700 if (ctx->suspended)
701 return;
702
703 for (i = 0; i < WINDOWS_NR; i++)
704 fimd_shadow_protect_win(ctx, i, true);
705 }
706
707 static void fimd_atomic_flush(struct exynos_drm_crtc *crtc)
708 {
709 struct fimd_context *ctx = crtc->ctx;
710 int i;
711
712 if (ctx->suspended)
713 return;
714
715 for (i = 0; i < WINDOWS_NR; i++)
716 fimd_shadow_protect_win(ctx, i, false);
717 }
718
719 static void fimd_update_plane(struct exynos_drm_crtc *crtc,
720 struct exynos_drm_plane *plane)
721 {
722 struct exynos_drm_plane_state *state =
723 to_exynos_plane_state(plane->base.state);
724 struct fimd_context *ctx = crtc->ctx;
725 struct drm_framebuffer *fb = state->base.fb;
726 dma_addr_t dma_addr;
727 unsigned long val, size, offset;
728 unsigned int last_x, last_y, buf_offsize, line_size;
729 unsigned int win = plane->index;
730 unsigned int bpp = fb->bits_per_pixel >> 3;
731 unsigned int pitch = fb->pitches[0];
732
733 if (ctx->suspended)
734 return;
735
736 offset = state->src.x * bpp;
737 offset += state->src.y * pitch;
738
739 /* buffer start address */
740 dma_addr = exynos_drm_fb_dma_addr(fb, 0) + offset;
741 val = (unsigned long)dma_addr;
742 writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
743
744 /* buffer end address */
745 size = pitch * state->crtc.h;
746 val = (unsigned long)(dma_addr + size);
747 writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
748
749 DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
750 (unsigned long)dma_addr, val, size);
751 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
752 state->crtc.w, state->crtc.h);
753
754 /* buffer size */
755 buf_offsize = pitch - (state->crtc.w * bpp);
756 line_size = state->crtc.w * bpp;
757 val = VIDW_BUF_SIZE_OFFSET(buf_offsize) |
758 VIDW_BUF_SIZE_PAGEWIDTH(line_size) |
759 VIDW_BUF_SIZE_OFFSET_E(buf_offsize) |
760 VIDW_BUF_SIZE_PAGEWIDTH_E(line_size);
761 writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
762
763 /* OSD position */
764 val = VIDOSDxA_TOPLEFT_X(state->crtc.x) |
765 VIDOSDxA_TOPLEFT_Y(state->crtc.y) |
766 VIDOSDxA_TOPLEFT_X_E(state->crtc.x) |
767 VIDOSDxA_TOPLEFT_Y_E(state->crtc.y);
768 writel(val, ctx->regs + VIDOSD_A(win));
769
770 last_x = state->crtc.x + state->crtc.w;
771 if (last_x)
772 last_x--;
773 last_y = state->crtc.y + state->crtc.h;
774 if (last_y)
775 last_y--;
776
777 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
778 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);
779
780 writel(val, ctx->regs + VIDOSD_B(win));
781
782 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
783 state->crtc.x, state->crtc.y, last_x, last_y);
784
785 /* OSD size */
786 if (win != 3 && win != 4) {
787 u32 offset = VIDOSD_D(win);
788 if (win == 0)
789 offset = VIDOSD_C(win);
790 val = state->crtc.w * state->crtc.h;
791 writel(val, ctx->regs + offset);
792
793 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
794 }
795
796 fimd_win_set_pixfmt(ctx, win, fb->pixel_format, state->src.w);
797
798 /* hardware window 0 doesn't support color key. */
799 if (win != 0)
800 fimd_win_set_colkey(ctx, win);
801
802 fimd_enable_video_output(ctx, win, true);
803
804 if (ctx->driver_data->has_shadowcon)
805 fimd_enable_shadow_channel_path(ctx, win, true);
806
807 if (ctx->i80_if)
808 atomic_set(&ctx->win_updated, 1);
809 }
810
811 static void fimd_disable_plane(struct exynos_drm_crtc *crtc,
812 struct exynos_drm_plane *plane)
813 {
814 struct fimd_context *ctx = crtc->ctx;
815 unsigned int win = plane->index;
816
817 if (ctx->suspended)
818 return;
819
820 fimd_enable_video_output(ctx, win, false);
821
822 if (ctx->driver_data->has_shadowcon)
823 fimd_enable_shadow_channel_path(ctx, win, false);
824 }
825
826 static void fimd_enable(struct exynos_drm_crtc *crtc)
827 {
828 struct fimd_context *ctx = crtc->ctx;
829
830 if (!ctx->suspended)
831 return;
832
833 ctx->suspended = false;
834
835 pm_runtime_get_sync(ctx->dev);
836
837 /* if vblank was enabled status, enable it again. */
838 if (test_and_clear_bit(0, &ctx->irq_flags))
839 fimd_enable_vblank(ctx->crtc);
840
841 fimd_commit(ctx->crtc);
842 }
843
844 static void fimd_disable(struct exynos_drm_crtc *crtc)
845 {
846 struct fimd_context *ctx = crtc->ctx;
847 int i;
848
849 if (ctx->suspended)
850 return;
851
852 /*
853 * We need to make sure that all windows are disabled before we
854 * suspend that connector. Otherwise we might try to scan from
855 * a destroyed buffer later.
856 */
857 for (i = 0; i < WINDOWS_NR; i++)
858 fimd_disable_plane(crtc, &ctx->planes[i]);
859
860 fimd_enable_vblank(crtc);
861 fimd_wait_for_vblank(crtc);
862 fimd_disable_vblank(crtc);
863
864 writel(0, ctx->regs + VIDCON0);
865
866 pm_runtime_put_sync(ctx->dev);
867 ctx->suspended = true;
868 }
869
870 static void fimd_trigger(struct device *dev)
871 {
872 struct fimd_context *ctx = dev_get_drvdata(dev);
873 const struct fimd_driver_data *driver_data = ctx->driver_data;
874 void *timing_base = ctx->regs + driver_data->timing_base;
875 u32 reg;
876
877 /*
878 * Skips triggering if in triggering state, because multiple triggering
879 * requests can cause panel reset.
880 */
881 if (atomic_read(&ctx->triggering))
882 return;
883
884 /* Enters triggering mode */
885 atomic_set(&ctx->triggering, 1);
886
887 reg = readl(timing_base + TRIGCON);
888 reg |= (TRGMODE_ENABLE | SWTRGCMD_ENABLE);
889 writel(reg, timing_base + TRIGCON);
890
891 /*
892 * Exits triggering mode if vblank is not enabled yet, because when the
893 * VIDINTCON0 register is not set, it can not exit from triggering mode.
894 */
895 if (!test_bit(0, &ctx->irq_flags))
896 atomic_set(&ctx->triggering, 0);
897 }
898
899 static void fimd_te_handler(struct exynos_drm_crtc *crtc)
900 {
901 struct fimd_context *ctx = crtc->ctx;
902 u32 trg_type = ctx->driver_data->trg_type;
903
904 /* Checks the crtc is detached already from encoder */
905 if (ctx->pipe < 0 || !ctx->drm_dev)
906 return;
907
908 if (trg_type == I80_HW_TRG)
909 goto out;
910
911 /*
912 * If there is a page flip request, triggers and handles the page flip
913 * event so that current fb can be updated into panel GRAM.
914 */
915 if (atomic_add_unless(&ctx->win_updated, -1, 0))
916 fimd_trigger(ctx->dev);
917
918 out:
919 /* Wakes up vsync event queue */
920 if (atomic_read(&ctx->wait_vsync_event)) {
921 atomic_set(&ctx->wait_vsync_event, 0);
922 wake_up(&ctx->wait_vsync_queue);
923 }
924
925 if (test_bit(0, &ctx->irq_flags))
926 drm_crtc_handle_vblank(&ctx->crtc->base);
927 }
928
929 static void fimd_dp_clock_enable(struct exynos_drm_clk *clk, bool enable)
930 {
931 struct fimd_context *ctx = container_of(clk, struct fimd_context,
932 dp_clk);
933 u32 val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE;
934 writel(val, ctx->regs + DP_MIE_CLKCON);
935 }
936
937 static const struct exynos_drm_crtc_ops fimd_crtc_ops = {
938 .enable = fimd_enable,
939 .disable = fimd_disable,
940 .commit = fimd_commit,
941 .enable_vblank = fimd_enable_vblank,
942 .disable_vblank = fimd_disable_vblank,
943 .atomic_begin = fimd_atomic_begin,
944 .update_plane = fimd_update_plane,
945 .disable_plane = fimd_disable_plane,
946 .atomic_flush = fimd_atomic_flush,
947 .te_handler = fimd_te_handler,
948 };
949
950 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
951 {
952 struct fimd_context *ctx = (struct fimd_context *)dev_id;
953 u32 val, clear_bit, start, start_s;
954 int win;
955
956 val = readl(ctx->regs + VIDINTCON1);
957
958 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
959 if (val & clear_bit)
960 writel(clear_bit, ctx->regs + VIDINTCON1);
961
962 /* check the crtc is detached already from encoder */
963 if (ctx->pipe < 0 || !ctx->drm_dev)
964 goto out;
965
966 if (!ctx->i80_if)
967 drm_crtc_handle_vblank(&ctx->crtc->base);
968
969 for (win = 0 ; win < WINDOWS_NR ; win++) {
970 struct exynos_drm_plane *plane = &ctx->planes[win];
971
972 if (!plane->pending_fb)
973 continue;
974
975 start = readl(ctx->regs + VIDWx_BUF_START(win, 0));
976 start_s = readl(ctx->regs + VIDWx_BUF_START_S(win, 0));
977 if (start == start_s)
978 exynos_drm_crtc_finish_update(ctx->crtc, plane);
979 }
980
981 if (ctx->i80_if) {
982 /* Exits triggering mode */
983 atomic_set(&ctx->triggering, 0);
984 } else {
985 /* set wait vsync event to zero and wake up queue. */
986 if (atomic_read(&ctx->wait_vsync_event)) {
987 atomic_set(&ctx->wait_vsync_event, 0);
988 wake_up(&ctx->wait_vsync_queue);
989 }
990 }
991
992 out:
993 return IRQ_HANDLED;
994 }
995
996 static int fimd_bind(struct device *dev, struct device *master, void *data)
997 {
998 struct fimd_context *ctx = dev_get_drvdata(dev);
999 struct drm_device *drm_dev = data;
1000 struct exynos_drm_private *priv = drm_dev->dev_private;
1001 struct exynos_drm_plane *exynos_plane;
1002 unsigned int i;
1003 int ret;
1004
1005 ctx->drm_dev = drm_dev;
1006 ctx->pipe = priv->pipe++;
1007
1008 for (i = 0; i < WINDOWS_NR; i++) {
1009 ctx->configs[i].pixel_formats = fimd_formats;
1010 ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_formats);
1011 ctx->configs[i].zpos = i;
1012 ctx->configs[i].type = fimd_win_types[i];
1013 ret = exynos_plane_init(drm_dev, &ctx->planes[i], i,
1014 1 << ctx->pipe, &ctx->configs[i]);
1015 if (ret)
1016 return ret;
1017 }
1018
1019 exynos_plane = &ctx->planes[DEFAULT_WIN];
1020 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
1021 ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD,
1022 &fimd_crtc_ops, ctx);
1023 if (IS_ERR(ctx->crtc))
1024 return PTR_ERR(ctx->crtc);
1025
1026 if (ctx->driver_data->has_dp_clk) {
1027 ctx->dp_clk.enable = fimd_dp_clock_enable;
1028 ctx->crtc->pipe_clk = &ctx->dp_clk;
1029 }
1030
1031 if (ctx->encoder)
1032 exynos_dpi_bind(drm_dev, ctx->encoder);
1033
1034 if (is_drm_iommu_supported(drm_dev))
1035 fimd_clear_channels(ctx->crtc);
1036
1037 ret = drm_iommu_attach_device(drm_dev, dev);
1038 if (ret)
1039 priv->pipe--;
1040
1041 return ret;
1042 }
1043
1044 static void fimd_unbind(struct device *dev, struct device *master,
1045 void *data)
1046 {
1047 struct fimd_context *ctx = dev_get_drvdata(dev);
1048
1049 fimd_disable(ctx->crtc);
1050
1051 drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
1052
1053 if (ctx->encoder)
1054 exynos_dpi_remove(ctx->encoder);
1055 }
1056
1057 static const struct component_ops fimd_component_ops = {
1058 .bind = fimd_bind,
1059 .unbind = fimd_unbind,
1060 };
1061
1062 static int fimd_probe(struct platform_device *pdev)
1063 {
1064 struct device *dev = &pdev->dev;
1065 struct fimd_context *ctx;
1066 struct device_node *i80_if_timings;
1067 struct resource *res;
1068 int ret;
1069
1070 if (!dev->of_node)
1071 return -ENODEV;
1072
1073 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1074 if (!ctx)
1075 return -ENOMEM;
1076
1077 ctx->dev = dev;
1078 ctx->suspended = true;
1079 ctx->driver_data = of_device_get_match_data(dev);
1080
1081 if (of_property_read_bool(dev->of_node, "samsung,invert-vden"))
1082 ctx->vidcon1 |= VIDCON1_INV_VDEN;
1083 if (of_property_read_bool(dev->of_node, "samsung,invert-vclk"))
1084 ctx->vidcon1 |= VIDCON1_INV_VCLK;
1085
1086 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
1087 if (i80_if_timings) {
1088 u32 val;
1089
1090 ctx->i80_if = true;
1091
1092 if (ctx->driver_data->has_vidoutcon)
1093 ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0;
1094 else
1095 ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0;
1096 /*
1097 * The user manual describes that this "DSI_EN" bit is required
1098 * to enable I80 24-bit data interface.
1099 */
1100 ctx->vidcon0 |= VIDCON0_DSI_EN;
1101
1102 if (of_property_read_u32(i80_if_timings, "cs-setup", &val))
1103 val = 0;
1104 ctx->i80ifcon = LCD_CS_SETUP(val);
1105 if (of_property_read_u32(i80_if_timings, "wr-setup", &val))
1106 val = 0;
1107 ctx->i80ifcon |= LCD_WR_SETUP(val);
1108 if (of_property_read_u32(i80_if_timings, "wr-active", &val))
1109 val = 1;
1110 ctx->i80ifcon |= LCD_WR_ACTIVE(val);
1111 if (of_property_read_u32(i80_if_timings, "wr-hold", &val))
1112 val = 0;
1113 ctx->i80ifcon |= LCD_WR_HOLD(val);
1114 }
1115 of_node_put(i80_if_timings);
1116
1117 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1118 "samsung,sysreg");
1119 if (IS_ERR(ctx->sysreg)) {
1120 dev_warn(dev, "failed to get system register.\n");
1121 ctx->sysreg = NULL;
1122 }
1123
1124 ctx->bus_clk = devm_clk_get(dev, "fimd");
1125 if (IS_ERR(ctx->bus_clk)) {
1126 dev_err(dev, "failed to get bus clock\n");
1127 return PTR_ERR(ctx->bus_clk);
1128 }
1129
1130 ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
1131 if (IS_ERR(ctx->lcd_clk)) {
1132 dev_err(dev, "failed to get lcd clock\n");
1133 return PTR_ERR(ctx->lcd_clk);
1134 }
1135
1136 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1137
1138 ctx->regs = devm_ioremap_resource(dev, res);
1139 if (IS_ERR(ctx->regs))
1140 return PTR_ERR(ctx->regs);
1141
1142 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1143 ctx->i80_if ? "lcd_sys" : "vsync");
1144 if (!res) {
1145 dev_err(dev, "irq request failed.\n");
1146 return -ENXIO;
1147 }
1148
1149 ret = devm_request_irq(dev, res->start, fimd_irq_handler,
1150 0, "drm_fimd", ctx);
1151 if (ret) {
1152 dev_err(dev, "irq request failed.\n");
1153 return ret;
1154 }
1155
1156 init_waitqueue_head(&ctx->wait_vsync_queue);
1157 atomic_set(&ctx->wait_vsync_event, 0);
1158
1159 platform_set_drvdata(pdev, ctx);
1160
1161 ctx->encoder = exynos_dpi_probe(dev);
1162 if (IS_ERR(ctx->encoder))
1163 return PTR_ERR(ctx->encoder);
1164
1165 pm_runtime_enable(dev);
1166
1167 ret = component_add(dev, &fimd_component_ops);
1168 if (ret)
1169 goto err_disable_pm_runtime;
1170
1171 return ret;
1172
1173 err_disable_pm_runtime:
1174 pm_runtime_disable(dev);
1175
1176 return ret;
1177 }
1178
1179 static int fimd_remove(struct platform_device *pdev)
1180 {
1181 pm_runtime_disable(&pdev->dev);
1182
1183 component_del(&pdev->dev, &fimd_component_ops);
1184
1185 return 0;
1186 }
1187
1188 #ifdef CONFIG_PM
1189 static int exynos_fimd_suspend(struct device *dev)
1190 {
1191 struct fimd_context *ctx = dev_get_drvdata(dev);
1192
1193 clk_disable_unprepare(ctx->lcd_clk);
1194 clk_disable_unprepare(ctx->bus_clk);
1195
1196 return 0;
1197 }
1198
1199 static int exynos_fimd_resume(struct device *dev)
1200 {
1201 struct fimd_context *ctx = dev_get_drvdata(dev);
1202 int ret;
1203
1204 ret = clk_prepare_enable(ctx->bus_clk);
1205 if (ret < 0) {
1206 DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret);
1207 return ret;
1208 }
1209
1210 ret = clk_prepare_enable(ctx->lcd_clk);
1211 if (ret < 0) {
1212 DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret);
1213 return ret;
1214 }
1215
1216 return 0;
1217 }
1218 #endif
1219
1220 static const struct dev_pm_ops exynos_fimd_pm_ops = {
1221 SET_RUNTIME_PM_OPS(exynos_fimd_suspend, exynos_fimd_resume, NULL)
1222 };
1223
1224 struct platform_driver fimd_driver = {
1225 .probe = fimd_probe,
1226 .remove = fimd_remove,
1227 .driver = {
1228 .name = "exynos4-fb",
1229 .owner = THIS_MODULE,
1230 .pm = &exynos_fimd_pm_ops,
1231 .of_match_table = fimd_driver_dt_match,
1232 },
1233 };
Linux kernel - Deliverables
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