3 * Copyright (C) 2011 Samsung Electronics Co.Ltd
5 * Joonyoung Shim <jy0922.shim@samsung.com>
6 * Inki Dae <inki.dae@samsung.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/platform_device.h>
18 #include <linux/clk.h>
20 #include <linux/of_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/component.h>
23 #include <linux/mfd/syscon.h>
24 #include <linux/regmap.h>
26 #include <video/of_display_timing.h>
27 #include <video/of_videomode.h>
28 #include <video/samsung_fimd.h>
29 #include <drm/exynos_drm.h>
31 #include "exynos_drm_drv.h"
32 #include "exynos_drm_fb.h"
33 #include "exynos_drm_fbdev.h"
34 #include "exynos_drm_crtc.h"
35 #include "exynos_drm_plane.h"
36 #include "exynos_drm_iommu.h"
39 * FIMD stands for Fully Interactive Mobile Display and
40 * as a display controller, it transfers contents drawn on memory
41 * to a LCD Panel through Display Interfaces such as RGB or
45 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
47 /* position control register for hardware window 0, 2 ~ 4.*/
48 #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
49 #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
51 * size control register for hardware windows 0 and alpha control register
52 * for hardware windows 1 ~ 4
54 #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16)
55 /* size control register for hardware windows 1 ~ 2. */
56 #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
58 #define VIDWnALPHA0(win) (VIDW_ALPHA + 0x00 + (win) * 8)
59 #define VIDWnALPHA1(win) (VIDW_ALPHA + 0x04 + (win) * 8)
61 #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
62 #define VIDWx_BUF_START_S(win, buf) (VIDW_BUF_START_S(buf) + (win) * 8)
63 #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8)
64 #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
66 /* color key control register for hardware window 1 ~ 4. */
67 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8))
68 /* color key value register for hardware window 1 ~ 4. */
69 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
71 /* I80 / RGB trigger control register */
73 #define TRGMODE_I80_RGB_ENABLE_I80 (1 << 0)
74 #define SWTRGCMD_I80_RGB_ENABLE (1 << 1)
76 /* display mode change control register except exynos4 */
77 #define VIDOUT_CON 0x000
78 #define VIDOUT_CON_F_I80_LDI0 (0x2 << 8)
80 /* I80 interface control for main LDI register */
81 #define I80IFCONFAx(x) (0x1B0 + (x) * 4)
82 #define I80IFCONFBx(x) (0x1B8 + (x) * 4)
83 #define LCD_CS_SETUP(x) ((x) << 16)
84 #define LCD_WR_SETUP(x) ((x) << 12)
85 #define LCD_WR_ACTIVE(x) ((x) << 8)
86 #define LCD_WR_HOLD(x) ((x) << 4)
87 #define I80IFEN_ENABLE (1 << 0)
89 /* FIMD has totally five hardware windows. */
93 struct fimd_driver_data
{
94 unsigned int timing_base
;
95 unsigned int lcdblk_offset
;
96 unsigned int lcdblk_vt_shift
;
97 unsigned int lcdblk_bypass_shift
;
99 unsigned int has_shadowcon
:1;
100 unsigned int has_clksel
:1;
101 unsigned int has_limited_fmt
:1;
102 unsigned int has_vidoutcon
:1;
103 unsigned int has_vtsel
:1;
106 static struct fimd_driver_data s3c64xx_fimd_driver_data
= {
109 .has_limited_fmt
= 1,
112 static struct fimd_driver_data exynos3_fimd_driver_data
= {
113 .timing_base
= 0x20000,
114 .lcdblk_offset
= 0x210,
115 .lcdblk_bypass_shift
= 1,
120 static struct fimd_driver_data exynos4_fimd_driver_data
= {
122 .lcdblk_offset
= 0x210,
123 .lcdblk_vt_shift
= 10,
124 .lcdblk_bypass_shift
= 1,
129 static struct fimd_driver_data exynos4415_fimd_driver_data
= {
130 .timing_base
= 0x20000,
131 .lcdblk_offset
= 0x210,
132 .lcdblk_vt_shift
= 10,
133 .lcdblk_bypass_shift
= 1,
139 static struct fimd_driver_data exynos5_fimd_driver_data
= {
140 .timing_base
= 0x20000,
141 .lcdblk_offset
= 0x214,
142 .lcdblk_vt_shift
= 24,
143 .lcdblk_bypass_shift
= 15,
149 struct fimd_context
{
151 struct drm_device
*drm_dev
;
152 struct exynos_drm_crtc
*crtc
;
153 struct exynos_drm_plane planes
[WINDOWS_NR
];
157 struct regmap
*sysreg
;
158 unsigned long irq_flags
;
166 wait_queue_head_t wait_vsync_queue
;
167 atomic_t wait_vsync_event
;
168 atomic_t win_updated
;
171 struct exynos_drm_panel_info panel
;
172 struct fimd_driver_data
*driver_data
;
173 struct drm_encoder
*encoder
;
176 static const struct of_device_id fimd_driver_dt_match
[] = {
177 { .compatible
= "samsung,s3c6400-fimd",
178 .data
= &s3c64xx_fimd_driver_data
},
179 { .compatible
= "samsung,exynos3250-fimd",
180 .data
= &exynos3_fimd_driver_data
},
181 { .compatible
= "samsung,exynos4210-fimd",
182 .data
= &exynos4_fimd_driver_data
},
183 { .compatible
= "samsung,exynos4415-fimd",
184 .data
= &exynos4415_fimd_driver_data
},
185 { .compatible
= "samsung,exynos5250-fimd",
186 .data
= &exynos5_fimd_driver_data
},
189 MODULE_DEVICE_TABLE(of
, fimd_driver_dt_match
);
191 static const uint32_t fimd_formats
[] = {
199 static inline struct fimd_driver_data
*drm_fimd_get_driver_data(
200 struct platform_device
*pdev
)
202 const struct of_device_id
*of_id
=
203 of_match_device(fimd_driver_dt_match
, &pdev
->dev
);
205 return (struct fimd_driver_data
*)of_id
->data
;
208 static int fimd_enable_vblank(struct exynos_drm_crtc
*crtc
)
210 struct fimd_context
*ctx
= crtc
->ctx
;
216 if (!test_and_set_bit(0, &ctx
->irq_flags
)) {
217 val
= readl(ctx
->regs
+ VIDINTCON0
);
219 val
|= VIDINTCON0_INT_ENABLE
;
222 val
|= VIDINTCON0_INT_I80IFDONE
;
223 val
|= VIDINTCON0_INT_SYSMAINCON
;
224 val
&= ~VIDINTCON0_INT_SYSSUBCON
;
226 val
|= VIDINTCON0_INT_FRAME
;
228 val
&= ~VIDINTCON0_FRAMESEL0_MASK
;
229 val
|= VIDINTCON0_FRAMESEL0_VSYNC
;
230 val
&= ~VIDINTCON0_FRAMESEL1_MASK
;
231 val
|= VIDINTCON0_FRAMESEL1_NONE
;
234 writel(val
, ctx
->regs
+ VIDINTCON0
);
240 static void fimd_disable_vblank(struct exynos_drm_crtc
*crtc
)
242 struct fimd_context
*ctx
= crtc
->ctx
;
248 if (test_and_clear_bit(0, &ctx
->irq_flags
)) {
249 val
= readl(ctx
->regs
+ VIDINTCON0
);
251 val
&= ~VIDINTCON0_INT_ENABLE
;
254 val
&= ~VIDINTCON0_INT_I80IFDONE
;
255 val
&= ~VIDINTCON0_INT_SYSMAINCON
;
256 val
&= ~VIDINTCON0_INT_SYSSUBCON
;
258 val
&= ~VIDINTCON0_INT_FRAME
;
260 writel(val
, ctx
->regs
+ VIDINTCON0
);
264 static void fimd_wait_for_vblank(struct exynos_drm_crtc
*crtc
)
266 struct fimd_context
*ctx
= crtc
->ctx
;
271 atomic_set(&ctx
->wait_vsync_event
, 1);
274 * wait for FIMD to signal VSYNC interrupt or return after
275 * timeout which is set to 50ms (refresh rate of 20).
277 if (!wait_event_timeout(ctx
->wait_vsync_queue
,
278 !atomic_read(&ctx
->wait_vsync_event
),
280 DRM_DEBUG_KMS("vblank wait timed out.\n");
283 static void fimd_enable_video_output(struct fimd_context
*ctx
, unsigned int win
,
286 u32 val
= readl(ctx
->regs
+ WINCON(win
));
289 val
|= WINCONx_ENWIN
;
291 val
&= ~WINCONx_ENWIN
;
293 writel(val
, ctx
->regs
+ WINCON(win
));
296 static void fimd_enable_shadow_channel_path(struct fimd_context
*ctx
,
300 u32 val
= readl(ctx
->regs
+ SHADOWCON
);
303 val
|= SHADOWCON_CHx_ENABLE(win
);
305 val
&= ~SHADOWCON_CHx_ENABLE(win
);
307 writel(val
, ctx
->regs
+ SHADOWCON
);
310 static void fimd_clear_channels(struct exynos_drm_crtc
*crtc
)
312 struct fimd_context
*ctx
= crtc
->ctx
;
313 unsigned int win
, ch_enabled
= 0;
315 DRM_DEBUG_KMS("%s\n", __FILE__
);
317 /* Hardware is in unknown state, so ensure it gets enabled properly */
318 pm_runtime_get_sync(ctx
->dev
);
320 clk_prepare_enable(ctx
->bus_clk
);
321 clk_prepare_enable(ctx
->lcd_clk
);
323 /* Check if any channel is enabled. */
324 for (win
= 0; win
< WINDOWS_NR
; win
++) {
325 u32 val
= readl(ctx
->regs
+ WINCON(win
));
327 if (val
& WINCONx_ENWIN
) {
328 fimd_enable_video_output(ctx
, win
, false);
330 if (ctx
->driver_data
->has_shadowcon
)
331 fimd_enable_shadow_channel_path(ctx
, win
,
338 /* Wait for vsync, as disable channel takes effect at next vsync */
340 int pipe
= ctx
->pipe
;
342 /* ensure that vblank interrupt won't be reported to core */
343 ctx
->suspended
= false;
346 fimd_enable_vblank(ctx
->crtc
);
347 fimd_wait_for_vblank(ctx
->crtc
);
348 fimd_disable_vblank(ctx
->crtc
);
350 ctx
->suspended
= true;
354 clk_disable_unprepare(ctx
->lcd_clk
);
355 clk_disable_unprepare(ctx
->bus_clk
);
357 pm_runtime_put(ctx
->dev
);
360 static u32
fimd_calc_clkdiv(struct fimd_context
*ctx
,
361 const struct drm_display_mode
*mode
)
363 unsigned long ideal_clk
= mode
->htotal
* mode
->vtotal
* mode
->vrefresh
;
368 * The frame done interrupt should be occurred prior to the
374 /* Find the clock divider value that gets us closest to ideal_clk */
375 clkdiv
= DIV_ROUND_UP(clk_get_rate(ctx
->lcd_clk
), ideal_clk
);
377 return (clkdiv
< 0x100) ? clkdiv
: 0xff;
380 static void fimd_commit(struct exynos_drm_crtc
*crtc
)
382 struct fimd_context
*ctx
= crtc
->ctx
;
383 struct drm_display_mode
*mode
= &crtc
->base
.state
->adjusted_mode
;
384 struct fimd_driver_data
*driver_data
= ctx
->driver_data
;
385 void *timing_base
= ctx
->regs
+ driver_data
->timing_base
;
391 /* nothing to do if we haven't set the mode yet */
392 if (mode
->htotal
== 0 || mode
->vtotal
== 0)
396 val
= ctx
->i80ifcon
| I80IFEN_ENABLE
;
397 writel(val
, timing_base
+ I80IFCONFAx(0));
399 /* disable auto frame rate */
400 writel(0, timing_base
+ I80IFCONFBx(0));
402 /* set video type selection to I80 interface */
403 if (driver_data
->has_vtsel
&& ctx
->sysreg
&&
404 regmap_update_bits(ctx
->sysreg
,
405 driver_data
->lcdblk_offset
,
406 0x3 << driver_data
->lcdblk_vt_shift
,
407 0x1 << driver_data
->lcdblk_vt_shift
)) {
408 DRM_ERROR("Failed to update sysreg for I80 i/f.\n");
412 int vsync_len
, vbpd
, vfpd
, hsync_len
, hbpd
, hfpd
;
415 /* setup polarity values */
416 vidcon1
= ctx
->vidcon1
;
417 if (mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
418 vidcon1
|= VIDCON1_INV_VSYNC
;
419 if (mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
420 vidcon1
|= VIDCON1_INV_HSYNC
;
421 writel(vidcon1
, ctx
->regs
+ driver_data
->timing_base
+ VIDCON1
);
423 /* setup vertical timing values. */
424 vsync_len
= mode
->crtc_vsync_end
- mode
->crtc_vsync_start
;
425 vbpd
= mode
->crtc_vtotal
- mode
->crtc_vsync_end
;
426 vfpd
= mode
->crtc_vsync_start
- mode
->crtc_vdisplay
;
428 val
= VIDTCON0_VBPD(vbpd
- 1) |
429 VIDTCON0_VFPD(vfpd
- 1) |
430 VIDTCON0_VSPW(vsync_len
- 1);
431 writel(val
, ctx
->regs
+ driver_data
->timing_base
+ VIDTCON0
);
433 /* setup horizontal timing values. */
434 hsync_len
= mode
->crtc_hsync_end
- mode
->crtc_hsync_start
;
435 hbpd
= mode
->crtc_htotal
- mode
->crtc_hsync_end
;
436 hfpd
= mode
->crtc_hsync_start
- mode
->crtc_hdisplay
;
438 val
= VIDTCON1_HBPD(hbpd
- 1) |
439 VIDTCON1_HFPD(hfpd
- 1) |
440 VIDTCON1_HSPW(hsync_len
- 1);
441 writel(val
, ctx
->regs
+ driver_data
->timing_base
+ VIDTCON1
);
444 if (driver_data
->has_vidoutcon
)
445 writel(ctx
->vidout_con
, timing_base
+ VIDOUT_CON
);
447 /* set bypass selection */
448 if (ctx
->sysreg
&& regmap_update_bits(ctx
->sysreg
,
449 driver_data
->lcdblk_offset
,
450 0x1 << driver_data
->lcdblk_bypass_shift
,
451 0x1 << driver_data
->lcdblk_bypass_shift
)) {
452 DRM_ERROR("Failed to update sysreg for bypass setting.\n");
456 /* setup horizontal and vertical display size. */
457 val
= VIDTCON2_LINEVAL(mode
->vdisplay
- 1) |
458 VIDTCON2_HOZVAL(mode
->hdisplay
- 1) |
459 VIDTCON2_LINEVAL_E(mode
->vdisplay
- 1) |
460 VIDTCON2_HOZVAL_E(mode
->hdisplay
- 1);
461 writel(val
, ctx
->regs
+ driver_data
->timing_base
+ VIDTCON2
);
464 * fields of register with prefix '_F' would be updated
465 * at vsync(same as dma start)
468 val
|= VIDCON0_ENVID
| VIDCON0_ENVID_F
;
470 if (ctx
->driver_data
->has_clksel
)
471 val
|= VIDCON0_CLKSEL_LCD
;
473 clkdiv
= fimd_calc_clkdiv(ctx
, mode
);
475 val
|= VIDCON0_CLKVAL_F(clkdiv
- 1) | VIDCON0_CLKDIR
;
477 writel(val
, ctx
->regs
+ VIDCON0
);
481 static void fimd_win_set_pixfmt(struct fimd_context
*ctx
, unsigned int win
,
482 struct drm_framebuffer
*fb
)
489 * In case of s3c64xx, window 0 doesn't support alpha channel.
490 * So the request format is ARGB8888 then change it to XRGB8888.
492 if (ctx
->driver_data
->has_limited_fmt
&& !win
) {
493 if (fb
->pixel_format
== DRM_FORMAT_ARGB8888
)
494 fb
->pixel_format
= DRM_FORMAT_XRGB8888
;
497 switch (fb
->pixel_format
) {
499 val
|= WINCON0_BPPMODE_8BPP_PALETTE
;
500 val
|= WINCONx_BURSTLEN_8WORD
;
501 val
|= WINCONx_BYTSWP
;
503 case DRM_FORMAT_XRGB1555
:
504 val
|= WINCON0_BPPMODE_16BPP_1555
;
505 val
|= WINCONx_HAWSWP
;
506 val
|= WINCONx_BURSTLEN_16WORD
;
508 case DRM_FORMAT_RGB565
:
509 val
|= WINCON0_BPPMODE_16BPP_565
;
510 val
|= WINCONx_HAWSWP
;
511 val
|= WINCONx_BURSTLEN_16WORD
;
513 case DRM_FORMAT_XRGB8888
:
514 val
|= WINCON0_BPPMODE_24BPP_888
;
516 val
|= WINCONx_BURSTLEN_16WORD
;
518 case DRM_FORMAT_ARGB8888
:
519 val
|= WINCON1_BPPMODE_25BPP_A1888
520 | WINCON1_BLD_PIX
| WINCON1_ALPHA_SEL
;
522 val
|= WINCONx_BURSTLEN_16WORD
;
525 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
527 val
|= WINCON0_BPPMODE_24BPP_888
;
529 val
|= WINCONx_BURSTLEN_16WORD
;
533 DRM_DEBUG_KMS("bpp = %d\n", fb
->bits_per_pixel
);
536 * In case of exynos, setting dma-burst to 16Word causes permanent
537 * tearing for very small buffers, e.g. cursor buffer. Burst Mode
538 * switching which is based on plane size is not recommended as
539 * plane size varies alot towards the end of the screen and rapid
540 * movement causes unstable DMA which results into iommu crash/tear.
543 if (fb
->width
< MIN_FB_WIDTH_FOR_16WORD_BURST
) {
544 val
&= ~WINCONx_BURSTLEN_MASK
;
545 val
|= WINCONx_BURSTLEN_4WORD
;
548 writel(val
, ctx
->regs
+ WINCON(win
));
550 /* hardware window 0 doesn't support alpha channel. */
553 val
= VIDISD14C_ALPHA0_R(0xf) |
554 VIDISD14C_ALPHA0_G(0xf) |
555 VIDISD14C_ALPHA0_B(0xf) |
556 VIDISD14C_ALPHA1_R(0xf) |
557 VIDISD14C_ALPHA1_G(0xf) |
558 VIDISD14C_ALPHA1_B(0xf);
560 writel(val
, ctx
->regs
+ VIDOSD_C(win
));
562 val
= VIDW_ALPHA_R(0xf) | VIDW_ALPHA_G(0xf) |
564 writel(val
, ctx
->regs
+ VIDWnALPHA0(win
));
565 writel(val
, ctx
->regs
+ VIDWnALPHA1(win
));
569 static void fimd_win_set_colkey(struct fimd_context
*ctx
, unsigned int win
)
571 unsigned int keycon0
= 0, keycon1
= 0;
573 keycon0
= ~(WxKEYCON0_KEYBL_EN
| WxKEYCON0_KEYEN_F
|
574 WxKEYCON0_DIRCON
) | WxKEYCON0_COMPKEY(0);
576 keycon1
= WxKEYCON1_COLVAL(0xffffffff);
578 writel(keycon0
, ctx
->regs
+ WKEYCON0_BASE(win
));
579 writel(keycon1
, ctx
->regs
+ WKEYCON1_BASE(win
));
583 * shadow_protect_win() - disable updating values from shadow registers at vsync
585 * @win: window to protect registers for
586 * @protect: 1 to protect (disable updates)
588 static void fimd_shadow_protect_win(struct fimd_context
*ctx
,
589 unsigned int win
, bool protect
)
594 * SHADOWCON/PRTCON register is used for enabling timing.
596 * for example, once only width value of a register is set,
597 * if the dma is started then fimd hardware could malfunction so
598 * with protect window setting, the register fields with prefix '_F'
599 * wouldn't be updated at vsync also but updated once unprotect window
603 if (ctx
->driver_data
->has_shadowcon
) {
605 bits
= SHADOWCON_WINx_PROTECT(win
);
608 bits
= PRTCON_PROTECT
;
611 val
= readl(ctx
->regs
+ reg
);
616 writel(val
, ctx
->regs
+ reg
);
619 static void fimd_atomic_begin(struct exynos_drm_crtc
*crtc
,
620 struct exynos_drm_plane
*plane
)
622 struct fimd_context
*ctx
= crtc
->ctx
;
627 fimd_shadow_protect_win(ctx
, plane
->zpos
, true);
630 static void fimd_atomic_flush(struct exynos_drm_crtc
*crtc
,
631 struct exynos_drm_plane
*plane
)
633 struct fimd_context
*ctx
= crtc
->ctx
;
638 fimd_shadow_protect_win(ctx
, plane
->zpos
, false);
641 static void fimd_update_plane(struct exynos_drm_crtc
*crtc
,
642 struct exynos_drm_plane
*plane
)
644 struct exynos_drm_plane_state
*state
=
645 to_exynos_plane_state(plane
->base
.state
);
646 struct fimd_context
*ctx
= crtc
->ctx
;
647 struct drm_framebuffer
*fb
= state
->base
.fb
;
649 unsigned long val
, size
, offset
;
650 unsigned int last_x
, last_y
, buf_offsize
, line_size
;
651 unsigned int win
= plane
->zpos
;
652 unsigned int bpp
= fb
->bits_per_pixel
>> 3;
653 unsigned int pitch
= fb
->pitches
[0];
658 offset
= state
->src
.x
* bpp
;
659 offset
+= state
->src
.y
* pitch
;
661 /* buffer start address */
662 dma_addr
= exynos_drm_fb_dma_addr(fb
, 0) + offset
;
663 val
= (unsigned long)dma_addr
;
664 writel(val
, ctx
->regs
+ VIDWx_BUF_START(win
, 0));
666 /* buffer end address */
667 size
= pitch
* state
->crtc
.h
;
668 val
= (unsigned long)(dma_addr
+ size
);
669 writel(val
, ctx
->regs
+ VIDWx_BUF_END(win
, 0));
671 DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
672 (unsigned long)dma_addr
, val
, size
);
673 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
674 state
->crtc
.w
, state
->crtc
.h
);
677 buf_offsize
= pitch
- (state
->crtc
.w
* bpp
);
678 line_size
= state
->crtc
.w
* bpp
;
679 val
= VIDW_BUF_SIZE_OFFSET(buf_offsize
) |
680 VIDW_BUF_SIZE_PAGEWIDTH(line_size
) |
681 VIDW_BUF_SIZE_OFFSET_E(buf_offsize
) |
682 VIDW_BUF_SIZE_PAGEWIDTH_E(line_size
);
683 writel(val
, ctx
->regs
+ VIDWx_BUF_SIZE(win
, 0));
686 val
= VIDOSDxA_TOPLEFT_X(state
->crtc
.x
) |
687 VIDOSDxA_TOPLEFT_Y(state
->crtc
.y
) |
688 VIDOSDxA_TOPLEFT_X_E(state
->crtc
.x
) |
689 VIDOSDxA_TOPLEFT_Y_E(state
->crtc
.y
);
690 writel(val
, ctx
->regs
+ VIDOSD_A(win
));
692 last_x
= state
->crtc
.x
+ state
->crtc
.w
;
695 last_y
= state
->crtc
.y
+ state
->crtc
.h
;
699 val
= VIDOSDxB_BOTRIGHT_X(last_x
) | VIDOSDxB_BOTRIGHT_Y(last_y
) |
700 VIDOSDxB_BOTRIGHT_X_E(last_x
) | VIDOSDxB_BOTRIGHT_Y_E(last_y
);
702 writel(val
, ctx
->regs
+ VIDOSD_B(win
));
704 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
705 state
->crtc
.x
, state
->crtc
.y
, last_x
, last_y
);
708 if (win
!= 3 && win
!= 4) {
709 u32 offset
= VIDOSD_D(win
);
711 offset
= VIDOSD_C(win
);
712 val
= state
->crtc
.w
* state
->crtc
.h
;
713 writel(val
, ctx
->regs
+ offset
);
715 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val
);
718 fimd_win_set_pixfmt(ctx
, win
, fb
);
720 /* hardware window 0 doesn't support color key. */
722 fimd_win_set_colkey(ctx
, win
);
724 fimd_enable_video_output(ctx
, win
, true);
726 if (ctx
->driver_data
->has_shadowcon
)
727 fimd_enable_shadow_channel_path(ctx
, win
, true);
730 atomic_set(&ctx
->win_updated
, 1);
733 static void fimd_disable_plane(struct exynos_drm_crtc
*crtc
,
734 struct exynos_drm_plane
*plane
)
736 struct fimd_context
*ctx
= crtc
->ctx
;
737 unsigned int win
= plane
->zpos
;
742 fimd_enable_video_output(ctx
, win
, false);
744 if (ctx
->driver_data
->has_shadowcon
)
745 fimd_enable_shadow_channel_path(ctx
, win
, false);
748 static void fimd_enable(struct exynos_drm_crtc
*crtc
)
750 struct fimd_context
*ctx
= crtc
->ctx
;
755 ctx
->suspended
= false;
757 pm_runtime_get_sync(ctx
->dev
);
759 /* if vblank was enabled status, enable it again. */
760 if (test_and_clear_bit(0, &ctx
->irq_flags
))
761 fimd_enable_vblank(ctx
->crtc
);
763 fimd_commit(ctx
->crtc
);
766 static void fimd_disable(struct exynos_drm_crtc
*crtc
)
768 struct fimd_context
*ctx
= crtc
->ctx
;
775 * We need to make sure that all windows are disabled before we
776 * suspend that connector. Otherwise we might try to scan from
777 * a destroyed buffer later.
779 for (i
= 0; i
< WINDOWS_NR
; i
++)
780 fimd_disable_plane(crtc
, &ctx
->planes
[i
]);
782 fimd_enable_vblank(crtc
);
783 fimd_wait_for_vblank(crtc
);
784 fimd_disable_vblank(crtc
);
786 writel(0, ctx
->regs
+ VIDCON0
);
788 pm_runtime_put_sync(ctx
->dev
);
789 ctx
->suspended
= true;
792 static void fimd_trigger(struct device
*dev
)
794 struct fimd_context
*ctx
= dev_get_drvdata(dev
);
795 struct fimd_driver_data
*driver_data
= ctx
->driver_data
;
796 void *timing_base
= ctx
->regs
+ driver_data
->timing_base
;
800 * Skips triggering if in triggering state, because multiple triggering
801 * requests can cause panel reset.
803 if (atomic_read(&ctx
->triggering
))
806 /* Enters triggering mode */
807 atomic_set(&ctx
->triggering
, 1);
809 reg
= readl(timing_base
+ TRIGCON
);
810 reg
|= (TRGMODE_I80_RGB_ENABLE_I80
| SWTRGCMD_I80_RGB_ENABLE
);
811 writel(reg
, timing_base
+ TRIGCON
);
814 * Exits triggering mode if vblank is not enabled yet, because when the
815 * VIDINTCON0 register is not set, it can not exit from triggering mode.
817 if (!test_bit(0, &ctx
->irq_flags
))
818 atomic_set(&ctx
->triggering
, 0);
821 static void fimd_te_handler(struct exynos_drm_crtc
*crtc
)
823 struct fimd_context
*ctx
= crtc
->ctx
;
825 /* Checks the crtc is detached already from encoder */
826 if (ctx
->pipe
< 0 || !ctx
->drm_dev
)
830 * If there is a page flip request, triggers and handles the page flip
831 * event so that current fb can be updated into panel GRAM.
833 if (atomic_add_unless(&ctx
->win_updated
, -1, 0))
834 fimd_trigger(ctx
->dev
);
836 /* Wakes up vsync event queue */
837 if (atomic_read(&ctx
->wait_vsync_event
)) {
838 atomic_set(&ctx
->wait_vsync_event
, 0);
839 wake_up(&ctx
->wait_vsync_queue
);
842 if (test_bit(0, &ctx
->irq_flags
))
843 drm_crtc_handle_vblank(&ctx
->crtc
->base
);
846 static void fimd_dp_clock_enable(struct exynos_drm_crtc
*crtc
, bool enable
)
848 struct fimd_context
*ctx
= crtc
->ctx
;
852 * Only Exynos 5250, 5260, 5410 and 542x requires enabling DP/MIE
853 * clock. On these SoCs the bootloader may enable it but any
854 * power domain off/on will reset it to disable state.
856 if (ctx
->driver_data
!= &exynos5_fimd_driver_data
)
859 val
= enable
? DP_MIE_CLK_DP_ENABLE
: DP_MIE_CLK_DISABLE
;
860 writel(val
, ctx
->regs
+ DP_MIE_CLKCON
);
863 static const struct exynos_drm_crtc_ops fimd_crtc_ops
= {
864 .enable
= fimd_enable
,
865 .disable
= fimd_disable
,
866 .commit
= fimd_commit
,
867 .enable_vblank
= fimd_enable_vblank
,
868 .disable_vblank
= fimd_disable_vblank
,
869 .wait_for_vblank
= fimd_wait_for_vblank
,
870 .atomic_begin
= fimd_atomic_begin
,
871 .update_plane
= fimd_update_plane
,
872 .disable_plane
= fimd_disable_plane
,
873 .atomic_flush
= fimd_atomic_flush
,
874 .te_handler
= fimd_te_handler
,
875 .clock_enable
= fimd_dp_clock_enable
,
878 static irqreturn_t
fimd_irq_handler(int irq
, void *dev_id
)
880 struct fimd_context
*ctx
= (struct fimd_context
*)dev_id
;
881 u32 val
, clear_bit
, start
, start_s
;
884 val
= readl(ctx
->regs
+ VIDINTCON1
);
886 clear_bit
= ctx
->i80_if
? VIDINTCON1_INT_I80
: VIDINTCON1_INT_FRAME
;
888 writel(clear_bit
, ctx
->regs
+ VIDINTCON1
);
890 /* check the crtc is detached already from encoder */
891 if (ctx
->pipe
< 0 || !ctx
->drm_dev
)
895 drm_crtc_handle_vblank(&ctx
->crtc
->base
);
897 for (win
= 0 ; win
< WINDOWS_NR
; win
++) {
898 struct exynos_drm_plane
*plane
= &ctx
->planes
[win
];
900 if (!plane
->pending_fb
)
903 start
= readl(ctx
->regs
+ VIDWx_BUF_START(win
, 0));
904 start_s
= readl(ctx
->regs
+ VIDWx_BUF_START_S(win
, 0));
905 if (start
== start_s
)
906 exynos_drm_crtc_finish_update(ctx
->crtc
, plane
);
910 /* Exits triggering mode */
911 atomic_set(&ctx
->triggering
, 0);
913 /* set wait vsync event to zero and wake up queue. */
914 if (atomic_read(&ctx
->wait_vsync_event
)) {
915 atomic_set(&ctx
->wait_vsync_event
, 0);
916 wake_up(&ctx
->wait_vsync_queue
);
924 static int fimd_bind(struct device
*dev
, struct device
*master
, void *data
)
926 struct fimd_context
*ctx
= dev_get_drvdata(dev
);
927 struct drm_device
*drm_dev
= data
;
928 struct exynos_drm_private
*priv
= drm_dev
->dev_private
;
929 struct exynos_drm_plane
*exynos_plane
;
930 enum drm_plane_type type
;
934 ctx
->drm_dev
= drm_dev
;
935 ctx
->pipe
= priv
->pipe
++;
937 for (zpos
= 0; zpos
< WINDOWS_NR
; zpos
++) {
938 type
= exynos_plane_get_type(zpos
, CURSOR_WIN
);
939 ret
= exynos_plane_init(drm_dev
, &ctx
->planes
[zpos
],
940 1 << ctx
->pipe
, type
, fimd_formats
,
941 ARRAY_SIZE(fimd_formats
), zpos
);
946 exynos_plane
= &ctx
->planes
[DEFAULT_WIN
];
947 ctx
->crtc
= exynos_drm_crtc_create(drm_dev
, &exynos_plane
->base
,
948 ctx
->pipe
, EXYNOS_DISPLAY_TYPE_LCD
,
949 &fimd_crtc_ops
, ctx
);
950 if (IS_ERR(ctx
->crtc
))
951 return PTR_ERR(ctx
->crtc
);
954 exynos_dpi_bind(drm_dev
, ctx
->encoder
);
956 if (is_drm_iommu_supported(drm_dev
))
957 fimd_clear_channels(ctx
->crtc
);
959 ret
= drm_iommu_attach_device(drm_dev
, dev
);
966 static void fimd_unbind(struct device
*dev
, struct device
*master
,
969 struct fimd_context
*ctx
= dev_get_drvdata(dev
);
971 fimd_disable(ctx
->crtc
);
973 drm_iommu_detach_device(ctx
->drm_dev
, ctx
->dev
);
976 exynos_dpi_remove(ctx
->encoder
);
979 static const struct component_ops fimd_component_ops
= {
981 .unbind
= fimd_unbind
,
984 static int fimd_probe(struct platform_device
*pdev
)
986 struct device
*dev
= &pdev
->dev
;
987 struct fimd_context
*ctx
;
988 struct device_node
*i80_if_timings
;
989 struct resource
*res
;
995 ctx
= devm_kzalloc(dev
, sizeof(*ctx
), GFP_KERNEL
);
1000 ctx
->suspended
= true;
1001 ctx
->driver_data
= drm_fimd_get_driver_data(pdev
);
1003 if (of_property_read_bool(dev
->of_node
, "samsung,invert-vden"))
1004 ctx
->vidcon1
|= VIDCON1_INV_VDEN
;
1005 if (of_property_read_bool(dev
->of_node
, "samsung,invert-vclk"))
1006 ctx
->vidcon1
|= VIDCON1_INV_VCLK
;
1008 i80_if_timings
= of_get_child_by_name(dev
->of_node
, "i80-if-timings");
1009 if (i80_if_timings
) {
1014 if (ctx
->driver_data
->has_vidoutcon
)
1015 ctx
->vidout_con
|= VIDOUT_CON_F_I80_LDI0
;
1017 ctx
->vidcon0
|= VIDCON0_VIDOUT_I80_LDI0
;
1019 * The user manual describes that this "DSI_EN" bit is required
1020 * to enable I80 24-bit data interface.
1022 ctx
->vidcon0
|= VIDCON0_DSI_EN
;
1024 if (of_property_read_u32(i80_if_timings
, "cs-setup", &val
))
1026 ctx
->i80ifcon
= LCD_CS_SETUP(val
);
1027 if (of_property_read_u32(i80_if_timings
, "wr-setup", &val
))
1029 ctx
->i80ifcon
|= LCD_WR_SETUP(val
);
1030 if (of_property_read_u32(i80_if_timings
, "wr-active", &val
))
1032 ctx
->i80ifcon
|= LCD_WR_ACTIVE(val
);
1033 if (of_property_read_u32(i80_if_timings
, "wr-hold", &val
))
1035 ctx
->i80ifcon
|= LCD_WR_HOLD(val
);
1037 of_node_put(i80_if_timings
);
1039 ctx
->sysreg
= syscon_regmap_lookup_by_phandle(dev
->of_node
,
1041 if (IS_ERR(ctx
->sysreg
)) {
1042 dev_warn(dev
, "failed to get system register.\n");
1046 ctx
->bus_clk
= devm_clk_get(dev
, "fimd");
1047 if (IS_ERR(ctx
->bus_clk
)) {
1048 dev_err(dev
, "failed to get bus clock\n");
1049 return PTR_ERR(ctx
->bus_clk
);
1052 ctx
->lcd_clk
= devm_clk_get(dev
, "sclk_fimd");
1053 if (IS_ERR(ctx
->lcd_clk
)) {
1054 dev_err(dev
, "failed to get lcd clock\n");
1055 return PTR_ERR(ctx
->lcd_clk
);
1058 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1060 ctx
->regs
= devm_ioremap_resource(dev
, res
);
1061 if (IS_ERR(ctx
->regs
))
1062 return PTR_ERR(ctx
->regs
);
1064 res
= platform_get_resource_byname(pdev
, IORESOURCE_IRQ
,
1065 ctx
->i80_if
? "lcd_sys" : "vsync");
1067 dev_err(dev
, "irq request failed.\n");
1071 ret
= devm_request_irq(dev
, res
->start
, fimd_irq_handler
,
1072 0, "drm_fimd", ctx
);
1074 dev_err(dev
, "irq request failed.\n");
1078 init_waitqueue_head(&ctx
->wait_vsync_queue
);
1079 atomic_set(&ctx
->wait_vsync_event
, 0);
1081 platform_set_drvdata(pdev
, ctx
);
1083 ctx
->encoder
= exynos_dpi_probe(dev
);
1084 if (IS_ERR(ctx
->encoder
))
1085 return PTR_ERR(ctx
->encoder
);
1087 pm_runtime_enable(dev
);
1089 ret
= component_add(dev
, &fimd_component_ops
);
1091 goto err_disable_pm_runtime
;
1095 err_disable_pm_runtime
:
1096 pm_runtime_disable(dev
);
1101 static int fimd_remove(struct platform_device
*pdev
)
1103 pm_runtime_disable(&pdev
->dev
);
1105 component_del(&pdev
->dev
, &fimd_component_ops
);
1111 static int exynos_fimd_suspend(struct device
*dev
)
1113 struct fimd_context
*ctx
= dev_get_drvdata(dev
);
1115 clk_disable_unprepare(ctx
->lcd_clk
);
1116 clk_disable_unprepare(ctx
->bus_clk
);
1121 static int exynos_fimd_resume(struct device
*dev
)
1123 struct fimd_context
*ctx
= dev_get_drvdata(dev
);
1126 ret
= clk_prepare_enable(ctx
->bus_clk
);
1128 DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret
);
1132 ret
= clk_prepare_enable(ctx
->lcd_clk
);
1134 DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret
);
1142 static const struct dev_pm_ops exynos_fimd_pm_ops
= {
1143 SET_RUNTIME_PM_OPS(exynos_fimd_suspend
, exynos_fimd_resume
, NULL
)
1146 struct platform_driver fimd_driver
= {
1147 .probe
= fimd_probe
,
1148 .remove
= fimd_remove
,
1150 .name
= "exynos4-fb",
1151 .owner
= THIS_MODULE
,
1152 .pm
= &exynos_fimd_pm_ops
,
1153 .of_match_table
= fimd_driver_dt_match
,