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drm/exynos: add drm_iommu_attach_device_if_possible()
[deliverable/linux.git] / drivers / gpu / drm / exynos / exynos_drm_fimd.c
1 /* exynos_drm_fimd.c
2 *
3 * Copyright (C) 2011 Samsung Electronics Co.Ltd
4 * Authors:
5 * Joonyoung Shim <jy0922.shim@samsung.com>
6 * Inki Dae <inki.dae@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14 #include <drm/drmP.h>
15
16 #include <linux/kernel.h>
17 #include <linux/platform_device.h>
18 #include <linux/clk.h>
19 #include <linux/of.h>
20 #include <linux/of_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/component.h>
23 #include <linux/mfd/syscon.h>
24 #include <linux/regmap.h>
25
26 #include <video/of_display_timing.h>
27 #include <video/of_videomode.h>
28 #include <video/samsung_fimd.h>
29 #include <drm/exynos_drm.h>
30
31 #include "exynos_drm_drv.h"
32 #include "exynos_drm_fbdev.h"
33 #include "exynos_drm_crtc.h"
34 #include "exynos_drm_plane.h"
35 #include "exynos_drm_iommu.h"
36
37 /*
38 * FIMD stands for Fully Interactive Mobile Display and
39 * as a display controller, it transfers contents drawn on memory
40 * to a LCD Panel through Display Interfaces such as RGB or
41 * CPU Interface.
42 */
43
44 #define FIMD_DEFAULT_FRAMERATE 60
45 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
46
47 /* position control register for hardware window 0, 2 ~ 4.*/
48 #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
49 #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
50 /*
51 * size control register for hardware windows 0 and alpha control register
52 * for hardware windows 1 ~ 4
53 */
54 #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16)
55 /* size control register for hardware windows 1 ~ 2. */
56 #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
57
58 #define VIDWnALPHA0(win) (VIDW_ALPHA + 0x00 + (win) * 8)
59 #define VIDWnALPHA1(win) (VIDW_ALPHA + 0x04 + (win) * 8)
60
61 #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
62 #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8)
63 #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
64
65 /* color key control register for hardware window 1 ~ 4. */
66 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8))
67 /* color key value register for hardware window 1 ~ 4. */
68 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
69
70 /* I80 / RGB trigger control register */
71 #define TRIGCON 0x1A4
72 #define TRGMODE_I80_RGB_ENABLE_I80 (1 << 0)
73 #define SWTRGCMD_I80_RGB_ENABLE (1 << 1)
74
75 /* display mode change control register except exynos4 */
76 #define VIDOUT_CON 0x000
77 #define VIDOUT_CON_F_I80_LDI0 (0x2 << 8)
78
79 /* I80 interface control for main LDI register */
80 #define I80IFCONFAx(x) (0x1B0 + (x) * 4)
81 #define I80IFCONFBx(x) (0x1B8 + (x) * 4)
82 #define LCD_CS_SETUP(x) ((x) << 16)
83 #define LCD_WR_SETUP(x) ((x) << 12)
84 #define LCD_WR_ACTIVE(x) ((x) << 8)
85 #define LCD_WR_HOLD(x) ((x) << 4)
86 #define I80IFEN_ENABLE (1 << 0)
87
88 /* FIMD has totally five hardware windows. */
89 #define WINDOWS_NR 5
90
91 struct fimd_driver_data {
92 unsigned int timing_base;
93 unsigned int lcdblk_offset;
94 unsigned int lcdblk_vt_shift;
95 unsigned int lcdblk_bypass_shift;
96
97 unsigned int has_shadowcon:1;
98 unsigned int has_clksel:1;
99 unsigned int has_limited_fmt:1;
100 unsigned int has_vidoutcon:1;
101 unsigned int has_vtsel:1;
102 };
103
104 static struct fimd_driver_data s3c64xx_fimd_driver_data = {
105 .timing_base = 0x0,
106 .has_clksel = 1,
107 .has_limited_fmt = 1,
108 };
109
110 static struct fimd_driver_data exynos3_fimd_driver_data = {
111 .timing_base = 0x20000,
112 .lcdblk_offset = 0x210,
113 .lcdblk_bypass_shift = 1,
114 .has_shadowcon = 1,
115 .has_vidoutcon = 1,
116 };
117
118 static struct fimd_driver_data exynos4_fimd_driver_data = {
119 .timing_base = 0x0,
120 .lcdblk_offset = 0x210,
121 .lcdblk_vt_shift = 10,
122 .lcdblk_bypass_shift = 1,
123 .has_shadowcon = 1,
124 .has_vtsel = 1,
125 };
126
127 static struct fimd_driver_data exynos4415_fimd_driver_data = {
128 .timing_base = 0x20000,
129 .lcdblk_offset = 0x210,
130 .lcdblk_vt_shift = 10,
131 .lcdblk_bypass_shift = 1,
132 .has_shadowcon = 1,
133 .has_vidoutcon = 1,
134 .has_vtsel = 1,
135 };
136
137 static struct fimd_driver_data exynos5_fimd_driver_data = {
138 .timing_base = 0x20000,
139 .lcdblk_offset = 0x214,
140 .lcdblk_vt_shift = 24,
141 .lcdblk_bypass_shift = 15,
142 .has_shadowcon = 1,
143 .has_vidoutcon = 1,
144 .has_vtsel = 1,
145 };
146
147 struct fimd_context {
148 struct device *dev;
149 struct drm_device *drm_dev;
150 struct exynos_drm_crtc *crtc;
151 struct exynos_drm_plane planes[WINDOWS_NR];
152 struct clk *bus_clk;
153 struct clk *lcd_clk;
154 void __iomem *regs;
155 struct regmap *sysreg;
156 unsigned int default_win;
157 unsigned long irq_flags;
158 u32 vidcon0;
159 u32 vidcon1;
160 u32 vidout_con;
161 u32 i80ifcon;
162 bool i80_if;
163 bool suspended;
164 int pipe;
165 wait_queue_head_t wait_vsync_queue;
166 atomic_t wait_vsync_event;
167 atomic_t win_updated;
168 atomic_t triggering;
169
170 struct exynos_drm_panel_info panel;
171 struct fimd_driver_data *driver_data;
172 struct exynos_drm_display *display;
173 };
174
175 static const struct of_device_id fimd_driver_dt_match[] = {
176 { .compatible = "samsung,s3c6400-fimd",
177 .data = &s3c64xx_fimd_driver_data },
178 { .compatible = "samsung,exynos3250-fimd",
179 .data = &exynos3_fimd_driver_data },
180 { .compatible = "samsung,exynos4210-fimd",
181 .data = &exynos4_fimd_driver_data },
182 { .compatible = "samsung,exynos4415-fimd",
183 .data = &exynos4415_fimd_driver_data },
184 { .compatible = "samsung,exynos5250-fimd",
185 .data = &exynos5_fimd_driver_data },
186 {},
187 };
188 MODULE_DEVICE_TABLE(of, fimd_driver_dt_match);
189
190 static inline struct fimd_driver_data *drm_fimd_get_driver_data(
191 struct platform_device *pdev)
192 {
193 const struct of_device_id *of_id =
194 of_match_device(fimd_driver_dt_match, &pdev->dev);
195
196 return (struct fimd_driver_data *)of_id->data;
197 }
198
199 static int fimd_enable_vblank(struct exynos_drm_crtc *crtc)
200 {
201 struct fimd_context *ctx = crtc->ctx;
202 u32 val;
203
204 if (ctx->suspended)
205 return -EPERM;
206
207 if (!test_and_set_bit(0, &ctx->irq_flags)) {
208 val = readl(ctx->regs + VIDINTCON0);
209
210 val |= VIDINTCON0_INT_ENABLE;
211
212 if (ctx->i80_if) {
213 val |= VIDINTCON0_INT_I80IFDONE;
214 val |= VIDINTCON0_INT_SYSMAINCON;
215 val &= ~VIDINTCON0_INT_SYSSUBCON;
216 } else {
217 val |= VIDINTCON0_INT_FRAME;
218
219 val &= ~VIDINTCON0_FRAMESEL0_MASK;
220 val |= VIDINTCON0_FRAMESEL0_VSYNC;
221 val &= ~VIDINTCON0_FRAMESEL1_MASK;
222 val |= VIDINTCON0_FRAMESEL1_NONE;
223 }
224
225 writel(val, ctx->regs + VIDINTCON0);
226 }
227
228 return 0;
229 }
230
231 static void fimd_disable_vblank(struct exynos_drm_crtc *crtc)
232 {
233 struct fimd_context *ctx = crtc->ctx;
234 u32 val;
235
236 if (ctx->suspended)
237 return;
238
239 if (test_and_clear_bit(0, &ctx->irq_flags)) {
240 val = readl(ctx->regs + VIDINTCON0);
241
242 val &= ~VIDINTCON0_INT_ENABLE;
243
244 if (ctx->i80_if) {
245 val &= ~VIDINTCON0_INT_I80IFDONE;
246 val &= ~VIDINTCON0_INT_SYSMAINCON;
247 val &= ~VIDINTCON0_INT_SYSSUBCON;
248 } else
249 val &= ~VIDINTCON0_INT_FRAME;
250
251 writel(val, ctx->regs + VIDINTCON0);
252 }
253 }
254
255 static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc)
256 {
257 struct fimd_context *ctx = crtc->ctx;
258
259 if (ctx->suspended)
260 return;
261
262 atomic_set(&ctx->wait_vsync_event, 1);
263
264 /*
265 * wait for FIMD to signal VSYNC interrupt or return after
266 * timeout which is set to 50ms (refresh rate of 20).
267 */
268 if (!wait_event_timeout(ctx->wait_vsync_queue,
269 !atomic_read(&ctx->wait_vsync_event),
270 HZ/20))
271 DRM_DEBUG_KMS("vblank wait timed out.\n");
272 }
273
274 static void fimd_enable_video_output(struct fimd_context *ctx, unsigned int win,
275 bool enable)
276 {
277 u32 val = readl(ctx->regs + WINCON(win));
278
279 if (enable)
280 val |= WINCONx_ENWIN;
281 else
282 val &= ~WINCONx_ENWIN;
283
284 writel(val, ctx->regs + WINCON(win));
285 }
286
287 static void fimd_enable_shadow_channel_path(struct fimd_context *ctx,
288 unsigned int win,
289 bool enable)
290 {
291 u32 val = readl(ctx->regs + SHADOWCON);
292
293 if (enable)
294 val |= SHADOWCON_CHx_ENABLE(win);
295 else
296 val &= ~SHADOWCON_CHx_ENABLE(win);
297
298 writel(val, ctx->regs + SHADOWCON);
299 }
300
301 static void fimd_clear_channels(struct exynos_drm_crtc *crtc)
302 {
303 struct fimd_context *ctx = crtc->ctx;
304 unsigned int win, ch_enabled = 0;
305
306 DRM_DEBUG_KMS("%s\n", __FILE__);
307
308 /* Hardware is in unknown state, so ensure it gets enabled properly */
309 pm_runtime_get_sync(ctx->dev);
310
311 clk_prepare_enable(ctx->bus_clk);
312 clk_prepare_enable(ctx->lcd_clk);
313
314 /* Check if any channel is enabled. */
315 for (win = 0; win < WINDOWS_NR; win++) {
316 u32 val = readl(ctx->regs + WINCON(win));
317
318 if (val & WINCONx_ENWIN) {
319 fimd_enable_video_output(ctx, win, false);
320
321 if (ctx->driver_data->has_shadowcon)
322 fimd_enable_shadow_channel_path(ctx, win,
323 false);
324
325 ch_enabled = 1;
326 }
327 }
328
329 /* Wait for vsync, as disable channel takes effect at next vsync */
330 if (ch_enabled) {
331 int pipe = ctx->pipe;
332
333 /* ensure that vblank interrupt won't be reported to core */
334 ctx->suspended = false;
335 ctx->pipe = -1;
336
337 fimd_enable_vblank(ctx->crtc);
338 fimd_wait_for_vblank(ctx->crtc);
339 fimd_disable_vblank(ctx->crtc);
340
341 ctx->suspended = true;
342 ctx->pipe = pipe;
343 }
344
345 clk_disable_unprepare(ctx->lcd_clk);
346 clk_disable_unprepare(ctx->bus_clk);
347
348 pm_runtime_put(ctx->dev);
349 }
350
351 static void fimd_iommu_detach_devices(struct fimd_context *ctx)
352 {
353 /* detach this sub driver from iommu mapping if supported. */
354 if (is_drm_iommu_supported(ctx->drm_dev))
355 drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
356 }
357
358 static u32 fimd_calc_clkdiv(struct fimd_context *ctx,
359 const struct drm_display_mode *mode)
360 {
361 unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
362 u32 clkdiv;
363
364 if (ctx->i80_if) {
365 /*
366 * The frame done interrupt should be occurred prior to the
367 * next TE signal.
368 */
369 ideal_clk *= 2;
370 }
371
372 /* Find the clock divider value that gets us closest to ideal_clk */
373 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->lcd_clk), ideal_clk);
374
375 return (clkdiv < 0x100) ? clkdiv : 0xff;
376 }
377
378 static bool fimd_mode_fixup(struct exynos_drm_crtc *crtc,
379 const struct drm_display_mode *mode,
380 struct drm_display_mode *adjusted_mode)
381 {
382 if (adjusted_mode->vrefresh == 0)
383 adjusted_mode->vrefresh = FIMD_DEFAULT_FRAMERATE;
384
385 return true;
386 }
387
388 static void fimd_commit(struct exynos_drm_crtc *crtc)
389 {
390 struct fimd_context *ctx = crtc->ctx;
391 struct drm_display_mode *mode = &crtc->base.state->adjusted_mode;
392 struct fimd_driver_data *driver_data = ctx->driver_data;
393 void *timing_base = ctx->regs + driver_data->timing_base;
394 u32 val, clkdiv;
395
396 if (ctx->suspended)
397 return;
398
399 /* nothing to do if we haven't set the mode yet */
400 if (mode->htotal == 0 || mode->vtotal == 0)
401 return;
402
403 if (ctx->i80_if) {
404 val = ctx->i80ifcon | I80IFEN_ENABLE;
405 writel(val, timing_base + I80IFCONFAx(0));
406
407 /* disable auto frame rate */
408 writel(0, timing_base + I80IFCONFBx(0));
409
410 /* set video type selection to I80 interface */
411 if (driver_data->has_vtsel && ctx->sysreg &&
412 regmap_update_bits(ctx->sysreg,
413 driver_data->lcdblk_offset,
414 0x3 << driver_data->lcdblk_vt_shift,
415 0x1 << driver_data->lcdblk_vt_shift)) {
416 DRM_ERROR("Failed to update sysreg for I80 i/f.\n");
417 return;
418 }
419 } else {
420 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
421 u32 vidcon1;
422
423 /* setup polarity values */
424 vidcon1 = ctx->vidcon1;
425 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
426 vidcon1 |= VIDCON1_INV_VSYNC;
427 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
428 vidcon1 |= VIDCON1_INV_HSYNC;
429 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
430
431 /* setup vertical timing values. */
432 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
433 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
434 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
435
436 val = VIDTCON0_VBPD(vbpd - 1) |
437 VIDTCON0_VFPD(vfpd - 1) |
438 VIDTCON0_VSPW(vsync_len - 1);
439 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
440
441 /* setup horizontal timing values. */
442 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
443 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
444 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
445
446 val = VIDTCON1_HBPD(hbpd - 1) |
447 VIDTCON1_HFPD(hfpd - 1) |
448 VIDTCON1_HSPW(hsync_len - 1);
449 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
450 }
451
452 if (driver_data->has_vidoutcon)
453 writel(ctx->vidout_con, timing_base + VIDOUT_CON);
454
455 /* set bypass selection */
456 if (ctx->sysreg && regmap_update_bits(ctx->sysreg,
457 driver_data->lcdblk_offset,
458 0x1 << driver_data->lcdblk_bypass_shift,
459 0x1 << driver_data->lcdblk_bypass_shift)) {
460 DRM_ERROR("Failed to update sysreg for bypass setting.\n");
461 return;
462 }
463
464 /* setup horizontal and vertical display size. */
465 val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
466 VIDTCON2_HOZVAL(mode->hdisplay - 1) |
467 VIDTCON2_LINEVAL_E(mode->vdisplay - 1) |
468 VIDTCON2_HOZVAL_E(mode->hdisplay - 1);
469 writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
470
471 /*
472 * fields of register with prefix '_F' would be updated
473 * at vsync(same as dma start)
474 */
475 val = ctx->vidcon0;
476 val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
477
478 if (ctx->driver_data->has_clksel)
479 val |= VIDCON0_CLKSEL_LCD;
480
481 clkdiv = fimd_calc_clkdiv(ctx, mode);
482 if (clkdiv > 1)
483 val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR;
484
485 writel(val, ctx->regs + VIDCON0);
486 }
487
488
489 static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win)
490 {
491 struct exynos_drm_plane *plane = &ctx->planes[win];
492 unsigned long val;
493
494 val = WINCONx_ENWIN;
495
496 /*
497 * In case of s3c64xx, window 0 doesn't support alpha channel.
498 * So the request format is ARGB8888 then change it to XRGB8888.
499 */
500 if (ctx->driver_data->has_limited_fmt && !win) {
501 if (plane->pixel_format == DRM_FORMAT_ARGB8888)
502 plane->pixel_format = DRM_FORMAT_XRGB8888;
503 }
504
505 switch (plane->pixel_format) {
506 case DRM_FORMAT_C8:
507 val |= WINCON0_BPPMODE_8BPP_PALETTE;
508 val |= WINCONx_BURSTLEN_8WORD;
509 val |= WINCONx_BYTSWP;
510 break;
511 case DRM_FORMAT_XRGB1555:
512 val |= WINCON0_BPPMODE_16BPP_1555;
513 val |= WINCONx_HAWSWP;
514 val |= WINCONx_BURSTLEN_16WORD;
515 break;
516 case DRM_FORMAT_RGB565:
517 val |= WINCON0_BPPMODE_16BPP_565;
518 val |= WINCONx_HAWSWP;
519 val |= WINCONx_BURSTLEN_16WORD;
520 break;
521 case DRM_FORMAT_XRGB8888:
522 val |= WINCON0_BPPMODE_24BPP_888;
523 val |= WINCONx_WSWP;
524 val |= WINCONx_BURSTLEN_16WORD;
525 break;
526 case DRM_FORMAT_ARGB8888:
527 val |= WINCON1_BPPMODE_25BPP_A1888
528 | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
529 val |= WINCONx_WSWP;
530 val |= WINCONx_BURSTLEN_16WORD;
531 break;
532 default:
533 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
534
535 val |= WINCON0_BPPMODE_24BPP_888;
536 val |= WINCONx_WSWP;
537 val |= WINCONx_BURSTLEN_16WORD;
538 break;
539 }
540
541 DRM_DEBUG_KMS("bpp = %d\n", plane->bpp);
542
543 /*
544 * In case of exynos, setting dma-burst to 16Word causes permanent
545 * tearing for very small buffers, e.g. cursor buffer. Burst Mode
546 * switching which is based on plane size is not recommended as
547 * plane size varies alot towards the end of the screen and rapid
548 * movement causes unstable DMA which results into iommu crash/tear.
549 */
550
551 if (plane->fb_width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
552 val &= ~WINCONx_BURSTLEN_MASK;
553 val |= WINCONx_BURSTLEN_4WORD;
554 }
555
556 writel(val, ctx->regs + WINCON(win));
557
558 /* hardware window 0 doesn't support alpha channel. */
559 if (win != 0) {
560 /* OSD alpha */
561 val = VIDISD14C_ALPHA0_R(0xf) |
562 VIDISD14C_ALPHA0_G(0xf) |
563 VIDISD14C_ALPHA0_B(0xf) |
564 VIDISD14C_ALPHA1_R(0xf) |
565 VIDISD14C_ALPHA1_G(0xf) |
566 VIDISD14C_ALPHA1_B(0xf);
567
568 writel(val, ctx->regs + VIDOSD_C(win));
569
570 val = VIDW_ALPHA_R(0xf) | VIDW_ALPHA_G(0xf) |
571 VIDW_ALPHA_G(0xf);
572 writel(val, ctx->regs + VIDWnALPHA0(win));
573 writel(val, ctx->regs + VIDWnALPHA1(win));
574 }
575 }
576
577 static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win)
578 {
579 unsigned int keycon0 = 0, keycon1 = 0;
580
581 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
582 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
583
584 keycon1 = WxKEYCON1_COLVAL(0xffffffff);
585
586 writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
587 writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
588 }
589
590 /**
591 * shadow_protect_win() - disable updating values from shadow registers at vsync
592 *
593 * @win: window to protect registers for
594 * @protect: 1 to protect (disable updates)
595 */
596 static void fimd_shadow_protect_win(struct fimd_context *ctx,
597 unsigned int win, bool protect)
598 {
599 u32 reg, bits, val;
600
601 if (ctx->driver_data->has_shadowcon) {
602 reg = SHADOWCON;
603 bits = SHADOWCON_WINx_PROTECT(win);
604 } else {
605 reg = PRTCON;
606 bits = PRTCON_PROTECT;
607 }
608
609 val = readl(ctx->regs + reg);
610 if (protect)
611 val |= bits;
612 else
613 val &= ~bits;
614 writel(val, ctx->regs + reg);
615 }
616
617 static void fimd_win_commit(struct exynos_drm_crtc *crtc, unsigned int win)
618 {
619 struct fimd_context *ctx = crtc->ctx;
620 struct exynos_drm_plane *plane;
621 dma_addr_t dma_addr;
622 unsigned long val, size, offset;
623 unsigned int last_x, last_y, buf_offsize, line_size;
624
625 if (ctx->suspended)
626 return;
627
628 if (win < 0 || win >= WINDOWS_NR)
629 return;
630
631 plane = &ctx->planes[win];
632
633 if (ctx->suspended)
634 return;
635
636 /*
637 * SHADOWCON/PRTCON register is used for enabling timing.
638 *
639 * for example, once only width value of a register is set,
640 * if the dma is started then fimd hardware could malfunction so
641 * with protect window setting, the register fields with prefix '_F'
642 * wouldn't be updated at vsync also but updated once unprotect window
643 * is set.
644 */
645
646 /* protect windows */
647 fimd_shadow_protect_win(ctx, win, true);
648
649
650 offset = plane->src_x * (plane->bpp >> 3);
651 offset += plane->src_y * plane->pitch;
652
653 /* buffer start address */
654 dma_addr = plane->dma_addr[0] + offset;
655 val = (unsigned long)dma_addr;
656 writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
657
658 /* buffer end address */
659 size = plane->pitch * plane->crtc_height;
660 val = (unsigned long)(dma_addr + size);
661 writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
662
663 DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
664 (unsigned long)dma_addr, val, size);
665 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
666 plane->crtc_width, plane->crtc_height);
667
668 /* buffer size */
669 buf_offsize = plane->pitch - (plane->crtc_width * (plane->bpp >> 3));
670 line_size = plane->crtc_width * (plane->bpp >> 3);
671 val = VIDW_BUF_SIZE_OFFSET(buf_offsize) |
672 VIDW_BUF_SIZE_PAGEWIDTH(line_size) |
673 VIDW_BUF_SIZE_OFFSET_E(buf_offsize) |
674 VIDW_BUF_SIZE_PAGEWIDTH_E(line_size);
675 writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
676
677 /* OSD position */
678 val = VIDOSDxA_TOPLEFT_X(plane->crtc_x) |
679 VIDOSDxA_TOPLEFT_Y(plane->crtc_y) |
680 VIDOSDxA_TOPLEFT_X_E(plane->crtc_x) |
681 VIDOSDxA_TOPLEFT_Y_E(plane->crtc_y);
682 writel(val, ctx->regs + VIDOSD_A(win));
683
684 last_x = plane->crtc_x + plane->crtc_width;
685 if (last_x)
686 last_x--;
687 last_y = plane->crtc_y + plane->crtc_height;
688 if (last_y)
689 last_y--;
690
691 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
692 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);
693
694 writel(val, ctx->regs + VIDOSD_B(win));
695
696 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
697 plane->crtc_x, plane->crtc_y, last_x, last_y);
698
699 /* OSD size */
700 if (win != 3 && win != 4) {
701 u32 offset = VIDOSD_D(win);
702 if (win == 0)
703 offset = VIDOSD_C(win);
704 val = plane->crtc_width * plane->crtc_height;
705 writel(val, ctx->regs + offset);
706
707 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
708 }
709
710 fimd_win_set_pixfmt(ctx, win);
711
712 /* hardware window 0 doesn't support color key. */
713 if (win != 0)
714 fimd_win_set_colkey(ctx, win);
715
716 fimd_enable_video_output(ctx, win, true);
717
718 if (ctx->driver_data->has_shadowcon)
719 fimd_enable_shadow_channel_path(ctx, win, true);
720
721 /* Enable DMA channel and unprotect windows */
722 fimd_shadow_protect_win(ctx, win, false);
723
724 if (ctx->i80_if)
725 atomic_set(&ctx->win_updated, 1);
726 }
727
728 static void fimd_win_disable(struct exynos_drm_crtc *crtc, unsigned int win)
729 {
730 struct fimd_context *ctx = crtc->ctx;
731 struct exynos_drm_plane *plane;
732
733 if (win < 0 || win >= WINDOWS_NR)
734 return;
735
736 plane = &ctx->planes[win];
737
738 if (ctx->suspended)
739 return;
740
741 /* protect windows */
742 fimd_shadow_protect_win(ctx, win, true);
743
744 fimd_enable_video_output(ctx, win, false);
745
746 if (ctx->driver_data->has_shadowcon)
747 fimd_enable_shadow_channel_path(ctx, win, false);
748
749 /* unprotect windows */
750 fimd_shadow_protect_win(ctx, win, false);
751 }
752
753 static void fimd_enable(struct exynos_drm_crtc *crtc)
754 {
755 struct fimd_context *ctx = crtc->ctx;
756 int ret;
757
758 if (!ctx->suspended)
759 return;
760
761 ctx->suspended = false;
762
763 pm_runtime_get_sync(ctx->dev);
764
765 ret = clk_prepare_enable(ctx->bus_clk);
766 if (ret < 0) {
767 DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret);
768 return;
769 }
770
771 ret = clk_prepare_enable(ctx->lcd_clk);
772 if (ret < 0) {
773 DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret);
774 return;
775 }
776
777 /* if vblank was enabled status, enable it again. */
778 if (test_and_clear_bit(0, &ctx->irq_flags))
779 fimd_enable_vblank(ctx->crtc);
780
781 fimd_commit(ctx->crtc);
782 }
783
784 static void fimd_disable(struct exynos_drm_crtc *crtc)
785 {
786 struct fimd_context *ctx = crtc->ctx;
787 int i;
788
789 if (ctx->suspended)
790 return;
791
792 /*
793 * We need to make sure that all windows are disabled before we
794 * suspend that connector. Otherwise we might try to scan from
795 * a destroyed buffer later.
796 */
797 for (i = 0; i < WINDOWS_NR; i++)
798 fimd_win_disable(crtc, i);
799
800 fimd_enable_vblank(crtc);
801 fimd_wait_for_vblank(crtc);
802 fimd_disable_vblank(crtc);
803
804 writel(0, ctx->regs + VIDCON0);
805
806 clk_disable_unprepare(ctx->lcd_clk);
807 clk_disable_unprepare(ctx->bus_clk);
808
809 pm_runtime_put_sync(ctx->dev);
810
811 ctx->suspended = true;
812 }
813
814 static void fimd_trigger(struct device *dev)
815 {
816 struct fimd_context *ctx = dev_get_drvdata(dev);
817 struct fimd_driver_data *driver_data = ctx->driver_data;
818 void *timing_base = ctx->regs + driver_data->timing_base;
819 u32 reg;
820
821 /*
822 * Skips triggering if in triggering state, because multiple triggering
823 * requests can cause panel reset.
824 */
825 if (atomic_read(&ctx->triggering))
826 return;
827
828 /* Enters triggering mode */
829 atomic_set(&ctx->triggering, 1);
830
831 reg = readl(timing_base + TRIGCON);
832 reg |= (TRGMODE_I80_RGB_ENABLE_I80 | SWTRGCMD_I80_RGB_ENABLE);
833 writel(reg, timing_base + TRIGCON);
834
835 /*
836 * Exits triggering mode if vblank is not enabled yet, because when the
837 * VIDINTCON0 register is not set, it can not exit from triggering mode.
838 */
839 if (!test_bit(0, &ctx->irq_flags))
840 atomic_set(&ctx->triggering, 0);
841 }
842
843 static void fimd_te_handler(struct exynos_drm_crtc *crtc)
844 {
845 struct fimd_context *ctx = crtc->ctx;
846
847 /* Checks the crtc is detached already from encoder */
848 if (ctx->pipe < 0 || !ctx->drm_dev)
849 return;
850
851 /*
852 * If there is a page flip request, triggers and handles the page flip
853 * event so that current fb can be updated into panel GRAM.
854 */
855 if (atomic_add_unless(&ctx->win_updated, -1, 0))
856 fimd_trigger(ctx->dev);
857
858 /* Wakes up vsync event queue */
859 if (atomic_read(&ctx->wait_vsync_event)) {
860 atomic_set(&ctx->wait_vsync_event, 0);
861 wake_up(&ctx->wait_vsync_queue);
862 }
863
864 if (test_bit(0, &ctx->irq_flags))
865 drm_handle_vblank(ctx->drm_dev, ctx->pipe);
866 }
867
868 static void fimd_dp_clock_enable(struct exynos_drm_crtc *crtc, bool enable)
869 {
870 struct fimd_context *ctx = crtc->ctx;
871 u32 val;
872
873 /*
874 * Only Exynos 5250, 5260, 5410 and 542x requires enabling DP/MIE
875 * clock. On these SoCs the bootloader may enable it but any
876 * power domain off/on will reset it to disable state.
877 */
878 if (ctx->driver_data != &exynos5_fimd_driver_data)
879 return;
880
881 val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE;
882 writel(DP_MIE_CLK_DP_ENABLE, ctx->regs + DP_MIE_CLKCON);
883 }
884
885 static const struct exynos_drm_crtc_ops fimd_crtc_ops = {
886 .enable = fimd_enable,
887 .disable = fimd_disable,
888 .mode_fixup = fimd_mode_fixup,
889 .commit = fimd_commit,
890 .enable_vblank = fimd_enable_vblank,
891 .disable_vblank = fimd_disable_vblank,
892 .wait_for_vblank = fimd_wait_for_vblank,
893 .win_commit = fimd_win_commit,
894 .win_disable = fimd_win_disable,
895 .te_handler = fimd_te_handler,
896 .clock_enable = fimd_dp_clock_enable,
897 .clear_channels = fimd_clear_channels,
898 };
899
900 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
901 {
902 struct fimd_context *ctx = (struct fimd_context *)dev_id;
903 u32 val, clear_bit;
904
905 val = readl(ctx->regs + VIDINTCON1);
906
907 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
908 if (val & clear_bit)
909 writel(clear_bit, ctx->regs + VIDINTCON1);
910
911 /* check the crtc is detached already from encoder */
912 if (ctx->pipe < 0 || !ctx->drm_dev)
913 goto out;
914
915 if (ctx->i80_if) {
916 exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
917
918 /* Exits triggering mode */
919 atomic_set(&ctx->triggering, 0);
920 } else {
921 drm_handle_vblank(ctx->drm_dev, ctx->pipe);
922 exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
923
924 /* set wait vsync event to zero and wake up queue. */
925 if (atomic_read(&ctx->wait_vsync_event)) {
926 atomic_set(&ctx->wait_vsync_event, 0);
927 wake_up(&ctx->wait_vsync_queue);
928 }
929 }
930
931 out:
932 return IRQ_HANDLED;
933 }
934
935 static int fimd_bind(struct device *dev, struct device *master, void *data)
936 {
937 struct fimd_context *ctx = dev_get_drvdata(dev);
938 struct drm_device *drm_dev = data;
939 struct exynos_drm_private *priv = drm_dev->dev_private;
940 struct exynos_drm_plane *exynos_plane;
941 enum drm_plane_type type;
942 unsigned int zpos;
943 int ret;
944
945 ctx->drm_dev = drm_dev;
946 ctx->pipe = priv->pipe++;
947
948 for (zpos = 0; zpos < WINDOWS_NR; zpos++) {
949 type = (zpos == ctx->default_win) ? DRM_PLANE_TYPE_PRIMARY :
950 DRM_PLANE_TYPE_OVERLAY;
951 ret = exynos_plane_init(drm_dev, &ctx->planes[zpos],
952 1 << ctx->pipe, type, zpos);
953 if (ret)
954 return ret;
955 }
956
957 exynos_plane = &ctx->planes[ctx->default_win];
958 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
959 ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD,
960 &fimd_crtc_ops, ctx);
961 if (IS_ERR(ctx->crtc))
962 return PTR_ERR(ctx->crtc);
963
964 if (ctx->display)
965 exynos_drm_create_enc_conn(drm_dev, ctx->display);
966
967 ret = drm_iommu_attach_device_if_possible(ctx->crtc, drm_dev, dev);
968 if (ret)
969 priv->pipe--;
970
971 return ret;
972 }
973
974 static void fimd_unbind(struct device *dev, struct device *master,
975 void *data)
976 {
977 struct fimd_context *ctx = dev_get_drvdata(dev);
978
979 fimd_disable(ctx->crtc);
980
981 fimd_iommu_detach_devices(ctx);
982
983 if (ctx->display)
984 exynos_dpi_remove(ctx->display);
985 }
986
987 static const struct component_ops fimd_component_ops = {
988 .bind = fimd_bind,
989 .unbind = fimd_unbind,
990 };
991
992 static int fimd_probe(struct platform_device *pdev)
993 {
994 struct device *dev = &pdev->dev;
995 struct fimd_context *ctx;
996 struct device_node *i80_if_timings;
997 struct resource *res;
998 int ret;
999
1000 if (!dev->of_node)
1001 return -ENODEV;
1002
1003 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1004 if (!ctx)
1005 return -ENOMEM;
1006
1007 ctx->dev = dev;
1008 ctx->suspended = true;
1009 ctx->driver_data = drm_fimd_get_driver_data(pdev);
1010
1011 if (of_property_read_bool(dev->of_node, "samsung,invert-vden"))
1012 ctx->vidcon1 |= VIDCON1_INV_VDEN;
1013 if (of_property_read_bool(dev->of_node, "samsung,invert-vclk"))
1014 ctx->vidcon1 |= VIDCON1_INV_VCLK;
1015
1016 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
1017 if (i80_if_timings) {
1018 u32 val;
1019
1020 ctx->i80_if = true;
1021
1022 if (ctx->driver_data->has_vidoutcon)
1023 ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0;
1024 else
1025 ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0;
1026 /*
1027 * The user manual describes that this "DSI_EN" bit is required
1028 * to enable I80 24-bit data interface.
1029 */
1030 ctx->vidcon0 |= VIDCON0_DSI_EN;
1031
1032 if (of_property_read_u32(i80_if_timings, "cs-setup", &val))
1033 val = 0;
1034 ctx->i80ifcon = LCD_CS_SETUP(val);
1035 if (of_property_read_u32(i80_if_timings, "wr-setup", &val))
1036 val = 0;
1037 ctx->i80ifcon |= LCD_WR_SETUP(val);
1038 if (of_property_read_u32(i80_if_timings, "wr-active", &val))
1039 val = 1;
1040 ctx->i80ifcon |= LCD_WR_ACTIVE(val);
1041 if (of_property_read_u32(i80_if_timings, "wr-hold", &val))
1042 val = 0;
1043 ctx->i80ifcon |= LCD_WR_HOLD(val);
1044 }
1045 of_node_put(i80_if_timings);
1046
1047 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1048 "samsung,sysreg");
1049 if (IS_ERR(ctx->sysreg)) {
1050 dev_warn(dev, "failed to get system register.\n");
1051 ctx->sysreg = NULL;
1052 }
1053
1054 ctx->bus_clk = devm_clk_get(dev, "fimd");
1055 if (IS_ERR(ctx->bus_clk)) {
1056 dev_err(dev, "failed to get bus clock\n");
1057 return PTR_ERR(ctx->bus_clk);
1058 }
1059
1060 ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
1061 if (IS_ERR(ctx->lcd_clk)) {
1062 dev_err(dev, "failed to get lcd clock\n");
1063 return PTR_ERR(ctx->lcd_clk);
1064 }
1065
1066 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1067
1068 ctx->regs = devm_ioremap_resource(dev, res);
1069 if (IS_ERR(ctx->regs))
1070 return PTR_ERR(ctx->regs);
1071
1072 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1073 ctx->i80_if ? "lcd_sys" : "vsync");
1074 if (!res) {
1075 dev_err(dev, "irq request failed.\n");
1076 return -ENXIO;
1077 }
1078
1079 ret = devm_request_irq(dev, res->start, fimd_irq_handler,
1080 0, "drm_fimd", ctx);
1081 if (ret) {
1082 dev_err(dev, "irq request failed.\n");
1083 return ret;
1084 }
1085
1086 init_waitqueue_head(&ctx->wait_vsync_queue);
1087 atomic_set(&ctx->wait_vsync_event, 0);
1088
1089 platform_set_drvdata(pdev, ctx);
1090
1091 ctx->display = exynos_dpi_probe(dev);
1092 if (IS_ERR(ctx->display)) {
1093 return PTR_ERR(ctx->display);
1094 }
1095
1096 pm_runtime_enable(dev);
1097
1098 ret = component_add(dev, &fimd_component_ops);
1099 if (ret)
1100 goto err_disable_pm_runtime;
1101
1102 return ret;
1103
1104 err_disable_pm_runtime:
1105 pm_runtime_disable(dev);
1106
1107 return ret;
1108 }
1109
1110 static int fimd_remove(struct platform_device *pdev)
1111 {
1112 pm_runtime_disable(&pdev->dev);
1113
1114 component_del(&pdev->dev, &fimd_component_ops);
1115
1116 return 0;
1117 }
1118
1119 struct platform_driver fimd_driver = {
1120 .probe = fimd_probe,
1121 .remove = fimd_remove,
1122 .driver = {
1123 .name = "exynos4-fb",
1124 .owner = THIS_MODULE,
1125 .of_match_table = fimd_driver_dt_match,
1126 },
1127 };
Linux kernel - Deliverables
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