3 * Copyright (C) 2011 Samsung Electronics Co.Ltd
5 * Joonyoung Shim <jy0922.shim@samsung.com>
6 * Inki Dae <inki.dae@samsung.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/clk.h>
20 #include <linux/pm_runtime.h>
22 #include <drm/exynos_drm.h>
23 #include <plat/regs-fb-v4.h>
25 #include "exynos_drm_drv.h"
26 #include "exynos_drm_fbdev.h"
27 #include "exynos_drm_crtc.h"
30 * FIMD is stand for Fully Interactive Mobile Display and
31 * as a display controller, it transfers contents drawn on memory
32 * to a LCD Panel through Display Interfaces such as RGB or
36 /* position control register for hardware window 0, 2 ~ 4.*/
37 #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
38 #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
39 /* size control register for hardware window 0. */
40 #define VIDOSD_C_SIZE_W0 (VIDOSD_BASE + 0x08)
41 /* alpha control register for hardware window 1 ~ 4. */
42 #define VIDOSD_C(win) (VIDOSD_BASE + 0x18 + (win) * 16)
43 /* size control register for hardware window 1 ~ 4. */
44 #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
46 #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
47 #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8)
48 #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
50 /* color key control register for hardware window 1 ~ 4. */
51 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + (x * 8))
52 /* color key value register for hardware window 1 ~ 4. */
53 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + (x * 8))
55 /* FIMD has totally five hardware windows. */
58 #define get_fimd_context(dev) platform_get_drvdata(to_platform_device(dev))
60 struct fimd_win_data
{
61 unsigned int offset_x
;
62 unsigned int offset_y
;
63 unsigned int ovl_width
;
64 unsigned int ovl_height
;
65 unsigned int fb_width
;
66 unsigned int fb_height
;
70 unsigned int buf_offsize
;
71 unsigned int line_size
; /* bytes */
76 struct exynos_drm_subdrv subdrv
;
78 struct drm_crtc
*crtc
;
81 struct resource
*regs_res
;
83 struct fimd_win_data win_data
[WINDOWS_NR
];
85 unsigned int default_win
;
86 unsigned long irq_flags
;
92 struct fb_videomode
*timing
;
95 static bool fimd_display_is_connected(struct device
*dev
)
97 DRM_DEBUG_KMS("%s\n", __FILE__
);
104 static void *fimd_get_timing(struct device
*dev
)
106 struct fimd_context
*ctx
= get_fimd_context(dev
);
108 DRM_DEBUG_KMS("%s\n", __FILE__
);
113 static int fimd_check_timing(struct device
*dev
, void *timing
)
115 DRM_DEBUG_KMS("%s\n", __FILE__
);
122 static int fimd_display_power_on(struct device
*dev
, int mode
)
124 DRM_DEBUG_KMS("%s\n", __FILE__
);
131 static struct exynos_drm_display_ops fimd_display_ops
= {
132 .type
= EXYNOS_DISPLAY_TYPE_LCD
,
133 .is_connected
= fimd_display_is_connected
,
134 .get_timing
= fimd_get_timing
,
135 .check_timing
= fimd_check_timing
,
136 .power_on
= fimd_display_power_on
,
139 static void fimd_dpms(struct device
*subdrv_dev
, int mode
)
141 struct fimd_context
*ctx
= get_fimd_context(subdrv_dev
);
143 DRM_DEBUG_KMS("%s, %d\n", __FILE__
, mode
);
145 mutex_lock(&ctx
->lock
);
148 case DRM_MODE_DPMS_ON
:
150 * enable fimd hardware only if suspended status.
152 * P.S. fimd_dpms function would be called at booting time so
153 * clk_enable could be called double time.
156 pm_runtime_get_sync(subdrv_dev
);
158 case DRM_MODE_DPMS_STANDBY
:
159 case DRM_MODE_DPMS_SUSPEND
:
160 case DRM_MODE_DPMS_OFF
:
161 pm_runtime_put_sync(subdrv_dev
);
164 DRM_DEBUG_KMS("unspecified mode %d\n", mode
);
168 mutex_unlock(&ctx
->lock
);
171 static void fimd_apply(struct device
*subdrv_dev
)
173 struct fimd_context
*ctx
= get_fimd_context(subdrv_dev
);
174 struct exynos_drm_manager
*mgr
= &ctx
->subdrv
.manager
;
175 struct exynos_drm_manager_ops
*mgr_ops
= mgr
->ops
;
176 struct exynos_drm_overlay_ops
*ovl_ops
= mgr
->overlay_ops
;
177 struct fimd_win_data
*win_data
;
180 DRM_DEBUG_KMS("%s\n", __FILE__
);
182 for (i
= 0; i
< WINDOWS_NR
; i
++) {
183 win_data
= &ctx
->win_data
[i
];
184 if (win_data
->enabled
&& (ovl_ops
&& ovl_ops
->commit
))
185 ovl_ops
->commit(subdrv_dev
, i
);
188 if (mgr_ops
&& mgr_ops
->commit
)
189 mgr_ops
->commit(subdrv_dev
);
192 static void fimd_commit(struct device
*dev
)
194 struct fimd_context
*ctx
= get_fimd_context(dev
);
195 struct fb_videomode
*timing
= ctx
->timing
;
201 DRM_DEBUG_KMS("%s\n", __FILE__
);
203 /* setup polarity values from machine code. */
204 writel(ctx
->vidcon1
, ctx
->regs
+ VIDCON1
);
206 /* setup vertical timing values. */
207 val
= VIDTCON0_VBPD(timing
->upper_margin
- 1) |
208 VIDTCON0_VFPD(timing
->lower_margin
- 1) |
209 VIDTCON0_VSPW(timing
->vsync_len
- 1);
210 writel(val
, ctx
->regs
+ VIDTCON0
);
212 /* setup horizontal timing values. */
213 val
= VIDTCON1_HBPD(timing
->left_margin
- 1) |
214 VIDTCON1_HFPD(timing
->right_margin
- 1) |
215 VIDTCON1_HSPW(timing
->hsync_len
- 1);
216 writel(val
, ctx
->regs
+ VIDTCON1
);
218 /* setup horizontal and vertical display size. */
219 val
= VIDTCON2_LINEVAL(timing
->yres
- 1) |
220 VIDTCON2_HOZVAL(timing
->xres
- 1);
221 writel(val
, ctx
->regs
+ VIDTCON2
);
223 /* setup clock source, clock divider, enable dma. */
225 val
&= ~(VIDCON0_CLKVAL_F_MASK
| VIDCON0_CLKDIR
);
228 val
|= VIDCON0_CLKVAL_F(ctx
->clkdiv
- 1) | VIDCON0_CLKDIR
;
230 val
&= ~VIDCON0_CLKDIR
; /* 1:1 clock */
233 * fields of register with prefix '_F' would be updated
234 * at vsync(same as dma start)
236 val
|= VIDCON0_ENVID
| VIDCON0_ENVID_F
;
237 writel(val
, ctx
->regs
+ VIDCON0
);
240 static int fimd_enable_vblank(struct device
*dev
)
242 struct fimd_context
*ctx
= get_fimd_context(dev
);
245 DRM_DEBUG_KMS("%s\n", __FILE__
);
250 if (!test_and_set_bit(0, &ctx
->irq_flags
)) {
251 val
= readl(ctx
->regs
+ VIDINTCON0
);
253 val
|= VIDINTCON0_INT_ENABLE
;
254 val
|= VIDINTCON0_INT_FRAME
;
256 val
&= ~VIDINTCON0_FRAMESEL0_MASK
;
257 val
|= VIDINTCON0_FRAMESEL0_VSYNC
;
258 val
&= ~VIDINTCON0_FRAMESEL1_MASK
;
259 val
|= VIDINTCON0_FRAMESEL1_NONE
;
261 writel(val
, ctx
->regs
+ VIDINTCON0
);
267 static void fimd_disable_vblank(struct device
*dev
)
269 struct fimd_context
*ctx
= get_fimd_context(dev
);
272 DRM_DEBUG_KMS("%s\n", __FILE__
);
277 if (test_and_clear_bit(0, &ctx
->irq_flags
)) {
278 val
= readl(ctx
->regs
+ VIDINTCON0
);
280 val
&= ~VIDINTCON0_INT_FRAME
;
281 val
&= ~VIDINTCON0_INT_ENABLE
;
283 writel(val
, ctx
->regs
+ VIDINTCON0
);
287 static struct exynos_drm_manager_ops fimd_manager_ops
= {
290 .commit
= fimd_commit
,
291 .enable_vblank
= fimd_enable_vblank
,
292 .disable_vblank
= fimd_disable_vblank
,
295 static void fimd_win_mode_set(struct device
*dev
,
296 struct exynos_drm_overlay
*overlay
)
298 struct fimd_context
*ctx
= get_fimd_context(dev
);
299 struct fimd_win_data
*win_data
;
301 unsigned long offset
;
303 DRM_DEBUG_KMS("%s\n", __FILE__
);
306 dev_err(dev
, "overlay is NULL\n");
311 if (win
== DEFAULT_ZPOS
)
312 win
= ctx
->default_win
;
314 if (win
< 0 || win
> WINDOWS_NR
)
317 offset
= overlay
->fb_x
* (overlay
->bpp
>> 3);
318 offset
+= overlay
->fb_y
* overlay
->pitch
;
320 DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset
, overlay
->pitch
);
322 win_data
= &ctx
->win_data
[win
];
324 win_data
->offset_x
= overlay
->crtc_x
;
325 win_data
->offset_y
= overlay
->crtc_y
;
326 win_data
->ovl_width
= overlay
->crtc_width
;
327 win_data
->ovl_height
= overlay
->crtc_height
;
328 win_data
->fb_width
= overlay
->fb_width
;
329 win_data
->fb_height
= overlay
->fb_height
;
330 win_data
->dma_addr
= overlay
->dma_addr
[0] + offset
;
331 win_data
->vaddr
= overlay
->vaddr
[0] + offset
;
332 win_data
->bpp
= overlay
->bpp
;
333 win_data
->buf_offsize
= (overlay
->fb_width
- overlay
->crtc_width
) *
335 win_data
->line_size
= overlay
->crtc_width
* (overlay
->bpp
>> 3);
337 DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n",
338 win_data
->offset_x
, win_data
->offset_y
);
339 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
340 win_data
->ovl_width
, win_data
->ovl_height
);
341 DRM_DEBUG_KMS("paddr = 0x%lx, vaddr = 0x%lx\n",
342 (unsigned long)win_data
->dma_addr
,
343 (unsigned long)win_data
->vaddr
);
344 DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n",
345 overlay
->fb_width
, overlay
->crtc_width
);
348 static void fimd_win_set_pixfmt(struct device
*dev
, unsigned int win
)
350 struct fimd_context
*ctx
= get_fimd_context(dev
);
351 struct fimd_win_data
*win_data
= &ctx
->win_data
[win
];
354 DRM_DEBUG_KMS("%s\n", __FILE__
);
358 switch (win_data
->bpp
) {
360 val
|= WINCON0_BPPMODE_1BPP
;
361 val
|= WINCONx_BITSWP
;
362 val
|= WINCONx_BURSTLEN_4WORD
;
365 val
|= WINCON0_BPPMODE_2BPP
;
366 val
|= WINCONx_BITSWP
;
367 val
|= WINCONx_BURSTLEN_8WORD
;
370 val
|= WINCON0_BPPMODE_4BPP
;
371 val
|= WINCONx_BITSWP
;
372 val
|= WINCONx_BURSTLEN_8WORD
;
375 val
|= WINCON0_BPPMODE_8BPP_PALETTE
;
376 val
|= WINCONx_BURSTLEN_8WORD
;
377 val
|= WINCONx_BYTSWP
;
380 val
|= WINCON0_BPPMODE_16BPP_565
;
381 val
|= WINCONx_HAWSWP
;
382 val
|= WINCONx_BURSTLEN_16WORD
;
385 val
|= WINCON0_BPPMODE_24BPP_888
;
387 val
|= WINCONx_BURSTLEN_16WORD
;
390 val
|= WINCON1_BPPMODE_28BPP_A4888
391 | WINCON1_BLD_PIX
| WINCON1_ALPHA_SEL
;
393 val
|= WINCONx_BURSTLEN_16WORD
;
396 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
398 val
|= WINCON0_BPPMODE_24BPP_888
;
400 val
|= WINCONx_BURSTLEN_16WORD
;
404 DRM_DEBUG_KMS("bpp = %d\n", win_data
->bpp
);
406 writel(val
, ctx
->regs
+ WINCON(win
));
409 static void fimd_win_set_colkey(struct device
*dev
, unsigned int win
)
411 struct fimd_context
*ctx
= get_fimd_context(dev
);
412 unsigned int keycon0
= 0, keycon1
= 0;
414 DRM_DEBUG_KMS("%s\n", __FILE__
);
416 keycon0
= ~(WxKEYCON0_KEYBL_EN
| WxKEYCON0_KEYEN_F
|
417 WxKEYCON0_DIRCON
) | WxKEYCON0_COMPKEY(0);
419 keycon1
= WxKEYCON1_COLVAL(0xffffffff);
421 writel(keycon0
, ctx
->regs
+ WKEYCON0_BASE(win
));
422 writel(keycon1
, ctx
->regs
+ WKEYCON1_BASE(win
));
425 static void fimd_win_commit(struct device
*dev
, int zpos
)
427 struct fimd_context
*ctx
= get_fimd_context(dev
);
428 struct fimd_win_data
*win_data
;
430 unsigned long val
, alpha
, size
;
432 DRM_DEBUG_KMS("%s\n", __FILE__
);
437 if (win
== DEFAULT_ZPOS
)
438 win
= ctx
->default_win
;
440 if (win
< 0 || win
> WINDOWS_NR
)
443 win_data
= &ctx
->win_data
[win
];
446 * SHADOWCON register is used for enabling timing.
448 * for example, once only width value of a register is set,
449 * if the dma is started then fimd hardware could malfunction so
450 * with protect window setting, the register fields with prefix '_F'
451 * wouldn't be updated at vsync also but updated once unprotect window
455 /* protect windows */
456 val
= readl(ctx
->regs
+ SHADOWCON
);
457 val
|= SHADOWCON_WINx_PROTECT(win
);
458 writel(val
, ctx
->regs
+ SHADOWCON
);
460 /* buffer start address */
461 val
= (unsigned long)win_data
->dma_addr
;
462 writel(val
, ctx
->regs
+ VIDWx_BUF_START(win
, 0));
464 /* buffer end address */
465 size
= win_data
->fb_width
* win_data
->ovl_height
* (win_data
->bpp
>> 3);
466 val
= (unsigned long)(win_data
->dma_addr
+ size
);
467 writel(val
, ctx
->regs
+ VIDWx_BUF_END(win
, 0));
469 DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
470 (unsigned long)win_data
->dma_addr
, val
, size
);
471 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
472 win_data
->ovl_width
, win_data
->ovl_height
);
475 val
= VIDW_BUF_SIZE_OFFSET(win_data
->buf_offsize
) |
476 VIDW_BUF_SIZE_PAGEWIDTH(win_data
->line_size
);
477 writel(val
, ctx
->regs
+ VIDWx_BUF_SIZE(win
, 0));
480 val
= VIDOSDxA_TOPLEFT_X(win_data
->offset_x
) |
481 VIDOSDxA_TOPLEFT_Y(win_data
->offset_y
);
482 writel(val
, ctx
->regs
+ VIDOSD_A(win
));
484 val
= VIDOSDxB_BOTRIGHT_X(win_data
->offset_x
+
485 win_data
->ovl_width
- 1) |
486 VIDOSDxB_BOTRIGHT_Y(win_data
->offset_y
+
487 win_data
->ovl_height
- 1);
488 writel(val
, ctx
->regs
+ VIDOSD_B(win
));
490 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
491 win_data
->offset_x
, win_data
->offset_y
,
492 win_data
->offset_x
+ win_data
->ovl_width
- 1,
493 win_data
->offset_y
+ win_data
->ovl_height
- 1);
495 /* hardware window 0 doesn't support alpha channel. */
498 alpha
= VIDISD14C_ALPHA1_R(0xf) |
499 VIDISD14C_ALPHA1_G(0xf) |
500 VIDISD14C_ALPHA1_B(0xf);
502 writel(alpha
, ctx
->regs
+ VIDOSD_C(win
));
506 if (win
!= 3 && win
!= 4) {
507 u32 offset
= VIDOSD_D(win
);
509 offset
= VIDOSD_C_SIZE_W0
;
510 val
= win_data
->ovl_width
* win_data
->ovl_height
;
511 writel(val
, ctx
->regs
+ offset
);
513 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val
);
516 fimd_win_set_pixfmt(dev
, win
);
518 /* hardware window 0 doesn't support color key. */
520 fimd_win_set_colkey(dev
, win
);
523 val
= readl(ctx
->regs
+ WINCON(win
));
524 val
|= WINCONx_ENWIN
;
525 writel(val
, ctx
->regs
+ WINCON(win
));
527 /* Enable DMA channel and unprotect windows */
528 val
= readl(ctx
->regs
+ SHADOWCON
);
529 val
|= SHADOWCON_CHx_ENABLE(win
);
530 val
&= ~SHADOWCON_WINx_PROTECT(win
);
531 writel(val
, ctx
->regs
+ SHADOWCON
);
533 win_data
->enabled
= true;
536 static void fimd_win_disable(struct device
*dev
, int zpos
)
538 struct fimd_context
*ctx
= get_fimd_context(dev
);
539 struct fimd_win_data
*win_data
;
543 DRM_DEBUG_KMS("%s\n", __FILE__
);
545 if (win
== DEFAULT_ZPOS
)
546 win
= ctx
->default_win
;
548 if (win
< 0 || win
> WINDOWS_NR
)
551 win_data
= &ctx
->win_data
[win
];
553 /* protect windows */
554 val
= readl(ctx
->regs
+ SHADOWCON
);
555 val
|= SHADOWCON_WINx_PROTECT(win
);
556 writel(val
, ctx
->regs
+ SHADOWCON
);
559 val
= readl(ctx
->regs
+ WINCON(win
));
560 val
&= ~WINCONx_ENWIN
;
561 writel(val
, ctx
->regs
+ WINCON(win
));
563 /* unprotect windows */
564 val
= readl(ctx
->regs
+ SHADOWCON
);
565 val
&= ~SHADOWCON_CHx_ENABLE(win
);
566 val
&= ~SHADOWCON_WINx_PROTECT(win
);
567 writel(val
, ctx
->regs
+ SHADOWCON
);
569 win_data
->enabled
= false;
572 static struct exynos_drm_overlay_ops fimd_overlay_ops
= {
573 .mode_set
= fimd_win_mode_set
,
574 .commit
= fimd_win_commit
,
575 .disable
= fimd_win_disable
,
578 static void fimd_finish_pageflip(struct drm_device
*drm_dev
, int crtc
)
580 struct exynos_drm_private
*dev_priv
= drm_dev
->dev_private
;
581 struct drm_pending_vblank_event
*e
, *t
;
584 bool is_checked
= false;
586 spin_lock_irqsave(&drm_dev
->event_lock
, flags
);
588 list_for_each_entry_safe(e
, t
, &dev_priv
->pageflip_event_list
,
590 /* if event's pipe isn't same as crtc then ignore it. */
596 do_gettimeofday(&now
);
597 e
->event
.sequence
= 0;
598 e
->event
.tv_sec
= now
.tv_sec
;
599 e
->event
.tv_usec
= now
.tv_usec
;
601 list_move_tail(&e
->base
.link
, &e
->base
.file_priv
->event_list
);
602 wake_up_interruptible(&e
->base
.file_priv
->event_wait
);
606 drm_vblank_put(drm_dev
, crtc
);
609 * don't off vblank if vblank_disable_allowed is 1,
610 * because vblank would be off by timer handler.
612 if (!drm_dev
->vblank_disable_allowed
)
613 drm_vblank_off(drm_dev
, crtc
);
616 spin_unlock_irqrestore(&drm_dev
->event_lock
, flags
);
619 static irqreturn_t
fimd_irq_handler(int irq
, void *dev_id
)
621 struct fimd_context
*ctx
= (struct fimd_context
*)dev_id
;
622 struct exynos_drm_subdrv
*subdrv
= &ctx
->subdrv
;
623 struct drm_device
*drm_dev
= subdrv
->drm_dev
;
624 struct exynos_drm_manager
*manager
= &subdrv
->manager
;
627 val
= readl(ctx
->regs
+ VIDINTCON1
);
629 if (val
& VIDINTCON1_INT_FRAME
)
630 /* VSYNC interrupt */
631 writel(VIDINTCON1_INT_FRAME
, ctx
->regs
+ VIDINTCON1
);
633 /* check the crtc is detached already from encoder */
634 if (manager
->pipe
< 0)
637 drm_handle_vblank(drm_dev
, manager
->pipe
);
638 fimd_finish_pageflip(drm_dev
, manager
->pipe
);
644 static int fimd_subdrv_probe(struct drm_device
*drm_dev
, struct device
*dev
)
646 DRM_DEBUG_KMS("%s\n", __FILE__
);
649 * enable drm irq mode.
650 * - with irq_enabled = 1, we can use the vblank feature.
652 * P.S. note that we wouldn't use drm irq handler but
653 * just specific driver own one instead because
654 * drm framework supports only one irq handler.
656 drm_dev
->irq_enabled
= 1;
659 * with vblank_disable_allowed = 1, vblank interrupt will be disabled
660 * by drm timer once a current process gives up ownership of
661 * vblank event.(after drm_vblank_put function is called)
663 drm_dev
->vblank_disable_allowed
= 1;
668 static void fimd_subdrv_remove(struct drm_device
*drm_dev
)
670 DRM_DEBUG_KMS("%s\n", __FILE__
);
675 static int fimd_calc_clkdiv(struct fimd_context
*ctx
,
676 struct fb_videomode
*timing
)
678 unsigned long clk
= clk_get_rate(ctx
->lcd_clk
);
681 u32 best_framerate
= 0;
684 DRM_DEBUG_KMS("%s\n", __FILE__
);
686 retrace
= timing
->left_margin
+ timing
->hsync_len
+
687 timing
->right_margin
+ timing
->xres
;
688 retrace
*= timing
->upper_margin
+ timing
->vsync_len
+
689 timing
->lower_margin
+ timing
->yres
;
691 /* default framerate is 60Hz */
692 if (!timing
->refresh
)
693 timing
->refresh
= 60;
697 for (clkdiv
= 1; clkdiv
< 0x100; clkdiv
++) {
700 /* get best framerate */
701 framerate
= clk
/ clkdiv
;
702 tmp
= timing
->refresh
- framerate
;
704 best_framerate
= framerate
;
708 best_framerate
= framerate
;
709 else if (tmp
< (best_framerate
- framerate
))
710 best_framerate
= framerate
;
718 static void fimd_clear_win(struct fimd_context
*ctx
, int win
)
722 DRM_DEBUG_KMS("%s\n", __FILE__
);
724 writel(0, ctx
->regs
+ WINCON(win
));
725 writel(0, ctx
->regs
+ VIDOSD_A(win
));
726 writel(0, ctx
->regs
+ VIDOSD_B(win
));
727 writel(0, ctx
->regs
+ VIDOSD_C(win
));
729 if (win
== 1 || win
== 2)
730 writel(0, ctx
->regs
+ VIDOSD_D(win
));
732 val
= readl(ctx
->regs
+ SHADOWCON
);
733 val
&= ~SHADOWCON_WINx_PROTECT(win
);
734 writel(val
, ctx
->regs
+ SHADOWCON
);
737 static int __devinit
fimd_probe(struct platform_device
*pdev
)
739 struct device
*dev
= &pdev
->dev
;
740 struct fimd_context
*ctx
;
741 struct exynos_drm_subdrv
*subdrv
;
742 struct exynos_drm_fimd_pdata
*pdata
;
743 struct fb_videomode
*timing
;
744 struct resource
*res
;
748 DRM_DEBUG_KMS("%s\n", __FILE__
);
750 pdata
= pdev
->dev
.platform_data
;
752 dev_err(dev
, "no platform data specified\n");
756 timing
= &pdata
->timing
;
758 dev_err(dev
, "timing is null.\n");
762 ctx
= kzalloc(sizeof(*ctx
), GFP_KERNEL
);
766 ctx
->bus_clk
= clk_get(dev
, "fimd");
767 if (IS_ERR(ctx
->bus_clk
)) {
768 dev_err(dev
, "failed to get bus clock\n");
769 ret
= PTR_ERR(ctx
->bus_clk
);
773 clk_enable(ctx
->bus_clk
);
775 ctx
->lcd_clk
= clk_get(dev
, "sclk_fimd");
776 if (IS_ERR(ctx
->lcd_clk
)) {
777 dev_err(dev
, "failed to get lcd clock\n");
778 ret
= PTR_ERR(ctx
->lcd_clk
);
782 clk_enable(ctx
->lcd_clk
);
784 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
786 dev_err(dev
, "failed to find registers\n");
791 ctx
->regs_res
= request_mem_region(res
->start
, resource_size(res
),
793 if (!ctx
->regs_res
) {
794 dev_err(dev
, "failed to claim register region\n");
799 ctx
->regs
= ioremap(res
->start
, resource_size(res
));
801 dev_err(dev
, "failed to map registers\n");
803 goto err_req_region_io
;
806 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
808 dev_err(dev
, "irq request failed.\n");
809 goto err_req_region_irq
;
812 ctx
->irq
= res
->start
;
814 ret
= request_irq(ctx
->irq
, fimd_irq_handler
, 0, "drm_fimd", ctx
);
816 dev_err(dev
, "irq request failed.\n");
820 ctx
->clkdiv
= fimd_calc_clkdiv(ctx
, timing
);
821 ctx
->vidcon0
= pdata
->vidcon0
;
822 ctx
->vidcon1
= pdata
->vidcon1
;
823 ctx
->default_win
= pdata
->default_win
;
824 ctx
->timing
= timing
;
826 timing
->pixclock
= clk_get_rate(ctx
->lcd_clk
) / ctx
->clkdiv
;
828 DRM_DEBUG_KMS("pixel clock = %d, clkdiv = %d\n",
829 timing
->pixclock
, ctx
->clkdiv
);
831 subdrv
= &ctx
->subdrv
;
833 subdrv
->probe
= fimd_subdrv_probe
;
834 subdrv
->remove
= fimd_subdrv_remove
;
835 subdrv
->manager
.pipe
= -1;
836 subdrv
->manager
.ops
= &fimd_manager_ops
;
837 subdrv
->manager
.overlay_ops
= &fimd_overlay_ops
;
838 subdrv
->manager
.display_ops
= &fimd_display_ops
;
839 subdrv
->manager
.dev
= dev
;
841 mutex_init(&ctx
->lock
);
843 platform_set_drvdata(pdev
, ctx
);
845 pm_runtime_set_active(dev
);
846 pm_runtime_enable(dev
);
847 pm_runtime_get_sync(dev
);
849 for (win
= 0; win
< WINDOWS_NR
; win
++)
850 fimd_clear_win(ctx
, win
);
852 exynos_drm_subdrv_register(subdrv
);
861 release_resource(ctx
->regs_res
);
862 kfree(ctx
->regs_res
);
865 clk_disable(ctx
->lcd_clk
);
866 clk_put(ctx
->lcd_clk
);
869 clk_disable(ctx
->bus_clk
);
870 clk_put(ctx
->bus_clk
);
877 static int __devexit
fimd_remove(struct platform_device
*pdev
)
879 struct device
*dev
= &pdev
->dev
;
880 struct fimd_context
*ctx
= platform_get_drvdata(pdev
);
882 DRM_DEBUG_KMS("%s\n", __FILE__
);
884 exynos_drm_subdrv_unregister(&ctx
->subdrv
);
889 clk_disable(ctx
->lcd_clk
);
890 clk_disable(ctx
->bus_clk
);
892 pm_runtime_set_suspended(dev
);
893 pm_runtime_put_sync(dev
);
896 pm_runtime_disable(dev
);
898 clk_put(ctx
->lcd_clk
);
899 clk_put(ctx
->bus_clk
);
902 release_resource(ctx
->regs_res
);
903 kfree(ctx
->regs_res
);
904 free_irq(ctx
->irq
, ctx
);
911 #ifdef CONFIG_PM_SLEEP
912 static int fimd_suspend(struct device
*dev
)
916 if (pm_runtime_suspended(dev
))
919 ret
= pm_runtime_suspend(dev
);
926 static int fimd_resume(struct device
*dev
)
930 ret
= pm_runtime_resume(dev
);
932 DRM_ERROR("failed to resume runtime pm.\n");
936 pm_runtime_disable(dev
);
938 ret
= pm_runtime_set_active(dev
);
940 DRM_ERROR("failed to active runtime pm.\n");
941 pm_runtime_enable(dev
);
942 pm_runtime_suspend(dev
);
946 pm_runtime_enable(dev
);
952 #ifdef CONFIG_PM_RUNTIME
953 static int fimd_runtime_suspend(struct device
*dev
)
955 struct fimd_context
*ctx
= get_fimd_context(dev
);
957 DRM_DEBUG_KMS("%s\n", __FILE__
);
959 clk_disable(ctx
->lcd_clk
);
960 clk_disable(ctx
->bus_clk
);
962 ctx
->suspended
= true;
966 static int fimd_runtime_resume(struct device
*dev
)
968 struct fimd_context
*ctx
= get_fimd_context(dev
);
971 DRM_DEBUG_KMS("%s\n", __FILE__
);
973 ret
= clk_enable(ctx
->bus_clk
);
977 ret
= clk_enable(ctx
->lcd_clk
);
979 clk_disable(ctx
->bus_clk
);
983 ctx
->suspended
= false;
985 /* if vblank was enabled status, enable it again. */
986 if (test_and_clear_bit(0, &ctx
->irq_flags
))
987 fimd_enable_vblank(dev
);
995 static const struct dev_pm_ops fimd_pm_ops
= {
996 SET_SYSTEM_SLEEP_PM_OPS(fimd_suspend
, fimd_resume
)
997 SET_RUNTIME_PM_OPS(fimd_runtime_suspend
, fimd_runtime_resume
, NULL
)
1000 static struct platform_driver fimd_driver
= {
1001 .probe
= fimd_probe
,
1002 .remove
= __devexit_p(fimd_remove
),
1004 .name
= "exynos4-fb",
1005 .owner
= THIS_MODULE
,
1010 static int __init
fimd_init(void)
1012 return platform_driver_register(&fimd_driver
);
1015 static void __exit
fimd_exit(void)
1017 platform_driver_unregister(&fimd_driver
);
1020 module_init(fimd_init
);
1021 module_exit(fimd_exit
);
1023 MODULE_AUTHOR("Joonyoung Shim <jy0922.shim@samsung.com>");
1024 MODULE_AUTHOR("Inki Dae <inki.dae@samsung.com>");
1025 MODULE_DESCRIPTION("Samsung DRM FIMD Driver");
1026 MODULE_LICENSE("GPL");