3 * Copyright (C) 2011 Samsung Electronics Co.Ltd
5 * Joonyoung Shim <jy0922.shim@samsung.com>
6 * Inki Dae <inki.dae@samsung.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/platform_device.h>
18 #include <linux/clk.h>
20 #include <linux/of_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/component.h>
24 #include <video/of_display_timing.h>
25 #include <video/of_videomode.h>
26 #include <video/samsung_fimd.h>
27 #include <drm/drm_panel.h>
28 #include <drm/exynos_drm.h>
30 #include "exynos_drm_drv.h"
31 #include "exynos_drm_fbdev.h"
32 #include "exynos_drm_crtc.h"
33 #include "exynos_drm_iommu.h"
36 * FIMD stands for Fully Interactive Mobile Display and
37 * as a display controller, it transfers contents drawn on memory
38 * to a LCD Panel through Display Interfaces such as RGB or
42 #define FIMD_DEFAULT_FRAMERATE 60
44 /* position control register for hardware window 0, 2 ~ 4.*/
45 #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
46 #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
48 * size control register for hardware windows 0 and alpha control register
49 * for hardware windows 1 ~ 4
51 #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16)
52 /* size control register for hardware windows 1 ~ 2. */
53 #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
55 #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
56 #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8)
57 #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
59 /* color key control register for hardware window 1 ~ 4. */
60 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8))
61 /* color key value register for hardware window 1 ~ 4. */
62 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
64 /* FIMD has totally five hardware windows. */
67 #define get_fimd_manager(mgr) platform_get_drvdata(to_platform_device(dev))
69 struct fimd_driver_data
{
70 unsigned int timing_base
;
72 unsigned int has_shadowcon
:1;
73 unsigned int has_clksel
:1;
74 unsigned int has_limited_fmt
:1;
77 static struct fimd_driver_data s3c64xx_fimd_driver_data
= {
83 static struct fimd_driver_data exynos4_fimd_driver_data
= {
88 static struct fimd_driver_data exynos5_fimd_driver_data
= {
89 .timing_base
= 0x20000,
93 struct fimd_win_data
{
94 unsigned int offset_x
;
95 unsigned int offset_y
;
96 unsigned int ovl_width
;
97 unsigned int ovl_height
;
98 unsigned int fb_width
;
99 unsigned int fb_height
;
101 unsigned int pixel_format
;
103 unsigned int buf_offsize
;
104 unsigned int line_size
; /* bytes */
109 struct fimd_context
{
111 struct drm_device
*drm_dev
;
115 struct drm_display_mode mode
;
116 struct fimd_win_data win_data
[WINDOWS_NR
];
117 unsigned int default_win
;
118 unsigned long irq_flags
;
122 wait_queue_head_t wait_vsync_queue
;
123 atomic_t wait_vsync_event
;
125 struct exynos_drm_panel_info panel
;
126 struct fimd_driver_data
*driver_data
;
129 static const struct of_device_id fimd_driver_dt_match
[] = {
130 { .compatible
= "samsung,s3c6400-fimd",
131 .data
= &s3c64xx_fimd_driver_data
},
132 { .compatible
= "samsung,exynos4210-fimd",
133 .data
= &exynos4_fimd_driver_data
},
134 { .compatible
= "samsung,exynos5250-fimd",
135 .data
= &exynos5_fimd_driver_data
},
139 static inline struct fimd_driver_data
*drm_fimd_get_driver_data(
140 struct platform_device
*pdev
)
142 const struct of_device_id
*of_id
=
143 of_match_device(fimd_driver_dt_match
, &pdev
->dev
);
145 return (struct fimd_driver_data
*)of_id
->data
;
148 static void fimd_wait_for_vblank(struct exynos_drm_manager
*mgr
)
150 struct fimd_context
*ctx
= mgr
->ctx
;
155 atomic_set(&ctx
->wait_vsync_event
, 1);
158 * wait for FIMD to signal VSYNC interrupt or return after
159 * timeout which is set to 50ms (refresh rate of 20).
161 if (!wait_event_timeout(ctx
->wait_vsync_queue
,
162 !atomic_read(&ctx
->wait_vsync_event
),
164 DRM_DEBUG_KMS("vblank wait timed out.\n");
168 static void fimd_clear_channel(struct exynos_drm_manager
*mgr
)
170 struct fimd_context
*ctx
= mgr
->ctx
;
171 int win
, ch_enabled
= 0;
173 DRM_DEBUG_KMS("%s\n", __FILE__
);
175 /* Check if any channel is enabled. */
176 for (win
= 0; win
< WINDOWS_NR
; win
++) {
177 u32 val
= readl(ctx
->regs
+ SHADOWCON
);
178 if (val
& SHADOWCON_CHx_ENABLE(win
)) {
179 val
&= ~SHADOWCON_CHx_ENABLE(win
);
180 writel(val
, ctx
->regs
+ SHADOWCON
);
185 /* Wait for vsync, as disable channel takes effect at next vsync */
187 fimd_wait_for_vblank(mgr
);
190 static int fimd_mgr_initialize(struct exynos_drm_manager
*mgr
,
191 struct drm_device
*drm_dev
)
193 struct fimd_context
*ctx
= mgr
->ctx
;
194 struct exynos_drm_private
*priv
;
195 priv
= drm_dev
->dev_private
;
197 mgr
->drm_dev
= ctx
->drm_dev
= drm_dev
;
198 mgr
->pipe
= ctx
->pipe
= priv
->pipe
++;
201 * enable drm irq mode.
202 * - with irq_enabled = true, we can use the vblank feature.
204 * P.S. note that we wouldn't use drm irq handler but
205 * just specific driver own one instead because
206 * drm framework supports only one irq handler.
208 drm_dev
->irq_enabled
= true;
211 * with vblank_disable_allowed = true, vblank interrupt will be disabled
212 * by drm timer once a current process gives up ownership of
213 * vblank event.(after drm_vblank_put function is called)
215 drm_dev
->vblank_disable_allowed
= true;
217 /* attach this sub driver to iommu mapping if supported. */
218 if (is_drm_iommu_supported(ctx
->drm_dev
)) {
220 * If any channel is already active, iommu will throw
221 * a PAGE FAULT when enabled. So clear any channel if enabled.
223 fimd_clear_channel(mgr
);
224 drm_iommu_attach_device(ctx
->drm_dev
, ctx
->dev
);
230 static void fimd_mgr_remove(struct exynos_drm_manager
*mgr
)
232 struct fimd_context
*ctx
= mgr
->ctx
;
234 /* detach this sub driver from iommu mapping if supported. */
235 if (is_drm_iommu_supported(ctx
->drm_dev
))
236 drm_iommu_detach_device(ctx
->drm_dev
, ctx
->dev
);
239 static u32
fimd_calc_clkdiv(struct fimd_context
*ctx
,
240 const struct drm_display_mode
*mode
)
242 unsigned long ideal_clk
= mode
->htotal
* mode
->vtotal
* mode
->vrefresh
;
245 /* Find the clock divider value that gets us closest to ideal_clk */
246 clkdiv
= DIV_ROUND_UP(clk_get_rate(ctx
->lcd_clk
), ideal_clk
);
248 return (clkdiv
< 0x100) ? clkdiv
: 0xff;
251 static bool fimd_mode_fixup(struct exynos_drm_manager
*mgr
,
252 const struct drm_display_mode
*mode
,
253 struct drm_display_mode
*adjusted_mode
)
255 if (adjusted_mode
->vrefresh
== 0)
256 adjusted_mode
->vrefresh
= FIMD_DEFAULT_FRAMERATE
;
261 static void fimd_mode_set(struct exynos_drm_manager
*mgr
,
262 const struct drm_display_mode
*in_mode
)
264 struct fimd_context
*ctx
= mgr
->ctx
;
266 drm_mode_copy(&ctx
->mode
, in_mode
);
269 static void fimd_commit(struct exynos_drm_manager
*mgr
)
271 struct fimd_context
*ctx
= mgr
->ctx
;
272 struct drm_display_mode
*mode
= &ctx
->mode
;
273 struct fimd_driver_data
*driver_data
;
274 u32 val
, clkdiv
, vidcon1
;
275 int vsync_len
, vbpd
, vfpd
, hsync_len
, hbpd
, hfpd
;
277 driver_data
= ctx
->driver_data
;
281 /* nothing to do if we haven't set the mode yet */
282 if (mode
->htotal
== 0 || mode
->vtotal
== 0)
285 /* setup polarity values */
286 vidcon1
= ctx
->vidcon1
;
287 if (mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
288 vidcon1
|= VIDCON1_INV_VSYNC
;
289 if (mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
290 vidcon1
|= VIDCON1_INV_HSYNC
;
291 writel(vidcon1
, ctx
->regs
+ driver_data
->timing_base
+ VIDCON1
);
293 /* setup vertical timing values. */
294 vsync_len
= mode
->crtc_vsync_end
- mode
->crtc_vsync_start
;
295 vbpd
= mode
->crtc_vtotal
- mode
->crtc_vsync_end
;
296 vfpd
= mode
->crtc_vsync_start
- mode
->crtc_vdisplay
;
298 val
= VIDTCON0_VBPD(vbpd
- 1) |
299 VIDTCON0_VFPD(vfpd
- 1) |
300 VIDTCON0_VSPW(vsync_len
- 1);
301 writel(val
, ctx
->regs
+ driver_data
->timing_base
+ VIDTCON0
);
303 /* setup horizontal timing values. */
304 hsync_len
= mode
->crtc_hsync_end
- mode
->crtc_hsync_start
;
305 hbpd
= mode
->crtc_htotal
- mode
->crtc_hsync_end
;
306 hfpd
= mode
->crtc_hsync_start
- mode
->crtc_hdisplay
;
308 val
= VIDTCON1_HBPD(hbpd
- 1) |
309 VIDTCON1_HFPD(hfpd
- 1) |
310 VIDTCON1_HSPW(hsync_len
- 1);
311 writel(val
, ctx
->regs
+ driver_data
->timing_base
+ VIDTCON1
);
313 /* setup horizontal and vertical display size. */
314 val
= VIDTCON2_LINEVAL(mode
->vdisplay
- 1) |
315 VIDTCON2_HOZVAL(mode
->hdisplay
- 1) |
316 VIDTCON2_LINEVAL_E(mode
->vdisplay
- 1) |
317 VIDTCON2_HOZVAL_E(mode
->hdisplay
- 1);
318 writel(val
, ctx
->regs
+ driver_data
->timing_base
+ VIDTCON2
);
321 * fields of register with prefix '_F' would be updated
322 * at vsync(same as dma start)
324 val
= VIDCON0_ENVID
| VIDCON0_ENVID_F
;
326 if (ctx
->driver_data
->has_clksel
)
327 val
|= VIDCON0_CLKSEL_LCD
;
329 clkdiv
= fimd_calc_clkdiv(ctx
, mode
);
331 val
|= VIDCON0_CLKVAL_F(clkdiv
- 1) | VIDCON0_CLKDIR
;
333 writel(val
, ctx
->regs
+ VIDCON0
);
336 static int fimd_enable_vblank(struct exynos_drm_manager
*mgr
)
338 struct fimd_context
*ctx
= mgr
->ctx
;
344 if (!test_and_set_bit(0, &ctx
->irq_flags
)) {
345 val
= readl(ctx
->regs
+ VIDINTCON0
);
347 val
|= VIDINTCON0_INT_ENABLE
;
348 val
|= VIDINTCON0_INT_FRAME
;
350 val
&= ~VIDINTCON0_FRAMESEL0_MASK
;
351 val
|= VIDINTCON0_FRAMESEL0_VSYNC
;
352 val
&= ~VIDINTCON0_FRAMESEL1_MASK
;
353 val
|= VIDINTCON0_FRAMESEL1_NONE
;
355 writel(val
, ctx
->regs
+ VIDINTCON0
);
361 static void fimd_disable_vblank(struct exynos_drm_manager
*mgr
)
363 struct fimd_context
*ctx
= mgr
->ctx
;
369 if (test_and_clear_bit(0, &ctx
->irq_flags
)) {
370 val
= readl(ctx
->regs
+ VIDINTCON0
);
372 val
&= ~VIDINTCON0_INT_FRAME
;
373 val
&= ~VIDINTCON0_INT_ENABLE
;
375 writel(val
, ctx
->regs
+ VIDINTCON0
);
379 static void fimd_win_mode_set(struct exynos_drm_manager
*mgr
,
380 struct exynos_drm_overlay
*overlay
)
382 struct fimd_context
*ctx
= mgr
->ctx
;
383 struct fimd_win_data
*win_data
;
385 unsigned long offset
;
388 DRM_ERROR("overlay is NULL\n");
393 if (win
== DEFAULT_ZPOS
)
394 win
= ctx
->default_win
;
396 if (win
< 0 || win
>= WINDOWS_NR
)
399 offset
= overlay
->fb_x
* (overlay
->bpp
>> 3);
400 offset
+= overlay
->fb_y
* overlay
->pitch
;
402 DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset
, overlay
->pitch
);
404 win_data
= &ctx
->win_data
[win
];
406 win_data
->offset_x
= overlay
->crtc_x
;
407 win_data
->offset_y
= overlay
->crtc_y
;
408 win_data
->ovl_width
= overlay
->crtc_width
;
409 win_data
->ovl_height
= overlay
->crtc_height
;
410 win_data
->fb_width
= overlay
->fb_width
;
411 win_data
->fb_height
= overlay
->fb_height
;
412 win_data
->dma_addr
= overlay
->dma_addr
[0] + offset
;
413 win_data
->bpp
= overlay
->bpp
;
414 win_data
->pixel_format
= overlay
->pixel_format
;
415 win_data
->buf_offsize
= (overlay
->fb_width
- overlay
->crtc_width
) *
417 win_data
->line_size
= overlay
->crtc_width
* (overlay
->bpp
>> 3);
419 DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n",
420 win_data
->offset_x
, win_data
->offset_y
);
421 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
422 win_data
->ovl_width
, win_data
->ovl_height
);
423 DRM_DEBUG_KMS("paddr = 0x%lx\n", (unsigned long)win_data
->dma_addr
);
424 DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n",
425 overlay
->fb_width
, overlay
->crtc_width
);
428 static void fimd_win_set_pixfmt(struct fimd_context
*ctx
, unsigned int win
)
430 struct fimd_win_data
*win_data
= &ctx
->win_data
[win
];
436 * In case of s3c64xx, window 0 doesn't support alpha channel.
437 * So the request format is ARGB8888 then change it to XRGB8888.
439 if (ctx
->driver_data
->has_limited_fmt
&& !win
) {
440 if (win_data
->pixel_format
== DRM_FORMAT_ARGB8888
)
441 win_data
->pixel_format
= DRM_FORMAT_XRGB8888
;
444 switch (win_data
->pixel_format
) {
446 val
|= WINCON0_BPPMODE_8BPP_PALETTE
;
447 val
|= WINCONx_BURSTLEN_8WORD
;
448 val
|= WINCONx_BYTSWP
;
450 case DRM_FORMAT_XRGB1555
:
451 val
|= WINCON0_BPPMODE_16BPP_1555
;
452 val
|= WINCONx_HAWSWP
;
453 val
|= WINCONx_BURSTLEN_16WORD
;
455 case DRM_FORMAT_RGB565
:
456 val
|= WINCON0_BPPMODE_16BPP_565
;
457 val
|= WINCONx_HAWSWP
;
458 val
|= WINCONx_BURSTLEN_16WORD
;
460 case DRM_FORMAT_XRGB8888
:
461 val
|= WINCON0_BPPMODE_24BPP_888
;
463 val
|= WINCONx_BURSTLEN_16WORD
;
465 case DRM_FORMAT_ARGB8888
:
466 val
|= WINCON1_BPPMODE_25BPP_A1888
467 | WINCON1_BLD_PIX
| WINCON1_ALPHA_SEL
;
469 val
|= WINCONx_BURSTLEN_16WORD
;
472 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
474 val
|= WINCON0_BPPMODE_24BPP_888
;
476 val
|= WINCONx_BURSTLEN_16WORD
;
480 DRM_DEBUG_KMS("bpp = %d\n", win_data
->bpp
);
482 writel(val
, ctx
->regs
+ WINCON(win
));
485 static void fimd_win_set_colkey(struct fimd_context
*ctx
, unsigned int win
)
487 unsigned int keycon0
= 0, keycon1
= 0;
489 keycon0
= ~(WxKEYCON0_KEYBL_EN
| WxKEYCON0_KEYEN_F
|
490 WxKEYCON0_DIRCON
) | WxKEYCON0_COMPKEY(0);
492 keycon1
= WxKEYCON1_COLVAL(0xffffffff);
494 writel(keycon0
, ctx
->regs
+ WKEYCON0_BASE(win
));
495 writel(keycon1
, ctx
->regs
+ WKEYCON1_BASE(win
));
499 * shadow_protect_win() - disable updating values from shadow registers at vsync
501 * @win: window to protect registers for
502 * @protect: 1 to protect (disable updates)
504 static void fimd_shadow_protect_win(struct fimd_context
*ctx
,
505 int win
, bool protect
)
509 if (ctx
->driver_data
->has_shadowcon
) {
511 bits
= SHADOWCON_WINx_PROTECT(win
);
514 bits
= PRTCON_PROTECT
;
517 val
= readl(ctx
->regs
+ reg
);
522 writel(val
, ctx
->regs
+ reg
);
525 static void fimd_win_commit(struct exynos_drm_manager
*mgr
, int zpos
)
527 struct fimd_context
*ctx
= mgr
->ctx
;
528 struct fimd_win_data
*win_data
;
530 unsigned long val
, alpha
, size
;
537 if (win
== DEFAULT_ZPOS
)
538 win
= ctx
->default_win
;
540 if (win
< 0 || win
>= WINDOWS_NR
)
543 win_data
= &ctx
->win_data
[win
];
545 /* If suspended, enable this on resume */
546 if (ctx
->suspended
) {
547 win_data
->resume
= true;
552 * SHADOWCON/PRTCON register is used for enabling timing.
554 * for example, once only width value of a register is set,
555 * if the dma is started then fimd hardware could malfunction so
556 * with protect window setting, the register fields with prefix '_F'
557 * wouldn't be updated at vsync also but updated once unprotect window
561 /* protect windows */
562 fimd_shadow_protect_win(ctx
, win
, true);
564 /* buffer start address */
565 val
= (unsigned long)win_data
->dma_addr
;
566 writel(val
, ctx
->regs
+ VIDWx_BUF_START(win
, 0));
568 /* buffer end address */
569 size
= win_data
->fb_width
* win_data
->ovl_height
* (win_data
->bpp
>> 3);
570 val
= (unsigned long)(win_data
->dma_addr
+ size
);
571 writel(val
, ctx
->regs
+ VIDWx_BUF_END(win
, 0));
573 DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
574 (unsigned long)win_data
->dma_addr
, val
, size
);
575 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
576 win_data
->ovl_width
, win_data
->ovl_height
);
579 val
= VIDW_BUF_SIZE_OFFSET(win_data
->buf_offsize
) |
580 VIDW_BUF_SIZE_PAGEWIDTH(win_data
->line_size
) |
581 VIDW_BUF_SIZE_OFFSET_E(win_data
->buf_offsize
) |
582 VIDW_BUF_SIZE_PAGEWIDTH_E(win_data
->line_size
);
583 writel(val
, ctx
->regs
+ VIDWx_BUF_SIZE(win
, 0));
586 val
= VIDOSDxA_TOPLEFT_X(win_data
->offset_x
) |
587 VIDOSDxA_TOPLEFT_Y(win_data
->offset_y
) |
588 VIDOSDxA_TOPLEFT_X_E(win_data
->offset_x
) |
589 VIDOSDxA_TOPLEFT_Y_E(win_data
->offset_y
);
590 writel(val
, ctx
->regs
+ VIDOSD_A(win
));
592 last_x
= win_data
->offset_x
+ win_data
->ovl_width
;
595 last_y
= win_data
->offset_y
+ win_data
->ovl_height
;
599 val
= VIDOSDxB_BOTRIGHT_X(last_x
) | VIDOSDxB_BOTRIGHT_Y(last_y
) |
600 VIDOSDxB_BOTRIGHT_X_E(last_x
) | VIDOSDxB_BOTRIGHT_Y_E(last_y
);
602 writel(val
, ctx
->regs
+ VIDOSD_B(win
));
604 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
605 win_data
->offset_x
, win_data
->offset_y
, last_x
, last_y
);
607 /* hardware window 0 doesn't support alpha channel. */
610 alpha
= VIDISD14C_ALPHA1_R(0xf) |
611 VIDISD14C_ALPHA1_G(0xf) |
612 VIDISD14C_ALPHA1_B(0xf);
614 writel(alpha
, ctx
->regs
+ VIDOSD_C(win
));
618 if (win
!= 3 && win
!= 4) {
619 u32 offset
= VIDOSD_D(win
);
621 offset
= VIDOSD_C(win
);
622 val
= win_data
->ovl_width
* win_data
->ovl_height
;
623 writel(val
, ctx
->regs
+ offset
);
625 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val
);
628 fimd_win_set_pixfmt(ctx
, win
);
630 /* hardware window 0 doesn't support color key. */
632 fimd_win_set_colkey(ctx
, win
);
635 val
= readl(ctx
->regs
+ WINCON(win
));
636 val
|= WINCONx_ENWIN
;
637 writel(val
, ctx
->regs
+ WINCON(win
));
639 /* Enable DMA channel and unprotect windows */
640 fimd_shadow_protect_win(ctx
, win
, false);
642 if (ctx
->driver_data
->has_shadowcon
) {
643 val
= readl(ctx
->regs
+ SHADOWCON
);
644 val
|= SHADOWCON_CHx_ENABLE(win
);
645 writel(val
, ctx
->regs
+ SHADOWCON
);
648 win_data
->enabled
= true;
651 static void fimd_win_disable(struct exynos_drm_manager
*mgr
, int zpos
)
653 struct fimd_context
*ctx
= mgr
->ctx
;
654 struct fimd_win_data
*win_data
;
658 if (win
== DEFAULT_ZPOS
)
659 win
= ctx
->default_win
;
661 if (win
< 0 || win
>= WINDOWS_NR
)
664 win_data
= &ctx
->win_data
[win
];
666 if (ctx
->suspended
) {
667 /* do not resume this window*/
668 win_data
->resume
= false;
672 /* protect windows */
673 fimd_shadow_protect_win(ctx
, win
, true);
676 val
= readl(ctx
->regs
+ WINCON(win
));
677 val
&= ~WINCONx_ENWIN
;
678 writel(val
, ctx
->regs
+ WINCON(win
));
680 /* unprotect windows */
681 if (ctx
->driver_data
->has_shadowcon
) {
682 val
= readl(ctx
->regs
+ SHADOWCON
);
683 val
&= ~SHADOWCON_CHx_ENABLE(win
);
684 writel(val
, ctx
->regs
+ SHADOWCON
);
687 fimd_shadow_protect_win(ctx
, win
, false);
689 win_data
->enabled
= false;
692 static void fimd_clear_win(struct fimd_context
*ctx
, int win
)
694 writel(0, ctx
->regs
+ WINCON(win
));
695 writel(0, ctx
->regs
+ VIDOSD_A(win
));
696 writel(0, ctx
->regs
+ VIDOSD_B(win
));
697 writel(0, ctx
->regs
+ VIDOSD_C(win
));
699 if (win
== 1 || win
== 2)
700 writel(0, ctx
->regs
+ VIDOSD_D(win
));
702 fimd_shadow_protect_win(ctx
, win
, false);
705 static void fimd_window_suspend(struct exynos_drm_manager
*mgr
)
707 struct fimd_context
*ctx
= mgr
->ctx
;
708 struct fimd_win_data
*win_data
;
711 for (i
= 0; i
< WINDOWS_NR
; i
++) {
712 win_data
= &ctx
->win_data
[i
];
713 win_data
->resume
= win_data
->enabled
;
714 if (win_data
->enabled
)
715 fimd_win_disable(mgr
, i
);
717 fimd_wait_for_vblank(mgr
);
720 static void fimd_window_resume(struct exynos_drm_manager
*mgr
)
722 struct fimd_context
*ctx
= mgr
->ctx
;
723 struct fimd_win_data
*win_data
;
726 for (i
= 0; i
< WINDOWS_NR
; i
++) {
727 win_data
= &ctx
->win_data
[i
];
728 win_data
->enabled
= win_data
->resume
;
729 win_data
->resume
= false;
733 static void fimd_apply(struct exynos_drm_manager
*mgr
)
735 struct fimd_context
*ctx
= mgr
->ctx
;
736 struct fimd_win_data
*win_data
;
739 for (i
= 0; i
< WINDOWS_NR
; i
++) {
740 win_data
= &ctx
->win_data
[i
];
741 if (win_data
->enabled
)
742 fimd_win_commit(mgr
, i
);
748 static int fimd_poweron(struct exynos_drm_manager
*mgr
)
750 struct fimd_context
*ctx
= mgr
->ctx
;
756 ctx
->suspended
= false;
758 pm_runtime_get_sync(ctx
->dev
);
760 ret
= clk_prepare_enable(ctx
->bus_clk
);
762 DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret
);
766 ret
= clk_prepare_enable(ctx
->lcd_clk
);
768 DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret
);
772 /* if vblank was enabled status, enable it again. */
773 if (test_and_clear_bit(0, &ctx
->irq_flags
)) {
774 ret
= fimd_enable_vblank(mgr
);
776 DRM_ERROR("Failed to re-enable vblank [%d]\n", ret
);
777 goto enable_vblank_err
;
781 fimd_window_resume(mgr
);
788 clk_disable_unprepare(ctx
->lcd_clk
);
790 clk_disable_unprepare(ctx
->bus_clk
);
792 ctx
->suspended
= true;
796 static int fimd_poweroff(struct exynos_drm_manager
*mgr
)
798 struct fimd_context
*ctx
= mgr
->ctx
;
804 * We need to make sure that all windows are disabled before we
805 * suspend that connector. Otherwise we might try to scan from
806 * a destroyed buffer later.
808 fimd_window_suspend(mgr
);
810 clk_disable_unprepare(ctx
->lcd_clk
);
811 clk_disable_unprepare(ctx
->bus_clk
);
813 pm_runtime_put_sync(ctx
->dev
);
815 ctx
->suspended
= true;
819 static void fimd_dpms(struct exynos_drm_manager
*mgr
, int mode
)
821 DRM_DEBUG_KMS("%s, %d\n", __FILE__
, mode
);
824 case DRM_MODE_DPMS_ON
:
827 case DRM_MODE_DPMS_STANDBY
:
828 case DRM_MODE_DPMS_SUSPEND
:
829 case DRM_MODE_DPMS_OFF
:
833 DRM_DEBUG_KMS("unspecified mode %d\n", mode
);
838 static struct exynos_drm_manager_ops fimd_manager_ops
= {
840 .mode_fixup
= fimd_mode_fixup
,
841 .mode_set
= fimd_mode_set
,
842 .commit
= fimd_commit
,
843 .enable_vblank
= fimd_enable_vblank
,
844 .disable_vblank
= fimd_disable_vblank
,
845 .wait_for_vblank
= fimd_wait_for_vblank
,
846 .win_mode_set
= fimd_win_mode_set
,
847 .win_commit
= fimd_win_commit
,
848 .win_disable
= fimd_win_disable
,
851 static struct exynos_drm_manager fimd_manager
= {
852 .type
= EXYNOS_DISPLAY_TYPE_LCD
,
853 .ops
= &fimd_manager_ops
,
856 static irqreturn_t
fimd_irq_handler(int irq
, void *dev_id
)
858 struct fimd_context
*ctx
= (struct fimd_context
*)dev_id
;
861 val
= readl(ctx
->regs
+ VIDINTCON1
);
863 if (val
& VIDINTCON1_INT_FRAME
)
864 /* VSYNC interrupt */
865 writel(VIDINTCON1_INT_FRAME
, ctx
->regs
+ VIDINTCON1
);
867 /* check the crtc is detached already from encoder */
868 if (ctx
->pipe
< 0 || !ctx
->drm_dev
)
871 drm_handle_vblank(ctx
->drm_dev
, ctx
->pipe
);
872 exynos_drm_crtc_finish_pageflip(ctx
->drm_dev
, ctx
->pipe
);
874 /* set wait vsync event to zero and wake up queue. */
875 if (atomic_read(&ctx
->wait_vsync_event
)) {
876 atomic_set(&ctx
->wait_vsync_event
, 0);
877 wake_up(&ctx
->wait_vsync_queue
);
883 static int fimd_bind(struct device
*dev
, struct device
*master
, void *data
)
885 struct platform_device
*pdev
= to_platform_device(dev
);
886 struct drm_device
*drm_dev
= data
;
887 struct fimd_context
*ctx
;
888 struct device_node
*dn
;
889 struct resource
*res
;
896 ctx
= devm_kzalloc(dev
, sizeof(*ctx
), GFP_KERNEL
);
901 ctx
->suspended
= true;
903 if (of_property_read_bool(dev
->of_node
, "samsung,invert-vden"))
904 ctx
->vidcon1
|= VIDCON1_INV_VDEN
;
905 if (of_property_read_bool(dev
->of_node
, "samsung,invert-vclk"))
906 ctx
->vidcon1
|= VIDCON1_INV_VCLK
;
908 ctx
->bus_clk
= devm_clk_get(dev
, "fimd");
909 if (IS_ERR(ctx
->bus_clk
)) {
910 dev_err(dev
, "failed to get bus clock\n");
911 return PTR_ERR(ctx
->bus_clk
);
914 ctx
->lcd_clk
= devm_clk_get(dev
, "sclk_fimd");
915 if (IS_ERR(ctx
->lcd_clk
)) {
916 dev_err(dev
, "failed to get lcd clock\n");
917 return PTR_ERR(ctx
->lcd_clk
);
920 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
922 ctx
->regs
= devm_ioremap_resource(dev
, res
);
923 if (IS_ERR(ctx
->regs
))
924 return PTR_ERR(ctx
->regs
);
926 res
= platform_get_resource_byname(pdev
, IORESOURCE_IRQ
, "vsync");
928 dev_err(dev
, "irq request failed.\n");
932 ret
= devm_request_irq(dev
, res
->start
, fimd_irq_handler
,
935 dev_err(dev
, "irq request failed.\n");
939 ctx
->driver_data
= drm_fimd_get_driver_data(pdev
);
940 init_waitqueue_head(&ctx
->wait_vsync_queue
);
941 atomic_set(&ctx
->wait_vsync_event
, 0);
943 platform_set_drvdata(pdev
, &fimd_manager
);
945 fimd_manager
.ctx
= ctx
;
946 fimd_mgr_initialize(&fimd_manager
, drm_dev
);
948 exynos_drm_crtc_create(&fimd_manager
);
950 dn
= exynos_dpi_of_find_panel_node(&pdev
->dev
);
953 * It should be called after exynos_drm_crtc_create call
954 * because exynos_dpi_probe call will try to find same lcd
955 * type of manager to setup possible_crtcs.
957 exynos_dpi_probe(drm_dev
, dev
);
960 for (win
= 0; win
< WINDOWS_NR
; win
++)
961 fimd_clear_win(ctx
, win
);
966 static void fimd_unbind(struct device
*dev
, struct device
*master
,
969 struct exynos_drm_manager
*mgr
= dev_get_drvdata(dev
);
970 struct drm_crtc
*crtc
= mgr
->crtc
;
971 struct device_node
*dn
;
973 fimd_dpms(mgr
, DRM_MODE_DPMS_OFF
);
975 dn
= exynos_dpi_of_find_panel_node(dev
);
977 exynos_dpi_remove(mgr
->drm_dev
, dev
);
979 fimd_mgr_remove(mgr
);
981 crtc
->funcs
->destroy(crtc
);
984 static const struct component_ops fimd_component_ops
= {
986 .unbind
= fimd_unbind
,
989 static int fimd_probe(struct platform_device
*pdev
)
991 struct device_node
*dn
;
993 /* Check if fimd node has port node. */
994 dn
= exynos_dpi_of_find_panel_node(&pdev
->dev
);
996 struct drm_panel
*panel
;
999 * Do not bind if there is the port node but a drm_panel
1000 * isn't added to panel_list yet.
1001 * In this case, fimd_probe will be called by defered probe
1002 * again after the drm_panel is added to panel_list.
1004 panel
= of_drm_find_panel(dn
);
1006 return -EPROBE_DEFER
;
1009 pm_runtime_enable(&pdev
->dev
);
1011 return exynos_drm_component_add(&pdev
->dev
, &fimd_component_ops
);
1014 static int fimd_remove(struct platform_device
*pdev
)
1016 pm_runtime_disable(&pdev
->dev
);
1018 exynos_drm_component_del(&pdev
->dev
, &fimd_component_ops
);
1022 struct platform_driver fimd_driver
= {
1023 .probe
= fimd_probe
,
1024 .remove
= fimd_remove
,
1026 .name
= "exynos4-fb",
1027 .owner
= THIS_MODULE
,
1028 .of_match_table
= fimd_driver_dt_match
,