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Merge remote-tracking branch 'asoc/fix/max98357a' into asoc-linus
[deliverable/linux.git] / drivers / gpu / drm / exynos / exynos_drm_fimd.c
1 /* exynos_drm_fimd.c
2 *
3 * Copyright (C) 2011 Samsung Electronics Co.Ltd
4 * Authors:
5 * Joonyoung Shim <jy0922.shim@samsung.com>
6 * Inki Dae <inki.dae@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14 #include <drm/drmP.h>
15
16 #include <linux/kernel.h>
17 #include <linux/platform_device.h>
18 #include <linux/clk.h>
19 #include <linux/of.h>
20 #include <linux/of_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/component.h>
23 #include <linux/mfd/syscon.h>
24 #include <linux/regmap.h>
25
26 #include <video/of_display_timing.h>
27 #include <video/of_videomode.h>
28 #include <video/samsung_fimd.h>
29 #include <drm/exynos_drm.h>
30
31 #include "exynos_drm_drv.h"
32 #include "exynos_drm_fbdev.h"
33 #include "exynos_drm_crtc.h"
34 #include "exynos_drm_iommu.h"
35
36 /*
37 * FIMD stands for Fully Interactive Mobile Display and
38 * as a display controller, it transfers contents drawn on memory
39 * to a LCD Panel through Display Interfaces such as RGB or
40 * CPU Interface.
41 */
42
43 #define FIMD_DEFAULT_FRAMERATE 60
44 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
45
46 /* position control register for hardware window 0, 2 ~ 4.*/
47 #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
48 #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
49 /*
50 * size control register for hardware windows 0 and alpha control register
51 * for hardware windows 1 ~ 4
52 */
53 #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16)
54 /* size control register for hardware windows 1 ~ 2. */
55 #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
56
57 #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
58 #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8)
59 #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
60
61 /* color key control register for hardware window 1 ~ 4. */
62 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8))
63 /* color key value register for hardware window 1 ~ 4. */
64 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
65
66 /* I80 / RGB trigger control register */
67 #define TRIGCON 0x1A4
68 #define TRGMODE_I80_RGB_ENABLE_I80 (1 << 0)
69 #define SWTRGCMD_I80_RGB_ENABLE (1 << 1)
70
71 /* display mode change control register except exynos4 */
72 #define VIDOUT_CON 0x000
73 #define VIDOUT_CON_F_I80_LDI0 (0x2 << 8)
74
75 /* I80 interface control for main LDI register */
76 #define I80IFCONFAx(x) (0x1B0 + (x) * 4)
77 #define I80IFCONFBx(x) (0x1B8 + (x) * 4)
78 #define LCD_CS_SETUP(x) ((x) << 16)
79 #define LCD_WR_SETUP(x) ((x) << 12)
80 #define LCD_WR_ACTIVE(x) ((x) << 8)
81 #define LCD_WR_HOLD(x) ((x) << 4)
82 #define I80IFEN_ENABLE (1 << 0)
83
84 /* FIMD has totally five hardware windows. */
85 #define WINDOWS_NR 5
86
87 struct fimd_driver_data {
88 unsigned int timing_base;
89 unsigned int lcdblk_offset;
90 unsigned int lcdblk_vt_shift;
91 unsigned int lcdblk_bypass_shift;
92
93 unsigned int has_shadowcon:1;
94 unsigned int has_clksel:1;
95 unsigned int has_limited_fmt:1;
96 unsigned int has_vidoutcon:1;
97 unsigned int has_vtsel:1;
98 };
99
100 static struct fimd_driver_data s3c64xx_fimd_driver_data = {
101 .timing_base = 0x0,
102 .has_clksel = 1,
103 .has_limited_fmt = 1,
104 };
105
106 static struct fimd_driver_data exynos3_fimd_driver_data = {
107 .timing_base = 0x20000,
108 .lcdblk_offset = 0x210,
109 .lcdblk_bypass_shift = 1,
110 .has_shadowcon = 1,
111 .has_vidoutcon = 1,
112 };
113
114 static struct fimd_driver_data exynos4_fimd_driver_data = {
115 .timing_base = 0x0,
116 .lcdblk_offset = 0x210,
117 .lcdblk_vt_shift = 10,
118 .lcdblk_bypass_shift = 1,
119 .has_shadowcon = 1,
120 .has_vtsel = 1,
121 };
122
123 static struct fimd_driver_data exynos4415_fimd_driver_data = {
124 .timing_base = 0x20000,
125 .lcdblk_offset = 0x210,
126 .lcdblk_vt_shift = 10,
127 .lcdblk_bypass_shift = 1,
128 .has_shadowcon = 1,
129 .has_vidoutcon = 1,
130 .has_vtsel = 1,
131 };
132
133 static struct fimd_driver_data exynos5_fimd_driver_data = {
134 .timing_base = 0x20000,
135 .lcdblk_offset = 0x214,
136 .lcdblk_vt_shift = 24,
137 .lcdblk_bypass_shift = 15,
138 .has_shadowcon = 1,
139 .has_vidoutcon = 1,
140 .has_vtsel = 1,
141 };
142
143 struct fimd_win_data {
144 unsigned int offset_x;
145 unsigned int offset_y;
146 unsigned int ovl_width;
147 unsigned int ovl_height;
148 unsigned int fb_width;
149 unsigned int fb_height;
150 unsigned int bpp;
151 unsigned int pixel_format;
152 dma_addr_t dma_addr;
153 unsigned int buf_offsize;
154 unsigned int line_size; /* bytes */
155 bool enabled;
156 bool resume;
157 };
158
159 struct fimd_context {
160 struct device *dev;
161 struct drm_device *drm_dev;
162 struct exynos_drm_crtc *crtc;
163 struct clk *bus_clk;
164 struct clk *lcd_clk;
165 void __iomem *regs;
166 struct regmap *sysreg;
167 struct fimd_win_data win_data[WINDOWS_NR];
168 unsigned int default_win;
169 unsigned long irq_flags;
170 u32 vidcon0;
171 u32 vidcon1;
172 u32 vidout_con;
173 u32 i80ifcon;
174 bool i80_if;
175 bool suspended;
176 int pipe;
177 wait_queue_head_t wait_vsync_queue;
178 atomic_t wait_vsync_event;
179 atomic_t win_updated;
180 atomic_t triggering;
181
182 struct exynos_drm_panel_info panel;
183 struct fimd_driver_data *driver_data;
184 struct exynos_drm_display *display;
185 };
186
187 static const struct of_device_id fimd_driver_dt_match[] = {
188 { .compatible = "samsung,s3c6400-fimd",
189 .data = &s3c64xx_fimd_driver_data },
190 { .compatible = "samsung,exynos3250-fimd",
191 .data = &exynos3_fimd_driver_data },
192 { .compatible = "samsung,exynos4210-fimd",
193 .data = &exynos4_fimd_driver_data },
194 { .compatible = "samsung,exynos4415-fimd",
195 .data = &exynos4415_fimd_driver_data },
196 { .compatible = "samsung,exynos5250-fimd",
197 .data = &exynos5_fimd_driver_data },
198 {},
199 };
200 MODULE_DEVICE_TABLE(of, fimd_driver_dt_match);
201
202 static inline struct fimd_driver_data *drm_fimd_get_driver_data(
203 struct platform_device *pdev)
204 {
205 const struct of_device_id *of_id =
206 of_match_device(fimd_driver_dt_match, &pdev->dev);
207
208 return (struct fimd_driver_data *)of_id->data;
209 }
210
211 static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc)
212 {
213 struct fimd_context *ctx = crtc->ctx;
214
215 if (ctx->suspended)
216 return;
217
218 atomic_set(&ctx->wait_vsync_event, 1);
219
220 /*
221 * wait for FIMD to signal VSYNC interrupt or return after
222 * timeout which is set to 50ms (refresh rate of 20).
223 */
224 if (!wait_event_timeout(ctx->wait_vsync_queue,
225 !atomic_read(&ctx->wait_vsync_event),
226 HZ/20))
227 DRM_DEBUG_KMS("vblank wait timed out.\n");
228 }
229
230 static void fimd_enable_video_output(struct fimd_context *ctx, int win,
231 bool enable)
232 {
233 u32 val = readl(ctx->regs + WINCON(win));
234
235 if (enable)
236 val |= WINCONx_ENWIN;
237 else
238 val &= ~WINCONx_ENWIN;
239
240 writel(val, ctx->regs + WINCON(win));
241 }
242
243 static void fimd_enable_shadow_channel_path(struct fimd_context *ctx, int win,
244 bool enable)
245 {
246 u32 val = readl(ctx->regs + SHADOWCON);
247
248 if (enable)
249 val |= SHADOWCON_CHx_ENABLE(win);
250 else
251 val &= ~SHADOWCON_CHx_ENABLE(win);
252
253 writel(val, ctx->regs + SHADOWCON);
254 }
255
256 static void fimd_clear_channel(struct fimd_context *ctx)
257 {
258 int win, ch_enabled = 0;
259
260 DRM_DEBUG_KMS("%s\n", __FILE__);
261
262 /* Check if any channel is enabled. */
263 for (win = 0; win < WINDOWS_NR; win++) {
264 u32 val = readl(ctx->regs + WINCON(win));
265
266 if (val & WINCONx_ENWIN) {
267 fimd_enable_video_output(ctx, win, false);
268
269 if (ctx->driver_data->has_shadowcon)
270 fimd_enable_shadow_channel_path(ctx, win,
271 false);
272
273 ch_enabled = 1;
274 }
275 }
276
277 /* Wait for vsync, as disable channel takes effect at next vsync */
278 if (ch_enabled) {
279 unsigned int state = ctx->suspended;
280
281 ctx->suspended = 0;
282 fimd_wait_for_vblank(ctx->crtc);
283 ctx->suspended = state;
284 }
285 }
286
287 static int fimd_ctx_initialize(struct fimd_context *ctx,
288 struct drm_device *drm_dev)
289 {
290 struct exynos_drm_private *priv;
291 priv = drm_dev->dev_private;
292
293 ctx->drm_dev = drm_dev;
294 ctx->pipe = priv->pipe++;
295
296 /* attach this sub driver to iommu mapping if supported. */
297 if (is_drm_iommu_supported(ctx->drm_dev)) {
298 int ret;
299
300 /*
301 * If any channel is already active, iommu will throw
302 * a PAGE FAULT when enabled. So clear any channel if enabled.
303 */
304 fimd_clear_channel(ctx);
305 ret = drm_iommu_attach_device(ctx->drm_dev, ctx->dev);
306 if (ret) {
307 DRM_ERROR("drm_iommu_attach failed.\n");
308 return ret;
309 }
310
311 }
312
313 return 0;
314 }
315
316 static void fimd_ctx_remove(struct fimd_context *ctx)
317 {
318 /* detach this sub driver from iommu mapping if supported. */
319 if (is_drm_iommu_supported(ctx->drm_dev))
320 drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
321 }
322
323 static u32 fimd_calc_clkdiv(struct fimd_context *ctx,
324 const struct drm_display_mode *mode)
325 {
326 unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
327 u32 clkdiv;
328
329 if (ctx->i80_if) {
330 /*
331 * The frame done interrupt should be occurred prior to the
332 * next TE signal.
333 */
334 ideal_clk *= 2;
335 }
336
337 /* Find the clock divider value that gets us closest to ideal_clk */
338 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->lcd_clk), ideal_clk);
339
340 return (clkdiv < 0x100) ? clkdiv : 0xff;
341 }
342
343 static bool fimd_mode_fixup(struct exynos_drm_crtc *crtc,
344 const struct drm_display_mode *mode,
345 struct drm_display_mode *adjusted_mode)
346 {
347 if (adjusted_mode->vrefresh == 0)
348 adjusted_mode->vrefresh = FIMD_DEFAULT_FRAMERATE;
349
350 return true;
351 }
352
353 static void fimd_commit(struct exynos_drm_crtc *crtc)
354 {
355 struct fimd_context *ctx = crtc->ctx;
356 struct drm_display_mode *mode = &crtc->base.mode;
357 struct fimd_driver_data *driver_data = ctx->driver_data;
358 void *timing_base = ctx->regs + driver_data->timing_base;
359 u32 val, clkdiv;
360
361 if (ctx->suspended)
362 return;
363
364 /* nothing to do if we haven't set the mode yet */
365 if (mode->htotal == 0 || mode->vtotal == 0)
366 return;
367
368 if (ctx->i80_if) {
369 val = ctx->i80ifcon | I80IFEN_ENABLE;
370 writel(val, timing_base + I80IFCONFAx(0));
371
372 /* disable auto frame rate */
373 writel(0, timing_base + I80IFCONFBx(0));
374
375 /* set video type selection to I80 interface */
376 if (driver_data->has_vtsel && ctx->sysreg &&
377 regmap_update_bits(ctx->sysreg,
378 driver_data->lcdblk_offset,
379 0x3 << driver_data->lcdblk_vt_shift,
380 0x1 << driver_data->lcdblk_vt_shift)) {
381 DRM_ERROR("Failed to update sysreg for I80 i/f.\n");
382 return;
383 }
384 } else {
385 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
386 u32 vidcon1;
387
388 /* setup polarity values */
389 vidcon1 = ctx->vidcon1;
390 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
391 vidcon1 |= VIDCON1_INV_VSYNC;
392 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
393 vidcon1 |= VIDCON1_INV_HSYNC;
394 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
395
396 /* setup vertical timing values. */
397 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
398 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
399 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
400
401 val = VIDTCON0_VBPD(vbpd - 1) |
402 VIDTCON0_VFPD(vfpd - 1) |
403 VIDTCON0_VSPW(vsync_len - 1);
404 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
405
406 /* setup horizontal timing values. */
407 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
408 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
409 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
410
411 val = VIDTCON1_HBPD(hbpd - 1) |
412 VIDTCON1_HFPD(hfpd - 1) |
413 VIDTCON1_HSPW(hsync_len - 1);
414 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
415 }
416
417 if (driver_data->has_vidoutcon)
418 writel(ctx->vidout_con, timing_base + VIDOUT_CON);
419
420 /* set bypass selection */
421 if (ctx->sysreg && regmap_update_bits(ctx->sysreg,
422 driver_data->lcdblk_offset,
423 0x1 << driver_data->lcdblk_bypass_shift,
424 0x1 << driver_data->lcdblk_bypass_shift)) {
425 DRM_ERROR("Failed to update sysreg for bypass setting.\n");
426 return;
427 }
428
429 /* setup horizontal and vertical display size. */
430 val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
431 VIDTCON2_HOZVAL(mode->hdisplay - 1) |
432 VIDTCON2_LINEVAL_E(mode->vdisplay - 1) |
433 VIDTCON2_HOZVAL_E(mode->hdisplay - 1);
434 writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
435
436 /*
437 * fields of register with prefix '_F' would be updated
438 * at vsync(same as dma start)
439 */
440 val = ctx->vidcon0;
441 val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
442
443 if (ctx->driver_data->has_clksel)
444 val |= VIDCON0_CLKSEL_LCD;
445
446 clkdiv = fimd_calc_clkdiv(ctx, mode);
447 if (clkdiv > 1)
448 val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR;
449
450 writel(val, ctx->regs + VIDCON0);
451 }
452
453 static int fimd_enable_vblank(struct exynos_drm_crtc *crtc)
454 {
455 struct fimd_context *ctx = crtc->ctx;
456 u32 val;
457
458 if (ctx->suspended)
459 return -EPERM;
460
461 if (!test_and_set_bit(0, &ctx->irq_flags)) {
462 val = readl(ctx->regs + VIDINTCON0);
463
464 val |= VIDINTCON0_INT_ENABLE;
465
466 if (ctx->i80_if) {
467 val |= VIDINTCON0_INT_I80IFDONE;
468 val |= VIDINTCON0_INT_SYSMAINCON;
469 val &= ~VIDINTCON0_INT_SYSSUBCON;
470 } else {
471 val |= VIDINTCON0_INT_FRAME;
472
473 val &= ~VIDINTCON0_FRAMESEL0_MASK;
474 val |= VIDINTCON0_FRAMESEL0_VSYNC;
475 val &= ~VIDINTCON0_FRAMESEL1_MASK;
476 val |= VIDINTCON0_FRAMESEL1_NONE;
477 }
478
479 writel(val, ctx->regs + VIDINTCON0);
480 }
481
482 return 0;
483 }
484
485 static void fimd_disable_vblank(struct exynos_drm_crtc *crtc)
486 {
487 struct fimd_context *ctx = crtc->ctx;
488 u32 val;
489
490 if (ctx->suspended)
491 return;
492
493 if (test_and_clear_bit(0, &ctx->irq_flags)) {
494 val = readl(ctx->regs + VIDINTCON0);
495
496 val &= ~VIDINTCON0_INT_ENABLE;
497
498 if (ctx->i80_if) {
499 val &= ~VIDINTCON0_INT_I80IFDONE;
500 val &= ~VIDINTCON0_INT_SYSMAINCON;
501 val &= ~VIDINTCON0_INT_SYSSUBCON;
502 } else
503 val &= ~VIDINTCON0_INT_FRAME;
504
505 writel(val, ctx->regs + VIDINTCON0);
506 }
507 }
508
509 static void fimd_win_mode_set(struct exynos_drm_crtc *crtc,
510 struct exynos_drm_plane *plane)
511 {
512 struct fimd_context *ctx = crtc->ctx;
513 struct fimd_win_data *win_data;
514 int win;
515 unsigned long offset;
516
517 if (!plane) {
518 DRM_ERROR("plane is NULL\n");
519 return;
520 }
521
522 win = plane->zpos;
523 if (win == DEFAULT_ZPOS)
524 win = ctx->default_win;
525
526 if (win < 0 || win >= WINDOWS_NR)
527 return;
528
529 offset = plane->fb_x * (plane->bpp >> 3);
530 offset += plane->fb_y * plane->pitch;
531
532 DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, plane->pitch);
533
534 win_data = &ctx->win_data[win];
535
536 win_data->offset_x = plane->crtc_x;
537 win_data->offset_y = plane->crtc_y;
538 win_data->ovl_width = plane->crtc_width;
539 win_data->ovl_height = plane->crtc_height;
540 win_data->fb_width = plane->fb_width;
541 win_data->fb_height = plane->fb_height;
542 win_data->dma_addr = plane->dma_addr[0] + offset;
543 win_data->bpp = plane->bpp;
544 win_data->pixel_format = plane->pixel_format;
545 win_data->buf_offsize = (plane->fb_width - plane->crtc_width) *
546 (plane->bpp >> 3);
547 win_data->line_size = plane->crtc_width * (plane->bpp >> 3);
548
549 DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n",
550 win_data->offset_x, win_data->offset_y);
551 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
552 win_data->ovl_width, win_data->ovl_height);
553 DRM_DEBUG_KMS("paddr = 0x%lx\n", (unsigned long)win_data->dma_addr);
554 DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n",
555 plane->fb_width, plane->crtc_width);
556 }
557
558 static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win)
559 {
560 struct fimd_win_data *win_data = &ctx->win_data[win];
561 unsigned long val;
562
563 val = WINCONx_ENWIN;
564
565 /*
566 * In case of s3c64xx, window 0 doesn't support alpha channel.
567 * So the request format is ARGB8888 then change it to XRGB8888.
568 */
569 if (ctx->driver_data->has_limited_fmt && !win) {
570 if (win_data->pixel_format == DRM_FORMAT_ARGB8888)
571 win_data->pixel_format = DRM_FORMAT_XRGB8888;
572 }
573
574 switch (win_data->pixel_format) {
575 case DRM_FORMAT_C8:
576 val |= WINCON0_BPPMODE_8BPP_PALETTE;
577 val |= WINCONx_BURSTLEN_8WORD;
578 val |= WINCONx_BYTSWP;
579 break;
580 case DRM_FORMAT_XRGB1555:
581 val |= WINCON0_BPPMODE_16BPP_1555;
582 val |= WINCONx_HAWSWP;
583 val |= WINCONx_BURSTLEN_16WORD;
584 break;
585 case DRM_FORMAT_RGB565:
586 val |= WINCON0_BPPMODE_16BPP_565;
587 val |= WINCONx_HAWSWP;
588 val |= WINCONx_BURSTLEN_16WORD;
589 break;
590 case DRM_FORMAT_XRGB8888:
591 val |= WINCON0_BPPMODE_24BPP_888;
592 val |= WINCONx_WSWP;
593 val |= WINCONx_BURSTLEN_16WORD;
594 break;
595 case DRM_FORMAT_ARGB8888:
596 val |= WINCON1_BPPMODE_25BPP_A1888
597 | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
598 val |= WINCONx_WSWP;
599 val |= WINCONx_BURSTLEN_16WORD;
600 break;
601 default:
602 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
603
604 val |= WINCON0_BPPMODE_24BPP_888;
605 val |= WINCONx_WSWP;
606 val |= WINCONx_BURSTLEN_16WORD;
607 break;
608 }
609
610 DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp);
611
612 /*
613 * In case of exynos, setting dma-burst to 16Word causes permanent
614 * tearing for very small buffers, e.g. cursor buffer. Burst Mode
615 * switching which is based on plane size is not recommended as
616 * plane size varies alot towards the end of the screen and rapid
617 * movement causes unstable DMA which results into iommu crash/tear.
618 */
619
620 if (win_data->fb_width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
621 val &= ~WINCONx_BURSTLEN_MASK;
622 val |= WINCONx_BURSTLEN_4WORD;
623 }
624
625 writel(val, ctx->regs + WINCON(win));
626 }
627
628 static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win)
629 {
630 unsigned int keycon0 = 0, keycon1 = 0;
631
632 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
633 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
634
635 keycon1 = WxKEYCON1_COLVAL(0xffffffff);
636
637 writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
638 writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
639 }
640
641 /**
642 * shadow_protect_win() - disable updating values from shadow registers at vsync
643 *
644 * @win: window to protect registers for
645 * @protect: 1 to protect (disable updates)
646 */
647 static void fimd_shadow_protect_win(struct fimd_context *ctx,
648 int win, bool protect)
649 {
650 u32 reg, bits, val;
651
652 if (ctx->driver_data->has_shadowcon) {
653 reg = SHADOWCON;
654 bits = SHADOWCON_WINx_PROTECT(win);
655 } else {
656 reg = PRTCON;
657 bits = PRTCON_PROTECT;
658 }
659
660 val = readl(ctx->regs + reg);
661 if (protect)
662 val |= bits;
663 else
664 val &= ~bits;
665 writel(val, ctx->regs + reg);
666 }
667
668 static void fimd_win_commit(struct exynos_drm_crtc *crtc, int zpos)
669 {
670 struct fimd_context *ctx = crtc->ctx;
671 struct fimd_win_data *win_data;
672 int win = zpos;
673 unsigned long val, alpha, size;
674 unsigned int last_x;
675 unsigned int last_y;
676
677 if (ctx->suspended)
678 return;
679
680 if (win == DEFAULT_ZPOS)
681 win = ctx->default_win;
682
683 if (win < 0 || win >= WINDOWS_NR)
684 return;
685
686 win_data = &ctx->win_data[win];
687
688 /* If suspended, enable this on resume */
689 if (ctx->suspended) {
690 win_data->resume = true;
691 return;
692 }
693
694 /*
695 * SHADOWCON/PRTCON register is used for enabling timing.
696 *
697 * for example, once only width value of a register is set,
698 * if the dma is started then fimd hardware could malfunction so
699 * with protect window setting, the register fields with prefix '_F'
700 * wouldn't be updated at vsync also but updated once unprotect window
701 * is set.
702 */
703
704 /* protect windows */
705 fimd_shadow_protect_win(ctx, win, true);
706
707 /* buffer start address */
708 val = (unsigned long)win_data->dma_addr;
709 writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
710
711 /* buffer end address */
712 size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3);
713 val = (unsigned long)(win_data->dma_addr + size);
714 writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
715
716 DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
717 (unsigned long)win_data->dma_addr, val, size);
718 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
719 win_data->ovl_width, win_data->ovl_height);
720
721 /* buffer size */
722 val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) |
723 VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size) |
724 VIDW_BUF_SIZE_OFFSET_E(win_data->buf_offsize) |
725 VIDW_BUF_SIZE_PAGEWIDTH_E(win_data->line_size);
726 writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
727
728 /* OSD position */
729 val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) |
730 VIDOSDxA_TOPLEFT_Y(win_data->offset_y) |
731 VIDOSDxA_TOPLEFT_X_E(win_data->offset_x) |
732 VIDOSDxA_TOPLEFT_Y_E(win_data->offset_y);
733 writel(val, ctx->regs + VIDOSD_A(win));
734
735 last_x = win_data->offset_x + win_data->ovl_width;
736 if (last_x)
737 last_x--;
738 last_y = win_data->offset_y + win_data->ovl_height;
739 if (last_y)
740 last_y--;
741
742 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
743 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);
744
745 writel(val, ctx->regs + VIDOSD_B(win));
746
747 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
748 win_data->offset_x, win_data->offset_y, last_x, last_y);
749
750 /* hardware window 0 doesn't support alpha channel. */
751 if (win != 0) {
752 /* OSD alpha */
753 alpha = VIDISD14C_ALPHA1_R(0xf) |
754 VIDISD14C_ALPHA1_G(0xf) |
755 VIDISD14C_ALPHA1_B(0xf);
756
757 writel(alpha, ctx->regs + VIDOSD_C(win));
758 }
759
760 /* OSD size */
761 if (win != 3 && win != 4) {
762 u32 offset = VIDOSD_D(win);
763 if (win == 0)
764 offset = VIDOSD_C(win);
765 val = win_data->ovl_width * win_data->ovl_height;
766 writel(val, ctx->regs + offset);
767
768 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
769 }
770
771 fimd_win_set_pixfmt(ctx, win);
772
773 /* hardware window 0 doesn't support color key. */
774 if (win != 0)
775 fimd_win_set_colkey(ctx, win);
776
777 fimd_enable_video_output(ctx, win, true);
778
779 if (ctx->driver_data->has_shadowcon)
780 fimd_enable_shadow_channel_path(ctx, win, true);
781
782 /* Enable DMA channel and unprotect windows */
783 fimd_shadow_protect_win(ctx, win, false);
784
785 win_data->enabled = true;
786
787 if (ctx->i80_if)
788 atomic_set(&ctx->win_updated, 1);
789 }
790
791 static void fimd_win_disable(struct exynos_drm_crtc *crtc, int zpos)
792 {
793 struct fimd_context *ctx = crtc->ctx;
794 struct fimd_win_data *win_data;
795 int win = zpos;
796
797 if (win == DEFAULT_ZPOS)
798 win = ctx->default_win;
799
800 if (win < 0 || win >= WINDOWS_NR)
801 return;
802
803 win_data = &ctx->win_data[win];
804
805 if (ctx->suspended) {
806 /* do not resume this window*/
807 win_data->resume = false;
808 return;
809 }
810
811 /* protect windows */
812 fimd_shadow_protect_win(ctx, win, true);
813
814 fimd_enable_video_output(ctx, win, false);
815
816 if (ctx->driver_data->has_shadowcon)
817 fimd_enable_shadow_channel_path(ctx, win, false);
818
819 /* unprotect windows */
820 fimd_shadow_protect_win(ctx, win, false);
821
822 win_data->enabled = false;
823 }
824
825 static void fimd_window_suspend(struct fimd_context *ctx)
826 {
827 struct fimd_win_data *win_data;
828 int i;
829
830 for (i = 0; i < WINDOWS_NR; i++) {
831 win_data = &ctx->win_data[i];
832 win_data->resume = win_data->enabled;
833 if (win_data->enabled)
834 fimd_win_disable(ctx->crtc, i);
835 }
836 }
837
838 static void fimd_window_resume(struct fimd_context *ctx)
839 {
840 struct fimd_win_data *win_data;
841 int i;
842
843 for (i = 0; i < WINDOWS_NR; i++) {
844 win_data = &ctx->win_data[i];
845 win_data->enabled = win_data->resume;
846 win_data->resume = false;
847 }
848 }
849
850 static void fimd_apply(struct fimd_context *ctx)
851 {
852 struct fimd_win_data *win_data;
853 int i;
854
855 for (i = 0; i < WINDOWS_NR; i++) {
856 win_data = &ctx->win_data[i];
857 if (win_data->enabled)
858 fimd_win_commit(ctx->crtc, i);
859 else
860 fimd_win_disable(ctx->crtc, i);
861 }
862
863 fimd_commit(ctx->crtc);
864 }
865
866 static int fimd_poweron(struct fimd_context *ctx)
867 {
868 int ret;
869
870 if (!ctx->suspended)
871 return 0;
872
873 ctx->suspended = false;
874
875 pm_runtime_get_sync(ctx->dev);
876
877 ret = clk_prepare_enable(ctx->bus_clk);
878 if (ret < 0) {
879 DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret);
880 goto bus_clk_err;
881 }
882
883 ret = clk_prepare_enable(ctx->lcd_clk);
884 if (ret < 0) {
885 DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret);
886 goto lcd_clk_err;
887 }
888
889 /* if vblank was enabled status, enable it again. */
890 if (test_and_clear_bit(0, &ctx->irq_flags)) {
891 ret = fimd_enable_vblank(ctx->crtc);
892 if (ret) {
893 DRM_ERROR("Failed to re-enable vblank [%d]\n", ret);
894 goto enable_vblank_err;
895 }
896 }
897
898 fimd_window_resume(ctx);
899
900 fimd_apply(ctx);
901
902 return 0;
903
904 enable_vblank_err:
905 clk_disable_unprepare(ctx->lcd_clk);
906 lcd_clk_err:
907 clk_disable_unprepare(ctx->bus_clk);
908 bus_clk_err:
909 ctx->suspended = true;
910 return ret;
911 }
912
913 static int fimd_poweroff(struct fimd_context *ctx)
914 {
915 if (ctx->suspended)
916 return 0;
917
918 /*
919 * We need to make sure that all windows are disabled before we
920 * suspend that connector. Otherwise we might try to scan from
921 * a destroyed buffer later.
922 */
923 fimd_window_suspend(ctx);
924
925 clk_disable_unprepare(ctx->lcd_clk);
926 clk_disable_unprepare(ctx->bus_clk);
927
928 pm_runtime_put_sync(ctx->dev);
929
930 ctx->suspended = true;
931 return 0;
932 }
933
934 static void fimd_dpms(struct exynos_drm_crtc *crtc, int mode)
935 {
936 DRM_DEBUG_KMS("%s, %d\n", __FILE__, mode);
937
938 switch (mode) {
939 case DRM_MODE_DPMS_ON:
940 fimd_poweron(crtc->ctx);
941 break;
942 case DRM_MODE_DPMS_STANDBY:
943 case DRM_MODE_DPMS_SUSPEND:
944 case DRM_MODE_DPMS_OFF:
945 fimd_poweroff(crtc->ctx);
946 break;
947 default:
948 DRM_DEBUG_KMS("unspecified mode %d\n", mode);
949 break;
950 }
951 }
952
953 static void fimd_trigger(struct device *dev)
954 {
955 struct fimd_context *ctx = dev_get_drvdata(dev);
956 struct fimd_driver_data *driver_data = ctx->driver_data;
957 void *timing_base = ctx->regs + driver_data->timing_base;
958 u32 reg;
959
960 /*
961 * Skips triggering if in triggering state, because multiple triggering
962 * requests can cause panel reset.
963 */
964 if (atomic_read(&ctx->triggering))
965 return;
966
967 /* Enters triggering mode */
968 atomic_set(&ctx->triggering, 1);
969
970 reg = readl(timing_base + TRIGCON);
971 reg |= (TRGMODE_I80_RGB_ENABLE_I80 | SWTRGCMD_I80_RGB_ENABLE);
972 writel(reg, timing_base + TRIGCON);
973
974 /*
975 * Exits triggering mode if vblank is not enabled yet, because when the
976 * VIDINTCON0 register is not set, it can not exit from triggering mode.
977 */
978 if (!test_bit(0, &ctx->irq_flags))
979 atomic_set(&ctx->triggering, 0);
980 }
981
982 static void fimd_te_handler(struct exynos_drm_crtc *crtc)
983 {
984 struct fimd_context *ctx = crtc->ctx;
985
986 /* Checks the crtc is detached already from encoder */
987 if (ctx->pipe < 0 || !ctx->drm_dev)
988 return;
989
990 /*
991 * If there is a page flip request, triggers and handles the page flip
992 * event so that current fb can be updated into panel GRAM.
993 */
994 if (atomic_add_unless(&ctx->win_updated, -1, 0))
995 fimd_trigger(ctx->dev);
996
997 /* Wakes up vsync event queue */
998 if (atomic_read(&ctx->wait_vsync_event)) {
999 atomic_set(&ctx->wait_vsync_event, 0);
1000 wake_up(&ctx->wait_vsync_queue);
1001 }
1002
1003 if (test_bit(0, &ctx->irq_flags))
1004 drm_handle_vblank(ctx->drm_dev, ctx->pipe);
1005 }
1006
1007 static struct exynos_drm_crtc_ops fimd_crtc_ops = {
1008 .dpms = fimd_dpms,
1009 .mode_fixup = fimd_mode_fixup,
1010 .commit = fimd_commit,
1011 .enable_vblank = fimd_enable_vblank,
1012 .disable_vblank = fimd_disable_vblank,
1013 .wait_for_vblank = fimd_wait_for_vblank,
1014 .win_mode_set = fimd_win_mode_set,
1015 .win_commit = fimd_win_commit,
1016 .win_disable = fimd_win_disable,
1017 .te_handler = fimd_te_handler,
1018 };
1019
1020 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
1021 {
1022 struct fimd_context *ctx = (struct fimd_context *)dev_id;
1023 u32 val, clear_bit;
1024
1025 val = readl(ctx->regs + VIDINTCON1);
1026
1027 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
1028 if (val & clear_bit)
1029 writel(clear_bit, ctx->regs + VIDINTCON1);
1030
1031 /* check the crtc is detached already from encoder */
1032 if (ctx->pipe < 0 || !ctx->drm_dev)
1033 goto out;
1034
1035 if (ctx->i80_if) {
1036 exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
1037
1038 /* Exits triggering mode */
1039 atomic_set(&ctx->triggering, 0);
1040 } else {
1041 drm_handle_vblank(ctx->drm_dev, ctx->pipe);
1042 exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
1043
1044 /* set wait vsync event to zero and wake up queue. */
1045 if (atomic_read(&ctx->wait_vsync_event)) {
1046 atomic_set(&ctx->wait_vsync_event, 0);
1047 wake_up(&ctx->wait_vsync_queue);
1048 }
1049 }
1050
1051 out:
1052 return IRQ_HANDLED;
1053 }
1054
1055 static int fimd_bind(struct device *dev, struct device *master, void *data)
1056 {
1057 struct fimd_context *ctx = dev_get_drvdata(dev);
1058 struct drm_device *drm_dev = data;
1059 int ret;
1060
1061 ret = fimd_ctx_initialize(ctx, drm_dev);
1062 if (ret) {
1063 DRM_ERROR("fimd_ctx_initialize failed.\n");
1064 return ret;
1065 }
1066
1067 ctx->crtc = exynos_drm_crtc_create(drm_dev, ctx->pipe,
1068 EXYNOS_DISPLAY_TYPE_LCD,
1069 &fimd_crtc_ops, ctx);
1070 if (IS_ERR(ctx->crtc)) {
1071 fimd_ctx_remove(ctx);
1072 return PTR_ERR(ctx->crtc);
1073 }
1074
1075 if (ctx->display)
1076 exynos_drm_create_enc_conn(drm_dev, ctx->display);
1077
1078 return 0;
1079
1080 }
1081
1082 static void fimd_unbind(struct device *dev, struct device *master,
1083 void *data)
1084 {
1085 struct fimd_context *ctx = dev_get_drvdata(dev);
1086
1087 fimd_dpms(ctx->crtc, DRM_MODE_DPMS_OFF);
1088
1089 if (ctx->display)
1090 exynos_dpi_remove(ctx->display);
1091
1092 fimd_ctx_remove(ctx);
1093 }
1094
1095 static const struct component_ops fimd_component_ops = {
1096 .bind = fimd_bind,
1097 .unbind = fimd_unbind,
1098 };
1099
1100 static int fimd_probe(struct platform_device *pdev)
1101 {
1102 struct device *dev = &pdev->dev;
1103 struct fimd_context *ctx;
1104 struct device_node *i80_if_timings;
1105 struct resource *res;
1106 int ret;
1107
1108 if (!dev->of_node)
1109 return -ENODEV;
1110
1111 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1112 if (!ctx)
1113 return -ENOMEM;
1114
1115 ret = exynos_drm_component_add(dev, EXYNOS_DEVICE_TYPE_CRTC,
1116 EXYNOS_DISPLAY_TYPE_LCD);
1117 if (ret)
1118 return ret;
1119
1120 ctx->dev = dev;
1121 ctx->suspended = true;
1122 ctx->driver_data = drm_fimd_get_driver_data(pdev);
1123
1124 if (of_property_read_bool(dev->of_node, "samsung,invert-vden"))
1125 ctx->vidcon1 |= VIDCON1_INV_VDEN;
1126 if (of_property_read_bool(dev->of_node, "samsung,invert-vclk"))
1127 ctx->vidcon1 |= VIDCON1_INV_VCLK;
1128
1129 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
1130 if (i80_if_timings) {
1131 u32 val;
1132
1133 ctx->i80_if = true;
1134
1135 if (ctx->driver_data->has_vidoutcon)
1136 ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0;
1137 else
1138 ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0;
1139 /*
1140 * The user manual describes that this "DSI_EN" bit is required
1141 * to enable I80 24-bit data interface.
1142 */
1143 ctx->vidcon0 |= VIDCON0_DSI_EN;
1144
1145 if (of_property_read_u32(i80_if_timings, "cs-setup", &val))
1146 val = 0;
1147 ctx->i80ifcon = LCD_CS_SETUP(val);
1148 if (of_property_read_u32(i80_if_timings, "wr-setup", &val))
1149 val = 0;
1150 ctx->i80ifcon |= LCD_WR_SETUP(val);
1151 if (of_property_read_u32(i80_if_timings, "wr-active", &val))
1152 val = 1;
1153 ctx->i80ifcon |= LCD_WR_ACTIVE(val);
1154 if (of_property_read_u32(i80_if_timings, "wr-hold", &val))
1155 val = 0;
1156 ctx->i80ifcon |= LCD_WR_HOLD(val);
1157 }
1158 of_node_put(i80_if_timings);
1159
1160 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1161 "samsung,sysreg");
1162 if (IS_ERR(ctx->sysreg)) {
1163 dev_warn(dev, "failed to get system register.\n");
1164 ctx->sysreg = NULL;
1165 }
1166
1167 ctx->bus_clk = devm_clk_get(dev, "fimd");
1168 if (IS_ERR(ctx->bus_clk)) {
1169 dev_err(dev, "failed to get bus clock\n");
1170 ret = PTR_ERR(ctx->bus_clk);
1171 goto err_del_component;
1172 }
1173
1174 ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
1175 if (IS_ERR(ctx->lcd_clk)) {
1176 dev_err(dev, "failed to get lcd clock\n");
1177 ret = PTR_ERR(ctx->lcd_clk);
1178 goto err_del_component;
1179 }
1180
1181 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1182
1183 ctx->regs = devm_ioremap_resource(dev, res);
1184 if (IS_ERR(ctx->regs)) {
1185 ret = PTR_ERR(ctx->regs);
1186 goto err_del_component;
1187 }
1188
1189 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1190 ctx->i80_if ? "lcd_sys" : "vsync");
1191 if (!res) {
1192 dev_err(dev, "irq request failed.\n");
1193 ret = -ENXIO;
1194 goto err_del_component;
1195 }
1196
1197 ret = devm_request_irq(dev, res->start, fimd_irq_handler,
1198 0, "drm_fimd", ctx);
1199 if (ret) {
1200 dev_err(dev, "irq request failed.\n");
1201 goto err_del_component;
1202 }
1203
1204 init_waitqueue_head(&ctx->wait_vsync_queue);
1205 atomic_set(&ctx->wait_vsync_event, 0);
1206
1207 platform_set_drvdata(pdev, ctx);
1208
1209 ctx->display = exynos_dpi_probe(dev);
1210 if (IS_ERR(ctx->display)) {
1211 ret = PTR_ERR(ctx->display);
1212 goto err_del_component;
1213 }
1214
1215 pm_runtime_enable(dev);
1216
1217 ret = component_add(dev, &fimd_component_ops);
1218 if (ret)
1219 goto err_disable_pm_runtime;
1220
1221 return ret;
1222
1223 err_disable_pm_runtime:
1224 pm_runtime_disable(dev);
1225
1226 err_del_component:
1227 exynos_drm_component_del(dev, EXYNOS_DEVICE_TYPE_CRTC);
1228 return ret;
1229 }
1230
1231 static int fimd_remove(struct platform_device *pdev)
1232 {
1233 pm_runtime_disable(&pdev->dev);
1234
1235 component_del(&pdev->dev, &fimd_component_ops);
1236 exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC);
1237
1238 return 0;
1239 }
1240
1241 struct platform_driver fimd_driver = {
1242 .probe = fimd_probe,
1243 .remove = fimd_remove,
1244 .driver = {
1245 .name = "exynos4-fb",
1246 .owner = THIS_MODULE,
1247 .of_match_table = fimd_driver_dt_match,
1248 },
1249 };
Linux kernel - Deliverables
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