3 * Copyright (C) 2011 Samsung Electronics Co.Ltd
5 * Joonyoung Shim <jy0922.shim@samsung.com>
6 * Inki Dae <inki.dae@samsung.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/clk.h>
20 #include <linux/pm_runtime.h>
22 #include <video/samsung_fimd.h>
23 #include <drm/exynos_drm.h>
25 #include "exynos_drm_drv.h"
26 #include "exynos_drm_fbdev.h"
27 #include "exynos_drm_crtc.h"
28 #include "exynos_drm_iommu.h"
31 * FIMD is stand for Fully Interactive Mobile Display and
32 * as a display controller, it transfers contents drawn on memory
33 * to a LCD Panel through Display Interfaces such as RGB or
37 /* position control register for hardware window 0, 2 ~ 4.*/
38 #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
39 #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
40 /* size control register for hardware window 0. */
41 #define VIDOSD_C_SIZE_W0 (VIDOSD_BASE + 0x08)
42 /* alpha control register for hardware window 1 ~ 4. */
43 #define VIDOSD_C(win) (VIDOSD_BASE + 0x18 + (win) * 16)
44 /* size control register for hardware window 1 ~ 4. */
45 #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
47 #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
48 #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8)
49 #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
51 /* color key control register for hardware window 1 ~ 4. */
52 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + (x * 8))
53 /* color key value register for hardware window 1 ~ 4. */
54 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + (x * 8))
56 /* FIMD has totally five hardware windows. */
59 #define get_fimd_context(dev) platform_get_drvdata(to_platform_device(dev))
61 struct fimd_driver_data
{
62 unsigned int timing_base
;
65 static struct fimd_driver_data exynos4_fimd_driver_data
= {
69 static struct fimd_driver_data exynos5_fimd_driver_data
= {
70 .timing_base
= 0x20000,
73 struct fimd_win_data
{
74 unsigned int offset_x
;
75 unsigned int offset_y
;
76 unsigned int ovl_width
;
77 unsigned int ovl_height
;
78 unsigned int fb_width
;
79 unsigned int fb_height
;
82 unsigned int buf_offsize
;
83 unsigned int line_size
; /* bytes */
89 struct exynos_drm_subdrv subdrv
;
91 struct drm_crtc
*crtc
;
95 struct fimd_win_data win_data
[WINDOWS_NR
];
97 unsigned int default_win
;
98 unsigned long irq_flags
;
103 wait_queue_head_t wait_vsync_queue
;
104 atomic_t wait_vsync_event
;
106 struct exynos_drm_panel_info
*panel
;
109 static inline struct fimd_driver_data
*drm_fimd_get_driver_data(
110 struct platform_device
*pdev
)
112 return (struct fimd_driver_data
*)
113 platform_get_device_id(pdev
)->driver_data
;
116 static bool fimd_display_is_connected(struct device
*dev
)
118 DRM_DEBUG_KMS("%s\n", __FILE__
);
125 static void *fimd_get_panel(struct device
*dev
)
127 struct fimd_context
*ctx
= get_fimd_context(dev
);
129 DRM_DEBUG_KMS("%s\n", __FILE__
);
134 static int fimd_check_timing(struct device
*dev
, void *timing
)
136 DRM_DEBUG_KMS("%s\n", __FILE__
);
143 static int fimd_display_power_on(struct device
*dev
, int mode
)
145 DRM_DEBUG_KMS("%s\n", __FILE__
);
152 static struct exynos_drm_display_ops fimd_display_ops
= {
153 .type
= EXYNOS_DISPLAY_TYPE_LCD
,
154 .is_connected
= fimd_display_is_connected
,
155 .get_panel
= fimd_get_panel
,
156 .check_timing
= fimd_check_timing
,
157 .power_on
= fimd_display_power_on
,
160 static void fimd_dpms(struct device
*subdrv_dev
, int mode
)
162 struct fimd_context
*ctx
= get_fimd_context(subdrv_dev
);
164 DRM_DEBUG_KMS("%s, %d\n", __FILE__
, mode
);
166 mutex_lock(&ctx
->lock
);
169 case DRM_MODE_DPMS_ON
:
171 * enable fimd hardware only if suspended status.
173 * P.S. fimd_dpms function would be called at booting time so
174 * clk_enable could be called double time.
177 pm_runtime_get_sync(subdrv_dev
);
179 case DRM_MODE_DPMS_STANDBY
:
180 case DRM_MODE_DPMS_SUSPEND
:
181 case DRM_MODE_DPMS_OFF
:
183 pm_runtime_put_sync(subdrv_dev
);
186 DRM_DEBUG_KMS("unspecified mode %d\n", mode
);
190 mutex_unlock(&ctx
->lock
);
193 static void fimd_apply(struct device
*subdrv_dev
)
195 struct fimd_context
*ctx
= get_fimd_context(subdrv_dev
);
196 struct exynos_drm_manager
*mgr
= ctx
->subdrv
.manager
;
197 struct exynos_drm_manager_ops
*mgr_ops
= mgr
->ops
;
198 struct exynos_drm_overlay_ops
*ovl_ops
= mgr
->overlay_ops
;
199 struct fimd_win_data
*win_data
;
202 DRM_DEBUG_KMS("%s\n", __FILE__
);
204 for (i
= 0; i
< WINDOWS_NR
; i
++) {
205 win_data
= &ctx
->win_data
[i
];
206 if (win_data
->enabled
&& (ovl_ops
&& ovl_ops
->commit
))
207 ovl_ops
->commit(subdrv_dev
, i
);
210 if (mgr_ops
&& mgr_ops
->commit
)
211 mgr_ops
->commit(subdrv_dev
);
214 static void fimd_commit(struct device
*dev
)
216 struct fimd_context
*ctx
= get_fimd_context(dev
);
217 struct exynos_drm_panel_info
*panel
= ctx
->panel
;
218 struct fb_videomode
*timing
= &panel
->timing
;
219 struct fimd_driver_data
*driver_data
;
220 struct platform_device
*pdev
= to_platform_device(dev
);
223 driver_data
= drm_fimd_get_driver_data(pdev
);
227 DRM_DEBUG_KMS("%s\n", __FILE__
);
229 /* setup polarity values from machine code. */
230 writel(ctx
->vidcon1
, ctx
->regs
+ driver_data
->timing_base
+ VIDCON1
);
232 /* setup vertical timing values. */
233 val
= VIDTCON0_VBPD(timing
->upper_margin
- 1) |
234 VIDTCON0_VFPD(timing
->lower_margin
- 1) |
235 VIDTCON0_VSPW(timing
->vsync_len
- 1);
236 writel(val
, ctx
->regs
+ driver_data
->timing_base
+ VIDTCON0
);
238 /* setup horizontal timing values. */
239 val
= VIDTCON1_HBPD(timing
->left_margin
- 1) |
240 VIDTCON1_HFPD(timing
->right_margin
- 1) |
241 VIDTCON1_HSPW(timing
->hsync_len
- 1);
242 writel(val
, ctx
->regs
+ driver_data
->timing_base
+ VIDTCON1
);
244 /* setup horizontal and vertical display size. */
245 val
= VIDTCON2_LINEVAL(timing
->yres
- 1) |
246 VIDTCON2_HOZVAL(timing
->xres
- 1);
247 writel(val
, ctx
->regs
+ driver_data
->timing_base
+ VIDTCON2
);
249 /* setup clock source, clock divider, enable dma. */
251 val
&= ~(VIDCON0_CLKVAL_F_MASK
| VIDCON0_CLKDIR
);
254 val
|= VIDCON0_CLKVAL_F(ctx
->clkdiv
- 1) | VIDCON0_CLKDIR
;
256 val
&= ~VIDCON0_CLKDIR
; /* 1:1 clock */
259 * fields of register with prefix '_F' would be updated
260 * at vsync(same as dma start)
262 val
|= VIDCON0_ENVID
| VIDCON0_ENVID_F
;
263 writel(val
, ctx
->regs
+ VIDCON0
);
266 static int fimd_enable_vblank(struct device
*dev
)
268 struct fimd_context
*ctx
= get_fimd_context(dev
);
271 DRM_DEBUG_KMS("%s\n", __FILE__
);
276 if (!test_and_set_bit(0, &ctx
->irq_flags
)) {
277 val
= readl(ctx
->regs
+ VIDINTCON0
);
279 val
|= VIDINTCON0_INT_ENABLE
;
280 val
|= VIDINTCON0_INT_FRAME
;
282 val
&= ~VIDINTCON0_FRAMESEL0_MASK
;
283 val
|= VIDINTCON0_FRAMESEL0_VSYNC
;
284 val
&= ~VIDINTCON0_FRAMESEL1_MASK
;
285 val
|= VIDINTCON0_FRAMESEL1_NONE
;
287 writel(val
, ctx
->regs
+ VIDINTCON0
);
293 static void fimd_disable_vblank(struct device
*dev
)
295 struct fimd_context
*ctx
= get_fimd_context(dev
);
298 DRM_DEBUG_KMS("%s\n", __FILE__
);
303 if (test_and_clear_bit(0, &ctx
->irq_flags
)) {
304 val
= readl(ctx
->regs
+ VIDINTCON0
);
306 val
&= ~VIDINTCON0_INT_FRAME
;
307 val
&= ~VIDINTCON0_INT_ENABLE
;
309 writel(val
, ctx
->regs
+ VIDINTCON0
);
313 static void fimd_wait_for_vblank(struct device
*dev
)
315 struct fimd_context
*ctx
= get_fimd_context(dev
);
320 atomic_set(&ctx
->wait_vsync_event
, 1);
323 * wait for FIMD to signal VSYNC interrupt or return after
324 * timeout which is set to 50ms (refresh rate of 20).
326 if (!wait_event_timeout(ctx
->wait_vsync_queue
,
327 !atomic_read(&ctx
->wait_vsync_event
),
329 DRM_DEBUG_KMS("vblank wait timed out.\n");
332 static struct exynos_drm_manager_ops fimd_manager_ops
= {
335 .commit
= fimd_commit
,
336 .enable_vblank
= fimd_enable_vblank
,
337 .disable_vblank
= fimd_disable_vblank
,
338 .wait_for_vblank
= fimd_wait_for_vblank
,
341 static void fimd_win_mode_set(struct device
*dev
,
342 struct exynos_drm_overlay
*overlay
)
344 struct fimd_context
*ctx
= get_fimd_context(dev
);
345 struct fimd_win_data
*win_data
;
347 unsigned long offset
;
349 DRM_DEBUG_KMS("%s\n", __FILE__
);
352 dev_err(dev
, "overlay is NULL\n");
357 if (win
== DEFAULT_ZPOS
)
358 win
= ctx
->default_win
;
360 if (win
< 0 || win
> WINDOWS_NR
)
363 offset
= overlay
->fb_x
* (overlay
->bpp
>> 3);
364 offset
+= overlay
->fb_y
* overlay
->pitch
;
366 DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset
, overlay
->pitch
);
368 win_data
= &ctx
->win_data
[win
];
370 win_data
->offset_x
= overlay
->crtc_x
;
371 win_data
->offset_y
= overlay
->crtc_y
;
372 win_data
->ovl_width
= overlay
->crtc_width
;
373 win_data
->ovl_height
= overlay
->crtc_height
;
374 win_data
->fb_width
= overlay
->fb_width
;
375 win_data
->fb_height
= overlay
->fb_height
;
376 win_data
->dma_addr
= overlay
->dma_addr
[0] + offset
;
377 win_data
->bpp
= overlay
->bpp
;
378 win_data
->buf_offsize
= (overlay
->fb_width
- overlay
->crtc_width
) *
380 win_data
->line_size
= overlay
->crtc_width
* (overlay
->bpp
>> 3);
382 DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n",
383 win_data
->offset_x
, win_data
->offset_y
);
384 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
385 win_data
->ovl_width
, win_data
->ovl_height
);
386 DRM_DEBUG_KMS("paddr = 0x%lx\n", (unsigned long)win_data
->dma_addr
);
387 DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n",
388 overlay
->fb_width
, overlay
->crtc_width
);
391 static void fimd_win_set_pixfmt(struct device
*dev
, unsigned int win
)
393 struct fimd_context
*ctx
= get_fimd_context(dev
);
394 struct fimd_win_data
*win_data
= &ctx
->win_data
[win
];
397 DRM_DEBUG_KMS("%s\n", __FILE__
);
401 switch (win_data
->bpp
) {
403 val
|= WINCON0_BPPMODE_1BPP
;
404 val
|= WINCONx_BITSWP
;
405 val
|= WINCONx_BURSTLEN_4WORD
;
408 val
|= WINCON0_BPPMODE_2BPP
;
409 val
|= WINCONx_BITSWP
;
410 val
|= WINCONx_BURSTLEN_8WORD
;
413 val
|= WINCON0_BPPMODE_4BPP
;
414 val
|= WINCONx_BITSWP
;
415 val
|= WINCONx_BURSTLEN_8WORD
;
418 val
|= WINCON0_BPPMODE_8BPP_PALETTE
;
419 val
|= WINCONx_BURSTLEN_8WORD
;
420 val
|= WINCONx_BYTSWP
;
423 val
|= WINCON0_BPPMODE_16BPP_565
;
424 val
|= WINCONx_HAWSWP
;
425 val
|= WINCONx_BURSTLEN_16WORD
;
428 val
|= WINCON0_BPPMODE_24BPP_888
;
430 val
|= WINCONx_BURSTLEN_16WORD
;
433 val
|= WINCON1_BPPMODE_28BPP_A4888
434 | WINCON1_BLD_PIX
| WINCON1_ALPHA_SEL
;
436 val
|= WINCONx_BURSTLEN_16WORD
;
439 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
441 val
|= WINCON0_BPPMODE_24BPP_888
;
443 val
|= WINCONx_BURSTLEN_16WORD
;
447 DRM_DEBUG_KMS("bpp = %d\n", win_data
->bpp
);
449 writel(val
, ctx
->regs
+ WINCON(win
));
452 static void fimd_win_set_colkey(struct device
*dev
, unsigned int win
)
454 struct fimd_context
*ctx
= get_fimd_context(dev
);
455 unsigned int keycon0
= 0, keycon1
= 0;
457 DRM_DEBUG_KMS("%s\n", __FILE__
);
459 keycon0
= ~(WxKEYCON0_KEYBL_EN
| WxKEYCON0_KEYEN_F
|
460 WxKEYCON0_DIRCON
) | WxKEYCON0_COMPKEY(0);
462 keycon1
= WxKEYCON1_COLVAL(0xffffffff);
464 writel(keycon0
, ctx
->regs
+ WKEYCON0_BASE(win
));
465 writel(keycon1
, ctx
->regs
+ WKEYCON1_BASE(win
));
468 static void fimd_win_commit(struct device
*dev
, int zpos
)
470 struct fimd_context
*ctx
= get_fimd_context(dev
);
471 struct fimd_win_data
*win_data
;
473 unsigned long val
, alpha
, size
;
475 DRM_DEBUG_KMS("%s\n", __FILE__
);
480 if (win
== DEFAULT_ZPOS
)
481 win
= ctx
->default_win
;
483 if (win
< 0 || win
> WINDOWS_NR
)
486 win_data
= &ctx
->win_data
[win
];
489 * SHADOWCON register is used for enabling timing.
491 * for example, once only width value of a register is set,
492 * if the dma is started then fimd hardware could malfunction so
493 * with protect window setting, the register fields with prefix '_F'
494 * wouldn't be updated at vsync also but updated once unprotect window
498 /* protect windows */
499 val
= readl(ctx
->regs
+ SHADOWCON
);
500 val
|= SHADOWCON_WINx_PROTECT(win
);
501 writel(val
, ctx
->regs
+ SHADOWCON
);
503 /* buffer start address */
504 val
= (unsigned long)win_data
->dma_addr
;
505 writel(val
, ctx
->regs
+ VIDWx_BUF_START(win
, 0));
507 /* buffer end address */
508 size
= win_data
->fb_width
* win_data
->ovl_height
* (win_data
->bpp
>> 3);
509 val
= (unsigned long)(win_data
->dma_addr
+ size
);
510 writel(val
, ctx
->regs
+ VIDWx_BUF_END(win
, 0));
512 DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
513 (unsigned long)win_data
->dma_addr
, val
, size
);
514 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
515 win_data
->ovl_width
, win_data
->ovl_height
);
518 val
= VIDW_BUF_SIZE_OFFSET(win_data
->buf_offsize
) |
519 VIDW_BUF_SIZE_PAGEWIDTH(win_data
->line_size
);
520 writel(val
, ctx
->regs
+ VIDWx_BUF_SIZE(win
, 0));
523 val
= VIDOSDxA_TOPLEFT_X(win_data
->offset_x
) |
524 VIDOSDxA_TOPLEFT_Y(win_data
->offset_y
);
525 writel(val
, ctx
->regs
+ VIDOSD_A(win
));
527 val
= VIDOSDxB_BOTRIGHT_X(win_data
->offset_x
+
528 win_data
->ovl_width
- 1) |
529 VIDOSDxB_BOTRIGHT_Y(win_data
->offset_y
+
530 win_data
->ovl_height
- 1);
531 writel(val
, ctx
->regs
+ VIDOSD_B(win
));
533 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
534 win_data
->offset_x
, win_data
->offset_y
,
535 win_data
->offset_x
+ win_data
->ovl_width
- 1,
536 win_data
->offset_y
+ win_data
->ovl_height
- 1);
538 /* hardware window 0 doesn't support alpha channel. */
541 alpha
= VIDISD14C_ALPHA1_R(0xf) |
542 VIDISD14C_ALPHA1_G(0xf) |
543 VIDISD14C_ALPHA1_B(0xf);
545 writel(alpha
, ctx
->regs
+ VIDOSD_C(win
));
549 if (win
!= 3 && win
!= 4) {
550 u32 offset
= VIDOSD_D(win
);
552 offset
= VIDOSD_C_SIZE_W0
;
553 val
= win_data
->ovl_width
* win_data
->ovl_height
;
554 writel(val
, ctx
->regs
+ offset
);
556 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val
);
559 fimd_win_set_pixfmt(dev
, win
);
561 /* hardware window 0 doesn't support color key. */
563 fimd_win_set_colkey(dev
, win
);
566 val
= readl(ctx
->regs
+ WINCON(win
));
567 val
|= WINCONx_ENWIN
;
568 writel(val
, ctx
->regs
+ WINCON(win
));
570 /* Enable DMA channel and unprotect windows */
571 val
= readl(ctx
->regs
+ SHADOWCON
);
572 val
|= SHADOWCON_CHx_ENABLE(win
);
573 val
&= ~SHADOWCON_WINx_PROTECT(win
);
574 writel(val
, ctx
->regs
+ SHADOWCON
);
576 win_data
->enabled
= true;
579 static void fimd_win_disable(struct device
*dev
, int zpos
)
581 struct fimd_context
*ctx
= get_fimd_context(dev
);
582 struct fimd_win_data
*win_data
;
586 DRM_DEBUG_KMS("%s\n", __FILE__
);
588 if (win
== DEFAULT_ZPOS
)
589 win
= ctx
->default_win
;
591 if (win
< 0 || win
> WINDOWS_NR
)
594 win_data
= &ctx
->win_data
[win
];
596 if (ctx
->suspended
) {
597 /* do not resume this window*/
598 win_data
->resume
= false;
602 /* protect windows */
603 val
= readl(ctx
->regs
+ SHADOWCON
);
604 val
|= SHADOWCON_WINx_PROTECT(win
);
605 writel(val
, ctx
->regs
+ SHADOWCON
);
608 val
= readl(ctx
->regs
+ WINCON(win
));
609 val
&= ~WINCONx_ENWIN
;
610 writel(val
, ctx
->regs
+ WINCON(win
));
612 /* unprotect windows */
613 val
= readl(ctx
->regs
+ SHADOWCON
);
614 val
&= ~SHADOWCON_CHx_ENABLE(win
);
615 val
&= ~SHADOWCON_WINx_PROTECT(win
);
616 writel(val
, ctx
->regs
+ SHADOWCON
);
618 win_data
->enabled
= false;
621 static struct exynos_drm_overlay_ops fimd_overlay_ops
= {
622 .mode_set
= fimd_win_mode_set
,
623 .commit
= fimd_win_commit
,
624 .disable
= fimd_win_disable
,
627 static struct exynos_drm_manager fimd_manager
= {
629 .ops
= &fimd_manager_ops
,
630 .overlay_ops
= &fimd_overlay_ops
,
631 .display_ops
= &fimd_display_ops
,
634 static void fimd_finish_pageflip(struct drm_device
*drm_dev
, int crtc
)
636 struct exynos_drm_private
*dev_priv
= drm_dev
->dev_private
;
637 struct drm_pending_vblank_event
*e
, *t
;
641 spin_lock_irqsave(&drm_dev
->event_lock
, flags
);
643 list_for_each_entry_safe(e
, t
, &dev_priv
->pageflip_event_list
,
645 /* if event's pipe isn't same as crtc then ignore it. */
649 do_gettimeofday(&now
);
650 e
->event
.sequence
= 0;
651 e
->event
.tv_sec
= now
.tv_sec
;
652 e
->event
.tv_usec
= now
.tv_usec
;
654 list_move_tail(&e
->base
.link
, &e
->base
.file_priv
->event_list
);
655 wake_up_interruptible(&e
->base
.file_priv
->event_wait
);
656 drm_vblank_put(drm_dev
, crtc
);
659 spin_unlock_irqrestore(&drm_dev
->event_lock
, flags
);
662 static irqreturn_t
fimd_irq_handler(int irq
, void *dev_id
)
664 struct fimd_context
*ctx
= (struct fimd_context
*)dev_id
;
665 struct exynos_drm_subdrv
*subdrv
= &ctx
->subdrv
;
666 struct drm_device
*drm_dev
= subdrv
->drm_dev
;
667 struct exynos_drm_manager
*manager
= subdrv
->manager
;
670 val
= readl(ctx
->regs
+ VIDINTCON1
);
672 if (val
& VIDINTCON1_INT_FRAME
)
673 /* VSYNC interrupt */
674 writel(VIDINTCON1_INT_FRAME
, ctx
->regs
+ VIDINTCON1
);
676 /* check the crtc is detached already from encoder */
677 if (manager
->pipe
< 0)
680 drm_handle_vblank(drm_dev
, manager
->pipe
);
681 fimd_finish_pageflip(drm_dev
, manager
->pipe
);
683 /* set wait vsync event to zero and wake up queue. */
684 if (atomic_read(&ctx
->wait_vsync_event
)) {
685 atomic_set(&ctx
->wait_vsync_event
, 0);
686 DRM_WAKEUP(&ctx
->wait_vsync_queue
);
692 static int fimd_subdrv_probe(struct drm_device
*drm_dev
, struct device
*dev
)
694 DRM_DEBUG_KMS("%s\n", __FILE__
);
697 * enable drm irq mode.
698 * - with irq_enabled = 1, we can use the vblank feature.
700 * P.S. note that we wouldn't use drm irq handler but
701 * just specific driver own one instead because
702 * drm framework supports only one irq handler.
704 drm_dev
->irq_enabled
= 1;
707 * with vblank_disable_allowed = 1, vblank interrupt will be disabled
708 * by drm timer once a current process gives up ownership of
709 * vblank event.(after drm_vblank_put function is called)
711 drm_dev
->vblank_disable_allowed
= 1;
713 /* attach this sub driver to iommu mapping if supported. */
714 if (is_drm_iommu_supported(drm_dev
))
715 drm_iommu_attach_device(drm_dev
, dev
);
720 static void fimd_subdrv_remove(struct drm_device
*drm_dev
, struct device
*dev
)
722 DRM_DEBUG_KMS("%s\n", __FILE__
);
724 /* detach this sub driver from iommu mapping if supported. */
725 if (is_drm_iommu_supported(drm_dev
))
726 drm_iommu_detach_device(drm_dev
, dev
);
729 static int fimd_calc_clkdiv(struct fimd_context
*ctx
,
730 struct fb_videomode
*timing
)
732 unsigned long clk
= clk_get_rate(ctx
->lcd_clk
);
735 u32 best_framerate
= 0;
738 DRM_DEBUG_KMS("%s\n", __FILE__
);
740 retrace
= timing
->left_margin
+ timing
->hsync_len
+
741 timing
->right_margin
+ timing
->xres
;
742 retrace
*= timing
->upper_margin
+ timing
->vsync_len
+
743 timing
->lower_margin
+ timing
->yres
;
745 /* default framerate is 60Hz */
746 if (!timing
->refresh
)
747 timing
->refresh
= 60;
751 for (clkdiv
= 1; clkdiv
< 0x100; clkdiv
++) {
754 /* get best framerate */
755 framerate
= clk
/ clkdiv
;
756 tmp
= timing
->refresh
- framerate
;
758 best_framerate
= framerate
;
762 best_framerate
= framerate
;
763 else if (tmp
< (best_framerate
- framerate
))
764 best_framerate
= framerate
;
772 static void fimd_clear_win(struct fimd_context
*ctx
, int win
)
776 DRM_DEBUG_KMS("%s\n", __FILE__
);
778 writel(0, ctx
->regs
+ WINCON(win
));
779 writel(0, ctx
->regs
+ VIDOSD_A(win
));
780 writel(0, ctx
->regs
+ VIDOSD_B(win
));
781 writel(0, ctx
->regs
+ VIDOSD_C(win
));
783 if (win
== 1 || win
== 2)
784 writel(0, ctx
->regs
+ VIDOSD_D(win
));
786 val
= readl(ctx
->regs
+ SHADOWCON
);
787 val
&= ~SHADOWCON_WINx_PROTECT(win
);
788 writel(val
, ctx
->regs
+ SHADOWCON
);
791 static int fimd_clock(struct fimd_context
*ctx
, bool enable
)
793 DRM_DEBUG_KMS("%s\n", __FILE__
);
798 ret
= clk_enable(ctx
->bus_clk
);
802 ret
= clk_enable(ctx
->lcd_clk
);
804 clk_disable(ctx
->bus_clk
);
808 clk_disable(ctx
->lcd_clk
);
809 clk_disable(ctx
->bus_clk
);
815 static void fimd_window_suspend(struct device
*dev
)
817 struct fimd_context
*ctx
= get_fimd_context(dev
);
818 struct fimd_win_data
*win_data
;
821 for (i
= 0; i
< WINDOWS_NR
; i
++) {
822 win_data
= &ctx
->win_data
[i
];
823 win_data
->resume
= win_data
->enabled
;
824 fimd_win_disable(dev
, i
);
826 fimd_wait_for_vblank(dev
);
829 static void fimd_window_resume(struct device
*dev
)
831 struct fimd_context
*ctx
= get_fimd_context(dev
);
832 struct fimd_win_data
*win_data
;
835 for (i
= 0; i
< WINDOWS_NR
; i
++) {
836 win_data
= &ctx
->win_data
[i
];
837 win_data
->enabled
= win_data
->resume
;
838 win_data
->resume
= false;
842 static int fimd_activate(struct fimd_context
*ctx
, bool enable
)
844 struct device
*dev
= ctx
->subdrv
.dev
;
848 ret
= fimd_clock(ctx
, true);
852 ctx
->suspended
= false;
854 /* if vblank was enabled status, enable it again. */
855 if (test_and_clear_bit(0, &ctx
->irq_flags
))
856 fimd_enable_vblank(dev
);
858 fimd_window_resume(dev
);
860 fimd_window_suspend(dev
);
862 fimd_clock(ctx
, false);
863 ctx
->suspended
= true;
869 static int __devinit
fimd_probe(struct platform_device
*pdev
)
871 struct device
*dev
= &pdev
->dev
;
872 struct fimd_context
*ctx
;
873 struct exynos_drm_subdrv
*subdrv
;
874 struct exynos_drm_fimd_pdata
*pdata
;
875 struct exynos_drm_panel_info
*panel
;
876 struct resource
*res
;
880 DRM_DEBUG_KMS("%s\n", __FILE__
);
882 pdata
= pdev
->dev
.platform_data
;
884 dev_err(dev
, "no platform data specified\n");
888 panel
= &pdata
->panel
;
890 dev_err(dev
, "panel is null.\n");
894 ctx
= devm_kzalloc(&pdev
->dev
, sizeof(*ctx
), GFP_KERNEL
);
898 ctx
->bus_clk
= devm_clk_get(dev
, "fimd");
899 if (IS_ERR(ctx
->bus_clk
)) {
900 dev_err(dev
, "failed to get bus clock\n");
901 return PTR_ERR(ctx
->bus_clk
);
904 ctx
->lcd_clk
= devm_clk_get(dev
, "sclk_fimd");
905 if (IS_ERR(ctx
->lcd_clk
)) {
906 dev_err(dev
, "failed to get lcd clock\n");
907 return PTR_ERR(ctx
->lcd_clk
);
910 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
912 ctx
->regs
= devm_request_and_ioremap(&pdev
->dev
, res
);
914 dev_err(dev
, "failed to map registers\n");
918 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
920 dev_err(dev
, "irq request failed.\n");
924 ctx
->irq
= res
->start
;
926 ret
= devm_request_irq(&pdev
->dev
, ctx
->irq
, fimd_irq_handler
,
929 dev_err(dev
, "irq request failed.\n");
933 ctx
->vidcon0
= pdata
->vidcon0
;
934 ctx
->vidcon1
= pdata
->vidcon1
;
935 ctx
->default_win
= pdata
->default_win
;
937 DRM_INIT_WAITQUEUE(&ctx
->wait_vsync_queue
);
938 atomic_set(&ctx
->wait_vsync_event
, 0);
940 subdrv
= &ctx
->subdrv
;
943 subdrv
->manager
= &fimd_manager
;
944 subdrv
->probe
= fimd_subdrv_probe
;
945 subdrv
->remove
= fimd_subdrv_remove
;
947 mutex_init(&ctx
->lock
);
949 platform_set_drvdata(pdev
, ctx
);
951 pm_runtime_enable(dev
);
952 pm_runtime_get_sync(dev
);
954 ctx
->clkdiv
= fimd_calc_clkdiv(ctx
, &panel
->timing
);
955 panel
->timing
.pixclock
= clk_get_rate(ctx
->lcd_clk
) / ctx
->clkdiv
;
957 DRM_DEBUG_KMS("pixel clock = %d, clkdiv = %d\n",
958 panel
->timing
.pixclock
, ctx
->clkdiv
);
960 for (win
= 0; win
< WINDOWS_NR
; win
++)
961 fimd_clear_win(ctx
, win
);
963 exynos_drm_subdrv_register(subdrv
);
968 static int __devexit
fimd_remove(struct platform_device
*pdev
)
970 struct device
*dev
= &pdev
->dev
;
971 struct fimd_context
*ctx
= platform_get_drvdata(pdev
);
973 DRM_DEBUG_KMS("%s\n", __FILE__
);
975 exynos_drm_subdrv_unregister(&ctx
->subdrv
);
980 clk_disable(ctx
->lcd_clk
);
981 clk_disable(ctx
->bus_clk
);
983 pm_runtime_set_suspended(dev
);
984 pm_runtime_put_sync(dev
);
987 pm_runtime_disable(dev
);
992 #ifdef CONFIG_PM_SLEEP
993 static int fimd_suspend(struct device
*dev
)
995 struct fimd_context
*ctx
= get_fimd_context(dev
);
998 * do not use pm_runtime_suspend(). if pm_runtime_suspend() is
999 * called here, an error would be returned by that interface
1000 * because the usage_count of pm runtime is more than 1.
1002 if (!pm_runtime_suspended(dev
))
1003 return fimd_activate(ctx
, false);
1008 static int fimd_resume(struct device
*dev
)
1010 struct fimd_context
*ctx
= get_fimd_context(dev
);
1013 * if entered to sleep when lcd panel was on, the usage_count
1014 * of pm runtime would still be 1 so in this case, fimd driver
1015 * should be on directly not drawing on pm runtime interface.
1017 if (pm_runtime_suspended(dev
)) {
1020 ret
= fimd_activate(ctx
, true);
1025 * in case of dpms on(standby), fimd_apply function will
1026 * be called by encoder's dpms callback to update fimd's
1027 * registers but in case of sleep wakeup, it's not.
1028 * so fimd_apply function should be called at here.
1037 #ifdef CONFIG_PM_RUNTIME
1038 static int fimd_runtime_suspend(struct device
*dev
)
1040 struct fimd_context
*ctx
= get_fimd_context(dev
);
1042 DRM_DEBUG_KMS("%s\n", __FILE__
);
1044 return fimd_activate(ctx
, false);
1047 static int fimd_runtime_resume(struct device
*dev
)
1049 struct fimd_context
*ctx
= get_fimd_context(dev
);
1051 DRM_DEBUG_KMS("%s\n", __FILE__
);
1053 return fimd_activate(ctx
, true);
1057 static struct platform_device_id fimd_driver_ids
[] = {
1059 .name
= "exynos4-fb",
1060 .driver_data
= (unsigned long)&exynos4_fimd_driver_data
,
1062 .name
= "exynos5-fb",
1063 .driver_data
= (unsigned long)&exynos5_fimd_driver_data
,
1067 MODULE_DEVICE_TABLE(platform
, fimd_driver_ids
);
1069 static const struct dev_pm_ops fimd_pm_ops
= {
1070 SET_SYSTEM_SLEEP_PM_OPS(fimd_suspend
, fimd_resume
)
1071 SET_RUNTIME_PM_OPS(fimd_runtime_suspend
, fimd_runtime_resume
, NULL
)
1074 struct platform_driver fimd_driver
= {
1075 .probe
= fimd_probe
,
1076 .remove
= __devexit_p(fimd_remove
),
1077 .id_table
= fimd_driver_ids
,
1079 .name
= "exynos4-fb",
1080 .owner
= THIS_MODULE
,