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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
[deliverable/linux.git] / drivers / gpu / drm / exynos / exynos_drm_fimd.c
1 /* exynos_drm_fimd.c
2 *
3 * Copyright (C) 2011 Samsung Electronics Co.Ltd
4 * Authors:
5 * Joonyoung Shim <jy0922.shim@samsung.com>
6 * Inki Dae <inki.dae@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14 #include <drm/drmP.h>
15
16 #include <linux/kernel.h>
17 #include <linux/platform_device.h>
18 #include <linux/clk.h>
19 #include <linux/of.h>
20 #include <linux/of_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/component.h>
23 #include <linux/mfd/syscon.h>
24 #include <linux/regmap.h>
25
26 #include <video/of_display_timing.h>
27 #include <video/of_videomode.h>
28 #include <video/samsung_fimd.h>
29 #include <drm/exynos_drm.h>
30
31 #include "exynos_drm_drv.h"
32 #include "exynos_drm_fbdev.h"
33 #include "exynos_drm_crtc.h"
34 #include "exynos_drm_iommu.h"
35
36 /*
37 * FIMD stands for Fully Interactive Mobile Display and
38 * as a display controller, it transfers contents drawn on memory
39 * to a LCD Panel through Display Interfaces such as RGB or
40 * CPU Interface.
41 */
42
43 #define FIMD_DEFAULT_FRAMERATE 60
44 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
45
46 /* position control register for hardware window 0, 2 ~ 4.*/
47 #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
48 #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
49 /*
50 * size control register for hardware windows 0 and alpha control register
51 * for hardware windows 1 ~ 4
52 */
53 #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16)
54 /* size control register for hardware windows 1 ~ 2. */
55 #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
56
57 #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
58 #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8)
59 #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
60
61 /* color key control register for hardware window 1 ~ 4. */
62 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8))
63 /* color key value register for hardware window 1 ~ 4. */
64 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
65
66 /* I80 / RGB trigger control register */
67 #define TRIGCON 0x1A4
68 #define TRGMODE_I80_RGB_ENABLE_I80 (1 << 0)
69 #define SWTRGCMD_I80_RGB_ENABLE (1 << 1)
70
71 /* display mode change control register except exynos4 */
72 #define VIDOUT_CON 0x000
73 #define VIDOUT_CON_F_I80_LDI0 (0x2 << 8)
74
75 /* I80 interface control for main LDI register */
76 #define I80IFCONFAx(x) (0x1B0 + (x) * 4)
77 #define I80IFCONFBx(x) (0x1B8 + (x) * 4)
78 #define LCD_CS_SETUP(x) ((x) << 16)
79 #define LCD_WR_SETUP(x) ((x) << 12)
80 #define LCD_WR_ACTIVE(x) ((x) << 8)
81 #define LCD_WR_HOLD(x) ((x) << 4)
82 #define I80IFEN_ENABLE (1 << 0)
83
84 /* FIMD has totally five hardware windows. */
85 #define WINDOWS_NR 5
86
87 struct fimd_driver_data {
88 unsigned int timing_base;
89 unsigned int lcdblk_offset;
90 unsigned int lcdblk_vt_shift;
91 unsigned int lcdblk_bypass_shift;
92
93 unsigned int has_shadowcon:1;
94 unsigned int has_clksel:1;
95 unsigned int has_limited_fmt:1;
96 unsigned int has_vidoutcon:1;
97 unsigned int has_vtsel:1;
98 };
99
100 static struct fimd_driver_data s3c64xx_fimd_driver_data = {
101 .timing_base = 0x0,
102 .has_clksel = 1,
103 .has_limited_fmt = 1,
104 };
105
106 static struct fimd_driver_data exynos3_fimd_driver_data = {
107 .timing_base = 0x20000,
108 .lcdblk_offset = 0x210,
109 .lcdblk_bypass_shift = 1,
110 .has_shadowcon = 1,
111 .has_vidoutcon = 1,
112 };
113
114 static struct fimd_driver_data exynos4_fimd_driver_data = {
115 .timing_base = 0x0,
116 .lcdblk_offset = 0x210,
117 .lcdblk_vt_shift = 10,
118 .lcdblk_bypass_shift = 1,
119 .has_shadowcon = 1,
120 .has_vtsel = 1,
121 };
122
123 static struct fimd_driver_data exynos4415_fimd_driver_data = {
124 .timing_base = 0x20000,
125 .lcdblk_offset = 0x210,
126 .lcdblk_vt_shift = 10,
127 .lcdblk_bypass_shift = 1,
128 .has_shadowcon = 1,
129 .has_vidoutcon = 1,
130 .has_vtsel = 1,
131 };
132
133 static struct fimd_driver_data exynos5_fimd_driver_data = {
134 .timing_base = 0x20000,
135 .lcdblk_offset = 0x214,
136 .lcdblk_vt_shift = 24,
137 .lcdblk_bypass_shift = 15,
138 .has_shadowcon = 1,
139 .has_vidoutcon = 1,
140 .has_vtsel = 1,
141 };
142
143 struct fimd_win_data {
144 unsigned int offset_x;
145 unsigned int offset_y;
146 unsigned int ovl_width;
147 unsigned int ovl_height;
148 unsigned int fb_width;
149 unsigned int fb_height;
150 unsigned int bpp;
151 unsigned int pixel_format;
152 dma_addr_t dma_addr;
153 unsigned int buf_offsize;
154 unsigned int line_size; /* bytes */
155 bool enabled;
156 bool resume;
157 };
158
159 struct fimd_context {
160 struct device *dev;
161 struct drm_device *drm_dev;
162 struct exynos_drm_crtc *crtc;
163 struct clk *bus_clk;
164 struct clk *lcd_clk;
165 void __iomem *regs;
166 struct regmap *sysreg;
167 struct fimd_win_data win_data[WINDOWS_NR];
168 unsigned int default_win;
169 unsigned long irq_flags;
170 u32 vidcon0;
171 u32 vidcon1;
172 u32 vidout_con;
173 u32 i80ifcon;
174 bool i80_if;
175 bool suspended;
176 int pipe;
177 wait_queue_head_t wait_vsync_queue;
178 atomic_t wait_vsync_event;
179 atomic_t win_updated;
180 atomic_t triggering;
181
182 struct exynos_drm_panel_info panel;
183 struct fimd_driver_data *driver_data;
184 struct exynos_drm_display *display;
185 };
186
187 static const struct of_device_id fimd_driver_dt_match[] = {
188 { .compatible = "samsung,s3c6400-fimd",
189 .data = &s3c64xx_fimd_driver_data },
190 { .compatible = "samsung,exynos3250-fimd",
191 .data = &exynos3_fimd_driver_data },
192 { .compatible = "samsung,exynos4210-fimd",
193 .data = &exynos4_fimd_driver_data },
194 { .compatible = "samsung,exynos4415-fimd",
195 .data = &exynos4415_fimd_driver_data },
196 { .compatible = "samsung,exynos5250-fimd",
197 .data = &exynos5_fimd_driver_data },
198 {},
199 };
200 MODULE_DEVICE_TABLE(of, fimd_driver_dt_match);
201
202 static inline struct fimd_driver_data *drm_fimd_get_driver_data(
203 struct platform_device *pdev)
204 {
205 const struct of_device_id *of_id =
206 of_match_device(fimd_driver_dt_match, &pdev->dev);
207
208 return (struct fimd_driver_data *)of_id->data;
209 }
210
211 static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc)
212 {
213 struct fimd_context *ctx = crtc->ctx;
214
215 if (ctx->suspended)
216 return;
217
218 atomic_set(&ctx->wait_vsync_event, 1);
219
220 /*
221 * wait for FIMD to signal VSYNC interrupt or return after
222 * timeout which is set to 50ms (refresh rate of 20).
223 */
224 if (!wait_event_timeout(ctx->wait_vsync_queue,
225 !atomic_read(&ctx->wait_vsync_event),
226 HZ/20))
227 DRM_DEBUG_KMS("vblank wait timed out.\n");
228 }
229
230 static void fimd_enable_video_output(struct fimd_context *ctx, int win,
231 bool enable)
232 {
233 u32 val = readl(ctx->regs + WINCON(win));
234
235 if (enable)
236 val |= WINCONx_ENWIN;
237 else
238 val &= ~WINCONx_ENWIN;
239
240 writel(val, ctx->regs + WINCON(win));
241 }
242
243 static void fimd_enable_shadow_channel_path(struct fimd_context *ctx, int win,
244 bool enable)
245 {
246 u32 val = readl(ctx->regs + SHADOWCON);
247
248 if (enable)
249 val |= SHADOWCON_CHx_ENABLE(win);
250 else
251 val &= ~SHADOWCON_CHx_ENABLE(win);
252
253 writel(val, ctx->regs + SHADOWCON);
254 }
255
256 static void fimd_clear_channel(struct fimd_context *ctx)
257 {
258 int win, ch_enabled = 0;
259
260 DRM_DEBUG_KMS("%s\n", __FILE__);
261
262 /* Check if any channel is enabled. */
263 for (win = 0; win < WINDOWS_NR; win++) {
264 u32 val = readl(ctx->regs + WINCON(win));
265
266 if (val & WINCONx_ENWIN) {
267 fimd_enable_video_output(ctx, win, false);
268
269 if (ctx->driver_data->has_shadowcon)
270 fimd_enable_shadow_channel_path(ctx, win,
271 false);
272
273 ch_enabled = 1;
274 }
275 }
276
277 /* Wait for vsync, as disable channel takes effect at next vsync */
278 if (ch_enabled) {
279 unsigned int state = ctx->suspended;
280
281 ctx->suspended = 0;
282 fimd_wait_for_vblank(ctx->crtc);
283 ctx->suspended = state;
284 }
285 }
286
287 static int fimd_iommu_attach_devices(struct fimd_context *ctx,
288 struct drm_device *drm_dev)
289 {
290
291 /* attach this sub driver to iommu mapping if supported. */
292 if (is_drm_iommu_supported(ctx->drm_dev)) {
293 int ret;
294
295 /*
296 * If any channel is already active, iommu will throw
297 * a PAGE FAULT when enabled. So clear any channel if enabled.
298 */
299 fimd_clear_channel(ctx);
300 ret = drm_iommu_attach_device(ctx->drm_dev, ctx->dev);
301 if (ret) {
302 DRM_ERROR("drm_iommu_attach failed.\n");
303 return ret;
304 }
305
306 }
307
308 return 0;
309 }
310
311 static void fimd_iommu_detach_devices(struct fimd_context *ctx)
312 {
313 /* detach this sub driver from iommu mapping if supported. */
314 if (is_drm_iommu_supported(ctx->drm_dev))
315 drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
316 }
317
318 static u32 fimd_calc_clkdiv(struct fimd_context *ctx,
319 const struct drm_display_mode *mode)
320 {
321 unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
322 u32 clkdiv;
323
324 if (ctx->i80_if) {
325 /*
326 * The frame done interrupt should be occurred prior to the
327 * next TE signal.
328 */
329 ideal_clk *= 2;
330 }
331
332 /* Find the clock divider value that gets us closest to ideal_clk */
333 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->lcd_clk), ideal_clk);
334
335 return (clkdiv < 0x100) ? clkdiv : 0xff;
336 }
337
338 static bool fimd_mode_fixup(struct exynos_drm_crtc *crtc,
339 const struct drm_display_mode *mode,
340 struct drm_display_mode *adjusted_mode)
341 {
342 if (adjusted_mode->vrefresh == 0)
343 adjusted_mode->vrefresh = FIMD_DEFAULT_FRAMERATE;
344
345 return true;
346 }
347
348 static void fimd_commit(struct exynos_drm_crtc *crtc)
349 {
350 struct fimd_context *ctx = crtc->ctx;
351 struct drm_display_mode *mode = &crtc->base.mode;
352 struct fimd_driver_data *driver_data = ctx->driver_data;
353 void *timing_base = ctx->regs + driver_data->timing_base;
354 u32 val, clkdiv;
355
356 if (ctx->suspended)
357 return;
358
359 /* nothing to do if we haven't set the mode yet */
360 if (mode->htotal == 0 || mode->vtotal == 0)
361 return;
362
363 if (ctx->i80_if) {
364 val = ctx->i80ifcon | I80IFEN_ENABLE;
365 writel(val, timing_base + I80IFCONFAx(0));
366
367 /* disable auto frame rate */
368 writel(0, timing_base + I80IFCONFBx(0));
369
370 /* set video type selection to I80 interface */
371 if (driver_data->has_vtsel && ctx->sysreg &&
372 regmap_update_bits(ctx->sysreg,
373 driver_data->lcdblk_offset,
374 0x3 << driver_data->lcdblk_vt_shift,
375 0x1 << driver_data->lcdblk_vt_shift)) {
376 DRM_ERROR("Failed to update sysreg for I80 i/f.\n");
377 return;
378 }
379 } else {
380 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
381 u32 vidcon1;
382
383 /* setup polarity values */
384 vidcon1 = ctx->vidcon1;
385 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
386 vidcon1 |= VIDCON1_INV_VSYNC;
387 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
388 vidcon1 |= VIDCON1_INV_HSYNC;
389 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
390
391 /* setup vertical timing values. */
392 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
393 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
394 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
395
396 val = VIDTCON0_VBPD(vbpd - 1) |
397 VIDTCON0_VFPD(vfpd - 1) |
398 VIDTCON0_VSPW(vsync_len - 1);
399 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
400
401 /* setup horizontal timing values. */
402 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
403 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
404 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
405
406 val = VIDTCON1_HBPD(hbpd - 1) |
407 VIDTCON1_HFPD(hfpd - 1) |
408 VIDTCON1_HSPW(hsync_len - 1);
409 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
410 }
411
412 if (driver_data->has_vidoutcon)
413 writel(ctx->vidout_con, timing_base + VIDOUT_CON);
414
415 /* set bypass selection */
416 if (ctx->sysreg && regmap_update_bits(ctx->sysreg,
417 driver_data->lcdblk_offset,
418 0x1 << driver_data->lcdblk_bypass_shift,
419 0x1 << driver_data->lcdblk_bypass_shift)) {
420 DRM_ERROR("Failed to update sysreg for bypass setting.\n");
421 return;
422 }
423
424 /* setup horizontal and vertical display size. */
425 val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
426 VIDTCON2_HOZVAL(mode->hdisplay - 1) |
427 VIDTCON2_LINEVAL_E(mode->vdisplay - 1) |
428 VIDTCON2_HOZVAL_E(mode->hdisplay - 1);
429 writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
430
431 /*
432 * fields of register with prefix '_F' would be updated
433 * at vsync(same as dma start)
434 */
435 val = ctx->vidcon0;
436 val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
437
438 if (ctx->driver_data->has_clksel)
439 val |= VIDCON0_CLKSEL_LCD;
440
441 clkdiv = fimd_calc_clkdiv(ctx, mode);
442 if (clkdiv > 1)
443 val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR;
444
445 writel(val, ctx->regs + VIDCON0);
446 }
447
448 static int fimd_enable_vblank(struct exynos_drm_crtc *crtc)
449 {
450 struct fimd_context *ctx = crtc->ctx;
451 u32 val;
452
453 if (ctx->suspended)
454 return -EPERM;
455
456 if (!test_and_set_bit(0, &ctx->irq_flags)) {
457 val = readl(ctx->regs + VIDINTCON0);
458
459 val |= VIDINTCON0_INT_ENABLE;
460
461 if (ctx->i80_if) {
462 val |= VIDINTCON0_INT_I80IFDONE;
463 val |= VIDINTCON0_INT_SYSMAINCON;
464 val &= ~VIDINTCON0_INT_SYSSUBCON;
465 } else {
466 val |= VIDINTCON0_INT_FRAME;
467
468 val &= ~VIDINTCON0_FRAMESEL0_MASK;
469 val |= VIDINTCON0_FRAMESEL0_VSYNC;
470 val &= ~VIDINTCON0_FRAMESEL1_MASK;
471 val |= VIDINTCON0_FRAMESEL1_NONE;
472 }
473
474 writel(val, ctx->regs + VIDINTCON0);
475 }
476
477 return 0;
478 }
479
480 static void fimd_disable_vblank(struct exynos_drm_crtc *crtc)
481 {
482 struct fimd_context *ctx = crtc->ctx;
483 u32 val;
484
485 if (ctx->suspended)
486 return;
487
488 if (test_and_clear_bit(0, &ctx->irq_flags)) {
489 val = readl(ctx->regs + VIDINTCON0);
490
491 val &= ~VIDINTCON0_INT_ENABLE;
492
493 if (ctx->i80_if) {
494 val &= ~VIDINTCON0_INT_I80IFDONE;
495 val &= ~VIDINTCON0_INT_SYSMAINCON;
496 val &= ~VIDINTCON0_INT_SYSSUBCON;
497 } else
498 val &= ~VIDINTCON0_INT_FRAME;
499
500 writel(val, ctx->regs + VIDINTCON0);
501 }
502 }
503
504 static void fimd_win_mode_set(struct exynos_drm_crtc *crtc,
505 struct exynos_drm_plane *plane)
506 {
507 struct fimd_context *ctx = crtc->ctx;
508 struct fimd_win_data *win_data;
509 int win;
510 unsigned long offset;
511
512 if (!plane) {
513 DRM_ERROR("plane is NULL\n");
514 return;
515 }
516
517 win = plane->zpos;
518 if (win == DEFAULT_ZPOS)
519 win = ctx->default_win;
520
521 if (win < 0 || win >= WINDOWS_NR)
522 return;
523
524 offset = plane->fb_x * (plane->bpp >> 3);
525 offset += plane->fb_y * plane->pitch;
526
527 DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, plane->pitch);
528
529 win_data = &ctx->win_data[win];
530
531 win_data->offset_x = plane->crtc_x;
532 win_data->offset_y = plane->crtc_y;
533 win_data->ovl_width = plane->crtc_width;
534 win_data->ovl_height = plane->crtc_height;
535 win_data->fb_width = plane->fb_width;
536 win_data->fb_height = plane->fb_height;
537 win_data->dma_addr = plane->dma_addr[0] + offset;
538 win_data->bpp = plane->bpp;
539 win_data->pixel_format = plane->pixel_format;
540 win_data->buf_offsize = (plane->fb_width - plane->crtc_width) *
541 (plane->bpp >> 3);
542 win_data->line_size = plane->crtc_width * (plane->bpp >> 3);
543
544 DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n",
545 win_data->offset_x, win_data->offset_y);
546 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
547 win_data->ovl_width, win_data->ovl_height);
548 DRM_DEBUG_KMS("paddr = 0x%lx\n", (unsigned long)win_data->dma_addr);
549 DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n",
550 plane->fb_width, plane->crtc_width);
551 }
552
553 static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win)
554 {
555 struct fimd_win_data *win_data = &ctx->win_data[win];
556 unsigned long val;
557
558 val = WINCONx_ENWIN;
559
560 /*
561 * In case of s3c64xx, window 0 doesn't support alpha channel.
562 * So the request format is ARGB8888 then change it to XRGB8888.
563 */
564 if (ctx->driver_data->has_limited_fmt && !win) {
565 if (win_data->pixel_format == DRM_FORMAT_ARGB8888)
566 win_data->pixel_format = DRM_FORMAT_XRGB8888;
567 }
568
569 switch (win_data->pixel_format) {
570 case DRM_FORMAT_C8:
571 val |= WINCON0_BPPMODE_8BPP_PALETTE;
572 val |= WINCONx_BURSTLEN_8WORD;
573 val |= WINCONx_BYTSWP;
574 break;
575 case DRM_FORMAT_XRGB1555:
576 val |= WINCON0_BPPMODE_16BPP_1555;
577 val |= WINCONx_HAWSWP;
578 val |= WINCONx_BURSTLEN_16WORD;
579 break;
580 case DRM_FORMAT_RGB565:
581 val |= WINCON0_BPPMODE_16BPP_565;
582 val |= WINCONx_HAWSWP;
583 val |= WINCONx_BURSTLEN_16WORD;
584 break;
585 case DRM_FORMAT_XRGB8888:
586 val |= WINCON0_BPPMODE_24BPP_888;
587 val |= WINCONx_WSWP;
588 val |= WINCONx_BURSTLEN_16WORD;
589 break;
590 case DRM_FORMAT_ARGB8888:
591 val |= WINCON1_BPPMODE_25BPP_A1888
592 | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
593 val |= WINCONx_WSWP;
594 val |= WINCONx_BURSTLEN_16WORD;
595 break;
596 default:
597 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
598
599 val |= WINCON0_BPPMODE_24BPP_888;
600 val |= WINCONx_WSWP;
601 val |= WINCONx_BURSTLEN_16WORD;
602 break;
603 }
604
605 DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp);
606
607 /*
608 * In case of exynos, setting dma-burst to 16Word causes permanent
609 * tearing for very small buffers, e.g. cursor buffer. Burst Mode
610 * switching which is based on plane size is not recommended as
611 * plane size varies alot towards the end of the screen and rapid
612 * movement causes unstable DMA which results into iommu crash/tear.
613 */
614
615 if (win_data->fb_width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
616 val &= ~WINCONx_BURSTLEN_MASK;
617 val |= WINCONx_BURSTLEN_4WORD;
618 }
619
620 writel(val, ctx->regs + WINCON(win));
621 }
622
623 static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win)
624 {
625 unsigned int keycon0 = 0, keycon1 = 0;
626
627 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
628 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
629
630 keycon1 = WxKEYCON1_COLVAL(0xffffffff);
631
632 writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
633 writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
634 }
635
636 /**
637 * shadow_protect_win() - disable updating values from shadow registers at vsync
638 *
639 * @win: window to protect registers for
640 * @protect: 1 to protect (disable updates)
641 */
642 static void fimd_shadow_protect_win(struct fimd_context *ctx,
643 int win, bool protect)
644 {
645 u32 reg, bits, val;
646
647 if (ctx->driver_data->has_shadowcon) {
648 reg = SHADOWCON;
649 bits = SHADOWCON_WINx_PROTECT(win);
650 } else {
651 reg = PRTCON;
652 bits = PRTCON_PROTECT;
653 }
654
655 val = readl(ctx->regs + reg);
656 if (protect)
657 val |= bits;
658 else
659 val &= ~bits;
660 writel(val, ctx->regs + reg);
661 }
662
663 static void fimd_win_commit(struct exynos_drm_crtc *crtc, int zpos)
664 {
665 struct fimd_context *ctx = crtc->ctx;
666 struct fimd_win_data *win_data;
667 int win = zpos;
668 unsigned long val, alpha, size;
669 unsigned int last_x;
670 unsigned int last_y;
671
672 if (ctx->suspended)
673 return;
674
675 if (win == DEFAULT_ZPOS)
676 win = ctx->default_win;
677
678 if (win < 0 || win >= WINDOWS_NR)
679 return;
680
681 win_data = &ctx->win_data[win];
682
683 /* If suspended, enable this on resume */
684 if (ctx->suspended) {
685 win_data->resume = true;
686 return;
687 }
688
689 /*
690 * SHADOWCON/PRTCON register is used for enabling timing.
691 *
692 * for example, once only width value of a register is set,
693 * if the dma is started then fimd hardware could malfunction so
694 * with protect window setting, the register fields with prefix '_F'
695 * wouldn't be updated at vsync also but updated once unprotect window
696 * is set.
697 */
698
699 /* protect windows */
700 fimd_shadow_protect_win(ctx, win, true);
701
702 /* buffer start address */
703 val = (unsigned long)win_data->dma_addr;
704 writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
705
706 /* buffer end address */
707 size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3);
708 val = (unsigned long)(win_data->dma_addr + size);
709 writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
710
711 DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
712 (unsigned long)win_data->dma_addr, val, size);
713 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
714 win_data->ovl_width, win_data->ovl_height);
715
716 /* buffer size */
717 val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) |
718 VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size) |
719 VIDW_BUF_SIZE_OFFSET_E(win_data->buf_offsize) |
720 VIDW_BUF_SIZE_PAGEWIDTH_E(win_data->line_size);
721 writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
722
723 /* OSD position */
724 val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) |
725 VIDOSDxA_TOPLEFT_Y(win_data->offset_y) |
726 VIDOSDxA_TOPLEFT_X_E(win_data->offset_x) |
727 VIDOSDxA_TOPLEFT_Y_E(win_data->offset_y);
728 writel(val, ctx->regs + VIDOSD_A(win));
729
730 last_x = win_data->offset_x + win_data->ovl_width;
731 if (last_x)
732 last_x--;
733 last_y = win_data->offset_y + win_data->ovl_height;
734 if (last_y)
735 last_y--;
736
737 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
738 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);
739
740 writel(val, ctx->regs + VIDOSD_B(win));
741
742 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
743 win_data->offset_x, win_data->offset_y, last_x, last_y);
744
745 /* hardware window 0 doesn't support alpha channel. */
746 if (win != 0) {
747 /* OSD alpha */
748 alpha = VIDISD14C_ALPHA1_R(0xf) |
749 VIDISD14C_ALPHA1_G(0xf) |
750 VIDISD14C_ALPHA1_B(0xf);
751
752 writel(alpha, ctx->regs + VIDOSD_C(win));
753 }
754
755 /* OSD size */
756 if (win != 3 && win != 4) {
757 u32 offset = VIDOSD_D(win);
758 if (win == 0)
759 offset = VIDOSD_C(win);
760 val = win_data->ovl_width * win_data->ovl_height;
761 writel(val, ctx->regs + offset);
762
763 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
764 }
765
766 fimd_win_set_pixfmt(ctx, win);
767
768 /* hardware window 0 doesn't support color key. */
769 if (win != 0)
770 fimd_win_set_colkey(ctx, win);
771
772 fimd_enable_video_output(ctx, win, true);
773
774 if (ctx->driver_data->has_shadowcon)
775 fimd_enable_shadow_channel_path(ctx, win, true);
776
777 /* Enable DMA channel and unprotect windows */
778 fimd_shadow_protect_win(ctx, win, false);
779
780 win_data->enabled = true;
781
782 if (ctx->i80_if)
783 atomic_set(&ctx->win_updated, 1);
784 }
785
786 static void fimd_win_disable(struct exynos_drm_crtc *crtc, int zpos)
787 {
788 struct fimd_context *ctx = crtc->ctx;
789 struct fimd_win_data *win_data;
790 int win = zpos;
791
792 if (win == DEFAULT_ZPOS)
793 win = ctx->default_win;
794
795 if (win < 0 || win >= WINDOWS_NR)
796 return;
797
798 win_data = &ctx->win_data[win];
799
800 if (ctx->suspended) {
801 /* do not resume this window*/
802 win_data->resume = false;
803 return;
804 }
805
806 /* protect windows */
807 fimd_shadow_protect_win(ctx, win, true);
808
809 fimd_enable_video_output(ctx, win, false);
810
811 if (ctx->driver_data->has_shadowcon)
812 fimd_enable_shadow_channel_path(ctx, win, false);
813
814 /* unprotect windows */
815 fimd_shadow_protect_win(ctx, win, false);
816
817 win_data->enabled = false;
818 }
819
820 static void fimd_window_suspend(struct fimd_context *ctx)
821 {
822 struct fimd_win_data *win_data;
823 int i;
824
825 for (i = 0; i < WINDOWS_NR; i++) {
826 win_data = &ctx->win_data[i];
827 win_data->resume = win_data->enabled;
828 if (win_data->enabled)
829 fimd_win_disable(ctx->crtc, i);
830 }
831 }
832
833 static void fimd_window_resume(struct fimd_context *ctx)
834 {
835 struct fimd_win_data *win_data;
836 int i;
837
838 for (i = 0; i < WINDOWS_NR; i++) {
839 win_data = &ctx->win_data[i];
840 win_data->enabled = win_data->resume;
841 win_data->resume = false;
842 }
843 }
844
845 static void fimd_apply(struct fimd_context *ctx)
846 {
847 struct fimd_win_data *win_data;
848 int i;
849
850 for (i = 0; i < WINDOWS_NR; i++) {
851 win_data = &ctx->win_data[i];
852 if (win_data->enabled)
853 fimd_win_commit(ctx->crtc, i);
854 else
855 fimd_win_disable(ctx->crtc, i);
856 }
857
858 fimd_commit(ctx->crtc);
859 }
860
861 static int fimd_poweron(struct fimd_context *ctx)
862 {
863 int ret;
864
865 if (!ctx->suspended)
866 return 0;
867
868 ctx->suspended = false;
869
870 pm_runtime_get_sync(ctx->dev);
871
872 ret = clk_prepare_enable(ctx->bus_clk);
873 if (ret < 0) {
874 DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret);
875 goto bus_clk_err;
876 }
877
878 ret = clk_prepare_enable(ctx->lcd_clk);
879 if (ret < 0) {
880 DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret);
881 goto lcd_clk_err;
882 }
883
884 /* if vblank was enabled status, enable it again. */
885 if (test_and_clear_bit(0, &ctx->irq_flags)) {
886 ret = fimd_enable_vblank(ctx->crtc);
887 if (ret) {
888 DRM_ERROR("Failed to re-enable vblank [%d]\n", ret);
889 goto enable_vblank_err;
890 }
891 }
892
893 fimd_window_resume(ctx);
894
895 fimd_apply(ctx);
896
897 return 0;
898
899 enable_vblank_err:
900 clk_disable_unprepare(ctx->lcd_clk);
901 lcd_clk_err:
902 clk_disable_unprepare(ctx->bus_clk);
903 bus_clk_err:
904 ctx->suspended = true;
905 return ret;
906 }
907
908 static int fimd_poweroff(struct fimd_context *ctx)
909 {
910 if (ctx->suspended)
911 return 0;
912
913 /*
914 * We need to make sure that all windows are disabled before we
915 * suspend that connector. Otherwise we might try to scan from
916 * a destroyed buffer later.
917 */
918 fimd_window_suspend(ctx);
919
920 clk_disable_unprepare(ctx->lcd_clk);
921 clk_disable_unprepare(ctx->bus_clk);
922
923 pm_runtime_put_sync(ctx->dev);
924
925 ctx->suspended = true;
926 return 0;
927 }
928
929 static void fimd_dpms(struct exynos_drm_crtc *crtc, int mode)
930 {
931 DRM_DEBUG_KMS("%s, %d\n", __FILE__, mode);
932
933 switch (mode) {
934 case DRM_MODE_DPMS_ON:
935 fimd_poweron(crtc->ctx);
936 break;
937 case DRM_MODE_DPMS_STANDBY:
938 case DRM_MODE_DPMS_SUSPEND:
939 case DRM_MODE_DPMS_OFF:
940 fimd_poweroff(crtc->ctx);
941 break;
942 default:
943 DRM_DEBUG_KMS("unspecified mode %d\n", mode);
944 break;
945 }
946 }
947
948 static void fimd_trigger(struct device *dev)
949 {
950 struct fimd_context *ctx = dev_get_drvdata(dev);
951 struct fimd_driver_data *driver_data = ctx->driver_data;
952 void *timing_base = ctx->regs + driver_data->timing_base;
953 u32 reg;
954
955 /*
956 * Skips triggering if in triggering state, because multiple triggering
957 * requests can cause panel reset.
958 */
959 if (atomic_read(&ctx->triggering))
960 return;
961
962 /* Enters triggering mode */
963 atomic_set(&ctx->triggering, 1);
964
965 reg = readl(timing_base + TRIGCON);
966 reg |= (TRGMODE_I80_RGB_ENABLE_I80 | SWTRGCMD_I80_RGB_ENABLE);
967 writel(reg, timing_base + TRIGCON);
968
969 /*
970 * Exits triggering mode if vblank is not enabled yet, because when the
971 * VIDINTCON0 register is not set, it can not exit from triggering mode.
972 */
973 if (!test_bit(0, &ctx->irq_flags))
974 atomic_set(&ctx->triggering, 0);
975 }
976
977 static void fimd_te_handler(struct exynos_drm_crtc *crtc)
978 {
979 struct fimd_context *ctx = crtc->ctx;
980
981 /* Checks the crtc is detached already from encoder */
982 if (ctx->pipe < 0 || !ctx->drm_dev)
983 return;
984
985 /*
986 * If there is a page flip request, triggers and handles the page flip
987 * event so that current fb can be updated into panel GRAM.
988 */
989 if (atomic_add_unless(&ctx->win_updated, -1, 0))
990 fimd_trigger(ctx->dev);
991
992 /* Wakes up vsync event queue */
993 if (atomic_read(&ctx->wait_vsync_event)) {
994 atomic_set(&ctx->wait_vsync_event, 0);
995 wake_up(&ctx->wait_vsync_queue);
996 }
997
998 if (test_bit(0, &ctx->irq_flags))
999 drm_handle_vblank(ctx->drm_dev, ctx->pipe);
1000 }
1001
1002 static struct exynos_drm_crtc_ops fimd_crtc_ops = {
1003 .dpms = fimd_dpms,
1004 .mode_fixup = fimd_mode_fixup,
1005 .commit = fimd_commit,
1006 .enable_vblank = fimd_enable_vblank,
1007 .disable_vblank = fimd_disable_vblank,
1008 .wait_for_vblank = fimd_wait_for_vblank,
1009 .win_mode_set = fimd_win_mode_set,
1010 .win_commit = fimd_win_commit,
1011 .win_disable = fimd_win_disable,
1012 .te_handler = fimd_te_handler,
1013 };
1014
1015 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
1016 {
1017 struct fimd_context *ctx = (struct fimd_context *)dev_id;
1018 u32 val, clear_bit;
1019
1020 val = readl(ctx->regs + VIDINTCON1);
1021
1022 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
1023 if (val & clear_bit)
1024 writel(clear_bit, ctx->regs + VIDINTCON1);
1025
1026 /* check the crtc is detached already from encoder */
1027 if (ctx->pipe < 0 || !ctx->drm_dev)
1028 goto out;
1029
1030 if (ctx->i80_if) {
1031 exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
1032
1033 /* Exits triggering mode */
1034 atomic_set(&ctx->triggering, 0);
1035 } else {
1036 drm_handle_vblank(ctx->drm_dev, ctx->pipe);
1037 exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
1038
1039 /* set wait vsync event to zero and wake up queue. */
1040 if (atomic_read(&ctx->wait_vsync_event)) {
1041 atomic_set(&ctx->wait_vsync_event, 0);
1042 wake_up(&ctx->wait_vsync_queue);
1043 }
1044 }
1045
1046 out:
1047 return IRQ_HANDLED;
1048 }
1049
1050 static int fimd_bind(struct device *dev, struct device *master, void *data)
1051 {
1052 struct fimd_context *ctx = dev_get_drvdata(dev);
1053 struct drm_device *drm_dev = data;
1054 struct exynos_drm_private *priv = drm_dev->dev_private;
1055 int ret;
1056
1057 ctx->drm_dev = drm_dev;
1058 ctx->pipe = priv->pipe++;
1059
1060 ctx->crtc = exynos_drm_crtc_create(drm_dev, ctx->pipe,
1061 EXYNOS_DISPLAY_TYPE_LCD,
1062 &fimd_crtc_ops, ctx);
1063
1064 if (ctx->display)
1065 exynos_drm_create_enc_conn(drm_dev, ctx->display);
1066
1067 ret = fimd_iommu_attach_devices(ctx, drm_dev);
1068 if (ret)
1069 return ret;
1070
1071 return 0;
1072
1073 }
1074
1075 static void fimd_unbind(struct device *dev, struct device *master,
1076 void *data)
1077 {
1078 struct fimd_context *ctx = dev_get_drvdata(dev);
1079
1080 fimd_dpms(ctx->crtc, DRM_MODE_DPMS_OFF);
1081
1082 fimd_iommu_detach_devices(ctx);
1083
1084 if (ctx->display)
1085 exynos_dpi_remove(ctx->display);
1086 }
1087
1088 static const struct component_ops fimd_component_ops = {
1089 .bind = fimd_bind,
1090 .unbind = fimd_unbind,
1091 };
1092
1093 static int fimd_probe(struct platform_device *pdev)
1094 {
1095 struct device *dev = &pdev->dev;
1096 struct fimd_context *ctx;
1097 struct device_node *i80_if_timings;
1098 struct resource *res;
1099 int ret;
1100
1101 if (!dev->of_node)
1102 return -ENODEV;
1103
1104 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1105 if (!ctx)
1106 return -ENOMEM;
1107
1108 ret = exynos_drm_component_add(dev, EXYNOS_DEVICE_TYPE_CRTC,
1109 EXYNOS_DISPLAY_TYPE_LCD);
1110 if (ret)
1111 return ret;
1112
1113 ctx->dev = dev;
1114 ctx->suspended = true;
1115 ctx->driver_data = drm_fimd_get_driver_data(pdev);
1116
1117 if (of_property_read_bool(dev->of_node, "samsung,invert-vden"))
1118 ctx->vidcon1 |= VIDCON1_INV_VDEN;
1119 if (of_property_read_bool(dev->of_node, "samsung,invert-vclk"))
1120 ctx->vidcon1 |= VIDCON1_INV_VCLK;
1121
1122 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
1123 if (i80_if_timings) {
1124 u32 val;
1125
1126 ctx->i80_if = true;
1127
1128 if (ctx->driver_data->has_vidoutcon)
1129 ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0;
1130 else
1131 ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0;
1132 /*
1133 * The user manual describes that this "DSI_EN" bit is required
1134 * to enable I80 24-bit data interface.
1135 */
1136 ctx->vidcon0 |= VIDCON0_DSI_EN;
1137
1138 if (of_property_read_u32(i80_if_timings, "cs-setup", &val))
1139 val = 0;
1140 ctx->i80ifcon = LCD_CS_SETUP(val);
1141 if (of_property_read_u32(i80_if_timings, "wr-setup", &val))
1142 val = 0;
1143 ctx->i80ifcon |= LCD_WR_SETUP(val);
1144 if (of_property_read_u32(i80_if_timings, "wr-active", &val))
1145 val = 1;
1146 ctx->i80ifcon |= LCD_WR_ACTIVE(val);
1147 if (of_property_read_u32(i80_if_timings, "wr-hold", &val))
1148 val = 0;
1149 ctx->i80ifcon |= LCD_WR_HOLD(val);
1150 }
1151 of_node_put(i80_if_timings);
1152
1153 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1154 "samsung,sysreg");
1155 if (IS_ERR(ctx->sysreg)) {
1156 dev_warn(dev, "failed to get system register.\n");
1157 ctx->sysreg = NULL;
1158 }
1159
1160 ctx->bus_clk = devm_clk_get(dev, "fimd");
1161 if (IS_ERR(ctx->bus_clk)) {
1162 dev_err(dev, "failed to get bus clock\n");
1163 ret = PTR_ERR(ctx->bus_clk);
1164 goto err_del_component;
1165 }
1166
1167 ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
1168 if (IS_ERR(ctx->lcd_clk)) {
1169 dev_err(dev, "failed to get lcd clock\n");
1170 ret = PTR_ERR(ctx->lcd_clk);
1171 goto err_del_component;
1172 }
1173
1174 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1175
1176 ctx->regs = devm_ioremap_resource(dev, res);
1177 if (IS_ERR(ctx->regs)) {
1178 ret = PTR_ERR(ctx->regs);
1179 goto err_del_component;
1180 }
1181
1182 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1183 ctx->i80_if ? "lcd_sys" : "vsync");
1184 if (!res) {
1185 dev_err(dev, "irq request failed.\n");
1186 ret = -ENXIO;
1187 goto err_del_component;
1188 }
1189
1190 ret = devm_request_irq(dev, res->start, fimd_irq_handler,
1191 0, "drm_fimd", ctx);
1192 if (ret) {
1193 dev_err(dev, "irq request failed.\n");
1194 goto err_del_component;
1195 }
1196
1197 init_waitqueue_head(&ctx->wait_vsync_queue);
1198 atomic_set(&ctx->wait_vsync_event, 0);
1199
1200 platform_set_drvdata(pdev, ctx);
1201
1202 ctx->display = exynos_dpi_probe(dev);
1203 if (IS_ERR(ctx->display)) {
1204 ret = PTR_ERR(ctx->display);
1205 goto err_del_component;
1206 }
1207
1208 pm_runtime_enable(dev);
1209
1210 ret = component_add(dev, &fimd_component_ops);
1211 if (ret)
1212 goto err_disable_pm_runtime;
1213
1214 return ret;
1215
1216 err_disable_pm_runtime:
1217 pm_runtime_disable(dev);
1218
1219 err_del_component:
1220 exynos_drm_component_del(dev, EXYNOS_DEVICE_TYPE_CRTC);
1221 return ret;
1222 }
1223
1224 static int fimd_remove(struct platform_device *pdev)
1225 {
1226 pm_runtime_disable(&pdev->dev);
1227
1228 component_del(&pdev->dev, &fimd_component_ops);
1229 exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC);
1230
1231 return 0;
1232 }
1233
1234 struct platform_driver fimd_driver = {
1235 .probe = fimd_probe,
1236 .remove = fimd_remove,
1237 .driver = {
1238 .name = "exynos4-fb",
1239 .owner = THIS_MODULE,
1240 .of_match_table = fimd_driver_dt_match,
1241 },
1242 };
Linux kernel - Deliverables
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