3 * Copyright (C) 2011 Samsung Electronics Co.Ltd
5 * Joonyoung Shim <jy0922.shim@samsung.com>
6 * Inki Dae <inki.dae@samsung.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/platform_device.h>
18 #include <linux/clk.h>
20 #include <linux/of_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/component.h>
23 #include <linux/mfd/syscon.h>
24 #include <linux/regmap.h>
26 #include <video/of_display_timing.h>
27 #include <video/of_videomode.h>
28 #include <video/samsung_fimd.h>
29 #include <drm/exynos_drm.h>
31 #include "exynos_drm_drv.h"
32 #include "exynos_drm_fbdev.h"
33 #include "exynos_drm_crtc.h"
34 #include "exynos_drm_iommu.h"
37 * FIMD stands for Fully Interactive Mobile Display and
38 * as a display controller, it transfers contents drawn on memory
39 * to a LCD Panel through Display Interfaces such as RGB or
43 #define FIMD_DEFAULT_FRAMERATE 60
44 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
46 /* position control register for hardware window 0, 2 ~ 4.*/
47 #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
48 #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
50 * size control register for hardware windows 0 and alpha control register
51 * for hardware windows 1 ~ 4
53 #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16)
54 /* size control register for hardware windows 1 ~ 2. */
55 #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
57 #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
58 #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8)
59 #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
61 /* color key control register for hardware window 1 ~ 4. */
62 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8))
63 /* color key value register for hardware window 1 ~ 4. */
64 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
66 /* I80 / RGB trigger control register */
68 #define TRGMODE_I80_RGB_ENABLE_I80 (1 << 0)
69 #define SWTRGCMD_I80_RGB_ENABLE (1 << 1)
71 /* display mode change control register except exynos4 */
72 #define VIDOUT_CON 0x000
73 #define VIDOUT_CON_F_I80_LDI0 (0x2 << 8)
75 /* I80 interface control for main LDI register */
76 #define I80IFCONFAx(x) (0x1B0 + (x) * 4)
77 #define I80IFCONFBx(x) (0x1B8 + (x) * 4)
78 #define LCD_CS_SETUP(x) ((x) << 16)
79 #define LCD_WR_SETUP(x) ((x) << 12)
80 #define LCD_WR_ACTIVE(x) ((x) << 8)
81 #define LCD_WR_HOLD(x) ((x) << 4)
82 #define I80IFEN_ENABLE (1 << 0)
84 /* FIMD has totally five hardware windows. */
87 struct fimd_driver_data
{
88 unsigned int timing_base
;
89 unsigned int lcdblk_offset
;
90 unsigned int lcdblk_vt_shift
;
91 unsigned int lcdblk_bypass_shift
;
93 unsigned int has_shadowcon
:1;
94 unsigned int has_clksel
:1;
95 unsigned int has_limited_fmt
:1;
96 unsigned int has_vidoutcon
:1;
97 unsigned int has_vtsel
:1;
100 static struct fimd_driver_data s3c64xx_fimd_driver_data
= {
103 .has_limited_fmt
= 1,
106 static struct fimd_driver_data exynos3_fimd_driver_data
= {
107 .timing_base
= 0x20000,
108 .lcdblk_offset
= 0x210,
109 .lcdblk_bypass_shift
= 1,
114 static struct fimd_driver_data exynos4_fimd_driver_data
= {
116 .lcdblk_offset
= 0x210,
117 .lcdblk_vt_shift
= 10,
118 .lcdblk_bypass_shift
= 1,
123 static struct fimd_driver_data exynos4415_fimd_driver_data
= {
124 .timing_base
= 0x20000,
125 .lcdblk_offset
= 0x210,
126 .lcdblk_vt_shift
= 10,
127 .lcdblk_bypass_shift
= 1,
133 static struct fimd_driver_data exynos5_fimd_driver_data
= {
134 .timing_base
= 0x20000,
135 .lcdblk_offset
= 0x214,
136 .lcdblk_vt_shift
= 24,
137 .lcdblk_bypass_shift
= 15,
143 struct fimd_win_data
{
144 unsigned int offset_x
;
145 unsigned int offset_y
;
146 unsigned int ovl_width
;
147 unsigned int ovl_height
;
148 unsigned int fb_width
;
149 unsigned int fb_height
;
150 unsigned int fb_pitch
;
152 unsigned int pixel_format
;
154 unsigned int buf_offsize
;
155 unsigned int line_size
; /* bytes */
160 struct fimd_context
{
162 struct drm_device
*drm_dev
;
163 struct exynos_drm_crtc
*crtc
;
167 struct regmap
*sysreg
;
168 struct fimd_win_data win_data
[WINDOWS_NR
];
169 unsigned int default_win
;
170 unsigned long irq_flags
;
178 wait_queue_head_t wait_vsync_queue
;
179 atomic_t wait_vsync_event
;
180 atomic_t win_updated
;
183 struct exynos_drm_panel_info panel
;
184 struct fimd_driver_data
*driver_data
;
185 struct exynos_drm_display
*display
;
188 static const struct of_device_id fimd_driver_dt_match
[] = {
189 { .compatible
= "samsung,s3c6400-fimd",
190 .data
= &s3c64xx_fimd_driver_data
},
191 { .compatible
= "samsung,exynos3250-fimd",
192 .data
= &exynos3_fimd_driver_data
},
193 { .compatible
= "samsung,exynos4210-fimd",
194 .data
= &exynos4_fimd_driver_data
},
195 { .compatible
= "samsung,exynos4415-fimd",
196 .data
= &exynos4415_fimd_driver_data
},
197 { .compatible
= "samsung,exynos5250-fimd",
198 .data
= &exynos5_fimd_driver_data
},
201 MODULE_DEVICE_TABLE(of
, fimd_driver_dt_match
);
203 static inline struct fimd_driver_data
*drm_fimd_get_driver_data(
204 struct platform_device
*pdev
)
206 const struct of_device_id
*of_id
=
207 of_match_device(fimd_driver_dt_match
, &pdev
->dev
);
209 return (struct fimd_driver_data
*)of_id
->data
;
212 static void fimd_wait_for_vblank(struct exynos_drm_crtc
*crtc
)
214 struct fimd_context
*ctx
= crtc
->ctx
;
219 atomic_set(&ctx
->wait_vsync_event
, 1);
222 * wait for FIMD to signal VSYNC interrupt or return after
223 * timeout which is set to 50ms (refresh rate of 20).
225 if (!wait_event_timeout(ctx
->wait_vsync_queue
,
226 !atomic_read(&ctx
->wait_vsync_event
),
228 DRM_DEBUG_KMS("vblank wait timed out.\n");
231 static void fimd_enable_video_output(struct fimd_context
*ctx
, int win
,
234 u32 val
= readl(ctx
->regs
+ WINCON(win
));
237 val
|= WINCONx_ENWIN
;
239 val
&= ~WINCONx_ENWIN
;
241 writel(val
, ctx
->regs
+ WINCON(win
));
244 static void fimd_enable_shadow_channel_path(struct fimd_context
*ctx
, int win
,
247 u32 val
= readl(ctx
->regs
+ SHADOWCON
);
250 val
|= SHADOWCON_CHx_ENABLE(win
);
252 val
&= ~SHADOWCON_CHx_ENABLE(win
);
254 writel(val
, ctx
->regs
+ SHADOWCON
);
257 static void fimd_clear_channel(struct fimd_context
*ctx
)
259 int win
, ch_enabled
= 0;
261 DRM_DEBUG_KMS("%s\n", __FILE__
);
263 /* Check if any channel is enabled. */
264 for (win
= 0; win
< WINDOWS_NR
; win
++) {
265 u32 val
= readl(ctx
->regs
+ WINCON(win
));
267 if (val
& WINCONx_ENWIN
) {
268 fimd_enable_video_output(ctx
, win
, false);
270 if (ctx
->driver_data
->has_shadowcon
)
271 fimd_enable_shadow_channel_path(ctx
, win
,
278 /* Wait for vsync, as disable channel takes effect at next vsync */
280 unsigned int state
= ctx
->suspended
;
283 fimd_wait_for_vblank(ctx
->crtc
);
284 ctx
->suspended
= state
;
288 static int fimd_iommu_attach_devices(struct fimd_context
*ctx
,
289 struct drm_device
*drm_dev
)
292 /* attach this sub driver to iommu mapping if supported. */
293 if (is_drm_iommu_supported(ctx
->drm_dev
)) {
297 * If any channel is already active, iommu will throw
298 * a PAGE FAULT when enabled. So clear any channel if enabled.
300 fimd_clear_channel(ctx
);
301 ret
= drm_iommu_attach_device(ctx
->drm_dev
, ctx
->dev
);
303 DRM_ERROR("drm_iommu_attach failed.\n");
312 static void fimd_iommu_detach_devices(struct fimd_context
*ctx
)
314 /* detach this sub driver from iommu mapping if supported. */
315 if (is_drm_iommu_supported(ctx
->drm_dev
))
316 drm_iommu_detach_device(ctx
->drm_dev
, ctx
->dev
);
319 static u32
fimd_calc_clkdiv(struct fimd_context
*ctx
,
320 const struct drm_display_mode
*mode
)
322 unsigned long ideal_clk
= mode
->htotal
* mode
->vtotal
* mode
->vrefresh
;
327 * The frame done interrupt should be occurred prior to the
333 /* Find the clock divider value that gets us closest to ideal_clk */
334 clkdiv
= DIV_ROUND_UP(clk_get_rate(ctx
->lcd_clk
), ideal_clk
);
336 return (clkdiv
< 0x100) ? clkdiv
: 0xff;
339 static bool fimd_mode_fixup(struct exynos_drm_crtc
*crtc
,
340 const struct drm_display_mode
*mode
,
341 struct drm_display_mode
*adjusted_mode
)
343 if (adjusted_mode
->vrefresh
== 0)
344 adjusted_mode
->vrefresh
= FIMD_DEFAULT_FRAMERATE
;
349 static void fimd_commit(struct exynos_drm_crtc
*crtc
)
351 struct fimd_context
*ctx
= crtc
->ctx
;
352 struct drm_display_mode
*mode
= &crtc
->base
.mode
;
353 struct fimd_driver_data
*driver_data
= ctx
->driver_data
;
354 void *timing_base
= ctx
->regs
+ driver_data
->timing_base
;
360 /* nothing to do if we haven't set the mode yet */
361 if (mode
->htotal
== 0 || mode
->vtotal
== 0)
365 val
= ctx
->i80ifcon
| I80IFEN_ENABLE
;
366 writel(val
, timing_base
+ I80IFCONFAx(0));
368 /* disable auto frame rate */
369 writel(0, timing_base
+ I80IFCONFBx(0));
371 /* set video type selection to I80 interface */
372 if (driver_data
->has_vtsel
&& ctx
->sysreg
&&
373 regmap_update_bits(ctx
->sysreg
,
374 driver_data
->lcdblk_offset
,
375 0x3 << driver_data
->lcdblk_vt_shift
,
376 0x1 << driver_data
->lcdblk_vt_shift
)) {
377 DRM_ERROR("Failed to update sysreg for I80 i/f.\n");
381 int vsync_len
, vbpd
, vfpd
, hsync_len
, hbpd
, hfpd
;
384 /* setup polarity values */
385 vidcon1
= ctx
->vidcon1
;
386 if (mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
387 vidcon1
|= VIDCON1_INV_VSYNC
;
388 if (mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
389 vidcon1
|= VIDCON1_INV_HSYNC
;
390 writel(vidcon1
, ctx
->regs
+ driver_data
->timing_base
+ VIDCON1
);
392 /* setup vertical timing values. */
393 vsync_len
= mode
->crtc_vsync_end
- mode
->crtc_vsync_start
;
394 vbpd
= mode
->crtc_vtotal
- mode
->crtc_vsync_end
;
395 vfpd
= mode
->crtc_vsync_start
- mode
->crtc_vdisplay
;
397 val
= VIDTCON0_VBPD(vbpd
- 1) |
398 VIDTCON0_VFPD(vfpd
- 1) |
399 VIDTCON0_VSPW(vsync_len
- 1);
400 writel(val
, ctx
->regs
+ driver_data
->timing_base
+ VIDTCON0
);
402 /* setup horizontal timing values. */
403 hsync_len
= mode
->crtc_hsync_end
- mode
->crtc_hsync_start
;
404 hbpd
= mode
->crtc_htotal
- mode
->crtc_hsync_end
;
405 hfpd
= mode
->crtc_hsync_start
- mode
->crtc_hdisplay
;
407 val
= VIDTCON1_HBPD(hbpd
- 1) |
408 VIDTCON1_HFPD(hfpd
- 1) |
409 VIDTCON1_HSPW(hsync_len
- 1);
410 writel(val
, ctx
->regs
+ driver_data
->timing_base
+ VIDTCON1
);
413 if (driver_data
->has_vidoutcon
)
414 writel(ctx
->vidout_con
, timing_base
+ VIDOUT_CON
);
416 /* set bypass selection */
417 if (ctx
->sysreg
&& regmap_update_bits(ctx
->sysreg
,
418 driver_data
->lcdblk_offset
,
419 0x1 << driver_data
->lcdblk_bypass_shift
,
420 0x1 << driver_data
->lcdblk_bypass_shift
)) {
421 DRM_ERROR("Failed to update sysreg for bypass setting.\n");
425 /* setup horizontal and vertical display size. */
426 val
= VIDTCON2_LINEVAL(mode
->vdisplay
- 1) |
427 VIDTCON2_HOZVAL(mode
->hdisplay
- 1) |
428 VIDTCON2_LINEVAL_E(mode
->vdisplay
- 1) |
429 VIDTCON2_HOZVAL_E(mode
->hdisplay
- 1);
430 writel(val
, ctx
->regs
+ driver_data
->timing_base
+ VIDTCON2
);
433 * fields of register with prefix '_F' would be updated
434 * at vsync(same as dma start)
437 val
|= VIDCON0_ENVID
| VIDCON0_ENVID_F
;
439 if (ctx
->driver_data
->has_clksel
)
440 val
|= VIDCON0_CLKSEL_LCD
;
442 clkdiv
= fimd_calc_clkdiv(ctx
, mode
);
444 val
|= VIDCON0_CLKVAL_F(clkdiv
- 1) | VIDCON0_CLKDIR
;
446 writel(val
, ctx
->regs
+ VIDCON0
);
449 static int fimd_enable_vblank(struct exynos_drm_crtc
*crtc
)
451 struct fimd_context
*ctx
= crtc
->ctx
;
457 if (!test_and_set_bit(0, &ctx
->irq_flags
)) {
458 val
= readl(ctx
->regs
+ VIDINTCON0
);
460 val
|= VIDINTCON0_INT_ENABLE
;
463 val
|= VIDINTCON0_INT_I80IFDONE
;
464 val
|= VIDINTCON0_INT_SYSMAINCON
;
465 val
&= ~VIDINTCON0_INT_SYSSUBCON
;
467 val
|= VIDINTCON0_INT_FRAME
;
469 val
&= ~VIDINTCON0_FRAMESEL0_MASK
;
470 val
|= VIDINTCON0_FRAMESEL0_VSYNC
;
471 val
&= ~VIDINTCON0_FRAMESEL1_MASK
;
472 val
|= VIDINTCON0_FRAMESEL1_NONE
;
475 writel(val
, ctx
->regs
+ VIDINTCON0
);
481 static void fimd_disable_vblank(struct exynos_drm_crtc
*crtc
)
483 struct fimd_context
*ctx
= crtc
->ctx
;
489 if (test_and_clear_bit(0, &ctx
->irq_flags
)) {
490 val
= readl(ctx
->regs
+ VIDINTCON0
);
492 val
&= ~VIDINTCON0_INT_ENABLE
;
495 val
&= ~VIDINTCON0_INT_I80IFDONE
;
496 val
&= ~VIDINTCON0_INT_SYSMAINCON
;
497 val
&= ~VIDINTCON0_INT_SYSSUBCON
;
499 val
&= ~VIDINTCON0_INT_FRAME
;
501 writel(val
, ctx
->regs
+ VIDINTCON0
);
505 static void fimd_win_mode_set(struct exynos_drm_crtc
*crtc
,
506 struct exynos_drm_plane
*plane
)
508 struct fimd_context
*ctx
= crtc
->ctx
;
509 struct fimd_win_data
*win_data
;
511 unsigned long offset
;
514 DRM_ERROR("plane is NULL\n");
519 if (win
== DEFAULT_ZPOS
)
520 win
= ctx
->default_win
;
522 if (win
< 0 || win
>= WINDOWS_NR
)
525 offset
= plane
->fb_x
* (plane
->bpp
>> 3);
526 offset
+= plane
->fb_y
* plane
->pitch
;
528 DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset
, plane
->pitch
);
530 win_data
= &ctx
->win_data
[win
];
532 win_data
->offset_x
= plane
->crtc_x
;
533 win_data
->offset_y
= plane
->crtc_y
;
534 win_data
->ovl_width
= plane
->crtc_width
;
535 win_data
->ovl_height
= plane
->crtc_height
;
536 win_data
->fb_pitch
= plane
->pitch
;
537 win_data
->fb_width
= plane
->fb_width
;
538 win_data
->fb_height
= plane
->fb_height
;
539 win_data
->dma_addr
= plane
->dma_addr
[0] + offset
;
540 win_data
->bpp
= plane
->bpp
;
541 win_data
->pixel_format
= plane
->pixel_format
;
542 win_data
->buf_offsize
=
543 plane
->pitch
- (plane
->crtc_width
* (plane
->bpp
>> 3));
544 win_data
->line_size
= plane
->crtc_width
* (plane
->bpp
>> 3);
546 DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n",
547 win_data
->offset_x
, win_data
->offset_y
);
548 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
549 win_data
->ovl_width
, win_data
->ovl_height
);
550 DRM_DEBUG_KMS("paddr = 0x%lx\n", (unsigned long)win_data
->dma_addr
);
551 DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n",
552 plane
->fb_width
, plane
->crtc_width
);
555 static void fimd_win_set_pixfmt(struct fimd_context
*ctx
, unsigned int win
)
557 struct fimd_win_data
*win_data
= &ctx
->win_data
[win
];
563 * In case of s3c64xx, window 0 doesn't support alpha channel.
564 * So the request format is ARGB8888 then change it to XRGB8888.
566 if (ctx
->driver_data
->has_limited_fmt
&& !win
) {
567 if (win_data
->pixel_format
== DRM_FORMAT_ARGB8888
)
568 win_data
->pixel_format
= DRM_FORMAT_XRGB8888
;
571 switch (win_data
->pixel_format
) {
573 val
|= WINCON0_BPPMODE_8BPP_PALETTE
;
574 val
|= WINCONx_BURSTLEN_8WORD
;
575 val
|= WINCONx_BYTSWP
;
577 case DRM_FORMAT_XRGB1555
:
578 val
|= WINCON0_BPPMODE_16BPP_1555
;
579 val
|= WINCONx_HAWSWP
;
580 val
|= WINCONx_BURSTLEN_16WORD
;
582 case DRM_FORMAT_RGB565
:
583 val
|= WINCON0_BPPMODE_16BPP_565
;
584 val
|= WINCONx_HAWSWP
;
585 val
|= WINCONx_BURSTLEN_16WORD
;
587 case DRM_FORMAT_XRGB8888
:
588 val
|= WINCON0_BPPMODE_24BPP_888
;
590 val
|= WINCONx_BURSTLEN_16WORD
;
592 case DRM_FORMAT_ARGB8888
:
593 val
|= WINCON1_BPPMODE_25BPP_A1888
594 | WINCON1_BLD_PIX
| WINCON1_ALPHA_SEL
;
596 val
|= WINCONx_BURSTLEN_16WORD
;
599 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
601 val
|= WINCON0_BPPMODE_24BPP_888
;
603 val
|= WINCONx_BURSTLEN_16WORD
;
607 DRM_DEBUG_KMS("bpp = %d\n", win_data
->bpp
);
610 * In case of exynos, setting dma-burst to 16Word causes permanent
611 * tearing for very small buffers, e.g. cursor buffer. Burst Mode
612 * switching which is based on plane size is not recommended as
613 * plane size varies alot towards the end of the screen and rapid
614 * movement causes unstable DMA which results into iommu crash/tear.
617 if (win_data
->fb_width
< MIN_FB_WIDTH_FOR_16WORD_BURST
) {
618 val
&= ~WINCONx_BURSTLEN_MASK
;
619 val
|= WINCONx_BURSTLEN_4WORD
;
622 writel(val
, ctx
->regs
+ WINCON(win
));
625 static void fimd_win_set_colkey(struct fimd_context
*ctx
, unsigned int win
)
627 unsigned int keycon0
= 0, keycon1
= 0;
629 keycon0
= ~(WxKEYCON0_KEYBL_EN
| WxKEYCON0_KEYEN_F
|
630 WxKEYCON0_DIRCON
) | WxKEYCON0_COMPKEY(0);
632 keycon1
= WxKEYCON1_COLVAL(0xffffffff);
634 writel(keycon0
, ctx
->regs
+ WKEYCON0_BASE(win
));
635 writel(keycon1
, ctx
->regs
+ WKEYCON1_BASE(win
));
639 * shadow_protect_win() - disable updating values from shadow registers at vsync
641 * @win: window to protect registers for
642 * @protect: 1 to protect (disable updates)
644 static void fimd_shadow_protect_win(struct fimd_context
*ctx
,
645 int win
, bool protect
)
649 if (ctx
->driver_data
->has_shadowcon
) {
651 bits
= SHADOWCON_WINx_PROTECT(win
);
654 bits
= PRTCON_PROTECT
;
657 val
= readl(ctx
->regs
+ reg
);
662 writel(val
, ctx
->regs
+ reg
);
665 static void fimd_win_commit(struct exynos_drm_crtc
*crtc
, int zpos
)
667 struct fimd_context
*ctx
= crtc
->ctx
;
668 struct fimd_win_data
*win_data
;
670 unsigned long val
, alpha
, size
;
677 if (win
== DEFAULT_ZPOS
)
678 win
= ctx
->default_win
;
680 if (win
< 0 || win
>= WINDOWS_NR
)
683 win_data
= &ctx
->win_data
[win
];
685 /* If suspended, enable this on resume */
686 if (ctx
->suspended
) {
687 win_data
->resume
= true;
692 * SHADOWCON/PRTCON register is used for enabling timing.
694 * for example, once only width value of a register is set,
695 * if the dma is started then fimd hardware could malfunction so
696 * with protect window setting, the register fields with prefix '_F'
697 * wouldn't be updated at vsync also but updated once unprotect window
701 /* protect windows */
702 fimd_shadow_protect_win(ctx
, win
, true);
704 /* buffer start address */
705 val
= (unsigned long)win_data
->dma_addr
;
706 writel(val
, ctx
->regs
+ VIDWx_BUF_START(win
, 0));
708 /* buffer end address */
709 size
= win_data
->fb_pitch
* win_data
->ovl_height
* (win_data
->bpp
>> 3);
710 val
= (unsigned long)(win_data
->dma_addr
+ size
);
711 writel(val
, ctx
->regs
+ VIDWx_BUF_END(win
, 0));
713 DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
714 (unsigned long)win_data
->dma_addr
, val
, size
);
715 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
716 win_data
->ovl_width
, win_data
->ovl_height
);
719 val
= VIDW_BUF_SIZE_OFFSET(win_data
->buf_offsize
) |
720 VIDW_BUF_SIZE_PAGEWIDTH(win_data
->line_size
) |
721 VIDW_BUF_SIZE_OFFSET_E(win_data
->buf_offsize
) |
722 VIDW_BUF_SIZE_PAGEWIDTH_E(win_data
->line_size
);
723 writel(val
, ctx
->regs
+ VIDWx_BUF_SIZE(win
, 0));
726 val
= VIDOSDxA_TOPLEFT_X(win_data
->offset_x
) |
727 VIDOSDxA_TOPLEFT_Y(win_data
->offset_y
) |
728 VIDOSDxA_TOPLEFT_X_E(win_data
->offset_x
) |
729 VIDOSDxA_TOPLEFT_Y_E(win_data
->offset_y
);
730 writel(val
, ctx
->regs
+ VIDOSD_A(win
));
732 last_x
= win_data
->offset_x
+ win_data
->ovl_width
;
735 last_y
= win_data
->offset_y
+ win_data
->ovl_height
;
739 val
= VIDOSDxB_BOTRIGHT_X(last_x
) | VIDOSDxB_BOTRIGHT_Y(last_y
) |
740 VIDOSDxB_BOTRIGHT_X_E(last_x
) | VIDOSDxB_BOTRIGHT_Y_E(last_y
);
742 writel(val
, ctx
->regs
+ VIDOSD_B(win
));
744 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
745 win_data
->offset_x
, win_data
->offset_y
, last_x
, last_y
);
747 /* hardware window 0 doesn't support alpha channel. */
750 alpha
= VIDISD14C_ALPHA1_R(0xf) |
751 VIDISD14C_ALPHA1_G(0xf) |
752 VIDISD14C_ALPHA1_B(0xf);
754 writel(alpha
, ctx
->regs
+ VIDOSD_C(win
));
758 if (win
!= 3 && win
!= 4) {
759 u32 offset
= VIDOSD_D(win
);
761 offset
= VIDOSD_C(win
);
762 val
= win_data
->ovl_width
* win_data
->ovl_height
;
763 writel(val
, ctx
->regs
+ offset
);
765 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val
);
768 fimd_win_set_pixfmt(ctx
, win
);
770 /* hardware window 0 doesn't support color key. */
772 fimd_win_set_colkey(ctx
, win
);
774 fimd_enable_video_output(ctx
, win
, true);
776 if (ctx
->driver_data
->has_shadowcon
)
777 fimd_enable_shadow_channel_path(ctx
, win
, true);
779 /* Enable DMA channel and unprotect windows */
780 fimd_shadow_protect_win(ctx
, win
, false);
782 win_data
->enabled
= true;
785 atomic_set(&ctx
->win_updated
, 1);
788 static void fimd_win_disable(struct exynos_drm_crtc
*crtc
, int zpos
)
790 struct fimd_context
*ctx
= crtc
->ctx
;
791 struct fimd_win_data
*win_data
;
794 if (win
== DEFAULT_ZPOS
)
795 win
= ctx
->default_win
;
797 if (win
< 0 || win
>= WINDOWS_NR
)
800 win_data
= &ctx
->win_data
[win
];
802 if (ctx
->suspended
) {
803 /* do not resume this window*/
804 win_data
->resume
= false;
808 /* protect windows */
809 fimd_shadow_protect_win(ctx
, win
, true);
811 fimd_enable_video_output(ctx
, win
, false);
813 if (ctx
->driver_data
->has_shadowcon
)
814 fimd_enable_shadow_channel_path(ctx
, win
, false);
816 /* unprotect windows */
817 fimd_shadow_protect_win(ctx
, win
, false);
819 win_data
->enabled
= false;
822 static void fimd_window_suspend(struct fimd_context
*ctx
)
824 struct fimd_win_data
*win_data
;
827 for (i
= 0; i
< WINDOWS_NR
; i
++) {
828 win_data
= &ctx
->win_data
[i
];
829 win_data
->resume
= win_data
->enabled
;
830 if (win_data
->enabled
)
831 fimd_win_disable(ctx
->crtc
, i
);
835 static void fimd_window_resume(struct fimd_context
*ctx
)
837 struct fimd_win_data
*win_data
;
840 for (i
= 0; i
< WINDOWS_NR
; i
++) {
841 win_data
= &ctx
->win_data
[i
];
842 win_data
->enabled
= win_data
->resume
;
843 win_data
->resume
= false;
847 static void fimd_apply(struct fimd_context
*ctx
)
849 struct fimd_win_data
*win_data
;
852 for (i
= 0; i
< WINDOWS_NR
; i
++) {
853 win_data
= &ctx
->win_data
[i
];
854 if (win_data
->enabled
)
855 fimd_win_commit(ctx
->crtc
, i
);
857 fimd_win_disable(ctx
->crtc
, i
);
860 fimd_commit(ctx
->crtc
);
863 static int fimd_poweron(struct fimd_context
*ctx
)
870 ctx
->suspended
= false;
872 pm_runtime_get_sync(ctx
->dev
);
874 ret
= clk_prepare_enable(ctx
->bus_clk
);
876 DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret
);
880 ret
= clk_prepare_enable(ctx
->lcd_clk
);
882 DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret
);
886 /* if vblank was enabled status, enable it again. */
887 if (test_and_clear_bit(0, &ctx
->irq_flags
)) {
888 ret
= fimd_enable_vblank(ctx
->crtc
);
890 DRM_ERROR("Failed to re-enable vblank [%d]\n", ret
);
891 goto enable_vblank_err
;
895 fimd_window_resume(ctx
);
902 clk_disable_unprepare(ctx
->lcd_clk
);
904 clk_disable_unprepare(ctx
->bus_clk
);
906 ctx
->suspended
= true;
910 static int fimd_poweroff(struct fimd_context
*ctx
)
916 * We need to make sure that all windows are disabled before we
917 * suspend that connector. Otherwise we might try to scan from
918 * a destroyed buffer later.
920 fimd_window_suspend(ctx
);
922 clk_disable_unprepare(ctx
->lcd_clk
);
923 clk_disable_unprepare(ctx
->bus_clk
);
925 pm_runtime_put_sync(ctx
->dev
);
927 ctx
->suspended
= true;
931 static void fimd_dpms(struct exynos_drm_crtc
*crtc
, int mode
)
933 DRM_DEBUG_KMS("%s, %d\n", __FILE__
, mode
);
936 case DRM_MODE_DPMS_ON
:
937 fimd_poweron(crtc
->ctx
);
939 case DRM_MODE_DPMS_STANDBY
:
940 case DRM_MODE_DPMS_SUSPEND
:
941 case DRM_MODE_DPMS_OFF
:
942 fimd_poweroff(crtc
->ctx
);
945 DRM_DEBUG_KMS("unspecified mode %d\n", mode
);
950 static void fimd_trigger(struct device
*dev
)
952 struct fimd_context
*ctx
= dev_get_drvdata(dev
);
953 struct fimd_driver_data
*driver_data
= ctx
->driver_data
;
954 void *timing_base
= ctx
->regs
+ driver_data
->timing_base
;
958 * Skips triggering if in triggering state, because multiple triggering
959 * requests can cause panel reset.
961 if (atomic_read(&ctx
->triggering
))
964 /* Enters triggering mode */
965 atomic_set(&ctx
->triggering
, 1);
967 reg
= readl(timing_base
+ TRIGCON
);
968 reg
|= (TRGMODE_I80_RGB_ENABLE_I80
| SWTRGCMD_I80_RGB_ENABLE
);
969 writel(reg
, timing_base
+ TRIGCON
);
972 * Exits triggering mode if vblank is not enabled yet, because when the
973 * VIDINTCON0 register is not set, it can not exit from triggering mode.
975 if (!test_bit(0, &ctx
->irq_flags
))
976 atomic_set(&ctx
->triggering
, 0);
979 static void fimd_te_handler(struct exynos_drm_crtc
*crtc
)
981 struct fimd_context
*ctx
= crtc
->ctx
;
983 /* Checks the crtc is detached already from encoder */
984 if (ctx
->pipe
< 0 || !ctx
->drm_dev
)
988 * If there is a page flip request, triggers and handles the page flip
989 * event so that current fb can be updated into panel GRAM.
991 if (atomic_add_unless(&ctx
->win_updated
, -1, 0))
992 fimd_trigger(ctx
->dev
);
994 /* Wakes up vsync event queue */
995 if (atomic_read(&ctx
->wait_vsync_event
)) {
996 atomic_set(&ctx
->wait_vsync_event
, 0);
997 wake_up(&ctx
->wait_vsync_queue
);
1000 if (test_bit(0, &ctx
->irq_flags
))
1001 drm_handle_vblank(ctx
->drm_dev
, ctx
->pipe
);
1004 static struct exynos_drm_crtc_ops fimd_crtc_ops
= {
1006 .mode_fixup
= fimd_mode_fixup
,
1007 .commit
= fimd_commit
,
1008 .enable_vblank
= fimd_enable_vblank
,
1009 .disable_vblank
= fimd_disable_vblank
,
1010 .wait_for_vblank
= fimd_wait_for_vblank
,
1011 .win_mode_set
= fimd_win_mode_set
,
1012 .win_commit
= fimd_win_commit
,
1013 .win_disable
= fimd_win_disable
,
1014 .te_handler
= fimd_te_handler
,
1017 static irqreturn_t
fimd_irq_handler(int irq
, void *dev_id
)
1019 struct fimd_context
*ctx
= (struct fimd_context
*)dev_id
;
1022 val
= readl(ctx
->regs
+ VIDINTCON1
);
1024 clear_bit
= ctx
->i80_if
? VIDINTCON1_INT_I80
: VIDINTCON1_INT_FRAME
;
1025 if (val
& clear_bit
)
1026 writel(clear_bit
, ctx
->regs
+ VIDINTCON1
);
1028 /* check the crtc is detached already from encoder */
1029 if (ctx
->pipe
< 0 || !ctx
->drm_dev
)
1033 exynos_drm_crtc_finish_pageflip(ctx
->drm_dev
, ctx
->pipe
);
1035 /* Exits triggering mode */
1036 atomic_set(&ctx
->triggering
, 0);
1038 drm_handle_vblank(ctx
->drm_dev
, ctx
->pipe
);
1039 exynos_drm_crtc_finish_pageflip(ctx
->drm_dev
, ctx
->pipe
);
1041 /* set wait vsync event to zero and wake up queue. */
1042 if (atomic_read(&ctx
->wait_vsync_event
)) {
1043 atomic_set(&ctx
->wait_vsync_event
, 0);
1044 wake_up(&ctx
->wait_vsync_queue
);
1052 static int fimd_bind(struct device
*dev
, struct device
*master
, void *data
)
1054 struct fimd_context
*ctx
= dev_get_drvdata(dev
);
1055 struct drm_device
*drm_dev
= data
;
1056 struct exynos_drm_private
*priv
= drm_dev
->dev_private
;
1059 ctx
->drm_dev
= drm_dev
;
1060 ctx
->pipe
= priv
->pipe
++;
1062 ctx
->crtc
= exynos_drm_crtc_create(drm_dev
, ctx
->pipe
,
1063 EXYNOS_DISPLAY_TYPE_LCD
,
1064 &fimd_crtc_ops
, ctx
);
1067 exynos_drm_create_enc_conn(drm_dev
, ctx
->display
);
1069 ret
= fimd_iommu_attach_devices(ctx
, drm_dev
);
1077 static void fimd_unbind(struct device
*dev
, struct device
*master
,
1080 struct fimd_context
*ctx
= dev_get_drvdata(dev
);
1082 fimd_dpms(ctx
->crtc
, DRM_MODE_DPMS_OFF
);
1084 fimd_iommu_detach_devices(ctx
);
1087 exynos_dpi_remove(ctx
->display
);
1090 static const struct component_ops fimd_component_ops
= {
1092 .unbind
= fimd_unbind
,
1095 static int fimd_probe(struct platform_device
*pdev
)
1097 struct device
*dev
= &pdev
->dev
;
1098 struct fimd_context
*ctx
;
1099 struct device_node
*i80_if_timings
;
1100 struct resource
*res
;
1106 ctx
= devm_kzalloc(dev
, sizeof(*ctx
), GFP_KERNEL
);
1110 ret
= exynos_drm_component_add(dev
, EXYNOS_DEVICE_TYPE_CRTC
,
1111 EXYNOS_DISPLAY_TYPE_LCD
);
1116 ctx
->suspended
= true;
1117 ctx
->driver_data
= drm_fimd_get_driver_data(pdev
);
1119 if (of_property_read_bool(dev
->of_node
, "samsung,invert-vden"))
1120 ctx
->vidcon1
|= VIDCON1_INV_VDEN
;
1121 if (of_property_read_bool(dev
->of_node
, "samsung,invert-vclk"))
1122 ctx
->vidcon1
|= VIDCON1_INV_VCLK
;
1124 i80_if_timings
= of_get_child_by_name(dev
->of_node
, "i80-if-timings");
1125 if (i80_if_timings
) {
1130 if (ctx
->driver_data
->has_vidoutcon
)
1131 ctx
->vidout_con
|= VIDOUT_CON_F_I80_LDI0
;
1133 ctx
->vidcon0
|= VIDCON0_VIDOUT_I80_LDI0
;
1135 * The user manual describes that this "DSI_EN" bit is required
1136 * to enable I80 24-bit data interface.
1138 ctx
->vidcon0
|= VIDCON0_DSI_EN
;
1140 if (of_property_read_u32(i80_if_timings
, "cs-setup", &val
))
1142 ctx
->i80ifcon
= LCD_CS_SETUP(val
);
1143 if (of_property_read_u32(i80_if_timings
, "wr-setup", &val
))
1145 ctx
->i80ifcon
|= LCD_WR_SETUP(val
);
1146 if (of_property_read_u32(i80_if_timings
, "wr-active", &val
))
1148 ctx
->i80ifcon
|= LCD_WR_ACTIVE(val
);
1149 if (of_property_read_u32(i80_if_timings
, "wr-hold", &val
))
1151 ctx
->i80ifcon
|= LCD_WR_HOLD(val
);
1153 of_node_put(i80_if_timings
);
1155 ctx
->sysreg
= syscon_regmap_lookup_by_phandle(dev
->of_node
,
1157 if (IS_ERR(ctx
->sysreg
)) {
1158 dev_warn(dev
, "failed to get system register.\n");
1162 ctx
->bus_clk
= devm_clk_get(dev
, "fimd");
1163 if (IS_ERR(ctx
->bus_clk
)) {
1164 dev_err(dev
, "failed to get bus clock\n");
1165 ret
= PTR_ERR(ctx
->bus_clk
);
1166 goto err_del_component
;
1169 ctx
->lcd_clk
= devm_clk_get(dev
, "sclk_fimd");
1170 if (IS_ERR(ctx
->lcd_clk
)) {
1171 dev_err(dev
, "failed to get lcd clock\n");
1172 ret
= PTR_ERR(ctx
->lcd_clk
);
1173 goto err_del_component
;
1176 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1178 ctx
->regs
= devm_ioremap_resource(dev
, res
);
1179 if (IS_ERR(ctx
->regs
)) {
1180 ret
= PTR_ERR(ctx
->regs
);
1181 goto err_del_component
;
1184 res
= platform_get_resource_byname(pdev
, IORESOURCE_IRQ
,
1185 ctx
->i80_if
? "lcd_sys" : "vsync");
1187 dev_err(dev
, "irq request failed.\n");
1189 goto err_del_component
;
1192 ret
= devm_request_irq(dev
, res
->start
, fimd_irq_handler
,
1193 0, "drm_fimd", ctx
);
1195 dev_err(dev
, "irq request failed.\n");
1196 goto err_del_component
;
1199 init_waitqueue_head(&ctx
->wait_vsync_queue
);
1200 atomic_set(&ctx
->wait_vsync_event
, 0);
1202 platform_set_drvdata(pdev
, ctx
);
1204 ctx
->display
= exynos_dpi_probe(dev
);
1205 if (IS_ERR(ctx
->display
)) {
1206 ret
= PTR_ERR(ctx
->display
);
1207 goto err_del_component
;
1210 pm_runtime_enable(dev
);
1212 ret
= component_add(dev
, &fimd_component_ops
);
1214 goto err_disable_pm_runtime
;
1218 err_disable_pm_runtime
:
1219 pm_runtime_disable(dev
);
1222 exynos_drm_component_del(dev
, EXYNOS_DEVICE_TYPE_CRTC
);
1226 static int fimd_remove(struct platform_device
*pdev
)
1228 pm_runtime_disable(&pdev
->dev
);
1230 component_del(&pdev
->dev
, &fimd_component_ops
);
1231 exynos_drm_component_del(&pdev
->dev
, EXYNOS_DEVICE_TYPE_CRTC
);
1236 struct platform_driver fimd_driver
= {
1237 .probe
= fimd_probe
,
1238 .remove
= fimd_remove
,
1240 .name
= "exynos4-fb",
1241 .owner
= THIS_MODULE
,
1242 .of_match_table
= fimd_driver_dt_match
,