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drm/exynos: Remove tracking log functions
[deliverable/linux.git] / drivers / gpu / drm / exynos / exynos_drm_gsc.c
1 /*
2 * Copyright (C) 2012 Samsung Electronics Co.Ltd
3 * Authors:
4 * Eunchul Kim <chulspro.kim@samsung.com>
5 * Jinyoung Jeon <jy0.jeon@samsung.com>
6 * Sangmin Lee <lsmin.lee@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/platform_device.h>
17 #include <linux/clk.h>
18 #include <linux/pm_runtime.h>
19 #include <plat/map-base.h>
20
21 #include <drm/drmP.h>
22 #include <drm/exynos_drm.h>
23 #include "regs-gsc.h"
24 #include "exynos_drm_ipp.h"
25 #include "exynos_drm_gsc.h"
26
27 /*
28 * GSC stands for General SCaler and
29 * supports image scaler/rotator and input/output DMA operations.
30 * input DMA reads image data from the memory.
31 * output DMA writes image data to memory.
32 * GSC supports image rotation and image effect functions.
33 *
34 * M2M operation : supports crop/scale/rotation/csc so on.
35 * Memory ----> GSC H/W ----> Memory.
36 * Writeback operation : supports cloned screen with FIMD.
37 * FIMD ----> GSC H/W ----> Memory.
38 * Output operation : supports direct display using local path.
39 * Memory ----> GSC H/W ----> FIMD, Mixer.
40 */
41
42 /*
43 * TODO
44 * 1. check suspend/resume api if needed.
45 * 2. need to check use case platform_device_id.
46 * 3. check src/dst size with, height.
47 * 4. added check_prepare api for right register.
48 * 5. need to add supported list in prop_list.
49 * 6. check prescaler/scaler optimization.
50 */
51
52 #define GSC_MAX_DEVS 4
53 #define GSC_MAX_SRC 4
54 #define GSC_MAX_DST 16
55 #define GSC_RESET_TIMEOUT 50
56 #define GSC_BUF_STOP 1
57 #define GSC_BUF_START 2
58 #define GSC_REG_SZ 16
59 #define GSC_WIDTH_ITU_709 1280
60 #define GSC_SC_UP_MAX_RATIO 65536
61 #define GSC_SC_DOWN_RATIO_7_8 74898
62 #define GSC_SC_DOWN_RATIO_6_8 87381
63 #define GSC_SC_DOWN_RATIO_5_8 104857
64 #define GSC_SC_DOWN_RATIO_4_8 131072
65 #define GSC_SC_DOWN_RATIO_3_8 174762
66 #define GSC_SC_DOWN_RATIO_2_8 262144
67 #define GSC_REFRESH_MIN 12
68 #define GSC_REFRESH_MAX 60
69 #define GSC_CROP_MAX 8192
70 #define GSC_CROP_MIN 32
71 #define GSC_SCALE_MAX 4224
72 #define GSC_SCALE_MIN 32
73 #define GSC_COEF_RATIO 7
74 #define GSC_COEF_PHASE 9
75 #define GSC_COEF_ATTR 16
76 #define GSC_COEF_H_8T 8
77 #define GSC_COEF_V_4T 4
78 #define GSC_COEF_DEPTH 3
79
80 #define get_gsc_context(dev) platform_get_drvdata(to_platform_device(dev))
81 #define get_ctx_from_ippdrv(ippdrv) container_of(ippdrv,\
82 struct gsc_context, ippdrv);
83 #define gsc_read(offset) readl(ctx->regs + (offset))
84 #define gsc_write(cfg, offset) writel(cfg, ctx->regs + (offset))
85
86 /*
87 * A structure of scaler.
88 *
89 * @range: narrow, wide.
90 * @pre_shfactor: pre sclaer shift factor.
91 * @pre_hratio: horizontal ratio of the prescaler.
92 * @pre_vratio: vertical ratio of the prescaler.
93 * @main_hratio: the main scaler's horizontal ratio.
94 * @main_vratio: the main scaler's vertical ratio.
95 */
96 struct gsc_scaler {
97 bool range;
98 u32 pre_shfactor;
99 u32 pre_hratio;
100 u32 pre_vratio;
101 unsigned long main_hratio;
102 unsigned long main_vratio;
103 };
104
105 /*
106 * A structure of scaler capability.
107 *
108 * find user manual 49.2 features.
109 * @tile_w: tile mode or rotation width.
110 * @tile_h: tile mode or rotation height.
111 * @w: other cases width.
112 * @h: other cases height.
113 */
114 struct gsc_capability {
115 /* tile or rotation */
116 u32 tile_w;
117 u32 tile_h;
118 /* other cases */
119 u32 w;
120 u32 h;
121 };
122
123 /*
124 * A structure of gsc context.
125 *
126 * @ippdrv: prepare initialization using ippdrv.
127 * @regs_res: register resources.
128 * @regs: memory mapped io registers.
129 * @lock: locking of operations.
130 * @gsc_clk: gsc gate clock.
131 * @sc: scaler infomations.
132 * @id: gsc id.
133 * @irq: irq number.
134 * @rotation: supports rotation of src.
135 * @suspended: qos operations.
136 */
137 struct gsc_context {
138 struct exynos_drm_ippdrv ippdrv;
139 struct resource *regs_res;
140 void __iomem *regs;
141 struct mutex lock;
142 struct clk *gsc_clk;
143 struct gsc_scaler sc;
144 int id;
145 int irq;
146 bool rotation;
147 bool suspended;
148 };
149
150 /* 8-tap Filter Coefficient */
151 static const int h_coef_8t[GSC_COEF_RATIO][GSC_COEF_ATTR][GSC_COEF_H_8T] = {
152 { /* Ratio <= 65536 (~8:8) */
153 { 0, 0, 0, 128, 0, 0, 0, 0 },
154 { -1, 2, -6, 127, 7, -2, 1, 0 },
155 { -1, 4, -12, 125, 16, -5, 1, 0 },
156 { -1, 5, -15, 120, 25, -8, 2, 0 },
157 { -1, 6, -18, 114, 35, -10, 3, -1 },
158 { -1, 6, -20, 107, 46, -13, 4, -1 },
159 { -2, 7, -21, 99, 57, -16, 5, -1 },
160 { -1, 6, -20, 89, 68, -18, 5, -1 },
161 { -1, 6, -20, 79, 79, -20, 6, -1 },
162 { -1, 5, -18, 68, 89, -20, 6, -1 },
163 { -1, 5, -16, 57, 99, -21, 7, -2 },
164 { -1, 4, -13, 46, 107, -20, 6, -1 },
165 { -1, 3, -10, 35, 114, -18, 6, -1 },
166 { 0, 2, -8, 25, 120, -15, 5, -1 },
167 { 0, 1, -5, 16, 125, -12, 4, -1 },
168 { 0, 1, -2, 7, 127, -6, 2, -1 }
169 }, { /* 65536 < Ratio <= 74898 (~8:7) */
170 { 3, -8, 14, 111, 13, -8, 3, 0 },
171 { 2, -6, 7, 112, 21, -10, 3, -1 },
172 { 2, -4, 1, 110, 28, -12, 4, -1 },
173 { 1, -2, -3, 106, 36, -13, 4, -1 },
174 { 1, -1, -7, 103, 44, -15, 4, -1 },
175 { 1, 1, -11, 97, 53, -16, 4, -1 },
176 { 0, 2, -13, 91, 61, -16, 4, -1 },
177 { 0, 3, -15, 85, 69, -17, 4, -1 },
178 { 0, 3, -16, 77, 77, -16, 3, 0 },
179 { -1, 4, -17, 69, 85, -15, 3, 0 },
180 { -1, 4, -16, 61, 91, -13, 2, 0 },
181 { -1, 4, -16, 53, 97, -11, 1, 1 },
182 { -1, 4, -15, 44, 103, -7, -1, 1 },
183 { -1, 4, -13, 36, 106, -3, -2, 1 },
184 { -1, 4, -12, 28, 110, 1, -4, 2 },
185 { -1, 3, -10, 21, 112, 7, -6, 2 }
186 }, { /* 74898 < Ratio <= 87381 (~8:6) */
187 { 2, -11, 25, 96, 25, -11, 2, 0 },
188 { 2, -10, 19, 96, 31, -12, 2, 0 },
189 { 2, -9, 14, 94, 37, -12, 2, 0 },
190 { 2, -8, 10, 92, 43, -12, 1, 0 },
191 { 2, -7, 5, 90, 49, -12, 1, 0 },
192 { 2, -5, 1, 86, 55, -12, 0, 1 },
193 { 2, -4, -2, 82, 61, -11, -1, 1 },
194 { 1, -3, -5, 77, 67, -9, -1, 1 },
195 { 1, -2, -7, 72, 72, -7, -2, 1 },
196 { 1, -1, -9, 67, 77, -5, -3, 1 },
197 { 1, -1, -11, 61, 82, -2, -4, 2 },
198 { 1, 0, -12, 55, 86, 1, -5, 2 },
199 { 0, 1, -12, 49, 90, 5, -7, 2 },
200 { 0, 1, -12, 43, 92, 10, -8, 2 },
201 { 0, 2, -12, 37, 94, 14, -9, 2 },
202 { 0, 2, -12, 31, 96, 19, -10, 2 }
203 }, { /* 87381 < Ratio <= 104857 (~8:5) */
204 { -1, -8, 33, 80, 33, -8, -1, 0 },
205 { -1, -8, 28, 80, 37, -7, -2, 1 },
206 { 0, -8, 24, 79, 41, -7, -2, 1 },
207 { 0, -8, 20, 78, 46, -6, -3, 1 },
208 { 0, -8, 16, 76, 50, -4, -3, 1 },
209 { 0, -7, 13, 74, 54, -3, -4, 1 },
210 { 1, -7, 10, 71, 58, -1, -5, 1 },
211 { 1, -6, 6, 68, 62, 1, -5, 1 },
212 { 1, -6, 4, 65, 65, 4, -6, 1 },
213 { 1, -5, 1, 62, 68, 6, -6, 1 },
214 { 1, -5, -1, 58, 71, 10, -7, 1 },
215 { 1, -4, -3, 54, 74, 13, -7, 0 },
216 { 1, -3, -4, 50, 76, 16, -8, 0 },
217 { 1, -3, -6, 46, 78, 20, -8, 0 },
218 { 1, -2, -7, 41, 79, 24, -8, 0 },
219 { 1, -2, -7, 37, 80, 28, -8, -1 }
220 }, { /* 104857 < Ratio <= 131072 (~8:4) */
221 { -3, 0, 35, 64, 35, 0, -3, 0 },
222 { -3, -1, 32, 64, 38, 1, -3, 0 },
223 { -2, -2, 29, 63, 41, 2, -3, 0 },
224 { -2, -3, 27, 63, 43, 4, -4, 0 },
225 { -2, -3, 24, 61, 46, 6, -4, 0 },
226 { -2, -3, 21, 60, 49, 7, -4, 0 },
227 { -1, -4, 19, 59, 51, 9, -4, -1 },
228 { -1, -4, 16, 57, 53, 12, -4, -1 },
229 { -1, -4, 14, 55, 55, 14, -4, -1 },
230 { -1, -4, 12, 53, 57, 16, -4, -1 },
231 { -1, -4, 9, 51, 59, 19, -4, -1 },
232 { 0, -4, 7, 49, 60, 21, -3, -2 },
233 { 0, -4, 6, 46, 61, 24, -3, -2 },
234 { 0, -4, 4, 43, 63, 27, -3, -2 },
235 { 0, -3, 2, 41, 63, 29, -2, -2 },
236 { 0, -3, 1, 38, 64, 32, -1, -3 }
237 }, { /* 131072 < Ratio <= 174762 (~8:3) */
238 { -1, 8, 33, 48, 33, 8, -1, 0 },
239 { -1, 7, 31, 49, 35, 9, -1, -1 },
240 { -1, 6, 30, 49, 36, 10, -1, -1 },
241 { -1, 5, 28, 48, 38, 12, -1, -1 },
242 { -1, 4, 26, 48, 39, 13, 0, -1 },
243 { -1, 3, 24, 47, 41, 15, 0, -1 },
244 { -1, 2, 23, 47, 42, 16, 0, -1 },
245 { -1, 2, 21, 45, 43, 18, 1, -1 },
246 { -1, 1, 19, 45, 45, 19, 1, -1 },
247 { -1, 1, 18, 43, 45, 21, 2, -1 },
248 { -1, 0, 16, 42, 47, 23, 2, -1 },
249 { -1, 0, 15, 41, 47, 24, 3, -1 },
250 { -1, 0, 13, 39, 48, 26, 4, -1 },
251 { -1, -1, 12, 38, 48, 28, 5, -1 },
252 { -1, -1, 10, 36, 49, 30, 6, -1 },
253 { -1, -1, 9, 35, 49, 31, 7, -1 }
254 }, { /* 174762 < Ratio <= 262144 (~8:2) */
255 { 2, 13, 30, 38, 30, 13, 2, 0 },
256 { 2, 12, 29, 38, 30, 14, 3, 0 },
257 { 2, 11, 28, 38, 31, 15, 3, 0 },
258 { 2, 10, 26, 38, 32, 16, 4, 0 },
259 { 1, 10, 26, 37, 33, 17, 4, 0 },
260 { 1, 9, 24, 37, 34, 18, 5, 0 },
261 { 1, 8, 24, 37, 34, 19, 5, 0 },
262 { 1, 7, 22, 36, 35, 20, 6, 1 },
263 { 1, 6, 21, 36, 36, 21, 6, 1 },
264 { 1, 6, 20, 35, 36, 22, 7, 1 },
265 { 0, 5, 19, 34, 37, 24, 8, 1 },
266 { 0, 5, 18, 34, 37, 24, 9, 1 },
267 { 0, 4, 17, 33, 37, 26, 10, 1 },
268 { 0, 4, 16, 32, 38, 26, 10, 2 },
269 { 0, 3, 15, 31, 38, 28, 11, 2 },
270 { 0, 3, 14, 30, 38, 29, 12, 2 }
271 }
272 };
273
274 /* 4-tap Filter Coefficient */
275 static const int v_coef_4t[GSC_COEF_RATIO][GSC_COEF_ATTR][GSC_COEF_V_4T] = {
276 { /* Ratio <= 65536 (~8:8) */
277 { 0, 128, 0, 0 },
278 { -4, 127, 5, 0 },
279 { -6, 124, 11, -1 },
280 { -8, 118, 19, -1 },
281 { -8, 111, 27, -2 },
282 { -8, 102, 37, -3 },
283 { -8, 92, 48, -4 },
284 { -7, 81, 59, -5 },
285 { -6, 70, 70, -6 },
286 { -5, 59, 81, -7 },
287 { -4, 48, 92, -8 },
288 { -3, 37, 102, -8 },
289 { -2, 27, 111, -8 },
290 { -1, 19, 118, -8 },
291 { -1, 11, 124, -6 },
292 { 0, 5, 127, -4 }
293 }, { /* 65536 < Ratio <= 74898 (~8:7) */
294 { 8, 112, 8, 0 },
295 { 4, 111, 14, -1 },
296 { 1, 109, 20, -2 },
297 { -2, 105, 27, -2 },
298 { -3, 100, 34, -3 },
299 { -5, 93, 43, -3 },
300 { -5, 86, 51, -4 },
301 { -5, 77, 60, -4 },
302 { -5, 69, 69, -5 },
303 { -4, 60, 77, -5 },
304 { -4, 51, 86, -5 },
305 { -3, 43, 93, -5 },
306 { -3, 34, 100, -3 },
307 { -2, 27, 105, -2 },
308 { -2, 20, 109, 1 },
309 { -1, 14, 111, 4 }
310 }, { /* 74898 < Ratio <= 87381 (~8:6) */
311 { 16, 96, 16, 0 },
312 { 12, 97, 21, -2 },
313 { 8, 96, 26, -2 },
314 { 5, 93, 32, -2 },
315 { 2, 89, 39, -2 },
316 { 0, 84, 46, -2 },
317 { -1, 79, 53, -3 },
318 { -2, 73, 59, -2 },
319 { -2, 66, 66, -2 },
320 { -2, 59, 73, -2 },
321 { -3, 53, 79, -1 },
322 { -2, 46, 84, 0 },
323 { -2, 39, 89, 2 },
324 { -2, 32, 93, 5 },
325 { -2, 26, 96, 8 },
326 { -2, 21, 97, 12 }
327 }, { /* 87381 < Ratio <= 104857 (~8:5) */
328 { 22, 84, 22, 0 },
329 { 18, 85, 26, -1 },
330 { 14, 84, 31, -1 },
331 { 11, 82, 36, -1 },
332 { 8, 79, 42, -1 },
333 { 6, 76, 47, -1 },
334 { 4, 72, 52, 0 },
335 { 2, 68, 58, 0 },
336 { 1, 63, 63, 1 },
337 { 0, 58, 68, 2 },
338 { 0, 52, 72, 4 },
339 { -1, 47, 76, 6 },
340 { -1, 42, 79, 8 },
341 { -1, 36, 82, 11 },
342 { -1, 31, 84, 14 },
343 { -1, 26, 85, 18 }
344 }, { /* 104857 < Ratio <= 131072 (~8:4) */
345 { 26, 76, 26, 0 },
346 { 22, 76, 30, 0 },
347 { 19, 75, 34, 0 },
348 { 16, 73, 38, 1 },
349 { 13, 71, 43, 1 },
350 { 10, 69, 47, 2 },
351 { 8, 66, 51, 3 },
352 { 6, 63, 55, 4 },
353 { 5, 59, 59, 5 },
354 { 4, 55, 63, 6 },
355 { 3, 51, 66, 8 },
356 { 2, 47, 69, 10 },
357 { 1, 43, 71, 13 },
358 { 1, 38, 73, 16 },
359 { 0, 34, 75, 19 },
360 { 0, 30, 76, 22 }
361 }, { /* 131072 < Ratio <= 174762 (~8:3) */
362 { 29, 70, 29, 0 },
363 { 26, 68, 32, 2 },
364 { 23, 67, 36, 2 },
365 { 20, 66, 39, 3 },
366 { 17, 65, 43, 3 },
367 { 15, 63, 46, 4 },
368 { 12, 61, 50, 5 },
369 { 10, 58, 53, 7 },
370 { 8, 56, 56, 8 },
371 { 7, 53, 58, 10 },
372 { 5, 50, 61, 12 },
373 { 4, 46, 63, 15 },
374 { 3, 43, 65, 17 },
375 { 3, 39, 66, 20 },
376 { 2, 36, 67, 23 },
377 { 2, 32, 68, 26 }
378 }, { /* 174762 < Ratio <= 262144 (~8:2) */
379 { 32, 64, 32, 0 },
380 { 28, 63, 34, 3 },
381 { 25, 62, 37, 4 },
382 { 22, 62, 40, 4 },
383 { 19, 61, 43, 5 },
384 { 17, 59, 46, 6 },
385 { 15, 58, 48, 7 },
386 { 13, 55, 51, 9 },
387 { 11, 53, 53, 11 },
388 { 9, 51, 55, 13 },
389 { 7, 48, 58, 15 },
390 { 6, 46, 59, 17 },
391 { 5, 43, 61, 19 },
392 { 4, 40, 62, 22 },
393 { 4, 37, 62, 25 },
394 { 3, 34, 63, 28 }
395 }
396 };
397
398 static int gsc_sw_reset(struct gsc_context *ctx)
399 {
400 u32 cfg;
401 int count = GSC_RESET_TIMEOUT;
402
403 /* s/w reset */
404 cfg = (GSC_SW_RESET_SRESET);
405 gsc_write(cfg, GSC_SW_RESET);
406
407 /* wait s/w reset complete */
408 while (count--) {
409 cfg = gsc_read(GSC_SW_RESET);
410 if (!cfg)
411 break;
412 usleep_range(1000, 2000);
413 }
414
415 if (cfg) {
416 DRM_ERROR("failed to reset gsc h/w.\n");
417 return -EBUSY;
418 }
419
420 /* reset sequence */
421 cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK);
422 cfg |= (GSC_IN_BASE_ADDR_MASK |
423 GSC_IN_BASE_ADDR_PINGPONG(0));
424 gsc_write(cfg, GSC_IN_BASE_ADDR_Y_MASK);
425 gsc_write(cfg, GSC_IN_BASE_ADDR_CB_MASK);
426 gsc_write(cfg, GSC_IN_BASE_ADDR_CR_MASK);
427
428 cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
429 cfg |= (GSC_OUT_BASE_ADDR_MASK |
430 GSC_OUT_BASE_ADDR_PINGPONG(0));
431 gsc_write(cfg, GSC_OUT_BASE_ADDR_Y_MASK);
432 gsc_write(cfg, GSC_OUT_BASE_ADDR_CB_MASK);
433 gsc_write(cfg, GSC_OUT_BASE_ADDR_CR_MASK);
434
435 return 0;
436 }
437
438 static void gsc_set_gscblk_fimd_wb(struct gsc_context *ctx, bool enable)
439 {
440 u32 gscblk_cfg;
441
442 gscblk_cfg = readl(SYSREG_GSCBLK_CFG1);
443
444 if (enable)
445 gscblk_cfg |= GSC_BLK_DISP1WB_DEST(ctx->id) |
446 GSC_BLK_GSCL_WB_IN_SRC_SEL(ctx->id) |
447 GSC_BLK_SW_RESET_WB_DEST(ctx->id);
448 else
449 gscblk_cfg |= GSC_BLK_PXLASYNC_LO_MASK_WB(ctx->id);
450
451 writel(gscblk_cfg, SYSREG_GSCBLK_CFG1);
452 }
453
454 static void gsc_handle_irq(struct gsc_context *ctx, bool enable,
455 bool overflow, bool done)
456 {
457 u32 cfg;
458
459 DRM_DEBUG_KMS("%s:enable[%d]overflow[%d]level[%d]\n", __func__,
460 enable, overflow, done);
461
462 cfg = gsc_read(GSC_IRQ);
463 cfg |= (GSC_IRQ_OR_MASK | GSC_IRQ_FRMDONE_MASK);
464
465 if (enable)
466 cfg |= GSC_IRQ_ENABLE;
467 else
468 cfg &= ~GSC_IRQ_ENABLE;
469
470 if (overflow)
471 cfg &= ~GSC_IRQ_OR_MASK;
472 else
473 cfg |= GSC_IRQ_OR_MASK;
474
475 if (done)
476 cfg &= ~GSC_IRQ_FRMDONE_MASK;
477 else
478 cfg |= GSC_IRQ_FRMDONE_MASK;
479
480 gsc_write(cfg, GSC_IRQ);
481 }
482
483
484 static int gsc_src_set_fmt(struct device *dev, u32 fmt)
485 {
486 struct gsc_context *ctx = get_gsc_context(dev);
487 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
488 u32 cfg;
489
490 DRM_DEBUG_KMS("%s:fmt[0x%x]\n", __func__, fmt);
491
492 cfg = gsc_read(GSC_IN_CON);
493 cfg &= ~(GSC_IN_RGB_TYPE_MASK | GSC_IN_YUV422_1P_ORDER_MASK |
494 GSC_IN_CHROMA_ORDER_MASK | GSC_IN_FORMAT_MASK |
495 GSC_IN_TILE_TYPE_MASK | GSC_IN_TILE_MODE |
496 GSC_IN_CHROM_STRIDE_SEL_MASK | GSC_IN_RB_SWAP_MASK);
497
498 switch (fmt) {
499 case DRM_FORMAT_RGB565:
500 cfg |= GSC_IN_RGB565;
501 break;
502 case DRM_FORMAT_XRGB8888:
503 cfg |= GSC_IN_XRGB8888;
504 break;
505 case DRM_FORMAT_BGRX8888:
506 cfg |= (GSC_IN_XRGB8888 | GSC_IN_RB_SWAP);
507 break;
508 case DRM_FORMAT_YUYV:
509 cfg |= (GSC_IN_YUV422_1P |
510 GSC_IN_YUV422_1P_ORDER_LSB_Y |
511 GSC_IN_CHROMA_ORDER_CBCR);
512 break;
513 case DRM_FORMAT_YVYU:
514 cfg |= (GSC_IN_YUV422_1P |
515 GSC_IN_YUV422_1P_ORDER_LSB_Y |
516 GSC_IN_CHROMA_ORDER_CRCB);
517 break;
518 case DRM_FORMAT_UYVY:
519 cfg |= (GSC_IN_YUV422_1P |
520 GSC_IN_YUV422_1P_OEDER_LSB_C |
521 GSC_IN_CHROMA_ORDER_CBCR);
522 break;
523 case DRM_FORMAT_VYUY:
524 cfg |= (GSC_IN_YUV422_1P |
525 GSC_IN_YUV422_1P_OEDER_LSB_C |
526 GSC_IN_CHROMA_ORDER_CRCB);
527 break;
528 case DRM_FORMAT_NV21:
529 case DRM_FORMAT_NV61:
530 cfg |= (GSC_IN_CHROMA_ORDER_CRCB |
531 GSC_IN_YUV420_2P);
532 break;
533 case DRM_FORMAT_YUV422:
534 cfg |= GSC_IN_YUV422_3P;
535 break;
536 case DRM_FORMAT_YUV420:
537 case DRM_FORMAT_YVU420:
538 cfg |= GSC_IN_YUV420_3P;
539 break;
540 case DRM_FORMAT_NV12:
541 case DRM_FORMAT_NV16:
542 cfg |= (GSC_IN_CHROMA_ORDER_CBCR |
543 GSC_IN_YUV420_2P);
544 break;
545 case DRM_FORMAT_NV12MT:
546 cfg |= (GSC_IN_TILE_C_16x8 | GSC_IN_TILE_MODE);
547 break;
548 default:
549 dev_err(ippdrv->dev, "inavlid target yuv order 0x%x.\n", fmt);
550 return -EINVAL;
551 }
552
553 gsc_write(cfg, GSC_IN_CON);
554
555 return 0;
556 }
557
558 static int gsc_src_set_transf(struct device *dev,
559 enum drm_exynos_degree degree,
560 enum drm_exynos_flip flip, bool *swap)
561 {
562 struct gsc_context *ctx = get_gsc_context(dev);
563 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
564 u32 cfg;
565
566 DRM_DEBUG_KMS("%s:degree[%d]flip[0x%x]\n", __func__,
567 degree, flip);
568
569 cfg = gsc_read(GSC_IN_CON);
570 cfg &= ~GSC_IN_ROT_MASK;
571
572 switch (degree) {
573 case EXYNOS_DRM_DEGREE_0:
574 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
575 cfg |= GSC_IN_ROT_XFLIP;
576 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
577 cfg |= GSC_IN_ROT_YFLIP;
578 break;
579 case EXYNOS_DRM_DEGREE_90:
580 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
581 cfg |= GSC_IN_ROT_90_XFLIP;
582 else if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
583 cfg |= GSC_IN_ROT_90_YFLIP;
584 else
585 cfg |= GSC_IN_ROT_90;
586 break;
587 case EXYNOS_DRM_DEGREE_180:
588 cfg |= GSC_IN_ROT_180;
589 break;
590 case EXYNOS_DRM_DEGREE_270:
591 cfg |= GSC_IN_ROT_270;
592 break;
593 default:
594 dev_err(ippdrv->dev, "inavlid degree value %d.\n", degree);
595 return -EINVAL;
596 }
597
598 gsc_write(cfg, GSC_IN_CON);
599
600 ctx->rotation = cfg &
601 (GSC_IN_ROT_90 | GSC_IN_ROT_270) ? 1 : 0;
602 *swap = ctx->rotation;
603
604 return 0;
605 }
606
607 static int gsc_src_set_size(struct device *dev, int swap,
608 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz)
609 {
610 struct gsc_context *ctx = get_gsc_context(dev);
611 struct drm_exynos_pos img_pos = *pos;
612 struct gsc_scaler *sc = &ctx->sc;
613 u32 cfg;
614
615 DRM_DEBUG_KMS("%s:swap[%d]x[%d]y[%d]w[%d]h[%d]\n",
616 __func__, swap, pos->x, pos->y, pos->w, pos->h);
617
618 if (swap) {
619 img_pos.w = pos->h;
620 img_pos.h = pos->w;
621 }
622
623 /* pixel offset */
624 cfg = (GSC_SRCIMG_OFFSET_X(img_pos.x) |
625 GSC_SRCIMG_OFFSET_Y(img_pos.y));
626 gsc_write(cfg, GSC_SRCIMG_OFFSET);
627
628 /* cropped size */
629 cfg = (GSC_CROPPED_WIDTH(img_pos.w) |
630 GSC_CROPPED_HEIGHT(img_pos.h));
631 gsc_write(cfg, GSC_CROPPED_SIZE);
632
633 DRM_DEBUG_KMS("%s:hsize[%d]vsize[%d]\n",
634 __func__, sz->hsize, sz->vsize);
635
636 /* original size */
637 cfg = gsc_read(GSC_SRCIMG_SIZE);
638 cfg &= ~(GSC_SRCIMG_HEIGHT_MASK |
639 GSC_SRCIMG_WIDTH_MASK);
640
641 cfg |= (GSC_SRCIMG_WIDTH(sz->hsize) |
642 GSC_SRCIMG_HEIGHT(sz->vsize));
643
644 gsc_write(cfg, GSC_SRCIMG_SIZE);
645
646 cfg = gsc_read(GSC_IN_CON);
647 cfg &= ~GSC_IN_RGB_TYPE_MASK;
648
649 DRM_DEBUG_KMS("%s:width[%d]range[%d]\n",
650 __func__, pos->w, sc->range);
651
652 if (pos->w >= GSC_WIDTH_ITU_709)
653 if (sc->range)
654 cfg |= GSC_IN_RGB_HD_WIDE;
655 else
656 cfg |= GSC_IN_RGB_HD_NARROW;
657 else
658 if (sc->range)
659 cfg |= GSC_IN_RGB_SD_WIDE;
660 else
661 cfg |= GSC_IN_RGB_SD_NARROW;
662
663 gsc_write(cfg, GSC_IN_CON);
664
665 return 0;
666 }
667
668 static int gsc_src_set_buf_seq(struct gsc_context *ctx, u32 buf_id,
669 enum drm_exynos_ipp_buf_type buf_type)
670 {
671 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
672 bool masked;
673 u32 cfg;
674 u32 mask = 0x00000001 << buf_id;
675
676 DRM_DEBUG_KMS("%s:buf_id[%d]buf_type[%d]\n", __func__,
677 buf_id, buf_type);
678
679 /* mask register set */
680 cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK);
681
682 switch (buf_type) {
683 case IPP_BUF_ENQUEUE:
684 masked = false;
685 break;
686 case IPP_BUF_DEQUEUE:
687 masked = true;
688 break;
689 default:
690 dev_err(ippdrv->dev, "invalid buf ctrl parameter.\n");
691 return -EINVAL;
692 }
693
694 /* sequence id */
695 cfg &= ~mask;
696 cfg |= masked << buf_id;
697 gsc_write(cfg, GSC_IN_BASE_ADDR_Y_MASK);
698 gsc_write(cfg, GSC_IN_BASE_ADDR_CB_MASK);
699 gsc_write(cfg, GSC_IN_BASE_ADDR_CR_MASK);
700
701 return 0;
702 }
703
704 static int gsc_src_set_addr(struct device *dev,
705 struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id,
706 enum drm_exynos_ipp_buf_type buf_type)
707 {
708 struct gsc_context *ctx = get_gsc_context(dev);
709 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
710 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
711 struct drm_exynos_ipp_property *property;
712
713 if (!c_node) {
714 DRM_ERROR("failed to get c_node.\n");
715 return -EFAULT;
716 }
717
718 property = &c_node->property;
719
720 DRM_DEBUG_KMS("%s:prop_id[%d]buf_id[%d]buf_type[%d]\n", __func__,
721 property->prop_id, buf_id, buf_type);
722
723 if (buf_id > GSC_MAX_SRC) {
724 dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id);
725 return -EINVAL;
726 }
727
728 /* address register set */
729 switch (buf_type) {
730 case IPP_BUF_ENQUEUE:
731 gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_Y],
732 GSC_IN_BASE_ADDR_Y(buf_id));
733 gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB],
734 GSC_IN_BASE_ADDR_CB(buf_id));
735 gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR],
736 GSC_IN_BASE_ADDR_CR(buf_id));
737 break;
738 case IPP_BUF_DEQUEUE:
739 gsc_write(0x0, GSC_IN_BASE_ADDR_Y(buf_id));
740 gsc_write(0x0, GSC_IN_BASE_ADDR_CB(buf_id));
741 gsc_write(0x0, GSC_IN_BASE_ADDR_CR(buf_id));
742 break;
743 default:
744 /* bypass */
745 break;
746 }
747
748 return gsc_src_set_buf_seq(ctx, buf_id, buf_type);
749 }
750
751 static struct exynos_drm_ipp_ops gsc_src_ops = {
752 .set_fmt = gsc_src_set_fmt,
753 .set_transf = gsc_src_set_transf,
754 .set_size = gsc_src_set_size,
755 .set_addr = gsc_src_set_addr,
756 };
757
758 static int gsc_dst_set_fmt(struct device *dev, u32 fmt)
759 {
760 struct gsc_context *ctx = get_gsc_context(dev);
761 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
762 u32 cfg;
763
764 DRM_DEBUG_KMS("%s:fmt[0x%x]\n", __func__, fmt);
765
766 cfg = gsc_read(GSC_OUT_CON);
767 cfg &= ~(GSC_OUT_RGB_TYPE_MASK | GSC_OUT_YUV422_1P_ORDER_MASK |
768 GSC_OUT_CHROMA_ORDER_MASK | GSC_OUT_FORMAT_MASK |
769 GSC_OUT_CHROM_STRIDE_SEL_MASK | GSC_OUT_RB_SWAP_MASK |
770 GSC_OUT_GLOBAL_ALPHA_MASK);
771
772 switch (fmt) {
773 case DRM_FORMAT_RGB565:
774 cfg |= GSC_OUT_RGB565;
775 break;
776 case DRM_FORMAT_XRGB8888:
777 cfg |= GSC_OUT_XRGB8888;
778 break;
779 case DRM_FORMAT_BGRX8888:
780 cfg |= (GSC_OUT_XRGB8888 | GSC_OUT_RB_SWAP);
781 break;
782 case DRM_FORMAT_YUYV:
783 cfg |= (GSC_OUT_YUV422_1P |
784 GSC_OUT_YUV422_1P_ORDER_LSB_Y |
785 GSC_OUT_CHROMA_ORDER_CBCR);
786 break;
787 case DRM_FORMAT_YVYU:
788 cfg |= (GSC_OUT_YUV422_1P |
789 GSC_OUT_YUV422_1P_ORDER_LSB_Y |
790 GSC_OUT_CHROMA_ORDER_CRCB);
791 break;
792 case DRM_FORMAT_UYVY:
793 cfg |= (GSC_OUT_YUV422_1P |
794 GSC_OUT_YUV422_1P_OEDER_LSB_C |
795 GSC_OUT_CHROMA_ORDER_CBCR);
796 break;
797 case DRM_FORMAT_VYUY:
798 cfg |= (GSC_OUT_YUV422_1P |
799 GSC_OUT_YUV422_1P_OEDER_LSB_C |
800 GSC_OUT_CHROMA_ORDER_CRCB);
801 break;
802 case DRM_FORMAT_NV21:
803 case DRM_FORMAT_NV61:
804 cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV420_2P);
805 break;
806 case DRM_FORMAT_YUV422:
807 case DRM_FORMAT_YUV420:
808 case DRM_FORMAT_YVU420:
809 cfg |= GSC_OUT_YUV420_3P;
810 break;
811 case DRM_FORMAT_NV12:
812 case DRM_FORMAT_NV16:
813 cfg |= (GSC_OUT_CHROMA_ORDER_CBCR |
814 GSC_OUT_YUV420_2P);
815 break;
816 case DRM_FORMAT_NV12MT:
817 cfg |= (GSC_OUT_TILE_C_16x8 | GSC_OUT_TILE_MODE);
818 break;
819 default:
820 dev_err(ippdrv->dev, "inavlid target yuv order 0x%x.\n", fmt);
821 return -EINVAL;
822 }
823
824 gsc_write(cfg, GSC_OUT_CON);
825
826 return 0;
827 }
828
829 static int gsc_dst_set_transf(struct device *dev,
830 enum drm_exynos_degree degree,
831 enum drm_exynos_flip flip, bool *swap)
832 {
833 struct gsc_context *ctx = get_gsc_context(dev);
834 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
835 u32 cfg;
836
837 DRM_DEBUG_KMS("%s:degree[%d]flip[0x%x]\n", __func__,
838 degree, flip);
839
840 cfg = gsc_read(GSC_IN_CON);
841 cfg &= ~GSC_IN_ROT_MASK;
842
843 switch (degree) {
844 case EXYNOS_DRM_DEGREE_0:
845 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
846 cfg |= GSC_IN_ROT_XFLIP;
847 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
848 cfg |= GSC_IN_ROT_YFLIP;
849 break;
850 case EXYNOS_DRM_DEGREE_90:
851 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
852 cfg |= GSC_IN_ROT_90_XFLIP;
853 else if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
854 cfg |= GSC_IN_ROT_90_YFLIP;
855 else
856 cfg |= GSC_IN_ROT_90;
857 break;
858 case EXYNOS_DRM_DEGREE_180:
859 cfg |= GSC_IN_ROT_180;
860 break;
861 case EXYNOS_DRM_DEGREE_270:
862 cfg |= GSC_IN_ROT_270;
863 break;
864 default:
865 dev_err(ippdrv->dev, "inavlid degree value %d.\n", degree);
866 return -EINVAL;
867 }
868
869 gsc_write(cfg, GSC_IN_CON);
870
871 ctx->rotation = cfg &
872 (GSC_IN_ROT_90 | GSC_IN_ROT_270) ? 1 : 0;
873 *swap = ctx->rotation;
874
875 return 0;
876 }
877
878 static int gsc_get_ratio_shift(u32 src, u32 dst, u32 *ratio)
879 {
880 DRM_DEBUG_KMS("%s:src[%d]dst[%d]\n", __func__, src, dst);
881
882 if (src >= dst * 8) {
883 DRM_ERROR("failed to make ratio and shift.\n");
884 return -EINVAL;
885 } else if (src >= dst * 4)
886 *ratio = 4;
887 else if (src >= dst * 2)
888 *ratio = 2;
889 else
890 *ratio = 1;
891
892 return 0;
893 }
894
895 static void gsc_get_prescaler_shfactor(u32 hratio, u32 vratio, u32 *shfactor)
896 {
897 if (hratio == 4 && vratio == 4)
898 *shfactor = 4;
899 else if ((hratio == 4 && vratio == 2) ||
900 (hratio == 2 && vratio == 4))
901 *shfactor = 3;
902 else if ((hratio == 4 && vratio == 1) ||
903 (hratio == 1 && vratio == 4) ||
904 (hratio == 2 && vratio == 2))
905 *shfactor = 2;
906 else if (hratio == 1 && vratio == 1)
907 *shfactor = 0;
908 else
909 *shfactor = 1;
910 }
911
912 static int gsc_set_prescaler(struct gsc_context *ctx, struct gsc_scaler *sc,
913 struct drm_exynos_pos *src, struct drm_exynos_pos *dst)
914 {
915 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
916 u32 cfg;
917 u32 src_w, src_h, dst_w, dst_h;
918 int ret = 0;
919
920 src_w = src->w;
921 src_h = src->h;
922
923 if (ctx->rotation) {
924 dst_w = dst->h;
925 dst_h = dst->w;
926 } else {
927 dst_w = dst->w;
928 dst_h = dst->h;
929 }
930
931 ret = gsc_get_ratio_shift(src_w, dst_w, &sc->pre_hratio);
932 if (ret) {
933 dev_err(ippdrv->dev, "failed to get ratio horizontal.\n");
934 return ret;
935 }
936
937 ret = gsc_get_ratio_shift(src_h, dst_h, &sc->pre_vratio);
938 if (ret) {
939 dev_err(ippdrv->dev, "failed to get ratio vertical.\n");
940 return ret;
941 }
942
943 DRM_DEBUG_KMS("%s:pre_hratio[%d]pre_vratio[%d]\n",
944 __func__, sc->pre_hratio, sc->pre_vratio);
945
946 sc->main_hratio = (src_w << 16) / dst_w;
947 sc->main_vratio = (src_h << 16) / dst_h;
948
949 DRM_DEBUG_KMS("%s:main_hratio[%ld]main_vratio[%ld]\n",
950 __func__, sc->main_hratio, sc->main_vratio);
951
952 gsc_get_prescaler_shfactor(sc->pre_hratio, sc->pre_vratio,
953 &sc->pre_shfactor);
954
955 DRM_DEBUG_KMS("%s:pre_shfactor[%d]\n", __func__,
956 sc->pre_shfactor);
957
958 cfg = (GSC_PRESC_SHFACTOR(sc->pre_shfactor) |
959 GSC_PRESC_H_RATIO(sc->pre_hratio) |
960 GSC_PRESC_V_RATIO(sc->pre_vratio));
961 gsc_write(cfg, GSC_PRE_SCALE_RATIO);
962
963 return ret;
964 }
965
966 static void gsc_set_h_coef(struct gsc_context *ctx, unsigned long main_hratio)
967 {
968 int i, j, k, sc_ratio;
969
970 if (main_hratio <= GSC_SC_UP_MAX_RATIO)
971 sc_ratio = 0;
972 else if (main_hratio <= GSC_SC_DOWN_RATIO_7_8)
973 sc_ratio = 1;
974 else if (main_hratio <= GSC_SC_DOWN_RATIO_6_8)
975 sc_ratio = 2;
976 else if (main_hratio <= GSC_SC_DOWN_RATIO_5_8)
977 sc_ratio = 3;
978 else if (main_hratio <= GSC_SC_DOWN_RATIO_4_8)
979 sc_ratio = 4;
980 else if (main_hratio <= GSC_SC_DOWN_RATIO_3_8)
981 sc_ratio = 5;
982 else
983 sc_ratio = 6;
984
985 for (i = 0; i < GSC_COEF_PHASE; i++)
986 for (j = 0; j < GSC_COEF_H_8T; j++)
987 for (k = 0; k < GSC_COEF_DEPTH; k++)
988 gsc_write(h_coef_8t[sc_ratio][i][j],
989 GSC_HCOEF(i, j, k));
990 }
991
992 static void gsc_set_v_coef(struct gsc_context *ctx, unsigned long main_vratio)
993 {
994 int i, j, k, sc_ratio;
995
996 if (main_vratio <= GSC_SC_UP_MAX_RATIO)
997 sc_ratio = 0;
998 else if (main_vratio <= GSC_SC_DOWN_RATIO_7_8)
999 sc_ratio = 1;
1000 else if (main_vratio <= GSC_SC_DOWN_RATIO_6_8)
1001 sc_ratio = 2;
1002 else if (main_vratio <= GSC_SC_DOWN_RATIO_5_8)
1003 sc_ratio = 3;
1004 else if (main_vratio <= GSC_SC_DOWN_RATIO_4_8)
1005 sc_ratio = 4;
1006 else if (main_vratio <= GSC_SC_DOWN_RATIO_3_8)
1007 sc_ratio = 5;
1008 else
1009 sc_ratio = 6;
1010
1011 for (i = 0; i < GSC_COEF_PHASE; i++)
1012 for (j = 0; j < GSC_COEF_V_4T; j++)
1013 for (k = 0; k < GSC_COEF_DEPTH; k++)
1014 gsc_write(v_coef_4t[sc_ratio][i][j],
1015 GSC_VCOEF(i, j, k));
1016 }
1017
1018 static void gsc_set_scaler(struct gsc_context *ctx, struct gsc_scaler *sc)
1019 {
1020 u32 cfg;
1021
1022 DRM_DEBUG_KMS("%s:main_hratio[%ld]main_vratio[%ld]\n",
1023 __func__, sc->main_hratio, sc->main_vratio);
1024
1025 gsc_set_h_coef(ctx, sc->main_hratio);
1026 cfg = GSC_MAIN_H_RATIO_VALUE(sc->main_hratio);
1027 gsc_write(cfg, GSC_MAIN_H_RATIO);
1028
1029 gsc_set_v_coef(ctx, sc->main_vratio);
1030 cfg = GSC_MAIN_V_RATIO_VALUE(sc->main_vratio);
1031 gsc_write(cfg, GSC_MAIN_V_RATIO);
1032 }
1033
1034 static int gsc_dst_set_size(struct device *dev, int swap,
1035 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz)
1036 {
1037 struct gsc_context *ctx = get_gsc_context(dev);
1038 struct drm_exynos_pos img_pos = *pos;
1039 struct gsc_scaler *sc = &ctx->sc;
1040 u32 cfg;
1041
1042 DRM_DEBUG_KMS("%s:swap[%d]x[%d]y[%d]w[%d]h[%d]\n",
1043 __func__, swap, pos->x, pos->y, pos->w, pos->h);
1044
1045 if (swap) {
1046 img_pos.w = pos->h;
1047 img_pos.h = pos->w;
1048 }
1049
1050 /* pixel offset */
1051 cfg = (GSC_DSTIMG_OFFSET_X(pos->x) |
1052 GSC_DSTIMG_OFFSET_Y(pos->y));
1053 gsc_write(cfg, GSC_DSTIMG_OFFSET);
1054
1055 /* scaled size */
1056 cfg = (GSC_SCALED_WIDTH(img_pos.w) | GSC_SCALED_HEIGHT(img_pos.h));
1057 gsc_write(cfg, GSC_SCALED_SIZE);
1058
1059 DRM_DEBUG_KMS("%s:hsize[%d]vsize[%d]\n",
1060 __func__, sz->hsize, sz->vsize);
1061
1062 /* original size */
1063 cfg = gsc_read(GSC_DSTIMG_SIZE);
1064 cfg &= ~(GSC_DSTIMG_HEIGHT_MASK |
1065 GSC_DSTIMG_WIDTH_MASK);
1066 cfg |= (GSC_DSTIMG_WIDTH(sz->hsize) |
1067 GSC_DSTIMG_HEIGHT(sz->vsize));
1068 gsc_write(cfg, GSC_DSTIMG_SIZE);
1069
1070 cfg = gsc_read(GSC_OUT_CON);
1071 cfg &= ~GSC_OUT_RGB_TYPE_MASK;
1072
1073 DRM_DEBUG_KMS("%s:width[%d]range[%d]\n",
1074 __func__, pos->w, sc->range);
1075
1076 if (pos->w >= GSC_WIDTH_ITU_709)
1077 if (sc->range)
1078 cfg |= GSC_OUT_RGB_HD_WIDE;
1079 else
1080 cfg |= GSC_OUT_RGB_HD_NARROW;
1081 else
1082 if (sc->range)
1083 cfg |= GSC_OUT_RGB_SD_WIDE;
1084 else
1085 cfg |= GSC_OUT_RGB_SD_NARROW;
1086
1087 gsc_write(cfg, GSC_OUT_CON);
1088
1089 return 0;
1090 }
1091
1092 static int gsc_dst_get_buf_seq(struct gsc_context *ctx)
1093 {
1094 u32 cfg, i, buf_num = GSC_REG_SZ;
1095 u32 mask = 0x00000001;
1096
1097 cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
1098
1099 for (i = 0; i < GSC_REG_SZ; i++)
1100 if (cfg & (mask << i))
1101 buf_num--;
1102
1103 DRM_DEBUG_KMS("%s:buf_num[%d]\n", __func__, buf_num);
1104
1105 return buf_num;
1106 }
1107
1108 static int gsc_dst_set_buf_seq(struct gsc_context *ctx, u32 buf_id,
1109 enum drm_exynos_ipp_buf_type buf_type)
1110 {
1111 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1112 bool masked;
1113 u32 cfg;
1114 u32 mask = 0x00000001 << buf_id;
1115 int ret = 0;
1116
1117 DRM_DEBUG_KMS("%s:buf_id[%d]buf_type[%d]\n", __func__,
1118 buf_id, buf_type);
1119
1120 mutex_lock(&ctx->lock);
1121
1122 /* mask register set */
1123 cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
1124
1125 switch (buf_type) {
1126 case IPP_BUF_ENQUEUE:
1127 masked = false;
1128 break;
1129 case IPP_BUF_DEQUEUE:
1130 masked = true;
1131 break;
1132 default:
1133 dev_err(ippdrv->dev, "invalid buf ctrl parameter.\n");
1134 ret = -EINVAL;
1135 goto err_unlock;
1136 }
1137
1138 /* sequence id */
1139 cfg &= ~mask;
1140 cfg |= masked << buf_id;
1141 gsc_write(cfg, GSC_OUT_BASE_ADDR_Y_MASK);
1142 gsc_write(cfg, GSC_OUT_BASE_ADDR_CB_MASK);
1143 gsc_write(cfg, GSC_OUT_BASE_ADDR_CR_MASK);
1144
1145 /* interrupt enable */
1146 if (buf_type == IPP_BUF_ENQUEUE &&
1147 gsc_dst_get_buf_seq(ctx) >= GSC_BUF_START)
1148 gsc_handle_irq(ctx, true, false, true);
1149
1150 /* interrupt disable */
1151 if (buf_type == IPP_BUF_DEQUEUE &&
1152 gsc_dst_get_buf_seq(ctx) <= GSC_BUF_STOP)
1153 gsc_handle_irq(ctx, false, false, true);
1154
1155 err_unlock:
1156 mutex_unlock(&ctx->lock);
1157 return ret;
1158 }
1159
1160 static int gsc_dst_set_addr(struct device *dev,
1161 struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id,
1162 enum drm_exynos_ipp_buf_type buf_type)
1163 {
1164 struct gsc_context *ctx = get_gsc_context(dev);
1165 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1166 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1167 struct drm_exynos_ipp_property *property;
1168
1169 if (!c_node) {
1170 DRM_ERROR("failed to get c_node.\n");
1171 return -EFAULT;
1172 }
1173
1174 property = &c_node->property;
1175
1176 DRM_DEBUG_KMS("%s:prop_id[%d]buf_id[%d]buf_type[%d]\n", __func__,
1177 property->prop_id, buf_id, buf_type);
1178
1179 if (buf_id > GSC_MAX_DST) {
1180 dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id);
1181 return -EINVAL;
1182 }
1183
1184 /* address register set */
1185 switch (buf_type) {
1186 case IPP_BUF_ENQUEUE:
1187 gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_Y],
1188 GSC_OUT_BASE_ADDR_Y(buf_id));
1189 gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB],
1190 GSC_OUT_BASE_ADDR_CB(buf_id));
1191 gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR],
1192 GSC_OUT_BASE_ADDR_CR(buf_id));
1193 break;
1194 case IPP_BUF_DEQUEUE:
1195 gsc_write(0x0, GSC_OUT_BASE_ADDR_Y(buf_id));
1196 gsc_write(0x0, GSC_OUT_BASE_ADDR_CB(buf_id));
1197 gsc_write(0x0, GSC_OUT_BASE_ADDR_CR(buf_id));
1198 break;
1199 default:
1200 /* bypass */
1201 break;
1202 }
1203
1204 return gsc_dst_set_buf_seq(ctx, buf_id, buf_type);
1205 }
1206
1207 static struct exynos_drm_ipp_ops gsc_dst_ops = {
1208 .set_fmt = gsc_dst_set_fmt,
1209 .set_transf = gsc_dst_set_transf,
1210 .set_size = gsc_dst_set_size,
1211 .set_addr = gsc_dst_set_addr,
1212 };
1213
1214 static int gsc_clk_ctrl(struct gsc_context *ctx, bool enable)
1215 {
1216 DRM_DEBUG_KMS("%s:enable[%d]\n", __func__, enable);
1217
1218 if (enable) {
1219 clk_enable(ctx->gsc_clk);
1220 ctx->suspended = false;
1221 } else {
1222 clk_disable(ctx->gsc_clk);
1223 ctx->suspended = true;
1224 }
1225
1226 return 0;
1227 }
1228
1229 static int gsc_get_src_buf_index(struct gsc_context *ctx)
1230 {
1231 u32 cfg, curr_index, i;
1232 u32 buf_id = GSC_MAX_SRC;
1233 int ret;
1234
1235 DRM_DEBUG_KMS("%s:gsc id[%d]\n", __func__, ctx->id);
1236
1237 cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK);
1238 curr_index = GSC_IN_CURR_GET_INDEX(cfg);
1239
1240 for (i = curr_index; i < GSC_MAX_SRC; i++) {
1241 if (!((cfg >> i) & 0x1)) {
1242 buf_id = i;
1243 break;
1244 }
1245 }
1246
1247 if (buf_id == GSC_MAX_SRC) {
1248 DRM_ERROR("failed to get in buffer index.\n");
1249 return -EINVAL;
1250 }
1251
1252 ret = gsc_src_set_buf_seq(ctx, buf_id, IPP_BUF_DEQUEUE);
1253 if (ret < 0) {
1254 DRM_ERROR("failed to dequeue.\n");
1255 return ret;
1256 }
1257
1258 DRM_DEBUG_KMS("%s:cfg[0x%x]curr_index[%d]buf_id[%d]\n", __func__, cfg,
1259 curr_index, buf_id);
1260
1261 return buf_id;
1262 }
1263
1264 static int gsc_get_dst_buf_index(struct gsc_context *ctx)
1265 {
1266 u32 cfg, curr_index, i;
1267 u32 buf_id = GSC_MAX_DST;
1268 int ret;
1269
1270 DRM_DEBUG_KMS("%s:gsc id[%d]\n", __func__, ctx->id);
1271
1272 cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
1273 curr_index = GSC_OUT_CURR_GET_INDEX(cfg);
1274
1275 for (i = curr_index; i < GSC_MAX_DST; i++) {
1276 if (!((cfg >> i) & 0x1)) {
1277 buf_id = i;
1278 break;
1279 }
1280 }
1281
1282 if (buf_id == GSC_MAX_DST) {
1283 DRM_ERROR("failed to get out buffer index.\n");
1284 return -EINVAL;
1285 }
1286
1287 ret = gsc_dst_set_buf_seq(ctx, buf_id, IPP_BUF_DEQUEUE);
1288 if (ret < 0) {
1289 DRM_ERROR("failed to dequeue.\n");
1290 return ret;
1291 }
1292
1293 DRM_DEBUG_KMS("%s:cfg[0x%x]curr_index[%d]buf_id[%d]\n", __func__, cfg,
1294 curr_index, buf_id);
1295
1296 return buf_id;
1297 }
1298
1299 static irqreturn_t gsc_irq_handler(int irq, void *dev_id)
1300 {
1301 struct gsc_context *ctx = dev_id;
1302 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1303 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1304 struct drm_exynos_ipp_event_work *event_work =
1305 c_node->event_work;
1306 u32 status;
1307 int buf_id[EXYNOS_DRM_OPS_MAX];
1308
1309 DRM_DEBUG_KMS("%s:gsc id[%d]\n", __func__, ctx->id);
1310
1311 status = gsc_read(GSC_IRQ);
1312 if (status & GSC_IRQ_STATUS_OR_IRQ) {
1313 dev_err(ippdrv->dev, "occured overflow at %d, status 0x%x.\n",
1314 ctx->id, status);
1315 return IRQ_NONE;
1316 }
1317
1318 if (status & GSC_IRQ_STATUS_OR_FRM_DONE) {
1319 dev_dbg(ippdrv->dev, "occured frame done at %d, status 0x%x.\n",
1320 ctx->id, status);
1321
1322 buf_id[EXYNOS_DRM_OPS_SRC] = gsc_get_src_buf_index(ctx);
1323 if (buf_id[EXYNOS_DRM_OPS_SRC] < 0)
1324 return IRQ_HANDLED;
1325
1326 buf_id[EXYNOS_DRM_OPS_DST] = gsc_get_dst_buf_index(ctx);
1327 if (buf_id[EXYNOS_DRM_OPS_DST] < 0)
1328 return IRQ_HANDLED;
1329
1330 DRM_DEBUG_KMS("%s:buf_id_src[%d]buf_id_dst[%d]\n", __func__,
1331 buf_id[EXYNOS_DRM_OPS_SRC], buf_id[EXYNOS_DRM_OPS_DST]);
1332
1333 event_work->ippdrv = ippdrv;
1334 event_work->buf_id[EXYNOS_DRM_OPS_SRC] =
1335 buf_id[EXYNOS_DRM_OPS_SRC];
1336 event_work->buf_id[EXYNOS_DRM_OPS_DST] =
1337 buf_id[EXYNOS_DRM_OPS_DST];
1338 queue_work(ippdrv->event_workq,
1339 (struct work_struct *)event_work);
1340 }
1341
1342 return IRQ_HANDLED;
1343 }
1344
1345 static int gsc_init_prop_list(struct exynos_drm_ippdrv *ippdrv)
1346 {
1347 struct drm_exynos_ipp_prop_list *prop_list;
1348
1349 prop_list = devm_kzalloc(ippdrv->dev, sizeof(*prop_list), GFP_KERNEL);
1350 if (!prop_list) {
1351 DRM_ERROR("failed to alloc property list.\n");
1352 return -ENOMEM;
1353 }
1354
1355 prop_list->version = 1;
1356 prop_list->writeback = 1;
1357 prop_list->refresh_min = GSC_REFRESH_MIN;
1358 prop_list->refresh_max = GSC_REFRESH_MAX;
1359 prop_list->flip = (1 << EXYNOS_DRM_FLIP_VERTICAL) |
1360 (1 << EXYNOS_DRM_FLIP_HORIZONTAL);
1361 prop_list->degree = (1 << EXYNOS_DRM_DEGREE_0) |
1362 (1 << EXYNOS_DRM_DEGREE_90) |
1363 (1 << EXYNOS_DRM_DEGREE_180) |
1364 (1 << EXYNOS_DRM_DEGREE_270);
1365 prop_list->csc = 1;
1366 prop_list->crop = 1;
1367 prop_list->crop_max.hsize = GSC_CROP_MAX;
1368 prop_list->crop_max.vsize = GSC_CROP_MAX;
1369 prop_list->crop_min.hsize = GSC_CROP_MIN;
1370 prop_list->crop_min.vsize = GSC_CROP_MIN;
1371 prop_list->scale = 1;
1372 prop_list->scale_max.hsize = GSC_SCALE_MAX;
1373 prop_list->scale_max.vsize = GSC_SCALE_MAX;
1374 prop_list->scale_min.hsize = GSC_SCALE_MIN;
1375 prop_list->scale_min.vsize = GSC_SCALE_MIN;
1376
1377 ippdrv->prop_list = prop_list;
1378
1379 return 0;
1380 }
1381
1382 static inline bool gsc_check_drm_flip(enum drm_exynos_flip flip)
1383 {
1384 switch (flip) {
1385 case EXYNOS_DRM_FLIP_NONE:
1386 case EXYNOS_DRM_FLIP_VERTICAL:
1387 case EXYNOS_DRM_FLIP_HORIZONTAL:
1388 case EXYNOS_DRM_FLIP_BOTH:
1389 return true;
1390 default:
1391 DRM_DEBUG_KMS("%s:invalid flip\n", __func__);
1392 return false;
1393 }
1394 }
1395
1396 static int gsc_ippdrv_check_property(struct device *dev,
1397 struct drm_exynos_ipp_property *property)
1398 {
1399 struct gsc_context *ctx = get_gsc_context(dev);
1400 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1401 struct drm_exynos_ipp_prop_list *pp = ippdrv->prop_list;
1402 struct drm_exynos_ipp_config *config;
1403 struct drm_exynos_pos *pos;
1404 struct drm_exynos_sz *sz;
1405 bool swap;
1406 int i;
1407
1408 for_each_ipp_ops(i) {
1409 if ((i == EXYNOS_DRM_OPS_SRC) &&
1410 (property->cmd == IPP_CMD_WB))
1411 continue;
1412
1413 config = &property->config[i];
1414 pos = &config->pos;
1415 sz = &config->sz;
1416
1417 /* check for flip */
1418 if (!gsc_check_drm_flip(config->flip)) {
1419 DRM_ERROR("invalid flip.\n");
1420 goto err_property;
1421 }
1422
1423 /* check for degree */
1424 switch (config->degree) {
1425 case EXYNOS_DRM_DEGREE_90:
1426 case EXYNOS_DRM_DEGREE_270:
1427 swap = true;
1428 break;
1429 case EXYNOS_DRM_DEGREE_0:
1430 case EXYNOS_DRM_DEGREE_180:
1431 swap = false;
1432 break;
1433 default:
1434 DRM_ERROR("invalid degree.\n");
1435 goto err_property;
1436 }
1437
1438 /* check for buffer bound */
1439 if ((pos->x + pos->w > sz->hsize) ||
1440 (pos->y + pos->h > sz->vsize)) {
1441 DRM_ERROR("out of buf bound.\n");
1442 goto err_property;
1443 }
1444
1445 /* check for crop */
1446 if ((i == EXYNOS_DRM_OPS_SRC) && (pp->crop)) {
1447 if (swap) {
1448 if ((pos->h < pp->crop_min.hsize) ||
1449 (sz->vsize > pp->crop_max.hsize) ||
1450 (pos->w < pp->crop_min.vsize) ||
1451 (sz->hsize > pp->crop_max.vsize)) {
1452 DRM_ERROR("out of crop size.\n");
1453 goto err_property;
1454 }
1455 } else {
1456 if ((pos->w < pp->crop_min.hsize) ||
1457 (sz->hsize > pp->crop_max.hsize) ||
1458 (pos->h < pp->crop_min.vsize) ||
1459 (sz->vsize > pp->crop_max.vsize)) {
1460 DRM_ERROR("out of crop size.\n");
1461 goto err_property;
1462 }
1463 }
1464 }
1465
1466 /* check for scale */
1467 if ((i == EXYNOS_DRM_OPS_DST) && (pp->scale)) {
1468 if (swap) {
1469 if ((pos->h < pp->scale_min.hsize) ||
1470 (sz->vsize > pp->scale_max.hsize) ||
1471 (pos->w < pp->scale_min.vsize) ||
1472 (sz->hsize > pp->scale_max.vsize)) {
1473 DRM_ERROR("out of scale size.\n");
1474 goto err_property;
1475 }
1476 } else {
1477 if ((pos->w < pp->scale_min.hsize) ||
1478 (sz->hsize > pp->scale_max.hsize) ||
1479 (pos->h < pp->scale_min.vsize) ||
1480 (sz->vsize > pp->scale_max.vsize)) {
1481 DRM_ERROR("out of scale size.\n");
1482 goto err_property;
1483 }
1484 }
1485 }
1486 }
1487
1488 return 0;
1489
1490 err_property:
1491 for_each_ipp_ops(i) {
1492 if ((i == EXYNOS_DRM_OPS_SRC) &&
1493 (property->cmd == IPP_CMD_WB))
1494 continue;
1495
1496 config = &property->config[i];
1497 pos = &config->pos;
1498 sz = &config->sz;
1499
1500 DRM_ERROR("[%s]f[%d]r[%d]pos[%d %d %d %d]sz[%d %d]\n",
1501 i ? "dst" : "src", config->flip, config->degree,
1502 pos->x, pos->y, pos->w, pos->h,
1503 sz->hsize, sz->vsize);
1504 }
1505
1506 return -EINVAL;
1507 }
1508
1509
1510 static int gsc_ippdrv_reset(struct device *dev)
1511 {
1512 struct gsc_context *ctx = get_gsc_context(dev);
1513 struct gsc_scaler *sc = &ctx->sc;
1514 int ret;
1515
1516 /* reset h/w block */
1517 ret = gsc_sw_reset(ctx);
1518 if (ret < 0) {
1519 dev_err(dev, "failed to reset hardware.\n");
1520 return ret;
1521 }
1522
1523 /* scaler setting */
1524 memset(&ctx->sc, 0x0, sizeof(ctx->sc));
1525 sc->range = true;
1526
1527 return 0;
1528 }
1529
1530 static int gsc_ippdrv_start(struct device *dev, enum drm_exynos_ipp_cmd cmd)
1531 {
1532 struct gsc_context *ctx = get_gsc_context(dev);
1533 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1534 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1535 struct drm_exynos_ipp_property *property;
1536 struct drm_exynos_ipp_config *config;
1537 struct drm_exynos_pos img_pos[EXYNOS_DRM_OPS_MAX];
1538 struct drm_exynos_ipp_set_wb set_wb;
1539 u32 cfg;
1540 int ret, i;
1541
1542 DRM_DEBUG_KMS("%s:cmd[%d]\n", __func__, cmd);
1543
1544 if (!c_node) {
1545 DRM_ERROR("failed to get c_node.\n");
1546 return -EINVAL;
1547 }
1548
1549 property = &c_node->property;
1550
1551 gsc_handle_irq(ctx, true, false, true);
1552
1553 for_each_ipp_ops(i) {
1554 config = &property->config[i];
1555 img_pos[i] = config->pos;
1556 }
1557
1558 switch (cmd) {
1559 case IPP_CMD_M2M:
1560 /* enable one shot */
1561 cfg = gsc_read(GSC_ENABLE);
1562 cfg &= ~(GSC_ENABLE_ON_CLEAR_MASK |
1563 GSC_ENABLE_CLK_GATE_MODE_MASK);
1564 cfg |= GSC_ENABLE_ON_CLEAR_ONESHOT;
1565 gsc_write(cfg, GSC_ENABLE);
1566
1567 /* src dma memory */
1568 cfg = gsc_read(GSC_IN_CON);
1569 cfg &= ~(GSC_IN_PATH_MASK | GSC_IN_LOCAL_SEL_MASK);
1570 cfg |= GSC_IN_PATH_MEMORY;
1571 gsc_write(cfg, GSC_IN_CON);
1572
1573 /* dst dma memory */
1574 cfg = gsc_read(GSC_OUT_CON);
1575 cfg |= GSC_OUT_PATH_MEMORY;
1576 gsc_write(cfg, GSC_OUT_CON);
1577 break;
1578 case IPP_CMD_WB:
1579 set_wb.enable = 1;
1580 set_wb.refresh = property->refresh_rate;
1581 gsc_set_gscblk_fimd_wb(ctx, set_wb.enable);
1582 exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb);
1583
1584 /* src local path */
1585 cfg = gsc_read(GSC_IN_CON);
1586 cfg &= ~(GSC_IN_PATH_MASK | GSC_IN_LOCAL_SEL_MASK);
1587 cfg |= (GSC_IN_PATH_LOCAL | GSC_IN_LOCAL_FIMD_WB);
1588 gsc_write(cfg, GSC_IN_CON);
1589
1590 /* dst dma memory */
1591 cfg = gsc_read(GSC_OUT_CON);
1592 cfg |= GSC_OUT_PATH_MEMORY;
1593 gsc_write(cfg, GSC_OUT_CON);
1594 break;
1595 case IPP_CMD_OUTPUT:
1596 /* src dma memory */
1597 cfg = gsc_read(GSC_IN_CON);
1598 cfg &= ~(GSC_IN_PATH_MASK | GSC_IN_LOCAL_SEL_MASK);
1599 cfg |= GSC_IN_PATH_MEMORY;
1600 gsc_write(cfg, GSC_IN_CON);
1601
1602 /* dst local path */
1603 cfg = gsc_read(GSC_OUT_CON);
1604 cfg |= GSC_OUT_PATH_MEMORY;
1605 gsc_write(cfg, GSC_OUT_CON);
1606 break;
1607 default:
1608 ret = -EINVAL;
1609 dev_err(dev, "invalid operations.\n");
1610 return ret;
1611 }
1612
1613 ret = gsc_set_prescaler(ctx, &ctx->sc,
1614 &img_pos[EXYNOS_DRM_OPS_SRC],
1615 &img_pos[EXYNOS_DRM_OPS_DST]);
1616 if (ret) {
1617 dev_err(dev, "failed to set precalser.\n");
1618 return ret;
1619 }
1620
1621 gsc_set_scaler(ctx, &ctx->sc);
1622
1623 cfg = gsc_read(GSC_ENABLE);
1624 cfg |= GSC_ENABLE_ON;
1625 gsc_write(cfg, GSC_ENABLE);
1626
1627 return 0;
1628 }
1629
1630 static void gsc_ippdrv_stop(struct device *dev, enum drm_exynos_ipp_cmd cmd)
1631 {
1632 struct gsc_context *ctx = get_gsc_context(dev);
1633 struct drm_exynos_ipp_set_wb set_wb = {0, 0};
1634 u32 cfg;
1635
1636 DRM_DEBUG_KMS("%s:cmd[%d]\n", __func__, cmd);
1637
1638 switch (cmd) {
1639 case IPP_CMD_M2M:
1640 /* bypass */
1641 break;
1642 case IPP_CMD_WB:
1643 gsc_set_gscblk_fimd_wb(ctx, set_wb.enable);
1644 exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb);
1645 break;
1646 case IPP_CMD_OUTPUT:
1647 default:
1648 dev_err(dev, "invalid operations.\n");
1649 break;
1650 }
1651
1652 gsc_handle_irq(ctx, false, false, true);
1653
1654 /* reset sequence */
1655 gsc_write(0xff, GSC_OUT_BASE_ADDR_Y_MASK);
1656 gsc_write(0xff, GSC_OUT_BASE_ADDR_CB_MASK);
1657 gsc_write(0xff, GSC_OUT_BASE_ADDR_CR_MASK);
1658
1659 cfg = gsc_read(GSC_ENABLE);
1660 cfg &= ~GSC_ENABLE_ON;
1661 gsc_write(cfg, GSC_ENABLE);
1662 }
1663
1664 static int gsc_probe(struct platform_device *pdev)
1665 {
1666 struct device *dev = &pdev->dev;
1667 struct gsc_context *ctx;
1668 struct resource *res;
1669 struct exynos_drm_ippdrv *ippdrv;
1670 int ret;
1671
1672 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1673 if (!ctx)
1674 return -ENOMEM;
1675
1676 /* clock control */
1677 ctx->gsc_clk = devm_clk_get(dev, "gscl");
1678 if (IS_ERR(ctx->gsc_clk)) {
1679 dev_err(dev, "failed to get gsc clock.\n");
1680 return PTR_ERR(ctx->gsc_clk);
1681 }
1682
1683 /* resource memory */
1684 ctx->regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1685 ctx->regs = devm_ioremap_resource(dev, ctx->regs_res);
1686 if (IS_ERR(ctx->regs))
1687 return PTR_ERR(ctx->regs);
1688
1689 /* resource irq */
1690 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1691 if (!res) {
1692 dev_err(dev, "failed to request irq resource.\n");
1693 return -ENOENT;
1694 }
1695
1696 ctx->irq = res->start;
1697 ret = devm_request_threaded_irq(dev, ctx->irq, NULL, gsc_irq_handler,
1698 IRQF_ONESHOT, "drm_gsc", ctx);
1699 if (ret < 0) {
1700 dev_err(dev, "failed to request irq.\n");
1701 return ret;
1702 }
1703
1704 /* context initailization */
1705 ctx->id = pdev->id;
1706
1707 ippdrv = &ctx->ippdrv;
1708 ippdrv->dev = dev;
1709 ippdrv->ops[EXYNOS_DRM_OPS_SRC] = &gsc_src_ops;
1710 ippdrv->ops[EXYNOS_DRM_OPS_DST] = &gsc_dst_ops;
1711 ippdrv->check_property = gsc_ippdrv_check_property;
1712 ippdrv->reset = gsc_ippdrv_reset;
1713 ippdrv->start = gsc_ippdrv_start;
1714 ippdrv->stop = gsc_ippdrv_stop;
1715 ret = gsc_init_prop_list(ippdrv);
1716 if (ret < 0) {
1717 dev_err(dev, "failed to init property list.\n");
1718 return ret;
1719 }
1720
1721 DRM_DEBUG_KMS("%s:id[%d]ippdrv[0x%x]\n", __func__, ctx->id,
1722 (int)ippdrv);
1723
1724 mutex_init(&ctx->lock);
1725 platform_set_drvdata(pdev, ctx);
1726
1727 pm_runtime_set_active(dev);
1728 pm_runtime_enable(dev);
1729
1730 ret = exynos_drm_ippdrv_register(ippdrv);
1731 if (ret < 0) {
1732 dev_err(dev, "failed to register drm gsc device.\n");
1733 goto err_ippdrv_register;
1734 }
1735
1736 dev_info(dev, "drm gsc registered successfully.\n");
1737
1738 return 0;
1739
1740 err_ippdrv_register:
1741 pm_runtime_disable(dev);
1742 return ret;
1743 }
1744
1745 static int gsc_remove(struct platform_device *pdev)
1746 {
1747 struct device *dev = &pdev->dev;
1748 struct gsc_context *ctx = get_gsc_context(dev);
1749 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1750
1751 exynos_drm_ippdrv_unregister(ippdrv);
1752 mutex_destroy(&ctx->lock);
1753
1754 pm_runtime_set_suspended(dev);
1755 pm_runtime_disable(dev);
1756
1757 return 0;
1758 }
1759
1760 #ifdef CONFIG_PM_SLEEP
1761 static int gsc_suspend(struct device *dev)
1762 {
1763 struct gsc_context *ctx = get_gsc_context(dev);
1764
1765 DRM_DEBUG_KMS("%s:id[%d]\n", __func__, ctx->id);
1766
1767 if (pm_runtime_suspended(dev))
1768 return 0;
1769
1770 return gsc_clk_ctrl(ctx, false);
1771 }
1772
1773 static int gsc_resume(struct device *dev)
1774 {
1775 struct gsc_context *ctx = get_gsc_context(dev);
1776
1777 DRM_DEBUG_KMS("%s:id[%d]\n", __func__, ctx->id);
1778
1779 if (!pm_runtime_suspended(dev))
1780 return gsc_clk_ctrl(ctx, true);
1781
1782 return 0;
1783 }
1784 #endif
1785
1786 #ifdef CONFIG_PM_RUNTIME
1787 static int gsc_runtime_suspend(struct device *dev)
1788 {
1789 struct gsc_context *ctx = get_gsc_context(dev);
1790
1791 DRM_DEBUG_KMS("%s:id[%d]\n", __func__, ctx->id);
1792
1793 return gsc_clk_ctrl(ctx, false);
1794 }
1795
1796 static int gsc_runtime_resume(struct device *dev)
1797 {
1798 struct gsc_context *ctx = get_gsc_context(dev);
1799
1800 DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1801
1802 return gsc_clk_ctrl(ctx, true);
1803 }
1804 #endif
1805
1806 static const struct dev_pm_ops gsc_pm_ops = {
1807 SET_SYSTEM_SLEEP_PM_OPS(gsc_suspend, gsc_resume)
1808 SET_RUNTIME_PM_OPS(gsc_runtime_suspend, gsc_runtime_resume, NULL)
1809 };
1810
1811 struct platform_driver gsc_driver = {
1812 .probe = gsc_probe,
1813 .remove = gsc_remove,
1814 .driver = {
1815 .name = "exynos-drm-gsc",
1816 .owner = THIS_MODULE,
1817 .pm = &gsc_pm_ops,
1818 },
1819 };
1820
Linux kernel - Deliverables
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