drivers/gpu/drm/exynos/regs-hdmi.h

   1 /*
   2  *
   3  *  Cloned from drivers/media/video/s5p-tv/regs-hdmi.h
   4  *
   5  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   6  * http://www.samsung.com/
   7  *
   8  * HDMI register header file for Samsung TVOUT driver
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13 */
  14
  15 #ifndef SAMSUNG_REGS_HDMI_H
  16 #define SAMSUNG_REGS_HDMI_H
  17
  18 /*
  19  * Register part
  20 */
  21
  22 /* HDMI Version 1.3 & Common */
  23 #define HDMI_CTRL_BASE(x)               ((x) + 0x00000000)
  24 #define HDMI_CORE_BASE(x)               ((x) + 0x00010000)
  25 #define HDMI_I2S_BASE(x)                ((x) + 0x00040000)
  26 #define HDMI_TG_BASE(x)                 ((x) + 0x00050000)
  27
  28 /* Control registers */
  29 #define HDMI_INTC_CON                   HDMI_CTRL_BASE(0x0000)
  30 #define HDMI_INTC_FLAG                  HDMI_CTRL_BASE(0x0004)
  31 #define HDMI_HPD_STATUS                 HDMI_CTRL_BASE(0x000C)
  32 #define HDMI_V13_PHY_RSTOUT             HDMI_CTRL_BASE(0x0014)
  33 #define HDMI_V13_PHY_VPLL               HDMI_CTRL_BASE(0x0018)
  34 #define HDMI_V13_PHY_CMU                HDMI_CTRL_BASE(0x001C)
  35 #define HDMI_V13_CORE_RSTOUT            HDMI_CTRL_BASE(0x0020)
  36
  37 /* Core registers */
  38 #define HDMI_CON_0                      HDMI_CORE_BASE(0x0000)
  39 #define HDMI_CON_1                      HDMI_CORE_BASE(0x0004)
  40 #define HDMI_CON_2                      HDMI_CORE_BASE(0x0008)
  41 #define HDMI_SYS_STATUS                 HDMI_CORE_BASE(0x0010)
  42 #define HDMI_V13_PHY_STATUS             HDMI_CORE_BASE(0x0014)
  43 #define HDMI_STATUS_EN                  HDMI_CORE_BASE(0x0020)
  44 #define HDMI_HPD                        HDMI_CORE_BASE(0x0030)
  45 #define HDMI_MODE_SEL                   HDMI_CORE_BASE(0x0040)
  46 #define HDMI_ENC_EN                     HDMI_CORE_BASE(0x0044)
  47 #define HDMI_V13_BLUE_SCREEN_0          HDMI_CORE_BASE(0x0050)
  48 #define HDMI_V13_BLUE_SCREEN_1          HDMI_CORE_BASE(0x0054)
  49 #define HDMI_V13_BLUE_SCREEN_2          HDMI_CORE_BASE(0x0058)
  50 #define HDMI_H_BLANK_0                  HDMI_CORE_BASE(0x00A0)
  51 #define HDMI_H_BLANK_1                  HDMI_CORE_BASE(0x00A4)
  52 #define HDMI_V13_V_BLANK_0              HDMI_CORE_BASE(0x00B0)
  53 #define HDMI_V13_V_BLANK_1              HDMI_CORE_BASE(0x00B4)
  54 #define HDMI_V13_V_BLANK_2              HDMI_CORE_BASE(0x00B8)
  55 #define HDMI_V13_H_V_LINE_0             HDMI_CORE_BASE(0x00C0)
  56 #define HDMI_V13_H_V_LINE_1             HDMI_CORE_BASE(0x00C4)
  57 #define HDMI_V13_H_V_LINE_2             HDMI_CORE_BASE(0x00C8)
  58 #define HDMI_VSYNC_POL                  HDMI_CORE_BASE(0x00E4)
  59 #define HDMI_INT_PRO_MODE               HDMI_CORE_BASE(0x00E8)
  60 #define HDMI_V13_V_BLANK_F_0            HDMI_CORE_BASE(0x0110)
  61 #define HDMI_V13_V_BLANK_F_1            HDMI_CORE_BASE(0x0114)
  62 #define HDMI_V13_V_BLANK_F_2            HDMI_CORE_BASE(0x0118)
  63 #define HDMI_V13_H_SYNC_GEN_0           HDMI_CORE_BASE(0x0120)
  64 #define HDMI_V13_H_SYNC_GEN_1           HDMI_CORE_BASE(0x0124)
  65 #define HDMI_V13_H_SYNC_GEN_2           HDMI_CORE_BASE(0x0128)
  66 #define HDMI_V13_V_SYNC_GEN_1_0         HDMI_CORE_BASE(0x0130)
  67 #define HDMI_V13_V_SYNC_GEN_1_1         HDMI_CORE_BASE(0x0134)
  68 #define HDMI_V13_V_SYNC_GEN_1_2         HDMI_CORE_BASE(0x0138)
  69 #define HDMI_V13_V_SYNC_GEN_2_0         HDMI_CORE_BASE(0x0140)
  70 #define HDMI_V13_V_SYNC_GEN_2_1         HDMI_CORE_BASE(0x0144)
  71 #define HDMI_V13_V_SYNC_GEN_2_2         HDMI_CORE_BASE(0x0148)
  72 #define HDMI_V13_V_SYNC_GEN_3_0         HDMI_CORE_BASE(0x0150)
  73 #define HDMI_V13_V_SYNC_GEN_3_1         HDMI_CORE_BASE(0x0154)
  74 #define HDMI_V13_V_SYNC_GEN_3_2         HDMI_CORE_BASE(0x0158)
  75 #define HDMI_V13_AVI_CON                HDMI_CORE_BASE(0x0300)
  76 #define HDMI_V13_AVI_BYTE(n)            HDMI_CORE_BASE(0x0320 + 4 * (n))
  77 #define HDMI_V13_DC_CONTROL             HDMI_CORE_BASE(0x05C0)
  78 #define HDMI_V13_VIDEO_PATTERN_GEN      HDMI_CORE_BASE(0x05C4)
  79 #define HDMI_V13_HPD_GEN                HDMI_CORE_BASE(0x05C8)
  80 #define HDMI_V13_AUI_CON                HDMI_CORE_BASE(0x0360)
  81 #define HDMI_V13_SPD_CON                HDMI_CORE_BASE(0x0400)
  82
  83 /* Timing generator registers */
  84 #define HDMI_TG_CMD                     HDMI_TG_BASE(0x0000)
  85 #define HDMI_TG_H_FSZ_L                 HDMI_TG_BASE(0x0018)
  86 #define HDMI_TG_H_FSZ_H                 HDMI_TG_BASE(0x001C)
  87 #define HDMI_TG_HACT_ST_L               HDMI_TG_BASE(0x0020)
  88 #define HDMI_TG_HACT_ST_H               HDMI_TG_BASE(0x0024)
  89 #define HDMI_TG_HACT_SZ_L               HDMI_TG_BASE(0x0028)
  90 #define HDMI_TG_HACT_SZ_H               HDMI_TG_BASE(0x002C)
  91 #define HDMI_TG_V_FSZ_L                 HDMI_TG_BASE(0x0030)
  92 #define HDMI_TG_V_FSZ_H                 HDMI_TG_BASE(0x0034)
  93 #define HDMI_TG_VSYNC_L                 HDMI_TG_BASE(0x0038)
  94 #define HDMI_TG_VSYNC_H                 HDMI_TG_BASE(0x003C)
  95 #define HDMI_TG_VSYNC2_L                HDMI_TG_BASE(0x0040)
  96 #define HDMI_TG_VSYNC2_H                HDMI_TG_BASE(0x0044)
  97 #define HDMI_TG_VACT_ST_L               HDMI_TG_BASE(0x0048)
  98 #define HDMI_TG_VACT_ST_H               HDMI_TG_BASE(0x004C)
  99 #define HDMI_TG_VACT_SZ_L               HDMI_TG_BASE(0x0050)
 100 #define HDMI_TG_VACT_SZ_H               HDMI_TG_BASE(0x0054)
 101 #define HDMI_TG_FIELD_CHG_L             HDMI_TG_BASE(0x0058)
 102 #define HDMI_TG_FIELD_CHG_H             HDMI_TG_BASE(0x005C)
 103 #define HDMI_TG_VACT_ST2_L              HDMI_TG_BASE(0x0060)
 104 #define HDMI_TG_VACT_ST2_H              HDMI_TG_BASE(0x0064)
 105 #define HDMI_TG_VSYNC_TOP_HDMI_L        HDMI_TG_BASE(0x0078)
 106 #define HDMI_TG_VSYNC_TOP_HDMI_H        HDMI_TG_BASE(0x007C)
 107 #define HDMI_TG_VSYNC_BOT_HDMI_L        HDMI_TG_BASE(0x0080)
 108 #define HDMI_TG_VSYNC_BOT_HDMI_H        HDMI_TG_BASE(0x0084)
 109 #define HDMI_TG_FIELD_TOP_HDMI_L        HDMI_TG_BASE(0x0088)
 110 #define HDMI_TG_FIELD_TOP_HDMI_H        HDMI_TG_BASE(0x008C)
 111 #define HDMI_TG_FIELD_BOT_HDMI_L        HDMI_TG_BASE(0x0090)
 112 #define HDMI_TG_FIELD_BOT_HDMI_H        HDMI_TG_BASE(0x0094)
 113
 114 /*
 115  * Bit definition part
 116  */
 117
 118 /* HDMI_INTC_CON */
 119 #define HDMI_INTC_EN_GLOBAL             (1 << 6)
 120 #define HDMI_INTC_EN_HPD_PLUG           (1 << 3)
 121 #define HDMI_INTC_EN_HPD_UNPLUG         (1 << 2)
 122
 123 /* HDMI_INTC_FLAG */
 124 #define HDMI_INTC_FLAG_HPD_PLUG         (1 << 3)
 125 #define HDMI_INTC_FLAG_HPD_UNPLUG       (1 << 2)
 126
 127 /* HDMI_PHY_RSTOUT */
 128 #define HDMI_PHY_SW_RSTOUT              (1 << 0)
 129
 130 /* HDMI_CORE_RSTOUT */
 131 #define HDMI_CORE_SW_RSTOUT             (1 << 0)
 132
 133 /* HDMI_CON_0 */
 134 #define HDMI_BLUE_SCR_EN                (1 << 5)
 135 #define HDMI_ASP_EN                     (1 << 2)
 136 #define HDMI_ASP_DIS                    (0 << 2)
 137 #define HDMI_ASP_MASK                   (1 << 2)
 138 #define HDMI_EN                         (1 << 0)
 139
 140 /* HDMI_CON_2 */
 141 #define HDMI_VID_PREAMBLE_DIS           (1 << 5)
 142 #define HDMI_GUARD_BAND_DIS             (1 << 1)
 143
 144 /* HDMI_PHY_STATUS */
 145 #define HDMI_PHY_STATUS_READY           (1 << 0)
 146
 147 /* HDMI_MODE_SEL */
 148 #define HDMI_MODE_HDMI_EN               (1 << 1)
 149 #define HDMI_MODE_DVI_EN                (1 << 0)
 150 #define HDMI_MODE_MASK                  (3 << 0)
 151
 152 /* HDMI_TG_CMD */
 153 #define HDMI_TG_EN                      (1 << 0)
 154 #define HDMI_FIELD_EN                   (1 << 1)
 155
 156
 157 /* HDMI Version 1.4 */
 158 /* Control registers */
 159 /* #define HDMI_INTC_CON                HDMI_CTRL_BASE(0x0000) */
 160 /* #define HDMI_INTC_FLAG               HDMI_CTRL_BASE(0x0004) */
 161 #define HDMI_HDCP_KEY_LOAD              HDMI_CTRL_BASE(0x0008)
 162 /* #define HDMI_HPD_STATUS              HDMI_CTRL_BASE(0x000C) */
 163 #define HDMI_INTC_CON_1                 HDMI_CTRL_BASE(0x0010)
 164 #define HDMI_INTC_FLAG_1                HDMI_CTRL_BASE(0x0014)
 165 #define HDMI_PHY_STATUS_0               HDMI_CTRL_BASE(0x0020)
 166 #define HDMI_PHY_STATUS_CMU             HDMI_CTRL_BASE(0x0024)
 167 #define HDMI_PHY_STATUS_PLL             HDMI_CTRL_BASE(0x0028)
 168 #define HDMI_PHY_CON_0                  HDMI_CTRL_BASE(0x0030)
 169 #define HDMI_HPD_CTRL                   HDMI_CTRL_BASE(0x0040)
 170 #define HDMI_HPD_ST                     HDMI_CTRL_BASE(0x0044)
 171 #define HDMI_HPD_TH_X                   HDMI_CTRL_BASE(0x0050)
 172 #define HDMI_AUDIO_CLKSEL               HDMI_CTRL_BASE(0x0070)
 173 #define HDMI_V14_PHY_RSTOUT             HDMI_CTRL_BASE(0x0074)
 174 #define HDMI_PHY_VPLL                   HDMI_CTRL_BASE(0x0078)
 175 #define HDMI_PHY_CMU                    HDMI_CTRL_BASE(0x007C)
 176 #define HDMI_CORE_RSTOUT                HDMI_CTRL_BASE(0x0080)
 177
 178 /* PHY Control bit definition */
 179
 180 /* HDMI_PHY_CON_0 */
 181 #define HDMI_PHY_POWER_OFF_EN           (1 << 0)
 182
 183 /* Video related registers */
 184 #define HDMI_YMAX                       HDMI_CORE_BASE(0x0060)
 185 #define HDMI_YMIN                       HDMI_CORE_BASE(0x0064)
 186 #define HDMI_CMAX                       HDMI_CORE_BASE(0x0068)
 187 #define HDMI_CMIN                       HDMI_CORE_BASE(0x006C)
 188
 189 #define HDMI_V2_BLANK_0                 HDMI_CORE_BASE(0x00B0)
 190 #define HDMI_V2_BLANK_1                 HDMI_CORE_BASE(0x00B4)
 191 #define HDMI_V1_BLANK_0                 HDMI_CORE_BASE(0x00B8)
 192 #define HDMI_V1_BLANK_1                 HDMI_CORE_BASE(0x00BC)
 193
 194 #define HDMI_V_LINE_0                   HDMI_CORE_BASE(0x00C0)
 195 #define HDMI_V_LINE_1                   HDMI_CORE_BASE(0x00C4)
 196 #define HDMI_H_LINE_0                   HDMI_CORE_BASE(0x00C8)
 197 #define HDMI_H_LINE_1                   HDMI_CORE_BASE(0x00CC)
 198
 199 #define HDMI_HSYNC_POL                  HDMI_CORE_BASE(0x00E0)
 200
 201 #define HDMI_V_BLANK_F0_0               HDMI_CORE_BASE(0x0110)
 202 #define HDMI_V_BLANK_F0_1               HDMI_CORE_BASE(0x0114)
 203 #define HDMI_V_BLANK_F1_0               HDMI_CORE_BASE(0x0118)
 204 #define HDMI_V_BLANK_F1_1               HDMI_CORE_BASE(0x011C)
 205
 206 #define HDMI_H_SYNC_START_0             HDMI_CORE_BASE(0x0120)
 207 #define HDMI_H_SYNC_START_1             HDMI_CORE_BASE(0x0124)
 208 #define HDMI_H_SYNC_END_0               HDMI_CORE_BASE(0x0128)
 209 #define HDMI_H_SYNC_END_1               HDMI_CORE_BASE(0x012C)
 210
 211 #define HDMI_V_SYNC_LINE_BEF_2_0        HDMI_CORE_BASE(0x0130)
 212 #define HDMI_V_SYNC_LINE_BEF_2_1        HDMI_CORE_BASE(0x0134)
 213 #define HDMI_V_SYNC_LINE_BEF_1_0        HDMI_CORE_BASE(0x0138)
 214 #define HDMI_V_SYNC_LINE_BEF_1_1        HDMI_CORE_BASE(0x013C)
 215
 216 #define HDMI_V_SYNC_LINE_AFT_2_0        HDMI_CORE_BASE(0x0140)
 217 #define HDMI_V_SYNC_LINE_AFT_2_1        HDMI_CORE_BASE(0x0144)
 218 #define HDMI_V_SYNC_LINE_AFT_1_0        HDMI_CORE_BASE(0x0148)
 219 #define HDMI_V_SYNC_LINE_AFT_1_1        HDMI_CORE_BASE(0x014C)
 220
 221 #define HDMI_V_SYNC_LINE_AFT_PXL_2_0    HDMI_CORE_BASE(0x0150)
 222 #define HDMI_V_SYNC_LINE_AFT_PXL_2_1    HDMI_CORE_BASE(0x0154)
 223 #define HDMI_V_SYNC_LINE_AFT_PXL_1_0    HDMI_CORE_BASE(0x0158)
 224 #define HDMI_V_SYNC_LINE_AFT_PXL_1_1    HDMI_CORE_BASE(0x015C)
 225
 226 #define HDMI_V_BLANK_F2_0               HDMI_CORE_BASE(0x0160)
 227 #define HDMI_V_BLANK_F2_1               HDMI_CORE_BASE(0x0164)
 228 #define HDMI_V_BLANK_F3_0               HDMI_CORE_BASE(0x0168)
 229 #define HDMI_V_BLANK_F3_1               HDMI_CORE_BASE(0x016C)
 230 #define HDMI_V_BLANK_F4_0               HDMI_CORE_BASE(0x0170)
 231 #define HDMI_V_BLANK_F4_1               HDMI_CORE_BASE(0x0174)
 232 #define HDMI_V_BLANK_F5_0               HDMI_CORE_BASE(0x0178)
 233 #define HDMI_V_BLANK_F5_1               HDMI_CORE_BASE(0x017C)
 234
 235 #define HDMI_V_SYNC_LINE_AFT_3_0        HDMI_CORE_BASE(0x0180)
 236 #define HDMI_V_SYNC_LINE_AFT_3_1        HDMI_CORE_BASE(0x0184)
 237 #define HDMI_V_SYNC_LINE_AFT_4_0        HDMI_CORE_BASE(0x0188)
 238 #define HDMI_V_SYNC_LINE_AFT_4_1        HDMI_CORE_BASE(0x018C)
 239 #define HDMI_V_SYNC_LINE_AFT_5_0        HDMI_CORE_BASE(0x0190)
 240 #define HDMI_V_SYNC_LINE_AFT_5_1        HDMI_CORE_BASE(0x0194)
 241 #define HDMI_V_SYNC_LINE_AFT_6_0        HDMI_CORE_BASE(0x0198)
 242 #define HDMI_V_SYNC_LINE_AFT_6_1        HDMI_CORE_BASE(0x019C)
 243
 244 #define HDMI_V_SYNC_LINE_AFT_PXL_3_0    HDMI_CORE_BASE(0x01A0)
 245 #define HDMI_V_SYNC_LINE_AFT_PXL_3_1    HDMI_CORE_BASE(0x01A4)
 246 #define HDMI_V_SYNC_LINE_AFT_PXL_4_0    HDMI_CORE_BASE(0x01A8)
 247 #define HDMI_V_SYNC_LINE_AFT_PXL_4_1    HDMI_CORE_BASE(0x01AC)
 248 #define HDMI_V_SYNC_LINE_AFT_PXL_5_0    HDMI_CORE_BASE(0x01B0)
 249 #define HDMI_V_SYNC_LINE_AFT_PXL_5_1    HDMI_CORE_BASE(0x01B4)
 250 #define HDMI_V_SYNC_LINE_AFT_PXL_6_0    HDMI_CORE_BASE(0x01B8)
 251 #define HDMI_V_SYNC_LINE_AFT_PXL_6_1    HDMI_CORE_BASE(0x01BC)
 252
 253 #define HDMI_VACT_SPACE_1_0             HDMI_CORE_BASE(0x01C0)
 254 #define HDMI_VACT_SPACE_1_1             HDMI_CORE_BASE(0x01C4)
 255 #define HDMI_VACT_SPACE_2_0             HDMI_CORE_BASE(0x01C8)
 256 #define HDMI_VACT_SPACE_2_1             HDMI_CORE_BASE(0x01CC)
 257 #define HDMI_VACT_SPACE_3_0             HDMI_CORE_BASE(0x01D0)
 258 #define HDMI_VACT_SPACE_3_1             HDMI_CORE_BASE(0x01D4)
 259 #define HDMI_VACT_SPACE_4_0             HDMI_CORE_BASE(0x01D8)
 260 #define HDMI_VACT_SPACE_4_1             HDMI_CORE_BASE(0x01DC)
 261 #define HDMI_VACT_SPACE_5_0             HDMI_CORE_BASE(0x01E0)
 262 #define HDMI_VACT_SPACE_5_1             HDMI_CORE_BASE(0x01E4)
 263 #define HDMI_VACT_SPACE_6_0             HDMI_CORE_BASE(0x01E8)
 264 #define HDMI_VACT_SPACE_6_1             HDMI_CORE_BASE(0x01EC)
 265
 266 #define HDMI_GCP_CON                    HDMI_CORE_BASE(0x0200)
 267 #define HDMI_GCP_BYTE1                  HDMI_CORE_BASE(0x0210)
 268 #define HDMI_GCP_BYTE2                  HDMI_CORE_BASE(0x0214)
 269 #define HDMI_GCP_BYTE3                  HDMI_CORE_BASE(0x0218)
 270
 271 /* Audio related registers */
 272 #define HDMI_ASP_CON                    HDMI_CORE_BASE(0x0300)
 273 #define HDMI_ASP_SP_FLAT                HDMI_CORE_BASE(0x0304)
 274 #define HDMI_ASP_CHCFG0                 HDMI_CORE_BASE(0x0310)
 275 #define HDMI_ASP_CHCFG1                 HDMI_CORE_BASE(0x0314)
 276 #define HDMI_ASP_CHCFG2                 HDMI_CORE_BASE(0x0318)
 277 #define HDMI_ASP_CHCFG3                 HDMI_CORE_BASE(0x031C)
 278
 279 #define HDMI_V13_ACR_CON                HDMI_CORE_BASE(0x0180)
 280 #define HDMI_V13_ACR_MCTS0              HDMI_CORE_BASE(0x0184)
 281 #define HDMI_V13_ACR_MCTS1              HDMI_CORE_BASE(0x0188)
 282 #define HDMI_V13_ACR_MCTS2              HDMI_CORE_BASE(0x018C)
 283 #define HDMI_V13_ACR_CTS0               HDMI_CORE_BASE(0x0190)
 284 #define HDMI_V13_ACR_CTS1               HDMI_CORE_BASE(0x0194)
 285 #define HDMI_V13_ACR_CTS2               HDMI_CORE_BASE(0x0198)
 286 #define HDMI_V13_ACR_N0                 HDMI_CORE_BASE(0x01A0)
 287 #define HDMI_V13_ACR_N1                 HDMI_CORE_BASE(0x01A4)
 288 #define HDMI_V13_ACR_N2                 HDMI_CORE_BASE(0x01A8)
 289 #define HDMI_V14_ACR_CON                HDMI_CORE_BASE(0x0400)
 290 #define HDMI_V14_ACR_MCTS0              HDMI_CORE_BASE(0x0410)
 291 #define HDMI_V14_ACR_MCTS1              HDMI_CORE_BASE(0x0414)
 292 #define HDMI_V14_ACR_MCTS2              HDMI_CORE_BASE(0x0418)
 293 #define HDMI_V14_ACR_CTS0               HDMI_CORE_BASE(0x0420)
 294 #define HDMI_V14_ACR_CTS1               HDMI_CORE_BASE(0x0424)
 295 #define HDMI_V14_ACR_CTS2               HDMI_CORE_BASE(0x0428)
 296 #define HDMI_V14_ACR_N0                 HDMI_CORE_BASE(0x0430)
 297 #define HDMI_V14_ACR_N1                 HDMI_CORE_BASE(0x0434)
 298 #define HDMI_V14_ACR_N2                 HDMI_CORE_BASE(0x0438)
 299
 300 /* Packet related registers */
 301 #define HDMI_ACP_CON                    HDMI_CORE_BASE(0x0500)
 302 #define HDMI_ACP_TYPE                   HDMI_CORE_BASE(0x0514)
 303 #define HDMI_ACP_DATA(n)                HDMI_CORE_BASE(0x0520 + 4 * (n))
 304
 305 #define HDMI_ISRC_CON                   HDMI_CORE_BASE(0x0600)
 306 #define HDMI_ISRC1_HEADER1              HDMI_CORE_BASE(0x0614)
 307 #define HDMI_ISRC1_DATA(n)              HDMI_CORE_BASE(0x0620 + 4 * (n))
 308 #define HDMI_ISRC2_DATA(n)              HDMI_CORE_BASE(0x06A0 + 4 * (n))
 309
 310 #define HDMI_AVI_CON                    HDMI_CORE_BASE(0x0700)
 311 #define HDMI_AVI_HEADER0                HDMI_CORE_BASE(0x0710)
 312 #define HDMI_AVI_HEADER1                HDMI_CORE_BASE(0x0714)
 313 #define HDMI_AVI_HEADER2                HDMI_CORE_BASE(0x0718)
 314 #define HDMI_AVI_CHECK_SUM              HDMI_CORE_BASE(0x071C)
 315 #define HDMI_AVI_BYTE(n)                HDMI_CORE_BASE(0x0720 + 4 * (n-1))
 316
 317 #define HDMI_AUI_CON                    HDMI_CORE_BASE(0x0800)
 318 #define HDMI_AUI_HEADER0                HDMI_CORE_BASE(0x0810)
 319 #define HDMI_AUI_HEADER1                HDMI_CORE_BASE(0x0814)
 320 #define HDMI_AUI_HEADER2                HDMI_CORE_BASE(0x0818)
 321 #define HDMI_AUI_CHECK_SUM              HDMI_CORE_BASE(0x081C)
 322 #define HDMI_AUI_BYTE(n)                HDMI_CORE_BASE(0x0820 + 4 * (n-1))
 323
 324 #define HDMI_MPG_CON                    HDMI_CORE_BASE(0x0900)
 325 #define HDMI_MPG_CHECK_SUM              HDMI_CORE_BASE(0x091C)
 326 #define HDMI_MPG_DATA(n)                HDMI_CORE_BASE(0x0920 + 4 * (n))
 327
 328 #define HDMI_SPD_CON                    HDMI_CORE_BASE(0x0A00)
 329 #define HDMI_SPD_HEADER0                HDMI_CORE_BASE(0x0A10)
 330 #define HDMI_SPD_HEADER1                HDMI_CORE_BASE(0x0A14)
 331 #define HDMI_SPD_HEADER2                HDMI_CORE_BASE(0x0A18)
 332 #define HDMI_SPD_DATA(n)                HDMI_CORE_BASE(0x0A20 + 4 * (n))
 333
 334 #define HDMI_GAMUT_CON                  HDMI_CORE_BASE(0x0B00)
 335 #define HDMI_GAMUT_HEADER0              HDMI_CORE_BASE(0x0B10)
 336 #define HDMI_GAMUT_HEADER1              HDMI_CORE_BASE(0x0B14)
 337 #define HDMI_GAMUT_HEADER2              HDMI_CORE_BASE(0x0B18)
 338 #define HDMI_GAMUT_METADATA(n)          HDMI_CORE_BASE(0x0B20 + 4 * (n))
 339
 340 #define HDMI_VSI_CON                    HDMI_CORE_BASE(0x0C00)
 341 #define HDMI_VSI_HEADER0                HDMI_CORE_BASE(0x0C10)
 342 #define HDMI_VSI_HEADER1                HDMI_CORE_BASE(0x0C14)
 343 #define HDMI_VSI_HEADER2                HDMI_CORE_BASE(0x0C18)
 344 #define HDMI_VSI_DATA(n)                HDMI_CORE_BASE(0x0C20 + 4 * (n))
 345
 346 #define HDMI_DC_CONTROL                 HDMI_CORE_BASE(0x0D00)
 347 #define HDMI_VIDEO_PATTERN_GEN          HDMI_CORE_BASE(0x0D04)
 348
 349 #define HDMI_AN_SEED_SEL                HDMI_CORE_BASE(0x0E48)
 350 #define HDMI_AN_SEED_0                  HDMI_CORE_BASE(0x0E58)
 351 #define HDMI_AN_SEED_1                  HDMI_CORE_BASE(0x0E5C)
 352 #define HDMI_AN_SEED_2                  HDMI_CORE_BASE(0x0E60)
 353 #define HDMI_AN_SEED_3                  HDMI_CORE_BASE(0x0E64)
 354
 355 /* AVI bit definition */
 356 #define HDMI_AVI_CON_DO_NOT_TRANSMIT    (0 << 1)
 357 #define HDMI_AVI_CON_EVERY_VSYNC        (1 << 1)
 358
 359 #define AVI_ACTIVE_FORMAT_VALID (1 << 4)
 360 #define AVI_UNDERSCANNED_DISPLAY_VALID  (1 << 1)
 361
 362 /* AUI bit definition */
 363 #define HDMI_AUI_CON_NO_TRAN            (0 << 0)
 364
 365 /* VSI bit definition */
 366 #define HDMI_VSI_CON_DO_NOT_TRANSMIT    (0 << 0)
 367
 368 /* HDCP related registers */
 369 #define HDMI_HDCP_SHA1(n)               HDMI_CORE_BASE(0x7000 + 4 * (n))
 370 #define HDMI_HDCP_KSV_LIST(n)           HDMI_CORE_BASE(0x7050 + 4 * (n))
 371
 372 #define HDMI_HDCP_KSV_LIST_CON          HDMI_CORE_BASE(0x7064)
 373 #define HDMI_HDCP_SHA_RESULT            HDMI_CORE_BASE(0x7070)
 374 #define HDMI_HDCP_CTRL1                 HDMI_CORE_BASE(0x7080)
 375 #define HDMI_HDCP_CTRL2                 HDMI_CORE_BASE(0x7084)
 376 #define HDMI_HDCP_CHECK_RESULT          HDMI_CORE_BASE(0x7090)
 377 #define HDMI_HDCP_BKSV(n)               HDMI_CORE_BASE(0x70A0 + 4 * (n))
 378 #define HDMI_HDCP_AKSV(n)               HDMI_CORE_BASE(0x70C0 + 4 * (n))
 379 #define HDMI_HDCP_AN(n)                 HDMI_CORE_BASE(0x70E0 + 4 * (n))
 380
 381 #define HDMI_HDCP_BCAPS                 HDMI_CORE_BASE(0x7100)
 382 #define HDMI_HDCP_BSTATUS_0             HDMI_CORE_BASE(0x7110)
 383 #define HDMI_HDCP_BSTATUS_1             HDMI_CORE_BASE(0x7114)
 384 #define HDMI_HDCP_RI_0                  HDMI_CORE_BASE(0x7140)
 385 #define HDMI_HDCP_RI_1                  HDMI_CORE_BASE(0x7144)
 386 #define HDMI_HDCP_I2C_INT               HDMI_CORE_BASE(0x7180)
 387 #define HDMI_HDCP_AN_INT                HDMI_CORE_BASE(0x7190)
 388 #define HDMI_HDCP_WDT_INT               HDMI_CORE_BASE(0x71A0)
 389 #define HDMI_HDCP_RI_INT                HDMI_CORE_BASE(0x71B0)
 390 #define HDMI_HDCP_RI_COMPARE_0          HDMI_CORE_BASE(0x71D0)
 391 #define HDMI_HDCP_RI_COMPARE_1          HDMI_CORE_BASE(0x71D4)
 392 #define HDMI_HDCP_FRAME_COUNT           HDMI_CORE_BASE(0x71E0)
 393
 394 #define HDMI_RGB_ROUND_EN               HDMI_CORE_BASE(0xD500)
 395 #define HDMI_VACT_SPACE_R_0             HDMI_CORE_BASE(0xD504)
 396 #define HDMI_VACT_SPACE_R_1             HDMI_CORE_BASE(0xD508)
 397 #define HDMI_VACT_SPACE_G_0             HDMI_CORE_BASE(0xD50C)
 398 #define HDMI_VACT_SPACE_G_1             HDMI_CORE_BASE(0xD510)
 399 #define HDMI_VACT_SPACE_B_0             HDMI_CORE_BASE(0xD514)
 400 #define HDMI_VACT_SPACE_B_1             HDMI_CORE_BASE(0xD518)
 401
 402 #define HDMI_BLUE_SCREEN_B_0            HDMI_CORE_BASE(0xD520)
 403 #define HDMI_BLUE_SCREEN_B_1            HDMI_CORE_BASE(0xD524)
 404 #define HDMI_BLUE_SCREEN_G_0            HDMI_CORE_BASE(0xD528)
 405 #define HDMI_BLUE_SCREEN_G_1            HDMI_CORE_BASE(0xD52C)
 406 #define HDMI_BLUE_SCREEN_R_0            HDMI_CORE_BASE(0xD530)
 407 #define HDMI_BLUE_SCREEN_R_1            HDMI_CORE_BASE(0xD534)
 408
 409 /* HDMI I2S register */
 410 #define HDMI_I2S_CLK_CON                HDMI_I2S_BASE(0x000)
 411 #define HDMI_I2S_CON_1                  HDMI_I2S_BASE(0x004)
 412 #define HDMI_I2S_CON_2                  HDMI_I2S_BASE(0x008)
 413 #define HDMI_I2S_PIN_SEL_0              HDMI_I2S_BASE(0x00c)
 414 #define HDMI_I2S_PIN_SEL_1              HDMI_I2S_BASE(0x010)
 415 #define HDMI_I2S_PIN_SEL_2              HDMI_I2S_BASE(0x014)
 416 #define HDMI_I2S_PIN_SEL_3              HDMI_I2S_BASE(0x018)
 417 #define HDMI_I2S_DSD_CON                HDMI_I2S_BASE(0x01c)
 418 #define HDMI_I2S_MUX_CON                HDMI_I2S_BASE(0x020)
 419 #define HDMI_I2S_CH_ST_CON              HDMI_I2S_BASE(0x024)
 420 #define HDMI_I2S_CH_ST_0                HDMI_I2S_BASE(0x028)
 421 #define HDMI_I2S_CH_ST_1                HDMI_I2S_BASE(0x02c)
 422 #define HDMI_I2S_CH_ST_2                HDMI_I2S_BASE(0x030)
 423 #define HDMI_I2S_CH_ST_3                HDMI_I2S_BASE(0x034)
 424 #define HDMI_I2S_CH_ST_4                HDMI_I2S_BASE(0x038)
 425 #define HDMI_I2S_CH_ST_SH_0             HDMI_I2S_BASE(0x03c)
 426 #define HDMI_I2S_CH_ST_SH_1             HDMI_I2S_BASE(0x040)
 427 #define HDMI_I2S_CH_ST_SH_2             HDMI_I2S_BASE(0x044)
 428 #define HDMI_I2S_CH_ST_SH_3             HDMI_I2S_BASE(0x048)
 429 #define HDMI_I2S_CH_ST_SH_4             HDMI_I2S_BASE(0x04c)
 430 #define HDMI_I2S_MUX_CH                 HDMI_I2S_BASE(0x054)
 431 #define HDMI_I2S_MUX_CUV                HDMI_I2S_BASE(0x058)
 432
 433 /* I2S bit definition */
 434
 435 /* I2S_CLK_CON */
 436 #define HDMI_I2S_CLK_DIS                (0)
 437 #define HDMI_I2S_CLK_EN                 (1)
 438
 439 /* I2S_CON_1 */
 440 #define HDMI_I2S_SCLK_FALLING_EDGE      (0 << 1)
 441 #define HDMI_I2S_SCLK_RISING_EDGE       (1 << 1)
 442 #define HDMI_I2S_L_CH_LOW_POL           (0)
 443 #define HDMI_I2S_L_CH_HIGH_POL          (1)
 444
 445 /* I2S_CON_2 */
 446 #define HDMI_I2S_MSB_FIRST_MODE         (0 << 6)
 447 #define HDMI_I2S_LSB_FIRST_MODE         (1 << 6)
 448 #define HDMI_I2S_BIT_CH_32FS            (0 << 4)
 449 #define HDMI_I2S_BIT_CH_48FS            (1 << 4)
 450 #define HDMI_I2S_BIT_CH_RESERVED        (2 << 4)
 451 #define HDMI_I2S_SDATA_16BIT            (1 << 2)
 452 #define HDMI_I2S_SDATA_20BIT            (2 << 2)
 453 #define HDMI_I2S_SDATA_24BIT            (3 << 2)
 454 #define HDMI_I2S_BASIC_FORMAT           (0)
 455 #define HDMI_I2S_L_JUST_FORMAT          (2)
 456 #define HDMI_I2S_R_JUST_FORMAT          (3)
 457 #define HDMI_I2S_CON_2_CLR              (~(0xFF))
 458 #define HDMI_I2S_SET_BIT_CH(x)          (((x) & 0x7) << 4)
 459 #define HDMI_I2S_SET_SDATA_BIT(x)       (((x) & 0x7) << 2)
 460
 461 /* I2S_PIN_SEL_0 */
 462 #define HDMI_I2S_SEL_SCLK(x)            (((x) & 0x7) << 4)
 463 #define HDMI_I2S_SEL_LRCK(x)            ((x) & 0x7)
 464
 465 /* I2S_PIN_SEL_1 */
 466 #define HDMI_I2S_SEL_SDATA1(x)          (((x) & 0x7) << 4)
 467 #define HDMI_I2S_SEL_SDATA2(x)          ((x) & 0x7)
 468
 469 /* I2S_PIN_SEL_2 */
 470 #define HDMI_I2S_SEL_SDATA3(x)          (((x) & 0x7) << 4)
 471 #define HDMI_I2S_SEL_SDATA2(x)          ((x) & 0x7)
 472
 473 /* I2S_PIN_SEL_3 */
 474 #define HDMI_I2S_SEL_DSD(x)             ((x) & 0x7)
 475
 476 /* I2S_DSD_CON */
 477 #define HDMI_I2S_DSD_CLK_RI_EDGE        (1 << 1)
 478 #define HDMI_I2S_DSD_CLK_FA_EDGE        (0 << 1)
 479 #define HDMI_I2S_DSD_ENABLE             (1)
 480 #define HDMI_I2S_DSD_DISABLE            (0)
 481
 482 /* I2S_MUX_CON */
 483 #define HDMI_I2S_NOISE_FILTER_ZERO      (0 << 5)
 484 #define HDMI_I2S_NOISE_FILTER_2_STAGE   (1 << 5)
 485 #define HDMI_I2S_NOISE_FILTER_3_STAGE   (2 << 5)
 486 #define HDMI_I2S_NOISE_FILTER_4_STAGE   (3 << 5)
 487 #define HDMI_I2S_NOISE_FILTER_5_STAGE   (4 << 5)
 488 #define HDMI_I2S_IN_DISABLE             (1 << 4)
 489 #define HDMI_I2S_IN_ENABLE              (0 << 4)
 490 #define HDMI_I2S_AUD_SPDIF              (0 << 2)
 491 #define HDMI_I2S_AUD_I2S                (1 << 2)
 492 #define HDMI_I2S_AUD_DSD                (2 << 2)
 493 #define HDMI_I2S_CUV_SPDIF_ENABLE       (0 << 1)
 494 #define HDMI_I2S_CUV_I2S_ENABLE         (1 << 1)
 495 #define HDMI_I2S_MUX_DISABLE            (0)
 496 #define HDMI_I2S_MUX_ENABLE             (1)
 497 #define HDMI_I2S_MUX_CON_CLR            (~(0xFF))
 498
 499 /* I2S_CH_ST_CON */
 500 #define HDMI_I2S_CH_STATUS_RELOAD       (1)
 501 #define HDMI_I2S_CH_ST_CON_CLR          (~(1))
 502
 503 /* I2S_CH_ST_0 / I2S_CH_ST_SH_0 */
 504 #define HDMI_I2S_CH_STATUS_MODE_0       (0 << 6)
 505 #define HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH        (0 << 3)
 506 #define HDMI_I2S_2AUD_CH_WITH_PREEMPH   (1 << 3)
 507 #define HDMI_I2S_DEFAULT_EMPHASIS       (0 << 3)
 508 #define HDMI_I2S_COPYRIGHT              (0 << 2)
 509 #define HDMI_I2S_NO_COPYRIGHT           (1 << 2)
 510 #define HDMI_I2S_LINEAR_PCM             (0 << 1)
 511 #define HDMI_I2S_NO_LINEAR_PCM          (1 << 1)
 512 #define HDMI_I2S_CONSUMER_FORMAT        (0)
 513 #define HDMI_I2S_PROF_FORMAT            (1)
 514 #define HDMI_I2S_CH_ST_0_CLR            (~(0xFF))
 515
 516 /* I2S_CH_ST_1 / I2S_CH_ST_SH_1 */
 517 #define HDMI_I2S_CD_PLAYER              (0x00)
 518 #define HDMI_I2S_DAT_PLAYER             (0x03)
 519 #define HDMI_I2S_DCC_PLAYER             (0x43)
 520 #define HDMI_I2S_MINI_DISC_PLAYER       (0x49)
 521
 522 /* I2S_CH_ST_2 / I2S_CH_ST_SH_2 */
 523 #define HDMI_I2S_CHANNEL_NUM_MASK       (0xF << 4)
 524 #define HDMI_I2S_SOURCE_NUM_MASK        (0xF)
 525 #define HDMI_I2S_SET_CHANNEL_NUM(x)     (((x) & (0xF)) << 4)
 526 #define HDMI_I2S_SET_SOURCE_NUM(x)      ((x) & (0xF))
 527
 528 /* I2S_CH_ST_3 / I2S_CH_ST_SH_3 */
 529 #define HDMI_I2S_CLK_ACCUR_LEVEL_1      (1 << 4)
 530 #define HDMI_I2S_CLK_ACCUR_LEVEL_2      (0 << 4)
 531 #define HDMI_I2S_CLK_ACCUR_LEVEL_3      (2 << 4)
 532 #define HDMI_I2S_SMP_FREQ_44_1          (0x0)
 533 #define HDMI_I2S_SMP_FREQ_48            (0x2)
 534 #define HDMI_I2S_SMP_FREQ_32            (0x3)
 535 #define HDMI_I2S_SMP_FREQ_96            (0xA)
 536 #define HDMI_I2S_SET_SMP_FREQ(x)        ((x) & (0xF))
 537
 538 /* I2S_CH_ST_4 / I2S_CH_ST_SH_4 */
 539 #define HDMI_I2S_ORG_SMP_FREQ_44_1      (0xF << 4)
 540 #define HDMI_I2S_ORG_SMP_FREQ_88_2      (0x7 << 4)
 541 #define HDMI_I2S_ORG_SMP_FREQ_22_05     (0xB << 4)
 542 #define HDMI_I2S_ORG_SMP_FREQ_176_4     (0x3 << 4)
 543 #define HDMI_I2S_WORD_LEN_NOT_DEFINE    (0x0 << 1)
 544 #define HDMI_I2S_WORD_LEN_MAX24_20BITS  (0x1 << 1)
 545 #define HDMI_I2S_WORD_LEN_MAX24_22BITS  (0x2 << 1)
 546 #define HDMI_I2S_WORD_LEN_MAX24_23BITS  (0x4 << 1)
 547 #define HDMI_I2S_WORD_LEN_MAX24_24BITS  (0x5 << 1)
 548 #define HDMI_I2S_WORD_LEN_MAX24_21BITS  (0x6 << 1)
 549 #define HDMI_I2S_WORD_LEN_MAX20_16BITS  (0x1 << 1)
 550 #define HDMI_I2S_WORD_LEN_MAX20_18BITS  (0x2 << 1)
 551 #define HDMI_I2S_WORD_LEN_MAX20_19BITS  (0x4 << 1)
 552 #define HDMI_I2S_WORD_LEN_MAX20_20BITS  (0x5 << 1)
 553 #define HDMI_I2S_WORD_LEN_MAX20_17BITS  (0x6 << 1)
 554 #define HDMI_I2S_WORD_LEN_MAX_24BITS    (1)
 555 #define HDMI_I2S_WORD_LEN_MAX_20BITS    (0)
 556
 557 /* I2S_MUX_CH */
 558 #define HDMI_I2S_CH3_R_EN               (1 << 7)
 559 #define HDMI_I2S_CH3_L_EN               (1 << 6)
 560 #define HDMI_I2S_CH3_EN                 (3 << 6)
 561 #define HDMI_I2S_CH2_R_EN               (1 << 5)
 562 #define HDMI_I2S_CH2_L_EN               (1 << 4)
 563 #define HDMI_I2S_CH2_EN                 (3 << 4)
 564 #define HDMI_I2S_CH1_R_EN               (1 << 3)
 565 #define HDMI_I2S_CH1_L_EN               (1 << 2)
 566 #define HDMI_I2S_CH1_EN                 (3 << 2)
 567 #define HDMI_I2S_CH0_R_EN               (1 << 1)
 568 #define HDMI_I2S_CH0_L_EN               (1)
 569 #define HDMI_I2S_CH0_EN                 (3)
 570 #define HDMI_I2S_CH_ALL_EN              (0xFF)
 571 #define HDMI_I2S_MUX_CH_CLR             (~HDMI_I2S_CH_ALL_EN)
 572
 573 /* I2S_MUX_CUV */
 574 #define HDMI_I2S_CUV_R_EN               (1 << 1)
 575 #define HDMI_I2S_CUV_L_EN               (1)
 576 #define HDMI_I2S_CUV_RL_EN              (0x03)
 577
 578 /* I2S_CUV_L_R */
 579 #define HDMI_I2S_CUV_R_DATA_MASK        (0x7 << 4)
 580 #define HDMI_I2S_CUV_L_DATA_MASK        (0x7)
 581
 582 /* Timing generator registers */
 583 /* TG configure/status registers */
 584 #define HDMI_TG_VACT_ST3_L              HDMI_TG_BASE(0x0068)
 585 #define HDMI_TG_VACT_ST3_H              HDMI_TG_BASE(0x006c)
 586 #define HDMI_TG_VACT_ST4_L              HDMI_TG_BASE(0x0070)
 587 #define HDMI_TG_VACT_ST4_H              HDMI_TG_BASE(0x0074)
 588 #define HDMI_TG_3D                      HDMI_TG_BASE(0x00F0)
 589
 590 /* HDMI PHY Registers Offsets*/
 591 #define HDMIPHY_POWER           (0x74 >> 2)
 592 #define HDMIPHY_MODE_SET_DONE           (0x7c >> 2)
 593
 594 /* HDMI PHY Values */
 595 #define HDMI_PHY_POWER_ON              0x80
 596 #define HDMI_PHY_POWER_OFF             0xff
 597
 598 /* HDMI PHY Values */
 599 #define HDMI_PHY_DISABLE_MODE_SET       0x80
 600 #define HDMI_PHY_ENABLE_MODE_SET        0x00
 601
 602 /* PMU Registers for PHY */
 603 #define PMU_HDMI_PHY_CONTROL            0x700
 604 #define PMU_HDMI_PHY_ENABLE_BIT         BIT(0)
 605
 606 #endif /* SAMSUNG_REGS_HDMI_H */