1 /**************************************************************************
2 * Copyright (c) 2011, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 **************************************************************************/
20 #include <linux/backlight.h>
26 #include "psb_intel_reg.h"
27 #include "intel_bios.h"
28 #include "cdv_device.h"
30 #define VGA_SR_INDEX 0x3c4
31 #define VGA_SR_DATA 0x3c5
33 static void cdv_disable_vga(struct drm_device
*dev
)
40 outb(1, VGA_SR_INDEX
);
41 sr1
= inb(VGA_SR_DATA
);
42 outb(sr1
| 1<<5, VGA_SR_DATA
);
45 REG_WRITE(vga_reg
, VGA_DISP_DISABLE
);
49 static int cdv_output_init(struct drm_device
*dev
)
51 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
54 cdv_intel_crt_init(dev
, &dev_priv
->mode_dev
);
55 cdv_intel_lvds_init(dev
, &dev_priv
->mode_dev
);
57 /* These bits indicate HDMI not SDVO on CDV, but we don't yet support
59 if (REG_READ(SDVOB
) & SDVO_DETECTED
)
60 cdv_hdmi_init(dev
, &dev_priv
->mode_dev
, SDVOB
);
61 if (REG_READ(SDVOC
) & SDVO_DETECTED
)
62 cdv_hdmi_init(dev
, &dev_priv
->mode_dev
, SDVOC
);
66 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
69 * Poulsbo Backlight Interfaces
72 #define BLC_PWM_PRECISION_FACTOR 100 /* 10000000 */
73 #define BLC_PWM_FREQ_CALC_CONSTANT 32
76 #define PSB_BLC_PWM_PRECISION_FACTOR 10
77 #define PSB_BLC_MAX_PWM_REG_FREQ 0xFFFE
78 #define PSB_BLC_MIN_PWM_REG_FREQ 0x2
80 #define PSB_BACKLIGHT_PWM_POLARITY_BIT_CLEAR (0xFFFE)
81 #define PSB_BACKLIGHT_PWM_CTL_SHIFT (16)
83 static int cdv_brightness
;
84 static struct backlight_device
*cdv_backlight_device
;
86 static int cdv_get_brightness(struct backlight_device
*bd
)
88 /* return locally cached var instead of HW read (due to DPST etc.) */
89 /* FIXME: ideally return actual value in case firmware fiddled with
91 return cdv_brightness
;
95 static int cdv_backlight_setup(struct drm_device
*dev
)
97 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
98 unsigned long core_clock
;
99 /* u32 bl_max_freq; */
100 /* unsigned long value; */
103 uint32_t blc_pwm_precision_factor
;
105 /* get bl_max_freq and pol from dev_priv*/
106 if (!dev_priv
->lvds_bl
) {
107 dev_err(dev
->dev
, "Has no valid LVDS backlight info\n");
110 bl_max_freq
= dev_priv
->lvds_bl
->freq
;
111 blc_pwm_precision_factor
= PSB_BLC_PWM_PRECISION_FACTOR
;
113 core_clock
= dev_priv
->core_freq
;
115 value
= (core_clock
* MHz
) / BLC_PWM_FREQ_CALC_CONSTANT
;
116 value
*= blc_pwm_precision_factor
;
117 value
/= bl_max_freq
;
118 value
/= blc_pwm_precision_factor
;
120 if (value
> (unsigned long long)PSB_BLC_MAX_PWM_REG_FREQ
||
121 value
< (unsigned long long)PSB_BLC_MIN_PWM_REG_FREQ
)
129 static int cdv_set_brightness(struct backlight_device
*bd
)
131 int level
= bd
->props
.brightness
;
133 /* Percentage 1-100% being valid */
137 /*cdv_intel_lvds_set_brightness(dev, level); FIXME */
138 cdv_brightness
= level
;
142 static const struct backlight_ops cdv_ops
= {
143 .get_brightness
= cdv_get_brightness
,
144 .update_status
= cdv_set_brightness
,
147 static int cdv_backlight_init(struct drm_device
*dev
)
149 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
151 struct backlight_properties props
;
153 memset(&props
, 0, sizeof(struct backlight_properties
));
154 props
.max_brightness
= 100;
155 props
.type
= BACKLIGHT_PLATFORM
;
157 cdv_backlight_device
= backlight_device_register("psb-bl",
158 NULL
, (void *)dev
, &cdv_ops
, &props
);
159 if (IS_ERR(cdv_backlight_device
))
160 return PTR_ERR(cdv_backlight_device
);
162 ret
= cdv_backlight_setup(dev
);
164 backlight_device_unregister(cdv_backlight_device
);
165 cdv_backlight_device
= NULL
;
168 cdv_backlight_device
->props
.brightness
= 100;
169 cdv_backlight_device
->props
.max_brightness
= 100;
170 backlight_update_status(cdv_backlight_device
);
171 dev_priv
->backlight_device
= cdv_backlight_device
;
178 * Provide the Cedarview specific chip logic and low level methods
179 * for power management
181 * FIXME: we need to implement the apm/ospm base management bits
182 * for this and the MID devices.
185 static inline u32
CDV_MSG_READ32(uint port
, uint offset
)
187 int mcr
= (0x10<<24) | (port
<< 16) | (offset
<< 8);
188 uint32_t ret_val
= 0;
189 struct pci_dev
*pci_root
= pci_get_bus_and_slot(0, 0);
190 pci_write_config_dword(pci_root
, 0xD0, mcr
);
191 pci_read_config_dword(pci_root
, 0xD4, &ret_val
);
192 pci_dev_put(pci_root
);
196 static inline void CDV_MSG_WRITE32(uint port
, uint offset
, u32 value
)
198 int mcr
= (0x11<<24) | (port
<< 16) | (offset
<< 8) | 0xF0;
199 struct pci_dev
*pci_root
= pci_get_bus_and_slot(0, 0);
200 pci_write_config_dword(pci_root
, 0xD4, value
);
201 pci_write_config_dword(pci_root
, 0xD0, mcr
);
202 pci_dev_put(pci_root
);
205 #define PSB_PM_SSC 0x20
206 #define PSB_PM_SSS 0x30
207 #define PSB_PWRGT_GFX_ON 0x02
208 #define PSB_PWRGT_GFX_OFF 0x01
209 #define PSB_PWRGT_GFX_D0 0x00
210 #define PSB_PWRGT_GFX_D3 0x03
212 static void cdv_init_pm(struct drm_device
*dev
)
214 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
218 dev_priv
->apm_base
= CDV_MSG_READ32(PSB_PUNIT_PORT
,
220 dev_priv
->ospm_base
= CDV_MSG_READ32(PSB_PUNIT_PORT
,
221 PSB_OSPMBA
) & 0xFFFF;
224 pwr_cnt
= inl(dev_priv
->apm_base
+ PSB_APM_CMD
);
227 pwr_cnt
&= ~PSB_PWRGT_GFX_MASK
;
228 pwr_cnt
|= PSB_PWRGT_GFX_ON
;
229 outl(pwr_cnt
, dev_priv
->apm_base
+ PSB_APM_CMD
);
231 /* Wait for the GPU power */
232 for (i
= 0; i
< 5; i
++) {
233 u32 pwr_sts
= inl(dev_priv
->apm_base
+ PSB_APM_STS
);
234 if ((pwr_sts
& PSB_PWRGT_GFX_MASK
) == 0)
238 dev_err(dev
->dev
, "GPU: power management timed out.\n");
242 * cdv_save_display_registers - save registers lost on suspend
243 * @dev: our DRM device
245 * Save the state we need in order to be able to restore the interface
246 * upon resume from suspend
248 static int cdv_save_display_registers(struct drm_device
*dev
)
250 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
251 struct psb_save_area
*regs
= &dev_priv
->regs
;
252 struct drm_connector
*connector
;
254 dev_info(dev
->dev
, "Saving GPU registers.\n");
256 pci_read_config_byte(dev
->pdev
, 0xF4, ®s
->cdv
.saveLBB
);
258 regs
->cdv
.saveDSPCLK_GATE_D
= REG_READ(DSPCLK_GATE_D
);
259 regs
->cdv
.saveRAMCLK_GATE_D
= REG_READ(RAMCLK_GATE_D
);
261 regs
->cdv
.saveDSPARB
= REG_READ(DSPARB
);
262 regs
->cdv
.saveDSPFW
[0] = REG_READ(DSPFW1
);
263 regs
->cdv
.saveDSPFW
[1] = REG_READ(DSPFW2
);
264 regs
->cdv
.saveDSPFW
[2] = REG_READ(DSPFW3
);
265 regs
->cdv
.saveDSPFW
[3] = REG_READ(DSPFW4
);
266 regs
->cdv
.saveDSPFW
[4] = REG_READ(DSPFW5
);
267 regs
->cdv
.saveDSPFW
[5] = REG_READ(DSPFW6
);
269 regs
->cdv
.saveADPA
= REG_READ(ADPA
);
271 regs
->cdv
.savePP_CONTROL
= REG_READ(PP_CONTROL
);
272 regs
->cdv
.savePFIT_PGM_RATIOS
= REG_READ(PFIT_PGM_RATIOS
);
273 regs
->saveBLC_PWM_CTL
= REG_READ(BLC_PWM_CTL
);
274 regs
->saveBLC_PWM_CTL2
= REG_READ(BLC_PWM_CTL2
);
275 regs
->cdv
.saveLVDS
= REG_READ(LVDS
);
277 regs
->cdv
.savePFIT_CONTROL
= REG_READ(PFIT_CONTROL
);
279 regs
->cdv
.savePP_ON_DELAYS
= REG_READ(PP_ON_DELAYS
);
280 regs
->cdv
.savePP_OFF_DELAYS
= REG_READ(PP_OFF_DELAYS
);
281 regs
->cdv
.savePP_CYCLE
= REG_READ(PP_CYCLE
);
283 regs
->cdv
.saveVGACNTRL
= REG_READ(VGACNTRL
);
285 regs
->cdv
.saveIER
= REG_READ(PSB_INT_ENABLE_R
);
286 regs
->cdv
.saveIMR
= REG_READ(PSB_INT_MASK_R
);
288 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
)
289 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_OFF
);
295 * cdv_restore_display_registers - restore lost register state
296 * @dev: our DRM device
298 * Restore register state that was lost during suspend and resume.
302 static int cdv_restore_display_registers(struct drm_device
*dev
)
304 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
305 struct psb_save_area
*regs
= &dev_priv
->regs
;
306 struct drm_connector
*connector
;
309 pci_write_config_byte(dev
->pdev
, 0xF4, regs
->cdv
.saveLBB
);
311 REG_WRITE(DSPCLK_GATE_D
, regs
->cdv
.saveDSPCLK_GATE_D
);
312 REG_WRITE(RAMCLK_GATE_D
, regs
->cdv
.saveRAMCLK_GATE_D
);
314 /* BIOS does below anyway */
315 REG_WRITE(DPIO_CFG
, 0);
316 REG_WRITE(DPIO_CFG
, DPIO_MODE_SELECT_0
| DPIO_CMN_RESET_N
);
318 temp
= REG_READ(DPLL_A
);
319 if ((temp
& DPLL_SYNCLOCK_ENABLE
) == 0) {
320 REG_WRITE(DPLL_A
, temp
| DPLL_SYNCLOCK_ENABLE
);
324 temp
= REG_READ(DPLL_B
);
325 if ((temp
& DPLL_SYNCLOCK_ENABLE
) == 0) {
326 REG_WRITE(DPLL_B
, temp
| DPLL_SYNCLOCK_ENABLE
);
332 REG_WRITE(DSPFW1
, regs
->cdv
.saveDSPFW
[0]);
333 REG_WRITE(DSPFW2
, regs
->cdv
.saveDSPFW
[1]);
334 REG_WRITE(DSPFW3
, regs
->cdv
.saveDSPFW
[2]);
335 REG_WRITE(DSPFW4
, regs
->cdv
.saveDSPFW
[3]);
336 REG_WRITE(DSPFW5
, regs
->cdv
.saveDSPFW
[4]);
337 REG_WRITE(DSPFW6
, regs
->cdv
.saveDSPFW
[5]);
339 REG_WRITE(DSPARB
, regs
->cdv
.saveDSPARB
);
340 REG_WRITE(ADPA
, regs
->cdv
.saveADPA
);
342 REG_WRITE(BLC_PWM_CTL2
, regs
->saveBLC_PWM_CTL2
);
343 REG_WRITE(LVDS
, regs
->cdv
.saveLVDS
);
344 REG_WRITE(PFIT_CONTROL
, regs
->cdv
.savePFIT_CONTROL
);
345 REG_WRITE(PFIT_PGM_RATIOS
, regs
->cdv
.savePFIT_PGM_RATIOS
);
346 REG_WRITE(BLC_PWM_CTL
, regs
->saveBLC_PWM_CTL
);
347 REG_WRITE(PP_ON_DELAYS
, regs
->cdv
.savePP_ON_DELAYS
);
348 REG_WRITE(PP_OFF_DELAYS
, regs
->cdv
.savePP_OFF_DELAYS
);
349 REG_WRITE(PP_CYCLE
, regs
->cdv
.savePP_CYCLE
);
350 REG_WRITE(PP_CONTROL
, regs
->cdv
.savePP_CONTROL
);
352 REG_WRITE(VGACNTRL
, regs
->cdv
.saveVGACNTRL
);
354 REG_WRITE(PSB_INT_ENABLE_R
, regs
->cdv
.saveIER
);
355 REG_WRITE(PSB_INT_MASK_R
, regs
->cdv
.saveIMR
);
357 /* Fix arbitration bug */
358 CDV_MSG_WRITE32(3, 0x30, 0x08027108);
360 drm_mode_config_reset(dev
);
362 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
)
363 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
365 /* Resume the modeset for every activated CRTC */
366 drm_helper_resume_force_mode(dev
);
370 static int cdv_power_down(struct drm_device
*dev
)
372 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
373 u32 pwr_cnt
, pwr_mask
, pwr_sts
;
376 pwr_cnt
= inl(dev_priv
->apm_base
+ PSB_APM_CMD
);
377 pwr_cnt
&= ~PSB_PWRGT_GFX_MASK
;
378 pwr_cnt
|= PSB_PWRGT_GFX_OFF
;
379 pwr_mask
= PSB_PWRGT_GFX_MASK
;
381 outl(pwr_cnt
, dev_priv
->apm_base
+ PSB_APM_CMD
);
384 pwr_sts
= inl(dev_priv
->apm_base
+ PSB_APM_STS
);
385 if ((pwr_sts
& pwr_mask
) == PSB_PWRGT_GFX_D3
)
392 static int cdv_power_up(struct drm_device
*dev
)
394 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
395 u32 pwr_cnt
, pwr_mask
, pwr_sts
;
398 pwr_cnt
= inl(dev_priv
->apm_base
+ PSB_APM_CMD
);
399 pwr_cnt
&= ~PSB_PWRGT_GFX_MASK
;
400 pwr_cnt
|= PSB_PWRGT_GFX_ON
;
401 pwr_mask
= PSB_PWRGT_GFX_MASK
;
403 outl(pwr_cnt
, dev_priv
->apm_base
+ PSB_APM_CMD
);
406 pwr_sts
= inl(dev_priv
->apm_base
+ PSB_APM_STS
);
407 if ((pwr_sts
& pwr_mask
) == PSB_PWRGT_GFX_D0
)
414 /* FIXME ? - shared with Poulsbo */
415 static void cdv_get_core_freq(struct drm_device
*dev
)
418 struct pci_dev
*pci_root
= pci_get_bus_and_slot(0, 0);
419 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
421 pci_write_config_dword(pci_root
, 0xD0, 0xD0050300);
422 pci_read_config_dword(pci_root
, 0xD4, &clock
);
423 pci_dev_put(pci_root
);
425 switch (clock
& 0x07) {
427 dev_priv
->core_freq
= 100;
430 dev_priv
->core_freq
= 133;
433 dev_priv
->core_freq
= 150;
436 dev_priv
->core_freq
= 178;
439 dev_priv
->core_freq
= 200;
444 dev_priv
->core_freq
= 266;
446 dev_priv
->core_freq
= 0;
450 static int cdv_chip_setup(struct drm_device
*dev
)
452 cdv_get_core_freq(dev
);
453 gma_intel_opregion_init(dev
);
454 psb_intel_init_bios(dev
);
458 /* CDV is much like Poulsbo but has MID like SGX offsets and PM */
460 const struct psb_ops cdv_chip_ops
= {
461 .name
= "GMA3600/3650",
465 .sgx_offset
= MRST_SGX_OFFSET
,
466 .chip_setup
= cdv_chip_setup
,
468 .crtc_helper
= &cdv_intel_helper_funcs
,
469 .crtc_funcs
= &cdv_intel_crtc_funcs
,
471 .output_init
= cdv_output_init
,
473 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
474 .backlight_init
= cdv_backlight_init
,
477 .init_pm
= cdv_init_pm
,
478 .save_regs
= cdv_save_display_registers
,
479 .restore_regs
= cdv_restore_display_registers
,
480 .power_down
= cdv_power_down
,
481 .power_up
= cdv_power_up
,