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Merge tag 'nfs-for-4.5-2' of git://git.linux-nfs.org/projects/trondmy/linux-nfs
[deliverable/linux.git] / drivers / gpu / drm / gma500 / cdv_intel_display.c
1 /*
2 * Copyright © 2006-2011 Intel Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc.,
15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
16 *
17 * Authors:
18 * Eric Anholt <eric@anholt.net>
19 */
20
21 #include <linux/i2c.h>
22
23 #include <drm/drmP.h>
24 #include "framebuffer.h"
25 #include "psb_drv.h"
26 #include "psb_intel_drv.h"
27 #include "psb_intel_reg.h"
28 #include "gma_display.h"
29 #include "power.h"
30 #include "cdv_device.h"
31
32 static bool cdv_intel_find_dp_pll(const struct gma_limit_t *limit,
33 struct drm_crtc *crtc, int target,
34 int refclk, struct gma_clock_t *best_clock);
35
36
37 #define CDV_LIMIT_SINGLE_LVDS_96 0
38 #define CDV_LIMIT_SINGLE_LVDS_100 1
39 #define CDV_LIMIT_DAC_HDMI_27 2
40 #define CDV_LIMIT_DAC_HDMI_96 3
41 #define CDV_LIMIT_DP_27 4
42 #define CDV_LIMIT_DP_100 5
43
44 static const struct gma_limit_t cdv_intel_limits[] = {
45 { /* CDV_SINGLE_LVDS_96MHz */
46 .dot = {.min = 20000, .max = 115500},
47 .vco = {.min = 1800000, .max = 3600000},
48 .n = {.min = 2, .max = 6},
49 .m = {.min = 60, .max = 160},
50 .m1 = {.min = 0, .max = 0},
51 .m2 = {.min = 58, .max = 158},
52 .p = {.min = 28, .max = 140},
53 .p1 = {.min = 2, .max = 10},
54 .p2 = {.dot_limit = 200000, .p2_slow = 14, .p2_fast = 14},
55 .find_pll = gma_find_best_pll,
56 },
57 { /* CDV_SINGLE_LVDS_100MHz */
58 .dot = {.min = 20000, .max = 115500},
59 .vco = {.min = 1800000, .max = 3600000},
60 .n = {.min = 2, .max = 6},
61 .m = {.min = 60, .max = 160},
62 .m1 = {.min = 0, .max = 0},
63 .m2 = {.min = 58, .max = 158},
64 .p = {.min = 28, .max = 140},
65 .p1 = {.min = 2, .max = 10},
66 /* The single-channel range is 25-112Mhz, and dual-channel
67 * is 80-224Mhz. Prefer single channel as much as possible.
68 */
69 .p2 = {.dot_limit = 200000, .p2_slow = 14, .p2_fast = 14},
70 .find_pll = gma_find_best_pll,
71 },
72 { /* CDV_DAC_HDMI_27MHz */
73 .dot = {.min = 20000, .max = 400000},
74 .vco = {.min = 1809000, .max = 3564000},
75 .n = {.min = 1, .max = 1},
76 .m = {.min = 67, .max = 132},
77 .m1 = {.min = 0, .max = 0},
78 .m2 = {.min = 65, .max = 130},
79 .p = {.min = 5, .max = 90},
80 .p1 = {.min = 1, .max = 9},
81 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5},
82 .find_pll = gma_find_best_pll,
83 },
84 { /* CDV_DAC_HDMI_96MHz */
85 .dot = {.min = 20000, .max = 400000},
86 .vco = {.min = 1800000, .max = 3600000},
87 .n = {.min = 2, .max = 6},
88 .m = {.min = 60, .max = 160},
89 .m1 = {.min = 0, .max = 0},
90 .m2 = {.min = 58, .max = 158},
91 .p = {.min = 5, .max = 100},
92 .p1 = {.min = 1, .max = 10},
93 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5},
94 .find_pll = gma_find_best_pll,
95 },
96 { /* CDV_DP_27MHz */
97 .dot = {.min = 160000, .max = 272000},
98 .vco = {.min = 1809000, .max = 3564000},
99 .n = {.min = 1, .max = 1},
100 .m = {.min = 67, .max = 132},
101 .m1 = {.min = 0, .max = 0},
102 .m2 = {.min = 65, .max = 130},
103 .p = {.min = 5, .max = 90},
104 .p1 = {.min = 1, .max = 9},
105 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 10},
106 .find_pll = cdv_intel_find_dp_pll,
107 },
108 { /* CDV_DP_100MHz */
109 .dot = {.min = 160000, .max = 272000},
110 .vco = {.min = 1800000, .max = 3600000},
111 .n = {.min = 2, .max = 6},
112 .m = {.min = 60, .max = 164},
113 .m1 = {.min = 0, .max = 0},
114 .m2 = {.min = 58, .max = 162},
115 .p = {.min = 5, .max = 100},
116 .p1 = {.min = 1, .max = 10},
117 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 10},
118 .find_pll = cdv_intel_find_dp_pll,
119 }
120 };
121
122 #define _wait_for(COND, MS, W) ({ \
123 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
124 int ret__ = 0; \
125 while (!(COND)) { \
126 if (time_after(jiffies, timeout__)) { \
127 ret__ = -ETIMEDOUT; \
128 break; \
129 } \
130 if (W && !in_dbg_master()) \
131 msleep(W); \
132 } \
133 ret__; \
134 })
135
136 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
137
138
139 int cdv_sb_read(struct drm_device *dev, u32 reg, u32 *val)
140 {
141 int ret;
142
143 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
144 if (ret) {
145 DRM_ERROR("timeout waiting for SB to idle before read\n");
146 return ret;
147 }
148
149 REG_WRITE(SB_ADDR, reg);
150 REG_WRITE(SB_PCKT,
151 SET_FIELD(SB_OPCODE_READ, SB_OPCODE) |
152 SET_FIELD(SB_DEST_DPLL, SB_DEST) |
153 SET_FIELD(0xf, SB_BYTE_ENABLE));
154
155 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
156 if (ret) {
157 DRM_ERROR("timeout waiting for SB to idle after read\n");
158 return ret;
159 }
160
161 *val = REG_READ(SB_DATA);
162
163 return 0;
164 }
165
166 int cdv_sb_write(struct drm_device *dev, u32 reg, u32 val)
167 {
168 int ret;
169 static bool dpio_debug = true;
170 u32 temp;
171
172 if (dpio_debug) {
173 if (cdv_sb_read(dev, reg, &temp) == 0)
174 DRM_DEBUG_KMS("0x%08x: 0x%08x (before)\n", reg, temp);
175 DRM_DEBUG_KMS("0x%08x: 0x%08x\n", reg, val);
176 }
177
178 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
179 if (ret) {
180 DRM_ERROR("timeout waiting for SB to idle before write\n");
181 return ret;
182 }
183
184 REG_WRITE(SB_ADDR, reg);
185 REG_WRITE(SB_DATA, val);
186 REG_WRITE(SB_PCKT,
187 SET_FIELD(SB_OPCODE_WRITE, SB_OPCODE) |
188 SET_FIELD(SB_DEST_DPLL, SB_DEST) |
189 SET_FIELD(0xf, SB_BYTE_ENABLE));
190
191 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
192 if (ret) {
193 DRM_ERROR("timeout waiting for SB to idle after write\n");
194 return ret;
195 }
196
197 if (dpio_debug) {
198 if (cdv_sb_read(dev, reg, &temp) == 0)
199 DRM_DEBUG_KMS("0x%08x: 0x%08x (after)\n", reg, temp);
200 }
201
202 return 0;
203 }
204
205 /* Reset the DPIO configuration register. The BIOS does this at every
206 * mode set.
207 */
208 void cdv_sb_reset(struct drm_device *dev)
209 {
210
211 REG_WRITE(DPIO_CFG, 0);
212 REG_READ(DPIO_CFG);
213 REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N);
214 }
215
216 /* Unlike most Intel display engines, on Cedarview the DPLL registers
217 * are behind this sideband bus. They must be programmed while the
218 * DPLL reference clock is on in the DPLL control register, but before
219 * the DPLL is enabled in the DPLL control register.
220 */
221 static int
222 cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc,
223 struct gma_clock_t *clock, bool is_lvds, u32 ddi_select)
224 {
225 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
226 int pipe = gma_crtc->pipe;
227 u32 m, n_vco, p;
228 int ret = 0;
229 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
230 int ref_sfr = (pipe == 0) ? SB_REF_DPLLA : SB_REF_DPLLB;
231 u32 ref_value;
232 u32 lane_reg, lane_value;
233
234 cdv_sb_reset(dev);
235
236 REG_WRITE(dpll_reg, DPLL_SYNCLOCK_ENABLE | DPLL_VGA_MODE_DIS);
237
238 udelay(100);
239
240 /* Follow the BIOS and write the REF/SFR Register. Hardcoded value */
241 ref_value = 0x68A701;
242
243 cdv_sb_write(dev, SB_REF_SFR(pipe), ref_value);
244
245 /* We don't know what the other fields of these regs are, so
246 * leave them in place.
247 */
248 /*
249 * The BIT 14:13 of 0x8010/0x8030 is used to select the ref clk
250 * for the pipe A/B. Display spec 1.06 has wrong definition.
251 * Correct definition is like below:
252 *
253 * refclka mean use clock from same PLL
254 *
255 * if DPLLA sets 01 and DPLLB sets 01, they use clock from their pll
256 *
257 * if DPLLA sets 01 and DPLLB sets 02, both use clk from DPLLA
258 *
259 */
260 ret = cdv_sb_read(dev, ref_sfr, &ref_value);
261 if (ret)
262 return ret;
263 ref_value &= ~(REF_CLK_MASK);
264
265 /* use DPLL_A for pipeB on CRT/HDMI */
266 if (pipe == 1 && !is_lvds && !(ddi_select & DP_MASK)) {
267 DRM_DEBUG_KMS("use DPLLA for pipe B\n");
268 ref_value |= REF_CLK_DPLLA;
269 } else {
270 DRM_DEBUG_KMS("use their DPLL for pipe A/B\n");
271 ref_value |= REF_CLK_DPLL;
272 }
273 ret = cdv_sb_write(dev, ref_sfr, ref_value);
274 if (ret)
275 return ret;
276
277 ret = cdv_sb_read(dev, SB_M(pipe), &m);
278 if (ret)
279 return ret;
280 m &= ~SB_M_DIVIDER_MASK;
281 m |= ((clock->m2) << SB_M_DIVIDER_SHIFT);
282 ret = cdv_sb_write(dev, SB_M(pipe), m);
283 if (ret)
284 return ret;
285
286 ret = cdv_sb_read(dev, SB_N_VCO(pipe), &n_vco);
287 if (ret)
288 return ret;
289
290 /* Follow the BIOS to program the N_DIVIDER REG */
291 n_vco &= 0xFFFF;
292 n_vco |= 0x107;
293 n_vco &= ~(SB_N_VCO_SEL_MASK |
294 SB_N_DIVIDER_MASK |
295 SB_N_CB_TUNE_MASK);
296
297 n_vco |= ((clock->n) << SB_N_DIVIDER_SHIFT);
298
299 if (clock->vco < 2250000) {
300 n_vco |= (2 << SB_N_CB_TUNE_SHIFT);
301 n_vco |= (0 << SB_N_VCO_SEL_SHIFT);
302 } else if (clock->vco < 2750000) {
303 n_vco |= (1 << SB_N_CB_TUNE_SHIFT);
304 n_vco |= (1 << SB_N_VCO_SEL_SHIFT);
305 } else if (clock->vco < 3300000) {
306 n_vco |= (0 << SB_N_CB_TUNE_SHIFT);
307 n_vco |= (2 << SB_N_VCO_SEL_SHIFT);
308 } else {
309 n_vco |= (0 << SB_N_CB_TUNE_SHIFT);
310 n_vco |= (3 << SB_N_VCO_SEL_SHIFT);
311 }
312
313 ret = cdv_sb_write(dev, SB_N_VCO(pipe), n_vco);
314 if (ret)
315 return ret;
316
317 ret = cdv_sb_read(dev, SB_P(pipe), &p);
318 if (ret)
319 return ret;
320 p &= ~(SB_P2_DIVIDER_MASK | SB_P1_DIVIDER_MASK);
321 p |= SET_FIELD(clock->p1, SB_P1_DIVIDER);
322 switch (clock->p2) {
323 case 5:
324 p |= SET_FIELD(SB_P2_5, SB_P2_DIVIDER);
325 break;
326 case 10:
327 p |= SET_FIELD(SB_P2_10, SB_P2_DIVIDER);
328 break;
329 case 14:
330 p |= SET_FIELD(SB_P2_14, SB_P2_DIVIDER);
331 break;
332 case 7:
333 p |= SET_FIELD(SB_P2_7, SB_P2_DIVIDER);
334 break;
335 default:
336 DRM_ERROR("Bad P2 clock: %d\n", clock->p2);
337 return -EINVAL;
338 }
339 ret = cdv_sb_write(dev, SB_P(pipe), p);
340 if (ret)
341 return ret;
342
343 if (ddi_select) {
344 if ((ddi_select & DDI_MASK) == DDI0_SELECT) {
345 lane_reg = PSB_LANE0;
346 cdv_sb_read(dev, lane_reg, &lane_value);
347 lane_value &= ~(LANE_PLL_MASK);
348 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
349 cdv_sb_write(dev, lane_reg, lane_value);
350
351 lane_reg = PSB_LANE1;
352 cdv_sb_read(dev, lane_reg, &lane_value);
353 lane_value &= ~(LANE_PLL_MASK);
354 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
355 cdv_sb_write(dev, lane_reg, lane_value);
356 } else {
357 lane_reg = PSB_LANE2;
358 cdv_sb_read(dev, lane_reg, &lane_value);
359 lane_value &= ~(LANE_PLL_MASK);
360 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
361 cdv_sb_write(dev, lane_reg, lane_value);
362
363 lane_reg = PSB_LANE3;
364 cdv_sb_read(dev, lane_reg, &lane_value);
365 lane_value &= ~(LANE_PLL_MASK);
366 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
367 cdv_sb_write(dev, lane_reg, lane_value);
368 }
369 }
370 return 0;
371 }
372
373 static const struct gma_limit_t *cdv_intel_limit(struct drm_crtc *crtc,
374 int refclk)
375 {
376 const struct gma_limit_t *limit;
377 if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
378 /*
379 * Now only single-channel LVDS is supported on CDV. If it is
380 * incorrect, please add the dual-channel LVDS.
381 */
382 if (refclk == 96000)
383 limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_96];
384 else
385 limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_100];
386 } else if (gma_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
387 gma_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
388 if (refclk == 27000)
389 limit = &cdv_intel_limits[CDV_LIMIT_DP_27];
390 else
391 limit = &cdv_intel_limits[CDV_LIMIT_DP_100];
392 } else {
393 if (refclk == 27000)
394 limit = &cdv_intel_limits[CDV_LIMIT_DAC_HDMI_27];
395 else
396 limit = &cdv_intel_limits[CDV_LIMIT_DAC_HDMI_96];
397 }
398 return limit;
399 }
400
401 /* m1 is reserved as 0 in CDV, n is a ring counter */
402 static void cdv_intel_clock(int refclk, struct gma_clock_t *clock)
403 {
404 clock->m = clock->m2 + 2;
405 clock->p = clock->p1 * clock->p2;
406 clock->vco = (refclk * clock->m) / clock->n;
407 clock->dot = clock->vco / clock->p;
408 }
409
410 static bool cdv_intel_find_dp_pll(const struct gma_limit_t *limit,
411 struct drm_crtc *crtc, int target,
412 int refclk,
413 struct gma_clock_t *best_clock)
414 {
415 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
416 struct gma_clock_t clock;
417
418 switch (refclk) {
419 case 27000:
420 if (target < 200000) {
421 clock.p1 = 2;
422 clock.p2 = 10;
423 clock.n = 1;
424 clock.m1 = 0;
425 clock.m2 = 118;
426 } else {
427 clock.p1 = 1;
428 clock.p2 = 10;
429 clock.n = 1;
430 clock.m1 = 0;
431 clock.m2 = 98;
432 }
433 break;
434
435 case 100000:
436 if (target < 200000) {
437 clock.p1 = 2;
438 clock.p2 = 10;
439 clock.n = 5;
440 clock.m1 = 0;
441 clock.m2 = 160;
442 } else {
443 clock.p1 = 1;
444 clock.p2 = 10;
445 clock.n = 5;
446 clock.m1 = 0;
447 clock.m2 = 133;
448 }
449 break;
450
451 default:
452 return false;
453 }
454
455 gma_crtc->clock_funcs->clock(refclk, &clock);
456 memcpy(best_clock, &clock, sizeof(struct gma_clock_t));
457 return true;
458 }
459
460 #define FIFO_PIPEA (1 << 0)
461 #define FIFO_PIPEB (1 << 1)
462
463 static bool cdv_intel_pipe_enabled(struct drm_device *dev, int pipe)
464 {
465 struct drm_crtc *crtc;
466 struct drm_psb_private *dev_priv = dev->dev_private;
467 struct gma_crtc *gma_crtc = NULL;
468
469 crtc = dev_priv->pipe_to_crtc_mapping[pipe];
470 gma_crtc = to_gma_crtc(crtc);
471
472 if (crtc->primary->fb == NULL || !gma_crtc->active)
473 return false;
474 return true;
475 }
476
477 void cdv_disable_sr(struct drm_device *dev)
478 {
479 if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) {
480
481 /* Disable self-refresh before adjust WM */
482 REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN));
483 REG_READ(FW_BLC_SELF);
484
485 gma_wait_for_vblank(dev);
486
487 /* Cedarview workaround to write ovelay plane, which force to leave
488 * MAX_FIFO state.
489 */
490 REG_WRITE(OV_OVADD, 0/*dev_priv->ovl_offset*/);
491 REG_READ(OV_OVADD);
492
493 gma_wait_for_vblank(dev);
494 }
495
496 }
497
498 void cdv_update_wm(struct drm_device *dev, struct drm_crtc *crtc)
499 {
500 struct drm_psb_private *dev_priv = dev->dev_private;
501 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
502
503 /* Is only one pipe enabled? */
504 if (cdv_intel_pipe_enabled(dev, 0) ^ cdv_intel_pipe_enabled(dev, 1)) {
505 u32 fw;
506
507 fw = REG_READ(DSPFW1);
508 fw &= ~DSP_FIFO_SR_WM_MASK;
509 fw |= (0x7e << DSP_FIFO_SR_WM_SHIFT);
510 fw &= ~CURSOR_B_FIFO_WM_MASK;
511 fw |= (0x4 << CURSOR_B_FIFO_WM_SHIFT);
512 REG_WRITE(DSPFW1, fw);
513
514 fw = REG_READ(DSPFW2);
515 fw &= ~CURSOR_A_FIFO_WM_MASK;
516 fw |= (0x6 << CURSOR_A_FIFO_WM_SHIFT);
517 fw &= ~DSP_PLANE_C_FIFO_WM_MASK;
518 fw |= (0x8 << DSP_PLANE_C_FIFO_WM_SHIFT);
519 REG_WRITE(DSPFW2, fw);
520
521 REG_WRITE(DSPFW3, 0x36000000);
522
523 /* ignore FW4 */
524
525 /* Is pipe b lvds ? */
526 if (gma_crtc->pipe == 1 &&
527 gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
528 REG_WRITE(DSPFW5, 0x00040330);
529 } else {
530 fw = (3 << DSP_PLANE_B_FIFO_WM1_SHIFT) |
531 (4 << DSP_PLANE_A_FIFO_WM1_SHIFT) |
532 (3 << CURSOR_B_FIFO_WM1_SHIFT) |
533 (4 << CURSOR_FIFO_SR_WM1_SHIFT);
534 REG_WRITE(DSPFW5, fw);
535 }
536
537 REG_WRITE(DSPFW6, 0x10);
538
539 gma_wait_for_vblank(dev);
540
541 /* enable self-refresh for single pipe active */
542 REG_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
543 REG_READ(FW_BLC_SELF);
544 gma_wait_for_vblank(dev);
545
546 } else {
547
548 /* HW team suggested values... */
549 REG_WRITE(DSPFW1, 0x3f880808);
550 REG_WRITE(DSPFW2, 0x0b020202);
551 REG_WRITE(DSPFW3, 0x24000000);
552 REG_WRITE(DSPFW4, 0x08030202);
553 REG_WRITE(DSPFW5, 0x01010101);
554 REG_WRITE(DSPFW6, 0x1d0);
555
556 gma_wait_for_vblank(dev);
557
558 dev_priv->ops->disable_sr(dev);
559 }
560 }
561
562 /**
563 * Return the pipe currently connected to the panel fitter,
564 * or -1 if the panel fitter is not present or not in use
565 */
566 static int cdv_intel_panel_fitter_pipe(struct drm_device *dev)
567 {
568 u32 pfit_control;
569
570 pfit_control = REG_READ(PFIT_CONTROL);
571
572 /* See if the panel fitter is in use */
573 if ((pfit_control & PFIT_ENABLE) == 0)
574 return -1;
575 return (pfit_control >> 29) & 0x3;
576 }
577
578 static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
579 struct drm_display_mode *mode,
580 struct drm_display_mode *adjusted_mode,
581 int x, int y,
582 struct drm_framebuffer *old_fb)
583 {
584 struct drm_device *dev = crtc->dev;
585 struct drm_psb_private *dev_priv = dev->dev_private;
586 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
587 int pipe = gma_crtc->pipe;
588 const struct psb_offset *map = &dev_priv->regmap[pipe];
589 int refclk;
590 struct gma_clock_t clock;
591 u32 dpll = 0, dspcntr, pipeconf;
592 bool ok;
593 bool is_crt = false, is_lvds = false, is_tv = false;
594 bool is_hdmi = false, is_dp = false;
595 struct drm_mode_config *mode_config = &dev->mode_config;
596 struct drm_connector *connector;
597 const struct gma_limit_t *limit;
598 u32 ddi_select = 0;
599 bool is_edp = false;
600
601 list_for_each_entry(connector, &mode_config->connector_list, head) {
602 struct gma_encoder *gma_encoder =
603 gma_attached_encoder(connector);
604
605 if (!connector->encoder
606 || connector->encoder->crtc != crtc)
607 continue;
608
609 ddi_select = gma_encoder->ddi_select;
610 switch (gma_encoder->type) {
611 case INTEL_OUTPUT_LVDS:
612 is_lvds = true;
613 break;
614 case INTEL_OUTPUT_TVOUT:
615 is_tv = true;
616 break;
617 case INTEL_OUTPUT_ANALOG:
618 is_crt = true;
619 break;
620 case INTEL_OUTPUT_HDMI:
621 is_hdmi = true;
622 break;
623 case INTEL_OUTPUT_DISPLAYPORT:
624 is_dp = true;
625 break;
626 case INTEL_OUTPUT_EDP:
627 is_edp = true;
628 break;
629 default:
630 DRM_ERROR("invalid output type.\n");
631 return 0;
632 }
633 }
634
635 if (dev_priv->dplla_96mhz)
636 /* low-end sku, 96/100 mhz */
637 refclk = 96000;
638 else
639 /* high-end sku, 27/100 mhz */
640 refclk = 27000;
641 if (is_dp || is_edp) {
642 /*
643 * Based on the spec the low-end SKU has only CRT/LVDS. So it is
644 * unnecessary to consider it for DP/eDP.
645 * On the high-end SKU, it will use the 27/100M reference clk
646 * for DP/eDP. When using SSC clock, the ref clk is 100MHz.Otherwise
647 * it will be 27MHz. From the VBIOS code it seems that the pipe A choose
648 * 27MHz for DP/eDP while the Pipe B chooses the 100MHz.
649 */
650 if (pipe == 0)
651 refclk = 27000;
652 else
653 refclk = 100000;
654 }
655
656 if (is_lvds && dev_priv->lvds_use_ssc) {
657 refclk = dev_priv->lvds_ssc_freq * 1000;
658 DRM_DEBUG_KMS("Use SSC reference clock %d Mhz\n", dev_priv->lvds_ssc_freq);
659 }
660
661 drm_mode_debug_printmodeline(adjusted_mode);
662
663 limit = gma_crtc->clock_funcs->limit(crtc, refclk);
664
665 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk,
666 &clock);
667 if (!ok) {
668 DRM_ERROR("Couldn't find PLL settings for mode! target: %d, actual: %d",
669 adjusted_mode->clock, clock.dot);
670 return 0;
671 }
672
673 dpll = DPLL_VGA_MODE_DIS;
674 if (is_tv) {
675 /* XXX: just matching BIOS for now */
676 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
677 dpll |= 3;
678 }
679 /* dpll |= PLL_REF_INPUT_DREFCLK; */
680
681 if (is_dp || is_edp) {
682 cdv_intel_dp_set_m_n(crtc, mode, adjusted_mode);
683 } else {
684 REG_WRITE(PIPE_GMCH_DATA_M(pipe), 0);
685 REG_WRITE(PIPE_GMCH_DATA_N(pipe), 0);
686 REG_WRITE(PIPE_DP_LINK_M(pipe), 0);
687 REG_WRITE(PIPE_DP_LINK_N(pipe), 0);
688 }
689
690 dpll |= DPLL_SYNCLOCK_ENABLE;
691 /* if (is_lvds)
692 dpll |= DPLLB_MODE_LVDS;
693 else
694 dpll |= DPLLB_MODE_DAC_SERIAL; */
695 /* dpll |= (2 << 11); */
696
697 /* setup pipeconf */
698 pipeconf = REG_READ(map->conf);
699
700 pipeconf &= ~(PIPE_BPC_MASK);
701 if (is_edp) {
702 switch (dev_priv->edp.bpp) {
703 case 24:
704 pipeconf |= PIPE_8BPC;
705 break;
706 case 18:
707 pipeconf |= PIPE_6BPC;
708 break;
709 case 30:
710 pipeconf |= PIPE_10BPC;
711 break;
712 default:
713 pipeconf |= PIPE_8BPC;
714 break;
715 }
716 } else if (is_lvds) {
717 /* the BPC will be 6 if it is 18-bit LVDS panel */
718 if ((REG_READ(LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
719 pipeconf |= PIPE_8BPC;
720 else
721 pipeconf |= PIPE_6BPC;
722 } else
723 pipeconf |= PIPE_8BPC;
724
725 /* Set up the display plane register */
726 dspcntr = DISPPLANE_GAMMA_ENABLE;
727
728 if (pipe == 0)
729 dspcntr |= DISPPLANE_SEL_PIPE_A;
730 else
731 dspcntr |= DISPPLANE_SEL_PIPE_B;
732
733 dspcntr |= DISPLAY_PLANE_ENABLE;
734 pipeconf |= PIPEACONF_ENABLE;
735
736 REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE);
737 REG_READ(map->dpll);
738
739 cdv_dpll_set_clock_cdv(dev, crtc, &clock, is_lvds, ddi_select);
740
741 udelay(150);
742
743
744 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
745 * This is an exception to the general rule that mode_set doesn't turn
746 * things on.
747 */
748 if (is_lvds) {
749 u32 lvds = REG_READ(LVDS);
750
751 lvds |=
752 LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP |
753 LVDS_PIPEB_SELECT;
754 /* Set the B0-B3 data pairs corresponding to
755 * whether we're going to
756 * set the DPLLs for dual-channel mode or not.
757 */
758 if (clock.p2 == 7)
759 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
760 else
761 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
762
763 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
764 * appropriately here, but we need to look more
765 * thoroughly into how panels behave in the two modes.
766 */
767
768 REG_WRITE(LVDS, lvds);
769 REG_READ(LVDS);
770 }
771
772 dpll |= DPLL_VCO_ENABLE;
773
774 /* Disable the panel fitter if it was on our pipe */
775 if (cdv_intel_panel_fitter_pipe(dev) == pipe)
776 REG_WRITE(PFIT_CONTROL, 0);
777
778 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
779 drm_mode_debug_printmodeline(mode);
780
781 REG_WRITE(map->dpll,
782 (REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE);
783 REG_READ(map->dpll);
784 /* Wait for the clocks to stabilize. */
785 udelay(150); /* 42 usec w/o calibration, 110 with. rounded up. */
786
787 if (!(REG_READ(map->dpll) & DPLL_LOCK)) {
788 dev_err(dev->dev, "Failed to get DPLL lock\n");
789 return -EBUSY;
790 }
791
792 {
793 int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
794 REG_WRITE(map->dpll_md, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
795 }
796
797 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |
798 ((adjusted_mode->crtc_htotal - 1) << 16));
799 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |
800 ((adjusted_mode->crtc_hblank_end - 1) << 16));
801 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |
802 ((adjusted_mode->crtc_hsync_end - 1) << 16));
803 REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |
804 ((adjusted_mode->crtc_vtotal - 1) << 16));
805 REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |
806 ((adjusted_mode->crtc_vblank_end - 1) << 16));
807 REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |
808 ((adjusted_mode->crtc_vsync_end - 1) << 16));
809 /* pipesrc and dspsize control the size that is scaled from,
810 * which should always be the user's requested size.
811 */
812 REG_WRITE(map->size,
813 ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
814 REG_WRITE(map->pos, 0);
815 REG_WRITE(map->src,
816 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
817 REG_WRITE(map->conf, pipeconf);
818 REG_READ(map->conf);
819
820 gma_wait_for_vblank(dev);
821
822 REG_WRITE(map->cntr, dspcntr);
823
824 /* Flush the plane changes */
825 {
826 const struct drm_crtc_helper_funcs *crtc_funcs =
827 crtc->helper_private;
828 crtc_funcs->mode_set_base(crtc, x, y, old_fb);
829 }
830
831 gma_wait_for_vblank(dev);
832
833 return 0;
834 }
835
836 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
837
838 /* FIXME: why are we using this, should it be cdv_ in this tree ? */
839
840 static void i8xx_clock(int refclk, struct gma_clock_t *clock)
841 {
842 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
843 clock->p = clock->p1 * clock->p2;
844 clock->vco = refclk * clock->m / (clock->n + 2);
845 clock->dot = clock->vco / clock->p;
846 }
847
848 /* Returns the clock of the currently programmed mode of the given pipe. */
849 static int cdv_intel_crtc_clock_get(struct drm_device *dev,
850 struct drm_crtc *crtc)
851 {
852 struct drm_psb_private *dev_priv = dev->dev_private;
853 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
854 int pipe = gma_crtc->pipe;
855 const struct psb_offset *map = &dev_priv->regmap[pipe];
856 u32 dpll;
857 u32 fp;
858 struct gma_clock_t clock;
859 bool is_lvds;
860 struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
861
862 if (gma_power_begin(dev, false)) {
863 dpll = REG_READ(map->dpll);
864 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
865 fp = REG_READ(map->fp0);
866 else
867 fp = REG_READ(map->fp1);
868 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);
869 gma_power_end(dev);
870 } else {
871 dpll = p->dpll;
872 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
873 fp = p->fp0;
874 else
875 fp = p->fp1;
876
877 is_lvds = (pipe == 1) &&
878 (dev_priv->regs.psb.saveLVDS & LVDS_PORT_EN);
879 }
880
881 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
882 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
883 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
884
885 if (is_lvds) {
886 clock.p1 =
887 ffs((dpll &
888 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
889 DPLL_FPA01_P1_POST_DIV_SHIFT);
890 if (clock.p1 == 0) {
891 clock.p1 = 4;
892 dev_err(dev->dev, "PLL %d\n", dpll);
893 }
894 clock.p2 = 14;
895
896 if ((dpll & PLL_REF_INPUT_MASK) ==
897 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
898 /* XXX: might not be 66MHz */
899 i8xx_clock(66000, &clock);
900 } else
901 i8xx_clock(48000, &clock);
902 } else {
903 if (dpll & PLL_P1_DIVIDE_BY_TWO)
904 clock.p1 = 2;
905 else {
906 clock.p1 =
907 ((dpll &
908 DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
909 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
910 }
911 if (dpll & PLL_P2_DIVIDE_BY_4)
912 clock.p2 = 4;
913 else
914 clock.p2 = 2;
915
916 i8xx_clock(48000, &clock);
917 }
918
919 /* XXX: It would be nice to validate the clocks, but we can't reuse
920 * i830PllIsValid() because it relies on the xf86_config connector
921 * configuration being accurate, which it isn't necessarily.
922 */
923
924 return clock.dot;
925 }
926
927 /** Returns the currently programmed mode of the given pipe. */
928 struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev,
929 struct drm_crtc *crtc)
930 {
931 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
932 int pipe = gma_crtc->pipe;
933 struct drm_psb_private *dev_priv = dev->dev_private;
934 struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
935 const struct psb_offset *map = &dev_priv->regmap[pipe];
936 struct drm_display_mode *mode;
937 int htot;
938 int hsync;
939 int vtot;
940 int vsync;
941
942 if (gma_power_begin(dev, false)) {
943 htot = REG_READ(map->htotal);
944 hsync = REG_READ(map->hsync);
945 vtot = REG_READ(map->vtotal);
946 vsync = REG_READ(map->vsync);
947 gma_power_end(dev);
948 } else {
949 htot = p->htotal;
950 hsync = p->hsync;
951 vtot = p->vtotal;
952 vsync = p->vsync;
953 }
954
955 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
956 if (!mode)
957 return NULL;
958
959 mode->clock = cdv_intel_crtc_clock_get(dev, crtc);
960 mode->hdisplay = (htot & 0xffff) + 1;
961 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
962 mode->hsync_start = (hsync & 0xffff) + 1;
963 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
964 mode->vdisplay = (vtot & 0xffff) + 1;
965 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
966 mode->vsync_start = (vsync & 0xffff) + 1;
967 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
968
969 drm_mode_set_name(mode);
970 drm_mode_set_crtcinfo(mode, 0);
971
972 return mode;
973 }
974
975 const struct drm_crtc_helper_funcs cdv_intel_helper_funcs = {
976 .dpms = gma_crtc_dpms,
977 .mode_fixup = gma_crtc_mode_fixup,
978 .mode_set = cdv_intel_crtc_mode_set,
979 .mode_set_base = gma_pipe_set_base,
980 .prepare = gma_crtc_prepare,
981 .commit = gma_crtc_commit,
982 .disable = gma_crtc_disable,
983 };
984
985 const struct drm_crtc_funcs cdv_intel_crtc_funcs = {
986 .cursor_set = gma_crtc_cursor_set,
987 .cursor_move = gma_crtc_cursor_move,
988 .gamma_set = gma_crtc_gamma_set,
989 .set_config = gma_crtc_set_config,
990 .destroy = gma_crtc_destroy,
991 };
992
993 const struct gma_clock_funcs cdv_clock_funcs = {
994 .clock = cdv_intel_clock,
995 .limit = cdv_intel_limit,
996 .pll_is_valid = gma_pll_is_valid,
997 };
Linux kernel - Deliverables
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