2 * Copyright © 2006-2011 Intel Corporation
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc.,
15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 * Eric Anholt <eric@anholt.net>
21 #include <linux/i2c.h>
22 #include <linux/pm_runtime.h>
25 #include "framebuffer.h"
27 #include "psb_intel_drv.h"
28 #include "psb_intel_reg.h"
29 #include "psb_intel_display.h"
31 #include "cdv_device.h"
34 struct cdv_intel_range_t
{
38 struct cdv_intel_p2_t
{
43 struct cdv_intel_clock_t
{
55 #define INTEL_P2_NUM 2
57 struct cdv_intel_limit_t
{
58 struct cdv_intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
59 struct cdv_intel_p2_t p2
;
60 bool (*find_pll
)(const struct cdv_intel_limit_t
*, struct drm_crtc
*,
61 int, int, struct cdv_intel_clock_t
*);
64 static bool cdv_intel_find_best_PLL(const struct cdv_intel_limit_t
*limit
,
65 struct drm_crtc
*crtc
, int target
, int refclk
,
66 struct cdv_intel_clock_t
*best_clock
);
67 static bool cdv_intel_find_dp_pll(const struct cdv_intel_limit_t
*limit
, struct drm_crtc
*crtc
, int target
,
69 struct cdv_intel_clock_t
*best_clock
);
71 #define CDV_LIMIT_SINGLE_LVDS_96 0
72 #define CDV_LIMIT_SINGLE_LVDS_100 1
73 #define CDV_LIMIT_DAC_HDMI_27 2
74 #define CDV_LIMIT_DAC_HDMI_96 3
75 #define CDV_LIMIT_DP_27 4
76 #define CDV_LIMIT_DP_100 5
78 static const struct cdv_intel_limit_t cdv_intel_limits
[] = {
79 { /* CDV_SINGLE_LVDS_96MHz */
80 .dot
= {.min
= 20000, .max
= 115500},
81 .vco
= {.min
= 1800000, .max
= 3600000},
82 .n
= {.min
= 2, .max
= 6},
83 .m
= {.min
= 60, .max
= 160},
84 .m1
= {.min
= 0, .max
= 0},
85 .m2
= {.min
= 58, .max
= 158},
86 .p
= {.min
= 28, .max
= 140},
87 .p1
= {.min
= 2, .max
= 10},
88 .p2
= {.dot_limit
= 200000,
89 .p2_slow
= 14, .p2_fast
= 14},
90 .find_pll
= cdv_intel_find_best_PLL
,
92 { /* CDV_SINGLE_LVDS_100MHz */
93 .dot
= {.min
= 20000, .max
= 115500},
94 .vco
= {.min
= 1800000, .max
= 3600000},
95 .n
= {.min
= 2, .max
= 6},
96 .m
= {.min
= 60, .max
= 160},
97 .m1
= {.min
= 0, .max
= 0},
98 .m2
= {.min
= 58, .max
= 158},
99 .p
= {.min
= 28, .max
= 140},
100 .p1
= {.min
= 2, .max
= 10},
101 /* The single-channel range is 25-112Mhz, and dual-channel
102 * is 80-224Mhz. Prefer single channel as much as possible.
104 .p2
= {.dot_limit
= 200000, .p2_slow
= 14, .p2_fast
= 14},
105 .find_pll
= cdv_intel_find_best_PLL
,
107 { /* CDV_DAC_HDMI_27MHz */
108 .dot
= {.min
= 20000, .max
= 400000},
109 .vco
= {.min
= 1809000, .max
= 3564000},
110 .n
= {.min
= 1, .max
= 1},
111 .m
= {.min
= 67, .max
= 132},
112 .m1
= {.min
= 0, .max
= 0},
113 .m2
= {.min
= 65, .max
= 130},
114 .p
= {.min
= 5, .max
= 90},
115 .p1
= {.min
= 1, .max
= 9},
116 .p2
= {.dot_limit
= 225000, .p2_slow
= 10, .p2_fast
= 5},
117 .find_pll
= cdv_intel_find_best_PLL
,
119 { /* CDV_DAC_HDMI_96MHz */
120 .dot
= {.min
= 20000, .max
= 400000},
121 .vco
= {.min
= 1800000, .max
= 3600000},
122 .n
= {.min
= 2, .max
= 6},
123 .m
= {.min
= 60, .max
= 160},
124 .m1
= {.min
= 0, .max
= 0},
125 .m2
= {.min
= 58, .max
= 158},
126 .p
= {.min
= 5, .max
= 100},
127 .p1
= {.min
= 1, .max
= 10},
128 .p2
= {.dot_limit
= 225000, .p2_slow
= 10, .p2_fast
= 5},
129 .find_pll
= cdv_intel_find_best_PLL
,
132 .dot
= {.min
= 160000, .max
= 272000},
133 .vco
= {.min
= 1809000, .max
= 3564000},
134 .n
= {.min
= 1, .max
= 1},
135 .m
= {.min
= 67, .max
= 132},
136 .m1
= {.min
= 0, .max
= 0},
137 .m2
= {.min
= 65, .max
= 130},
138 .p
= {.min
= 5, .max
= 90},
139 .p1
= {.min
= 1, .max
= 9},
140 .p2
= {.dot_limit
= 225000, .p2_slow
= 10, .p2_fast
= 10},
141 .find_pll
= cdv_intel_find_dp_pll
,
143 { /* CDV_DP_100MHz */
144 .dot
= {.min
= 160000, .max
= 272000},
145 .vco
= {.min
= 1800000, .max
= 3600000},
146 .n
= {.min
= 2, .max
= 6},
147 .m
= {.min
= 60, .max
= 164},
148 .m1
= {.min
= 0, .max
= 0},
149 .m2
= {.min
= 58, .max
= 162},
150 .p
= {.min
= 5, .max
= 100},
151 .p1
= {.min
= 1, .max
= 10},
152 .p2
= {.dot_limit
= 225000, .p2_slow
= 10, .p2_fast
= 10},
153 .find_pll
= cdv_intel_find_dp_pll
,
157 #define _wait_for(COND, MS, W) ({ \
158 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
161 if (time_after(jiffies, timeout__)) { \
162 ret__ = -ETIMEDOUT; \
165 if (W && !in_dbg_master()) \
171 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
174 int cdv_sb_read(struct drm_device
*dev
, u32 reg
, u32
*val
)
178 ret
= wait_for((REG_READ(SB_PCKT
) & SB_BUSY
) == 0, 1000);
180 DRM_ERROR("timeout waiting for SB to idle before read\n");
184 REG_WRITE(SB_ADDR
, reg
);
186 SET_FIELD(SB_OPCODE_READ
, SB_OPCODE
) |
187 SET_FIELD(SB_DEST_DPLL
, SB_DEST
) |
188 SET_FIELD(0xf, SB_BYTE_ENABLE
));
190 ret
= wait_for((REG_READ(SB_PCKT
) & SB_BUSY
) == 0, 1000);
192 DRM_ERROR("timeout waiting for SB to idle after read\n");
196 *val
= REG_READ(SB_DATA
);
201 int cdv_sb_write(struct drm_device
*dev
, u32 reg
, u32 val
)
204 static bool dpio_debug
= true;
208 if (cdv_sb_read(dev
, reg
, &temp
) == 0)
209 DRM_DEBUG_KMS("0x%08x: 0x%08x (before)\n", reg
, temp
);
210 DRM_DEBUG_KMS("0x%08x: 0x%08x\n", reg
, val
);
213 ret
= wait_for((REG_READ(SB_PCKT
) & SB_BUSY
) == 0, 1000);
215 DRM_ERROR("timeout waiting for SB to idle before write\n");
219 REG_WRITE(SB_ADDR
, reg
);
220 REG_WRITE(SB_DATA
, val
);
222 SET_FIELD(SB_OPCODE_WRITE
, SB_OPCODE
) |
223 SET_FIELD(SB_DEST_DPLL
, SB_DEST
) |
224 SET_FIELD(0xf, SB_BYTE_ENABLE
));
226 ret
= wait_for((REG_READ(SB_PCKT
) & SB_BUSY
) == 0, 1000);
228 DRM_ERROR("timeout waiting for SB to idle after write\n");
233 if (cdv_sb_read(dev
, reg
, &temp
) == 0)
234 DRM_DEBUG_KMS("0x%08x: 0x%08x (after)\n", reg
, temp
);
240 /* Reset the DPIO configuration register. The BIOS does this at every
243 void cdv_sb_reset(struct drm_device
*dev
)
246 REG_WRITE(DPIO_CFG
, 0);
248 REG_WRITE(DPIO_CFG
, DPIO_MODE_SELECT_0
| DPIO_CMN_RESET_N
);
251 /* Unlike most Intel display engines, on Cedarview the DPLL registers
252 * are behind this sideband bus. They must be programmed while the
253 * DPLL reference clock is on in the DPLL control register, but before
254 * the DPLL is enabled in the DPLL control register.
257 cdv_dpll_set_clock_cdv(struct drm_device
*dev
, struct drm_crtc
*crtc
,
258 struct cdv_intel_clock_t
*clock
, bool is_lvds
, u32 ddi_select
)
260 struct psb_intel_crtc
*psb_crtc
= to_psb_intel_crtc(crtc
);
261 int pipe
= psb_crtc
->pipe
;
264 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
265 int ref_sfr
= (pipe
== 0) ? SB_REF_DPLLA
: SB_REF_DPLLB
;
267 u32 lane_reg
, lane_value
;
271 REG_WRITE(dpll_reg
, DPLL_SYNCLOCK_ENABLE
| DPLL_VGA_MODE_DIS
);
275 /* Follow the BIOS and write the REF/SFR Register. Hardcoded value */
276 ref_value
= 0x68A701;
278 cdv_sb_write(dev
, SB_REF_SFR(pipe
), ref_value
);
280 /* We don't know what the other fields of these regs are, so
281 * leave them in place.
284 * The BIT 14:13 of 0x8010/0x8030 is used to select the ref clk
285 * for the pipe A/B. Display spec 1.06 has wrong definition.
286 * Correct definition is like below:
288 * refclka mean use clock from same PLL
290 * if DPLLA sets 01 and DPLLB sets 01, they use clock from their pll
292 * if DPLLA sets 01 and DPLLB sets 02, both use clk from DPLLA
295 ret
= cdv_sb_read(dev
, ref_sfr
, &ref_value
);
298 ref_value
&= ~(REF_CLK_MASK
);
300 /* use DPLL_A for pipeB on CRT/HDMI */
301 if (pipe
== 1 && !is_lvds
&& !(ddi_select
& DP_MASK
)) {
302 DRM_DEBUG_KMS("use DPLLA for pipe B\n");
303 ref_value
|= REF_CLK_DPLLA
;
305 DRM_DEBUG_KMS("use their DPLL for pipe A/B\n");
306 ref_value
|= REF_CLK_DPLL
;
308 ret
= cdv_sb_write(dev
, ref_sfr
, ref_value
);
312 ret
= cdv_sb_read(dev
, SB_M(pipe
), &m
);
315 m
&= ~SB_M_DIVIDER_MASK
;
316 m
|= ((clock
->m2
) << SB_M_DIVIDER_SHIFT
);
317 ret
= cdv_sb_write(dev
, SB_M(pipe
), m
);
321 ret
= cdv_sb_read(dev
, SB_N_VCO(pipe
), &n_vco
);
325 /* Follow the BIOS to program the N_DIVIDER REG */
328 n_vco
&= ~(SB_N_VCO_SEL_MASK
|
332 n_vco
|= ((clock
->n
) << SB_N_DIVIDER_SHIFT
);
334 if (clock
->vco
< 2250000) {
335 n_vco
|= (2 << SB_N_CB_TUNE_SHIFT
);
336 n_vco
|= (0 << SB_N_VCO_SEL_SHIFT
);
337 } else if (clock
->vco
< 2750000) {
338 n_vco
|= (1 << SB_N_CB_TUNE_SHIFT
);
339 n_vco
|= (1 << SB_N_VCO_SEL_SHIFT
);
340 } else if (clock
->vco
< 3300000) {
341 n_vco
|= (0 << SB_N_CB_TUNE_SHIFT
);
342 n_vco
|= (2 << SB_N_VCO_SEL_SHIFT
);
344 n_vco
|= (0 << SB_N_CB_TUNE_SHIFT
);
345 n_vco
|= (3 << SB_N_VCO_SEL_SHIFT
);
348 ret
= cdv_sb_write(dev
, SB_N_VCO(pipe
), n_vco
);
352 ret
= cdv_sb_read(dev
, SB_P(pipe
), &p
);
355 p
&= ~(SB_P2_DIVIDER_MASK
| SB_P1_DIVIDER_MASK
);
356 p
|= SET_FIELD(clock
->p1
, SB_P1_DIVIDER
);
359 p
|= SET_FIELD(SB_P2_5
, SB_P2_DIVIDER
);
362 p
|= SET_FIELD(SB_P2_10
, SB_P2_DIVIDER
);
365 p
|= SET_FIELD(SB_P2_14
, SB_P2_DIVIDER
);
368 p
|= SET_FIELD(SB_P2_7
, SB_P2_DIVIDER
);
371 DRM_ERROR("Bad P2 clock: %d\n", clock
->p2
);
374 ret
= cdv_sb_write(dev
, SB_P(pipe
), p
);
379 if ((ddi_select
& DDI_MASK
) == DDI0_SELECT
) {
380 lane_reg
= PSB_LANE0
;
381 cdv_sb_read(dev
, lane_reg
, &lane_value
);
382 lane_value
&= ~(LANE_PLL_MASK
);
383 lane_value
|= LANE_PLL_ENABLE
| LANE_PLL_PIPE(pipe
);
384 cdv_sb_write(dev
, lane_reg
, lane_value
);
386 lane_reg
= PSB_LANE1
;
387 cdv_sb_read(dev
, lane_reg
, &lane_value
);
388 lane_value
&= ~(LANE_PLL_MASK
);
389 lane_value
|= LANE_PLL_ENABLE
| LANE_PLL_PIPE(pipe
);
390 cdv_sb_write(dev
, lane_reg
, lane_value
);
392 lane_reg
= PSB_LANE2
;
393 cdv_sb_read(dev
, lane_reg
, &lane_value
);
394 lane_value
&= ~(LANE_PLL_MASK
);
395 lane_value
|= LANE_PLL_ENABLE
| LANE_PLL_PIPE(pipe
);
396 cdv_sb_write(dev
, lane_reg
, lane_value
);
398 lane_reg
= PSB_LANE3
;
399 cdv_sb_read(dev
, lane_reg
, &lane_value
);
400 lane_value
&= ~(LANE_PLL_MASK
);
401 lane_value
|= LANE_PLL_ENABLE
| LANE_PLL_PIPE(pipe
);
402 cdv_sb_write(dev
, lane_reg
, lane_value
);
409 * Returns whether any encoder on the specified pipe is of the specified type
411 static bool cdv_intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
413 struct drm_device
*dev
= crtc
->dev
;
414 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
415 struct drm_connector
*l_entry
;
417 list_for_each_entry(l_entry
, &mode_config
->connector_list
, head
) {
418 if (l_entry
->encoder
&& l_entry
->encoder
->crtc
== crtc
) {
419 struct psb_intel_encoder
*psb_intel_encoder
=
420 psb_intel_attached_encoder(l_entry
);
421 if (psb_intel_encoder
->type
== type
)
428 static const struct cdv_intel_limit_t
*cdv_intel_limit(struct drm_crtc
*crtc
,
431 const struct cdv_intel_limit_t
*limit
;
432 if (cdv_intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
434 * Now only single-channel LVDS is supported on CDV. If it is
435 * incorrect, please add the dual-channel LVDS.
438 limit
= &cdv_intel_limits
[CDV_LIMIT_SINGLE_LVDS_96
];
440 limit
= &cdv_intel_limits
[CDV_LIMIT_SINGLE_LVDS_100
];
441 } else if (psb_intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
442 psb_intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
)) {
444 limit
= &cdv_intel_limits
[CDV_LIMIT_DP_27
];
446 limit
= &cdv_intel_limits
[CDV_LIMIT_DP_100
];
449 limit
= &cdv_intel_limits
[CDV_LIMIT_DAC_HDMI_27
];
451 limit
= &cdv_intel_limits
[CDV_LIMIT_DAC_HDMI_96
];
456 /* m1 is reserved as 0 in CDV, n is a ring counter */
457 static void cdv_intel_clock(struct drm_device
*dev
,
458 int refclk
, struct cdv_intel_clock_t
*clock
)
460 clock
->m
= clock
->m2
+ 2;
461 clock
->p
= clock
->p1
* clock
->p2
;
462 clock
->vco
= (refclk
* clock
->m
) / clock
->n
;
463 clock
->dot
= clock
->vco
/ clock
->p
;
467 #define INTELPllInvalid(s) { /* ErrorF (s) */; return false; }
468 static bool cdv_intel_PLL_is_valid(struct drm_crtc
*crtc
,
469 const struct cdv_intel_limit_t
*limit
,
470 struct cdv_intel_clock_t
*clock
)
472 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
473 INTELPllInvalid("p1 out of range\n");
474 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
475 INTELPllInvalid("p out of range\n");
476 /* unnecessary to check the range of m(m1/M2)/n again */
477 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
478 INTELPllInvalid("vco out of range\n");
479 /* XXX: We may need to be checking "Dot clock"
480 * depending on the multiplier, connector, etc.,
481 * rather than just a single range.
483 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
484 INTELPllInvalid("dot out of range\n");
489 static bool cdv_intel_find_best_PLL(const struct cdv_intel_limit_t
*limit
,
490 struct drm_crtc
*crtc
, int target
, int refclk
,
491 struct cdv_intel_clock_t
*best_clock
)
493 struct drm_device
*dev
= crtc
->dev
;
494 struct cdv_intel_clock_t clock
;
498 if (cdv_intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
499 (REG_READ(LVDS
) & LVDS_PORT_EN
) != 0) {
501 * For LVDS, if the panel is on, just rely on its current
502 * settings for dual-channel. We haven't figured out how to
503 * reliably set up different single/dual channel state, if we
506 if ((REG_READ(LVDS
) & LVDS_CLKB_POWER_MASK
) ==
508 clock
.p2
= limit
->p2
.p2_fast
;
510 clock
.p2
= limit
->p2
.p2_slow
;
512 if (target
< limit
->p2
.dot_limit
)
513 clock
.p2
= limit
->p2
.p2_slow
;
515 clock
.p2
= limit
->p2
.p2_fast
;
518 memset(best_clock
, 0, sizeof(*best_clock
));
520 /* m1 is reserved as 0 in CDV, n is a ring counter.
521 So skip the m1 loop */
522 for (clock
.n
= limit
->n
.min
; clock
.n
<= limit
->n
.max
; clock
.n
++) {
523 for (clock
.m2
= limit
->m2
.min
; clock
.m2
<= limit
->m2
.max
;
525 for (clock
.p1
= limit
->p1
.min
;
526 clock
.p1
<= limit
->p1
.max
;
530 cdv_intel_clock(dev
, refclk
, &clock
);
532 if (!cdv_intel_PLL_is_valid(crtc
,
536 this_err
= abs(clock
.dot
- target
);
537 if (this_err
< err
) {
545 return err
!= target
;
548 static bool cdv_intel_find_dp_pll(const struct cdv_intel_limit_t
*limit
, struct drm_crtc
*crtc
, int target
,
550 struct cdv_intel_clock_t
*best_clock
)
552 struct cdv_intel_clock_t clock
;
553 if (refclk
== 27000) {
554 if (target
< 200000) {
567 } else if (refclk
== 100000) {
568 if (target
< 200000) {
583 clock
.m
= clock
.m2
+ 2;
584 clock
.p
= clock
.p1
* clock
.p2
;
585 clock
.vco
= (refclk
* clock
.m
) / clock
.n
;
586 clock
.dot
= clock
.vco
/ clock
.p
;
587 memcpy(best_clock
, &clock
, sizeof(struct cdv_intel_clock_t
));
591 static int cdv_intel_pipe_set_base(struct drm_crtc
*crtc
,
592 int x
, int y
, struct drm_framebuffer
*old_fb
)
594 struct drm_device
*dev
= crtc
->dev
;
595 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
596 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
597 struct psb_framebuffer
*psbfb
= to_psb_fb(crtc
->fb
);
598 int pipe
= psb_intel_crtc
->pipe
;
599 const struct psb_offset
*map
= &dev_priv
->regmap
[pipe
];
600 unsigned long start
, offset
;
604 if (!gma_power_begin(dev
, true))
609 dev_err(dev
->dev
, "No FB bound\n");
610 goto psb_intel_pipe_cleaner
;
614 /* We are displaying this buffer, make sure it is actually loaded
616 ret
= psb_gtt_pin(psbfb
->gtt
);
618 goto psb_intel_pipe_set_base_exit
;
619 start
= psbfb
->gtt
->offset
;
620 offset
= y
* crtc
->fb
->pitches
[0] + x
* (crtc
->fb
->bits_per_pixel
/ 8);
622 REG_WRITE(map
->stride
, crtc
->fb
->pitches
[0]);
624 dspcntr
= REG_READ(map
->cntr
);
625 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
627 switch (crtc
->fb
->bits_per_pixel
) {
629 dspcntr
|= DISPPLANE_8BPP
;
632 if (crtc
->fb
->depth
== 15)
633 dspcntr
|= DISPPLANE_15_16BPP
;
635 dspcntr
|= DISPPLANE_16BPP
;
639 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
642 dev_err(dev
->dev
, "Unknown color depth\n");
644 goto psb_intel_pipe_set_base_exit
;
646 REG_WRITE(map
->cntr
, dspcntr
);
649 "Writing base %08lX %08lX %d %d\n", start
, offset
, x
, y
);
651 REG_WRITE(map
->base
, offset
);
653 REG_WRITE(map
->surf
, start
);
656 psb_intel_pipe_cleaner
:
657 /* If there was a previous display we can now unpin it */
659 psb_gtt_unpin(to_psb_fb(old_fb
)->gtt
);
661 psb_intel_pipe_set_base_exit
:
666 #define FIFO_PIPEA (1 << 0)
667 #define FIFO_PIPEB (1 << 1)
669 static bool cdv_intel_pipe_enabled(struct drm_device
*dev
, int pipe
)
671 struct drm_crtc
*crtc
;
672 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
673 struct psb_intel_crtc
*psb_intel_crtc
= NULL
;
675 crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
676 psb_intel_crtc
= to_psb_intel_crtc(crtc
);
678 if (crtc
->fb
== NULL
|| !psb_intel_crtc
->active
)
683 static bool cdv_intel_single_pipe_active (struct drm_device
*dev
)
685 uint32_t pipe_enabled
= 0;
687 if (cdv_intel_pipe_enabled(dev
, 0))
688 pipe_enabled
|= FIFO_PIPEA
;
690 if (cdv_intel_pipe_enabled(dev
, 1))
691 pipe_enabled
|= FIFO_PIPEB
;
694 DRM_DEBUG_KMS("pipe enabled %x\n", pipe_enabled
);
696 if (pipe_enabled
== FIFO_PIPEA
|| pipe_enabled
== FIFO_PIPEB
)
702 static bool is_pipeb_lvds(struct drm_device
*dev
, struct drm_crtc
*crtc
)
704 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
705 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
706 struct drm_connector
*connector
;
708 if (psb_intel_crtc
->pipe
!= 1)
711 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
712 struct psb_intel_encoder
*psb_intel_encoder
=
713 psb_intel_attached_encoder(connector
);
715 if (!connector
->encoder
716 || connector
->encoder
->crtc
!= crtc
)
719 if (psb_intel_encoder
->type
== INTEL_OUTPUT_LVDS
)
726 static void cdv_intel_disable_self_refresh (struct drm_device
*dev
)
728 if (REG_READ(FW_BLC_SELF
) & FW_BLC_SELF_EN
) {
730 /* Disable self-refresh before adjust WM */
731 REG_WRITE(FW_BLC_SELF
, (REG_READ(FW_BLC_SELF
) & ~FW_BLC_SELF_EN
));
732 REG_READ(FW_BLC_SELF
);
734 cdv_intel_wait_for_vblank(dev
);
736 /* Cedarview workaround to write ovelay plane, which force to leave
739 REG_WRITE(OV_OVADD
, 0/*dev_priv->ovl_offset*/);
742 cdv_intel_wait_for_vblank(dev
);
747 static void cdv_intel_update_watermark (struct drm_device
*dev
, struct drm_crtc
*crtc
)
750 if (cdv_intel_single_pipe_active(dev
)) {
753 fw
= REG_READ(DSPFW1
);
754 fw
&= ~DSP_FIFO_SR_WM_MASK
;
755 fw
|= (0x7e << DSP_FIFO_SR_WM_SHIFT
);
756 fw
&= ~CURSOR_B_FIFO_WM_MASK
;
757 fw
|= (0x4 << CURSOR_B_FIFO_WM_SHIFT
);
758 REG_WRITE(DSPFW1
, fw
);
760 fw
= REG_READ(DSPFW2
);
761 fw
&= ~CURSOR_A_FIFO_WM_MASK
;
762 fw
|= (0x6 << CURSOR_A_FIFO_WM_SHIFT
);
763 fw
&= ~DSP_PLANE_C_FIFO_WM_MASK
;
764 fw
|= (0x8 << DSP_PLANE_C_FIFO_WM_SHIFT
);
765 REG_WRITE(DSPFW2
, fw
);
767 REG_WRITE(DSPFW3
, 0x36000000);
771 if (is_pipeb_lvds(dev
, crtc
)) {
772 REG_WRITE(DSPFW5
, 0x00040330);
774 fw
= (3 << DSP_PLANE_B_FIFO_WM1_SHIFT
) |
775 (4 << DSP_PLANE_A_FIFO_WM1_SHIFT
) |
776 (3 << CURSOR_B_FIFO_WM1_SHIFT
) |
777 (4 << CURSOR_FIFO_SR_WM1_SHIFT
);
778 REG_WRITE(DSPFW5
, fw
);
781 REG_WRITE(DSPFW6
, 0x10);
783 cdv_intel_wait_for_vblank(dev
);
785 /* enable self-refresh for single pipe active */
786 REG_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
787 REG_READ(FW_BLC_SELF
);
788 cdv_intel_wait_for_vblank(dev
);
792 /* HW team suggested values... */
793 REG_WRITE(DSPFW1
, 0x3f880808);
794 REG_WRITE(DSPFW2
, 0x0b020202);
795 REG_WRITE(DSPFW3
, 0x24000000);
796 REG_WRITE(DSPFW4
, 0x08030202);
797 REG_WRITE(DSPFW5
, 0x01010101);
798 REG_WRITE(DSPFW6
, 0x1d0);
800 cdv_intel_wait_for_vblank(dev
);
802 cdv_intel_disable_self_refresh(dev
);
807 /** Loads the palette/gamma unit for the CRTC with the prepared values */
808 static void cdv_intel_crtc_load_lut(struct drm_crtc
*crtc
)
810 struct drm_device
*dev
= crtc
->dev
;
811 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
812 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
813 int palreg
= PALETTE_A
;
816 /* The clocks have to be on to load the palette. */
820 switch (psb_intel_crtc
->pipe
) {
830 dev_err(dev
->dev
, "Illegal Pipe Number.\n");
834 if (gma_power_begin(dev
, false)) {
835 for (i
= 0; i
< 256; i
++) {
836 REG_WRITE(palreg
+ 4 * i
,
837 ((psb_intel_crtc
->lut_r
[i
] +
838 psb_intel_crtc
->lut_adj
[i
]) << 16) |
839 ((psb_intel_crtc
->lut_g
[i
] +
840 psb_intel_crtc
->lut_adj
[i
]) << 8) |
841 (psb_intel_crtc
->lut_b
[i
] +
842 psb_intel_crtc
->lut_adj
[i
]));
846 for (i
= 0; i
< 256; i
++) {
847 dev_priv
->regs
.pipe
[0].palette
[i
] =
848 ((psb_intel_crtc
->lut_r
[i
] +
849 psb_intel_crtc
->lut_adj
[i
]) << 16) |
850 ((psb_intel_crtc
->lut_g
[i
] +
851 psb_intel_crtc
->lut_adj
[i
]) << 8) |
852 (psb_intel_crtc
->lut_b
[i
] +
853 psb_intel_crtc
->lut_adj
[i
]);
860 * Sets the power management mode of the pipe and plane.
862 * This code should probably grow support for turning the cursor off and back
863 * on appropriately at the same time as we're turning the pipe off/on.
865 static void cdv_intel_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
867 struct drm_device
*dev
= crtc
->dev
;
868 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
869 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
870 int pipe
= psb_intel_crtc
->pipe
;
871 const struct psb_offset
*map
= &dev_priv
->regmap
[pipe
];
874 /* XXX: When our outputs are all unaware of DPMS modes other than off
875 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
877 cdv_intel_disable_self_refresh(dev
);
880 case DRM_MODE_DPMS_ON
:
881 case DRM_MODE_DPMS_STANDBY
:
882 case DRM_MODE_DPMS_SUSPEND
:
883 if (psb_intel_crtc
->active
)
886 psb_intel_crtc
->active
= true;
888 /* Enable the DPLL */
889 temp
= REG_READ(map
->dpll
);
890 if ((temp
& DPLL_VCO_ENABLE
) == 0) {
891 REG_WRITE(map
->dpll
, temp
);
893 /* Wait for the clocks to stabilize. */
895 REG_WRITE(map
->dpll
, temp
| DPLL_VCO_ENABLE
);
897 /* Wait for the clocks to stabilize. */
899 REG_WRITE(map
->dpll
, temp
| DPLL_VCO_ENABLE
);
901 /* Wait for the clocks to stabilize. */
905 /* Jim Bish - switch plan and pipe per scott */
906 /* Enable the plane */
907 temp
= REG_READ(map
->cntr
);
908 if ((temp
& DISPLAY_PLANE_ENABLE
) == 0) {
910 temp
| DISPLAY_PLANE_ENABLE
);
911 /* Flush the plane changes */
912 REG_WRITE(map
->base
, REG_READ(map
->base
));
917 /* Enable the pipe */
918 temp
= REG_READ(map
->conf
);
919 if ((temp
& PIPEACONF_ENABLE
) == 0)
920 REG_WRITE(map
->conf
, temp
| PIPEACONF_ENABLE
);
922 temp
= REG_READ(map
->status
);
924 temp
|= PIPE_FIFO_UNDERRUN
;
925 REG_WRITE(map
->status
, temp
);
926 REG_READ(map
->status
);
928 cdv_intel_crtc_load_lut(crtc
);
930 /* Give the overlay scaler a chance to enable
931 * if it's on this pipe */
932 /* psb_intel_crtc_dpms_video(crtc, true); TODO */
934 case DRM_MODE_DPMS_OFF
:
935 if (!psb_intel_crtc
->active
)
938 psb_intel_crtc
->active
= false;
940 /* Give the overlay scaler a chance to disable
941 * if it's on this pipe */
942 /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */
944 /* Disable the VGA plane that we never use */
945 REG_WRITE(VGACNTRL
, VGA_DISP_DISABLE
);
947 /* Jim Bish - changed pipe/plane here as well. */
949 drm_vblank_off(dev
, pipe
);
950 /* Wait for vblank for the disable to take effect */
951 cdv_intel_wait_for_vblank(dev
);
953 /* Next, disable display pipes */
954 temp
= REG_READ(map
->conf
);
955 if ((temp
& PIPEACONF_ENABLE
) != 0) {
956 REG_WRITE(map
->conf
, temp
& ~PIPEACONF_ENABLE
);
960 /* Wait for vblank for the disable to take effect. */
961 cdv_intel_wait_for_vblank(dev
);
965 /* Disable display plane */
966 temp
= REG_READ(map
->cntr
);
967 if ((temp
& DISPLAY_PLANE_ENABLE
) != 0) {
969 temp
& ~DISPLAY_PLANE_ENABLE
);
970 /* Flush the plane changes */
971 REG_WRITE(map
->base
, REG_READ(map
->base
));
975 temp
= REG_READ(map
->dpll
);
976 if ((temp
& DPLL_VCO_ENABLE
) != 0) {
977 REG_WRITE(map
->dpll
, temp
& ~DPLL_VCO_ENABLE
);
981 /* Wait for the clocks to turn off. */
985 cdv_intel_update_watermark(dev
, crtc
);
986 /*Set FIFO Watermarks*/
987 REG_WRITE(DSPARB
, 0x3F3E);
990 static void cdv_intel_crtc_prepare(struct drm_crtc
*crtc
)
992 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
993 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_OFF
);
996 static void cdv_intel_crtc_commit(struct drm_crtc
*crtc
)
998 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
999 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
1002 static bool cdv_intel_crtc_mode_fixup(struct drm_crtc
*crtc
,
1003 const struct drm_display_mode
*mode
,
1004 struct drm_display_mode
*adjusted_mode
)
1011 * Return the pipe currently connected to the panel fitter,
1012 * or -1 if the panel fitter is not present or not in use
1014 static int cdv_intel_panel_fitter_pipe(struct drm_device
*dev
)
1018 pfit_control
= REG_READ(PFIT_CONTROL
);
1020 /* See if the panel fitter is in use */
1021 if ((pfit_control
& PFIT_ENABLE
) == 0)
1023 return (pfit_control
>> 29) & 0x3;
1026 static int cdv_intel_crtc_mode_set(struct drm_crtc
*crtc
,
1027 struct drm_display_mode
*mode
,
1028 struct drm_display_mode
*adjusted_mode
,
1030 struct drm_framebuffer
*old_fb
)
1032 struct drm_device
*dev
= crtc
->dev
;
1033 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
1034 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
1035 int pipe
= psb_intel_crtc
->pipe
;
1036 const struct psb_offset
*map
= &dev_priv
->regmap
[pipe
];
1038 struct cdv_intel_clock_t clock
;
1039 u32 dpll
= 0, dspcntr
, pipeconf
;
1041 bool is_crt
= false, is_lvds
= false, is_tv
= false;
1042 bool is_hdmi
= false, is_dp
= false;
1043 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
1044 struct drm_connector
*connector
;
1045 const struct cdv_intel_limit_t
*limit
;
1047 bool is_edp
= false;
1049 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
1050 struct psb_intel_encoder
*psb_intel_encoder
=
1051 psb_intel_attached_encoder(connector
);
1053 if (!connector
->encoder
1054 || connector
->encoder
->crtc
!= crtc
)
1057 ddi_select
= psb_intel_encoder
->ddi_select
;
1058 switch (psb_intel_encoder
->type
) {
1059 case INTEL_OUTPUT_LVDS
:
1062 case INTEL_OUTPUT_TVOUT
:
1065 case INTEL_OUTPUT_ANALOG
:
1068 case INTEL_OUTPUT_HDMI
:
1071 case INTEL_OUTPUT_DISPLAYPORT
:
1074 case INTEL_OUTPUT_EDP
:
1078 DRM_ERROR("invalid output type.\n");
1083 if (dev_priv
->dplla_96mhz
)
1084 /* low-end sku, 96/100 mhz */
1087 /* high-end sku, 27/100 mhz */
1089 if (is_dp
|| is_edp
) {
1091 * Based on the spec the low-end SKU has only CRT/LVDS. So it is
1092 * unnecessary to consider it for DP/eDP.
1093 * On the high-end SKU, it will use the 27/100M reference clk
1094 * for DP/eDP. When using SSC clock, the ref clk is 100MHz.Otherwise
1095 * it will be 27MHz. From the VBIOS code it seems that the pipe A choose
1096 * 27MHz for DP/eDP while the Pipe B chooses the 100MHz.
1104 if (is_lvds
&& dev_priv
->lvds_use_ssc
) {
1105 refclk
= dev_priv
->lvds_ssc_freq
* 1000;
1106 DRM_DEBUG_KMS("Use SSC reference clock %d Mhz\n", dev_priv
->lvds_ssc_freq
);
1109 drm_mode_debug_printmodeline(adjusted_mode
);
1111 limit
= cdv_intel_limit(crtc
, refclk
);
1113 ok
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
,
1116 dev_err(dev
->dev
, "Couldn't find PLL settings for mode!\n");
1120 dpll
= DPLL_VGA_MODE_DIS
;
1122 /* XXX: just matching BIOS for now */
1123 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
1126 /* dpll |= PLL_REF_INPUT_DREFCLK; */
1128 if (is_dp
|| is_edp
) {
1129 cdv_intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
1131 REG_WRITE(PIPE_GMCH_DATA_M(pipe
), 0);
1132 REG_WRITE(PIPE_GMCH_DATA_N(pipe
), 0);
1133 REG_WRITE(PIPE_DP_LINK_M(pipe
), 0);
1134 REG_WRITE(PIPE_DP_LINK_N(pipe
), 0);
1137 dpll
|= DPLL_SYNCLOCK_ENABLE
;
1139 dpll |= DPLLB_MODE_LVDS;
1141 dpll |= DPLLB_MODE_DAC_SERIAL; */
1142 /* dpll |= (2 << 11); */
1144 /* setup pipeconf */
1145 pipeconf
= REG_READ(map
->conf
);
1147 pipeconf
&= ~(PIPE_BPC_MASK
);
1149 switch (dev_priv
->edp
.bpp
) {
1151 pipeconf
|= PIPE_8BPC
;
1154 pipeconf
|= PIPE_6BPC
;
1157 pipeconf
|= PIPE_10BPC
;
1160 pipeconf
|= PIPE_8BPC
;
1163 } else if (is_lvds
) {
1164 /* the BPC will be 6 if it is 18-bit LVDS panel */
1165 if ((REG_READ(LVDS
) & LVDS_A3_POWER_MASK
) == LVDS_A3_POWER_UP
)
1166 pipeconf
|= PIPE_8BPC
;
1168 pipeconf
|= PIPE_6BPC
;
1170 pipeconf
|= PIPE_8BPC
;
1172 /* Set up the display plane register */
1173 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
1176 dspcntr
|= DISPPLANE_SEL_PIPE_A
;
1178 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
1180 dspcntr
|= DISPLAY_PLANE_ENABLE
;
1181 pipeconf
|= PIPEACONF_ENABLE
;
1183 REG_WRITE(map
->dpll
, dpll
| DPLL_VGA_MODE_DIS
| DPLL_SYNCLOCK_ENABLE
);
1184 REG_READ(map
->dpll
);
1186 cdv_dpll_set_clock_cdv(dev
, crtc
, &clock
, is_lvds
, ddi_select
);
1191 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
1192 * This is an exception to the general rule that mode_set doesn't turn
1196 u32 lvds
= REG_READ(LVDS
);
1199 LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
|
1201 /* Set the B0-B3 data pairs corresponding to
1202 * whether we're going to
1203 * set the DPLLs for dual-channel mode or not.
1206 lvds
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
1208 lvds
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
1210 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
1211 * appropriately here, but we need to look more
1212 * thoroughly into how panels behave in the two modes.
1215 REG_WRITE(LVDS
, lvds
);
1219 dpll
|= DPLL_VCO_ENABLE
;
1221 /* Disable the panel fitter if it was on our pipe */
1222 if (cdv_intel_panel_fitter_pipe(dev
) == pipe
)
1223 REG_WRITE(PFIT_CONTROL
, 0);
1225 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe
== 0 ? 'A' : 'B');
1226 drm_mode_debug_printmodeline(mode
);
1228 REG_WRITE(map
->dpll
,
1229 (REG_READ(map
->dpll
) & ~DPLL_LOCK
) | DPLL_VCO_ENABLE
);
1230 REG_READ(map
->dpll
);
1231 /* Wait for the clocks to stabilize. */
1232 udelay(150); /* 42 usec w/o calibration, 110 with. rounded up. */
1234 if (!(REG_READ(map
->dpll
) & DPLL_LOCK
)) {
1235 dev_err(dev
->dev
, "Failed to get DPLL lock\n");
1240 int sdvo_pixel_multiply
= adjusted_mode
->clock
/ mode
->clock
;
1241 REG_WRITE(map
->dpll_md
, (0 << DPLL_MD_UDI_DIVIDER_SHIFT
) | ((sdvo_pixel_multiply
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
));
1244 REG_WRITE(map
->htotal
, (adjusted_mode
->crtc_hdisplay
- 1) |
1245 ((adjusted_mode
->crtc_htotal
- 1) << 16));
1246 REG_WRITE(map
->hblank
, (adjusted_mode
->crtc_hblank_start
- 1) |
1247 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
1248 REG_WRITE(map
->hsync
, (adjusted_mode
->crtc_hsync_start
- 1) |
1249 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
1250 REG_WRITE(map
->vtotal
, (adjusted_mode
->crtc_vdisplay
- 1) |
1251 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
1252 REG_WRITE(map
->vblank
, (adjusted_mode
->crtc_vblank_start
- 1) |
1253 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
1254 REG_WRITE(map
->vsync
, (adjusted_mode
->crtc_vsync_start
- 1) |
1255 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
1256 /* pipesrc and dspsize control the size that is scaled from,
1257 * which should always be the user's requested size.
1259 REG_WRITE(map
->size
,
1260 ((mode
->vdisplay
- 1) << 16) | (mode
->hdisplay
- 1));
1261 REG_WRITE(map
->pos
, 0);
1263 ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
1264 REG_WRITE(map
->conf
, pipeconf
);
1265 REG_READ(map
->conf
);
1267 cdv_intel_wait_for_vblank(dev
);
1269 REG_WRITE(map
->cntr
, dspcntr
);
1271 /* Flush the plane changes */
1273 struct drm_crtc_helper_funcs
*crtc_funcs
=
1274 crtc
->helper_private
;
1275 crtc_funcs
->mode_set_base(crtc
, x
, y
, old_fb
);
1278 cdv_intel_wait_for_vblank(dev
);
1285 * Save HW states of giving crtc
1287 static void cdv_intel_crtc_save(struct drm_crtc
*crtc
)
1289 struct drm_device
*dev
= crtc
->dev
;
1290 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
1291 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
1292 struct psb_intel_crtc_state
*crtc_state
= psb_intel_crtc
->crtc_state
;
1293 const struct psb_offset
*map
= &dev_priv
->regmap
[psb_intel_crtc
->pipe
];
1294 uint32_t paletteReg
;
1298 dev_dbg(dev
->dev
, "No CRTC state found\n");
1302 crtc_state
->saveDSPCNTR
= REG_READ(map
->cntr
);
1303 crtc_state
->savePIPECONF
= REG_READ(map
->conf
);
1304 crtc_state
->savePIPESRC
= REG_READ(map
->src
);
1305 crtc_state
->saveFP0
= REG_READ(map
->fp0
);
1306 crtc_state
->saveFP1
= REG_READ(map
->fp1
);
1307 crtc_state
->saveDPLL
= REG_READ(map
->dpll
);
1308 crtc_state
->saveHTOTAL
= REG_READ(map
->htotal
);
1309 crtc_state
->saveHBLANK
= REG_READ(map
->hblank
);
1310 crtc_state
->saveHSYNC
= REG_READ(map
->hsync
);
1311 crtc_state
->saveVTOTAL
= REG_READ(map
->vtotal
);
1312 crtc_state
->saveVBLANK
= REG_READ(map
->vblank
);
1313 crtc_state
->saveVSYNC
= REG_READ(map
->vsync
);
1314 crtc_state
->saveDSPSTRIDE
= REG_READ(map
->stride
);
1316 /*NOTE: DSPSIZE DSPPOS only for psb*/
1317 crtc_state
->saveDSPSIZE
= REG_READ(map
->size
);
1318 crtc_state
->saveDSPPOS
= REG_READ(map
->pos
);
1320 crtc_state
->saveDSPBASE
= REG_READ(map
->base
);
1322 DRM_DEBUG("(%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n",
1323 crtc_state
->saveDSPCNTR
,
1324 crtc_state
->savePIPECONF
,
1325 crtc_state
->savePIPESRC
,
1326 crtc_state
->saveFP0
,
1327 crtc_state
->saveFP1
,
1328 crtc_state
->saveDPLL
,
1329 crtc_state
->saveHTOTAL
,
1330 crtc_state
->saveHBLANK
,
1331 crtc_state
->saveHSYNC
,
1332 crtc_state
->saveVTOTAL
,
1333 crtc_state
->saveVBLANK
,
1334 crtc_state
->saveVSYNC
,
1335 crtc_state
->saveDSPSTRIDE
,
1336 crtc_state
->saveDSPSIZE
,
1337 crtc_state
->saveDSPPOS
,
1338 crtc_state
->saveDSPBASE
1341 paletteReg
= map
->palette
;
1342 for (i
= 0; i
< 256; ++i
)
1343 crtc_state
->savePalette
[i
] = REG_READ(paletteReg
+ (i
<< 2));
1347 * Restore HW states of giving crtc
1349 static void cdv_intel_crtc_restore(struct drm_crtc
*crtc
)
1351 struct drm_device
*dev
= crtc
->dev
;
1352 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
1353 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
1354 struct psb_intel_crtc_state
*crtc_state
= psb_intel_crtc
->crtc_state
;
1355 const struct psb_offset
*map
= &dev_priv
->regmap
[psb_intel_crtc
->pipe
];
1356 uint32_t paletteReg
;
1360 dev_dbg(dev
->dev
, "No crtc state\n");
1365 "current:(%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n",
1366 REG_READ(map
->cntr
),
1367 REG_READ(map
->conf
),
1371 REG_READ(map
->dpll
),
1372 REG_READ(map
->htotal
),
1373 REG_READ(map
->hblank
),
1374 REG_READ(map
->hsync
),
1375 REG_READ(map
->vtotal
),
1376 REG_READ(map
->vblank
),
1377 REG_READ(map
->vsync
),
1378 REG_READ(map
->stride
),
1379 REG_READ(map
->size
),
1385 "saved: (%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n",
1386 crtc_state
->saveDSPCNTR
,
1387 crtc_state
->savePIPECONF
,
1388 crtc_state
->savePIPESRC
,
1389 crtc_state
->saveFP0
,
1390 crtc_state
->saveFP1
,
1391 crtc_state
->saveDPLL
,
1392 crtc_state
->saveHTOTAL
,
1393 crtc_state
->saveHBLANK
,
1394 crtc_state
->saveHSYNC
,
1395 crtc_state
->saveVTOTAL
,
1396 crtc_state
->saveVBLANK
,
1397 crtc_state
->saveVSYNC
,
1398 crtc_state
->saveDSPSTRIDE
,
1399 crtc_state
->saveDSPSIZE
,
1400 crtc_state
->saveDSPPOS
,
1401 crtc_state
->saveDSPBASE
1405 if (crtc_state
->saveDPLL
& DPLL_VCO_ENABLE
) {
1406 REG_WRITE(map
->dpll
,
1407 crtc_state
->saveDPLL
& ~DPLL_VCO_ENABLE
);
1408 REG_READ(map
->dpll
);
1409 DRM_DEBUG("write dpll: %x\n",
1410 REG_READ(map
->dpll
));
1414 REG_WRITE(map
->fp0
, crtc_state
->saveFP0
);
1417 REG_WRITE(map
->fp1
, crtc_state
->saveFP1
);
1420 REG_WRITE(map
->dpll
, crtc_state
->saveDPLL
);
1421 REG_READ(map
->dpll
);
1424 REG_WRITE(map
->htotal
, crtc_state
->saveHTOTAL
);
1425 REG_WRITE(map
->hblank
, crtc_state
->saveHBLANK
);
1426 REG_WRITE(map
->hsync
, crtc_state
->saveHSYNC
);
1427 REG_WRITE(map
->vtotal
, crtc_state
->saveVTOTAL
);
1428 REG_WRITE(map
->vblank
, crtc_state
->saveVBLANK
);
1429 REG_WRITE(map
->vsync
, crtc_state
->saveVSYNC
);
1430 REG_WRITE(map
->stride
, crtc_state
->saveDSPSTRIDE
);
1432 REG_WRITE(map
->size
, crtc_state
->saveDSPSIZE
);
1433 REG_WRITE(map
->pos
, crtc_state
->saveDSPPOS
);
1435 REG_WRITE(map
->src
, crtc_state
->savePIPESRC
);
1436 REG_WRITE(map
->base
, crtc_state
->saveDSPBASE
);
1437 REG_WRITE(map
->conf
, crtc_state
->savePIPECONF
);
1439 cdv_intel_wait_for_vblank(dev
);
1441 REG_WRITE(map
->cntr
, crtc_state
->saveDSPCNTR
);
1442 REG_WRITE(map
->base
, crtc_state
->saveDSPBASE
);
1444 cdv_intel_wait_for_vblank(dev
);
1446 paletteReg
= map
->palette
;
1447 for (i
= 0; i
< 256; ++i
)
1448 REG_WRITE(paletteReg
+ (i
<< 2), crtc_state
->savePalette
[i
]);
1451 static int cdv_intel_crtc_cursor_set(struct drm_crtc
*crtc
,
1452 struct drm_file
*file_priv
,
1454 uint32_t width
, uint32_t height
)
1456 struct drm_device
*dev
= crtc
->dev
;
1457 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
1458 int pipe
= psb_intel_crtc
->pipe
;
1459 uint32_t control
= (pipe
== 0) ? CURACNTR
: CURBCNTR
;
1460 uint32_t base
= (pipe
== 0) ? CURABASE
: CURBBASE
;
1463 struct gtt_range
*gt
;
1464 struct drm_gem_object
*obj
;
1467 /* if we want to turn of the cursor ignore width and height */
1469 /* turn off the cursor */
1470 temp
= CURSOR_MODE_DISABLE
;
1472 if (gma_power_begin(dev
, false)) {
1473 REG_WRITE(control
, temp
);
1478 /* unpin the old GEM object */
1479 if (psb_intel_crtc
->cursor_obj
) {
1480 gt
= container_of(psb_intel_crtc
->cursor_obj
,
1481 struct gtt_range
, gem
);
1483 drm_gem_object_unreference(psb_intel_crtc
->cursor_obj
);
1484 psb_intel_crtc
->cursor_obj
= NULL
;
1490 /* Currently we only support 64x64 cursors */
1491 if (width
!= 64 || height
!= 64) {
1492 dev_dbg(dev
->dev
, "we currently only support 64x64 cursors\n");
1496 obj
= drm_gem_object_lookup(dev
, file_priv
, handle
);
1500 if (obj
->size
< width
* height
* 4) {
1501 dev_dbg(dev
->dev
, "buffer is to small\n");
1506 gt
= container_of(obj
, struct gtt_range
, gem
);
1508 /* Pin the memory into the GTT */
1509 ret
= psb_gtt_pin(gt
);
1511 dev_err(dev
->dev
, "Can not pin down handle 0x%x\n", handle
);
1515 addr
= gt
->offset
; /* Or resource.start ??? */
1517 psb_intel_crtc
->cursor_addr
= addr
;
1520 /* set the pipe for the cursor */
1521 temp
|= (pipe
<< 28);
1522 temp
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
1524 if (gma_power_begin(dev
, false)) {
1525 REG_WRITE(control
, temp
);
1526 REG_WRITE(base
, addr
);
1530 /* unpin the old GEM object */
1531 if (psb_intel_crtc
->cursor_obj
) {
1532 gt
= container_of(psb_intel_crtc
->cursor_obj
,
1533 struct gtt_range
, gem
);
1535 drm_gem_object_unreference(psb_intel_crtc
->cursor_obj
);
1538 psb_intel_crtc
->cursor_obj
= obj
;
1542 drm_gem_object_unreference(obj
);
1546 static int cdv_intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
1548 struct drm_device
*dev
= crtc
->dev
;
1549 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
1550 int pipe
= psb_intel_crtc
->pipe
;
1556 temp
|= (CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
);
1560 temp
|= (CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
);
1564 temp
|= ((x
& CURSOR_POS_MASK
) << CURSOR_X_SHIFT
);
1565 temp
|= ((y
& CURSOR_POS_MASK
) << CURSOR_Y_SHIFT
);
1567 adder
= psb_intel_crtc
->cursor_addr
;
1569 if (gma_power_begin(dev
, false)) {
1570 REG_WRITE((pipe
== 0) ? CURAPOS
: CURBPOS
, temp
);
1571 REG_WRITE((pipe
== 0) ? CURABASE
: CURBBASE
, adder
);
1577 static void cdv_intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
,
1578 u16
*green
, u16
*blue
, uint32_t start
, uint32_t size
)
1580 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
1582 int end
= (start
+ size
> 256) ? 256 : start
+ size
;
1584 for (i
= start
; i
< end
; i
++) {
1585 psb_intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
1586 psb_intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
1587 psb_intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
1590 cdv_intel_crtc_load_lut(crtc
);
1593 static int cdv_crtc_set_config(struct drm_mode_set
*set
)
1596 struct drm_device
*dev
= set
->crtc
->dev
;
1597 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
1599 if (!dev_priv
->rpm_enabled
)
1600 return drm_crtc_helper_set_config(set
);
1602 pm_runtime_forbid(&dev
->pdev
->dev
);
1604 ret
= drm_crtc_helper_set_config(set
);
1606 pm_runtime_allow(&dev
->pdev
->dev
);
1611 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
1613 /* FIXME: why are we using this, should it be cdv_ in this tree ? */
1615 static void i8xx_clock(int refclk
, struct cdv_intel_clock_t
*clock
)
1617 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
1618 clock
->p
= clock
->p1
* clock
->p2
;
1619 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
1620 clock
->dot
= clock
->vco
/ clock
->p
;
1623 /* Returns the clock of the currently programmed mode of the given pipe. */
1624 static int cdv_intel_crtc_clock_get(struct drm_device
*dev
,
1625 struct drm_crtc
*crtc
)
1627 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
1628 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
1629 int pipe
= psb_intel_crtc
->pipe
;
1630 const struct psb_offset
*map
= &dev_priv
->regmap
[pipe
];
1633 struct cdv_intel_clock_t clock
;
1635 struct psb_pipe
*p
= &dev_priv
->regs
.pipe
[pipe
];
1637 if (gma_power_begin(dev
, false)) {
1638 dpll
= REG_READ(map
->dpll
);
1639 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
1640 fp
= REG_READ(map
->fp0
);
1642 fp
= REG_READ(map
->fp1
);
1643 is_lvds
= (pipe
== 1) && (REG_READ(LVDS
) & LVDS_PORT_EN
);
1647 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
1652 is_lvds
= (pipe
== 1) &&
1653 (dev_priv
->regs
.psb
.saveLVDS
& LVDS_PORT_EN
);
1656 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
1657 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
1658 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
1663 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
1664 DPLL_FPA01_P1_POST_DIV_SHIFT
);
1665 if (clock
.p1
== 0) {
1667 dev_err(dev
->dev
, "PLL %d\n", dpll
);
1671 if ((dpll
& PLL_REF_INPUT_MASK
) ==
1672 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
1673 /* XXX: might not be 66MHz */
1674 i8xx_clock(66000, &clock
);
1676 i8xx_clock(48000, &clock
);
1678 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
1683 DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
1684 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
1686 if (dpll
& PLL_P2_DIVIDE_BY_4
)
1691 i8xx_clock(48000, &clock
);
1694 /* XXX: It would be nice to validate the clocks, but we can't reuse
1695 * i830PllIsValid() because it relies on the xf86_config connector
1696 * configuration being accurate, which it isn't necessarily.
1702 /** Returns the currently programmed mode of the given pipe. */
1703 struct drm_display_mode
*cdv_intel_crtc_mode_get(struct drm_device
*dev
,
1704 struct drm_crtc
*crtc
)
1706 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
1707 int pipe
= psb_intel_crtc
->pipe
;
1708 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
1709 struct psb_pipe
*p
= &dev_priv
->regs
.pipe
[pipe
];
1710 const struct psb_offset
*map
= &dev_priv
->regmap
[pipe
];
1711 struct drm_display_mode
*mode
;
1717 if (gma_power_begin(dev
, false)) {
1718 htot
= REG_READ(map
->htotal
);
1719 hsync
= REG_READ(map
->hsync
);
1720 vtot
= REG_READ(map
->vtotal
);
1721 vsync
= REG_READ(map
->vsync
);
1730 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
1734 mode
->clock
= cdv_intel_crtc_clock_get(dev
, crtc
);
1735 mode
->hdisplay
= (htot
& 0xffff) + 1;
1736 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
1737 mode
->hsync_start
= (hsync
& 0xffff) + 1;
1738 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
1739 mode
->vdisplay
= (vtot
& 0xffff) + 1;
1740 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
1741 mode
->vsync_start
= (vsync
& 0xffff) + 1;
1742 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
1744 drm_mode_set_name(mode
);
1745 drm_mode_set_crtcinfo(mode
, 0);
1750 static void cdv_intel_crtc_destroy(struct drm_crtc
*crtc
)
1752 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
1754 kfree(psb_intel_crtc
->crtc_state
);
1755 drm_crtc_cleanup(crtc
);
1756 kfree(psb_intel_crtc
);
1759 static void cdv_intel_crtc_disable(struct drm_crtc
*crtc
)
1761 struct gtt_range
*gt
;
1762 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
1764 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_OFF
);
1767 gt
= to_psb_fb(crtc
->fb
)->gtt
;
1772 const struct drm_crtc_helper_funcs cdv_intel_helper_funcs
= {
1773 .dpms
= cdv_intel_crtc_dpms
,
1774 .mode_fixup
= cdv_intel_crtc_mode_fixup
,
1775 .mode_set
= cdv_intel_crtc_mode_set
,
1776 .mode_set_base
= cdv_intel_pipe_set_base
,
1777 .prepare
= cdv_intel_crtc_prepare
,
1778 .commit
= cdv_intel_crtc_commit
,
1779 .disable
= cdv_intel_crtc_disable
,
1782 const struct drm_crtc_funcs cdv_intel_crtc_funcs
= {
1783 .save
= cdv_intel_crtc_save
,
1784 .restore
= cdv_intel_crtc_restore
,
1785 .cursor_set
= cdv_intel_crtc_cursor_set
,
1786 .cursor_move
= cdv_intel_crtc_cursor_move
,
1787 .gamma_set
= cdv_intel_crtc_gamma_set
,
1788 .set_config
= cdv_crtc_set_config
,
1789 .destroy
= cdv_intel_crtc_destroy
,