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drm/gma500/cdv: Convert to gma_crtc_dpms()
[deliverable/linux.git] / drivers / gpu / drm / gma500 / cdv_intel_display.c
1 /*
2 * Copyright © 2006-2011 Intel Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc.,
15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
16 *
17 * Authors:
18 * Eric Anholt <eric@anholt.net>
19 */
20
21 #include <linux/i2c.h>
22 #include <linux/pm_runtime.h>
23
24 #include <drm/drmP.h>
25 #include "framebuffer.h"
26 #include "psb_drv.h"
27 #include "psb_intel_drv.h"
28 #include "psb_intel_reg.h"
29 #include "gma_display.h"
30 #include "power.h"
31 #include "cdv_device.h"
32
33 static bool cdv_intel_find_dp_pll(const struct gma_limit_t *limit,
34 struct drm_crtc *crtc, int target,
35 int refclk, struct gma_clock_t *best_clock);
36
37
38 #define CDV_LIMIT_SINGLE_LVDS_96 0
39 #define CDV_LIMIT_SINGLE_LVDS_100 1
40 #define CDV_LIMIT_DAC_HDMI_27 2
41 #define CDV_LIMIT_DAC_HDMI_96 3
42 #define CDV_LIMIT_DP_27 4
43 #define CDV_LIMIT_DP_100 5
44
45 static const struct gma_limit_t cdv_intel_limits[] = {
46 { /* CDV_SINGLE_LVDS_96MHz */
47 .dot = {.min = 20000, .max = 115500},
48 .vco = {.min = 1800000, .max = 3600000},
49 .n = {.min = 2, .max = 6},
50 .m = {.min = 60, .max = 160},
51 .m1 = {.min = 0, .max = 0},
52 .m2 = {.min = 58, .max = 158},
53 .p = {.min = 28, .max = 140},
54 .p1 = {.min = 2, .max = 10},
55 .p2 = {.dot_limit = 200000, .p2_slow = 14, .p2_fast = 14},
56 .find_pll = gma_find_best_pll,
57 },
58 { /* CDV_SINGLE_LVDS_100MHz */
59 .dot = {.min = 20000, .max = 115500},
60 .vco = {.min = 1800000, .max = 3600000},
61 .n = {.min = 2, .max = 6},
62 .m = {.min = 60, .max = 160},
63 .m1 = {.min = 0, .max = 0},
64 .m2 = {.min = 58, .max = 158},
65 .p = {.min = 28, .max = 140},
66 .p1 = {.min = 2, .max = 10},
67 /* The single-channel range is 25-112Mhz, and dual-channel
68 * is 80-224Mhz. Prefer single channel as much as possible.
69 */
70 .p2 = {.dot_limit = 200000, .p2_slow = 14, .p2_fast = 14},
71 .find_pll = gma_find_best_pll,
72 },
73 { /* CDV_DAC_HDMI_27MHz */
74 .dot = {.min = 20000, .max = 400000},
75 .vco = {.min = 1809000, .max = 3564000},
76 .n = {.min = 1, .max = 1},
77 .m = {.min = 67, .max = 132},
78 .m1 = {.min = 0, .max = 0},
79 .m2 = {.min = 65, .max = 130},
80 .p = {.min = 5, .max = 90},
81 .p1 = {.min = 1, .max = 9},
82 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5},
83 .find_pll = gma_find_best_pll,
84 },
85 { /* CDV_DAC_HDMI_96MHz */
86 .dot = {.min = 20000, .max = 400000},
87 .vco = {.min = 1800000, .max = 3600000},
88 .n = {.min = 2, .max = 6},
89 .m = {.min = 60, .max = 160},
90 .m1 = {.min = 0, .max = 0},
91 .m2 = {.min = 58, .max = 158},
92 .p = {.min = 5, .max = 100},
93 .p1 = {.min = 1, .max = 10},
94 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5},
95 .find_pll = gma_find_best_pll,
96 },
97 { /* CDV_DP_27MHz */
98 .dot = {.min = 160000, .max = 272000},
99 .vco = {.min = 1809000, .max = 3564000},
100 .n = {.min = 1, .max = 1},
101 .m = {.min = 67, .max = 132},
102 .m1 = {.min = 0, .max = 0},
103 .m2 = {.min = 65, .max = 130},
104 .p = {.min = 5, .max = 90},
105 .p1 = {.min = 1, .max = 9},
106 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 10},
107 .find_pll = cdv_intel_find_dp_pll,
108 },
109 { /* CDV_DP_100MHz */
110 .dot = {.min = 160000, .max = 272000},
111 .vco = {.min = 1800000, .max = 3600000},
112 .n = {.min = 2, .max = 6},
113 .m = {.min = 60, .max = 164},
114 .m1 = {.min = 0, .max = 0},
115 .m2 = {.min = 58, .max = 162},
116 .p = {.min = 5, .max = 100},
117 .p1 = {.min = 1, .max = 10},
118 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 10},
119 .find_pll = cdv_intel_find_dp_pll,
120 }
121 };
122
123 #define _wait_for(COND, MS, W) ({ \
124 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
125 int ret__ = 0; \
126 while (!(COND)) { \
127 if (time_after(jiffies, timeout__)) { \
128 ret__ = -ETIMEDOUT; \
129 break; \
130 } \
131 if (W && !in_dbg_master()) \
132 msleep(W); \
133 } \
134 ret__; \
135 })
136
137 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
138
139
140 int cdv_sb_read(struct drm_device *dev, u32 reg, u32 *val)
141 {
142 int ret;
143
144 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
145 if (ret) {
146 DRM_ERROR("timeout waiting for SB to idle before read\n");
147 return ret;
148 }
149
150 REG_WRITE(SB_ADDR, reg);
151 REG_WRITE(SB_PCKT,
152 SET_FIELD(SB_OPCODE_READ, SB_OPCODE) |
153 SET_FIELD(SB_DEST_DPLL, SB_DEST) |
154 SET_FIELD(0xf, SB_BYTE_ENABLE));
155
156 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
157 if (ret) {
158 DRM_ERROR("timeout waiting for SB to idle after read\n");
159 return ret;
160 }
161
162 *val = REG_READ(SB_DATA);
163
164 return 0;
165 }
166
167 int cdv_sb_write(struct drm_device *dev, u32 reg, u32 val)
168 {
169 int ret;
170 static bool dpio_debug = true;
171 u32 temp;
172
173 if (dpio_debug) {
174 if (cdv_sb_read(dev, reg, &temp) == 0)
175 DRM_DEBUG_KMS("0x%08x: 0x%08x (before)\n", reg, temp);
176 DRM_DEBUG_KMS("0x%08x: 0x%08x\n", reg, val);
177 }
178
179 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
180 if (ret) {
181 DRM_ERROR("timeout waiting for SB to idle before write\n");
182 return ret;
183 }
184
185 REG_WRITE(SB_ADDR, reg);
186 REG_WRITE(SB_DATA, val);
187 REG_WRITE(SB_PCKT,
188 SET_FIELD(SB_OPCODE_WRITE, SB_OPCODE) |
189 SET_FIELD(SB_DEST_DPLL, SB_DEST) |
190 SET_FIELD(0xf, SB_BYTE_ENABLE));
191
192 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
193 if (ret) {
194 DRM_ERROR("timeout waiting for SB to idle after write\n");
195 return ret;
196 }
197
198 if (dpio_debug) {
199 if (cdv_sb_read(dev, reg, &temp) == 0)
200 DRM_DEBUG_KMS("0x%08x: 0x%08x (after)\n", reg, temp);
201 }
202
203 return 0;
204 }
205
206 /* Reset the DPIO configuration register. The BIOS does this at every
207 * mode set.
208 */
209 void cdv_sb_reset(struct drm_device *dev)
210 {
211
212 REG_WRITE(DPIO_CFG, 0);
213 REG_READ(DPIO_CFG);
214 REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N);
215 }
216
217 /* Unlike most Intel display engines, on Cedarview the DPLL registers
218 * are behind this sideband bus. They must be programmed while the
219 * DPLL reference clock is on in the DPLL control register, but before
220 * the DPLL is enabled in the DPLL control register.
221 */
222 static int
223 cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc,
224 struct gma_clock_t *clock, bool is_lvds, u32 ddi_select)
225 {
226 struct psb_intel_crtc *psb_crtc = to_psb_intel_crtc(crtc);
227 int pipe = psb_crtc->pipe;
228 u32 m, n_vco, p;
229 int ret = 0;
230 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
231 int ref_sfr = (pipe == 0) ? SB_REF_DPLLA : SB_REF_DPLLB;
232 u32 ref_value;
233 u32 lane_reg, lane_value;
234
235 cdv_sb_reset(dev);
236
237 REG_WRITE(dpll_reg, DPLL_SYNCLOCK_ENABLE | DPLL_VGA_MODE_DIS);
238
239 udelay(100);
240
241 /* Follow the BIOS and write the REF/SFR Register. Hardcoded value */
242 ref_value = 0x68A701;
243
244 cdv_sb_write(dev, SB_REF_SFR(pipe), ref_value);
245
246 /* We don't know what the other fields of these regs are, so
247 * leave them in place.
248 */
249 /*
250 * The BIT 14:13 of 0x8010/0x8030 is used to select the ref clk
251 * for the pipe A/B. Display spec 1.06 has wrong definition.
252 * Correct definition is like below:
253 *
254 * refclka mean use clock from same PLL
255 *
256 * if DPLLA sets 01 and DPLLB sets 01, they use clock from their pll
257 *
258 * if DPLLA sets 01 and DPLLB sets 02, both use clk from DPLLA
259 *
260 */
261 ret = cdv_sb_read(dev, ref_sfr, &ref_value);
262 if (ret)
263 return ret;
264 ref_value &= ~(REF_CLK_MASK);
265
266 /* use DPLL_A for pipeB on CRT/HDMI */
267 if (pipe == 1 && !is_lvds && !(ddi_select & DP_MASK)) {
268 DRM_DEBUG_KMS("use DPLLA for pipe B\n");
269 ref_value |= REF_CLK_DPLLA;
270 } else {
271 DRM_DEBUG_KMS("use their DPLL for pipe A/B\n");
272 ref_value |= REF_CLK_DPLL;
273 }
274 ret = cdv_sb_write(dev, ref_sfr, ref_value);
275 if (ret)
276 return ret;
277
278 ret = cdv_sb_read(dev, SB_M(pipe), &m);
279 if (ret)
280 return ret;
281 m &= ~SB_M_DIVIDER_MASK;
282 m |= ((clock->m2) << SB_M_DIVIDER_SHIFT);
283 ret = cdv_sb_write(dev, SB_M(pipe), m);
284 if (ret)
285 return ret;
286
287 ret = cdv_sb_read(dev, SB_N_VCO(pipe), &n_vco);
288 if (ret)
289 return ret;
290
291 /* Follow the BIOS to program the N_DIVIDER REG */
292 n_vco &= 0xFFFF;
293 n_vco |= 0x107;
294 n_vco &= ~(SB_N_VCO_SEL_MASK |
295 SB_N_DIVIDER_MASK |
296 SB_N_CB_TUNE_MASK);
297
298 n_vco |= ((clock->n) << SB_N_DIVIDER_SHIFT);
299
300 if (clock->vco < 2250000) {
301 n_vco |= (2 << SB_N_CB_TUNE_SHIFT);
302 n_vco |= (0 << SB_N_VCO_SEL_SHIFT);
303 } else if (clock->vco < 2750000) {
304 n_vco |= (1 << SB_N_CB_TUNE_SHIFT);
305 n_vco |= (1 << SB_N_VCO_SEL_SHIFT);
306 } else if (clock->vco < 3300000) {
307 n_vco |= (0 << SB_N_CB_TUNE_SHIFT);
308 n_vco |= (2 << SB_N_VCO_SEL_SHIFT);
309 } else {
310 n_vco |= (0 << SB_N_CB_TUNE_SHIFT);
311 n_vco |= (3 << SB_N_VCO_SEL_SHIFT);
312 }
313
314 ret = cdv_sb_write(dev, SB_N_VCO(pipe), n_vco);
315 if (ret)
316 return ret;
317
318 ret = cdv_sb_read(dev, SB_P(pipe), &p);
319 if (ret)
320 return ret;
321 p &= ~(SB_P2_DIVIDER_MASK | SB_P1_DIVIDER_MASK);
322 p |= SET_FIELD(clock->p1, SB_P1_DIVIDER);
323 switch (clock->p2) {
324 case 5:
325 p |= SET_FIELD(SB_P2_5, SB_P2_DIVIDER);
326 break;
327 case 10:
328 p |= SET_FIELD(SB_P2_10, SB_P2_DIVIDER);
329 break;
330 case 14:
331 p |= SET_FIELD(SB_P2_14, SB_P2_DIVIDER);
332 break;
333 case 7:
334 p |= SET_FIELD(SB_P2_7, SB_P2_DIVIDER);
335 break;
336 default:
337 DRM_ERROR("Bad P2 clock: %d\n", clock->p2);
338 return -EINVAL;
339 }
340 ret = cdv_sb_write(dev, SB_P(pipe), p);
341 if (ret)
342 return ret;
343
344 if (ddi_select) {
345 if ((ddi_select & DDI_MASK) == DDI0_SELECT) {
346 lane_reg = PSB_LANE0;
347 cdv_sb_read(dev, lane_reg, &lane_value);
348 lane_value &= ~(LANE_PLL_MASK);
349 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
350 cdv_sb_write(dev, lane_reg, lane_value);
351
352 lane_reg = PSB_LANE1;
353 cdv_sb_read(dev, lane_reg, &lane_value);
354 lane_value &= ~(LANE_PLL_MASK);
355 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
356 cdv_sb_write(dev, lane_reg, lane_value);
357 } else {
358 lane_reg = PSB_LANE2;
359 cdv_sb_read(dev, lane_reg, &lane_value);
360 lane_value &= ~(LANE_PLL_MASK);
361 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
362 cdv_sb_write(dev, lane_reg, lane_value);
363
364 lane_reg = PSB_LANE3;
365 cdv_sb_read(dev, lane_reg, &lane_value);
366 lane_value &= ~(LANE_PLL_MASK);
367 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
368 cdv_sb_write(dev, lane_reg, lane_value);
369 }
370 }
371 return 0;
372 }
373
374 static const struct gma_limit_t *cdv_intel_limit(struct drm_crtc *crtc,
375 int refclk)
376 {
377 const struct gma_limit_t *limit;
378 if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
379 /*
380 * Now only single-channel LVDS is supported on CDV. If it is
381 * incorrect, please add the dual-channel LVDS.
382 */
383 if (refclk == 96000)
384 limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_96];
385 else
386 limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_100];
387 } else if (gma_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
388 gma_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
389 if (refclk == 27000)
390 limit = &cdv_intel_limits[CDV_LIMIT_DP_27];
391 else
392 limit = &cdv_intel_limits[CDV_LIMIT_DP_100];
393 } else {
394 if (refclk == 27000)
395 limit = &cdv_intel_limits[CDV_LIMIT_DAC_HDMI_27];
396 else
397 limit = &cdv_intel_limits[CDV_LIMIT_DAC_HDMI_96];
398 }
399 return limit;
400 }
401
402 /* m1 is reserved as 0 in CDV, n is a ring counter */
403 static void cdv_intel_clock(int refclk, struct gma_clock_t *clock)
404 {
405 clock->m = clock->m2 + 2;
406 clock->p = clock->p1 * clock->p2;
407 clock->vco = (refclk * clock->m) / clock->n;
408 clock->dot = clock->vco / clock->p;
409 }
410
411 static bool cdv_intel_find_dp_pll(const struct gma_limit_t *limit,
412 struct drm_crtc *crtc, int target,
413 int refclk,
414 struct gma_clock_t *best_clock)
415 {
416 struct gma_clock_t clock;
417 if (refclk == 27000) {
418 if (target < 200000) {
419 clock.p1 = 2;
420 clock.p2 = 10;
421 clock.n = 1;
422 clock.m1 = 0;
423 clock.m2 = 118;
424 } else {
425 clock.p1 = 1;
426 clock.p2 = 10;
427 clock.n = 1;
428 clock.m1 = 0;
429 clock.m2 = 98;
430 }
431 } else if (refclk == 100000) {
432 if (target < 200000) {
433 clock.p1 = 2;
434 clock.p2 = 10;
435 clock.n = 5;
436 clock.m1 = 0;
437 clock.m2 = 160;
438 } else {
439 clock.p1 = 1;
440 clock.p2 = 10;
441 clock.n = 5;
442 clock.m1 = 0;
443 clock.m2 = 133;
444 }
445 } else
446 return false;
447 clock.m = clock.m2 + 2;
448 clock.p = clock.p1 * clock.p2;
449 clock.vco = (refclk * clock.m) / clock.n;
450 clock.dot = clock.vco / clock.p;
451 memcpy(best_clock, &clock, sizeof(struct gma_clock_t));
452 return true;
453 }
454
455 #define FIFO_PIPEA (1 << 0)
456 #define FIFO_PIPEB (1 << 1)
457
458 static bool cdv_intel_pipe_enabled(struct drm_device *dev, int pipe)
459 {
460 struct drm_crtc *crtc;
461 struct drm_psb_private *dev_priv = dev->dev_private;
462 struct psb_intel_crtc *psb_intel_crtc = NULL;
463
464 crtc = dev_priv->pipe_to_crtc_mapping[pipe];
465 psb_intel_crtc = to_psb_intel_crtc(crtc);
466
467 if (crtc->fb == NULL || !psb_intel_crtc->active)
468 return false;
469 return true;
470 }
471
472 static bool cdv_intel_single_pipe_active (struct drm_device *dev)
473 {
474 uint32_t pipe_enabled = 0;
475
476 if (cdv_intel_pipe_enabled(dev, 0))
477 pipe_enabled |= FIFO_PIPEA;
478
479 if (cdv_intel_pipe_enabled(dev, 1))
480 pipe_enabled |= FIFO_PIPEB;
481
482
483 DRM_DEBUG_KMS("pipe enabled %x\n", pipe_enabled);
484
485 if (pipe_enabled == FIFO_PIPEA || pipe_enabled == FIFO_PIPEB)
486 return true;
487 else
488 return false;
489 }
490
491 static bool is_pipeb_lvds(struct drm_device *dev, struct drm_crtc *crtc)
492 {
493 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
494 struct drm_mode_config *mode_config = &dev->mode_config;
495 struct drm_connector *connector;
496
497 if (psb_intel_crtc->pipe != 1)
498 return false;
499
500 list_for_each_entry(connector, &mode_config->connector_list, head) {
501 struct psb_intel_encoder *psb_intel_encoder =
502 psb_intel_attached_encoder(connector);
503
504 if (!connector->encoder
505 || connector->encoder->crtc != crtc)
506 continue;
507
508 if (psb_intel_encoder->type == INTEL_OUTPUT_LVDS)
509 return true;
510 }
511
512 return false;
513 }
514
515 void cdv_intel_disable_self_refresh(struct drm_device *dev)
516 {
517 if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) {
518
519 /* Disable self-refresh before adjust WM */
520 REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN));
521 REG_READ(FW_BLC_SELF);
522
523 gma_wait_for_vblank(dev);
524
525 /* Cedarview workaround to write ovelay plane, which force to leave
526 * MAX_FIFO state.
527 */
528 REG_WRITE(OV_OVADD, 0/*dev_priv->ovl_offset*/);
529 REG_READ(OV_OVADD);
530
531 gma_wait_for_vblank(dev);
532 }
533
534 }
535
536 void cdv_intel_update_watermark(struct drm_device *dev, struct drm_crtc *crtc)
537 {
538
539 if (cdv_intel_single_pipe_active(dev)) {
540 u32 fw;
541
542 fw = REG_READ(DSPFW1);
543 fw &= ~DSP_FIFO_SR_WM_MASK;
544 fw |= (0x7e << DSP_FIFO_SR_WM_SHIFT);
545 fw &= ~CURSOR_B_FIFO_WM_MASK;
546 fw |= (0x4 << CURSOR_B_FIFO_WM_SHIFT);
547 REG_WRITE(DSPFW1, fw);
548
549 fw = REG_READ(DSPFW2);
550 fw &= ~CURSOR_A_FIFO_WM_MASK;
551 fw |= (0x6 << CURSOR_A_FIFO_WM_SHIFT);
552 fw &= ~DSP_PLANE_C_FIFO_WM_MASK;
553 fw |= (0x8 << DSP_PLANE_C_FIFO_WM_SHIFT);
554 REG_WRITE(DSPFW2, fw);
555
556 REG_WRITE(DSPFW3, 0x36000000);
557
558 /* ignore FW4 */
559
560 if (is_pipeb_lvds(dev, crtc)) {
561 REG_WRITE(DSPFW5, 0x00040330);
562 } else {
563 fw = (3 << DSP_PLANE_B_FIFO_WM1_SHIFT) |
564 (4 << DSP_PLANE_A_FIFO_WM1_SHIFT) |
565 (3 << CURSOR_B_FIFO_WM1_SHIFT) |
566 (4 << CURSOR_FIFO_SR_WM1_SHIFT);
567 REG_WRITE(DSPFW5, fw);
568 }
569
570 REG_WRITE(DSPFW6, 0x10);
571
572 gma_wait_for_vblank(dev);
573
574 /* enable self-refresh for single pipe active */
575 REG_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
576 REG_READ(FW_BLC_SELF);
577 gma_wait_for_vblank(dev);
578
579 } else {
580
581 /* HW team suggested values... */
582 REG_WRITE(DSPFW1, 0x3f880808);
583 REG_WRITE(DSPFW2, 0x0b020202);
584 REG_WRITE(DSPFW3, 0x24000000);
585 REG_WRITE(DSPFW4, 0x08030202);
586 REG_WRITE(DSPFW5, 0x01010101);
587 REG_WRITE(DSPFW6, 0x1d0);
588
589 gma_wait_for_vblank(dev);
590
591 cdv_intel_disable_self_refresh(dev);
592
593 }
594 }
595
596 /** Loads the palette/gamma unit for the CRTC with the prepared values */
597 static void cdv_intel_crtc_load_lut(struct drm_crtc *crtc)
598 {
599 struct drm_device *dev = crtc->dev;
600 struct drm_psb_private *dev_priv = dev->dev_private;
601 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
602 int palreg = PALETTE_A;
603 int i;
604
605 /* The clocks have to be on to load the palette. */
606 if (!crtc->enabled)
607 return;
608
609 switch (psb_intel_crtc->pipe) {
610 case 0:
611 break;
612 case 1:
613 palreg = PALETTE_B;
614 break;
615 case 2:
616 palreg = PALETTE_C;
617 break;
618 default:
619 dev_err(dev->dev, "Illegal Pipe Number.\n");
620 return;
621 }
622
623 if (gma_power_begin(dev, false)) {
624 for (i = 0; i < 256; i++) {
625 REG_WRITE(palreg + 4 * i,
626 ((psb_intel_crtc->lut_r[i] +
627 psb_intel_crtc->lut_adj[i]) << 16) |
628 ((psb_intel_crtc->lut_g[i] +
629 psb_intel_crtc->lut_adj[i]) << 8) |
630 (psb_intel_crtc->lut_b[i] +
631 psb_intel_crtc->lut_adj[i]));
632 }
633 gma_power_end(dev);
634 } else {
635 for (i = 0; i < 256; i++) {
636 dev_priv->regs.pipe[0].palette[i] =
637 ((psb_intel_crtc->lut_r[i] +
638 psb_intel_crtc->lut_adj[i]) << 16) |
639 ((psb_intel_crtc->lut_g[i] +
640 psb_intel_crtc->lut_adj[i]) << 8) |
641 (psb_intel_crtc->lut_b[i] +
642 psb_intel_crtc->lut_adj[i]);
643 }
644
645 }
646 }
647
648 /**
649 * Return the pipe currently connected to the panel fitter,
650 * or -1 if the panel fitter is not present or not in use
651 */
652 static int cdv_intel_panel_fitter_pipe(struct drm_device *dev)
653 {
654 u32 pfit_control;
655
656 pfit_control = REG_READ(PFIT_CONTROL);
657
658 /* See if the panel fitter is in use */
659 if ((pfit_control & PFIT_ENABLE) == 0)
660 return -1;
661 return (pfit_control >> 29) & 0x3;
662 }
663
664 static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
665 struct drm_display_mode *mode,
666 struct drm_display_mode *adjusted_mode,
667 int x, int y,
668 struct drm_framebuffer *old_fb)
669 {
670 struct drm_device *dev = crtc->dev;
671 struct drm_psb_private *dev_priv = dev->dev_private;
672 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
673 int pipe = psb_intel_crtc->pipe;
674 const struct psb_offset *map = &dev_priv->regmap[pipe];
675 int refclk;
676 struct gma_clock_t clock;
677 u32 dpll = 0, dspcntr, pipeconf;
678 bool ok;
679 bool is_crt = false, is_lvds = false, is_tv = false;
680 bool is_hdmi = false, is_dp = false;
681 struct drm_mode_config *mode_config = &dev->mode_config;
682 struct drm_connector *connector;
683 const struct gma_limit_t *limit;
684 u32 ddi_select = 0;
685 bool is_edp = false;
686
687 list_for_each_entry(connector, &mode_config->connector_list, head) {
688 struct psb_intel_encoder *psb_intel_encoder =
689 psb_intel_attached_encoder(connector);
690
691 if (!connector->encoder
692 || connector->encoder->crtc != crtc)
693 continue;
694
695 ddi_select = psb_intel_encoder->ddi_select;
696 switch (psb_intel_encoder->type) {
697 case INTEL_OUTPUT_LVDS:
698 is_lvds = true;
699 break;
700 case INTEL_OUTPUT_TVOUT:
701 is_tv = true;
702 break;
703 case INTEL_OUTPUT_ANALOG:
704 is_crt = true;
705 break;
706 case INTEL_OUTPUT_HDMI:
707 is_hdmi = true;
708 break;
709 case INTEL_OUTPUT_DISPLAYPORT:
710 is_dp = true;
711 break;
712 case INTEL_OUTPUT_EDP:
713 is_edp = true;
714 break;
715 default:
716 DRM_ERROR("invalid output type.\n");
717 return 0;
718 }
719 }
720
721 if (dev_priv->dplla_96mhz)
722 /* low-end sku, 96/100 mhz */
723 refclk = 96000;
724 else
725 /* high-end sku, 27/100 mhz */
726 refclk = 27000;
727 if (is_dp || is_edp) {
728 /*
729 * Based on the spec the low-end SKU has only CRT/LVDS. So it is
730 * unnecessary to consider it for DP/eDP.
731 * On the high-end SKU, it will use the 27/100M reference clk
732 * for DP/eDP. When using SSC clock, the ref clk is 100MHz.Otherwise
733 * it will be 27MHz. From the VBIOS code it seems that the pipe A choose
734 * 27MHz for DP/eDP while the Pipe B chooses the 100MHz.
735 */
736 if (pipe == 0)
737 refclk = 27000;
738 else
739 refclk = 100000;
740 }
741
742 if (is_lvds && dev_priv->lvds_use_ssc) {
743 refclk = dev_priv->lvds_ssc_freq * 1000;
744 DRM_DEBUG_KMS("Use SSC reference clock %d Mhz\n", dev_priv->lvds_ssc_freq);
745 }
746
747 drm_mode_debug_printmodeline(adjusted_mode);
748
749 limit = psb_intel_crtc->clock_funcs->limit(crtc, refclk);
750
751 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk,
752 &clock);
753 if (!ok) {
754 DRM_ERROR("Couldn't find PLL settings for mode! target: %d, actual: %d",
755 adjusted_mode->clock, clock.dot);
756 return 0;
757 }
758
759 dpll = DPLL_VGA_MODE_DIS;
760 if (is_tv) {
761 /* XXX: just matching BIOS for now */
762 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
763 dpll |= 3;
764 }
765 /* dpll |= PLL_REF_INPUT_DREFCLK; */
766
767 if (is_dp || is_edp) {
768 cdv_intel_dp_set_m_n(crtc, mode, adjusted_mode);
769 } else {
770 REG_WRITE(PIPE_GMCH_DATA_M(pipe), 0);
771 REG_WRITE(PIPE_GMCH_DATA_N(pipe), 0);
772 REG_WRITE(PIPE_DP_LINK_M(pipe), 0);
773 REG_WRITE(PIPE_DP_LINK_N(pipe), 0);
774 }
775
776 dpll |= DPLL_SYNCLOCK_ENABLE;
777 /* if (is_lvds)
778 dpll |= DPLLB_MODE_LVDS;
779 else
780 dpll |= DPLLB_MODE_DAC_SERIAL; */
781 /* dpll |= (2 << 11); */
782
783 /* setup pipeconf */
784 pipeconf = REG_READ(map->conf);
785
786 pipeconf &= ~(PIPE_BPC_MASK);
787 if (is_edp) {
788 switch (dev_priv->edp.bpp) {
789 case 24:
790 pipeconf |= PIPE_8BPC;
791 break;
792 case 18:
793 pipeconf |= PIPE_6BPC;
794 break;
795 case 30:
796 pipeconf |= PIPE_10BPC;
797 break;
798 default:
799 pipeconf |= PIPE_8BPC;
800 break;
801 }
802 } else if (is_lvds) {
803 /* the BPC will be 6 if it is 18-bit LVDS panel */
804 if ((REG_READ(LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
805 pipeconf |= PIPE_8BPC;
806 else
807 pipeconf |= PIPE_6BPC;
808 } else
809 pipeconf |= PIPE_8BPC;
810
811 /* Set up the display plane register */
812 dspcntr = DISPPLANE_GAMMA_ENABLE;
813
814 if (pipe == 0)
815 dspcntr |= DISPPLANE_SEL_PIPE_A;
816 else
817 dspcntr |= DISPPLANE_SEL_PIPE_B;
818
819 dspcntr |= DISPLAY_PLANE_ENABLE;
820 pipeconf |= PIPEACONF_ENABLE;
821
822 REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE);
823 REG_READ(map->dpll);
824
825 cdv_dpll_set_clock_cdv(dev, crtc, &clock, is_lvds, ddi_select);
826
827 udelay(150);
828
829
830 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
831 * This is an exception to the general rule that mode_set doesn't turn
832 * things on.
833 */
834 if (is_lvds) {
835 u32 lvds = REG_READ(LVDS);
836
837 lvds |=
838 LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP |
839 LVDS_PIPEB_SELECT;
840 /* Set the B0-B3 data pairs corresponding to
841 * whether we're going to
842 * set the DPLLs for dual-channel mode or not.
843 */
844 if (clock.p2 == 7)
845 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
846 else
847 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
848
849 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
850 * appropriately here, but we need to look more
851 * thoroughly into how panels behave in the two modes.
852 */
853
854 REG_WRITE(LVDS, lvds);
855 REG_READ(LVDS);
856 }
857
858 dpll |= DPLL_VCO_ENABLE;
859
860 /* Disable the panel fitter if it was on our pipe */
861 if (cdv_intel_panel_fitter_pipe(dev) == pipe)
862 REG_WRITE(PFIT_CONTROL, 0);
863
864 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
865 drm_mode_debug_printmodeline(mode);
866
867 REG_WRITE(map->dpll,
868 (REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE);
869 REG_READ(map->dpll);
870 /* Wait for the clocks to stabilize. */
871 udelay(150); /* 42 usec w/o calibration, 110 with. rounded up. */
872
873 if (!(REG_READ(map->dpll) & DPLL_LOCK)) {
874 dev_err(dev->dev, "Failed to get DPLL lock\n");
875 return -EBUSY;
876 }
877
878 {
879 int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
880 REG_WRITE(map->dpll_md, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
881 }
882
883 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |
884 ((adjusted_mode->crtc_htotal - 1) << 16));
885 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |
886 ((adjusted_mode->crtc_hblank_end - 1) << 16));
887 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |
888 ((adjusted_mode->crtc_hsync_end - 1) << 16));
889 REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |
890 ((adjusted_mode->crtc_vtotal - 1) << 16));
891 REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |
892 ((adjusted_mode->crtc_vblank_end - 1) << 16));
893 REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |
894 ((adjusted_mode->crtc_vsync_end - 1) << 16));
895 /* pipesrc and dspsize control the size that is scaled from,
896 * which should always be the user's requested size.
897 */
898 REG_WRITE(map->size,
899 ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
900 REG_WRITE(map->pos, 0);
901 REG_WRITE(map->src,
902 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
903 REG_WRITE(map->conf, pipeconf);
904 REG_READ(map->conf);
905
906 gma_wait_for_vblank(dev);
907
908 REG_WRITE(map->cntr, dspcntr);
909
910 /* Flush the plane changes */
911 {
912 struct drm_crtc_helper_funcs *crtc_funcs =
913 crtc->helper_private;
914 crtc_funcs->mode_set_base(crtc, x, y, old_fb);
915 }
916
917 gma_wait_for_vblank(dev);
918
919 return 0;
920 }
921
922
923 /**
924 * Save HW states of giving crtc
925 */
926 static void cdv_intel_crtc_save(struct drm_crtc *crtc)
927 {
928 struct drm_device *dev = crtc->dev;
929 struct drm_psb_private *dev_priv = dev->dev_private;
930 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
931 struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state;
932 const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe];
933 uint32_t paletteReg;
934 int i;
935
936 if (!crtc_state) {
937 dev_dbg(dev->dev, "No CRTC state found\n");
938 return;
939 }
940
941 crtc_state->saveDSPCNTR = REG_READ(map->cntr);
942 crtc_state->savePIPECONF = REG_READ(map->conf);
943 crtc_state->savePIPESRC = REG_READ(map->src);
944 crtc_state->saveFP0 = REG_READ(map->fp0);
945 crtc_state->saveFP1 = REG_READ(map->fp1);
946 crtc_state->saveDPLL = REG_READ(map->dpll);
947 crtc_state->saveHTOTAL = REG_READ(map->htotal);
948 crtc_state->saveHBLANK = REG_READ(map->hblank);
949 crtc_state->saveHSYNC = REG_READ(map->hsync);
950 crtc_state->saveVTOTAL = REG_READ(map->vtotal);
951 crtc_state->saveVBLANK = REG_READ(map->vblank);
952 crtc_state->saveVSYNC = REG_READ(map->vsync);
953 crtc_state->saveDSPSTRIDE = REG_READ(map->stride);
954
955 /*NOTE: DSPSIZE DSPPOS only for psb*/
956 crtc_state->saveDSPSIZE = REG_READ(map->size);
957 crtc_state->saveDSPPOS = REG_READ(map->pos);
958
959 crtc_state->saveDSPBASE = REG_READ(map->base);
960
961 DRM_DEBUG("(%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n",
962 crtc_state->saveDSPCNTR,
963 crtc_state->savePIPECONF,
964 crtc_state->savePIPESRC,
965 crtc_state->saveFP0,
966 crtc_state->saveFP1,
967 crtc_state->saveDPLL,
968 crtc_state->saveHTOTAL,
969 crtc_state->saveHBLANK,
970 crtc_state->saveHSYNC,
971 crtc_state->saveVTOTAL,
972 crtc_state->saveVBLANK,
973 crtc_state->saveVSYNC,
974 crtc_state->saveDSPSTRIDE,
975 crtc_state->saveDSPSIZE,
976 crtc_state->saveDSPPOS,
977 crtc_state->saveDSPBASE
978 );
979
980 paletteReg = map->palette;
981 for (i = 0; i < 256; ++i)
982 crtc_state->savePalette[i] = REG_READ(paletteReg + (i << 2));
983 }
984
985 /**
986 * Restore HW states of giving crtc
987 */
988 static void cdv_intel_crtc_restore(struct drm_crtc *crtc)
989 {
990 struct drm_device *dev = crtc->dev;
991 struct drm_psb_private *dev_priv = dev->dev_private;
992 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
993 struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state;
994 const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe];
995 uint32_t paletteReg;
996 int i;
997
998 if (!crtc_state) {
999 dev_dbg(dev->dev, "No crtc state\n");
1000 return;
1001 }
1002
1003 DRM_DEBUG(
1004 "current:(%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n",
1005 REG_READ(map->cntr),
1006 REG_READ(map->conf),
1007 REG_READ(map->src),
1008 REG_READ(map->fp0),
1009 REG_READ(map->fp1),
1010 REG_READ(map->dpll),
1011 REG_READ(map->htotal),
1012 REG_READ(map->hblank),
1013 REG_READ(map->hsync),
1014 REG_READ(map->vtotal),
1015 REG_READ(map->vblank),
1016 REG_READ(map->vsync),
1017 REG_READ(map->stride),
1018 REG_READ(map->size),
1019 REG_READ(map->pos),
1020 REG_READ(map->base)
1021 );
1022
1023 DRM_DEBUG(
1024 "saved: (%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n",
1025 crtc_state->saveDSPCNTR,
1026 crtc_state->savePIPECONF,
1027 crtc_state->savePIPESRC,
1028 crtc_state->saveFP0,
1029 crtc_state->saveFP1,
1030 crtc_state->saveDPLL,
1031 crtc_state->saveHTOTAL,
1032 crtc_state->saveHBLANK,
1033 crtc_state->saveHSYNC,
1034 crtc_state->saveVTOTAL,
1035 crtc_state->saveVBLANK,
1036 crtc_state->saveVSYNC,
1037 crtc_state->saveDSPSTRIDE,
1038 crtc_state->saveDSPSIZE,
1039 crtc_state->saveDSPPOS,
1040 crtc_state->saveDSPBASE
1041 );
1042
1043
1044 if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) {
1045 REG_WRITE(map->dpll,
1046 crtc_state->saveDPLL & ~DPLL_VCO_ENABLE);
1047 REG_READ(map->dpll);
1048 DRM_DEBUG("write dpll: %x\n",
1049 REG_READ(map->dpll));
1050 udelay(150);
1051 }
1052
1053 REG_WRITE(map->fp0, crtc_state->saveFP0);
1054 REG_READ(map->fp0);
1055
1056 REG_WRITE(map->fp1, crtc_state->saveFP1);
1057 REG_READ(map->fp1);
1058
1059 REG_WRITE(map->dpll, crtc_state->saveDPLL);
1060 REG_READ(map->dpll);
1061 udelay(150);
1062
1063 REG_WRITE(map->htotal, crtc_state->saveHTOTAL);
1064 REG_WRITE(map->hblank, crtc_state->saveHBLANK);
1065 REG_WRITE(map->hsync, crtc_state->saveHSYNC);
1066 REG_WRITE(map->vtotal, crtc_state->saveVTOTAL);
1067 REG_WRITE(map->vblank, crtc_state->saveVBLANK);
1068 REG_WRITE(map->vsync, crtc_state->saveVSYNC);
1069 REG_WRITE(map->stride, crtc_state->saveDSPSTRIDE);
1070
1071 REG_WRITE(map->size, crtc_state->saveDSPSIZE);
1072 REG_WRITE(map->pos, crtc_state->saveDSPPOS);
1073
1074 REG_WRITE(map->src, crtc_state->savePIPESRC);
1075 REG_WRITE(map->base, crtc_state->saveDSPBASE);
1076 REG_WRITE(map->conf, crtc_state->savePIPECONF);
1077
1078 gma_wait_for_vblank(dev);
1079
1080 REG_WRITE(map->cntr, crtc_state->saveDSPCNTR);
1081 REG_WRITE(map->base, crtc_state->saveDSPBASE);
1082
1083 gma_wait_for_vblank(dev);
1084
1085 paletteReg = map->palette;
1086 for (i = 0; i < 256; ++i)
1087 REG_WRITE(paletteReg + (i << 2), crtc_state->savePalette[i]);
1088 }
1089
1090 static int cdv_intel_crtc_cursor_set(struct drm_crtc *crtc,
1091 struct drm_file *file_priv,
1092 uint32_t handle,
1093 uint32_t width, uint32_t height)
1094 {
1095 struct drm_device *dev = crtc->dev;
1096 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1097 int pipe = psb_intel_crtc->pipe;
1098 uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
1099 uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
1100 uint32_t temp;
1101 size_t addr = 0;
1102 struct gtt_range *gt;
1103 struct drm_gem_object *obj;
1104 int ret = 0;
1105
1106 /* if we want to turn of the cursor ignore width and height */
1107 if (!handle) {
1108 /* turn off the cursor */
1109 temp = CURSOR_MODE_DISABLE;
1110
1111 if (gma_power_begin(dev, false)) {
1112 REG_WRITE(control, temp);
1113 REG_WRITE(base, 0);
1114 gma_power_end(dev);
1115 }
1116
1117 /* unpin the old GEM object */
1118 if (psb_intel_crtc->cursor_obj) {
1119 gt = container_of(psb_intel_crtc->cursor_obj,
1120 struct gtt_range, gem);
1121 psb_gtt_unpin(gt);
1122 drm_gem_object_unreference(psb_intel_crtc->cursor_obj);
1123 psb_intel_crtc->cursor_obj = NULL;
1124 }
1125
1126 return 0;
1127 }
1128
1129 /* Currently we only support 64x64 cursors */
1130 if (width != 64 || height != 64) {
1131 dev_dbg(dev->dev, "we currently only support 64x64 cursors\n");
1132 return -EINVAL;
1133 }
1134
1135 obj = drm_gem_object_lookup(dev, file_priv, handle);
1136 if (!obj)
1137 return -ENOENT;
1138
1139 if (obj->size < width * height * 4) {
1140 dev_dbg(dev->dev, "buffer is to small\n");
1141 ret = -ENOMEM;
1142 goto unref_cursor;
1143 }
1144
1145 gt = container_of(obj, struct gtt_range, gem);
1146
1147 /* Pin the memory into the GTT */
1148 ret = psb_gtt_pin(gt);
1149 if (ret) {
1150 dev_err(dev->dev, "Can not pin down handle 0x%x\n", handle);
1151 goto unref_cursor;
1152 }
1153
1154 addr = gt->offset; /* Or resource.start ??? */
1155
1156 psb_intel_crtc->cursor_addr = addr;
1157
1158 temp = 0;
1159 /* set the pipe for the cursor */
1160 temp |= (pipe << 28);
1161 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
1162
1163 if (gma_power_begin(dev, false)) {
1164 REG_WRITE(control, temp);
1165 REG_WRITE(base, addr);
1166 gma_power_end(dev);
1167 }
1168
1169 /* unpin the old GEM object */
1170 if (psb_intel_crtc->cursor_obj) {
1171 gt = container_of(psb_intel_crtc->cursor_obj,
1172 struct gtt_range, gem);
1173 psb_gtt_unpin(gt);
1174 drm_gem_object_unreference(psb_intel_crtc->cursor_obj);
1175 }
1176
1177 psb_intel_crtc->cursor_obj = obj;
1178 return ret;
1179
1180 unref_cursor:
1181 drm_gem_object_unreference(obj);
1182 return ret;
1183 }
1184
1185 static int cdv_intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
1186 {
1187 struct drm_device *dev = crtc->dev;
1188 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1189 int pipe = psb_intel_crtc->pipe;
1190 uint32_t temp = 0;
1191 uint32_t adder;
1192
1193
1194 if (x < 0) {
1195 temp |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT);
1196 x = -x;
1197 }
1198 if (y < 0) {
1199 temp |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT);
1200 y = -y;
1201 }
1202
1203 temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT);
1204 temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
1205
1206 adder = psb_intel_crtc->cursor_addr;
1207
1208 if (gma_power_begin(dev, false)) {
1209 REG_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
1210 REG_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
1211 gma_power_end(dev);
1212 }
1213 return 0;
1214 }
1215
1216 static void cdv_intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red,
1217 u16 *green, u16 *blue, uint32_t start, uint32_t size)
1218 {
1219 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1220 int i;
1221 int end = (start + size > 256) ? 256 : start + size;
1222
1223 for (i = start; i < end; i++) {
1224 psb_intel_crtc->lut_r[i] = red[i] >> 8;
1225 psb_intel_crtc->lut_g[i] = green[i] >> 8;
1226 psb_intel_crtc->lut_b[i] = blue[i] >> 8;
1227 }
1228
1229 cdv_intel_crtc_load_lut(crtc);
1230 }
1231
1232 static int cdv_crtc_set_config(struct drm_mode_set *set)
1233 {
1234 int ret = 0;
1235 struct drm_device *dev = set->crtc->dev;
1236 struct drm_psb_private *dev_priv = dev->dev_private;
1237
1238 if (!dev_priv->rpm_enabled)
1239 return drm_crtc_helper_set_config(set);
1240
1241 pm_runtime_forbid(&dev->pdev->dev);
1242
1243 ret = drm_crtc_helper_set_config(set);
1244
1245 pm_runtime_allow(&dev->pdev->dev);
1246
1247 return ret;
1248 }
1249
1250 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
1251
1252 /* FIXME: why are we using this, should it be cdv_ in this tree ? */
1253
1254 static void i8xx_clock(int refclk, struct gma_clock_t *clock)
1255 {
1256 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
1257 clock->p = clock->p1 * clock->p2;
1258 clock->vco = refclk * clock->m / (clock->n + 2);
1259 clock->dot = clock->vco / clock->p;
1260 }
1261
1262 /* Returns the clock of the currently programmed mode of the given pipe. */
1263 static int cdv_intel_crtc_clock_get(struct drm_device *dev,
1264 struct drm_crtc *crtc)
1265 {
1266 struct drm_psb_private *dev_priv = dev->dev_private;
1267 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1268 int pipe = psb_intel_crtc->pipe;
1269 const struct psb_offset *map = &dev_priv->regmap[pipe];
1270 u32 dpll;
1271 u32 fp;
1272 struct gma_clock_t clock;
1273 bool is_lvds;
1274 struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
1275
1276 if (gma_power_begin(dev, false)) {
1277 dpll = REG_READ(map->dpll);
1278 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
1279 fp = REG_READ(map->fp0);
1280 else
1281 fp = REG_READ(map->fp1);
1282 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);
1283 gma_power_end(dev);
1284 } else {
1285 dpll = p->dpll;
1286 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
1287 fp = p->fp0;
1288 else
1289 fp = p->fp1;
1290
1291 is_lvds = (pipe == 1) &&
1292 (dev_priv->regs.psb.saveLVDS & LVDS_PORT_EN);
1293 }
1294
1295 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
1296 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
1297 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
1298
1299 if (is_lvds) {
1300 clock.p1 =
1301 ffs((dpll &
1302 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
1303 DPLL_FPA01_P1_POST_DIV_SHIFT);
1304 if (clock.p1 == 0) {
1305 clock.p1 = 4;
1306 dev_err(dev->dev, "PLL %d\n", dpll);
1307 }
1308 clock.p2 = 14;
1309
1310 if ((dpll & PLL_REF_INPUT_MASK) ==
1311 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
1312 /* XXX: might not be 66MHz */
1313 i8xx_clock(66000, &clock);
1314 } else
1315 i8xx_clock(48000, &clock);
1316 } else {
1317 if (dpll & PLL_P1_DIVIDE_BY_TWO)
1318 clock.p1 = 2;
1319 else {
1320 clock.p1 =
1321 ((dpll &
1322 DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
1323 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
1324 }
1325 if (dpll & PLL_P2_DIVIDE_BY_4)
1326 clock.p2 = 4;
1327 else
1328 clock.p2 = 2;
1329
1330 i8xx_clock(48000, &clock);
1331 }
1332
1333 /* XXX: It would be nice to validate the clocks, but we can't reuse
1334 * i830PllIsValid() because it relies on the xf86_config connector
1335 * configuration being accurate, which it isn't necessarily.
1336 */
1337
1338 return clock.dot;
1339 }
1340
1341 /** Returns the currently programmed mode of the given pipe. */
1342 struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev,
1343 struct drm_crtc *crtc)
1344 {
1345 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1346 int pipe = psb_intel_crtc->pipe;
1347 struct drm_psb_private *dev_priv = dev->dev_private;
1348 struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
1349 const struct psb_offset *map = &dev_priv->regmap[pipe];
1350 struct drm_display_mode *mode;
1351 int htot;
1352 int hsync;
1353 int vtot;
1354 int vsync;
1355
1356 if (gma_power_begin(dev, false)) {
1357 htot = REG_READ(map->htotal);
1358 hsync = REG_READ(map->hsync);
1359 vtot = REG_READ(map->vtotal);
1360 vsync = REG_READ(map->vsync);
1361 gma_power_end(dev);
1362 } else {
1363 htot = p->htotal;
1364 hsync = p->hsync;
1365 vtot = p->vtotal;
1366 vsync = p->vsync;
1367 }
1368
1369 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
1370 if (!mode)
1371 return NULL;
1372
1373 mode->clock = cdv_intel_crtc_clock_get(dev, crtc);
1374 mode->hdisplay = (htot & 0xffff) + 1;
1375 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
1376 mode->hsync_start = (hsync & 0xffff) + 1;
1377 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
1378 mode->vdisplay = (vtot & 0xffff) + 1;
1379 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
1380 mode->vsync_start = (vsync & 0xffff) + 1;
1381 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
1382
1383 drm_mode_set_name(mode);
1384 drm_mode_set_crtcinfo(mode, 0);
1385
1386 return mode;
1387 }
1388
1389 const struct drm_crtc_helper_funcs cdv_intel_helper_funcs = {
1390 .dpms = gma_crtc_dpms,
1391 .mode_fixup = gma_crtc_mode_fixup,
1392 .mode_set = cdv_intel_crtc_mode_set,
1393 .mode_set_base = gma_pipe_set_base,
1394 .prepare = gma_crtc_prepare,
1395 .commit = gma_crtc_commit,
1396 .disable = gma_crtc_disable,
1397 };
1398
1399 const struct drm_crtc_funcs cdv_intel_crtc_funcs = {
1400 .save = cdv_intel_crtc_save,
1401 .restore = cdv_intel_crtc_restore,
1402 .cursor_set = cdv_intel_crtc_cursor_set,
1403 .cursor_move = cdv_intel_crtc_cursor_move,
1404 .gamma_set = cdv_intel_crtc_gamma_set,
1405 .set_config = cdv_crtc_set_config,
1406 .destroy = gma_crtc_destroy,
1407 };
1408
1409 const struct gma_clock_funcs cdv_clock_funcs = {
1410 .clock = cdv_intel_clock,
1411 .limit = cdv_intel_limit,
1412 .pll_is_valid = gma_pll_is_valid,
1413 };
Linux kernel - Deliverables
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