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drm/gma500: Convert to generic encoder funcs
[deliverable/linux.git] / drivers / gpu / drm / gma500 / cdv_intel_display.c
1 /*
2 * Copyright © 2006-2011 Intel Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc.,
15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
16 *
17 * Authors:
18 * Eric Anholt <eric@anholt.net>
19 */
20
21 #include <linux/i2c.h>
22 #include <linux/pm_runtime.h>
23
24 #include <drm/drmP.h>
25 #include "framebuffer.h"
26 #include "psb_drv.h"
27 #include "psb_intel_drv.h"
28 #include "psb_intel_reg.h"
29 #include "gma_display.h"
30 #include "power.h"
31 #include "cdv_device.h"
32
33 static bool cdv_intel_find_dp_pll(const struct gma_limit_t *limit,
34 struct drm_crtc *crtc, int target,
35 int refclk, struct gma_clock_t *best_clock);
36
37
38 #define CDV_LIMIT_SINGLE_LVDS_96 0
39 #define CDV_LIMIT_SINGLE_LVDS_100 1
40 #define CDV_LIMIT_DAC_HDMI_27 2
41 #define CDV_LIMIT_DAC_HDMI_96 3
42 #define CDV_LIMIT_DP_27 4
43 #define CDV_LIMIT_DP_100 5
44
45 static const struct gma_limit_t cdv_intel_limits[] = {
46 { /* CDV_SINGLE_LVDS_96MHz */
47 .dot = {.min = 20000, .max = 115500},
48 .vco = {.min = 1800000, .max = 3600000},
49 .n = {.min = 2, .max = 6},
50 .m = {.min = 60, .max = 160},
51 .m1 = {.min = 0, .max = 0},
52 .m2 = {.min = 58, .max = 158},
53 .p = {.min = 28, .max = 140},
54 .p1 = {.min = 2, .max = 10},
55 .p2 = {.dot_limit = 200000, .p2_slow = 14, .p2_fast = 14},
56 .find_pll = gma_find_best_pll,
57 },
58 { /* CDV_SINGLE_LVDS_100MHz */
59 .dot = {.min = 20000, .max = 115500},
60 .vco = {.min = 1800000, .max = 3600000},
61 .n = {.min = 2, .max = 6},
62 .m = {.min = 60, .max = 160},
63 .m1 = {.min = 0, .max = 0},
64 .m2 = {.min = 58, .max = 158},
65 .p = {.min = 28, .max = 140},
66 .p1 = {.min = 2, .max = 10},
67 /* The single-channel range is 25-112Mhz, and dual-channel
68 * is 80-224Mhz. Prefer single channel as much as possible.
69 */
70 .p2 = {.dot_limit = 200000, .p2_slow = 14, .p2_fast = 14},
71 .find_pll = gma_find_best_pll,
72 },
73 { /* CDV_DAC_HDMI_27MHz */
74 .dot = {.min = 20000, .max = 400000},
75 .vco = {.min = 1809000, .max = 3564000},
76 .n = {.min = 1, .max = 1},
77 .m = {.min = 67, .max = 132},
78 .m1 = {.min = 0, .max = 0},
79 .m2 = {.min = 65, .max = 130},
80 .p = {.min = 5, .max = 90},
81 .p1 = {.min = 1, .max = 9},
82 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5},
83 .find_pll = gma_find_best_pll,
84 },
85 { /* CDV_DAC_HDMI_96MHz */
86 .dot = {.min = 20000, .max = 400000},
87 .vco = {.min = 1800000, .max = 3600000},
88 .n = {.min = 2, .max = 6},
89 .m = {.min = 60, .max = 160},
90 .m1 = {.min = 0, .max = 0},
91 .m2 = {.min = 58, .max = 158},
92 .p = {.min = 5, .max = 100},
93 .p1 = {.min = 1, .max = 10},
94 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5},
95 .find_pll = gma_find_best_pll,
96 },
97 { /* CDV_DP_27MHz */
98 .dot = {.min = 160000, .max = 272000},
99 .vco = {.min = 1809000, .max = 3564000},
100 .n = {.min = 1, .max = 1},
101 .m = {.min = 67, .max = 132},
102 .m1 = {.min = 0, .max = 0},
103 .m2 = {.min = 65, .max = 130},
104 .p = {.min = 5, .max = 90},
105 .p1 = {.min = 1, .max = 9},
106 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 10},
107 .find_pll = cdv_intel_find_dp_pll,
108 },
109 { /* CDV_DP_100MHz */
110 .dot = {.min = 160000, .max = 272000},
111 .vco = {.min = 1800000, .max = 3600000},
112 .n = {.min = 2, .max = 6},
113 .m = {.min = 60, .max = 164},
114 .m1 = {.min = 0, .max = 0},
115 .m2 = {.min = 58, .max = 162},
116 .p = {.min = 5, .max = 100},
117 .p1 = {.min = 1, .max = 10},
118 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 10},
119 .find_pll = cdv_intel_find_dp_pll,
120 }
121 };
122
123 #define _wait_for(COND, MS, W) ({ \
124 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
125 int ret__ = 0; \
126 while (!(COND)) { \
127 if (time_after(jiffies, timeout__)) { \
128 ret__ = -ETIMEDOUT; \
129 break; \
130 } \
131 if (W && !in_dbg_master()) \
132 msleep(W); \
133 } \
134 ret__; \
135 })
136
137 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
138
139
140 int cdv_sb_read(struct drm_device *dev, u32 reg, u32 *val)
141 {
142 int ret;
143
144 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
145 if (ret) {
146 DRM_ERROR("timeout waiting for SB to idle before read\n");
147 return ret;
148 }
149
150 REG_WRITE(SB_ADDR, reg);
151 REG_WRITE(SB_PCKT,
152 SET_FIELD(SB_OPCODE_READ, SB_OPCODE) |
153 SET_FIELD(SB_DEST_DPLL, SB_DEST) |
154 SET_FIELD(0xf, SB_BYTE_ENABLE));
155
156 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
157 if (ret) {
158 DRM_ERROR("timeout waiting for SB to idle after read\n");
159 return ret;
160 }
161
162 *val = REG_READ(SB_DATA);
163
164 return 0;
165 }
166
167 int cdv_sb_write(struct drm_device *dev, u32 reg, u32 val)
168 {
169 int ret;
170 static bool dpio_debug = true;
171 u32 temp;
172
173 if (dpio_debug) {
174 if (cdv_sb_read(dev, reg, &temp) == 0)
175 DRM_DEBUG_KMS("0x%08x: 0x%08x (before)\n", reg, temp);
176 DRM_DEBUG_KMS("0x%08x: 0x%08x\n", reg, val);
177 }
178
179 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
180 if (ret) {
181 DRM_ERROR("timeout waiting for SB to idle before write\n");
182 return ret;
183 }
184
185 REG_WRITE(SB_ADDR, reg);
186 REG_WRITE(SB_DATA, val);
187 REG_WRITE(SB_PCKT,
188 SET_FIELD(SB_OPCODE_WRITE, SB_OPCODE) |
189 SET_FIELD(SB_DEST_DPLL, SB_DEST) |
190 SET_FIELD(0xf, SB_BYTE_ENABLE));
191
192 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
193 if (ret) {
194 DRM_ERROR("timeout waiting for SB to idle after write\n");
195 return ret;
196 }
197
198 if (dpio_debug) {
199 if (cdv_sb_read(dev, reg, &temp) == 0)
200 DRM_DEBUG_KMS("0x%08x: 0x%08x (after)\n", reg, temp);
201 }
202
203 return 0;
204 }
205
206 /* Reset the DPIO configuration register. The BIOS does this at every
207 * mode set.
208 */
209 void cdv_sb_reset(struct drm_device *dev)
210 {
211
212 REG_WRITE(DPIO_CFG, 0);
213 REG_READ(DPIO_CFG);
214 REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N);
215 }
216
217 /* Unlike most Intel display engines, on Cedarview the DPLL registers
218 * are behind this sideband bus. They must be programmed while the
219 * DPLL reference clock is on in the DPLL control register, but before
220 * the DPLL is enabled in the DPLL control register.
221 */
222 static int
223 cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc,
224 struct gma_clock_t *clock, bool is_lvds, u32 ddi_select)
225 {
226 struct psb_intel_crtc *psb_crtc = to_psb_intel_crtc(crtc);
227 int pipe = psb_crtc->pipe;
228 u32 m, n_vco, p;
229 int ret = 0;
230 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
231 int ref_sfr = (pipe == 0) ? SB_REF_DPLLA : SB_REF_DPLLB;
232 u32 ref_value;
233 u32 lane_reg, lane_value;
234
235 cdv_sb_reset(dev);
236
237 REG_WRITE(dpll_reg, DPLL_SYNCLOCK_ENABLE | DPLL_VGA_MODE_DIS);
238
239 udelay(100);
240
241 /* Follow the BIOS and write the REF/SFR Register. Hardcoded value */
242 ref_value = 0x68A701;
243
244 cdv_sb_write(dev, SB_REF_SFR(pipe), ref_value);
245
246 /* We don't know what the other fields of these regs are, so
247 * leave them in place.
248 */
249 /*
250 * The BIT 14:13 of 0x8010/0x8030 is used to select the ref clk
251 * for the pipe A/B. Display spec 1.06 has wrong definition.
252 * Correct definition is like below:
253 *
254 * refclka mean use clock from same PLL
255 *
256 * if DPLLA sets 01 and DPLLB sets 01, they use clock from their pll
257 *
258 * if DPLLA sets 01 and DPLLB sets 02, both use clk from DPLLA
259 *
260 */
261 ret = cdv_sb_read(dev, ref_sfr, &ref_value);
262 if (ret)
263 return ret;
264 ref_value &= ~(REF_CLK_MASK);
265
266 /* use DPLL_A for pipeB on CRT/HDMI */
267 if (pipe == 1 && !is_lvds && !(ddi_select & DP_MASK)) {
268 DRM_DEBUG_KMS("use DPLLA for pipe B\n");
269 ref_value |= REF_CLK_DPLLA;
270 } else {
271 DRM_DEBUG_KMS("use their DPLL for pipe A/B\n");
272 ref_value |= REF_CLK_DPLL;
273 }
274 ret = cdv_sb_write(dev, ref_sfr, ref_value);
275 if (ret)
276 return ret;
277
278 ret = cdv_sb_read(dev, SB_M(pipe), &m);
279 if (ret)
280 return ret;
281 m &= ~SB_M_DIVIDER_MASK;
282 m |= ((clock->m2) << SB_M_DIVIDER_SHIFT);
283 ret = cdv_sb_write(dev, SB_M(pipe), m);
284 if (ret)
285 return ret;
286
287 ret = cdv_sb_read(dev, SB_N_VCO(pipe), &n_vco);
288 if (ret)
289 return ret;
290
291 /* Follow the BIOS to program the N_DIVIDER REG */
292 n_vco &= 0xFFFF;
293 n_vco |= 0x107;
294 n_vco &= ~(SB_N_VCO_SEL_MASK |
295 SB_N_DIVIDER_MASK |
296 SB_N_CB_TUNE_MASK);
297
298 n_vco |= ((clock->n) << SB_N_DIVIDER_SHIFT);
299
300 if (clock->vco < 2250000) {
301 n_vco |= (2 << SB_N_CB_TUNE_SHIFT);
302 n_vco |= (0 << SB_N_VCO_SEL_SHIFT);
303 } else if (clock->vco < 2750000) {
304 n_vco |= (1 << SB_N_CB_TUNE_SHIFT);
305 n_vco |= (1 << SB_N_VCO_SEL_SHIFT);
306 } else if (clock->vco < 3300000) {
307 n_vco |= (0 << SB_N_CB_TUNE_SHIFT);
308 n_vco |= (2 << SB_N_VCO_SEL_SHIFT);
309 } else {
310 n_vco |= (0 << SB_N_CB_TUNE_SHIFT);
311 n_vco |= (3 << SB_N_VCO_SEL_SHIFT);
312 }
313
314 ret = cdv_sb_write(dev, SB_N_VCO(pipe), n_vco);
315 if (ret)
316 return ret;
317
318 ret = cdv_sb_read(dev, SB_P(pipe), &p);
319 if (ret)
320 return ret;
321 p &= ~(SB_P2_DIVIDER_MASK | SB_P1_DIVIDER_MASK);
322 p |= SET_FIELD(clock->p1, SB_P1_DIVIDER);
323 switch (clock->p2) {
324 case 5:
325 p |= SET_FIELD(SB_P2_5, SB_P2_DIVIDER);
326 break;
327 case 10:
328 p |= SET_FIELD(SB_P2_10, SB_P2_DIVIDER);
329 break;
330 case 14:
331 p |= SET_FIELD(SB_P2_14, SB_P2_DIVIDER);
332 break;
333 case 7:
334 p |= SET_FIELD(SB_P2_7, SB_P2_DIVIDER);
335 break;
336 default:
337 DRM_ERROR("Bad P2 clock: %d\n", clock->p2);
338 return -EINVAL;
339 }
340 ret = cdv_sb_write(dev, SB_P(pipe), p);
341 if (ret)
342 return ret;
343
344 if (ddi_select) {
345 if ((ddi_select & DDI_MASK) == DDI0_SELECT) {
346 lane_reg = PSB_LANE0;
347 cdv_sb_read(dev, lane_reg, &lane_value);
348 lane_value &= ~(LANE_PLL_MASK);
349 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
350 cdv_sb_write(dev, lane_reg, lane_value);
351
352 lane_reg = PSB_LANE1;
353 cdv_sb_read(dev, lane_reg, &lane_value);
354 lane_value &= ~(LANE_PLL_MASK);
355 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
356 cdv_sb_write(dev, lane_reg, lane_value);
357 } else {
358 lane_reg = PSB_LANE2;
359 cdv_sb_read(dev, lane_reg, &lane_value);
360 lane_value &= ~(LANE_PLL_MASK);
361 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
362 cdv_sb_write(dev, lane_reg, lane_value);
363
364 lane_reg = PSB_LANE3;
365 cdv_sb_read(dev, lane_reg, &lane_value);
366 lane_value &= ~(LANE_PLL_MASK);
367 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
368 cdv_sb_write(dev, lane_reg, lane_value);
369 }
370 }
371 return 0;
372 }
373
374 static const struct gma_limit_t *cdv_intel_limit(struct drm_crtc *crtc,
375 int refclk)
376 {
377 const struct gma_limit_t *limit;
378 if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
379 /*
380 * Now only single-channel LVDS is supported on CDV. If it is
381 * incorrect, please add the dual-channel LVDS.
382 */
383 if (refclk == 96000)
384 limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_96];
385 else
386 limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_100];
387 } else if (gma_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
388 gma_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
389 if (refclk == 27000)
390 limit = &cdv_intel_limits[CDV_LIMIT_DP_27];
391 else
392 limit = &cdv_intel_limits[CDV_LIMIT_DP_100];
393 } else {
394 if (refclk == 27000)
395 limit = &cdv_intel_limits[CDV_LIMIT_DAC_HDMI_27];
396 else
397 limit = &cdv_intel_limits[CDV_LIMIT_DAC_HDMI_96];
398 }
399 return limit;
400 }
401
402 /* m1 is reserved as 0 in CDV, n is a ring counter */
403 static void cdv_intel_clock(int refclk, struct gma_clock_t *clock)
404 {
405 clock->m = clock->m2 + 2;
406 clock->p = clock->p1 * clock->p2;
407 clock->vco = (refclk * clock->m) / clock->n;
408 clock->dot = clock->vco / clock->p;
409 }
410
411 static bool cdv_intel_find_dp_pll(const struct gma_limit_t *limit,
412 struct drm_crtc *crtc, int target,
413 int refclk,
414 struct gma_clock_t *best_clock)
415 {
416 struct gma_clock_t clock;
417 if (refclk == 27000) {
418 if (target < 200000) {
419 clock.p1 = 2;
420 clock.p2 = 10;
421 clock.n = 1;
422 clock.m1 = 0;
423 clock.m2 = 118;
424 } else {
425 clock.p1 = 1;
426 clock.p2 = 10;
427 clock.n = 1;
428 clock.m1 = 0;
429 clock.m2 = 98;
430 }
431 } else if (refclk == 100000) {
432 if (target < 200000) {
433 clock.p1 = 2;
434 clock.p2 = 10;
435 clock.n = 5;
436 clock.m1 = 0;
437 clock.m2 = 160;
438 } else {
439 clock.p1 = 1;
440 clock.p2 = 10;
441 clock.n = 5;
442 clock.m1 = 0;
443 clock.m2 = 133;
444 }
445 } else
446 return false;
447 clock.m = clock.m2 + 2;
448 clock.p = clock.p1 * clock.p2;
449 clock.vco = (refclk * clock.m) / clock.n;
450 clock.dot = clock.vco / clock.p;
451 memcpy(best_clock, &clock, sizeof(struct gma_clock_t));
452 return true;
453 }
454
455 #define FIFO_PIPEA (1 << 0)
456 #define FIFO_PIPEB (1 << 1)
457
458 static bool cdv_intel_pipe_enabled(struct drm_device *dev, int pipe)
459 {
460 struct drm_crtc *crtc;
461 struct drm_psb_private *dev_priv = dev->dev_private;
462 struct psb_intel_crtc *psb_intel_crtc = NULL;
463
464 crtc = dev_priv->pipe_to_crtc_mapping[pipe];
465 psb_intel_crtc = to_psb_intel_crtc(crtc);
466
467 if (crtc->fb == NULL || !psb_intel_crtc->active)
468 return false;
469 return true;
470 }
471
472 static bool cdv_intel_single_pipe_active (struct drm_device *dev)
473 {
474 uint32_t pipe_enabled = 0;
475
476 if (cdv_intel_pipe_enabled(dev, 0))
477 pipe_enabled |= FIFO_PIPEA;
478
479 if (cdv_intel_pipe_enabled(dev, 1))
480 pipe_enabled |= FIFO_PIPEB;
481
482
483 DRM_DEBUG_KMS("pipe enabled %x\n", pipe_enabled);
484
485 if (pipe_enabled == FIFO_PIPEA || pipe_enabled == FIFO_PIPEB)
486 return true;
487 else
488 return false;
489 }
490
491 static bool is_pipeb_lvds(struct drm_device *dev, struct drm_crtc *crtc)
492 {
493 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
494 struct drm_mode_config *mode_config = &dev->mode_config;
495 struct drm_connector *connector;
496
497 if (psb_intel_crtc->pipe != 1)
498 return false;
499
500 list_for_each_entry(connector, &mode_config->connector_list, head) {
501 struct psb_intel_encoder *psb_intel_encoder =
502 gma_attached_encoder(connector);
503
504 if (!connector->encoder
505 || connector->encoder->crtc != crtc)
506 continue;
507
508 if (psb_intel_encoder->type == INTEL_OUTPUT_LVDS)
509 return true;
510 }
511
512 return false;
513 }
514
515 void cdv_intel_disable_self_refresh(struct drm_device *dev)
516 {
517 if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) {
518
519 /* Disable self-refresh before adjust WM */
520 REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN));
521 REG_READ(FW_BLC_SELF);
522
523 gma_wait_for_vblank(dev);
524
525 /* Cedarview workaround to write ovelay plane, which force to leave
526 * MAX_FIFO state.
527 */
528 REG_WRITE(OV_OVADD, 0/*dev_priv->ovl_offset*/);
529 REG_READ(OV_OVADD);
530
531 gma_wait_for_vblank(dev);
532 }
533
534 }
535
536 void cdv_intel_update_watermark(struct drm_device *dev, struct drm_crtc *crtc)
537 {
538
539 if (cdv_intel_single_pipe_active(dev)) {
540 u32 fw;
541
542 fw = REG_READ(DSPFW1);
543 fw &= ~DSP_FIFO_SR_WM_MASK;
544 fw |= (0x7e << DSP_FIFO_SR_WM_SHIFT);
545 fw &= ~CURSOR_B_FIFO_WM_MASK;
546 fw |= (0x4 << CURSOR_B_FIFO_WM_SHIFT);
547 REG_WRITE(DSPFW1, fw);
548
549 fw = REG_READ(DSPFW2);
550 fw &= ~CURSOR_A_FIFO_WM_MASK;
551 fw |= (0x6 << CURSOR_A_FIFO_WM_SHIFT);
552 fw &= ~DSP_PLANE_C_FIFO_WM_MASK;
553 fw |= (0x8 << DSP_PLANE_C_FIFO_WM_SHIFT);
554 REG_WRITE(DSPFW2, fw);
555
556 REG_WRITE(DSPFW3, 0x36000000);
557
558 /* ignore FW4 */
559
560 if (is_pipeb_lvds(dev, crtc)) {
561 REG_WRITE(DSPFW5, 0x00040330);
562 } else {
563 fw = (3 << DSP_PLANE_B_FIFO_WM1_SHIFT) |
564 (4 << DSP_PLANE_A_FIFO_WM1_SHIFT) |
565 (3 << CURSOR_B_FIFO_WM1_SHIFT) |
566 (4 << CURSOR_FIFO_SR_WM1_SHIFT);
567 REG_WRITE(DSPFW5, fw);
568 }
569
570 REG_WRITE(DSPFW6, 0x10);
571
572 gma_wait_for_vblank(dev);
573
574 /* enable self-refresh for single pipe active */
575 REG_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
576 REG_READ(FW_BLC_SELF);
577 gma_wait_for_vblank(dev);
578
579 } else {
580
581 /* HW team suggested values... */
582 REG_WRITE(DSPFW1, 0x3f880808);
583 REG_WRITE(DSPFW2, 0x0b020202);
584 REG_WRITE(DSPFW3, 0x24000000);
585 REG_WRITE(DSPFW4, 0x08030202);
586 REG_WRITE(DSPFW5, 0x01010101);
587 REG_WRITE(DSPFW6, 0x1d0);
588
589 gma_wait_for_vblank(dev);
590
591 cdv_intel_disable_self_refresh(dev);
592
593 }
594 }
595
596 /**
597 * Return the pipe currently connected to the panel fitter,
598 * or -1 if the panel fitter is not present or not in use
599 */
600 static int cdv_intel_panel_fitter_pipe(struct drm_device *dev)
601 {
602 u32 pfit_control;
603
604 pfit_control = REG_READ(PFIT_CONTROL);
605
606 /* See if the panel fitter is in use */
607 if ((pfit_control & PFIT_ENABLE) == 0)
608 return -1;
609 return (pfit_control >> 29) & 0x3;
610 }
611
612 static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
613 struct drm_display_mode *mode,
614 struct drm_display_mode *adjusted_mode,
615 int x, int y,
616 struct drm_framebuffer *old_fb)
617 {
618 struct drm_device *dev = crtc->dev;
619 struct drm_psb_private *dev_priv = dev->dev_private;
620 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
621 int pipe = psb_intel_crtc->pipe;
622 const struct psb_offset *map = &dev_priv->regmap[pipe];
623 int refclk;
624 struct gma_clock_t clock;
625 u32 dpll = 0, dspcntr, pipeconf;
626 bool ok;
627 bool is_crt = false, is_lvds = false, is_tv = false;
628 bool is_hdmi = false, is_dp = false;
629 struct drm_mode_config *mode_config = &dev->mode_config;
630 struct drm_connector *connector;
631 const struct gma_limit_t *limit;
632 u32 ddi_select = 0;
633 bool is_edp = false;
634
635 list_for_each_entry(connector, &mode_config->connector_list, head) {
636 struct psb_intel_encoder *psb_intel_encoder =
637 gma_attached_encoder(connector);
638
639 if (!connector->encoder
640 || connector->encoder->crtc != crtc)
641 continue;
642
643 ddi_select = psb_intel_encoder->ddi_select;
644 switch (psb_intel_encoder->type) {
645 case INTEL_OUTPUT_LVDS:
646 is_lvds = true;
647 break;
648 case INTEL_OUTPUT_TVOUT:
649 is_tv = true;
650 break;
651 case INTEL_OUTPUT_ANALOG:
652 is_crt = true;
653 break;
654 case INTEL_OUTPUT_HDMI:
655 is_hdmi = true;
656 break;
657 case INTEL_OUTPUT_DISPLAYPORT:
658 is_dp = true;
659 break;
660 case INTEL_OUTPUT_EDP:
661 is_edp = true;
662 break;
663 default:
664 DRM_ERROR("invalid output type.\n");
665 return 0;
666 }
667 }
668
669 if (dev_priv->dplla_96mhz)
670 /* low-end sku, 96/100 mhz */
671 refclk = 96000;
672 else
673 /* high-end sku, 27/100 mhz */
674 refclk = 27000;
675 if (is_dp || is_edp) {
676 /*
677 * Based on the spec the low-end SKU has only CRT/LVDS. So it is
678 * unnecessary to consider it for DP/eDP.
679 * On the high-end SKU, it will use the 27/100M reference clk
680 * for DP/eDP. When using SSC clock, the ref clk is 100MHz.Otherwise
681 * it will be 27MHz. From the VBIOS code it seems that the pipe A choose
682 * 27MHz for DP/eDP while the Pipe B chooses the 100MHz.
683 */
684 if (pipe == 0)
685 refclk = 27000;
686 else
687 refclk = 100000;
688 }
689
690 if (is_lvds && dev_priv->lvds_use_ssc) {
691 refclk = dev_priv->lvds_ssc_freq * 1000;
692 DRM_DEBUG_KMS("Use SSC reference clock %d Mhz\n", dev_priv->lvds_ssc_freq);
693 }
694
695 drm_mode_debug_printmodeline(adjusted_mode);
696
697 limit = psb_intel_crtc->clock_funcs->limit(crtc, refclk);
698
699 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk,
700 &clock);
701 if (!ok) {
702 DRM_ERROR("Couldn't find PLL settings for mode! target: %d, actual: %d",
703 adjusted_mode->clock, clock.dot);
704 return 0;
705 }
706
707 dpll = DPLL_VGA_MODE_DIS;
708 if (is_tv) {
709 /* XXX: just matching BIOS for now */
710 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
711 dpll |= 3;
712 }
713 /* dpll |= PLL_REF_INPUT_DREFCLK; */
714
715 if (is_dp || is_edp) {
716 cdv_intel_dp_set_m_n(crtc, mode, adjusted_mode);
717 } else {
718 REG_WRITE(PIPE_GMCH_DATA_M(pipe), 0);
719 REG_WRITE(PIPE_GMCH_DATA_N(pipe), 0);
720 REG_WRITE(PIPE_DP_LINK_M(pipe), 0);
721 REG_WRITE(PIPE_DP_LINK_N(pipe), 0);
722 }
723
724 dpll |= DPLL_SYNCLOCK_ENABLE;
725 /* if (is_lvds)
726 dpll |= DPLLB_MODE_LVDS;
727 else
728 dpll |= DPLLB_MODE_DAC_SERIAL; */
729 /* dpll |= (2 << 11); */
730
731 /* setup pipeconf */
732 pipeconf = REG_READ(map->conf);
733
734 pipeconf &= ~(PIPE_BPC_MASK);
735 if (is_edp) {
736 switch (dev_priv->edp.bpp) {
737 case 24:
738 pipeconf |= PIPE_8BPC;
739 break;
740 case 18:
741 pipeconf |= PIPE_6BPC;
742 break;
743 case 30:
744 pipeconf |= PIPE_10BPC;
745 break;
746 default:
747 pipeconf |= PIPE_8BPC;
748 break;
749 }
750 } else if (is_lvds) {
751 /* the BPC will be 6 if it is 18-bit LVDS panel */
752 if ((REG_READ(LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
753 pipeconf |= PIPE_8BPC;
754 else
755 pipeconf |= PIPE_6BPC;
756 } else
757 pipeconf |= PIPE_8BPC;
758
759 /* Set up the display plane register */
760 dspcntr = DISPPLANE_GAMMA_ENABLE;
761
762 if (pipe == 0)
763 dspcntr |= DISPPLANE_SEL_PIPE_A;
764 else
765 dspcntr |= DISPPLANE_SEL_PIPE_B;
766
767 dspcntr |= DISPLAY_PLANE_ENABLE;
768 pipeconf |= PIPEACONF_ENABLE;
769
770 REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE);
771 REG_READ(map->dpll);
772
773 cdv_dpll_set_clock_cdv(dev, crtc, &clock, is_lvds, ddi_select);
774
775 udelay(150);
776
777
778 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
779 * This is an exception to the general rule that mode_set doesn't turn
780 * things on.
781 */
782 if (is_lvds) {
783 u32 lvds = REG_READ(LVDS);
784
785 lvds |=
786 LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP |
787 LVDS_PIPEB_SELECT;
788 /* Set the B0-B3 data pairs corresponding to
789 * whether we're going to
790 * set the DPLLs for dual-channel mode or not.
791 */
792 if (clock.p2 == 7)
793 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
794 else
795 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
796
797 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
798 * appropriately here, but we need to look more
799 * thoroughly into how panels behave in the two modes.
800 */
801
802 REG_WRITE(LVDS, lvds);
803 REG_READ(LVDS);
804 }
805
806 dpll |= DPLL_VCO_ENABLE;
807
808 /* Disable the panel fitter if it was on our pipe */
809 if (cdv_intel_panel_fitter_pipe(dev) == pipe)
810 REG_WRITE(PFIT_CONTROL, 0);
811
812 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
813 drm_mode_debug_printmodeline(mode);
814
815 REG_WRITE(map->dpll,
816 (REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE);
817 REG_READ(map->dpll);
818 /* Wait for the clocks to stabilize. */
819 udelay(150); /* 42 usec w/o calibration, 110 with. rounded up. */
820
821 if (!(REG_READ(map->dpll) & DPLL_LOCK)) {
822 dev_err(dev->dev, "Failed to get DPLL lock\n");
823 return -EBUSY;
824 }
825
826 {
827 int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
828 REG_WRITE(map->dpll_md, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
829 }
830
831 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |
832 ((adjusted_mode->crtc_htotal - 1) << 16));
833 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |
834 ((adjusted_mode->crtc_hblank_end - 1) << 16));
835 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |
836 ((adjusted_mode->crtc_hsync_end - 1) << 16));
837 REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |
838 ((adjusted_mode->crtc_vtotal - 1) << 16));
839 REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |
840 ((adjusted_mode->crtc_vblank_end - 1) << 16));
841 REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |
842 ((adjusted_mode->crtc_vsync_end - 1) << 16));
843 /* pipesrc and dspsize control the size that is scaled from,
844 * which should always be the user's requested size.
845 */
846 REG_WRITE(map->size,
847 ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
848 REG_WRITE(map->pos, 0);
849 REG_WRITE(map->src,
850 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
851 REG_WRITE(map->conf, pipeconf);
852 REG_READ(map->conf);
853
854 gma_wait_for_vblank(dev);
855
856 REG_WRITE(map->cntr, dspcntr);
857
858 /* Flush the plane changes */
859 {
860 struct drm_crtc_helper_funcs *crtc_funcs =
861 crtc->helper_private;
862 crtc_funcs->mode_set_base(crtc, x, y, old_fb);
863 }
864
865 gma_wait_for_vblank(dev);
866
867 return 0;
868 }
869
870
871 /**
872 * Save HW states of giving crtc
873 */
874 static void cdv_intel_crtc_save(struct drm_crtc *crtc)
875 {
876 struct drm_device *dev = crtc->dev;
877 struct drm_psb_private *dev_priv = dev->dev_private;
878 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
879 struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state;
880 const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe];
881 uint32_t paletteReg;
882 int i;
883
884 if (!crtc_state) {
885 dev_dbg(dev->dev, "No CRTC state found\n");
886 return;
887 }
888
889 crtc_state->saveDSPCNTR = REG_READ(map->cntr);
890 crtc_state->savePIPECONF = REG_READ(map->conf);
891 crtc_state->savePIPESRC = REG_READ(map->src);
892 crtc_state->saveFP0 = REG_READ(map->fp0);
893 crtc_state->saveFP1 = REG_READ(map->fp1);
894 crtc_state->saveDPLL = REG_READ(map->dpll);
895 crtc_state->saveHTOTAL = REG_READ(map->htotal);
896 crtc_state->saveHBLANK = REG_READ(map->hblank);
897 crtc_state->saveHSYNC = REG_READ(map->hsync);
898 crtc_state->saveVTOTAL = REG_READ(map->vtotal);
899 crtc_state->saveVBLANK = REG_READ(map->vblank);
900 crtc_state->saveVSYNC = REG_READ(map->vsync);
901 crtc_state->saveDSPSTRIDE = REG_READ(map->stride);
902
903 /*NOTE: DSPSIZE DSPPOS only for psb*/
904 crtc_state->saveDSPSIZE = REG_READ(map->size);
905 crtc_state->saveDSPPOS = REG_READ(map->pos);
906
907 crtc_state->saveDSPBASE = REG_READ(map->base);
908
909 DRM_DEBUG("(%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n",
910 crtc_state->saveDSPCNTR,
911 crtc_state->savePIPECONF,
912 crtc_state->savePIPESRC,
913 crtc_state->saveFP0,
914 crtc_state->saveFP1,
915 crtc_state->saveDPLL,
916 crtc_state->saveHTOTAL,
917 crtc_state->saveHBLANK,
918 crtc_state->saveHSYNC,
919 crtc_state->saveVTOTAL,
920 crtc_state->saveVBLANK,
921 crtc_state->saveVSYNC,
922 crtc_state->saveDSPSTRIDE,
923 crtc_state->saveDSPSIZE,
924 crtc_state->saveDSPPOS,
925 crtc_state->saveDSPBASE
926 );
927
928 paletteReg = map->palette;
929 for (i = 0; i < 256; ++i)
930 crtc_state->savePalette[i] = REG_READ(paletteReg + (i << 2));
931 }
932
933 /**
934 * Restore HW states of giving crtc
935 */
936 static void cdv_intel_crtc_restore(struct drm_crtc *crtc)
937 {
938 struct drm_device *dev = crtc->dev;
939 struct drm_psb_private *dev_priv = dev->dev_private;
940 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
941 struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state;
942 const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe];
943 uint32_t paletteReg;
944 int i;
945
946 if (!crtc_state) {
947 dev_dbg(dev->dev, "No crtc state\n");
948 return;
949 }
950
951 DRM_DEBUG(
952 "current:(%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n",
953 REG_READ(map->cntr),
954 REG_READ(map->conf),
955 REG_READ(map->src),
956 REG_READ(map->fp0),
957 REG_READ(map->fp1),
958 REG_READ(map->dpll),
959 REG_READ(map->htotal),
960 REG_READ(map->hblank),
961 REG_READ(map->hsync),
962 REG_READ(map->vtotal),
963 REG_READ(map->vblank),
964 REG_READ(map->vsync),
965 REG_READ(map->stride),
966 REG_READ(map->size),
967 REG_READ(map->pos),
968 REG_READ(map->base)
969 );
970
971 DRM_DEBUG(
972 "saved: (%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n",
973 crtc_state->saveDSPCNTR,
974 crtc_state->savePIPECONF,
975 crtc_state->savePIPESRC,
976 crtc_state->saveFP0,
977 crtc_state->saveFP1,
978 crtc_state->saveDPLL,
979 crtc_state->saveHTOTAL,
980 crtc_state->saveHBLANK,
981 crtc_state->saveHSYNC,
982 crtc_state->saveVTOTAL,
983 crtc_state->saveVBLANK,
984 crtc_state->saveVSYNC,
985 crtc_state->saveDSPSTRIDE,
986 crtc_state->saveDSPSIZE,
987 crtc_state->saveDSPPOS,
988 crtc_state->saveDSPBASE
989 );
990
991
992 if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) {
993 REG_WRITE(map->dpll,
994 crtc_state->saveDPLL & ~DPLL_VCO_ENABLE);
995 REG_READ(map->dpll);
996 DRM_DEBUG("write dpll: %x\n",
997 REG_READ(map->dpll));
998 udelay(150);
999 }
1000
1001 REG_WRITE(map->fp0, crtc_state->saveFP0);
1002 REG_READ(map->fp0);
1003
1004 REG_WRITE(map->fp1, crtc_state->saveFP1);
1005 REG_READ(map->fp1);
1006
1007 REG_WRITE(map->dpll, crtc_state->saveDPLL);
1008 REG_READ(map->dpll);
1009 udelay(150);
1010
1011 REG_WRITE(map->htotal, crtc_state->saveHTOTAL);
1012 REG_WRITE(map->hblank, crtc_state->saveHBLANK);
1013 REG_WRITE(map->hsync, crtc_state->saveHSYNC);
1014 REG_WRITE(map->vtotal, crtc_state->saveVTOTAL);
1015 REG_WRITE(map->vblank, crtc_state->saveVBLANK);
1016 REG_WRITE(map->vsync, crtc_state->saveVSYNC);
1017 REG_WRITE(map->stride, crtc_state->saveDSPSTRIDE);
1018
1019 REG_WRITE(map->size, crtc_state->saveDSPSIZE);
1020 REG_WRITE(map->pos, crtc_state->saveDSPPOS);
1021
1022 REG_WRITE(map->src, crtc_state->savePIPESRC);
1023 REG_WRITE(map->base, crtc_state->saveDSPBASE);
1024 REG_WRITE(map->conf, crtc_state->savePIPECONF);
1025
1026 gma_wait_for_vblank(dev);
1027
1028 REG_WRITE(map->cntr, crtc_state->saveDSPCNTR);
1029 REG_WRITE(map->base, crtc_state->saveDSPBASE);
1030
1031 gma_wait_for_vblank(dev);
1032
1033 paletteReg = map->palette;
1034 for (i = 0; i < 256; ++i)
1035 REG_WRITE(paletteReg + (i << 2), crtc_state->savePalette[i]);
1036 }
1037
1038 static int cdv_crtc_set_config(struct drm_mode_set *set)
1039 {
1040 int ret = 0;
1041 struct drm_device *dev = set->crtc->dev;
1042 struct drm_psb_private *dev_priv = dev->dev_private;
1043
1044 if (!dev_priv->rpm_enabled)
1045 return drm_crtc_helper_set_config(set);
1046
1047 pm_runtime_forbid(&dev->pdev->dev);
1048
1049 ret = drm_crtc_helper_set_config(set);
1050
1051 pm_runtime_allow(&dev->pdev->dev);
1052
1053 return ret;
1054 }
1055
1056 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
1057
1058 /* FIXME: why are we using this, should it be cdv_ in this tree ? */
1059
1060 static void i8xx_clock(int refclk, struct gma_clock_t *clock)
1061 {
1062 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
1063 clock->p = clock->p1 * clock->p2;
1064 clock->vco = refclk * clock->m / (clock->n + 2);
1065 clock->dot = clock->vco / clock->p;
1066 }
1067
1068 /* Returns the clock of the currently programmed mode of the given pipe. */
1069 static int cdv_intel_crtc_clock_get(struct drm_device *dev,
1070 struct drm_crtc *crtc)
1071 {
1072 struct drm_psb_private *dev_priv = dev->dev_private;
1073 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1074 int pipe = psb_intel_crtc->pipe;
1075 const struct psb_offset *map = &dev_priv->regmap[pipe];
1076 u32 dpll;
1077 u32 fp;
1078 struct gma_clock_t clock;
1079 bool is_lvds;
1080 struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
1081
1082 if (gma_power_begin(dev, false)) {
1083 dpll = REG_READ(map->dpll);
1084 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
1085 fp = REG_READ(map->fp0);
1086 else
1087 fp = REG_READ(map->fp1);
1088 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);
1089 gma_power_end(dev);
1090 } else {
1091 dpll = p->dpll;
1092 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
1093 fp = p->fp0;
1094 else
1095 fp = p->fp1;
1096
1097 is_lvds = (pipe == 1) &&
1098 (dev_priv->regs.psb.saveLVDS & LVDS_PORT_EN);
1099 }
1100
1101 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
1102 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
1103 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
1104
1105 if (is_lvds) {
1106 clock.p1 =
1107 ffs((dpll &
1108 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
1109 DPLL_FPA01_P1_POST_DIV_SHIFT);
1110 if (clock.p1 == 0) {
1111 clock.p1 = 4;
1112 dev_err(dev->dev, "PLL %d\n", dpll);
1113 }
1114 clock.p2 = 14;
1115
1116 if ((dpll & PLL_REF_INPUT_MASK) ==
1117 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
1118 /* XXX: might not be 66MHz */
1119 i8xx_clock(66000, &clock);
1120 } else
1121 i8xx_clock(48000, &clock);
1122 } else {
1123 if (dpll & PLL_P1_DIVIDE_BY_TWO)
1124 clock.p1 = 2;
1125 else {
1126 clock.p1 =
1127 ((dpll &
1128 DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
1129 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
1130 }
1131 if (dpll & PLL_P2_DIVIDE_BY_4)
1132 clock.p2 = 4;
1133 else
1134 clock.p2 = 2;
1135
1136 i8xx_clock(48000, &clock);
1137 }
1138
1139 /* XXX: It would be nice to validate the clocks, but we can't reuse
1140 * i830PllIsValid() because it relies on the xf86_config connector
1141 * configuration being accurate, which it isn't necessarily.
1142 */
1143
1144 return clock.dot;
1145 }
1146
1147 /** Returns the currently programmed mode of the given pipe. */
1148 struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev,
1149 struct drm_crtc *crtc)
1150 {
1151 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1152 int pipe = psb_intel_crtc->pipe;
1153 struct drm_psb_private *dev_priv = dev->dev_private;
1154 struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
1155 const struct psb_offset *map = &dev_priv->regmap[pipe];
1156 struct drm_display_mode *mode;
1157 int htot;
1158 int hsync;
1159 int vtot;
1160 int vsync;
1161
1162 if (gma_power_begin(dev, false)) {
1163 htot = REG_READ(map->htotal);
1164 hsync = REG_READ(map->hsync);
1165 vtot = REG_READ(map->vtotal);
1166 vsync = REG_READ(map->vsync);
1167 gma_power_end(dev);
1168 } else {
1169 htot = p->htotal;
1170 hsync = p->hsync;
1171 vtot = p->vtotal;
1172 vsync = p->vsync;
1173 }
1174
1175 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
1176 if (!mode)
1177 return NULL;
1178
1179 mode->clock = cdv_intel_crtc_clock_get(dev, crtc);
1180 mode->hdisplay = (htot & 0xffff) + 1;
1181 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
1182 mode->hsync_start = (hsync & 0xffff) + 1;
1183 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
1184 mode->vdisplay = (vtot & 0xffff) + 1;
1185 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
1186 mode->vsync_start = (vsync & 0xffff) + 1;
1187 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
1188
1189 drm_mode_set_name(mode);
1190 drm_mode_set_crtcinfo(mode, 0);
1191
1192 return mode;
1193 }
1194
1195 const struct drm_crtc_helper_funcs cdv_intel_helper_funcs = {
1196 .dpms = gma_crtc_dpms,
1197 .mode_fixup = gma_crtc_mode_fixup,
1198 .mode_set = cdv_intel_crtc_mode_set,
1199 .mode_set_base = gma_pipe_set_base,
1200 .prepare = gma_crtc_prepare,
1201 .commit = gma_crtc_commit,
1202 .disable = gma_crtc_disable,
1203 };
1204
1205 const struct drm_crtc_funcs cdv_intel_crtc_funcs = {
1206 .save = cdv_intel_crtc_save,
1207 .restore = cdv_intel_crtc_restore,
1208 .cursor_set = gma_crtc_cursor_set,
1209 .cursor_move = gma_crtc_cursor_move,
1210 .gamma_set = gma_crtc_gamma_set,
1211 .set_config = cdv_crtc_set_config,
1212 .destroy = gma_crtc_destroy,
1213 };
1214
1215 const struct gma_clock_funcs cdv_clock_funcs = {
1216 .clock = cdv_intel_clock,
1217 .limit = cdv_intel_limit,
1218 .pll_is_valid = gma_pll_is_valid,
1219 };
Linux kernel - Deliverables
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