2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/module.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
35 #include "psb_intel_drv.h"
36 #include "psb_intel_reg.h"
37 #include <drm/drm_dp_helper.h>
39 #define _wait_for(COND, MS, W) ({ \
40 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
43 if (time_after(jiffies, timeout__)) { \
47 if (W && !in_dbg_master()) msleep(W); \
52 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
54 #define DP_LINK_STATUS_SIZE 6
55 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
57 #define DP_LINK_CONFIGURATION_SIZE 9
59 #define CDV_FAST_LINK_TRAIN 1
64 uint8_t link_configuration
[DP_LINK_CONFIGURATION_SIZE
];
71 struct psb_intel_encoder
*encoder
;
72 struct i2c_adapter adapter
;
73 struct i2c_algo_dp_aux_data algo
;
75 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
76 int panel_power_up_delay
;
77 int panel_power_down_delay
;
78 int panel_power_cycle_delay
;
79 int backlight_on_delay
;
80 int backlight_off_delay
;
81 struct drm_display_mode
*panel_fixed_mode
; /* for eDP */
95 static struct ddi_regoff ddi_DP_train_table
[] = {
96 {.PreEmph1
= 0x812c, .PreEmph2
= 0x8124, .VSwing1
= 0x8154,
97 .VSwing2
= 0x8148, .VSwing3
= 0x814C, .VSwing4
= 0x8150,
99 {.PreEmph1
= 0x822c, .PreEmph2
= 0x8224, .VSwing1
= 0x8254,
100 .VSwing2
= 0x8248, .VSwing3
= 0x824C, .VSwing4
= 0x8250,
104 static uint32_t dp_vswing_premph_table
[] = {
111 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
112 * @intel_dp: DP struct
114 * If a CPU or PCH DP output is attached to an eDP panel, this function
115 * will return true, and false otherwise.
117 static bool is_edp(struct psb_intel_encoder
*encoder
)
119 return encoder
->type
== INTEL_OUTPUT_EDP
;
123 static void cdv_intel_dp_start_link_train(struct psb_intel_encoder
*encoder
);
124 static void cdv_intel_dp_complete_link_train(struct psb_intel_encoder
*encoder
);
125 static void cdv_intel_dp_link_down(struct psb_intel_encoder
*encoder
);
128 cdv_intel_dp_max_lane_count(struct psb_intel_encoder
*encoder
)
130 struct cdv_intel_dp
*intel_dp
= encoder
->dev_priv
;
131 int max_lane_count
= 4;
133 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
134 max_lane_count
= intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & 0x1f;
135 switch (max_lane_count
) {
136 case 1: case 2: case 4:
142 return max_lane_count
;
146 cdv_intel_dp_max_link_bw(struct psb_intel_encoder
*encoder
)
148 struct cdv_intel_dp
*intel_dp
= encoder
->dev_priv
;
149 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
151 switch (max_link_bw
) {
152 case DP_LINK_BW_1_62
:
156 max_link_bw
= DP_LINK_BW_1_62
;
163 cdv_intel_dp_link_clock(uint8_t link_bw
)
165 if (link_bw
== DP_LINK_BW_2_7
)
172 cdv_intel_dp_link_required(int pixel_clock
, int bpp
)
174 return (pixel_clock
* bpp
+ 7) / 8;
178 cdv_intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
180 return (max_link_clock
* max_lanes
* 19) / 20;
183 static void cdv_intel_edp_panel_vdd_on(struct psb_intel_encoder
*intel_encoder
)
185 struct drm_device
*dev
= intel_encoder
->base
.dev
;
186 struct cdv_intel_dp
*intel_dp
= intel_encoder
->dev_priv
;
189 if (intel_dp
->panel_on
) {
190 DRM_DEBUG_KMS("Skip VDD on because of panel on\n");
195 pp
= REG_READ(PP_CONTROL
);
198 REG_WRITE(PP_CONTROL
, pp
);
199 REG_READ(PP_CONTROL
);
200 msleep(intel_dp
->panel_power_up_delay
);
203 static void cdv_intel_edp_panel_vdd_off(struct psb_intel_encoder
*intel_encoder
)
205 struct drm_device
*dev
= intel_encoder
->base
.dev
;
209 pp
= REG_READ(PP_CONTROL
);
211 pp
&= ~EDP_FORCE_VDD
;
212 REG_WRITE(PP_CONTROL
, pp
);
213 REG_READ(PP_CONTROL
);
217 /* Returns true if the panel was already on when called */
218 static bool cdv_intel_edp_panel_on(struct psb_intel_encoder
*intel_encoder
)
220 struct drm_device
*dev
= intel_encoder
->base
.dev
;
221 struct cdv_intel_dp
*intel_dp
= intel_encoder
->dev_priv
;
222 u32 pp
, idle_on_mask
= PP_ON
| PP_SEQUENCE_NONE
;
224 if (intel_dp
->panel_on
)
228 pp
= REG_READ(PP_CONTROL
);
229 pp
&= ~PANEL_UNLOCK_MASK
;
231 pp
|= (PANEL_UNLOCK_REGS
| POWER_TARGET_ON
);
232 REG_WRITE(PP_CONTROL
, pp
);
233 REG_READ(PP_CONTROL
);
235 if (wait_for(((REG_READ(PP_STATUS
) & idle_on_mask
) == idle_on_mask
), 1000)) {
236 DRM_DEBUG_KMS("Error in Powering up eDP panel, status %x\n", REG_READ(PP_STATUS
));
237 intel_dp
->panel_on
= false;
239 intel_dp
->panel_on
= true;
240 msleep(intel_dp
->panel_power_up_delay
);
245 static void cdv_intel_edp_panel_off (struct psb_intel_encoder
*intel_encoder
)
247 struct drm_device
*dev
= intel_encoder
->base
.dev
;
248 u32 pp
, idle_off_mask
= PP_ON
;
249 struct cdv_intel_dp
*intel_dp
= intel_encoder
->dev_priv
;
253 pp
= REG_READ(PP_CONTROL
);
255 if ((pp
& POWER_TARGET_ON
) == 0)
258 intel_dp
->panel_on
= false;
259 pp
&= ~PANEL_UNLOCK_MASK
;
260 /* ILK workaround: disable reset around power sequence */
262 pp
&= ~POWER_TARGET_ON
;
263 pp
&= ~EDP_FORCE_VDD
;
264 pp
&= ~EDP_BLC_ENABLE
;
265 REG_WRITE(PP_CONTROL
, pp
);
266 REG_READ(PP_CONTROL
);
267 DRM_DEBUG_KMS("PP_STATUS %x\n", REG_READ(PP_STATUS
));
269 if (wait_for((REG_READ(PP_STATUS
) & idle_off_mask
) == 0, 1000)) {
270 DRM_DEBUG_KMS("Error in turning off Panel\n");
273 msleep(intel_dp
->panel_power_cycle_delay
);
274 DRM_DEBUG_KMS("Over\n");
277 static void cdv_intel_edp_backlight_on (struct psb_intel_encoder
*intel_encoder
)
279 struct drm_device
*dev
= intel_encoder
->base
.dev
;
284 * If we enable the backlight right away following a panel power
285 * on, we may see slight flicker as the panel syncs with the eDP
286 * link. So delay a bit to make sure the image is solid before
287 * allowing it to appear.
290 pp
= REG_READ(PP_CONTROL
);
292 pp
|= EDP_BLC_ENABLE
;
293 REG_WRITE(PP_CONTROL
, pp
);
294 gma_backlight_enable(dev
);
297 static void cdv_intel_edp_backlight_off (struct psb_intel_encoder
*intel_encoder
)
299 struct drm_device
*dev
= intel_encoder
->base
.dev
;
300 struct cdv_intel_dp
*intel_dp
= intel_encoder
->dev_priv
;
304 gma_backlight_disable(dev
);
306 pp
= REG_READ(PP_CONTROL
);
308 pp
&= ~EDP_BLC_ENABLE
;
309 REG_WRITE(PP_CONTROL
, pp
);
310 msleep(intel_dp
->backlight_off_delay
);
314 cdv_intel_dp_mode_valid(struct drm_connector
*connector
,
315 struct drm_display_mode
*mode
)
317 struct psb_intel_encoder
*encoder
= psb_intel_attached_encoder(connector
);
318 struct cdv_intel_dp
*intel_dp
= encoder
->dev_priv
;
319 int max_link_clock
= cdv_intel_dp_link_clock(cdv_intel_dp_max_link_bw(encoder
));
320 int max_lanes
= cdv_intel_dp_max_lane_count(encoder
);
321 struct drm_psb_private
*dev_priv
= connector
->dev
->dev_private
;
323 if (is_edp(encoder
) && intel_dp
->panel_fixed_mode
) {
324 if (mode
->hdisplay
> intel_dp
->panel_fixed_mode
->hdisplay
)
326 if (mode
->vdisplay
> intel_dp
->panel_fixed_mode
->vdisplay
)
330 /* only refuse the mode on non eDP since we have seen some weird eDP panels
331 which are outside spec tolerances but somehow work by magic */
332 if (!is_edp(encoder
) &&
333 (cdv_intel_dp_link_required(mode
->clock
, dev_priv
->edp
.bpp
)
334 > cdv_intel_dp_max_data_rate(max_link_clock
, max_lanes
)))
335 return MODE_CLOCK_HIGH
;
337 if (is_edp(encoder
)) {
338 if (cdv_intel_dp_link_required(mode
->clock
, 24)
339 > cdv_intel_dp_max_data_rate(max_link_clock
, max_lanes
))
340 return MODE_CLOCK_HIGH
;
343 if (mode
->clock
< 10000)
344 return MODE_CLOCK_LOW
;
350 pack_aux(uint8_t *src
, int src_bytes
)
357 for (i
= 0; i
< src_bytes
; i
++)
358 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
363 unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
368 for (i
= 0; i
< dst_bytes
; i
++)
369 dst
[i
] = src
>> ((3-i
) * 8);
373 cdv_intel_dp_aux_ch(struct psb_intel_encoder
*encoder
,
374 uint8_t *send
, int send_bytes
,
375 uint8_t *recv
, int recv_size
)
377 struct cdv_intel_dp
*intel_dp
= encoder
->dev_priv
;
378 uint32_t output_reg
= intel_dp
->output_reg
;
379 struct drm_device
*dev
= encoder
->base
.dev
;
380 uint32_t ch_ctl
= output_reg
+ 0x10;
381 uint32_t ch_data
= ch_ctl
+ 4;
385 uint32_t aux_clock_divider
;
388 /* The clock divider is based off the hrawclk,
389 * and would like to run at 2MHz. So, take the
390 * hrawclk value and divide by 2 and use that
391 * On CDV platform it uses 200MHz as hrawclk.
394 aux_clock_divider
= 200 / 2;
400 if (REG_READ(ch_ctl
) & DP_AUX_CH_CTL_SEND_BUSY
) {
401 DRM_ERROR("dp_aux_ch not started status 0x%08x\n",
406 /* Must try at least 3 times according to DP spec */
407 for (try = 0; try < 5; try++) {
408 /* Load the send data into the aux channel data registers */
409 for (i
= 0; i
< send_bytes
; i
+= 4)
410 REG_WRITE(ch_data
+ i
,
411 pack_aux(send
+ i
, send_bytes
- i
));
413 /* Send the command and wait for it to complete */
415 DP_AUX_CH_CTL_SEND_BUSY
|
416 DP_AUX_CH_CTL_TIME_OUT_400us
|
417 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
418 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
419 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
) |
421 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
422 DP_AUX_CH_CTL_RECEIVE_ERROR
);
424 status
= REG_READ(ch_ctl
);
425 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
430 /* Clear done status and any errors */
434 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
435 DP_AUX_CH_CTL_RECEIVE_ERROR
);
436 if (status
& DP_AUX_CH_CTL_DONE
)
440 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
441 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
445 /* Check for timeout or receive error.
446 * Timeouts occur when the sink is not connected
448 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
449 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
453 /* Timeouts occur when the device isn't connected, so they're
454 * "normal" -- don't fill the kernel log with these */
455 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
456 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
460 /* Unload any bytes sent back from the other side */
461 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
462 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
463 if (recv_bytes
> recv_size
)
464 recv_bytes
= recv_size
;
466 for (i
= 0; i
< recv_bytes
; i
+= 4)
467 unpack_aux(REG_READ(ch_data
+ i
),
468 recv
+ i
, recv_bytes
- i
);
473 /* Write data to the aux channel in native mode */
475 cdv_intel_dp_aux_native_write(struct psb_intel_encoder
*encoder
,
476 uint16_t address
, uint8_t *send
, int send_bytes
)
485 msg
[0] = AUX_NATIVE_WRITE
<< 4;
486 msg
[1] = address
>> 8;
487 msg
[2] = address
& 0xff;
488 msg
[3] = send_bytes
- 1;
489 memcpy(&msg
[4], send
, send_bytes
);
490 msg_bytes
= send_bytes
+ 4;
492 ret
= cdv_intel_dp_aux_ch(encoder
, msg
, msg_bytes
, &ack
, 1);
495 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
)
497 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
505 /* Write a single byte to the aux channel in native mode */
507 cdv_intel_dp_aux_native_write_1(struct psb_intel_encoder
*encoder
,
508 uint16_t address
, uint8_t byte
)
510 return cdv_intel_dp_aux_native_write(encoder
, address
, &byte
, 1);
513 /* read bytes from a native aux channel */
515 cdv_intel_dp_aux_native_read(struct psb_intel_encoder
*encoder
,
516 uint16_t address
, uint8_t *recv
, int recv_bytes
)
525 msg
[0] = AUX_NATIVE_READ
<< 4;
526 msg
[1] = address
>> 8;
527 msg
[2] = address
& 0xff;
528 msg
[3] = recv_bytes
- 1;
531 reply_bytes
= recv_bytes
+ 1;
534 ret
= cdv_intel_dp_aux_ch(encoder
, msg
, msg_bytes
,
541 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
) {
542 memcpy(recv
, reply
+ 1, ret
- 1);
545 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
553 cdv_intel_dp_i2c_aux_ch(struct i2c_adapter
*adapter
, int mode
,
554 uint8_t write_byte
, uint8_t *read_byte
)
556 struct i2c_algo_dp_aux_data
*algo_data
= adapter
->algo_data
;
557 struct cdv_intel_dp
*intel_dp
= container_of(adapter
,
560 struct psb_intel_encoder
*encoder
= intel_dp
->encoder
;
561 uint16_t address
= algo_data
->address
;
569 /* Set up the command byte */
570 if (mode
& MODE_I2C_READ
)
571 msg
[0] = AUX_I2C_READ
<< 4;
573 msg
[0] = AUX_I2C_WRITE
<< 4;
575 if (!(mode
& MODE_I2C_STOP
))
576 msg
[0] |= AUX_I2C_MOT
<< 4;
578 msg
[1] = address
>> 8;
599 for (retry
= 0; retry
< 5; retry
++) {
600 ret
= cdv_intel_dp_aux_ch(encoder
,
604 DRM_DEBUG_KMS("aux_ch failed %d\n", ret
);
608 switch (reply
[0] & AUX_NATIVE_REPLY_MASK
) {
609 case AUX_NATIVE_REPLY_ACK
:
610 /* I2C-over-AUX Reply field is only valid
611 * when paired with AUX ACK.
614 case AUX_NATIVE_REPLY_NACK
:
615 DRM_DEBUG_KMS("aux_ch native nack\n");
617 case AUX_NATIVE_REPLY_DEFER
:
621 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
626 switch (reply
[0] & AUX_I2C_REPLY_MASK
) {
627 case AUX_I2C_REPLY_ACK
:
628 if (mode
== MODE_I2C_READ
) {
629 *read_byte
= reply
[1];
631 return reply_bytes
- 1;
632 case AUX_I2C_REPLY_NACK
:
633 DRM_DEBUG_KMS("aux_i2c nack\n");
635 case AUX_I2C_REPLY_DEFER
:
636 DRM_DEBUG_KMS("aux_i2c defer\n");
640 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply
[0]);
645 DRM_ERROR("too many retries, giving up\n");
650 cdv_intel_dp_i2c_init(struct psb_intel_connector
*connector
, struct psb_intel_encoder
*encoder
, const char *name
)
652 struct cdv_intel_dp
*intel_dp
= encoder
->dev_priv
;
655 DRM_DEBUG_KMS("i2c_init %s\n", name
);
657 intel_dp
->algo
.running
= false;
658 intel_dp
->algo
.address
= 0;
659 intel_dp
->algo
.aux_ch
= cdv_intel_dp_i2c_aux_ch
;
661 memset(&intel_dp
->adapter
, '\0', sizeof (intel_dp
->adapter
));
662 intel_dp
->adapter
.owner
= THIS_MODULE
;
663 intel_dp
->adapter
.class = I2C_CLASS_DDC
;
664 strncpy (intel_dp
->adapter
.name
, name
, sizeof(intel_dp
->adapter
.name
) - 1);
665 intel_dp
->adapter
.name
[sizeof(intel_dp
->adapter
.name
) - 1] = '\0';
666 intel_dp
->adapter
.algo_data
= &intel_dp
->algo
;
667 intel_dp
->adapter
.dev
.parent
= &connector
->base
.kdev
;
670 cdv_intel_edp_panel_vdd_on(encoder
);
671 ret
= i2c_dp_aux_add_bus(&intel_dp
->adapter
);
673 cdv_intel_edp_panel_vdd_off(encoder
);
678 void cdv_intel_fixed_panel_mode(struct drm_display_mode
*fixed_mode
,
679 struct drm_display_mode
*adjusted_mode
)
681 adjusted_mode
->hdisplay
= fixed_mode
->hdisplay
;
682 adjusted_mode
->hsync_start
= fixed_mode
->hsync_start
;
683 adjusted_mode
->hsync_end
= fixed_mode
->hsync_end
;
684 adjusted_mode
->htotal
= fixed_mode
->htotal
;
686 adjusted_mode
->vdisplay
= fixed_mode
->vdisplay
;
687 adjusted_mode
->vsync_start
= fixed_mode
->vsync_start
;
688 adjusted_mode
->vsync_end
= fixed_mode
->vsync_end
;
689 adjusted_mode
->vtotal
= fixed_mode
->vtotal
;
691 adjusted_mode
->clock
= fixed_mode
->clock
;
693 drm_mode_set_crtcinfo(adjusted_mode
, CRTC_INTERLACE_HALVE_V
);
697 cdv_intel_dp_mode_fixup(struct drm_encoder
*encoder
, const struct drm_display_mode
*mode
,
698 struct drm_display_mode
*adjusted_mode
)
700 struct drm_psb_private
*dev_priv
= encoder
->dev
->dev_private
;
701 struct psb_intel_encoder
*intel_encoder
= to_psb_intel_encoder(encoder
);
702 struct cdv_intel_dp
*intel_dp
= intel_encoder
->dev_priv
;
703 int lane_count
, clock
;
704 int max_lane_count
= cdv_intel_dp_max_lane_count(intel_encoder
);
705 int max_clock
= cdv_intel_dp_max_link_bw(intel_encoder
) == DP_LINK_BW_2_7
? 1 : 0;
706 static int bws
[2] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
};
707 int refclock
= mode
->clock
;
710 if (is_edp(intel_encoder
) && intel_dp
->panel_fixed_mode
) {
711 cdv_intel_fixed_panel_mode(intel_dp
->panel_fixed_mode
, adjusted_mode
);
712 refclock
= intel_dp
->panel_fixed_mode
->clock
;
713 bpp
= dev_priv
->edp
.bpp
;
716 for (lane_count
= 1; lane_count
<= max_lane_count
; lane_count
<<= 1) {
717 for (clock
= max_clock
; clock
>= 0; clock
--) {
718 int link_avail
= cdv_intel_dp_max_data_rate(cdv_intel_dp_link_clock(bws
[clock
]), lane_count
);
720 if (cdv_intel_dp_link_required(refclock
, bpp
) <= link_avail
) {
721 intel_dp
->link_bw
= bws
[clock
];
722 intel_dp
->lane_count
= lane_count
;
723 adjusted_mode
->clock
= cdv_intel_dp_link_clock(intel_dp
->link_bw
);
724 DRM_DEBUG_KMS("Display port link bw %02x lane "
725 "count %d clock %d\n",
726 intel_dp
->link_bw
, intel_dp
->lane_count
,
727 adjusted_mode
->clock
);
732 if (is_edp(intel_encoder
)) {
733 /* okay we failed just pick the highest */
734 intel_dp
->lane_count
= max_lane_count
;
735 intel_dp
->link_bw
= bws
[max_clock
];
736 adjusted_mode
->clock
= cdv_intel_dp_link_clock(intel_dp
->link_bw
);
737 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
738 "count %d clock %d\n",
739 intel_dp
->link_bw
, intel_dp
->lane_count
,
740 adjusted_mode
->clock
);
747 struct cdv_intel_dp_m_n
{
756 cdv_intel_reduce_ratio(uint32_t *num
, uint32_t *den
)
759 while (*num > 0xffffff || *den > 0xffffff) {
765 value
= m
* (0x800000);
766 m
= do_div(value
, *den
);
772 cdv_intel_dp_compute_m_n(int bpp
,
776 struct cdv_intel_dp_m_n
*m_n
)
779 m_n
->gmch_m
= (pixel_clock
* bpp
+ 7) >> 3;
780 m_n
->gmch_n
= link_clock
* nlanes
;
781 cdv_intel_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
782 m_n
->link_m
= pixel_clock
;
783 m_n
->link_n
= link_clock
;
784 cdv_intel_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
788 cdv_intel_dp_set_m_n(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
789 struct drm_display_mode
*adjusted_mode
)
791 struct drm_device
*dev
= crtc
->dev
;
792 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
793 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
794 struct drm_encoder
*encoder
;
795 struct psb_intel_crtc
*intel_crtc
= to_psb_intel_crtc(crtc
);
796 int lane_count
= 4, bpp
= 24;
797 struct cdv_intel_dp_m_n m_n
;
798 int pipe
= intel_crtc
->pipe
;
801 * Find the lane count in the intel_encoder private
803 list_for_each_entry(encoder
, &mode_config
->encoder_list
, head
) {
804 struct psb_intel_encoder
*intel_encoder
;
805 struct cdv_intel_dp
*intel_dp
;
807 if (encoder
->crtc
!= crtc
)
810 intel_encoder
= to_psb_intel_encoder(encoder
);
811 intel_dp
= intel_encoder
->dev_priv
;
812 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
) {
813 lane_count
= intel_dp
->lane_count
;
815 } else if (is_edp(intel_encoder
)) {
816 lane_count
= intel_dp
->lane_count
;
817 bpp
= dev_priv
->edp
.bpp
;
823 * Compute the GMCH and Link ratios. The '3' here is
824 * the number of bytes_per_pixel post-LUT, which we always
825 * set up for 8-bits of R/G/B, or 3 bytes total.
827 cdv_intel_dp_compute_m_n(bpp
, lane_count
,
828 mode
->clock
, adjusted_mode
->clock
, &m_n
);
831 REG_WRITE(PIPE_GMCH_DATA_M(pipe
),
832 ((m_n
.tu
- 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT
) |
834 REG_WRITE(PIPE_GMCH_DATA_N(pipe
), m_n
.gmch_n
);
835 REG_WRITE(PIPE_DP_LINK_M(pipe
), m_n
.link_m
);
836 REG_WRITE(PIPE_DP_LINK_N(pipe
), m_n
.link_n
);
841 cdv_intel_dp_mode_set(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
,
842 struct drm_display_mode
*adjusted_mode
)
844 struct psb_intel_encoder
*intel_encoder
= to_psb_intel_encoder(encoder
);
845 struct drm_crtc
*crtc
= encoder
->crtc
;
846 struct psb_intel_crtc
*intel_crtc
= to_psb_intel_crtc(crtc
);
847 struct cdv_intel_dp
*intel_dp
= intel_encoder
->dev_priv
;
848 struct drm_device
*dev
= encoder
->dev
;
850 intel_dp
->DP
= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
851 intel_dp
->DP
|= intel_dp
->color_range
;
853 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
854 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
855 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
856 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
858 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
860 switch (intel_dp
->lane_count
) {
862 intel_dp
->DP
|= DP_PORT_WIDTH_1
;
865 intel_dp
->DP
|= DP_PORT_WIDTH_2
;
868 intel_dp
->DP
|= DP_PORT_WIDTH_4
;
871 if (intel_dp
->has_audio
)
872 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
874 memset(intel_dp
->link_configuration
, 0, DP_LINK_CONFIGURATION_SIZE
);
875 intel_dp
->link_configuration
[0] = intel_dp
->link_bw
;
876 intel_dp
->link_configuration
[1] = intel_dp
->lane_count
;
879 * Check for DPCD version > 1.1 and enhanced framing support
881 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
882 (intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_ENHANCED_FRAME_CAP
)) {
883 intel_dp
->link_configuration
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
884 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
887 /* CPT DP's pipe select is decided in TRANS_DP_CTL */
888 if (intel_crtc
->pipe
== 1)
889 intel_dp
->DP
|= DP_PIPEB_SELECT
;
891 REG_WRITE(intel_dp
->output_reg
, (intel_dp
->DP
| DP_PORT_EN
));
892 DRM_DEBUG_KMS("DP expected reg is %x\n", intel_dp
->DP
);
893 if (is_edp(intel_encoder
)) {
894 uint32_t pfit_control
;
895 cdv_intel_edp_panel_on(intel_encoder
);
897 if (mode
->hdisplay
!= adjusted_mode
->hdisplay
||
898 mode
->vdisplay
!= adjusted_mode
->vdisplay
)
899 pfit_control
= PFIT_ENABLE
;
903 pfit_control
|= intel_crtc
->pipe
<< PFIT_PIPE_SHIFT
;
905 REG_WRITE(PFIT_CONTROL
, pfit_control
);
910 /* If the sink supports it, try to set the power state appropriately */
911 static void cdv_intel_dp_sink_dpms(struct psb_intel_encoder
*encoder
, int mode
)
913 struct cdv_intel_dp
*intel_dp
= encoder
->dev_priv
;
916 /* Should have a valid DPCD by this point */
917 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
920 if (mode
!= DRM_MODE_DPMS_ON
) {
921 ret
= cdv_intel_dp_aux_native_write_1(encoder
, DP_SET_POWER
,
924 DRM_DEBUG_DRIVER("failed to write sink power state\n");
927 * When turning on, we need to retry for 1ms to give the sink
930 for (i
= 0; i
< 3; i
++) {
931 ret
= cdv_intel_dp_aux_native_write_1(encoder
,
941 static void cdv_intel_dp_prepare(struct drm_encoder
*encoder
)
943 struct psb_intel_encoder
*intel_encoder
= to_psb_intel_encoder(encoder
);
944 int edp
= is_edp(intel_encoder
);
947 cdv_intel_edp_backlight_off(intel_encoder
);
948 cdv_intel_edp_panel_off(intel_encoder
);
949 cdv_intel_edp_panel_vdd_on(intel_encoder
);
951 /* Wake up the sink first */
952 cdv_intel_dp_sink_dpms(intel_encoder
, DRM_MODE_DPMS_ON
);
953 cdv_intel_dp_link_down(intel_encoder
);
955 cdv_intel_edp_panel_vdd_off(intel_encoder
);
958 static void cdv_intel_dp_commit(struct drm_encoder
*encoder
)
960 struct psb_intel_encoder
*intel_encoder
= to_psb_intel_encoder(encoder
);
961 int edp
= is_edp(intel_encoder
);
964 cdv_intel_edp_panel_on(intel_encoder
);
965 cdv_intel_dp_start_link_train(intel_encoder
);
966 cdv_intel_dp_complete_link_train(intel_encoder
);
968 cdv_intel_edp_backlight_on(intel_encoder
);
972 cdv_intel_dp_dpms(struct drm_encoder
*encoder
, int mode
)
974 struct psb_intel_encoder
*intel_encoder
= to_psb_intel_encoder(encoder
);
975 struct cdv_intel_dp
*intel_dp
= intel_encoder
->dev_priv
;
976 struct drm_device
*dev
= encoder
->dev
;
977 uint32_t dp_reg
= REG_READ(intel_dp
->output_reg
);
978 int edp
= is_edp(intel_encoder
);
980 if (mode
!= DRM_MODE_DPMS_ON
) {
982 cdv_intel_edp_backlight_off(intel_encoder
);
983 cdv_intel_edp_panel_vdd_on(intel_encoder
);
985 cdv_intel_dp_sink_dpms(intel_encoder
, mode
);
986 cdv_intel_dp_link_down(intel_encoder
);
988 cdv_intel_edp_panel_vdd_off(intel_encoder
);
989 cdv_intel_edp_panel_off(intel_encoder
);
993 cdv_intel_edp_panel_on(intel_encoder
);
994 cdv_intel_dp_sink_dpms(intel_encoder
, mode
);
995 if (!(dp_reg
& DP_PORT_EN
)) {
996 cdv_intel_dp_start_link_train(intel_encoder
);
997 cdv_intel_dp_complete_link_train(intel_encoder
);
1000 cdv_intel_edp_backlight_on(intel_encoder
);
1005 * Native read with retry for link status and receiver capability reads for
1006 * cases where the sink may still be asleep.
1009 cdv_intel_dp_aux_native_read_retry(struct psb_intel_encoder
*encoder
, uint16_t address
,
1010 uint8_t *recv
, int recv_bytes
)
1015 * Sinks are *supposed* to come up within 1ms from an off state,
1016 * but we're also supposed to retry 3 times per the spec.
1018 for (i
= 0; i
< 3; i
++) {
1019 ret
= cdv_intel_dp_aux_native_read(encoder
, address
, recv
,
1021 if (ret
== recv_bytes
)
1030 * Fetch AUX CH registers 0x202 - 0x207 which contain
1031 * link status information
1034 cdv_intel_dp_get_link_status(struct psb_intel_encoder
*encoder
)
1036 struct cdv_intel_dp
*intel_dp
= encoder
->dev_priv
;
1037 return cdv_intel_dp_aux_native_read_retry(encoder
,
1039 intel_dp
->link_status
,
1040 DP_LINK_STATUS_SIZE
);
1044 cdv_intel_dp_link_status(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
1047 return link_status
[r
- DP_LANE0_1_STATUS
];
1051 cdv_intel_get_adjust_request_voltage(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
1054 int i
= DP_ADJUST_REQUEST_LANE0_1
+ (lane
>> 1);
1055 int s
= ((lane
& 1) ?
1056 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT
:
1057 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT
);
1058 uint8_t l
= cdv_intel_dp_link_status(link_status
, i
);
1060 return ((l
>> s
) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT
;
1064 cdv_intel_get_adjust_request_pre_emphasis(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
1067 int i
= DP_ADJUST_REQUEST_LANE0_1
+ (lane
>> 1);
1068 int s
= ((lane
& 1) ?
1069 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT
:
1070 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT
);
1071 uint8_t l
= cdv_intel_dp_link_status(link_status
, i
);
1073 return ((l
>> s
) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT
;
1078 static char *voltage_names
[] = {
1079 "0.4V", "0.6V", "0.8V", "1.2V"
1081 static char *pre_emph_names
[] = {
1082 "0dB", "3.5dB", "6dB", "9.5dB"
1084 static char *link_train_names
[] = {
1085 "pattern 1", "pattern 2", "idle", "off"
1089 #define CDV_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200
1092 cdv_intel_dp_pre_emphasis_max(uint8_t voltage_swing)
1094 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1095 case DP_TRAIN_VOLTAGE_SWING_400:
1096 return DP_TRAIN_PRE_EMPHASIS_6;
1097 case DP_TRAIN_VOLTAGE_SWING_600:
1098 return DP_TRAIN_PRE_EMPHASIS_6;
1099 case DP_TRAIN_VOLTAGE_SWING_800:
1100 return DP_TRAIN_PRE_EMPHASIS_3_5;
1101 case DP_TRAIN_VOLTAGE_SWING_1200:
1103 return DP_TRAIN_PRE_EMPHASIS_0;
1108 cdv_intel_get_adjust_train(struct psb_intel_encoder
*encoder
)
1110 struct cdv_intel_dp
*intel_dp
= encoder
->dev_priv
;
1115 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
1116 uint8_t this_v
= cdv_intel_get_adjust_request_voltage(intel_dp
->link_status
, lane
);
1117 uint8_t this_p
= cdv_intel_get_adjust_request_pre_emphasis(intel_dp
->link_status
, lane
);
1125 if (v
>= CDV_DP_VOLTAGE_MAX
)
1126 v
= CDV_DP_VOLTAGE_MAX
| DP_TRAIN_MAX_SWING_REACHED
;
1128 if (p
== DP_TRAIN_PRE_EMPHASIS_MASK
)
1129 p
|= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
1131 for (lane
= 0; lane
< 4; lane
++)
1132 intel_dp
->train_set
[lane
] = v
| p
;
1137 cdv_intel_get_lane_status(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
1140 int i
= DP_LANE0_1_STATUS
+ (lane
>> 1);
1141 int s
= (lane
& 1) * 4;
1142 uint8_t l
= cdv_intel_dp_link_status(link_status
, i
);
1144 return (l
>> s
) & 0xf;
1147 /* Check for clock recovery is done on all channels */
1149 cdv_intel_clock_recovery_ok(uint8_t link_status
[DP_LINK_STATUS_SIZE
], int lane_count
)
1152 uint8_t lane_status
;
1154 for (lane
= 0; lane
< lane_count
; lane
++) {
1155 lane_status
= cdv_intel_get_lane_status(link_status
, lane
);
1156 if ((lane_status
& DP_LANE_CR_DONE
) == 0)
1162 /* Check to see if channel eq is done on all channels */
1163 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1164 DP_LANE_CHANNEL_EQ_DONE|\
1165 DP_LANE_SYMBOL_LOCKED)
1167 cdv_intel_channel_eq_ok(struct psb_intel_encoder
*encoder
)
1169 struct cdv_intel_dp
*intel_dp
= encoder
->dev_priv
;
1171 uint8_t lane_status
;
1174 lane_align
= cdv_intel_dp_link_status(intel_dp
->link_status
,
1175 DP_LANE_ALIGN_STATUS_UPDATED
);
1176 if ((lane_align
& DP_INTERLANE_ALIGN_DONE
) == 0)
1178 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
1179 lane_status
= cdv_intel_get_lane_status(intel_dp
->link_status
, lane
);
1180 if ((lane_status
& CHANNEL_EQ_BITS
) != CHANNEL_EQ_BITS
)
1187 cdv_intel_dp_set_link_train(struct psb_intel_encoder
*encoder
,
1188 uint32_t dp_reg_value
,
1189 uint8_t dp_train_pat
)
1192 struct drm_device
*dev
= encoder
->base
.dev
;
1194 struct cdv_intel_dp
*intel_dp
= encoder
->dev_priv
;
1196 REG_WRITE(intel_dp
->output_reg
, dp_reg_value
);
1197 REG_READ(intel_dp
->output_reg
);
1199 ret
= cdv_intel_dp_aux_native_write_1(encoder
,
1200 DP_TRAINING_PATTERN_SET
,
1204 DRM_DEBUG_KMS("Failure in setting link pattern %x\n",
1214 cdv_intel_dplink_set_level(struct psb_intel_encoder
*encoder
,
1215 uint8_t dp_train_pat
)
1219 struct cdv_intel_dp
*intel_dp
= encoder
->dev_priv
;
1221 ret
= cdv_intel_dp_aux_native_write(encoder
,
1222 DP_TRAINING_LANE0_SET
,
1223 intel_dp
->train_set
,
1224 intel_dp
->lane_count
);
1226 if (ret
!= intel_dp
->lane_count
) {
1227 DRM_DEBUG_KMS("Failure in setting level %d, lane_cnt= %d\n",
1228 intel_dp
->train_set
[0], intel_dp
->lane_count
);
1235 cdv_intel_dp_set_vswing_premph(struct psb_intel_encoder
*encoder
, uint8_t signal_level
)
1237 struct drm_device
*dev
= encoder
->base
.dev
;
1238 struct cdv_intel_dp
*intel_dp
= encoder
->dev_priv
;
1239 struct ddi_regoff
*ddi_reg
;
1240 int vswing
, premph
, index
;
1242 if (intel_dp
->output_reg
== DP_B
)
1243 ddi_reg
= &ddi_DP_train_table
[0];
1245 ddi_reg
= &ddi_DP_train_table
[1];
1247 vswing
= (signal_level
& DP_TRAIN_VOLTAGE_SWING_MASK
);
1248 premph
= ((signal_level
& DP_TRAIN_PRE_EMPHASIS_MASK
)) >>
1249 DP_TRAIN_PRE_EMPHASIS_SHIFT
;
1251 if (vswing
+ premph
> 3)
1253 #ifdef CDV_FAST_LINK_TRAIN
1256 DRM_DEBUG_KMS("Test2\n");
1259 /* ;Swing voltage programming
1260 ;gfx_dpio_set_reg(0xc058, 0x0505313A) */
1261 cdv_sb_write(dev
, ddi_reg
->VSwing5
, 0x0505313A);
1263 /* ;gfx_dpio_set_reg(0x8154, 0x43406055) */
1264 cdv_sb_write(dev
, ddi_reg
->VSwing1
, 0x43406055);
1266 /* ;gfx_dpio_set_reg(0x8148, 0x55338954)
1267 * The VSwing_PreEmph table is also considered based on the vswing/premp
1269 index
= (vswing
+ premph
) * 2;
1270 if (premph
== 1 && vswing
== 1) {
1271 cdv_sb_write(dev
, ddi_reg
->VSwing2
, 0x055738954);
1273 cdv_sb_write(dev
, ddi_reg
->VSwing2
, dp_vswing_premph_table
[index
]);
1275 /* ;gfx_dpio_set_reg(0x814c, 0x40802040) */
1276 if ((vswing
+ premph
) == DP_TRAIN_VOLTAGE_SWING_1200
)
1277 cdv_sb_write(dev
, ddi_reg
->VSwing3
, 0x70802040);
1279 cdv_sb_write(dev
, ddi_reg
->VSwing3
, 0x40802040);
1281 /* ;gfx_dpio_set_reg(0x8150, 0x2b405555) */
1282 /* cdv_sb_write(dev, ddi_reg->VSwing4, 0x2b405555); */
1284 /* ;gfx_dpio_set_reg(0x8154, 0xc3406055) */
1285 cdv_sb_write(dev
, ddi_reg
->VSwing1
, 0xc3406055);
1287 /* ;Pre emphasis programming
1288 * ;gfx_dpio_set_reg(0xc02c, 0x1f030040)
1290 cdv_sb_write(dev
, ddi_reg
->PreEmph1
, 0x1f030040);
1292 /* ;gfx_dpio_set_reg(0x8124, 0x00004000) */
1293 index
= 2 * premph
+ 1;
1294 cdv_sb_write(dev
, ddi_reg
->PreEmph2
, dp_vswing_premph_table
[index
]);
1299 /* Enable corresponding port and start training pattern 1 */
1301 cdv_intel_dp_start_link_train(struct psb_intel_encoder
*encoder
)
1303 struct drm_device
*dev
= encoder
->base
.dev
;
1304 struct cdv_intel_dp
*intel_dp
= encoder
->dev_priv
;
1307 bool clock_recovery
= false;
1310 uint32_t DP
= intel_dp
->DP
;
1313 DP
&= ~DP_LINK_TRAIN_MASK
;
1316 reg
|= DP_LINK_TRAIN_PAT_1
;
1317 /* Enable output, wait for it to become active */
1318 REG_WRITE(intel_dp
->output_reg
, reg
);
1319 REG_READ(intel_dp
->output_reg
);
1320 psb_intel_wait_for_vblank(dev
);
1322 DRM_DEBUG_KMS("Link config\n");
1323 /* Write the link configuration data */
1324 cdv_intel_dp_aux_native_write(encoder
, DP_LINK_BW_SET
,
1325 intel_dp
->link_configuration
,
1328 memset(intel_dp
->train_set
, 0, 4);
1331 clock_recovery
= false;
1333 DRM_DEBUG_KMS("Start train\n");
1334 reg
= DP
| DP_LINK_TRAIN_PAT_1
;
1338 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1339 DRM_DEBUG_KMS("DP Link Train Set %x, Link_config %x, %x\n",
1340 intel_dp
->train_set
[0],
1341 intel_dp
->link_configuration
[0],
1342 intel_dp
->link_configuration
[1]);
1344 if (!cdv_intel_dp_set_link_train(encoder
, reg
, DP_TRAINING_PATTERN_1
)) {
1345 DRM_DEBUG_KMS("Failure in aux-transfer setting pattern 1\n");
1347 cdv_intel_dp_set_vswing_premph(encoder
, intel_dp
->train_set
[0]);
1348 /* Set training pattern 1 */
1350 cdv_intel_dplink_set_level(encoder
, DP_TRAINING_PATTERN_1
);
1353 if (!cdv_intel_dp_get_link_status(encoder
))
1356 DRM_DEBUG_KMS("DP Link status %x, %x, %x, %x, %x, %x\n",
1357 intel_dp
->link_status
[0], intel_dp
->link_status
[1], intel_dp
->link_status
[2],
1358 intel_dp
->link_status
[3], intel_dp
->link_status
[4], intel_dp
->link_status
[5]);
1360 if (cdv_intel_clock_recovery_ok(intel_dp
->link_status
, intel_dp
->lane_count
)) {
1361 DRM_DEBUG_KMS("PT1 train is done\n");
1362 clock_recovery
= true;
1366 /* Check to see if we've tried the max voltage */
1367 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
1368 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
1370 if (i
== intel_dp
->lane_count
)
1373 /* Check to see if we've tried the same voltage 5 times */
1374 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
1380 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
1382 /* Compute new intel_dp->train_set as requested by target */
1383 cdv_intel_get_adjust_train(encoder
);
1387 if (!clock_recovery
) {
1388 DRM_DEBUG_KMS("failure in DP patter 1 training, train set %x\n", intel_dp
->train_set
[0]);
1395 cdv_intel_dp_complete_link_train(struct psb_intel_encoder
*encoder
)
1397 struct drm_device
*dev
= encoder
->base
.dev
;
1398 struct cdv_intel_dp
*intel_dp
= encoder
->dev_priv
;
1399 bool channel_eq
= false;
1400 int tries
, cr_tries
;
1402 uint32_t DP
= intel_dp
->DP
;
1404 /* channel equalization */
1409 DRM_DEBUG_KMS("\n");
1410 reg
= DP
| DP_LINK_TRAIN_PAT_2
;
1414 DRM_DEBUG_KMS("DP Link Train Set %x, Link_config %x, %x\n",
1415 intel_dp
->train_set
[0],
1416 intel_dp
->link_configuration
[0],
1417 intel_dp
->link_configuration
[1]);
1418 /* channel eq pattern */
1420 if (!cdv_intel_dp_set_link_train(encoder
, reg
,
1421 DP_TRAINING_PATTERN_2
)) {
1422 DRM_DEBUG_KMS("Failure in aux-transfer setting pattern 2\n");
1424 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1427 DRM_ERROR("failed to train DP, aborting\n");
1428 cdv_intel_dp_link_down(encoder
);
1432 cdv_intel_dp_set_vswing_premph(encoder
, intel_dp
->train_set
[0]);
1434 cdv_intel_dplink_set_level(encoder
, DP_TRAINING_PATTERN_2
);
1437 if (!cdv_intel_dp_get_link_status(encoder
))
1440 DRM_DEBUG_KMS("DP Link status %x, %x, %x, %x, %x, %x\n",
1441 intel_dp
->link_status
[0], intel_dp
->link_status
[1], intel_dp
->link_status
[2],
1442 intel_dp
->link_status
[3], intel_dp
->link_status
[4], intel_dp
->link_status
[5]);
1444 /* Make sure clock is still ok */
1445 if (!cdv_intel_clock_recovery_ok(intel_dp
->link_status
, intel_dp
->lane_count
)) {
1446 cdv_intel_dp_start_link_train(encoder
);
1451 if (cdv_intel_channel_eq_ok(encoder
)) {
1452 DRM_DEBUG_KMS("PT2 train is done\n");
1457 /* Try 5 times, then try clock recovery if that fails */
1459 cdv_intel_dp_link_down(encoder
);
1460 cdv_intel_dp_start_link_train(encoder
);
1466 /* Compute new intel_dp->train_set as requested by target */
1467 cdv_intel_get_adjust_train(encoder
);
1472 reg
= DP
| DP_LINK_TRAIN_OFF
;
1474 REG_WRITE(intel_dp
->output_reg
, reg
);
1475 REG_READ(intel_dp
->output_reg
);
1476 cdv_intel_dp_aux_native_write_1(encoder
,
1477 DP_TRAINING_PATTERN_SET
, DP_TRAINING_PATTERN_DISABLE
);
1481 cdv_intel_dp_link_down(struct psb_intel_encoder
*encoder
)
1483 struct drm_device
*dev
= encoder
->base
.dev
;
1484 struct cdv_intel_dp
*intel_dp
= encoder
->dev_priv
;
1485 uint32_t DP
= intel_dp
->DP
;
1487 if ((REG_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0)
1490 DRM_DEBUG_KMS("\n");
1494 DP
&= ~DP_LINK_TRAIN_MASK
;
1495 REG_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
1497 REG_READ(intel_dp
->output_reg
);
1501 REG_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
1502 REG_READ(intel_dp
->output_reg
);
1505 static enum drm_connector_status
1506 cdv_dp_detect(struct psb_intel_encoder
*encoder
)
1508 struct cdv_intel_dp
*intel_dp
= encoder
->dev_priv
;
1509 enum drm_connector_status status
;
1511 status
= connector_status_disconnected
;
1512 if (cdv_intel_dp_aux_native_read(encoder
, 0x000, intel_dp
->dpcd
,
1513 sizeof (intel_dp
->dpcd
)) == sizeof (intel_dp
->dpcd
))
1515 if (intel_dp
->dpcd
[DP_DPCD_REV
] != 0)
1516 status
= connector_status_connected
;
1518 if (status
== connector_status_connected
)
1519 DRM_DEBUG_KMS("DPCD: Rev=%x LN_Rate=%x LN_CNT=%x LN_DOWNSP=%x\n",
1520 intel_dp
->dpcd
[0], intel_dp
->dpcd
[1],
1521 intel_dp
->dpcd
[2], intel_dp
->dpcd
[3]);
1526 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1528 * \return true if DP port is connected.
1529 * \return false if DP port is disconnected.
1531 static enum drm_connector_status
1532 cdv_intel_dp_detect(struct drm_connector
*connector
, bool force
)
1534 struct psb_intel_encoder
*encoder
= psb_intel_attached_encoder(connector
);
1535 struct cdv_intel_dp
*intel_dp
= encoder
->dev_priv
;
1536 enum drm_connector_status status
;
1537 struct edid
*edid
= NULL
;
1538 int edp
= is_edp(encoder
);
1540 intel_dp
->has_audio
= false;
1543 cdv_intel_edp_panel_vdd_on(encoder
);
1544 status
= cdv_dp_detect(encoder
);
1545 if (status
!= connector_status_connected
) {
1547 cdv_intel_edp_panel_vdd_off(encoder
);
1551 if (intel_dp
->force_audio
) {
1552 intel_dp
->has_audio
= intel_dp
->force_audio
> 0;
1554 edid
= drm_get_edid(connector
, &intel_dp
->adapter
);
1556 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
1561 cdv_intel_edp_panel_vdd_off(encoder
);
1563 return connector_status_connected
;
1566 static int cdv_intel_dp_get_modes(struct drm_connector
*connector
)
1568 struct psb_intel_encoder
*intel_encoder
= psb_intel_attached_encoder(connector
);
1569 struct cdv_intel_dp
*intel_dp
= intel_encoder
->dev_priv
;
1570 struct edid
*edid
= NULL
;
1572 int edp
= is_edp(intel_encoder
);
1575 edid
= drm_get_edid(connector
, &intel_dp
->adapter
);
1577 drm_mode_connector_update_edid_property(connector
, edid
);
1578 ret
= drm_add_edid_modes(connector
, edid
);
1582 if (is_edp(intel_encoder
)) {
1583 struct drm_device
*dev
= connector
->dev
;
1584 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
1586 cdv_intel_edp_panel_vdd_off(intel_encoder
);
1588 if (edp
&& !intel_dp
->panel_fixed_mode
) {
1589 struct drm_display_mode
*newmode
;
1590 list_for_each_entry(newmode
, &connector
->probed_modes
,
1592 if (newmode
->type
& DRM_MODE_TYPE_PREFERRED
) {
1593 intel_dp
->panel_fixed_mode
=
1594 drm_mode_duplicate(dev
, newmode
);
1602 if (!intel_dp
->panel_fixed_mode
&& dev_priv
->lfp_lvds_vbt_mode
) {
1603 intel_dp
->panel_fixed_mode
=
1604 drm_mode_duplicate(dev
, dev_priv
->lfp_lvds_vbt_mode
);
1605 if (intel_dp
->panel_fixed_mode
) {
1606 intel_dp
->panel_fixed_mode
->type
|=
1607 DRM_MODE_TYPE_PREFERRED
;
1610 if (intel_dp
->panel_fixed_mode
!= NULL
) {
1611 struct drm_display_mode
*mode
;
1612 mode
= drm_mode_duplicate(dev
, intel_dp
->panel_fixed_mode
);
1613 drm_mode_probed_add(connector
, mode
);
1622 cdv_intel_dp_detect_audio(struct drm_connector
*connector
)
1624 struct psb_intel_encoder
*encoder
= psb_intel_attached_encoder(connector
);
1625 struct cdv_intel_dp
*intel_dp
= encoder
->dev_priv
;
1627 bool has_audio
= false;
1628 int edp
= is_edp(encoder
);
1631 cdv_intel_edp_panel_vdd_on(encoder
);
1633 edid
= drm_get_edid(connector
, &intel_dp
->adapter
);
1635 has_audio
= drm_detect_monitor_audio(edid
);
1639 cdv_intel_edp_panel_vdd_off(encoder
);
1645 cdv_intel_dp_set_property(struct drm_connector
*connector
,
1646 struct drm_property
*property
,
1649 struct drm_psb_private
*dev_priv
= connector
->dev
->dev_private
;
1650 struct psb_intel_encoder
*encoder
= psb_intel_attached_encoder(connector
);
1651 struct cdv_intel_dp
*intel_dp
= encoder
->dev_priv
;
1654 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
1658 if (property
== dev_priv
->force_audio_property
) {
1662 if (i
== intel_dp
->force_audio
)
1665 intel_dp
->force_audio
= i
;
1668 has_audio
= cdv_intel_dp_detect_audio(connector
);
1672 if (has_audio
== intel_dp
->has_audio
)
1675 intel_dp
->has_audio
= has_audio
;
1679 if (property
== dev_priv
->broadcast_rgb_property
) {
1680 if (val
== !!intel_dp
->color_range
)
1683 intel_dp
->color_range
= val
? DP_COLOR_RANGE_16_235
: 0;
1690 if (encoder
->base
.crtc
) {
1691 struct drm_crtc
*crtc
= encoder
->base
.crtc
;
1692 drm_crtc_helper_set_mode(crtc
, &crtc
->mode
,
1701 cdv_intel_dp_destroy(struct drm_connector
*connector
)
1703 struct psb_intel_encoder
*psb_intel_encoder
=
1704 psb_intel_attached_encoder(connector
);
1705 struct cdv_intel_dp
*intel_dp
= psb_intel_encoder
->dev_priv
;
1707 if (is_edp(psb_intel_encoder
)) {
1708 /* cdv_intel_panel_destroy_backlight(connector->dev); */
1709 if (intel_dp
->panel_fixed_mode
) {
1710 kfree(intel_dp
->panel_fixed_mode
);
1711 intel_dp
->panel_fixed_mode
= NULL
;
1714 i2c_del_adapter(&intel_dp
->adapter
);
1715 drm_sysfs_connector_remove(connector
);
1716 drm_connector_cleanup(connector
);
1720 static void cdv_intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
1722 drm_encoder_cleanup(encoder
);
1725 static const struct drm_encoder_helper_funcs cdv_intel_dp_helper_funcs
= {
1726 .dpms
= cdv_intel_dp_dpms
,
1727 .mode_fixup
= cdv_intel_dp_mode_fixup
,
1728 .prepare
= cdv_intel_dp_prepare
,
1729 .mode_set
= cdv_intel_dp_mode_set
,
1730 .commit
= cdv_intel_dp_commit
,
1733 static const struct drm_connector_funcs cdv_intel_dp_connector_funcs
= {
1734 .dpms
= drm_helper_connector_dpms
,
1735 .detect
= cdv_intel_dp_detect
,
1736 .fill_modes
= drm_helper_probe_single_connector_modes
,
1737 .set_property
= cdv_intel_dp_set_property
,
1738 .destroy
= cdv_intel_dp_destroy
,
1741 static const struct drm_connector_helper_funcs cdv_intel_dp_connector_helper_funcs
= {
1742 .get_modes
= cdv_intel_dp_get_modes
,
1743 .mode_valid
= cdv_intel_dp_mode_valid
,
1744 .best_encoder
= psb_intel_best_encoder
,
1747 static const struct drm_encoder_funcs cdv_intel_dp_enc_funcs
= {
1748 .destroy
= cdv_intel_dp_encoder_destroy
,
1752 static void cdv_intel_dp_add_properties(struct drm_connector
*connector
)
1754 cdv_intel_attach_force_audio_property(connector
);
1755 cdv_intel_attach_broadcast_rgb_property(connector
);
1758 /* check the VBT to see whether the eDP is on DP-D port */
1759 static bool cdv_intel_dpc_is_edp(struct drm_device
*dev
)
1761 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
1762 struct child_device_config
*p_child
;
1765 if (!dev_priv
->child_dev_num
)
1768 for (i
= 0; i
< dev_priv
->child_dev_num
; i
++) {
1769 p_child
= dev_priv
->child_dev
+ i
;
1771 if (p_child
->dvo_port
== PORT_IDPC
&&
1772 p_child
->device_type
== DEVICE_TYPE_eDP
)
1778 /* Cedarview display clock gating
1780 We need this disable dot get correct behaviour while enabling
1781 DP/eDP. TODO - investigate if we can turn it back to normality
1783 static void cdv_disable_intel_clock_gating(struct drm_device
*dev
)
1786 reg_value
= REG_READ(DSPCLK_GATE_D
);
1788 reg_value
|= (DPUNIT_PIPEB_GATE_DISABLE
|
1789 DPUNIT_PIPEA_GATE_DISABLE
|
1790 DPCUNIT_CLOCK_GATE_DISABLE
|
1791 DPLSUNIT_CLOCK_GATE_DISABLE
|
1792 DPOUNIT_CLOCK_GATE_DISABLE
|
1793 DPIOUNIT_CLOCK_GATE_DISABLE
);
1795 REG_WRITE(DSPCLK_GATE_D
, reg_value
);
1801 cdv_intel_dp_init(struct drm_device
*dev
, struct psb_intel_mode_device
*mode_dev
, int output_reg
)
1803 struct psb_intel_encoder
*psb_intel_encoder
;
1804 struct psb_intel_connector
*psb_intel_connector
;
1805 struct drm_connector
*connector
;
1806 struct drm_encoder
*encoder
;
1807 struct cdv_intel_dp
*intel_dp
;
1808 const char *name
= NULL
;
1809 int type
= DRM_MODE_CONNECTOR_DisplayPort
;
1811 psb_intel_encoder
= kzalloc(sizeof(struct psb_intel_encoder
), GFP_KERNEL
);
1812 if (!psb_intel_encoder
)
1814 psb_intel_connector
= kzalloc(sizeof(struct psb_intel_connector
), GFP_KERNEL
);
1815 if (!psb_intel_connector
)
1817 intel_dp
= kzalloc(sizeof(struct cdv_intel_dp
), GFP_KERNEL
);
1821 if ((output_reg
== DP_C
) && cdv_intel_dpc_is_edp(dev
))
1822 type
= DRM_MODE_CONNECTOR_eDP
;
1824 connector
= &psb_intel_connector
->base
;
1825 encoder
= &psb_intel_encoder
->base
;
1827 drm_connector_init(dev
, connector
, &cdv_intel_dp_connector_funcs
, type
);
1828 drm_encoder_init(dev
, encoder
, &cdv_intel_dp_enc_funcs
, DRM_MODE_ENCODER_TMDS
);
1830 psb_intel_connector_attach_encoder(psb_intel_connector
, psb_intel_encoder
);
1832 if (type
== DRM_MODE_CONNECTOR_DisplayPort
)
1833 psb_intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
1835 psb_intel_encoder
->type
= INTEL_OUTPUT_EDP
;
1838 psb_intel_encoder
->dev_priv
=intel_dp
;
1839 intel_dp
->encoder
= psb_intel_encoder
;
1840 intel_dp
->output_reg
= output_reg
;
1842 drm_encoder_helper_add(encoder
, &cdv_intel_dp_helper_funcs
);
1843 drm_connector_helper_add(connector
, &cdv_intel_dp_connector_helper_funcs
);
1845 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
1846 connector
->interlace_allowed
= false;
1847 connector
->doublescan_allowed
= false;
1849 drm_sysfs_connector_add(connector
);
1851 /* Set up the DDC bus. */
1852 switch (output_reg
) {
1855 psb_intel_encoder
->ddi_select
= (DP_MASK
| DDI0_SELECT
);
1859 psb_intel_encoder
->ddi_select
= (DP_MASK
| DDI1_SELECT
);
1863 cdv_disable_intel_clock_gating(dev
);
1865 cdv_intel_dp_i2c_init(psb_intel_connector
, psb_intel_encoder
, name
);
1866 /* FIXME:fail check */
1867 cdv_intel_dp_add_properties(connector
);
1869 if (is_edp(psb_intel_encoder
)) {
1871 struct edp_power_seq cur
;
1872 u32 pp_on
, pp_off
, pp_div
;
1875 pp_on
= REG_READ(PP_CONTROL
);
1876 pp_on
&= ~PANEL_UNLOCK_MASK
;
1877 pp_on
|= PANEL_UNLOCK_REGS
;
1879 REG_WRITE(PP_CONTROL
, pp_on
);
1881 pwm_ctrl
= REG_READ(BLC_PWM_CTL2
);
1882 pwm_ctrl
|= PWM_PIPE_B
;
1883 REG_WRITE(BLC_PWM_CTL2
, pwm_ctrl
);
1885 pp_on
= REG_READ(PP_ON_DELAYS
);
1886 pp_off
= REG_READ(PP_OFF_DELAYS
);
1887 pp_div
= REG_READ(PP_DIVISOR
);
1889 /* Pull timing values out of registers */
1890 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
1891 PANEL_POWER_UP_DELAY_SHIFT
;
1893 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
1894 PANEL_LIGHT_ON_DELAY_SHIFT
;
1896 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
1897 PANEL_LIGHT_OFF_DELAY_SHIFT
;
1899 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
1900 PANEL_POWER_DOWN_DELAY_SHIFT
;
1902 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
1903 PANEL_POWER_CYCLE_DELAY_SHIFT
);
1905 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
1906 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
1909 intel_dp
->panel_power_up_delay
= cur
.t1_t3
/ 10;
1910 intel_dp
->backlight_on_delay
= cur
.t8
/ 10;
1911 intel_dp
->backlight_off_delay
= cur
.t9
/ 10;
1912 intel_dp
->panel_power_down_delay
= cur
.t10
/ 10;
1913 intel_dp
->panel_power_cycle_delay
= (cur
.t11_t12
- 1) * 100;
1915 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
1916 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
1917 intel_dp
->panel_power_cycle_delay
);
1919 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
1920 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
1923 cdv_intel_edp_panel_vdd_on(psb_intel_encoder
);
1924 ret
= cdv_intel_dp_aux_native_read(psb_intel_encoder
, DP_DPCD_REV
,
1926 sizeof(intel_dp
->dpcd
));
1927 cdv_intel_edp_panel_vdd_off(psb_intel_encoder
);
1929 /* if this fails, presume the device is a ghost */
1930 DRM_INFO("failed to retrieve link info, disabling eDP\n");
1931 cdv_intel_dp_encoder_destroy(encoder
);
1932 cdv_intel_dp_destroy(connector
);
1935 DRM_DEBUG_KMS("DPCD: Rev=%x LN_Rate=%x LN_CNT=%x LN_DOWNSP=%x\n",
1936 intel_dp
->dpcd
[0], intel_dp
->dpcd
[1],
1937 intel_dp
->dpcd
[2], intel_dp
->dpcd
[3]);
1940 /* The CDV reference driver moves pnale backlight setup into the displays that
1941 have a backlight: this is a good idea and one we should probably adopt, however
1942 we need to migrate all the drivers before we can do that */
1943 /*cdv_intel_panel_setup_backlight(dev); */
1948 kfree(psb_intel_connector
);
1950 kfree(psb_intel_encoder
);