drivers/gpu/drm/gma500/gma_display.c

   1 /*
   2  * Copyright © 2006-2011 Intel Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program; if not, write to the Free Software Foundation, Inc.,
  15  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  16  *
  17  * Authors:
  18  *      Eric Anholt <eric@anholt.net>
  19  *      Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
  20  */
  21
  22 #include <drm/drmP.h>
  23 #include "gma_display.h"
  24 #include "psb_intel_drv.h"
  25 #include "psb_intel_reg.h"
  26 #include "psb_drv.h"
  27 #include "framebuffer.h"
  28
  29 /**
  30  * Returns whether any output on the specified pipe is of the specified type
  31  */
  32 bool gma_pipe_has_type(struct drm_crtc *crtc, int type)
  33 {
  34         struct drm_device *dev = crtc->dev;
  35         struct drm_mode_config *mode_config = &dev->mode_config;
  36         struct drm_connector *l_entry;
  37
  38         list_for_each_entry(l_entry, &mode_config->connector_list, head) {
  39                 if (l_entry->encoder && l_entry->encoder->crtc == crtc) {
  40                         struct psb_intel_encoder *psb_intel_encoder =
  41                                         psb_intel_attached_encoder(l_entry);
  42                         if (psb_intel_encoder->type == type)
  43                                 return true;
  44                 }
  45         }
  46
  47         return false;
  48 }
  49
  50 void gma_wait_for_vblank(struct drm_device *dev)
  51 {
  52         /* Wait for 20ms, i.e. one cycle at 50hz. */
  53         mdelay(20);
  54 }
  55
  56 int gma_pipe_set_base(struct drm_crtc *crtc, int x, int y,
  57                       struct drm_framebuffer *old_fb)
  58 {
  59         struct drm_device *dev = crtc->dev;
  60         struct drm_psb_private *dev_priv = dev->dev_private;
  61         struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
  62         struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb);
  63         int pipe = psb_intel_crtc->pipe;
  64         const struct psb_offset *map = &dev_priv->regmap[pipe];
  65         unsigned long start, offset;
  66         u32 dspcntr;
  67         int ret = 0;
  68
  69         if (!gma_power_begin(dev, true))
  70                 return 0;
  71
  72         /* no fb bound */
  73         if (!crtc->fb) {
  74                 dev_err(dev->dev, "No FB bound\n");
  75                 goto gma_pipe_cleaner;
  76         }
  77
  78         /* We are displaying this buffer, make sure it is actually loaded
  79            into the GTT */
  80         ret = psb_gtt_pin(psbfb->gtt);
  81         if (ret < 0)
  82                 goto gma_pipe_set_base_exit;
  83         start = psbfb->gtt->offset;
  84         offset = y * crtc->fb->pitches[0] + x * (crtc->fb->bits_per_pixel / 8);
  85
  86         REG_WRITE(map->stride, crtc->fb->pitches[0]);
  87
  88         dspcntr = REG_READ(map->cntr);
  89         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
  90
  91         switch (crtc->fb->bits_per_pixel) {
  92         case 8:
  93                 dspcntr |= DISPPLANE_8BPP;
  94                 break;
  95         case 16:
  96                 if (crtc->fb->depth == 15)
  97                         dspcntr |= DISPPLANE_15_16BPP;
  98                 else
  99                         dspcntr |= DISPPLANE_16BPP;
 100                 break;
 101         case 24:
 102         case 32:
 103                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
 104                 break;
 105         default:
 106                 dev_err(dev->dev, "Unknown color depth\n");
 107                 ret = -EINVAL;
 108                 goto gma_pipe_set_base_exit;
 109         }
 110         REG_WRITE(map->cntr, dspcntr);
 111
 112         dev_dbg(dev->dev,
 113                 "Writing base %08lX %08lX %d %d\n", start, offset, x, y);
 114
 115         /* FIXME: Investigate whether this really is the base for psb and why
 116                   the linear offset is named base for the other chips. map->surf
 117                   should be the base and map->linoff the offset for all chips */
 118         if (IS_PSB(dev)) {
 119                 REG_WRITE(map->base, offset + start);
 120                 REG_READ(map->base);
 121         } else {
 122                 REG_WRITE(map->base, offset);
 123                 REG_READ(map->base);
 124                 REG_WRITE(map->surf, start);
 125                 REG_READ(map->surf);
 126         }
 127
 128 gma_pipe_cleaner:
 129         /* If there was a previous display we can now unpin it */
 130         if (old_fb)
 131                 psb_gtt_unpin(to_psb_fb(old_fb)->gtt);
 132
 133 gma_pipe_set_base_exit:
 134         gma_power_end(dev);
 135         return ret;
 136 }
 137
 138 /* Loads the palette/gamma unit for the CRTC with the prepared values */
 139 void gma_crtc_load_lut(struct drm_crtc *crtc)
 140 {
 141         struct drm_device *dev = crtc->dev;
 142         struct drm_psb_private *dev_priv = dev->dev_private;
 143         struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
 144         const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe];
 145         int palreg = map->palette;
 146         int i;
 147
 148         /* The clocks have to be on to load the palette. */
 149         if (!crtc->enabled)
 150                 return;
 151
 152         if (gma_power_begin(dev, false)) {
 153                 for (i = 0; i < 256; i++) {
 154                         REG_WRITE(palreg + 4 * i,
 155                                   ((psb_intel_crtc->lut_r[i] +
 156                                   psb_intel_crtc->lut_adj[i]) << 16) |
 157                                   ((psb_intel_crtc->lut_g[i] +
 158                                   psb_intel_crtc->lut_adj[i]) << 8) |
 159                                   (psb_intel_crtc->lut_b[i] +
 160                                   psb_intel_crtc->lut_adj[i]));
 161                 }
 162                 gma_power_end(dev);
 163         } else {
 164                 for (i = 0; i < 256; i++) {
 165                         /* FIXME: Why pipe[0] and not pipe[..._crtc->pipe]? */
 166                         dev_priv->regs.pipe[0].palette[i] =
 167                                   ((psb_intel_crtc->lut_r[i] +
 168                                   psb_intel_crtc->lut_adj[i]) << 16) |
 169                                   ((psb_intel_crtc->lut_g[i] +
 170                                   psb_intel_crtc->lut_adj[i]) << 8) |
 171                                   (psb_intel_crtc->lut_b[i] +
 172                                   psb_intel_crtc->lut_adj[i]);
 173                 }
 174
 175         }
 176 }
 177
 178 void gma_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, u16 *blue,
 179                         u32 start, u32 size)
 180 {
 181         struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
 182         int i;
 183         int end = (start + size > 256) ? 256 : start + size;
 184
 185         for (i = start; i < end; i++) {
 186                 psb_intel_crtc->lut_r[i] = red[i] >> 8;
 187                 psb_intel_crtc->lut_g[i] = green[i] >> 8;
 188                 psb_intel_crtc->lut_b[i] = blue[i] >> 8;
 189         }
 190
 191         gma_crtc_load_lut(crtc);
 192 }
 193
 194 /**
 195  * Sets the power management mode of the pipe and plane.
 196  *
 197  * This code should probably grow support for turning the cursor off and back
 198  * on appropriately at the same time as we're turning the pipe off/on.
 199  */
 200 void gma_crtc_dpms(struct drm_crtc *crtc, int mode)
 201 {
 202         struct drm_device *dev = crtc->dev;
 203         struct drm_psb_private *dev_priv = dev->dev_private;
 204         struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
 205         int pipe = psb_intel_crtc->pipe;
 206         const struct psb_offset *map = &dev_priv->regmap[pipe];
 207         u32 temp;
 208
 209         /* XXX: When our outputs are all unaware of DPMS modes other than off
 210          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
 211          */
 212
 213         /* FIXME: Uncomment this when we move cdv to generic dpms
 214         if (IS_CDV(dev))
 215                 cdv_intel_disable_self_refresh(dev);
 216         */
 217
 218         switch (mode) {
 219         case DRM_MODE_DPMS_ON:
 220         case DRM_MODE_DPMS_STANDBY:
 221         case DRM_MODE_DPMS_SUSPEND:
 222                 if (psb_intel_crtc->active)
 223                         break;
 224
 225                 psb_intel_crtc->active = true;
 226
 227                 /* Enable the DPLL */
 228                 temp = REG_READ(map->dpll);
 229                 if ((temp & DPLL_VCO_ENABLE) == 0) {
 230                         REG_WRITE(map->dpll, temp);
 231                         REG_READ(map->dpll);
 232                         /* Wait for the clocks to stabilize. */
 233                         udelay(150);
 234                         REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
 235                         REG_READ(map->dpll);
 236                         /* Wait for the clocks to stabilize. */
 237                         udelay(150);
 238                         REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
 239                         REG_READ(map->dpll);
 240                         /* Wait for the clocks to stabilize. */
 241                         udelay(150);
 242                 }
 243
 244                 /* Enable the plane */
 245                 temp = REG_READ(map->cntr);
 246                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
 247                         REG_WRITE(map->cntr,
 248                                   temp | DISPLAY_PLANE_ENABLE);
 249                         /* Flush the plane changes */
 250                         REG_WRITE(map->base, REG_READ(map->base));
 251                 }
 252
 253                 udelay(150);
 254
 255                 /* Enable the pipe */
 256                 temp = REG_READ(map->conf);
 257                 if ((temp & PIPEACONF_ENABLE) == 0)
 258                         REG_WRITE(map->conf, temp | PIPEACONF_ENABLE);
 259
 260                 temp = REG_READ(map->status);
 261                 temp &= ~(0xFFFF);
 262                 temp |= PIPE_FIFO_UNDERRUN;
 263                 REG_WRITE(map->status, temp);
 264                 REG_READ(map->status);
 265
 266                 gma_crtc_load_lut(crtc);
 267
 268                 /* Give the overlay scaler a chance to enable
 269                  * if it's on this pipe */
 270                 /* psb_intel_crtc_dpms_video(crtc, true); TODO */
 271                 break;
 272         case DRM_MODE_DPMS_OFF:
 273                 if (!psb_intel_crtc->active)
 274                         break;
 275
 276                 psb_intel_crtc->active = false;
 277
 278                 /* Give the overlay scaler a chance to disable
 279                  * if it's on this pipe */
 280                 /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */
 281
 282                 /* Disable the VGA plane that we never use */
 283                 REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
 284
 285                 /* Turn off vblank interrupts */
 286                 drm_vblank_off(dev, pipe);
 287
 288                 /* Wait for vblank for the disable to take effect */
 289                 gma_wait_for_vblank(dev);
 290
 291                 /* Disable plane */
 292                 temp = REG_READ(map->cntr);
 293                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
 294                         REG_WRITE(map->cntr,
 295                                   temp & ~DISPLAY_PLANE_ENABLE);
 296                         /* Flush the plane changes */
 297                         REG_WRITE(map->base, REG_READ(map->base));
 298                         REG_READ(map->base);
 299                 }
 300
 301                 /* Disable pipe */
 302                 temp = REG_READ(map->conf);
 303                 if ((temp & PIPEACONF_ENABLE) != 0) {
 304                         REG_WRITE(map->conf, temp & ~PIPEACONF_ENABLE);
 305                         REG_READ(map->conf);
 306                 }
 307
 308                 /* Wait for vblank for the disable to take effect. */
 309                 gma_wait_for_vblank(dev);
 310
 311                 udelay(150);
 312
 313                 /* Disable DPLL */
 314                 temp = REG_READ(map->dpll);
 315                 if ((temp & DPLL_VCO_ENABLE) != 0) {
 316                         REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE);
 317                         REG_READ(map->dpll);
 318                 }
 319
 320                 /* Wait for the clocks to turn off. */
 321                 udelay(150);
 322                 break;
 323         }
 324
 325         /* FIXME: Uncomment this when we move cdv to generic dpms
 326         if (IS_CDV(dev))
 327                 cdv_intel_update_watermark(dev, crtc);
 328         */
 329
 330         /* Set FIFO watermarks */
 331         REG_WRITE(DSPARB, 0x3F3E);
 332 }
 333
 334 bool gma_crtc_mode_fixup(struct drm_crtc *crtc,
 335                          const struct drm_display_mode *mode,
 336                          struct drm_display_mode *adjusted_mode)
 337 {
 338         return true;
 339 }
 340
 341 void gma_crtc_prepare(struct drm_crtc *crtc)
 342 {
 343         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
 344         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
 345 }
 346
 347 void gma_crtc_commit(struct drm_crtc *crtc)
 348 {
 349         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
 350         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
 351 }
 352
 353 void gma_crtc_disable(struct drm_crtc *crtc)
 354 {
 355         struct gtt_range *gt;
 356         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
 357
 358         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
 359
 360         if (crtc->fb) {
 361                 gt = to_psb_fb(crtc->fb)->gtt;
 362                 psb_gtt_unpin(gt);
 363         }
 364 }
 365
 366 void gma_crtc_destroy(struct drm_crtc *crtc)
 367 {
 368         struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
 369
 370         kfree(psb_intel_crtc->crtc_state);
 371         drm_crtc_cleanup(crtc);
 372         kfree(psb_intel_crtc);
 373 }
 374
 375 #define GMA_PLL_INVALID(s) { /* DRM_ERROR(s); */ return false; }
 376
 377 bool gma_pll_is_valid(struct drm_crtc *crtc,
 378                       const struct gma_limit_t *limit,
 379                       struct gma_clock_t *clock)
 380 {
 381         if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
 382                 GMA_PLL_INVALID("p1 out of range");
 383         if (clock->p < limit->p.min || limit->p.max < clock->p)
 384                 GMA_PLL_INVALID("p out of range");
 385         if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
 386                 GMA_PLL_INVALID("m2 out of range");
 387         if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
 388                 GMA_PLL_INVALID("m1 out of range");
 389         /* On CDV m1 is always 0 */
 390         if (clock->m1 <= clock->m2 && clock->m1 != 0)
 391                 GMA_PLL_INVALID("m1 <= m2 && m1 != 0");
 392         if (clock->m < limit->m.min || limit->m.max < clock->m)
 393                 GMA_PLL_INVALID("m out of range");
 394         if (clock->n < limit->n.min || limit->n.max < clock->n)
 395                 GMA_PLL_INVALID("n out of range");
 396         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 397                 GMA_PLL_INVALID("vco out of range");
 398         /* XXX: We may need to be checking "Dot clock"
 399          * depending on the multiplier, connector, etc.,
 400          * rather than just a single range.
 401          */
 402         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 403                 GMA_PLL_INVALID("dot out of range");
 404
 405         return true;
 406 }
 407
 408 bool gma_find_best_pll(const struct gma_limit_t *limit,
 409                        struct drm_crtc *crtc, int target, int refclk,
 410                        struct gma_clock_t *best_clock)
 411 {
 412         struct drm_device *dev = crtc->dev;
 413         const struct gma_clock_funcs *clock_funcs =
 414                                         to_psb_intel_crtc(crtc)->clock_funcs;
 415         struct gma_clock_t clock;
 416         int err = target;
 417
 418         if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 419             (REG_READ(LVDS) & LVDS_PORT_EN) != 0) {
 420                 /*
 421                  * For LVDS, if the panel is on, just rely on its current
 422                  * settings for dual-channel.  We haven't figured out how to
 423                  * reliably set up different single/dual channel state, if we
 424                  * even can.
 425                  */
 426                 if ((REG_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 427                     LVDS_CLKB_POWER_UP)
 428                         clock.p2 = limit->p2.p2_fast;
 429                 else
 430                         clock.p2 = limit->p2.p2_slow;
 431         } else {
 432                 if (target < limit->p2.dot_limit)
 433                         clock.p2 = limit->p2.p2_slow;
 434                 else
 435                         clock.p2 = limit->p2.p2_fast;
 436         }
 437
 438         memset(best_clock, 0, sizeof(*best_clock));
 439
 440         /* m1 is always 0 on CDV so the outmost loop will run just once */
 441         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 442                 for (clock.m2 = limit->m2.min;
 443                      (clock.m2 < clock.m1 || clock.m1 == 0) &&
 444                       clock.m2 <= limit->m2.max; clock.m2++) {
 445                         for (clock.n = limit->n.min;
 446                              clock.n <= limit->n.max; clock.n++) {
 447                                 for (clock.p1 = limit->p1.min;
 448                                      clock.p1 <= limit->p1.max;
 449                                      clock.p1++) {
 450                                         int this_err;
 451
 452                                         clock_funcs->clock(refclk, &clock);
 453
 454                                         if (!clock_funcs->pll_is_valid(crtc,
 455                                                                 limit, &clock))
 456                                                 continue;
 457
 458                                         this_err = abs(clock.dot - target);
 459                                         if (this_err < err) {
 460                                                 *best_clock = clock;
 461                                                 err = this_err;
 462                                         }
 463                                 }
 464                         }
 465                 }
 466         }
 467
 468         return err != target;
 469 }