drivers/gpu/drm/gma500/intel_gmbus.c

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2008,2010 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  *
  25  * Authors:
  26  *      Eric Anholt <eric@anholt.net>
  27  *      Chris Wilson <chris@chris-wilson.co.uk>
  28  */
  29 #include <linux/module.h>
  30 #include <linux/i2c.h>
  31 #include <linux/i2c-algo-bit.h>
  32 #include <drm/drmP.h>
  33 #include "psb_intel_drv.h"
  34 #include <drm/gma_drm.h>
  35 #include "psb_drv.h"
  36 #include "psb_intel_reg.h"
  37
  38 #define _wait_for(COND, MS, W) ({ \
  39         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS);       \
  40         int ret__ = 0;                                                  \
  41         while (! (COND)) {                                              \
  42                 if (time_after(jiffies, timeout__)) {                   \
  43                         ret__ = -ETIMEDOUT;                             \
  44                         break;                                          \
  45                 }                                                       \
  46                 if (W && !(in_atomic() || in_dbg_master())) msleep(W);  \
  47         }                                                               \
  48         ret__;                                                          \
  49 })
  50
  51 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  52 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  53
  54 #define GMBUS_REG_READ(reg) ioread32(dev_priv->gmbus_reg + (reg))
  55 #define GMBUS_REG_WRITE(reg, val) iowrite32((val), dev_priv->gmbus_reg + (reg))
  56
  57 /* Intel GPIO access functions */
  58
  59 #define I2C_RISEFALL_TIME 20
  60
  61 static inline struct intel_gmbus *
  62 to_intel_gmbus(struct i2c_adapter *i2c)
  63 {
  64         return container_of(i2c, struct intel_gmbus, adapter);
  65 }
  66
  67 struct intel_gpio {
  68         struct i2c_adapter adapter;
  69         struct i2c_algo_bit_data algo;
  70         struct drm_psb_private *dev_priv;
  71         u32 reg;
  72 };
  73
  74 void
  75 gma_intel_i2c_reset(struct drm_device *dev)
  76 {
  77         struct drm_psb_private *dev_priv = dev->dev_private;
  78         GMBUS_REG_WRITE(GMBUS0, 0);
  79 }
  80
  81 static void intel_i2c_quirk_set(struct drm_psb_private *dev_priv, bool enable)
  82 {
  83         /* When using bit bashing for I2C, this bit needs to be set to 1 */
  84         /* FIXME: We are never Pineview, right?
  85
  86         u32 val;
  87
  88         if (!IS_PINEVIEW(dev_priv->dev))
  89                 return;
  90
  91         val = REG_READ(DSPCLK_GATE_D);
  92         if (enable)
  93                 val |= DPCUNIT_CLOCK_GATE_DISABLE;
  94         else
  95                 val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
  96         REG_WRITE(DSPCLK_GATE_D, val);
  97
  98         return;
  99         */
 100 }
 101
 102 static u32 get_reserved(struct intel_gpio *gpio)
 103 {
 104         struct drm_psb_private *dev_priv = gpio->dev_priv;
 105         u32 reserved = 0;
 106
 107         /* On most chips, these bits must be preserved in software. */
 108         reserved = GMBUS_REG_READ(gpio->reg) &
 109                                      (GPIO_DATA_PULLUP_DISABLE |
 110                                       GPIO_CLOCK_PULLUP_DISABLE);
 111
 112         return reserved;
 113 }
 114
 115 static int get_clock(void *data)
 116 {
 117         struct intel_gpio *gpio = data;
 118         struct drm_psb_private *dev_priv = gpio->dev_priv;
 119         u32 reserved = get_reserved(gpio);
 120         GMBUS_REG_WRITE(gpio->reg, reserved | GPIO_CLOCK_DIR_MASK);
 121         GMBUS_REG_WRITE(gpio->reg, reserved);
 122         return (GMBUS_REG_READ(gpio->reg) & GPIO_CLOCK_VAL_IN) != 0;
 123 }
 124
 125 static int get_data(void *data)
 126 {
 127         struct intel_gpio *gpio = data;
 128         struct drm_psb_private *dev_priv = gpio->dev_priv;
 129         u32 reserved = get_reserved(gpio);
 130         GMBUS_REG_WRITE(gpio->reg, reserved | GPIO_DATA_DIR_MASK);
 131         GMBUS_REG_WRITE(gpio->reg, reserved);
 132         return (GMBUS_REG_READ(gpio->reg) & GPIO_DATA_VAL_IN) != 0;
 133 }
 134
 135 static void set_clock(void *data, int state_high)
 136 {
 137         struct intel_gpio *gpio = data;
 138         struct drm_psb_private *dev_priv = gpio->dev_priv;
 139         u32 reserved = get_reserved(gpio);
 140         u32 clock_bits;
 141
 142         if (state_high)
 143                 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
 144         else
 145                 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
 146                         GPIO_CLOCK_VAL_MASK;
 147
 148         GMBUS_REG_WRITE(gpio->reg, reserved | clock_bits);
 149         GMBUS_REG_READ(gpio->reg); /* Posting */
 150 }
 151
 152 static void set_data(void *data, int state_high)
 153 {
 154         struct intel_gpio *gpio = data;
 155         struct drm_psb_private *dev_priv = gpio->dev_priv;
 156         u32 reserved = get_reserved(gpio);
 157         u32 data_bits;
 158
 159         if (state_high)
 160                 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
 161         else
 162                 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
 163                         GPIO_DATA_VAL_MASK;
 164
 165         GMBUS_REG_WRITE(gpio->reg, reserved | data_bits);
 166         GMBUS_REG_READ(gpio->reg);
 167 }
 168
 169 static struct i2c_adapter *
 170 intel_gpio_create(struct drm_psb_private *dev_priv, u32 pin)
 171 {
 172         static const int map_pin_to_reg[] = {
 173                 0,
 174                 GPIOB,
 175                 GPIOA,
 176                 GPIOC,
 177                 GPIOD,
 178                 GPIOE,
 179                 0,
 180                 GPIOF,
 181         };
 182         struct intel_gpio *gpio;
 183
 184         if (pin >= ARRAY_SIZE(map_pin_to_reg) || !map_pin_to_reg[pin])
 185                 return NULL;
 186
 187         gpio = kzalloc(sizeof(struct intel_gpio), GFP_KERNEL);
 188         if (gpio == NULL)
 189                 return NULL;
 190
 191         gpio->reg = map_pin_to_reg[pin];
 192         gpio->dev_priv = dev_priv;
 193
 194         snprintf(gpio->adapter.name, sizeof(gpio->adapter.name),
 195                  "gma500 GPIO%c", "?BACDE?F"[pin]);
 196         gpio->adapter.owner = THIS_MODULE;
 197         gpio->adapter.algo_data = &gpio->algo;
 198         gpio->adapter.dev.parent = &dev_priv->dev->pdev->dev;
 199         gpio->algo.setsda = set_data;
 200         gpio->algo.setscl = set_clock;
 201         gpio->algo.getsda = get_data;
 202         gpio->algo.getscl = get_clock;
 203         gpio->algo.udelay = I2C_RISEFALL_TIME;
 204         gpio->algo.timeout = usecs_to_jiffies(2200);
 205         gpio->algo.data = gpio;
 206
 207         if (i2c_bit_add_bus(&gpio->adapter))
 208                 goto out_free;
 209
 210         return &gpio->adapter;
 211
 212 out_free:
 213         kfree(gpio);
 214         return NULL;
 215 }
 216
 217 static int
 218 intel_i2c_quirk_xfer(struct drm_psb_private *dev_priv,
 219                      struct i2c_adapter *adapter,
 220                      struct i2c_msg *msgs,
 221                      int num)
 222 {
 223         struct intel_gpio *gpio = container_of(adapter,
 224                                                struct intel_gpio,
 225                                                adapter);
 226         int ret;
 227
 228         gma_intel_i2c_reset(dev_priv->dev);
 229
 230         intel_i2c_quirk_set(dev_priv, true);
 231         set_data(gpio, 1);
 232         set_clock(gpio, 1);
 233         udelay(I2C_RISEFALL_TIME);
 234
 235         ret = adapter->algo->master_xfer(adapter, msgs, num);
 236
 237         set_data(gpio, 1);
 238         set_clock(gpio, 1);
 239         intel_i2c_quirk_set(dev_priv, false);
 240
 241         return ret;
 242 }
 243
 244 static int
 245 gmbus_xfer(struct i2c_adapter *adapter,
 246            struct i2c_msg *msgs,
 247            int num)
 248 {
 249         struct intel_gmbus *bus = container_of(adapter,
 250                                                struct intel_gmbus,
 251                                                adapter);
 252         struct drm_psb_private *dev_priv = adapter->algo_data;
 253         int i, reg_offset;
 254
 255         if (bus->force_bit)
 256                 return intel_i2c_quirk_xfer(dev_priv,
 257                                             bus->force_bit, msgs, num);
 258
 259         reg_offset = 0;
 260
 261         GMBUS_REG_WRITE(GMBUS0 + reg_offset, bus->reg0);
 262
 263         for (i = 0; i < num; i++) {
 264                 u16 len = msgs[i].len;
 265                 u8 *buf = msgs[i].buf;
 266
 267                 if (msgs[i].flags & I2C_M_RD) {
 268                         GMBUS_REG_WRITE(GMBUS1 + reg_offset,
 269                                         GMBUS_CYCLE_WAIT |
 270                                         (i + 1 == num ? GMBUS_CYCLE_STOP : 0) |
 271                                         (len << GMBUS_BYTE_COUNT_SHIFT) |
 272                                         (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
 273                                         GMBUS_SLAVE_READ | GMBUS_SW_RDY);
 274                         GMBUS_REG_READ(GMBUS2+reg_offset);
 275                         do {
 276                                 u32 val, loop = 0;
 277
 278                                 if (wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) &
 279                                              (GMBUS_SATOER | GMBUS_HW_RDY), 50))
 280                                         goto timeout;
 281                                 if (GMBUS_REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
 282                                         goto clear_err;
 283
 284                                 val = GMBUS_REG_READ(GMBUS3 + reg_offset);
 285                                 do {
 286                                         *buf++ = val & 0xff;
 287                                         val >>= 8;
 288                                 } while (--len && ++loop < 4);
 289                         } while (len);
 290                 } else {
 291                         u32 val, loop;
 292
 293                         val = loop = 0;
 294                         do {
 295                                 val |= *buf++ << (8 * loop);
 296                         } while (--len && ++loop < 4);
 297
 298                         GMBUS_REG_WRITE(GMBUS3 + reg_offset, val);
 299                         GMBUS_REG_WRITE(GMBUS1 + reg_offset,
 300                                    (i + 1 == num ? GMBUS_CYCLE_STOP : GMBUS_CYCLE_WAIT) |
 301                                    (msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) |
 302                                    (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
 303                                    GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
 304                         GMBUS_REG_READ(GMBUS2+reg_offset);
 305
 306                         while (len) {
 307                                 if (wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) &
 308                                              (GMBUS_SATOER | GMBUS_HW_RDY), 50))
 309                                         goto timeout;
 310                                 if (GMBUS_REG_READ(GMBUS2 + reg_offset) &
 311                                     GMBUS_SATOER)
 312                                         goto clear_err;
 313
 314                                 val = loop = 0;
 315                                 do {
 316                                         val |= *buf++ << (8 * loop);
 317                                 } while (--len && ++loop < 4);
 318
 319                                 GMBUS_REG_WRITE(GMBUS3 + reg_offset, val);
 320                                 GMBUS_REG_READ(GMBUS2+reg_offset);
 321                         }
 322                 }
 323
 324                 if (i + 1 < num && wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50))
 325                         goto timeout;
 326                 if (GMBUS_REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
 327                         goto clear_err;
 328         }
 329
 330         goto done;
 331
 332 clear_err:
 333         /* Toggle the Software Clear Interrupt bit. This has the effect
 334          * of resetting the GMBUS controller and so clearing the
 335          * BUS_ERROR raised by the slave's NAK.
 336          */
 337         GMBUS_REG_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
 338         GMBUS_REG_WRITE(GMBUS1 + reg_offset, 0);
 339
 340 done:
 341         /* Mark the GMBUS interface as disabled. We will re-enable it at the
 342          * start of the next xfer, till then let it sleep.
 343          */
 344         GMBUS_REG_WRITE(GMBUS0 + reg_offset, 0);
 345         return i;
 346
 347 timeout:
 348         DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n",
 349                  bus->reg0 & 0xff, bus->adapter.name);
 350         GMBUS_REG_WRITE(GMBUS0 + reg_offset, 0);
 351
 352         /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
 353         bus->force_bit = intel_gpio_create(dev_priv, bus->reg0 & 0xff);
 354         if (!bus->force_bit)
 355                 return -ENOMEM;
 356
 357         return intel_i2c_quirk_xfer(dev_priv, bus->force_bit, msgs, num);
 358 }
 359
 360 static u32 gmbus_func(struct i2c_adapter *adapter)
 361 {
 362         struct intel_gmbus *bus = container_of(adapter,
 363                                                struct intel_gmbus,
 364                                                adapter);
 365
 366         if (bus->force_bit)
 367                 bus->force_bit->algo->functionality(bus->force_bit);
 368
 369         return (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
 370                 /* I2C_FUNC_10BIT_ADDR | */
 371                 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
 372                 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
 373 }
 374
 375 static const struct i2c_algorithm gmbus_algorithm = {
 376         .master_xfer    = gmbus_xfer,
 377         .functionality  = gmbus_func
 378 };
 379
 380 /**
 381  * intel_gmbus_setup - instantiate all Intel i2c GMBuses
 382  * @dev: DRM device
 383  */
 384 int gma_intel_setup_gmbus(struct drm_device *dev)
 385 {
 386         static const char *names[GMBUS_NUM_PORTS] = {
 387                 "disabled",
 388                 "ssc",
 389                 "vga",
 390                 "panel",
 391                 "dpc",
 392                 "dpb",
 393                 "reserved",
 394                 "dpd",
 395         };
 396         struct drm_psb_private *dev_priv = dev->dev_private;
 397         int ret, i;
 398
 399         dev_priv->gmbus = kcalloc(GMBUS_NUM_PORTS, sizeof(struct intel_gmbus),
 400                                   GFP_KERNEL);
 401         if (dev_priv->gmbus == NULL)
 402                 return -ENOMEM;
 403
 404         if (IS_MRST(dev))
 405                 dev_priv->gmbus_reg = dev_priv->aux_reg;
 406         else
 407                 dev_priv->gmbus_reg = dev_priv->vdc_reg;
 408
 409         for (i = 0; i < GMBUS_NUM_PORTS; i++) {
 410                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
 411
 412                 bus->adapter.owner = THIS_MODULE;
 413                 bus->adapter.class = I2C_CLASS_DDC;
 414                 snprintf(bus->adapter.name,
 415                          sizeof(bus->adapter.name),
 416                          "gma500 gmbus %s",
 417                          names[i]);
 418
 419                 bus->adapter.dev.parent = &dev->pdev->dev;
 420                 bus->adapter.algo_data  = dev_priv;
 421
 422                 bus->adapter.algo = &gmbus_algorithm;
 423                 ret = i2c_add_adapter(&bus->adapter);
 424                 if (ret)
 425                         goto err;
 426
 427                 /* By default use a conservative clock rate */
 428                 bus->reg0 = i | GMBUS_RATE_100KHZ;
 429
 430                 /* XXX force bit banging until GMBUS is fully debugged */
 431                 bus->force_bit = intel_gpio_create(dev_priv, i);
 432         }
 433
 434         gma_intel_i2c_reset(dev_priv->dev);
 435
 436         return 0;
 437
 438 err:
 439         while (--i) {
 440                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
 441                 i2c_del_adapter(&bus->adapter);
 442         }
 443         kfree(dev_priv->gmbus);
 444         dev_priv->gmbus = NULL;
 445         return ret;
 446 }
 447
 448 void gma_intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
 449 {
 450         struct intel_gmbus *bus = to_intel_gmbus(adapter);
 451
 452         /* speed:
 453          * 0x0 = 100 KHz
 454          * 0x1 = 50 KHz
 455          * 0x2 = 400 KHz
 456          * 0x3 = 1000 Khz
 457          */
 458         bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | (speed << 8);
 459 }
 460
 461 void gma_intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
 462 {
 463         struct intel_gmbus *bus = to_intel_gmbus(adapter);
 464
 465         if (force_bit) {
 466                 if (bus->force_bit == NULL) {
 467                         struct drm_psb_private *dev_priv = adapter->algo_data;
 468                         bus->force_bit = intel_gpio_create(dev_priv,
 469                                                            bus->reg0 & 0xff);
 470                 }
 471         } else {
 472                 if (bus->force_bit) {
 473                         i2c_del_adapter(bus->force_bit);
 474                         kfree(bus->force_bit);
 475                         bus->force_bit = NULL;
 476                 }
 477         }
 478 }
 479
 480 void gma_intel_teardown_gmbus(struct drm_device *dev)
 481 {
 482         struct drm_psb_private *dev_priv = dev->dev_private;
 483         int i;
 484
 485         if (dev_priv->gmbus == NULL)
 486                 return;
 487
 488         for (i = 0; i < GMBUS_NUM_PORTS; i++) {
 489                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
 490                 if (bus->force_bit) {
 491                         i2c_del_adapter(bus->force_bit);
 492                         kfree(bus->force_bit);
 493                 }
 494                 i2c_del_adapter(&bus->adapter);
 495         }
 496
 497         dev_priv->gmbus_reg = NULL; /* iounmap is done in driver_unload */
 498         kfree(dev_priv->gmbus);
 499         dev_priv->gmbus = NULL;
 500 }