2 * Copyright © 2006-2011 Intel Corporation
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc.,
15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 * Eric Anholt <eric@anholt.net>
21 #include <linux/i2c.h>
22 #include <linux/pm_runtime.h>
25 #include "framebuffer.h"
27 #include "psb_intel_drv.h"
28 #include "psb_intel_reg.h"
29 #include "gma_display.h"
32 #define INTEL_LIMIT_I9XX_SDVO_DAC 0
33 #define INTEL_LIMIT_I9XX_LVDS 1
35 static const struct gma_limit_t psb_intel_limits
[] = {
36 { /* INTEL_LIMIT_I9XX_SDVO_DAC */
37 .dot
= {.min
= 20000, .max
= 400000},
38 .vco
= {.min
= 1400000, .max
= 2800000},
39 .n
= {.min
= 1, .max
= 6},
40 .m
= {.min
= 70, .max
= 120},
41 .m1
= {.min
= 8, .max
= 18},
42 .m2
= {.min
= 3, .max
= 7},
43 .p
= {.min
= 5, .max
= 80},
44 .p1
= {.min
= 1, .max
= 8},
45 .p2
= {.dot_limit
= 200000, .p2_slow
= 10, .p2_fast
= 5},
46 .find_pll
= gma_find_best_pll
,
48 { /* INTEL_LIMIT_I9XX_LVDS */
49 .dot
= {.min
= 20000, .max
= 400000},
50 .vco
= {.min
= 1400000, .max
= 2800000},
51 .n
= {.min
= 1, .max
= 6},
52 .m
= {.min
= 70, .max
= 120},
53 .m1
= {.min
= 8, .max
= 18},
54 .m2
= {.min
= 3, .max
= 7},
55 .p
= {.min
= 7, .max
= 98},
56 .p1
= {.min
= 1, .max
= 8},
57 /* The single-channel range is 25-112Mhz, and dual-channel
58 * is 80-224Mhz. Prefer single channel as much as possible.
60 .p2
= {.dot_limit
= 112000, .p2_slow
= 14, .p2_fast
= 7},
61 .find_pll
= gma_find_best_pll
,
65 static const struct gma_limit_t
*psb_intel_limit(struct drm_crtc
*crtc
,
68 const struct gma_limit_t
*limit
;
70 if (gma_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
71 limit
= &psb_intel_limits
[INTEL_LIMIT_I9XX_LVDS
];
73 limit
= &psb_intel_limits
[INTEL_LIMIT_I9XX_SDVO_DAC
];
77 static void psb_intel_clock(int refclk
, struct gma_clock_t
*clock
)
79 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
80 clock
->p
= clock
->p1
* clock
->p2
;
81 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
82 clock
->dot
= clock
->vco
/ clock
->p
;
85 static int psb_intel_pipe_set_base(struct drm_crtc
*crtc
,
86 int x
, int y
, struct drm_framebuffer
*old_fb
)
88 struct drm_device
*dev
= crtc
->dev
;
89 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
90 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
91 struct psb_framebuffer
*psbfb
= to_psb_fb(crtc
->fb
);
92 int pipe
= psb_intel_crtc
->pipe
;
93 const struct psb_offset
*map
= &dev_priv
->regmap
[pipe
];
94 unsigned long start
, offset
;
98 if (!gma_power_begin(dev
, true))
103 dev_dbg(dev
->dev
, "No FB bound\n");
104 goto psb_intel_pipe_cleaner
;
107 /* We are displaying this buffer, make sure it is actually loaded
109 ret
= psb_gtt_pin(psbfb
->gtt
);
111 goto psb_intel_pipe_set_base_exit
;
112 start
= psbfb
->gtt
->offset
;
114 offset
= y
* crtc
->fb
->pitches
[0] + x
* (crtc
->fb
->bits_per_pixel
/ 8);
116 REG_WRITE(map
->stride
, crtc
->fb
->pitches
[0]);
118 dspcntr
= REG_READ(map
->cntr
);
119 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
121 switch (crtc
->fb
->bits_per_pixel
) {
123 dspcntr
|= DISPPLANE_8BPP
;
126 if (crtc
->fb
->depth
== 15)
127 dspcntr
|= DISPPLANE_15_16BPP
;
129 dspcntr
|= DISPPLANE_16BPP
;
133 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
136 dev_err(dev
->dev
, "Unknown color depth\n");
138 psb_gtt_unpin(psbfb
->gtt
);
139 goto psb_intel_pipe_set_base_exit
;
141 REG_WRITE(map
->cntr
, dspcntr
);
143 REG_WRITE(map
->base
, start
+ offset
);
146 psb_intel_pipe_cleaner
:
147 /* If there was a previous display we can now unpin it */
149 psb_gtt_unpin(to_psb_fb(old_fb
)->gtt
);
151 psb_intel_pipe_set_base_exit
:
157 * Sets the power management mode of the pipe and plane.
159 * This code should probably grow support for turning the cursor off and back
160 * on appropriately at the same time as we're turning the pipe off/on.
162 static void psb_intel_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
164 struct drm_device
*dev
= crtc
->dev
;
165 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
166 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
167 int pipe
= psb_intel_crtc
->pipe
;
168 const struct psb_offset
*map
= &dev_priv
->regmap
[pipe
];
171 /* XXX: When our outputs are all unaware of DPMS modes other than off
172 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
175 case DRM_MODE_DPMS_ON
:
176 case DRM_MODE_DPMS_STANDBY
:
177 case DRM_MODE_DPMS_SUSPEND
:
178 /* Enable the DPLL */
179 temp
= REG_READ(map
->dpll
);
180 if ((temp
& DPLL_VCO_ENABLE
) == 0) {
181 REG_WRITE(map
->dpll
, temp
);
183 /* Wait for the clocks to stabilize. */
185 REG_WRITE(map
->dpll
, temp
| DPLL_VCO_ENABLE
);
187 /* Wait for the clocks to stabilize. */
189 REG_WRITE(map
->dpll
, temp
| DPLL_VCO_ENABLE
);
191 /* Wait for the clocks to stabilize. */
195 /* Enable the pipe */
196 temp
= REG_READ(map
->conf
);
197 if ((temp
& PIPEACONF_ENABLE
) == 0)
198 REG_WRITE(map
->conf
, temp
| PIPEACONF_ENABLE
);
200 /* Enable the plane */
201 temp
= REG_READ(map
->cntr
);
202 if ((temp
& DISPLAY_PLANE_ENABLE
) == 0) {
204 temp
| DISPLAY_PLANE_ENABLE
);
205 /* Flush the plane changes */
206 REG_WRITE(map
->base
, REG_READ(map
->base
));
209 psb_intel_crtc_load_lut(crtc
);
211 /* Give the overlay scaler a chance to enable
212 * if it's on this pipe */
213 /* psb_intel_crtc_dpms_video(crtc, true); TODO */
215 case DRM_MODE_DPMS_OFF
:
216 /* Give the overlay scaler a chance to disable
217 * if it's on this pipe */
218 /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */
220 /* Disable the VGA plane that we never use */
221 REG_WRITE(VGACNTRL
, VGA_DISP_DISABLE
);
223 /* Disable display plane */
224 temp
= REG_READ(map
->cntr
);
225 if ((temp
& DISPLAY_PLANE_ENABLE
) != 0) {
227 temp
& ~DISPLAY_PLANE_ENABLE
);
228 /* Flush the plane changes */
229 REG_WRITE(map
->base
, REG_READ(map
->base
));
233 /* Next, disable display pipes */
234 temp
= REG_READ(map
->conf
);
235 if ((temp
& PIPEACONF_ENABLE
) != 0) {
236 REG_WRITE(map
->conf
, temp
& ~PIPEACONF_ENABLE
);
240 /* Wait for vblank for the disable to take effect. */
241 gma_wait_for_vblank(dev
);
243 temp
= REG_READ(map
->dpll
);
244 if ((temp
& DPLL_VCO_ENABLE
) != 0) {
245 REG_WRITE(map
->dpll
, temp
& ~DPLL_VCO_ENABLE
);
249 /* Wait for the clocks to turn off. */
254 /*Set FIFO Watermarks*/
255 REG_WRITE(DSPARB
, 0x3F3E);
258 void psb_intel_encoder_prepare(struct drm_encoder
*encoder
)
260 struct drm_encoder_helper_funcs
*encoder_funcs
=
261 encoder
->helper_private
;
262 /* lvds has its own version of prepare see psb_intel_lvds_prepare */
263 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_OFF
);
266 void psb_intel_encoder_commit(struct drm_encoder
*encoder
)
268 struct drm_encoder_helper_funcs
*encoder_funcs
=
269 encoder
->helper_private
;
270 /* lvds has its own version of commit see psb_intel_lvds_commit */
271 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
274 void psb_intel_encoder_destroy(struct drm_encoder
*encoder
)
276 struct psb_intel_encoder
*intel_encoder
= to_psb_intel_encoder(encoder
);
278 drm_encoder_cleanup(encoder
);
279 kfree(intel_encoder
);
283 * Return the pipe currently connected to the panel fitter,
284 * or -1 if the panel fitter is not present or not in use
286 static int psb_intel_panel_fitter_pipe(struct drm_device
*dev
)
290 pfit_control
= REG_READ(PFIT_CONTROL
);
292 /* See if the panel fitter is in use */
293 if ((pfit_control
& PFIT_ENABLE
) == 0)
295 /* Must be on PIPE 1 for PSB */
299 static int psb_intel_crtc_mode_set(struct drm_crtc
*crtc
,
300 struct drm_display_mode
*mode
,
301 struct drm_display_mode
*adjusted_mode
,
303 struct drm_framebuffer
*old_fb
)
305 struct drm_device
*dev
= crtc
->dev
;
306 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
307 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
308 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
309 int pipe
= psb_intel_crtc
->pipe
;
310 const struct psb_offset
*map
= &dev_priv
->regmap
[pipe
];
312 struct gma_clock_t clock
;
313 u32 dpll
= 0, fp
= 0, dspcntr
, pipeconf
;
314 bool ok
, is_sdvo
= false;
315 bool is_lvds
= false, is_tv
= false;
316 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
317 struct drm_connector
*connector
;
318 const struct gma_limit_t
*limit
;
320 /* No scan out no play */
321 if (crtc
->fb
== NULL
) {
322 crtc_funcs
->mode_set_base(crtc
, x
, y
, old_fb
);
326 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
327 struct psb_intel_encoder
*psb_intel_encoder
=
328 psb_intel_attached_encoder(connector
);
330 if (!connector
->encoder
331 || connector
->encoder
->crtc
!= crtc
)
334 switch (psb_intel_encoder
->type
) {
335 case INTEL_OUTPUT_LVDS
:
338 case INTEL_OUTPUT_SDVO
:
341 case INTEL_OUTPUT_TVOUT
:
349 limit
= psb_intel_crtc
->clock_funcs
->limit(crtc
, refclk
);
351 ok
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
,
354 DRM_ERROR("Couldn't find PLL settings for mode! target: %d, actual: %d",
355 adjusted_mode
->clock
, clock
.dot
);
359 fp
= clock
.n
<< 16 | clock
.m1
<< 8 | clock
.m2
;
361 dpll
= DPLL_VGA_MODE_DIS
;
363 dpll
|= DPLLB_MODE_LVDS
;
364 dpll
|= DPLL_DVO_HIGH_SPEED
;
366 dpll
|= DPLLB_MODE_DAC_SERIAL
;
368 int sdvo_pixel_multiply
=
369 adjusted_mode
->clock
/ mode
->clock
;
370 dpll
|= DPLL_DVO_HIGH_SPEED
;
372 (sdvo_pixel_multiply
- 1) << SDVO_MULTIPLIER_SHIFT_HIRES
;
375 /* compute bitmask from p1 value */
376 dpll
|= (1 << (clock
.p1
- 1)) << 16;
379 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
382 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
385 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
388 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
393 /* XXX: just matching BIOS for now */
394 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
397 dpll
|= PLL_REF_INPUT_DREFCLK
;
400 pipeconf
= REG_READ(map
->conf
);
402 /* Set up the display plane register */
403 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
406 dspcntr
|= DISPPLANE_SEL_PIPE_A
;
408 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
410 dspcntr
|= DISPLAY_PLANE_ENABLE
;
411 pipeconf
|= PIPEACONF_ENABLE
;
412 dpll
|= DPLL_VCO_ENABLE
;
415 /* Disable the panel fitter if it was on our pipe */
416 if (psb_intel_panel_fitter_pipe(dev
) == pipe
)
417 REG_WRITE(PFIT_CONTROL
, 0);
419 drm_mode_debug_printmodeline(mode
);
421 if (dpll
& DPLL_VCO_ENABLE
) {
422 REG_WRITE(map
->fp0
, fp
);
423 REG_WRITE(map
->dpll
, dpll
& ~DPLL_VCO_ENABLE
);
428 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
429 * This is an exception to the general rule that mode_set doesn't turn
433 u32 lvds
= REG_READ(LVDS
);
435 lvds
&= ~LVDS_PIPEB_SELECT
;
437 lvds
|= LVDS_PIPEB_SELECT
;
439 lvds
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
;
440 /* Set the B0-B3 data pairs corresponding to
441 * whether we're going to
442 * set the DPLLs for dual-channel mode or not.
444 lvds
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
446 lvds
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
448 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
449 * appropriately here, but we need to look more
450 * thoroughly into how panels behave in the two modes.
453 REG_WRITE(LVDS
, lvds
);
457 REG_WRITE(map
->fp0
, fp
);
458 REG_WRITE(map
->dpll
, dpll
);
460 /* Wait for the clocks to stabilize. */
463 /* write it again -- the BIOS does, after all */
464 REG_WRITE(map
->dpll
, dpll
);
467 /* Wait for the clocks to stabilize. */
470 REG_WRITE(map
->htotal
, (adjusted_mode
->crtc_hdisplay
- 1) |
471 ((adjusted_mode
->crtc_htotal
- 1) << 16));
472 REG_WRITE(map
->hblank
, (adjusted_mode
->crtc_hblank_start
- 1) |
473 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
474 REG_WRITE(map
->hsync
, (adjusted_mode
->crtc_hsync_start
- 1) |
475 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
476 REG_WRITE(map
->vtotal
, (adjusted_mode
->crtc_vdisplay
- 1) |
477 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
478 REG_WRITE(map
->vblank
, (adjusted_mode
->crtc_vblank_start
- 1) |
479 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
480 REG_WRITE(map
->vsync
, (adjusted_mode
->crtc_vsync_start
- 1) |
481 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
482 /* pipesrc and dspsize control the size that is scaled from,
483 * which should always be the user's requested size.
486 ((mode
->vdisplay
- 1) << 16) | (mode
->hdisplay
- 1));
487 REG_WRITE(map
->pos
, 0);
489 ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
490 REG_WRITE(map
->conf
, pipeconf
);
493 gma_wait_for_vblank(dev
);
495 REG_WRITE(map
->cntr
, dspcntr
);
497 /* Flush the plane changes */
498 crtc_funcs
->mode_set_base(crtc
, x
, y
, old_fb
);
500 gma_wait_for_vblank(dev
);
505 /** Loads the palette/gamma unit for the CRTC with the prepared values */
506 void psb_intel_crtc_load_lut(struct drm_crtc
*crtc
)
508 struct drm_device
*dev
= crtc
->dev
;
509 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
510 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
511 const struct psb_offset
*map
= &dev_priv
->regmap
[psb_intel_crtc
->pipe
];
512 int palreg
= map
->palette
;
515 /* The clocks have to be on to load the palette. */
519 switch (psb_intel_crtc
->pipe
) {
524 dev_err(dev
->dev
, "Illegal Pipe Number.\n");
528 if (gma_power_begin(dev
, false)) {
529 for (i
= 0; i
< 256; i
++) {
530 REG_WRITE(palreg
+ 4 * i
,
531 ((psb_intel_crtc
->lut_r
[i
] +
532 psb_intel_crtc
->lut_adj
[i
]) << 16) |
533 ((psb_intel_crtc
->lut_g
[i
] +
534 psb_intel_crtc
->lut_adj
[i
]) << 8) |
535 (psb_intel_crtc
->lut_b
[i
] +
536 psb_intel_crtc
->lut_adj
[i
]));
540 for (i
= 0; i
< 256; i
++) {
541 dev_priv
->regs
.pipe
[0].palette
[i
] =
542 ((psb_intel_crtc
->lut_r
[i
] +
543 psb_intel_crtc
->lut_adj
[i
]) << 16) |
544 ((psb_intel_crtc
->lut_g
[i
] +
545 psb_intel_crtc
->lut_adj
[i
]) << 8) |
546 (psb_intel_crtc
->lut_b
[i
] +
547 psb_intel_crtc
->lut_adj
[i
]);
554 * Save HW states of giving crtc
556 static void psb_intel_crtc_save(struct drm_crtc
*crtc
)
558 struct drm_device
*dev
= crtc
->dev
;
559 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
560 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
561 struct psb_intel_crtc_state
*crtc_state
= psb_intel_crtc
->crtc_state
;
562 const struct psb_offset
*map
= &dev_priv
->regmap
[psb_intel_crtc
->pipe
];
567 dev_err(dev
->dev
, "No CRTC state found\n");
571 crtc_state
->saveDSPCNTR
= REG_READ(map
->cntr
);
572 crtc_state
->savePIPECONF
= REG_READ(map
->conf
);
573 crtc_state
->savePIPESRC
= REG_READ(map
->src
);
574 crtc_state
->saveFP0
= REG_READ(map
->fp0
);
575 crtc_state
->saveFP1
= REG_READ(map
->fp1
);
576 crtc_state
->saveDPLL
= REG_READ(map
->dpll
);
577 crtc_state
->saveHTOTAL
= REG_READ(map
->htotal
);
578 crtc_state
->saveHBLANK
= REG_READ(map
->hblank
);
579 crtc_state
->saveHSYNC
= REG_READ(map
->hsync
);
580 crtc_state
->saveVTOTAL
= REG_READ(map
->vtotal
);
581 crtc_state
->saveVBLANK
= REG_READ(map
->vblank
);
582 crtc_state
->saveVSYNC
= REG_READ(map
->vsync
);
583 crtc_state
->saveDSPSTRIDE
= REG_READ(map
->stride
);
585 /*NOTE: DSPSIZE DSPPOS only for psb*/
586 crtc_state
->saveDSPSIZE
= REG_READ(map
->size
);
587 crtc_state
->saveDSPPOS
= REG_READ(map
->pos
);
589 crtc_state
->saveDSPBASE
= REG_READ(map
->base
);
591 paletteReg
= map
->palette
;
592 for (i
= 0; i
< 256; ++i
)
593 crtc_state
->savePalette
[i
] = REG_READ(paletteReg
+ (i
<< 2));
597 * Restore HW states of giving crtc
599 static void psb_intel_crtc_restore(struct drm_crtc
*crtc
)
601 struct drm_device
*dev
= crtc
->dev
;
602 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
603 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
604 struct psb_intel_crtc_state
*crtc_state
= psb_intel_crtc
->crtc_state
;
605 const struct psb_offset
*map
= &dev_priv
->regmap
[psb_intel_crtc
->pipe
];
610 dev_err(dev
->dev
, "No crtc state\n");
614 if (crtc_state
->saveDPLL
& DPLL_VCO_ENABLE
) {
616 crtc_state
->saveDPLL
& ~DPLL_VCO_ENABLE
);
621 REG_WRITE(map
->fp0
, crtc_state
->saveFP0
);
624 REG_WRITE(map
->fp1
, crtc_state
->saveFP1
);
627 REG_WRITE(map
->dpll
, crtc_state
->saveDPLL
);
631 REG_WRITE(map
->htotal
, crtc_state
->saveHTOTAL
);
632 REG_WRITE(map
->hblank
, crtc_state
->saveHBLANK
);
633 REG_WRITE(map
->hsync
, crtc_state
->saveHSYNC
);
634 REG_WRITE(map
->vtotal
, crtc_state
->saveVTOTAL
);
635 REG_WRITE(map
->vblank
, crtc_state
->saveVBLANK
);
636 REG_WRITE(map
->vsync
, crtc_state
->saveVSYNC
);
637 REG_WRITE(map
->stride
, crtc_state
->saveDSPSTRIDE
);
639 REG_WRITE(map
->size
, crtc_state
->saveDSPSIZE
);
640 REG_WRITE(map
->pos
, crtc_state
->saveDSPPOS
);
642 REG_WRITE(map
->src
, crtc_state
->savePIPESRC
);
643 REG_WRITE(map
->base
, crtc_state
->saveDSPBASE
);
644 REG_WRITE(map
->conf
, crtc_state
->savePIPECONF
);
646 gma_wait_for_vblank(dev
);
648 REG_WRITE(map
->cntr
, crtc_state
->saveDSPCNTR
);
649 REG_WRITE(map
->base
, crtc_state
->saveDSPBASE
);
651 gma_wait_for_vblank(dev
);
653 paletteReg
= map
->palette
;
654 for (i
= 0; i
< 256; ++i
)
655 REG_WRITE(paletteReg
+ (i
<< 2), crtc_state
->savePalette
[i
]);
658 static int psb_intel_crtc_cursor_set(struct drm_crtc
*crtc
,
659 struct drm_file
*file_priv
,
661 uint32_t width
, uint32_t height
)
663 struct drm_device
*dev
= crtc
->dev
;
664 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
665 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
666 int pipe
= psb_intel_crtc
->pipe
;
667 uint32_t control
= (pipe
== 0) ? CURACNTR
: CURBCNTR
;
668 uint32_t base
= (pipe
== 0) ? CURABASE
: CURBBASE
;
671 struct gtt_range
*gt
;
672 struct gtt_range
*cursor_gt
= psb_intel_crtc
->cursor_gt
;
673 struct drm_gem_object
*obj
;
674 void *tmp_dst
, *tmp_src
;
675 int ret
= 0, i
, cursor_pages
;
677 /* if we want to turn of the cursor ignore width and height */
679 /* turn off the cursor */
680 temp
= CURSOR_MODE_DISABLE
;
682 if (gma_power_begin(dev
, false)) {
683 REG_WRITE(control
, temp
);
688 /* Unpin the old GEM object */
689 if (psb_intel_crtc
->cursor_obj
) {
690 gt
= container_of(psb_intel_crtc
->cursor_obj
,
691 struct gtt_range
, gem
);
693 drm_gem_object_unreference(psb_intel_crtc
->cursor_obj
);
694 psb_intel_crtc
->cursor_obj
= NULL
;
700 /* Currently we only support 64x64 cursors */
701 if (width
!= 64 || height
!= 64) {
702 dev_dbg(dev
->dev
, "we currently only support 64x64 cursors\n");
706 obj
= drm_gem_object_lookup(dev
, file_priv
, handle
);
710 if (obj
->size
< width
* height
* 4) {
711 dev_dbg(dev
->dev
, "buffer is to small\n");
716 gt
= container_of(obj
, struct gtt_range
, gem
);
718 /* Pin the memory into the GTT */
719 ret
= psb_gtt_pin(gt
);
721 dev_err(dev
->dev
, "Can not pin down handle 0x%x\n", handle
);
725 if (dev_priv
->ops
->cursor_needs_phys
) {
726 if (cursor_gt
== NULL
) {
727 dev_err(dev
->dev
, "No hardware cursor mem available");
732 /* Prevent overflow */
736 cursor_pages
= gt
->npage
;
738 /* Copy the cursor to cursor mem */
739 tmp_dst
= dev_priv
->vram_addr
+ cursor_gt
->offset
;
740 for (i
= 0; i
< cursor_pages
; i
++) {
741 tmp_src
= kmap(gt
->pages
[i
]);
742 memcpy(tmp_dst
, tmp_src
, PAGE_SIZE
);
743 kunmap(gt
->pages
[i
]);
744 tmp_dst
+= PAGE_SIZE
;
747 addr
= psb_intel_crtc
->cursor_addr
;
749 addr
= gt
->offset
; /* Or resource.start ??? */
750 psb_intel_crtc
->cursor_addr
= addr
;
754 /* set the pipe for the cursor */
755 temp
|= (pipe
<< 28);
756 temp
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
758 if (gma_power_begin(dev
, false)) {
759 REG_WRITE(control
, temp
);
760 REG_WRITE(base
, addr
);
764 /* unpin the old bo */
765 if (psb_intel_crtc
->cursor_obj
) {
766 gt
= container_of(psb_intel_crtc
->cursor_obj
,
767 struct gtt_range
, gem
);
769 drm_gem_object_unreference(psb_intel_crtc
->cursor_obj
);
772 psb_intel_crtc
->cursor_obj
= obj
;
776 drm_gem_object_unreference(obj
);
780 static int psb_intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
782 struct drm_device
*dev
= crtc
->dev
;
783 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
784 int pipe
= psb_intel_crtc
->pipe
;
790 temp
|= (CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
);
794 temp
|= (CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
);
798 temp
|= ((x
& CURSOR_POS_MASK
) << CURSOR_X_SHIFT
);
799 temp
|= ((y
& CURSOR_POS_MASK
) << CURSOR_Y_SHIFT
);
801 addr
= psb_intel_crtc
->cursor_addr
;
803 if (gma_power_begin(dev
, false)) {
804 REG_WRITE((pipe
== 0) ? CURAPOS
: CURBPOS
, temp
);
805 REG_WRITE((pipe
== 0) ? CURABASE
: CURBBASE
, addr
);
811 static void psb_intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
,
812 u16
*green
, u16
*blue
, uint32_t type
, uint32_t size
)
814 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
820 for (i
= 0; i
< 256; i
++) {
821 psb_intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
822 psb_intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
823 psb_intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
826 psb_intel_crtc_load_lut(crtc
);
829 static int psb_crtc_set_config(struct drm_mode_set
*set
)
832 struct drm_device
*dev
= set
->crtc
->dev
;
833 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
835 if (!dev_priv
->rpm_enabled
)
836 return drm_crtc_helper_set_config(set
);
838 pm_runtime_forbid(&dev
->pdev
->dev
);
839 ret
= drm_crtc_helper_set_config(set
);
840 pm_runtime_allow(&dev
->pdev
->dev
);
844 /* Returns the clock of the currently programmed mode of the given pipe. */
845 static int psb_intel_crtc_clock_get(struct drm_device
*dev
,
846 struct drm_crtc
*crtc
)
848 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
849 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
850 int pipe
= psb_intel_crtc
->pipe
;
851 const struct psb_offset
*map
= &dev_priv
->regmap
[pipe
];
854 struct gma_clock_t clock
;
856 struct psb_pipe
*p
= &dev_priv
->regs
.pipe
[pipe
];
858 if (gma_power_begin(dev
, false)) {
859 dpll
= REG_READ(map
->dpll
);
860 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
861 fp
= REG_READ(map
->fp0
);
863 fp
= REG_READ(map
->fp1
);
864 is_lvds
= (pipe
== 1) && (REG_READ(LVDS
) & LVDS_PORT_EN
);
869 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
874 is_lvds
= (pipe
== 1) && (dev_priv
->regs
.psb
.saveLVDS
&
878 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
879 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
880 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
885 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
886 DPLL_FPA01_P1_POST_DIV_SHIFT
);
889 if ((dpll
& PLL_REF_INPUT_MASK
) ==
890 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
891 /* XXX: might not be 66MHz */
892 psb_intel_clock(66000, &clock
);
894 psb_intel_clock(48000, &clock
);
896 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
901 DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
902 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
904 if (dpll
& PLL_P2_DIVIDE_BY_4
)
909 psb_intel_clock(48000, &clock
);
912 /* XXX: It would be nice to validate the clocks, but we can't reuse
913 * i830PllIsValid() because it relies on the xf86_config connector
914 * configuration being accurate, which it isn't necessarily.
920 /** Returns the currently programmed mode of the given pipe. */
921 struct drm_display_mode
*psb_intel_crtc_mode_get(struct drm_device
*dev
,
922 struct drm_crtc
*crtc
)
924 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
925 int pipe
= psb_intel_crtc
->pipe
;
926 struct drm_display_mode
*mode
;
931 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
932 struct psb_pipe
*p
= &dev_priv
->regs
.pipe
[pipe
];
933 const struct psb_offset
*map
= &dev_priv
->regmap
[pipe
];
935 if (gma_power_begin(dev
, false)) {
936 htot
= REG_READ(map
->htotal
);
937 hsync
= REG_READ(map
->hsync
);
938 vtot
= REG_READ(map
->vtotal
);
939 vsync
= REG_READ(map
->vsync
);
948 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
952 mode
->clock
= psb_intel_crtc_clock_get(dev
, crtc
);
953 mode
->hdisplay
= (htot
& 0xffff) + 1;
954 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
955 mode
->hsync_start
= (hsync
& 0xffff) + 1;
956 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
957 mode
->vdisplay
= (vtot
& 0xffff) + 1;
958 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
959 mode
->vsync_start
= (vsync
& 0xffff) + 1;
960 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
962 drm_mode_set_name(mode
);
963 drm_mode_set_crtcinfo(mode
, 0);
968 static void psb_intel_crtc_destroy(struct drm_crtc
*crtc
)
970 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
971 struct gtt_range
*gt
;
973 /* Unpin the old GEM object */
974 if (psb_intel_crtc
->cursor_obj
) {
975 gt
= container_of(psb_intel_crtc
->cursor_obj
,
976 struct gtt_range
, gem
);
978 drm_gem_object_unreference(psb_intel_crtc
->cursor_obj
);
979 psb_intel_crtc
->cursor_obj
= NULL
;
982 if (psb_intel_crtc
->cursor_gt
!= NULL
)
983 psb_gtt_free_range(crtc
->dev
, psb_intel_crtc
->cursor_gt
);
984 kfree(psb_intel_crtc
->crtc_state
);
985 drm_crtc_cleanup(crtc
);
986 kfree(psb_intel_crtc
);
989 const struct drm_crtc_helper_funcs psb_intel_helper_funcs
= {
990 .dpms
= psb_intel_crtc_dpms
,
991 .mode_fixup
= gma_crtc_mode_fixup
,
992 .mode_set
= psb_intel_crtc_mode_set
,
993 .mode_set_base
= psb_intel_pipe_set_base
,
994 .prepare
= gma_crtc_prepare
,
995 .commit
= gma_crtc_commit
,
996 .disable
= gma_crtc_disable
,
999 const struct drm_crtc_funcs psb_intel_crtc_funcs
= {
1000 .save
= psb_intel_crtc_save
,
1001 .restore
= psb_intel_crtc_restore
,
1002 .cursor_set
= psb_intel_crtc_cursor_set
,
1003 .cursor_move
= psb_intel_crtc_cursor_move
,
1004 .gamma_set
= psb_intel_crtc_gamma_set
,
1005 .set_config
= psb_crtc_set_config
,
1006 .destroy
= psb_intel_crtc_destroy
,
1009 const struct gma_clock_funcs psb_clock_funcs
= {
1010 .clock
= psb_intel_clock
,
1011 .limit
= psb_intel_limit
,
1012 .pll_is_valid
= gma_pll_is_valid
,
1016 * Set the default value of cursor control and base register
1017 * to zero. This is a workaround for h/w defect on Oaktrail
1019 static void psb_intel_cursor_init(struct drm_device
*dev
,
1020 struct psb_intel_crtc
*psb_intel_crtc
)
1022 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
1023 u32 control
[3] = { CURACNTR
, CURBCNTR
, CURCCNTR
};
1024 u32 base
[3] = { CURABASE
, CURBBASE
, CURCBASE
};
1025 struct gtt_range
*cursor_gt
;
1027 if (dev_priv
->ops
->cursor_needs_phys
) {
1028 /* Allocate 4 pages of stolen mem for a hardware cursor. That
1029 * is enough for the 64 x 64 ARGB cursors we support.
1031 cursor_gt
= psb_gtt_alloc_range(dev
, 4 * PAGE_SIZE
, "cursor", 1);
1033 psb_intel_crtc
->cursor_gt
= NULL
;
1036 psb_intel_crtc
->cursor_gt
= cursor_gt
;
1037 psb_intel_crtc
->cursor_addr
= dev_priv
->stolen_base
+
1040 psb_intel_crtc
->cursor_gt
= NULL
;
1044 REG_WRITE(control
[psb_intel_crtc
->pipe
], 0);
1045 REG_WRITE(base
[psb_intel_crtc
->pipe
], 0);
1048 void psb_intel_crtc_init(struct drm_device
*dev
, int pipe
,
1049 struct psb_intel_mode_device
*mode_dev
)
1051 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
1052 struct psb_intel_crtc
*psb_intel_crtc
;
1054 uint16_t *r_base
, *g_base
, *b_base
;
1056 /* We allocate a extra array of drm_connector pointers
1057 * for fbdev after the crtc */
1059 kzalloc(sizeof(struct psb_intel_crtc
) +
1060 (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)),
1062 if (psb_intel_crtc
== NULL
)
1065 psb_intel_crtc
->crtc_state
=
1066 kzalloc(sizeof(struct psb_intel_crtc_state
), GFP_KERNEL
);
1067 if (!psb_intel_crtc
->crtc_state
) {
1068 dev_err(dev
->dev
, "Crtc state error: No memory\n");
1069 kfree(psb_intel_crtc
);
1073 /* Set the CRTC operations from the chip specific data */
1074 drm_crtc_init(dev
, &psb_intel_crtc
->base
, dev_priv
->ops
->crtc_funcs
);
1076 /* Set the CRTC clock functions from chip specific data */
1077 psb_intel_crtc
->clock_funcs
= dev_priv
->ops
->clock_funcs
;
1079 drm_mode_crtc_set_gamma_size(&psb_intel_crtc
->base
, 256);
1080 psb_intel_crtc
->pipe
= pipe
;
1081 psb_intel_crtc
->plane
= pipe
;
1083 r_base
= psb_intel_crtc
->base
.gamma_store
;
1084 g_base
= r_base
+ 256;
1085 b_base
= g_base
+ 256;
1086 for (i
= 0; i
< 256; i
++) {
1087 psb_intel_crtc
->lut_r
[i
] = i
;
1088 psb_intel_crtc
->lut_g
[i
] = i
;
1089 psb_intel_crtc
->lut_b
[i
] = i
;
1094 psb_intel_crtc
->lut_adj
[i
] = 0;
1097 psb_intel_crtc
->mode_dev
= mode_dev
;
1098 psb_intel_crtc
->cursor_addr
= 0;
1100 drm_crtc_helper_add(&psb_intel_crtc
->base
,
1101 dev_priv
->ops
->crtc_helper
);
1103 /* Setup the array of drm_connector pointer array */
1104 psb_intel_crtc
->mode_set
.crtc
= &psb_intel_crtc
->base
;
1105 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
1106 dev_priv
->plane_to_crtc_mapping
[psb_intel_crtc
->plane
] != NULL
);
1107 dev_priv
->plane_to_crtc_mapping
[psb_intel_crtc
->plane
] =
1108 &psb_intel_crtc
->base
;
1109 dev_priv
->pipe_to_crtc_mapping
[psb_intel_crtc
->pipe
] =
1110 &psb_intel_crtc
->base
;
1111 psb_intel_crtc
->mode_set
.connectors
=
1112 (struct drm_connector
**) (psb_intel_crtc
+ 1);
1113 psb_intel_crtc
->mode_set
.num_connectors
= 0;
1114 psb_intel_cursor_init(dev
, psb_intel_crtc
);
1116 /* Set to true so that the pipe is forced off on initial config. */
1117 psb_intel_crtc
->active
= true;
1120 int psb_intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
1121 struct drm_file
*file_priv
)
1123 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
1124 struct drm_psb_get_pipe_from_crtc_id_arg
*pipe_from_crtc_id
= data
;
1125 struct drm_mode_object
*drmmode_obj
;
1126 struct psb_intel_crtc
*crtc
;
1129 dev_err(dev
->dev
, "called with no initialization\n");
1133 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
1134 DRM_MODE_OBJECT_CRTC
);
1137 dev_err(dev
->dev
, "no such CRTC id\n");
1141 crtc
= to_psb_intel_crtc(obj_to_crtc(drmmode_obj
));
1142 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
1147 struct drm_crtc
*psb_intel_get_crtc_from_pipe(struct drm_device
*dev
, int pipe
)
1149 struct drm_crtc
*crtc
= NULL
;
1151 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
1152 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
1153 if (psb_intel_crtc
->pipe
== pipe
)
1159 int psb_intel_connector_clones(struct drm_device
*dev
, int type_mask
)
1162 struct drm_connector
*connector
;
1165 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
1167 struct psb_intel_encoder
*psb_intel_encoder
=
1168 psb_intel_attached_encoder(connector
);
1169 if (type_mask
& (1 << psb_intel_encoder
->type
))
1170 index_mask
|= (1 << entry
);
1176 /* current intel driver doesn't take advantage of encoders
1177 always give back the encoder for the connector
1179 struct drm_encoder
*psb_intel_best_encoder(struct drm_connector
*connector
)
1181 struct psb_intel_encoder
*psb_intel_encoder
=
1182 psb_intel_attached_encoder(connector
);
1184 return &psb_intel_encoder
->base
;
1187 void psb_intel_connector_attach_encoder(struct psb_intel_connector
*connector
,
1188 struct psb_intel_encoder
*encoder
)
1190 connector
->encoder
= encoder
;
1191 drm_mode_connector_attach_encoder(&connector
->base
,