2 * Copyright © 2006-2011 Intel Corporation
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc.,
15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 * Eric Anholt <eric@anholt.net>
21 #include <linux/i2c.h>
22 #include <linux/pm_runtime.h>
25 #include "framebuffer.h"
27 #include "psb_intel_drv.h"
28 #include "psb_intel_reg.h"
29 #include "psb_intel_display.h"
32 struct psb_intel_clock_t
{
44 struct psb_intel_range_t
{
48 struct psb_intel_p2_t
{
53 #define INTEL_P2_NUM 2
55 struct psb_intel_limit_t
{
56 struct psb_intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
57 struct psb_intel_p2_t p2
;
60 #define I9XX_DOT_MIN 20000
61 #define I9XX_DOT_MAX 400000
62 #define I9XX_VCO_MIN 1400000
63 #define I9XX_VCO_MAX 2800000
67 #define I9XX_M_MAX 120
69 #define I9XX_M1_MAX 18
72 #define I9XX_P_SDVO_DAC_MIN 5
73 #define I9XX_P_SDVO_DAC_MAX 80
74 #define I9XX_P_LVDS_MIN 7
75 #define I9XX_P_LVDS_MAX 98
78 #define I9XX_P2_SDVO_DAC_SLOW 10
79 #define I9XX_P2_SDVO_DAC_FAST 5
80 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
81 #define I9XX_P2_LVDS_SLOW 14
82 #define I9XX_P2_LVDS_FAST 7
83 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
85 #define INTEL_LIMIT_I9XX_SDVO_DAC 0
86 #define INTEL_LIMIT_I9XX_LVDS 1
88 static const struct psb_intel_limit_t psb_intel_limits
[] = {
89 { /* INTEL_LIMIT_I9XX_SDVO_DAC */
90 .dot
= {.min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
91 .vco
= {.min
= I9XX_VCO_MIN
, .max
= I9XX_VCO_MAX
},
92 .n
= {.min
= I9XX_N_MIN
, .max
= I9XX_N_MAX
},
93 .m
= {.min
= I9XX_M_MIN
, .max
= I9XX_M_MAX
},
94 .m1
= {.min
= I9XX_M1_MIN
, .max
= I9XX_M1_MAX
},
95 .m2
= {.min
= I9XX_M2_MIN
, .max
= I9XX_M2_MAX
},
96 .p
= {.min
= I9XX_P_SDVO_DAC_MIN
, .max
= I9XX_P_SDVO_DAC_MAX
},
97 .p1
= {.min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
98 .p2
= {.dot_limit
= I9XX_P2_SDVO_DAC_SLOW_LIMIT
,
99 .p2_slow
= I9XX_P2_SDVO_DAC_SLOW
, .p2_fast
=
100 I9XX_P2_SDVO_DAC_FAST
},
102 { /* INTEL_LIMIT_I9XX_LVDS */
103 .dot
= {.min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
104 .vco
= {.min
= I9XX_VCO_MIN
, .max
= I9XX_VCO_MAX
},
105 .n
= {.min
= I9XX_N_MIN
, .max
= I9XX_N_MAX
},
106 .m
= {.min
= I9XX_M_MIN
, .max
= I9XX_M_MAX
},
107 .m1
= {.min
= I9XX_M1_MIN
, .max
= I9XX_M1_MAX
},
108 .m2
= {.min
= I9XX_M2_MIN
, .max
= I9XX_M2_MAX
},
109 .p
= {.min
= I9XX_P_LVDS_MIN
, .max
= I9XX_P_LVDS_MAX
},
110 .p1
= {.min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
111 /* The single-channel range is 25-112Mhz, and dual-channel
112 * is 80-224Mhz. Prefer single channel as much as possible.
114 .p2
= {.dot_limit
= I9XX_P2_LVDS_SLOW_LIMIT
,
115 .p2_slow
= I9XX_P2_LVDS_SLOW
, .p2_fast
= I9XX_P2_LVDS_FAST
},
119 static const struct psb_intel_limit_t
*psb_intel_limit(struct drm_crtc
*crtc
)
121 const struct psb_intel_limit_t
*limit
;
123 if (psb_intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
124 limit
= &psb_intel_limits
[INTEL_LIMIT_I9XX_LVDS
];
126 limit
= &psb_intel_limits
[INTEL_LIMIT_I9XX_SDVO_DAC
];
130 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
132 static void i8xx_clock(int refclk
, struct psb_intel_clock_t
*clock
)
134 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
135 clock
->p
= clock
->p1
* clock
->p2
;
136 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
137 clock
->dot
= clock
->vco
/ clock
->p
;
140 /** Derive the pixel clock for the given refclk and divisors for 9xx chips. */
142 static void i9xx_clock(int refclk
, struct psb_intel_clock_t
*clock
)
144 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
145 clock
->p
= clock
->p1
* clock
->p2
;
146 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
147 clock
->dot
= clock
->vco
/ clock
->p
;
150 static void psb_intel_clock(struct drm_device
*dev
, int refclk
,
151 struct psb_intel_clock_t
*clock
)
153 return i9xx_clock(refclk
, clock
);
157 * Returns whether any output on the specified pipe is of the specified type
159 bool psb_intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
161 struct drm_device
*dev
= crtc
->dev
;
162 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
163 struct drm_connector
*l_entry
;
165 list_for_each_entry(l_entry
, &mode_config
->connector_list
, head
) {
166 if (l_entry
->encoder
&& l_entry
->encoder
->crtc
== crtc
) {
167 struct psb_intel_encoder
*psb_intel_encoder
=
168 psb_intel_attached_encoder(l_entry
);
169 if (psb_intel_encoder
->type
== type
)
176 #define INTELPllInvalid(s) { /* ErrorF (s) */; return false; }
178 * Returns whether the given set of divisors are valid for a given refclk with
179 * the given connectors.
182 static bool psb_intel_PLL_is_valid(struct drm_crtc
*crtc
,
183 struct psb_intel_clock_t
*clock
)
185 const struct psb_intel_limit_t
*limit
= psb_intel_limit(crtc
);
187 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
188 INTELPllInvalid("p1 out of range\n");
189 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
190 INTELPllInvalid("p out of range\n");
191 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
192 INTELPllInvalid("m2 out of range\n");
193 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
194 INTELPllInvalid("m1 out of range\n");
195 if (clock
->m1
<= clock
->m2
)
196 INTELPllInvalid("m1 <= m2\n");
197 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
198 INTELPllInvalid("m out of range\n");
199 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
200 INTELPllInvalid("n out of range\n");
201 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
202 INTELPllInvalid("vco out of range\n");
203 /* XXX: We may need to be checking "Dot clock"
204 * depending on the multiplier, connector, etc.,
205 * rather than just a single range.
207 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
208 INTELPllInvalid("dot out of range\n");
214 * Returns a set of divisors for the desired target clock with the given
215 * refclk, or FALSE. The returned values represent the clock equation:
216 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
218 static bool psb_intel_find_best_PLL(struct drm_crtc
*crtc
, int target
,
220 struct psb_intel_clock_t
*best_clock
)
222 struct drm_device
*dev
= crtc
->dev
;
223 struct psb_intel_clock_t clock
;
224 const struct psb_intel_limit_t
*limit
= psb_intel_limit(crtc
);
227 if (psb_intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
228 (REG_READ(LVDS
) & LVDS_PORT_EN
) != 0) {
230 * For LVDS, if the panel is on, just rely on its current
231 * settings for dual-channel. We haven't figured out how to
232 * reliably set up different single/dual channel state, if we
235 if ((REG_READ(LVDS
) & LVDS_CLKB_POWER_MASK
) ==
237 clock
.p2
= limit
->p2
.p2_fast
;
239 clock
.p2
= limit
->p2
.p2_slow
;
241 if (target
< limit
->p2
.dot_limit
)
242 clock
.p2
= limit
->p2
.p2_slow
;
244 clock
.p2
= limit
->p2
.p2_fast
;
247 memset(best_clock
, 0, sizeof(*best_clock
));
249 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
251 for (clock
.m2
= limit
->m2
.min
;
252 clock
.m2
< clock
.m1
&& clock
.m2
<= limit
->m2
.max
;
254 for (clock
.n
= limit
->n
.min
;
255 clock
.n
<= limit
->n
.max
; clock
.n
++) {
256 for (clock
.p1
= limit
->p1
.min
;
257 clock
.p1
<= limit
->p1
.max
;
261 psb_intel_clock(dev
, refclk
, &clock
);
263 if (!psb_intel_PLL_is_valid
267 this_err
= abs(clock
.dot
- target
);
268 if (this_err
< err
) {
277 return err
!= target
;
280 void psb_intel_wait_for_vblank(struct drm_device
*dev
)
282 /* Wait for 20ms, i.e. one cycle at 50hz. */
286 static int psb_intel_pipe_set_base(struct drm_crtc
*crtc
,
287 int x
, int y
, struct drm_framebuffer
*old_fb
)
289 struct drm_device
*dev
= crtc
->dev
;
290 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
291 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
292 struct psb_framebuffer
*psbfb
= to_psb_fb(crtc
->fb
);
293 int pipe
= psb_intel_crtc
->pipe
;
294 const struct psb_offset
*map
= &dev_priv
->regmap
[pipe
];
295 unsigned long start
, offset
;
299 if (!gma_power_begin(dev
, true))
304 dev_dbg(dev
->dev
, "No FB bound\n");
305 goto psb_intel_pipe_cleaner
;
308 /* We are displaying this buffer, make sure it is actually loaded
310 ret
= psb_gtt_pin(psbfb
->gtt
);
312 goto psb_intel_pipe_set_base_exit
;
313 start
= psbfb
->gtt
->offset
;
315 offset
= y
* crtc
->fb
->pitches
[0] + x
* (crtc
->fb
->bits_per_pixel
/ 8);
317 REG_WRITE(map
->stride
, crtc
->fb
->pitches
[0]);
319 dspcntr
= REG_READ(map
->cntr
);
320 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
322 switch (crtc
->fb
->bits_per_pixel
) {
324 dspcntr
|= DISPPLANE_8BPP
;
327 if (crtc
->fb
->depth
== 15)
328 dspcntr
|= DISPPLANE_15_16BPP
;
330 dspcntr
|= DISPPLANE_16BPP
;
334 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
337 dev_err(dev
->dev
, "Unknown color depth\n");
339 psb_gtt_unpin(psbfb
->gtt
);
340 goto psb_intel_pipe_set_base_exit
;
342 REG_WRITE(map
->cntr
, dspcntr
);
344 REG_WRITE(map
->base
, start
+ offset
);
347 psb_intel_pipe_cleaner
:
348 /* If there was a previous display we can now unpin it */
350 psb_gtt_unpin(to_psb_fb(old_fb
)->gtt
);
352 psb_intel_pipe_set_base_exit
:
358 * Sets the power management mode of the pipe and plane.
360 * This code should probably grow support for turning the cursor off and back
361 * on appropriately at the same time as we're turning the pipe off/on.
363 static void psb_intel_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
365 struct drm_device
*dev
= crtc
->dev
;
366 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
367 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
368 int pipe
= psb_intel_crtc
->pipe
;
369 const struct psb_offset
*map
= &dev_priv
->regmap
[pipe
];
372 /* XXX: When our outputs are all unaware of DPMS modes other than off
373 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
376 case DRM_MODE_DPMS_ON
:
377 case DRM_MODE_DPMS_STANDBY
:
378 case DRM_MODE_DPMS_SUSPEND
:
379 /* Enable the DPLL */
380 temp
= REG_READ(map
->dpll
);
381 if ((temp
& DPLL_VCO_ENABLE
) == 0) {
382 REG_WRITE(map
->dpll
, temp
);
384 /* Wait for the clocks to stabilize. */
386 REG_WRITE(map
->dpll
, temp
| DPLL_VCO_ENABLE
);
388 /* Wait for the clocks to stabilize. */
390 REG_WRITE(map
->dpll
, temp
| DPLL_VCO_ENABLE
);
392 /* Wait for the clocks to stabilize. */
396 /* Enable the pipe */
397 temp
= REG_READ(map
->conf
);
398 if ((temp
& PIPEACONF_ENABLE
) == 0)
399 REG_WRITE(map
->conf
, temp
| PIPEACONF_ENABLE
);
401 /* Enable the plane */
402 temp
= REG_READ(map
->cntr
);
403 if ((temp
& DISPLAY_PLANE_ENABLE
) == 0) {
405 temp
| DISPLAY_PLANE_ENABLE
);
406 /* Flush the plane changes */
407 REG_WRITE(map
->base
, REG_READ(map
->base
));
410 psb_intel_crtc_load_lut(crtc
);
412 /* Give the overlay scaler a chance to enable
413 * if it's on this pipe */
414 /* psb_intel_crtc_dpms_video(crtc, true); TODO */
416 case DRM_MODE_DPMS_OFF
:
417 /* Give the overlay scaler a chance to disable
418 * if it's on this pipe */
419 /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */
421 /* Disable the VGA plane that we never use */
422 REG_WRITE(VGACNTRL
, VGA_DISP_DISABLE
);
424 /* Disable display plane */
425 temp
= REG_READ(map
->cntr
);
426 if ((temp
& DISPLAY_PLANE_ENABLE
) != 0) {
428 temp
& ~DISPLAY_PLANE_ENABLE
);
429 /* Flush the plane changes */
430 REG_WRITE(map
->base
, REG_READ(map
->base
));
434 /* Next, disable display pipes */
435 temp
= REG_READ(map
->conf
);
436 if ((temp
& PIPEACONF_ENABLE
) != 0) {
437 REG_WRITE(map
->conf
, temp
& ~PIPEACONF_ENABLE
);
441 /* Wait for vblank for the disable to take effect. */
442 psb_intel_wait_for_vblank(dev
);
444 temp
= REG_READ(map
->dpll
);
445 if ((temp
& DPLL_VCO_ENABLE
) != 0) {
446 REG_WRITE(map
->dpll
, temp
& ~DPLL_VCO_ENABLE
);
450 /* Wait for the clocks to turn off. */
455 /*Set FIFO Watermarks*/
456 REG_WRITE(DSPARB
, 0x3F3E);
459 static void psb_intel_crtc_prepare(struct drm_crtc
*crtc
)
461 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
462 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_OFF
);
465 static void psb_intel_crtc_commit(struct drm_crtc
*crtc
)
467 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
468 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
471 void psb_intel_encoder_prepare(struct drm_encoder
*encoder
)
473 struct drm_encoder_helper_funcs
*encoder_funcs
=
474 encoder
->helper_private
;
475 /* lvds has its own version of prepare see psb_intel_lvds_prepare */
476 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_OFF
);
479 void psb_intel_encoder_commit(struct drm_encoder
*encoder
)
481 struct drm_encoder_helper_funcs
*encoder_funcs
=
482 encoder
->helper_private
;
483 /* lvds has its own version of commit see psb_intel_lvds_commit */
484 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
487 void psb_intel_encoder_destroy(struct drm_encoder
*encoder
)
489 struct psb_intel_encoder
*intel_encoder
= to_psb_intel_encoder(encoder
);
491 drm_encoder_cleanup(encoder
);
492 kfree(intel_encoder
);
495 static bool psb_intel_crtc_mode_fixup(struct drm_crtc
*crtc
,
496 const struct drm_display_mode
*mode
,
497 struct drm_display_mode
*adjusted_mode
)
504 * Return the pipe currently connected to the panel fitter,
505 * or -1 if the panel fitter is not present or not in use
507 static int psb_intel_panel_fitter_pipe(struct drm_device
*dev
)
511 pfit_control
= REG_READ(PFIT_CONTROL
);
513 /* See if the panel fitter is in use */
514 if ((pfit_control
& PFIT_ENABLE
) == 0)
516 /* Must be on PIPE 1 for PSB */
520 static int psb_intel_crtc_mode_set(struct drm_crtc
*crtc
,
521 struct drm_display_mode
*mode
,
522 struct drm_display_mode
*adjusted_mode
,
524 struct drm_framebuffer
*old_fb
)
526 struct drm_device
*dev
= crtc
->dev
;
527 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
528 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
529 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
530 int pipe
= psb_intel_crtc
->pipe
;
531 const struct psb_offset
*map
= &dev_priv
->regmap
[pipe
];
533 struct psb_intel_clock_t clock
;
534 u32 dpll
= 0, fp
= 0, dspcntr
, pipeconf
;
535 bool ok
, is_sdvo
= false;
536 bool is_lvds
= false, is_tv
= false;
537 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
538 struct drm_connector
*connector
;
540 /* No scan out no play */
541 if (crtc
->fb
== NULL
) {
542 crtc_funcs
->mode_set_base(crtc
, x
, y
, old_fb
);
546 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
547 struct psb_intel_encoder
*psb_intel_encoder
=
548 psb_intel_attached_encoder(connector
);
550 if (!connector
->encoder
551 || connector
->encoder
->crtc
!= crtc
)
554 switch (psb_intel_encoder
->type
) {
555 case INTEL_OUTPUT_LVDS
:
558 case INTEL_OUTPUT_SDVO
:
561 case INTEL_OUTPUT_TVOUT
:
569 ok
= psb_intel_find_best_PLL(crtc
, adjusted_mode
->clock
, refclk
,
572 dev_err(dev
->dev
, "Couldn't find PLL settings for mode!\n");
576 fp
= clock
.n
<< 16 | clock
.m1
<< 8 | clock
.m2
;
578 dpll
= DPLL_VGA_MODE_DIS
;
580 dpll
|= DPLLB_MODE_LVDS
;
581 dpll
|= DPLL_DVO_HIGH_SPEED
;
583 dpll
|= DPLLB_MODE_DAC_SERIAL
;
585 int sdvo_pixel_multiply
=
586 adjusted_mode
->clock
/ mode
->clock
;
587 dpll
|= DPLL_DVO_HIGH_SPEED
;
589 (sdvo_pixel_multiply
- 1) << SDVO_MULTIPLIER_SHIFT_HIRES
;
592 /* compute bitmask from p1 value */
593 dpll
|= (1 << (clock
.p1
- 1)) << 16;
596 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
599 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
602 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
605 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
610 /* XXX: just matching BIOS for now */
611 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
614 dpll
|= PLL_REF_INPUT_DREFCLK
;
617 pipeconf
= REG_READ(map
->conf
);
619 /* Set up the display plane register */
620 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
623 dspcntr
|= DISPPLANE_SEL_PIPE_A
;
625 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
627 dspcntr
|= DISPLAY_PLANE_ENABLE
;
628 pipeconf
|= PIPEACONF_ENABLE
;
629 dpll
|= DPLL_VCO_ENABLE
;
632 /* Disable the panel fitter if it was on our pipe */
633 if (psb_intel_panel_fitter_pipe(dev
) == pipe
)
634 REG_WRITE(PFIT_CONTROL
, 0);
636 drm_mode_debug_printmodeline(mode
);
638 if (dpll
& DPLL_VCO_ENABLE
) {
639 REG_WRITE(map
->fp0
, fp
);
640 REG_WRITE(map
->dpll
, dpll
& ~DPLL_VCO_ENABLE
);
645 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
646 * This is an exception to the general rule that mode_set doesn't turn
650 u32 lvds
= REG_READ(LVDS
);
652 lvds
&= ~LVDS_PIPEB_SELECT
;
654 lvds
|= LVDS_PIPEB_SELECT
;
656 lvds
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
;
657 /* Set the B0-B3 data pairs corresponding to
658 * whether we're going to
659 * set the DPLLs for dual-channel mode or not.
661 lvds
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
663 lvds
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
665 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
666 * appropriately here, but we need to look more
667 * thoroughly into how panels behave in the two modes.
670 REG_WRITE(LVDS
, lvds
);
674 REG_WRITE(map
->fp0
, fp
);
675 REG_WRITE(map
->dpll
, dpll
);
677 /* Wait for the clocks to stabilize. */
680 /* write it again -- the BIOS does, after all */
681 REG_WRITE(map
->dpll
, dpll
);
684 /* Wait for the clocks to stabilize. */
687 REG_WRITE(map
->htotal
, (adjusted_mode
->crtc_hdisplay
- 1) |
688 ((adjusted_mode
->crtc_htotal
- 1) << 16));
689 REG_WRITE(map
->hblank
, (adjusted_mode
->crtc_hblank_start
- 1) |
690 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
691 REG_WRITE(map
->hsync
, (adjusted_mode
->crtc_hsync_start
- 1) |
692 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
693 REG_WRITE(map
->vtotal
, (adjusted_mode
->crtc_vdisplay
- 1) |
694 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
695 REG_WRITE(map
->vblank
, (adjusted_mode
->crtc_vblank_start
- 1) |
696 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
697 REG_WRITE(map
->vsync
, (adjusted_mode
->crtc_vsync_start
- 1) |
698 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
699 /* pipesrc and dspsize control the size that is scaled from,
700 * which should always be the user's requested size.
703 ((mode
->vdisplay
- 1) << 16) | (mode
->hdisplay
- 1));
704 REG_WRITE(map
->pos
, 0);
706 ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
707 REG_WRITE(map
->conf
, pipeconf
);
710 psb_intel_wait_for_vblank(dev
);
712 REG_WRITE(map
->cntr
, dspcntr
);
714 /* Flush the plane changes */
715 crtc_funcs
->mode_set_base(crtc
, x
, y
, old_fb
);
717 psb_intel_wait_for_vblank(dev
);
722 /** Loads the palette/gamma unit for the CRTC with the prepared values */
723 void psb_intel_crtc_load_lut(struct drm_crtc
*crtc
)
725 struct drm_device
*dev
= crtc
->dev
;
726 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
727 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
728 const struct psb_offset
*map
= &dev_priv
->regmap
[psb_intel_crtc
->pipe
];
729 int palreg
= map
->palette
;
732 /* The clocks have to be on to load the palette. */
736 switch (psb_intel_crtc
->pipe
) {
741 dev_err(dev
->dev
, "Illegal Pipe Number.\n");
745 if (gma_power_begin(dev
, false)) {
746 for (i
= 0; i
< 256; i
++) {
747 REG_WRITE(palreg
+ 4 * i
,
748 ((psb_intel_crtc
->lut_r
[i
] +
749 psb_intel_crtc
->lut_adj
[i
]) << 16) |
750 ((psb_intel_crtc
->lut_g
[i
] +
751 psb_intel_crtc
->lut_adj
[i
]) << 8) |
752 (psb_intel_crtc
->lut_b
[i
] +
753 psb_intel_crtc
->lut_adj
[i
]));
757 for (i
= 0; i
< 256; i
++) {
758 dev_priv
->regs
.pipe
[0].palette
[i
] =
759 ((psb_intel_crtc
->lut_r
[i
] +
760 psb_intel_crtc
->lut_adj
[i
]) << 16) |
761 ((psb_intel_crtc
->lut_g
[i
] +
762 psb_intel_crtc
->lut_adj
[i
]) << 8) |
763 (psb_intel_crtc
->lut_b
[i
] +
764 psb_intel_crtc
->lut_adj
[i
]);
771 * Save HW states of giving crtc
773 static void psb_intel_crtc_save(struct drm_crtc
*crtc
)
775 struct drm_device
*dev
= crtc
->dev
;
776 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
777 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
778 struct psb_intel_crtc_state
*crtc_state
= psb_intel_crtc
->crtc_state
;
779 const struct psb_offset
*map
= &dev_priv
->regmap
[psb_intel_crtc
->pipe
];
784 dev_err(dev
->dev
, "No CRTC state found\n");
788 crtc_state
->saveDSPCNTR
= REG_READ(map
->cntr
);
789 crtc_state
->savePIPECONF
= REG_READ(map
->conf
);
790 crtc_state
->savePIPESRC
= REG_READ(map
->src
);
791 crtc_state
->saveFP0
= REG_READ(map
->fp0
);
792 crtc_state
->saveFP1
= REG_READ(map
->fp1
);
793 crtc_state
->saveDPLL
= REG_READ(map
->dpll
);
794 crtc_state
->saveHTOTAL
= REG_READ(map
->htotal
);
795 crtc_state
->saveHBLANK
= REG_READ(map
->hblank
);
796 crtc_state
->saveHSYNC
= REG_READ(map
->hsync
);
797 crtc_state
->saveVTOTAL
= REG_READ(map
->vtotal
);
798 crtc_state
->saveVBLANK
= REG_READ(map
->vblank
);
799 crtc_state
->saveVSYNC
= REG_READ(map
->vsync
);
800 crtc_state
->saveDSPSTRIDE
= REG_READ(map
->stride
);
802 /*NOTE: DSPSIZE DSPPOS only for psb*/
803 crtc_state
->saveDSPSIZE
= REG_READ(map
->size
);
804 crtc_state
->saveDSPPOS
= REG_READ(map
->pos
);
806 crtc_state
->saveDSPBASE
= REG_READ(map
->base
);
808 paletteReg
= map
->palette
;
809 for (i
= 0; i
< 256; ++i
)
810 crtc_state
->savePalette
[i
] = REG_READ(paletteReg
+ (i
<< 2));
814 * Restore HW states of giving crtc
816 static void psb_intel_crtc_restore(struct drm_crtc
*crtc
)
818 struct drm_device
*dev
= crtc
->dev
;
819 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
820 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
821 struct psb_intel_crtc_state
*crtc_state
= psb_intel_crtc
->crtc_state
;
822 const struct psb_offset
*map
= &dev_priv
->regmap
[psb_intel_crtc
->pipe
];
827 dev_err(dev
->dev
, "No crtc state\n");
831 if (crtc_state
->saveDPLL
& DPLL_VCO_ENABLE
) {
833 crtc_state
->saveDPLL
& ~DPLL_VCO_ENABLE
);
838 REG_WRITE(map
->fp0
, crtc_state
->saveFP0
);
841 REG_WRITE(map
->fp1
, crtc_state
->saveFP1
);
844 REG_WRITE(map
->dpll
, crtc_state
->saveDPLL
);
848 REG_WRITE(map
->htotal
, crtc_state
->saveHTOTAL
);
849 REG_WRITE(map
->hblank
, crtc_state
->saveHBLANK
);
850 REG_WRITE(map
->hsync
, crtc_state
->saveHSYNC
);
851 REG_WRITE(map
->vtotal
, crtc_state
->saveVTOTAL
);
852 REG_WRITE(map
->vblank
, crtc_state
->saveVBLANK
);
853 REG_WRITE(map
->vsync
, crtc_state
->saveVSYNC
);
854 REG_WRITE(map
->stride
, crtc_state
->saveDSPSTRIDE
);
856 REG_WRITE(map
->size
, crtc_state
->saveDSPSIZE
);
857 REG_WRITE(map
->pos
, crtc_state
->saveDSPPOS
);
859 REG_WRITE(map
->src
, crtc_state
->savePIPESRC
);
860 REG_WRITE(map
->base
, crtc_state
->saveDSPBASE
);
861 REG_WRITE(map
->conf
, crtc_state
->savePIPECONF
);
863 psb_intel_wait_for_vblank(dev
);
865 REG_WRITE(map
->cntr
, crtc_state
->saveDSPCNTR
);
866 REG_WRITE(map
->base
, crtc_state
->saveDSPBASE
);
868 psb_intel_wait_for_vblank(dev
);
870 paletteReg
= map
->palette
;
871 for (i
= 0; i
< 256; ++i
)
872 REG_WRITE(paletteReg
+ (i
<< 2), crtc_state
->savePalette
[i
]);
875 static int psb_intel_crtc_cursor_set(struct drm_crtc
*crtc
,
876 struct drm_file
*file_priv
,
878 uint32_t width
, uint32_t height
)
880 struct drm_device
*dev
= crtc
->dev
;
881 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
882 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
883 int pipe
= psb_intel_crtc
->pipe
;
884 uint32_t control
= (pipe
== 0) ? CURACNTR
: CURBCNTR
;
885 uint32_t base
= (pipe
== 0) ? CURABASE
: CURBBASE
;
888 struct gtt_range
*gt
;
889 struct gtt_range
*cursor_gt
= psb_intel_crtc
->cursor_gt
;
890 struct drm_gem_object
*obj
;
891 void *tmp_dst
, *tmp_src
;
892 int ret
, i
, cursor_pages
;
894 /* if we want to turn of the cursor ignore width and height */
896 /* turn off the cursor */
897 temp
= CURSOR_MODE_DISABLE
;
899 if (gma_power_begin(dev
, false)) {
900 REG_WRITE(control
, temp
);
905 /* Unpin the old GEM object */
906 if (psb_intel_crtc
->cursor_obj
) {
907 gt
= container_of(psb_intel_crtc
->cursor_obj
,
908 struct gtt_range
, gem
);
910 drm_gem_object_unreference(psb_intel_crtc
->cursor_obj
);
911 psb_intel_crtc
->cursor_obj
= NULL
;
917 /* Currently we only support 64x64 cursors */
918 if (width
!= 64 || height
!= 64) {
919 dev_dbg(dev
->dev
, "we currently only support 64x64 cursors\n");
923 obj
= drm_gem_object_lookup(dev
, file_priv
, handle
);
927 if (obj
->size
< width
* height
* 4) {
928 dev_dbg(dev
->dev
, "buffer is to small\n");
932 gt
= container_of(obj
, struct gtt_range
, gem
);
934 /* Pin the memory into the GTT */
935 ret
= psb_gtt_pin(gt
);
937 dev_err(dev
->dev
, "Can not pin down handle 0x%x\n", handle
);
941 if (dev_priv
->ops
->cursor_needs_phys
) {
942 if (cursor_gt
== NULL
) {
943 dev_err(dev
->dev
, "No hardware cursor mem available");
947 /* Prevent overflow */
951 cursor_pages
= gt
->npage
;
953 /* Copy the cursor to cursor mem */
954 tmp_dst
= dev_priv
->vram_addr
+ cursor_gt
->offset
;
955 for (i
= 0; i
< cursor_pages
; i
++) {
956 tmp_src
= kmap(gt
->pages
[i
]);
957 memcpy(tmp_dst
, tmp_src
, PAGE_SIZE
);
958 kunmap(gt
->pages
[i
]);
959 tmp_dst
+= PAGE_SIZE
;
962 addr
= psb_intel_crtc
->cursor_addr
;
964 addr
= gt
->offset
; /* Or resource.start ??? */
965 psb_intel_crtc
->cursor_addr
= addr
;
969 /* set the pipe for the cursor */
970 temp
|= (pipe
<< 28);
971 temp
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
973 if (gma_power_begin(dev
, false)) {
974 REG_WRITE(control
, temp
);
975 REG_WRITE(base
, addr
);
979 /* unpin the old bo */
980 if (psb_intel_crtc
->cursor_obj
) {
981 gt
= container_of(psb_intel_crtc
->cursor_obj
,
982 struct gtt_range
, gem
);
984 drm_gem_object_unreference(psb_intel_crtc
->cursor_obj
);
985 psb_intel_crtc
->cursor_obj
= obj
;
990 static int psb_intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
992 struct drm_device
*dev
= crtc
->dev
;
993 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
994 int pipe
= psb_intel_crtc
->pipe
;
1000 temp
|= (CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
);
1004 temp
|= (CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
);
1008 temp
|= ((x
& CURSOR_POS_MASK
) << CURSOR_X_SHIFT
);
1009 temp
|= ((y
& CURSOR_POS_MASK
) << CURSOR_Y_SHIFT
);
1011 addr
= psb_intel_crtc
->cursor_addr
;
1013 if (gma_power_begin(dev
, false)) {
1014 REG_WRITE((pipe
== 0) ? CURAPOS
: CURBPOS
, temp
);
1015 REG_WRITE((pipe
== 0) ? CURABASE
: CURBBASE
, addr
);
1021 void psb_intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
,
1022 u16
*green
, u16
*blue
, uint32_t type
, uint32_t size
)
1024 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
1030 for (i
= 0; i
< 256; i
++) {
1031 psb_intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
1032 psb_intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
1033 psb_intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
1036 psb_intel_crtc_load_lut(crtc
);
1039 static int psb_crtc_set_config(struct drm_mode_set
*set
)
1042 struct drm_device
*dev
= set
->crtc
->dev
;
1043 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
1045 if (!dev_priv
->rpm_enabled
)
1046 return drm_crtc_helper_set_config(set
);
1048 pm_runtime_forbid(&dev
->pdev
->dev
);
1049 ret
= drm_crtc_helper_set_config(set
);
1050 pm_runtime_allow(&dev
->pdev
->dev
);
1054 /* Returns the clock of the currently programmed mode of the given pipe. */
1055 static int psb_intel_crtc_clock_get(struct drm_device
*dev
,
1056 struct drm_crtc
*crtc
)
1058 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
1059 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
1060 int pipe
= psb_intel_crtc
->pipe
;
1061 const struct psb_offset
*map
= &dev_priv
->regmap
[pipe
];
1064 struct psb_intel_clock_t clock
;
1066 struct psb_pipe
*p
= &dev_priv
->regs
.pipe
[pipe
];
1068 if (gma_power_begin(dev
, false)) {
1069 dpll
= REG_READ(map
->dpll
);
1070 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
1071 fp
= REG_READ(map
->fp0
);
1073 fp
= REG_READ(map
->fp1
);
1074 is_lvds
= (pipe
== 1) && (REG_READ(LVDS
) & LVDS_PORT_EN
);
1079 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
1084 is_lvds
= (pipe
== 1) && (dev_priv
->regs
.psb
.saveLVDS
&
1088 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
1089 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
1090 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
1095 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
1096 DPLL_FPA01_P1_POST_DIV_SHIFT
);
1099 if ((dpll
& PLL_REF_INPUT_MASK
) ==
1100 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
1101 /* XXX: might not be 66MHz */
1102 i8xx_clock(66000, &clock
);
1104 i8xx_clock(48000, &clock
);
1106 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
1111 DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
1112 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
1114 if (dpll
& PLL_P2_DIVIDE_BY_4
)
1119 i8xx_clock(48000, &clock
);
1122 /* XXX: It would be nice to validate the clocks, but we can't reuse
1123 * i830PllIsValid() because it relies on the xf86_config connector
1124 * configuration being accurate, which it isn't necessarily.
1130 /** Returns the currently programmed mode of the given pipe. */
1131 struct drm_display_mode
*psb_intel_crtc_mode_get(struct drm_device
*dev
,
1132 struct drm_crtc
*crtc
)
1134 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
1135 int pipe
= psb_intel_crtc
->pipe
;
1136 struct drm_display_mode
*mode
;
1141 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
1142 struct psb_pipe
*p
= &dev_priv
->regs
.pipe
[pipe
];
1143 const struct psb_offset
*map
= &dev_priv
->regmap
[pipe
];
1145 if (gma_power_begin(dev
, false)) {
1146 htot
= REG_READ(map
->htotal
);
1147 hsync
= REG_READ(map
->hsync
);
1148 vtot
= REG_READ(map
->vtotal
);
1149 vsync
= REG_READ(map
->vsync
);
1158 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
1162 mode
->clock
= psb_intel_crtc_clock_get(dev
, crtc
);
1163 mode
->hdisplay
= (htot
& 0xffff) + 1;
1164 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
1165 mode
->hsync_start
= (hsync
& 0xffff) + 1;
1166 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
1167 mode
->vdisplay
= (vtot
& 0xffff) + 1;
1168 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
1169 mode
->vsync_start
= (vsync
& 0xffff) + 1;
1170 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
1172 drm_mode_set_name(mode
);
1173 drm_mode_set_crtcinfo(mode
, 0);
1178 void psb_intel_crtc_destroy(struct drm_crtc
*crtc
)
1180 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
1181 struct gtt_range
*gt
;
1183 /* Unpin the old GEM object */
1184 if (psb_intel_crtc
->cursor_obj
) {
1185 gt
= container_of(psb_intel_crtc
->cursor_obj
,
1186 struct gtt_range
, gem
);
1188 drm_gem_object_unreference(psb_intel_crtc
->cursor_obj
);
1189 psb_intel_crtc
->cursor_obj
= NULL
;
1192 if (psb_intel_crtc
->cursor_gt
!= NULL
)
1193 psb_gtt_free_range(crtc
->dev
, psb_intel_crtc
->cursor_gt
);
1194 kfree(psb_intel_crtc
->crtc_state
);
1195 drm_crtc_cleanup(crtc
);
1196 kfree(psb_intel_crtc
);
1199 const struct drm_crtc_helper_funcs psb_intel_helper_funcs
= {
1200 .dpms
= psb_intel_crtc_dpms
,
1201 .mode_fixup
= psb_intel_crtc_mode_fixup
,
1202 .mode_set
= psb_intel_crtc_mode_set
,
1203 .mode_set_base
= psb_intel_pipe_set_base
,
1204 .prepare
= psb_intel_crtc_prepare
,
1205 .commit
= psb_intel_crtc_commit
,
1208 const struct drm_crtc_funcs psb_intel_crtc_funcs
= {
1209 .save
= psb_intel_crtc_save
,
1210 .restore
= psb_intel_crtc_restore
,
1211 .cursor_set
= psb_intel_crtc_cursor_set
,
1212 .cursor_move
= psb_intel_crtc_cursor_move
,
1213 .gamma_set
= psb_intel_crtc_gamma_set
,
1214 .set_config
= psb_crtc_set_config
,
1215 .destroy
= psb_intel_crtc_destroy
,
1219 * Set the default value of cursor control and base register
1220 * to zero. This is a workaround for h/w defect on Oaktrail
1222 static void psb_intel_cursor_init(struct drm_device
*dev
,
1223 struct psb_intel_crtc
*psb_intel_crtc
)
1225 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
1226 u32 control
[3] = { CURACNTR
, CURBCNTR
, CURCCNTR
};
1227 u32 base
[3] = { CURABASE
, CURBBASE
, CURCBASE
};
1228 struct gtt_range
*cursor_gt
;
1230 if (dev_priv
->ops
->cursor_needs_phys
) {
1231 /* Allocate 4 pages of stolen mem for a hardware cursor. That
1232 * is enough for the 64 x 64 ARGB cursors we support.
1234 cursor_gt
= psb_gtt_alloc_range(dev
, 4 * PAGE_SIZE
, "cursor", 1);
1236 psb_intel_crtc
->cursor_gt
= NULL
;
1239 psb_intel_crtc
->cursor_gt
= cursor_gt
;
1240 psb_intel_crtc
->cursor_addr
= dev_priv
->stolen_base
+
1243 psb_intel_crtc
->cursor_gt
= NULL
;
1247 REG_WRITE(control
[psb_intel_crtc
->pipe
], 0);
1248 REG_WRITE(base
[psb_intel_crtc
->pipe
], 0);
1251 void psb_intel_crtc_init(struct drm_device
*dev
, int pipe
,
1252 struct psb_intel_mode_device
*mode_dev
)
1254 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
1255 struct psb_intel_crtc
*psb_intel_crtc
;
1257 uint16_t *r_base
, *g_base
, *b_base
;
1259 /* We allocate a extra array of drm_connector pointers
1260 * for fbdev after the crtc */
1262 kzalloc(sizeof(struct psb_intel_crtc
) +
1263 (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)),
1265 if (psb_intel_crtc
== NULL
)
1268 psb_intel_crtc
->crtc_state
=
1269 kzalloc(sizeof(struct psb_intel_crtc_state
), GFP_KERNEL
);
1270 if (!psb_intel_crtc
->crtc_state
) {
1271 dev_err(dev
->dev
, "Crtc state error: No memory\n");
1272 kfree(psb_intel_crtc
);
1276 /* Set the CRTC operations from the chip specific data */
1277 drm_crtc_init(dev
, &psb_intel_crtc
->base
, dev_priv
->ops
->crtc_funcs
);
1279 drm_mode_crtc_set_gamma_size(&psb_intel_crtc
->base
, 256);
1280 psb_intel_crtc
->pipe
= pipe
;
1281 psb_intel_crtc
->plane
= pipe
;
1283 r_base
= psb_intel_crtc
->base
.gamma_store
;
1284 g_base
= r_base
+ 256;
1285 b_base
= g_base
+ 256;
1286 for (i
= 0; i
< 256; i
++) {
1287 psb_intel_crtc
->lut_r
[i
] = i
;
1288 psb_intel_crtc
->lut_g
[i
] = i
;
1289 psb_intel_crtc
->lut_b
[i
] = i
;
1294 psb_intel_crtc
->lut_adj
[i
] = 0;
1297 psb_intel_crtc
->mode_dev
= mode_dev
;
1298 psb_intel_crtc
->cursor_addr
= 0;
1300 drm_crtc_helper_add(&psb_intel_crtc
->base
,
1301 dev_priv
->ops
->crtc_helper
);
1303 /* Setup the array of drm_connector pointer array */
1304 psb_intel_crtc
->mode_set
.crtc
= &psb_intel_crtc
->base
;
1305 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
1306 dev_priv
->plane_to_crtc_mapping
[psb_intel_crtc
->plane
] != NULL
);
1307 dev_priv
->plane_to_crtc_mapping
[psb_intel_crtc
->plane
] =
1308 &psb_intel_crtc
->base
;
1309 dev_priv
->pipe_to_crtc_mapping
[psb_intel_crtc
->pipe
] =
1310 &psb_intel_crtc
->base
;
1311 psb_intel_crtc
->mode_set
.connectors
=
1312 (struct drm_connector
**) (psb_intel_crtc
+ 1);
1313 psb_intel_crtc
->mode_set
.num_connectors
= 0;
1314 psb_intel_cursor_init(dev
, psb_intel_crtc
);
1316 /* Set to true so that the pipe is forced off on initial config. */
1317 psb_intel_crtc
->active
= true;
1320 int psb_intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
1321 struct drm_file
*file_priv
)
1323 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
1324 struct drm_psb_get_pipe_from_crtc_id_arg
*pipe_from_crtc_id
= data
;
1325 struct drm_mode_object
*drmmode_obj
;
1326 struct psb_intel_crtc
*crtc
;
1329 dev_err(dev
->dev
, "called with no initialization\n");
1333 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
1334 DRM_MODE_OBJECT_CRTC
);
1337 dev_err(dev
->dev
, "no such CRTC id\n");
1341 crtc
= to_psb_intel_crtc(obj_to_crtc(drmmode_obj
));
1342 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
1347 struct drm_crtc
*psb_intel_get_crtc_from_pipe(struct drm_device
*dev
, int pipe
)
1349 struct drm_crtc
*crtc
= NULL
;
1351 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
1352 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
1353 if (psb_intel_crtc
->pipe
== pipe
)
1359 int psb_intel_connector_clones(struct drm_device
*dev
, int type_mask
)
1362 struct drm_connector
*connector
;
1365 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
1367 struct psb_intel_encoder
*psb_intel_encoder
=
1368 psb_intel_attached_encoder(connector
);
1369 if (type_mask
& (1 << psb_intel_encoder
->type
))
1370 index_mask
|= (1 << entry
);
1376 /* current intel driver doesn't take advantage of encoders
1377 always give back the encoder for the connector
1379 struct drm_encoder
*psb_intel_best_encoder(struct drm_connector
*connector
)
1381 struct psb_intel_encoder
*psb_intel_encoder
=
1382 psb_intel_attached_encoder(connector
);
1384 return &psb_intel_encoder
->base
;
1387 void psb_intel_connector_attach_encoder(struct psb_intel_connector
*connector
,
1388 struct psb_intel_encoder
*encoder
)
1390 connector
->encoder
= encoder
;
1391 drm_mode_connector_attach_encoder(&connector
->base
,