2 * Copyright (C) 2012 Texas Instruments
3 * Author: Rob Clark <robdclark@gmail.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/component.h>
19 #include <linux/hdmi.h>
20 #include <linux/module.h>
21 #include <linux/irq.h>
22 #include <sound/asoundef.h>
25 #include <drm/drm_atomic_helper.h>
26 #include <drm/drm_crtc_helper.h>
27 #include <drm/drm_edid.h>
28 #include <drm/drm_of.h>
29 #include <drm/i2c/tda998x.h>
31 #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
34 struct i2c_client
*cec
;
35 struct i2c_client
*hdmi
;
44 struct tda998x_encoder_params params
;
46 wait_queue_head_t wq_edid
;
47 volatile int wq_edid_wait
;
49 struct work_struct detect_work
;
50 struct timer_list edid_delay_timer
;
51 wait_queue_head_t edid_delay_waitq
;
52 bool edid_delay_active
;
54 struct drm_encoder encoder
;
55 struct drm_connector connector
;
58 #define conn_to_tda998x_priv(x) \
59 container_of(x, struct tda998x_priv, connector)
61 #define enc_to_tda998x_priv(x) \
62 container_of(x, struct tda998x_priv, encoder)
64 /* The TDA9988 series of devices use a paged register scheme.. to simplify
65 * things we encode the page # in upper bits of the register #. To read/
66 * write a given register, we need to make sure CURPAGE register is set
67 * appropriately. Which implies reads/writes are not atomic. Fun!
70 #define REG(page, addr) (((page) << 8) | (addr))
71 #define REG2ADDR(reg) ((reg) & 0xff)
72 #define REG2PAGE(reg) (((reg) >> 8) & 0xff)
74 #define REG_CURPAGE 0xff /* write */
77 /* Page 00h: General Control */
78 #define REG_VERSION_LSB REG(0x00, 0x00) /* read */
79 #define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */
80 # define MAIN_CNTRL0_SR (1 << 0)
81 # define MAIN_CNTRL0_DECS (1 << 1)
82 # define MAIN_CNTRL0_DEHS (1 << 2)
83 # define MAIN_CNTRL0_CECS (1 << 3)
84 # define MAIN_CNTRL0_CEHS (1 << 4)
85 # define MAIN_CNTRL0_SCALER (1 << 7)
86 #define REG_VERSION_MSB REG(0x00, 0x02) /* read */
87 #define REG_SOFTRESET REG(0x00, 0x0a) /* write */
88 # define SOFTRESET_AUDIO (1 << 0)
89 # define SOFTRESET_I2C_MASTER (1 << 1)
90 #define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */
91 #define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */
92 #define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
93 # define I2C_MASTER_DIS_MM (1 << 0)
94 # define I2C_MASTER_DIS_FILT (1 << 1)
95 # define I2C_MASTER_APP_STRT_LAT (1 << 2)
96 #define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */
97 # define FEAT_POWERDOWN_SPDIF (1 << 3)
98 #define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */
99 #define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */
100 #define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */
101 # define INT_FLAGS_2_EDID_BLK_RD (1 << 1)
102 #define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */
103 #define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */
104 #define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */
105 #define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */
106 #define REG_ENA_AP REG(0x00, 0x1e) /* read/write */
107 #define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */
108 # define VIP_CNTRL_0_MIRR_A (1 << 7)
109 # define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4)
110 # define VIP_CNTRL_0_MIRR_B (1 << 3)
111 # define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0)
112 #define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */
113 # define VIP_CNTRL_1_MIRR_C (1 << 7)
114 # define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4)
115 # define VIP_CNTRL_1_MIRR_D (1 << 3)
116 # define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0)
117 #define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */
118 # define VIP_CNTRL_2_MIRR_E (1 << 7)
119 # define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4)
120 # define VIP_CNTRL_2_MIRR_F (1 << 3)
121 # define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0)
122 #define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */
123 # define VIP_CNTRL_3_X_TGL (1 << 0)
124 # define VIP_CNTRL_3_H_TGL (1 << 1)
125 # define VIP_CNTRL_3_V_TGL (1 << 2)
126 # define VIP_CNTRL_3_EMB (1 << 3)
127 # define VIP_CNTRL_3_SYNC_DE (1 << 4)
128 # define VIP_CNTRL_3_SYNC_HS (1 << 5)
129 # define VIP_CNTRL_3_DE_INT (1 << 6)
130 # define VIP_CNTRL_3_EDGE (1 << 7)
131 #define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */
132 # define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0)
133 # define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2)
134 # define VIP_CNTRL_4_CCIR656 (1 << 4)
135 # define VIP_CNTRL_4_656_ALT (1 << 5)
136 # define VIP_CNTRL_4_TST_656 (1 << 6)
137 # define VIP_CNTRL_4_TST_PAT (1 << 7)
138 #define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */
139 # define VIP_CNTRL_5_CKCASE (1 << 0)
140 # define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1)
141 #define REG_MUX_AP REG(0x00, 0x26) /* read/write */
142 # define MUX_AP_SELECT_I2S 0x64
143 # define MUX_AP_SELECT_SPDIF 0x40
144 #define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */
145 #define REG_MAT_CONTRL REG(0x00, 0x80) /* write */
146 # define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0)
147 # define MAT_CONTRL_MAT_BP (1 << 2)
148 #define REG_VIDFORMAT REG(0x00, 0xa0) /* write */
149 #define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */
150 #define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */
151 #define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */
152 #define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */
153 #define REG_NPIX_MSB REG(0x00, 0xa5) /* write */
154 #define REG_NPIX_LSB REG(0x00, 0xa6) /* write */
155 #define REG_NLINE_MSB REG(0x00, 0xa7) /* write */
156 #define REG_NLINE_LSB REG(0x00, 0xa8) /* write */
157 #define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */
158 #define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */
159 #define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */
160 #define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */
161 #define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */
162 #define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */
163 #define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */
164 #define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */
165 #define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */
166 #define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */
167 #define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */
168 #define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */
169 #define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */
170 #define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */
171 #define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */
172 #define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */
173 #define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */
174 #define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */
175 #define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */
176 #define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */
177 #define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */
178 #define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */
179 #define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */
180 #define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */
181 #define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */
182 #define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */
183 #define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */
184 #define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */
185 #define REG_DE_START_MSB REG(0x00, 0xc5) /* write */
186 #define REG_DE_START_LSB REG(0x00, 0xc6) /* write */
187 #define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */
188 #define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */
189 #define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */
190 # define TBG_CNTRL_0_TOP_TGL (1 << 0)
191 # define TBG_CNTRL_0_TOP_SEL (1 << 1)
192 # define TBG_CNTRL_0_DE_EXT (1 << 2)
193 # define TBG_CNTRL_0_TOP_EXT (1 << 3)
194 # define TBG_CNTRL_0_FRAME_DIS (1 << 5)
195 # define TBG_CNTRL_0_SYNC_MTHD (1 << 6)
196 # define TBG_CNTRL_0_SYNC_ONCE (1 << 7)
197 #define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */
198 # define TBG_CNTRL_1_H_TGL (1 << 0)
199 # define TBG_CNTRL_1_V_TGL (1 << 1)
200 # define TBG_CNTRL_1_TGL_EN (1 << 2)
201 # define TBG_CNTRL_1_X_EXT (1 << 3)
202 # define TBG_CNTRL_1_H_EXT (1 << 4)
203 # define TBG_CNTRL_1_V_EXT (1 << 5)
204 # define TBG_CNTRL_1_DWIN_DIS (1 << 6)
205 #define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */
206 #define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */
207 # define HVF_CNTRL_0_SM (1 << 7)
208 # define HVF_CNTRL_0_RWB (1 << 6)
209 # define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2)
210 # define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0)
211 #define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */
212 # define HVF_CNTRL_1_FOR (1 << 0)
213 # define HVF_CNTRL_1_YUVBLK (1 << 1)
214 # define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2)
215 # define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4)
216 # define HVF_CNTRL_1_SEMI_PLANAR (1 << 6)
217 #define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */
218 #define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */
219 # define I2S_FORMAT(x) (((x) & 3) << 0)
220 #define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */
221 # define AIP_CLKSEL_AIP_SPDIF (0 << 3)
222 # define AIP_CLKSEL_AIP_I2S (1 << 3)
223 # define AIP_CLKSEL_FS_ACLK (0 << 0)
224 # define AIP_CLKSEL_FS_MCLK (1 << 0)
225 # define AIP_CLKSEL_FS_FS64SPDIF (2 << 0)
227 /* Page 02h: PLL settings */
228 #define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */
229 # define PLL_SERIAL_1_SRL_FDN (1 << 0)
230 # define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1)
231 # define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6)
232 #define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */
233 # define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0)
234 # define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4)
235 #define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */
236 # define PLL_SERIAL_3_SRL_CCIR (1 << 0)
237 # define PLL_SERIAL_3_SRL_DE (1 << 2)
238 # define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4)
239 #define REG_SERIALIZER REG(0x02, 0x03) /* read/write */
240 #define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */
241 #define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */
242 #define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */
243 #define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */
244 #define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */
245 #define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */
246 #define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */
247 #define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */
248 # define AUDIO_DIV_SERCLK_1 0
249 # define AUDIO_DIV_SERCLK_2 1
250 # define AUDIO_DIV_SERCLK_4 2
251 # define AUDIO_DIV_SERCLK_8 3
252 # define AUDIO_DIV_SERCLK_16 4
253 # define AUDIO_DIV_SERCLK_32 5
254 #define REG_SEL_CLK REG(0x02, 0x11) /* read/write */
255 # define SEL_CLK_SEL_CLK1 (1 << 0)
256 # define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1)
257 # define SEL_CLK_ENA_SC_CLK (1 << 3)
258 #define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */
261 /* Page 09h: EDID Control */
262 #define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */
263 /* next 127 successive registers are the EDID block */
264 #define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */
265 #define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */
266 #define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */
267 #define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */
268 #define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */
271 /* Page 10h: information frames and packets */
272 #define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */
273 #define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */
274 #define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */
275 #define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */
276 #define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */
279 /* Page 11h: audio settings and content info packets */
280 #define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */
281 # define AIP_CNTRL_0_RST_FIFO (1 << 0)
282 # define AIP_CNTRL_0_SWAP (1 << 1)
283 # define AIP_CNTRL_0_LAYOUT (1 << 2)
284 # define AIP_CNTRL_0_ACR_MAN (1 << 5)
285 # define AIP_CNTRL_0_RST_CTS (1 << 6)
286 #define REG_CA_I2S REG(0x11, 0x01) /* read/write */
287 # define CA_I2S_CA_I2S(x) (((x) & 31) << 0)
288 # define CA_I2S_HBR_CHSTAT (1 << 6)
289 #define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */
290 #define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */
291 #define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */
292 #define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */
293 #define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */
294 #define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */
295 #define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */
296 #define REG_CTS_N REG(0x11, 0x0c) /* read/write */
297 # define CTS_N_K(x) (((x) & 7) << 0)
298 # define CTS_N_M(x) (((x) & 3) << 4)
299 #define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */
300 # define ENC_CNTRL_RST_ENC (1 << 0)
301 # define ENC_CNTRL_RST_SEL (1 << 1)
302 # define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2)
303 #define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */
304 # define DIP_FLAGS_ACR (1 << 0)
305 # define DIP_FLAGS_GC (1 << 1)
306 #define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */
307 # define DIP_IF_FLAGS_IF1 (1 << 1)
308 # define DIP_IF_FLAGS_IF2 (1 << 2)
309 # define DIP_IF_FLAGS_IF3 (1 << 3)
310 # define DIP_IF_FLAGS_IF4 (1 << 4)
311 # define DIP_IF_FLAGS_IF5 (1 << 5)
312 #define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */
315 /* Page 12h: HDCP and OTP */
316 #define REG_TX3 REG(0x12, 0x9a) /* read/write */
317 #define REG_TX4 REG(0x12, 0x9b) /* read/write */
318 # define TX4_PD_RAM (1 << 1)
319 #define REG_TX33 REG(0x12, 0xb8) /* read/write */
320 # define TX33_HDMI (1 << 1)
323 /* Page 13h: Gamut related metadata packets */
327 /* CEC registers: (not paged)
329 #define REG_CEC_INTSTATUS 0xee /* read */
330 # define CEC_INTSTATUS_CEC (1 << 0)
331 # define CEC_INTSTATUS_HDMI (1 << 1)
332 #define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */
333 # define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7)
334 # define CEC_FRO_IM_CLK_CTRL_ENA_OTP (1 << 6)
335 # define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1)
336 # define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0)
337 #define REG_CEC_RXSHPDINTENA 0xfc /* read/write */
338 #define REG_CEC_RXSHPDINT 0xfd /* read */
339 # define CEC_RXSHPDINT_RXSENS BIT(0)
340 # define CEC_RXSHPDINT_HPD BIT(1)
341 #define REG_CEC_RXSHPDLEV 0xfe /* read */
342 # define CEC_RXSHPDLEV_RXSENS (1 << 0)
343 # define CEC_RXSHPDLEV_HPD (1 << 1)
345 #define REG_CEC_ENAMODS 0xff /* read/write */
346 # define CEC_ENAMODS_DIS_FRO (1 << 6)
347 # define CEC_ENAMODS_DIS_CCLK (1 << 5)
348 # define CEC_ENAMODS_EN_RXSENS (1 << 2)
349 # define CEC_ENAMODS_EN_HDMI (1 << 1)
350 # define CEC_ENAMODS_EN_CEC (1 << 0)
353 /* Device versions: */
354 #define TDA9989N2 0x0101
355 #define TDA19989 0x0201
356 #define TDA19989N2 0x0202
357 #define TDA19988 0x0301
360 cec_write(struct tda998x_priv
*priv
, u16 addr
, u8 val
)
362 struct i2c_client
*client
= priv
->cec
;
363 u8 buf
[] = {addr
, val
};
366 ret
= i2c_master_send(client
, buf
, sizeof(buf
));
368 dev_err(&client
->dev
, "Error %d writing to cec:0x%x\n", ret
, addr
);
372 cec_read(struct tda998x_priv
*priv
, u8 addr
)
374 struct i2c_client
*client
= priv
->cec
;
378 ret
= i2c_master_send(client
, &addr
, sizeof(addr
));
382 ret
= i2c_master_recv(client
, &val
, sizeof(val
));
389 dev_err(&client
->dev
, "Error %d reading from cec:0x%x\n", ret
, addr
);
394 set_page(struct tda998x_priv
*priv
, u16 reg
)
396 if (REG2PAGE(reg
) != priv
->current_page
) {
397 struct i2c_client
*client
= priv
->hdmi
;
399 REG_CURPAGE
, REG2PAGE(reg
)
401 int ret
= i2c_master_send(client
, buf
, sizeof(buf
));
403 dev_err(&client
->dev
, "%s %04x err %d\n", __func__
,
408 priv
->current_page
= REG2PAGE(reg
);
414 reg_read_range(struct tda998x_priv
*priv
, u16 reg
, char *buf
, int cnt
)
416 struct i2c_client
*client
= priv
->hdmi
;
417 u8 addr
= REG2ADDR(reg
);
420 mutex_lock(&priv
->mutex
);
421 ret
= set_page(priv
, reg
);
425 ret
= i2c_master_send(client
, &addr
, sizeof(addr
));
429 ret
= i2c_master_recv(client
, buf
, cnt
);
436 dev_err(&client
->dev
, "Error %d reading from 0x%x\n", ret
, reg
);
438 mutex_unlock(&priv
->mutex
);
443 reg_write_range(struct tda998x_priv
*priv
, u16 reg
, u8
*p
, int cnt
)
445 struct i2c_client
*client
= priv
->hdmi
;
449 buf
[0] = REG2ADDR(reg
);
450 memcpy(&buf
[1], p
, cnt
);
452 mutex_lock(&priv
->mutex
);
453 ret
= set_page(priv
, reg
);
457 ret
= i2c_master_send(client
, buf
, cnt
+ 1);
459 dev_err(&client
->dev
, "Error %d writing to 0x%x\n", ret
, reg
);
461 mutex_unlock(&priv
->mutex
);
465 reg_read(struct tda998x_priv
*priv
, u16 reg
)
470 ret
= reg_read_range(priv
, reg
, &val
, sizeof(val
));
477 reg_write(struct tda998x_priv
*priv
, u16 reg
, u8 val
)
479 struct i2c_client
*client
= priv
->hdmi
;
480 u8 buf
[] = {REG2ADDR(reg
), val
};
483 mutex_lock(&priv
->mutex
);
484 ret
= set_page(priv
, reg
);
488 ret
= i2c_master_send(client
, buf
, sizeof(buf
));
490 dev_err(&client
->dev
, "Error %d writing to 0x%x\n", ret
, reg
);
492 mutex_unlock(&priv
->mutex
);
496 reg_write16(struct tda998x_priv
*priv
, u16 reg
, u16 val
)
498 struct i2c_client
*client
= priv
->hdmi
;
499 u8 buf
[] = {REG2ADDR(reg
), val
>> 8, val
};
502 mutex_lock(&priv
->mutex
);
503 ret
= set_page(priv
, reg
);
507 ret
= i2c_master_send(client
, buf
, sizeof(buf
));
509 dev_err(&client
->dev
, "Error %d writing to 0x%x\n", ret
, reg
);
511 mutex_unlock(&priv
->mutex
);
515 reg_set(struct tda998x_priv
*priv
, u16 reg
, u8 val
)
519 old_val
= reg_read(priv
, reg
);
521 reg_write(priv
, reg
, old_val
| val
);
525 reg_clear(struct tda998x_priv
*priv
, u16 reg
, u8 val
)
529 old_val
= reg_read(priv
, reg
);
531 reg_write(priv
, reg
, old_val
& ~val
);
535 tda998x_reset(struct tda998x_priv
*priv
)
537 /* reset audio and i2c master: */
538 reg_write(priv
, REG_SOFTRESET
, SOFTRESET_AUDIO
| SOFTRESET_I2C_MASTER
);
540 reg_write(priv
, REG_SOFTRESET
, 0);
543 /* reset transmitter: */
544 reg_set(priv
, REG_MAIN_CNTRL0
, MAIN_CNTRL0_SR
);
545 reg_clear(priv
, REG_MAIN_CNTRL0
, MAIN_CNTRL0_SR
);
547 /* PLL registers common configuration */
548 reg_write(priv
, REG_PLL_SERIAL_1
, 0x00);
549 reg_write(priv
, REG_PLL_SERIAL_2
, PLL_SERIAL_2_SRL_NOSC(1));
550 reg_write(priv
, REG_PLL_SERIAL_3
, 0x00);
551 reg_write(priv
, REG_SERIALIZER
, 0x00);
552 reg_write(priv
, REG_BUFFER_OUT
, 0x00);
553 reg_write(priv
, REG_PLL_SCG1
, 0x00);
554 reg_write(priv
, REG_AUDIO_DIV
, AUDIO_DIV_SERCLK_8
);
555 reg_write(priv
, REG_SEL_CLK
, SEL_CLK_SEL_CLK1
| SEL_CLK_ENA_SC_CLK
);
556 reg_write(priv
, REG_PLL_SCGN1
, 0xfa);
557 reg_write(priv
, REG_PLL_SCGN2
, 0x00);
558 reg_write(priv
, REG_PLL_SCGR1
, 0x5b);
559 reg_write(priv
, REG_PLL_SCGR2
, 0x00);
560 reg_write(priv
, REG_PLL_SCG2
, 0x10);
562 /* Write the default value MUX register */
563 reg_write(priv
, REG_MUX_VP_VIP_OUT
, 0x24);
567 * The TDA998x has a problem when trying to read the EDID close to a
568 * HPD assertion: it needs a delay of 100ms to avoid timing out while
569 * trying to read EDID data.
571 * However, tda998x_encoder_get_modes() may be called at any moment
572 * after tda998x_connector_detect() indicates that we are connected, so
573 * we need to delay probing modes in tda998x_encoder_get_modes() after
574 * we have seen a HPD inactive->active transition. This code implements
577 static void tda998x_edid_delay_done(unsigned long data
)
579 struct tda998x_priv
*priv
= (struct tda998x_priv
*)data
;
581 priv
->edid_delay_active
= false;
582 wake_up(&priv
->edid_delay_waitq
);
583 schedule_work(&priv
->detect_work
);
586 static void tda998x_edid_delay_start(struct tda998x_priv
*priv
)
588 priv
->edid_delay_active
= true;
589 mod_timer(&priv
->edid_delay_timer
, jiffies
+ HZ
/10);
592 static int tda998x_edid_delay_wait(struct tda998x_priv
*priv
)
594 return wait_event_killable(priv
->edid_delay_waitq
, !priv
->edid_delay_active
);
598 * We need to run the KMS hotplug event helper outside of our threaded
599 * interrupt routine as this can call back into our get_modes method,
600 * which will want to make use of interrupts.
602 static void tda998x_detect_work(struct work_struct
*work
)
604 struct tda998x_priv
*priv
=
605 container_of(work
, struct tda998x_priv
, detect_work
);
606 struct drm_device
*dev
= priv
->encoder
.dev
;
609 drm_kms_helper_hotplug_event(dev
);
613 * only 2 interrupts may occur: screen plug/unplug and EDID read
615 static irqreturn_t
tda998x_irq_thread(int irq
, void *data
)
617 struct tda998x_priv
*priv
= data
;
618 u8 sta
, cec
, lvl
, flag0
, flag1
, flag2
;
619 bool handled
= false;
621 sta
= cec_read(priv
, REG_CEC_INTSTATUS
);
622 cec
= cec_read(priv
, REG_CEC_RXSHPDINT
);
623 lvl
= cec_read(priv
, REG_CEC_RXSHPDLEV
);
624 flag0
= reg_read(priv
, REG_INT_FLAGS_0
);
625 flag1
= reg_read(priv
, REG_INT_FLAGS_1
);
626 flag2
= reg_read(priv
, REG_INT_FLAGS_2
);
628 "tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n",
629 sta
, cec
, lvl
, flag0
, flag1
, flag2
);
631 if (cec
& CEC_RXSHPDINT_HPD
) {
632 if (lvl
& CEC_RXSHPDLEV_HPD
)
633 tda998x_edid_delay_start(priv
);
635 schedule_work(&priv
->detect_work
);
640 if ((flag2
& INT_FLAGS_2_EDID_BLK_RD
) && priv
->wq_edid_wait
) {
641 priv
->wq_edid_wait
= 0;
642 wake_up(&priv
->wq_edid
);
646 return IRQ_RETVAL(handled
);
650 tda998x_write_if(struct tda998x_priv
*priv
, u8 bit
, u16 addr
,
651 union hdmi_infoframe
*frame
)
656 len
= hdmi_infoframe_pack(frame
, buf
, sizeof(buf
));
658 dev_err(&priv
->hdmi
->dev
,
659 "hdmi_infoframe_pack() type=0x%02x failed: %zd\n",
660 frame
->any
.type
, len
);
664 reg_clear(priv
, REG_DIP_IF_FLAGS
, bit
);
665 reg_write_range(priv
, addr
, buf
, len
);
666 reg_set(priv
, REG_DIP_IF_FLAGS
, bit
);
670 tda998x_write_aif(struct tda998x_priv
*priv
, struct tda998x_encoder_params
*p
)
672 union hdmi_infoframe frame
;
674 hdmi_audio_infoframe_init(&frame
.audio
);
676 frame
.audio
.channels
= p
->audio_frame
[1] & 0x07;
677 frame
.audio
.channel_allocation
= p
->audio_frame
[4];
678 frame
.audio
.level_shift_value
= (p
->audio_frame
[5] & 0x78) >> 3;
679 frame
.audio
.downmix_inhibit
= (p
->audio_frame
[5] & 0x80) >> 7;
682 * L-PCM and IEC61937 compressed audio shall always set sample
683 * frequency to "refer to stream". For others, see the HDMI
686 frame
.audio
.sample_frequency
= (p
->audio_frame
[2] & 0x1c) >> 2;
688 tda998x_write_if(priv
, DIP_IF_FLAGS_IF4
, REG_IF4_HB0
, &frame
);
692 tda998x_write_avi(struct tda998x_priv
*priv
, struct drm_display_mode
*mode
)
694 union hdmi_infoframe frame
;
696 drm_hdmi_avi_infoframe_from_display_mode(&frame
.avi
, mode
);
697 frame
.avi
.quantization_range
= HDMI_QUANTIZATION_RANGE_FULL
;
699 tda998x_write_if(priv
, DIP_IF_FLAGS_IF2
, REG_IF2_HB0
, &frame
);
702 static void tda998x_audio_mute(struct tda998x_priv
*priv
, bool on
)
705 reg_set(priv
, REG_SOFTRESET
, SOFTRESET_AUDIO
);
706 reg_clear(priv
, REG_SOFTRESET
, SOFTRESET_AUDIO
);
707 reg_set(priv
, REG_AIP_CNTRL_0
, AIP_CNTRL_0_RST_FIFO
);
709 reg_clear(priv
, REG_AIP_CNTRL_0
, AIP_CNTRL_0_RST_FIFO
);
714 tda998x_configure_audio(struct tda998x_priv
*priv
,
715 struct drm_display_mode
*mode
, struct tda998x_encoder_params
*p
)
717 u8 buf
[6], clksel_aip
, clksel_fs
, cts_n
, adiv
;
720 /* Enable audio ports */
721 reg_write(priv
, REG_ENA_AP
, p
->audio_cfg
);
722 reg_write(priv
, REG_ENA_ACLK
, p
->audio_clk_cfg
);
724 /* Set audio input source */
725 switch (p
->audio_format
) {
727 reg_write(priv
, REG_MUX_AP
, MUX_AP_SELECT_SPDIF
);
728 clksel_aip
= AIP_CLKSEL_AIP_SPDIF
;
729 clksel_fs
= AIP_CLKSEL_FS_FS64SPDIF
;
730 cts_n
= CTS_N_M(3) | CTS_N_K(3);
734 reg_write(priv
, REG_MUX_AP
, MUX_AP_SELECT_I2S
);
735 clksel_aip
= AIP_CLKSEL_AIP_I2S
;
736 clksel_fs
= AIP_CLKSEL_FS_ACLK
;
737 cts_n
= CTS_N_M(3) | CTS_N_K(3);
745 reg_write(priv
, REG_AIP_CLKSEL
, clksel_aip
);
746 reg_clear(priv
, REG_AIP_CNTRL_0
, AIP_CNTRL_0_LAYOUT
|
747 AIP_CNTRL_0_ACR_MAN
); /* auto CTS */
748 reg_write(priv
, REG_CTS_N
, cts_n
);
751 * Audio input somehow depends on HDMI line rate which is
752 * related to pixclk. Testing showed that modes with pixclk
753 * >100MHz need a larger divider while <40MHz need the default.
754 * There is no detailed info in the datasheet, so we just
755 * assume 100MHz requires larger divider.
757 adiv
= AUDIO_DIV_SERCLK_8
;
758 if (mode
->clock
> 100000)
759 adiv
++; /* AUDIO_DIV_SERCLK_16 */
761 /* S/PDIF asks for a larger divider */
762 if (p
->audio_format
== AFMT_SPDIF
)
763 adiv
++; /* AUDIO_DIV_SERCLK_16 or _32 */
765 reg_write(priv
, REG_AUDIO_DIV
, adiv
);
768 * This is the approximate value of N, which happens to be
769 * the recommended values for non-coherent clocks.
771 n
= 128 * p
->audio_sample_rate
/ 1000;
773 /* Write the CTS and N values */
780 reg_write_range(priv
, REG_ACR_CTS_0
, buf
, 6);
782 /* Set CTS clock reference */
783 reg_write(priv
, REG_AIP_CLKSEL
, clksel_aip
| clksel_fs
);
785 /* Reset CTS generator */
786 reg_set(priv
, REG_AIP_CNTRL_0
, AIP_CNTRL_0_RST_CTS
);
787 reg_clear(priv
, REG_AIP_CNTRL_0
, AIP_CNTRL_0_RST_CTS
);
789 /* Write the channel status */
790 buf
[0] = IEC958_AES0_CON_NOT_COPYRIGHT
;
792 buf
[2] = IEC958_AES3_CON_FS_NOTID
;
793 buf
[3] = IEC958_AES4_CON_ORIGFS_NOTID
|
794 IEC958_AES4_CON_MAX_WORDLEN_24
;
795 reg_write_range(priv
, REG_CH_STAT_B(0), buf
, 4);
797 tda998x_audio_mute(priv
, true);
799 tda998x_audio_mute(priv
, false);
801 /* Write the audio information packet */
802 tda998x_write_aif(priv
, p
);
805 /* DRM encoder functions */
807 static void tda998x_encoder_set_config(struct tda998x_priv
*priv
,
808 const struct tda998x_encoder_params
*p
)
810 priv
->vip_cntrl_0
= VIP_CNTRL_0_SWAP_A(p
->swap_a
) |
811 (p
->mirr_a
? VIP_CNTRL_0_MIRR_A
: 0) |
812 VIP_CNTRL_0_SWAP_B(p
->swap_b
) |
813 (p
->mirr_b
? VIP_CNTRL_0_MIRR_B
: 0);
814 priv
->vip_cntrl_1
= VIP_CNTRL_1_SWAP_C(p
->swap_c
) |
815 (p
->mirr_c
? VIP_CNTRL_1_MIRR_C
: 0) |
816 VIP_CNTRL_1_SWAP_D(p
->swap_d
) |
817 (p
->mirr_d
? VIP_CNTRL_1_MIRR_D
: 0);
818 priv
->vip_cntrl_2
= VIP_CNTRL_2_SWAP_E(p
->swap_e
) |
819 (p
->mirr_e
? VIP_CNTRL_2_MIRR_E
: 0) |
820 VIP_CNTRL_2_SWAP_F(p
->swap_f
) |
821 (p
->mirr_f
? VIP_CNTRL_2_MIRR_F
: 0);
826 static void tda998x_encoder_dpms(struct drm_encoder
*encoder
, int mode
)
828 struct tda998x_priv
*priv
= enc_to_tda998x_priv(encoder
);
830 /* we only care about on or off: */
831 if (mode
!= DRM_MODE_DPMS_ON
)
832 mode
= DRM_MODE_DPMS_OFF
;
834 if (mode
== priv
->dpms
)
838 case DRM_MODE_DPMS_ON
:
839 /* enable video ports, audio will be enabled later */
840 reg_write(priv
, REG_ENA_VP_0
, 0xff);
841 reg_write(priv
, REG_ENA_VP_1
, 0xff);
842 reg_write(priv
, REG_ENA_VP_2
, 0xff);
843 /* set muxing after enabling ports: */
844 reg_write(priv
, REG_VIP_CNTRL_0
, priv
->vip_cntrl_0
);
845 reg_write(priv
, REG_VIP_CNTRL_1
, priv
->vip_cntrl_1
);
846 reg_write(priv
, REG_VIP_CNTRL_2
, priv
->vip_cntrl_2
);
848 case DRM_MODE_DPMS_OFF
:
849 /* disable video ports */
850 reg_write(priv
, REG_ENA_VP_0
, 0x00);
851 reg_write(priv
, REG_ENA_VP_1
, 0x00);
852 reg_write(priv
, REG_ENA_VP_2
, 0x00);
859 static int tda998x_connector_mode_valid(struct drm_connector
*connector
,
860 struct drm_display_mode
*mode
)
862 /* TDA19988 dotclock can go up to 165MHz */
863 struct tda998x_priv
*priv
= conn_to_tda998x_priv(connector
);
865 if (mode
->clock
> ((priv
->rev
== TDA19988
) ? 165000 : 150000))
866 return MODE_CLOCK_HIGH
;
867 if (mode
->htotal
>= BIT(13))
868 return MODE_BAD_HVALUE
;
869 if (mode
->vtotal
>= BIT(11))
870 return MODE_BAD_VVALUE
;
875 tda998x_encoder_mode_set(struct drm_encoder
*encoder
,
876 struct drm_display_mode
*mode
,
877 struct drm_display_mode
*adjusted_mode
)
879 struct tda998x_priv
*priv
= enc_to_tda998x_priv(encoder
);
880 u16 ref_pix
, ref_line
, n_pix
, n_line
;
881 u16 hs_pix_s
, hs_pix_e
;
882 u16 vs1_pix_s
, vs1_pix_e
, vs1_line_s
, vs1_line_e
;
883 u16 vs2_pix_s
, vs2_pix_e
, vs2_line_s
, vs2_line_e
;
884 u16 vwin1_line_s
, vwin1_line_e
;
885 u16 vwin2_line_s
, vwin2_line_e
;
886 u16 de_pix_s
, de_pix_e
;
890 * Internally TDA998x is using ITU-R BT.656 style sync but
891 * we get VESA style sync. TDA998x is using a reference pixel
892 * relative to ITU to sync to the input frame and for output
893 * sync generation. Currently, we are using reference detection
894 * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point
895 * which is position of rising VS with coincident rising HS.
897 * Now there is some issues to take care of:
898 * - HDMI data islands require sync-before-active
899 * - TDA998x register values must be > 0 to be enabled
900 * - REFLINE needs an additional offset of +1
901 * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB
903 * So we add +1 to all horizontal and vertical register values,
904 * plus an additional +3 for REFPIX as we are using RGB input only.
906 n_pix
= mode
->htotal
;
907 n_line
= mode
->vtotal
;
909 hs_pix_e
= mode
->hsync_end
- mode
->hdisplay
;
910 hs_pix_s
= mode
->hsync_start
- mode
->hdisplay
;
911 de_pix_e
= mode
->htotal
;
912 de_pix_s
= mode
->htotal
- mode
->hdisplay
;
913 ref_pix
= 3 + hs_pix_s
;
916 * Attached LCD controllers may generate broken sync. Allow
917 * those to adjust the position of the rising VS edge by adding
920 if (adjusted_mode
->flags
& DRM_MODE_FLAG_HSKEW
)
921 ref_pix
+= adjusted_mode
->hskew
;
923 if ((mode
->flags
& DRM_MODE_FLAG_INTERLACE
) == 0) {
924 ref_line
= 1 + mode
->vsync_start
- mode
->vdisplay
;
925 vwin1_line_s
= mode
->vtotal
- mode
->vdisplay
- 1;
926 vwin1_line_e
= vwin1_line_s
+ mode
->vdisplay
;
927 vs1_pix_s
= vs1_pix_e
= hs_pix_s
;
928 vs1_line_s
= mode
->vsync_start
- mode
->vdisplay
;
929 vs1_line_e
= vs1_line_s
+
930 mode
->vsync_end
- mode
->vsync_start
;
931 vwin2_line_s
= vwin2_line_e
= 0;
932 vs2_pix_s
= vs2_pix_e
= 0;
933 vs2_line_s
= vs2_line_e
= 0;
935 ref_line
= 1 + (mode
->vsync_start
- mode
->vdisplay
)/2;
936 vwin1_line_s
= (mode
->vtotal
- mode
->vdisplay
)/2;
937 vwin1_line_e
= vwin1_line_s
+ mode
->vdisplay
/2;
938 vs1_pix_s
= vs1_pix_e
= hs_pix_s
;
939 vs1_line_s
= (mode
->vsync_start
- mode
->vdisplay
)/2;
940 vs1_line_e
= vs1_line_s
+
941 (mode
->vsync_end
- mode
->vsync_start
)/2;
942 vwin2_line_s
= vwin1_line_s
+ mode
->vtotal
/2;
943 vwin2_line_e
= vwin2_line_s
+ mode
->vdisplay
/2;
944 vs2_pix_s
= vs2_pix_e
= hs_pix_s
+ mode
->htotal
/2;
945 vs2_line_s
= vs1_line_s
+ mode
->vtotal
/2 ;
946 vs2_line_e
= vs2_line_s
+
947 (mode
->vsync_end
- mode
->vsync_start
)/2;
950 div
= 148500 / mode
->clock
;
957 /* mute the audio FIFO: */
958 reg_set(priv
, REG_AIP_CNTRL_0
, AIP_CNTRL_0_RST_FIFO
);
960 /* set HDMI HDCP mode off: */
961 reg_write(priv
, REG_TBG_CNTRL_1
, TBG_CNTRL_1_DWIN_DIS
);
962 reg_clear(priv
, REG_TX33
, TX33_HDMI
);
963 reg_write(priv
, REG_ENC_CNTRL
, ENC_CNTRL_CTL_CODE(0));
965 /* no pre-filter or interpolator: */
966 reg_write(priv
, REG_HVF_CNTRL_0
, HVF_CNTRL_0_PREFIL(0) |
967 HVF_CNTRL_0_INTPOL(0));
968 reg_write(priv
, REG_VIP_CNTRL_5
, VIP_CNTRL_5_SP_CNT(0));
969 reg_write(priv
, REG_VIP_CNTRL_4
, VIP_CNTRL_4_BLANKIT(0) |
972 reg_clear(priv
, REG_PLL_SERIAL_1
, PLL_SERIAL_1_SRL_MAN_IZ
);
973 reg_clear(priv
, REG_PLL_SERIAL_3
, PLL_SERIAL_3_SRL_CCIR
|
974 PLL_SERIAL_3_SRL_DE
);
975 reg_write(priv
, REG_SERIALIZER
, 0);
976 reg_write(priv
, REG_HVF_CNTRL_1
, HVF_CNTRL_1_VQR(0));
978 /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */
980 reg_write(priv
, REG_RPT_CNTRL
, 0);
981 reg_write(priv
, REG_SEL_CLK
, SEL_CLK_SEL_VRF_CLK(0) |
982 SEL_CLK_SEL_CLK1
| SEL_CLK_ENA_SC_CLK
);
984 reg_write(priv
, REG_PLL_SERIAL_2
, PLL_SERIAL_2_SRL_NOSC(div
) |
985 PLL_SERIAL_2_SRL_PR(rep
));
987 /* set color matrix bypass flag: */
988 reg_write(priv
, REG_MAT_CONTRL
, MAT_CONTRL_MAT_BP
|
989 MAT_CONTRL_MAT_SC(1));
991 /* set BIAS tmds value: */
992 reg_write(priv
, REG_ANA_GENERAL
, 0x09);
995 * Sync on rising HSYNC/VSYNC
997 reg
= VIP_CNTRL_3_SYNC_HS
;
1000 * TDA19988 requires high-active sync at input stage,
1001 * so invert low-active sync provided by master encoder here
1003 if (mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
1004 reg
|= VIP_CNTRL_3_H_TGL
;
1005 if (mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
1006 reg
|= VIP_CNTRL_3_V_TGL
;
1007 reg_write(priv
, REG_VIP_CNTRL_3
, reg
);
1009 reg_write(priv
, REG_VIDFORMAT
, 0x00);
1010 reg_write16(priv
, REG_REFPIX_MSB
, ref_pix
);
1011 reg_write16(priv
, REG_REFLINE_MSB
, ref_line
);
1012 reg_write16(priv
, REG_NPIX_MSB
, n_pix
);
1013 reg_write16(priv
, REG_NLINE_MSB
, n_line
);
1014 reg_write16(priv
, REG_VS_LINE_STRT_1_MSB
, vs1_line_s
);
1015 reg_write16(priv
, REG_VS_PIX_STRT_1_MSB
, vs1_pix_s
);
1016 reg_write16(priv
, REG_VS_LINE_END_1_MSB
, vs1_line_e
);
1017 reg_write16(priv
, REG_VS_PIX_END_1_MSB
, vs1_pix_e
);
1018 reg_write16(priv
, REG_VS_LINE_STRT_2_MSB
, vs2_line_s
);
1019 reg_write16(priv
, REG_VS_PIX_STRT_2_MSB
, vs2_pix_s
);
1020 reg_write16(priv
, REG_VS_LINE_END_2_MSB
, vs2_line_e
);
1021 reg_write16(priv
, REG_VS_PIX_END_2_MSB
, vs2_pix_e
);
1022 reg_write16(priv
, REG_HS_PIX_START_MSB
, hs_pix_s
);
1023 reg_write16(priv
, REG_HS_PIX_STOP_MSB
, hs_pix_e
);
1024 reg_write16(priv
, REG_VWIN_START_1_MSB
, vwin1_line_s
);
1025 reg_write16(priv
, REG_VWIN_END_1_MSB
, vwin1_line_e
);
1026 reg_write16(priv
, REG_VWIN_START_2_MSB
, vwin2_line_s
);
1027 reg_write16(priv
, REG_VWIN_END_2_MSB
, vwin2_line_e
);
1028 reg_write16(priv
, REG_DE_START_MSB
, de_pix_s
);
1029 reg_write16(priv
, REG_DE_STOP_MSB
, de_pix_e
);
1031 if (priv
->rev
== TDA19988
) {
1032 /* let incoming pixels fill the active space (if any) */
1033 reg_write(priv
, REG_ENABLE_SPACE
, 0x00);
1037 * Always generate sync polarity relative to input sync and
1038 * revert input stage toggled sync at output stage
1040 reg
= TBG_CNTRL_1_DWIN_DIS
| TBG_CNTRL_1_TGL_EN
;
1041 if (mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
1042 reg
|= TBG_CNTRL_1_H_TGL
;
1043 if (mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
1044 reg
|= TBG_CNTRL_1_V_TGL
;
1045 reg_write(priv
, REG_TBG_CNTRL_1
, reg
);
1047 /* must be last register set: */
1048 reg_write(priv
, REG_TBG_CNTRL_0
, 0);
1050 /* Only setup the info frames if the sink is HDMI */
1051 if (priv
->is_hdmi_sink
) {
1052 /* We need to turn HDMI HDCP stuff on to get audio through */
1053 reg
&= ~TBG_CNTRL_1_DWIN_DIS
;
1054 reg_write(priv
, REG_TBG_CNTRL_1
, reg
);
1055 reg_write(priv
, REG_ENC_CNTRL
, ENC_CNTRL_CTL_CODE(1));
1056 reg_set(priv
, REG_TX33
, TX33_HDMI
);
1058 tda998x_write_avi(priv
, adjusted_mode
);
1060 if (priv
->params
.audio_cfg
)
1061 tda998x_configure_audio(priv
, adjusted_mode
,
1066 static enum drm_connector_status
1067 tda998x_connector_detect(struct drm_connector
*connector
, bool force
)
1069 struct tda998x_priv
*priv
= conn_to_tda998x_priv(connector
);
1070 u8 val
= cec_read(priv
, REG_CEC_RXSHPDLEV
);
1072 return (val
& CEC_RXSHPDLEV_HPD
) ? connector_status_connected
:
1073 connector_status_disconnected
;
1076 static int read_edid_block(void *data
, u8
*buf
, unsigned int blk
, size_t length
)
1078 struct tda998x_priv
*priv
= data
;
1082 offset
= (blk
& 1) ? 128 : 0;
1085 reg_write(priv
, REG_DDC_ADDR
, 0xa0);
1086 reg_write(priv
, REG_DDC_OFFS
, offset
);
1087 reg_write(priv
, REG_DDC_SEGM_ADDR
, 0x60);
1088 reg_write(priv
, REG_DDC_SEGM
, segptr
);
1090 /* enable reading EDID: */
1091 priv
->wq_edid_wait
= 1;
1092 reg_write(priv
, REG_EDID_CTRL
, 0x1);
1094 /* flag must be cleared by sw: */
1095 reg_write(priv
, REG_EDID_CTRL
, 0x0);
1097 /* wait for block read to complete: */
1098 if (priv
->hdmi
->irq
) {
1099 i
= wait_event_timeout(priv
->wq_edid
,
1100 !priv
->wq_edid_wait
,
1101 msecs_to_jiffies(100));
1103 dev_err(&priv
->hdmi
->dev
, "read edid wait err %d\n", i
);
1107 for (i
= 100; i
> 0; i
--) {
1109 ret
= reg_read(priv
, REG_INT_FLAGS_2
);
1112 if (ret
& INT_FLAGS_2_EDID_BLK_RD
)
1118 dev_err(&priv
->hdmi
->dev
, "read edid timeout\n");
1122 ret
= reg_read_range(priv
, REG_EDID_DATA_0
, buf
, length
);
1123 if (ret
!= length
) {
1124 dev_err(&priv
->hdmi
->dev
, "failed to read edid block %d: %d\n",
1132 static int tda998x_connector_get_modes(struct drm_connector
*connector
)
1134 struct tda998x_priv
*priv
= conn_to_tda998x_priv(connector
);
1139 * If we get killed while waiting for the HPD timeout, return
1140 * no modes found: we are not in a restartable path, so we
1141 * can't handle signals gracefully.
1143 if (tda998x_edid_delay_wait(priv
))
1146 if (priv
->rev
== TDA19988
)
1147 reg_clear(priv
, REG_TX4
, TX4_PD_RAM
);
1149 edid
= drm_do_get_edid(connector
, read_edid_block
, priv
);
1151 if (priv
->rev
== TDA19988
)
1152 reg_set(priv
, REG_TX4
, TX4_PD_RAM
);
1155 dev_warn(&priv
->hdmi
->dev
, "failed to read EDID\n");
1159 drm_mode_connector_update_edid_property(connector
, edid
);
1160 n
= drm_add_edid_modes(connector
, edid
);
1161 priv
->is_hdmi_sink
= drm_detect_hdmi_monitor(edid
);
1167 static void tda998x_encoder_set_polling(struct tda998x_priv
*priv
,
1168 struct drm_connector
*connector
)
1170 if (priv
->hdmi
->irq
)
1171 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
1173 connector
->polled
= DRM_CONNECTOR_POLL_CONNECT
|
1174 DRM_CONNECTOR_POLL_DISCONNECT
;
1177 static void tda998x_destroy(struct tda998x_priv
*priv
)
1179 /* disable all IRQs and free the IRQ handler */
1180 cec_write(priv
, REG_CEC_RXSHPDINTENA
, 0);
1181 reg_clear(priv
, REG_INT_FLAGS_2
, INT_FLAGS_2_EDID_BLK_RD
);
1183 if (priv
->hdmi
->irq
)
1184 free_irq(priv
->hdmi
->irq
, priv
);
1186 del_timer_sync(&priv
->edid_delay_timer
);
1187 cancel_work_sync(&priv
->detect_work
);
1189 i2c_unregister_device(priv
->cec
);
1192 /* I2C driver functions */
1194 static int tda998x_create(struct i2c_client
*client
, struct tda998x_priv
*priv
)
1196 struct device_node
*np
= client
->dev
.of_node
;
1198 int rev_lo
, rev_hi
, ret
;
1199 unsigned short cec_addr
;
1201 priv
->vip_cntrl_0
= VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3);
1202 priv
->vip_cntrl_1
= VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1);
1203 priv
->vip_cntrl_2
= VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5);
1205 priv
->current_page
= 0xff;
1206 priv
->hdmi
= client
;
1207 /* CEC I2C address bound to TDA998x I2C addr by configuration pins */
1208 cec_addr
= 0x34 + (client
->addr
& 0x03);
1209 priv
->cec
= i2c_new_dummy(client
->adapter
, cec_addr
);
1213 priv
->dpms
= DRM_MODE_DPMS_OFF
;
1215 mutex_init(&priv
->mutex
); /* protect the page access */
1216 init_waitqueue_head(&priv
->edid_delay_waitq
);
1217 setup_timer(&priv
->edid_delay_timer
, tda998x_edid_delay_done
,
1218 (unsigned long)priv
);
1219 INIT_WORK(&priv
->detect_work
, tda998x_detect_work
);
1221 /* wake up the device: */
1222 cec_write(priv
, REG_CEC_ENAMODS
,
1223 CEC_ENAMODS_EN_RXSENS
| CEC_ENAMODS_EN_HDMI
);
1225 tda998x_reset(priv
);
1228 rev_lo
= reg_read(priv
, REG_VERSION_LSB
);
1229 rev_hi
= reg_read(priv
, REG_VERSION_MSB
);
1230 if (rev_lo
< 0 || rev_hi
< 0) {
1231 ret
= rev_lo
< 0 ? rev_lo
: rev_hi
;
1235 priv
->rev
= rev_lo
| rev_hi
<< 8;
1237 /* mask off feature bits: */
1238 priv
->rev
&= ~0x30; /* not-hdcp and not-scalar bit */
1240 switch (priv
->rev
) {
1242 dev_info(&client
->dev
, "found TDA9989 n2");
1245 dev_info(&client
->dev
, "found TDA19989");
1248 dev_info(&client
->dev
, "found TDA19989 n2");
1251 dev_info(&client
->dev
, "found TDA19988");
1254 dev_err(&client
->dev
, "found unsupported device: %04x\n",
1259 /* after reset, enable DDC: */
1260 reg_write(priv
, REG_DDC_DISABLE
, 0x00);
1262 /* set clock on DDC channel: */
1263 reg_write(priv
, REG_TX3
, 39);
1265 /* if necessary, disable multi-master: */
1266 if (priv
->rev
== TDA19989
)
1267 reg_set(priv
, REG_I2C_MASTER
, I2C_MASTER_DIS_MM
);
1269 cec_write(priv
, REG_CEC_FRO_IM_CLK_CTRL
,
1270 CEC_FRO_IM_CLK_CTRL_GHOST_DIS
| CEC_FRO_IM_CLK_CTRL_IMCLK_SEL
);
1272 /* initialize the optional IRQ */
1276 /* init read EDID waitqueue and HDP work */
1277 init_waitqueue_head(&priv
->wq_edid
);
1279 /* clear pending interrupts */
1280 reg_read(priv
, REG_INT_FLAGS_0
);
1281 reg_read(priv
, REG_INT_FLAGS_1
);
1282 reg_read(priv
, REG_INT_FLAGS_2
);
1285 irqd_get_trigger_type(irq_get_irq_data(client
->irq
));
1286 ret
= request_threaded_irq(client
->irq
, NULL
,
1288 irqf_trigger
| IRQF_ONESHOT
,
1291 dev_err(&client
->dev
,
1292 "failed to request IRQ#%u: %d\n",
1297 /* enable HPD irq */
1298 cec_write(priv
, REG_CEC_RXSHPDINTENA
, CEC_RXSHPDLEV_HPD
);
1301 /* enable EDID read irq: */
1302 reg_set(priv
, REG_INT_FLAGS_2
, INT_FLAGS_2_EDID_BLK_RD
);
1305 return 0; /* non-DT */
1307 /* get the optional video properties */
1308 ret
= of_property_read_u32(np
, "video-ports", &video
);
1310 priv
->vip_cntrl_0
= video
>> 16;
1311 priv
->vip_cntrl_1
= video
>> 8;
1312 priv
->vip_cntrl_2
= video
;
1318 /* if encoder_init fails, the encoder slave is never registered,
1322 i2c_unregister_device(priv
->cec
);
1326 static void tda998x_encoder_prepare(struct drm_encoder
*encoder
)
1328 tda998x_encoder_dpms(encoder
, DRM_MODE_DPMS_OFF
);
1331 static void tda998x_encoder_commit(struct drm_encoder
*encoder
)
1333 tda998x_encoder_dpms(encoder
, DRM_MODE_DPMS_ON
);
1336 static const struct drm_encoder_helper_funcs tda998x_encoder_helper_funcs
= {
1337 .dpms
= tda998x_encoder_dpms
,
1338 .prepare
= tda998x_encoder_prepare
,
1339 .commit
= tda998x_encoder_commit
,
1340 .mode_set
= tda998x_encoder_mode_set
,
1343 static void tda998x_encoder_destroy(struct drm_encoder
*encoder
)
1345 struct tda998x_priv
*priv
= enc_to_tda998x_priv(encoder
);
1347 tda998x_destroy(priv
);
1348 drm_encoder_cleanup(encoder
);
1351 static const struct drm_encoder_funcs tda998x_encoder_funcs
= {
1352 .destroy
= tda998x_encoder_destroy
,
1355 static struct drm_encoder
*
1356 tda998x_connector_best_encoder(struct drm_connector
*connector
)
1358 struct tda998x_priv
*priv
= conn_to_tda998x_priv(connector
);
1360 return &priv
->encoder
;
1364 const struct drm_connector_helper_funcs tda998x_connector_helper_funcs
= {
1365 .get_modes
= tda998x_connector_get_modes
,
1366 .mode_valid
= tda998x_connector_mode_valid
,
1367 .best_encoder
= tda998x_connector_best_encoder
,
1370 static void tda998x_connector_destroy(struct drm_connector
*connector
)
1372 drm_connector_unregister(connector
);
1373 drm_connector_cleanup(connector
);
1376 static int tda998x_connector_dpms(struct drm_connector
*connector
, int mode
)
1378 if (drm_core_check_feature(connector
->dev
, DRIVER_ATOMIC
))
1379 return drm_atomic_helper_connector_dpms(connector
, mode
);
1381 return drm_helper_connector_dpms(connector
, mode
);
1384 static const struct drm_connector_funcs tda998x_connector_funcs
= {
1385 .dpms
= tda998x_connector_dpms
,
1386 .reset
= drm_atomic_helper_connector_reset
,
1387 .fill_modes
= drm_helper_probe_single_connector_modes
,
1388 .detect
= tda998x_connector_detect
,
1389 .destroy
= tda998x_connector_destroy
,
1390 .atomic_duplicate_state
= drm_atomic_helper_connector_duplicate_state
,
1391 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
1394 static int tda998x_bind(struct device
*dev
, struct device
*master
, void *data
)
1396 struct tda998x_encoder_params
*params
= dev
->platform_data
;
1397 struct i2c_client
*client
= to_i2c_client(dev
);
1398 struct drm_device
*drm
= data
;
1399 struct tda998x_priv
*priv
;
1403 priv
= devm_kzalloc(dev
, sizeof(*priv
), GFP_KERNEL
);
1407 dev_set_drvdata(dev
, priv
);
1410 crtcs
= drm_of_find_possible_crtcs(drm
, dev
->of_node
);
1412 /* If no CRTCs were found, fall back to our old behaviour */
1414 dev_warn(dev
, "Falling back to first CRTC\n");
1418 priv
->connector
.interlace_allowed
= 1;
1419 priv
->encoder
.possible_crtcs
= crtcs
;
1421 ret
= tda998x_create(client
, priv
);
1425 if (!dev
->of_node
&& params
)
1426 tda998x_encoder_set_config(priv
, params
);
1428 tda998x_encoder_set_polling(priv
, &priv
->connector
);
1430 drm_encoder_helper_add(&priv
->encoder
, &tda998x_encoder_helper_funcs
);
1431 ret
= drm_encoder_init(drm
, &priv
->encoder
, &tda998x_encoder_funcs
,
1432 DRM_MODE_ENCODER_TMDS
, NULL
);
1436 drm_connector_helper_add(&priv
->connector
,
1437 &tda998x_connector_helper_funcs
);
1438 ret
= drm_connector_init(drm
, &priv
->connector
,
1439 &tda998x_connector_funcs
,
1440 DRM_MODE_CONNECTOR_HDMIA
);
1444 ret
= drm_connector_register(&priv
->connector
);
1448 drm_mode_connector_attach_encoder(&priv
->connector
, &priv
->encoder
);
1453 drm_connector_cleanup(&priv
->connector
);
1455 drm_encoder_cleanup(&priv
->encoder
);
1457 tda998x_destroy(priv
);
1461 static void tda998x_unbind(struct device
*dev
, struct device
*master
,
1464 struct tda998x_priv
*priv
= dev_get_drvdata(dev
);
1466 drm_connector_unregister(&priv
->connector
);
1467 drm_connector_cleanup(&priv
->connector
);
1468 drm_encoder_cleanup(&priv
->encoder
);
1469 tda998x_destroy(priv
);
1472 static const struct component_ops tda998x_ops
= {
1473 .bind
= tda998x_bind
,
1474 .unbind
= tda998x_unbind
,
1478 tda998x_probe(struct i2c_client
*client
, const struct i2c_device_id
*id
)
1480 return component_add(&client
->dev
, &tda998x_ops
);
1483 static int tda998x_remove(struct i2c_client
*client
)
1485 component_del(&client
->dev
, &tda998x_ops
);
1490 static const struct of_device_id tda998x_dt_ids
[] = {
1491 { .compatible
= "nxp,tda998x", },
1494 MODULE_DEVICE_TABLE(of
, tda998x_dt_ids
);
1497 static struct i2c_device_id tda998x_ids
[] = {
1501 MODULE_DEVICE_TABLE(i2c
, tda998x_ids
);
1503 static struct i2c_driver tda998x_driver
= {
1504 .probe
= tda998x_probe
,
1505 .remove
= tda998x_remove
,
1508 .of_match_table
= of_match_ptr(tda998x_dt_ids
),
1510 .id_table
= tda998x_ids
,
1513 module_i2c_driver(tda998x_driver
);
1515 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1516 MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder");
1517 MODULE_LICENSE("GPL");