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drm/i915: Flatten engine init control flow
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_cmd_parser.c
1 /*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Brad Volkin <bradley.d.volkin@intel.com>
25 *
26 */
27
28 #include "i915_drv.h"
29
30 /**
31 * DOC: batch buffer command parser
32 *
33 * Motivation:
34 * Certain OpenGL features (e.g. transform feedback, performance monitoring)
35 * require userspace code to submit batches containing commands such as
36 * MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some
37 * generations of the hardware will noop these commands in "unsecure" batches
38 * (which includes all userspace batches submitted via i915) even though the
39 * commands may be safe and represent the intended programming model of the
40 * device.
41 *
42 * The software command parser is similar in operation to the command parsing
43 * done in hardware for unsecure batches. However, the software parser allows
44 * some operations that would be noop'd by hardware, if the parser determines
45 * the operation is safe, and submits the batch as "secure" to prevent hardware
46 * parsing.
47 *
48 * Threats:
49 * At a high level, the hardware (and software) checks attempt to prevent
50 * granting userspace undue privileges. There are three categories of privilege.
51 *
52 * First, commands which are explicitly defined as privileged or which should
53 * only be used by the kernel driver. The parser generally rejects such
54 * commands, though it may allow some from the drm master process.
55 *
56 * Second, commands which access registers. To support correct/enhanced
57 * userspace functionality, particularly certain OpenGL extensions, the parser
58 * provides a whitelist of registers which userspace may safely access (for both
59 * normal and drm master processes).
60 *
61 * Third, commands which access privileged memory (i.e. GGTT, HWS page, etc).
62 * The parser always rejects such commands.
63 *
64 * The majority of the problematic commands fall in the MI_* range, with only a
65 * few specific commands on each ring (e.g. PIPE_CONTROL and MI_FLUSH_DW).
66 *
67 * Implementation:
68 * Each ring maintains tables of commands and registers which the parser uses in
69 * scanning batch buffers submitted to that ring.
70 *
71 * Since the set of commands that the parser must check for is significantly
72 * smaller than the number of commands supported, the parser tables contain only
73 * those commands required by the parser. This generally works because command
74 * opcode ranges have standard command length encodings. So for commands that
75 * the parser does not need to check, it can easily skip them. This is
76 * implemented via a per-ring length decoding vfunc.
77 *
78 * Unfortunately, there are a number of commands that do not follow the standard
79 * length encoding for their opcode range, primarily amongst the MI_* commands.
80 * To handle this, the parser provides a way to define explicit "skip" entries
81 * in the per-ring command tables.
82 *
83 * Other command table entries map fairly directly to high level categories
84 * mentioned above: rejected, master-only, register whitelist. The parser
85 * implements a number of checks, including the privileged memory checks, via a
86 * general bitmasking mechanism.
87 */
88
89 #define STD_MI_OPCODE_MASK 0xFF800000
90 #define STD_3D_OPCODE_MASK 0xFFFF0000
91 #define STD_2D_OPCODE_MASK 0xFFC00000
92 #define STD_MFX_OPCODE_MASK 0xFFFF0000
93
94 #define CMD(op, opm, f, lm, fl, ...) \
95 { \
96 .flags = (fl) | ((f) ? CMD_DESC_FIXED : 0), \
97 .cmd = { (op), (opm) }, \
98 .length = { (lm) }, \
99 __VA_ARGS__ \
100 }
101
102 /* Convenience macros to compress the tables */
103 #define SMI STD_MI_OPCODE_MASK
104 #define S3D STD_3D_OPCODE_MASK
105 #define S2D STD_2D_OPCODE_MASK
106 #define SMFX STD_MFX_OPCODE_MASK
107 #define F true
108 #define S CMD_DESC_SKIP
109 #define R CMD_DESC_REJECT
110 #define W CMD_DESC_REGISTER
111 #define B CMD_DESC_BITMASK
112 #define M CMD_DESC_MASTER
113
114 /* Command Mask Fixed Len Action
115 ---------------------------------------------------------- */
116 static const struct drm_i915_cmd_descriptor common_cmds[] = {
117 CMD( MI_NOOP, SMI, F, 1, S ),
118 CMD( MI_USER_INTERRUPT, SMI, F, 1, R ),
119 CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, M ),
120 CMD( MI_ARB_CHECK, SMI, F, 1, S ),
121 CMD( MI_REPORT_HEAD, SMI, F, 1, S ),
122 CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ),
123 CMD( MI_SEMAPHORE_MBOX, SMI, !F, 0xFF, R ),
124 CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, R ),
125 CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W,
126 .reg = { .offset = 1, .mask = 0x007FFFFC } ),
127 CMD( MI_STORE_REGISTER_MEM(1), SMI, !F, 0xFF, W | B,
128 .reg = { .offset = 1, .mask = 0x007FFFFC },
129 .bits = {{
130 .offset = 0,
131 .mask = MI_GLOBAL_GTT,
132 .expected = 0,
133 }}, ),
134 CMD( MI_LOAD_REGISTER_MEM, SMI, !F, 0xFF, W | B,
135 .reg = { .offset = 1, .mask = 0x007FFFFC },
136 .bits = {{
137 .offset = 0,
138 .mask = MI_GLOBAL_GTT,
139 .expected = 0,
140 }}, ),
141 /*
142 * MI_BATCH_BUFFER_START requires some special handling. It's not
143 * really a 'skip' action but it doesn't seem like it's worth adding
144 * a new action. See i915_parse_cmds().
145 */
146 CMD( MI_BATCH_BUFFER_START, SMI, !F, 0xFF, S ),
147 };
148
149 static const struct drm_i915_cmd_descriptor render_cmds[] = {
150 CMD( MI_FLUSH, SMI, F, 1, S ),
151 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
152 CMD( MI_PREDICATE, SMI, F, 1, S ),
153 CMD( MI_TOPOLOGY_FILTER, SMI, F, 1, S ),
154 CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ),
155 CMD( MI_SET_CONTEXT, SMI, !F, 0xFF, R ),
156 CMD( MI_URB_CLEAR, SMI, !F, 0xFF, S ),
157 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3F, B,
158 .bits = {{
159 .offset = 0,
160 .mask = MI_GLOBAL_GTT,
161 .expected = 0,
162 }}, ),
163 CMD( MI_UPDATE_GTT, SMI, !F, 0xFF, R ),
164 CMD( MI_CLFLUSH, SMI, !F, 0x3FF, B,
165 .bits = {{
166 .offset = 0,
167 .mask = MI_GLOBAL_GTT,
168 .expected = 0,
169 }}, ),
170 CMD( MI_REPORT_PERF_COUNT, SMI, !F, 0x3F, B,
171 .bits = {{
172 .offset = 1,
173 .mask = MI_REPORT_PERF_COUNT_GGTT,
174 .expected = 0,
175 }}, ),
176 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,
177 .bits = {{
178 .offset = 0,
179 .mask = MI_GLOBAL_GTT,
180 .expected = 0,
181 }}, ),
182 CMD( GFX_OP_3DSTATE_VF_STATISTICS, S3D, F, 1, S ),
183 CMD( PIPELINE_SELECT, S3D, F, 1, S ),
184 CMD( MEDIA_VFE_STATE, S3D, !F, 0xFFFF, B,
185 .bits = {{
186 .offset = 2,
187 .mask = MEDIA_VFE_STATE_MMIO_ACCESS_MASK,
188 .expected = 0,
189 }}, ),
190 CMD( GPGPU_OBJECT, S3D, !F, 0xFF, S ),
191 CMD( GPGPU_WALKER, S3D, !F, 0xFF, S ),
192 CMD( GFX_OP_3DSTATE_SO_DECL_LIST, S3D, !F, 0x1FF, S ),
193 CMD( GFX_OP_PIPE_CONTROL(5), S3D, !F, 0xFF, B,
194 .bits = {{
195 .offset = 1,
196 .mask = (PIPE_CONTROL_MMIO_WRITE | PIPE_CONTROL_NOTIFY),
197 .expected = 0,
198 },
199 {
200 .offset = 1,
201 .mask = (PIPE_CONTROL_GLOBAL_GTT_IVB |
202 PIPE_CONTROL_STORE_DATA_INDEX),
203 .expected = 0,
204 .condition_offset = 1,
205 .condition_mask = PIPE_CONTROL_POST_SYNC_OP_MASK,
206 }}, ),
207 };
208
209 static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = {
210 CMD( MI_SET_PREDICATE, SMI, F, 1, S ),
211 CMD( MI_RS_CONTROL, SMI, F, 1, S ),
212 CMD( MI_URB_ATOMIC_ALLOC, SMI, F, 1, S ),
213 CMD( MI_RS_CONTEXT, SMI, F, 1, S ),
214 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, M ),
215 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ),
216 CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, R ),
217 CMD( MI_RS_STORE_DATA_IMM, SMI, !F, 0xFF, S ),
218 CMD( MI_LOAD_URB_MEM, SMI, !F, 0xFF, S ),
219 CMD( MI_STORE_URB_MEM, SMI, !F, 0xFF, S ),
220 CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_VS, S3D, !F, 0x7FF, S ),
221 CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_PS, S3D, !F, 0x7FF, S ),
222
223 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS, S3D, !F, 0x1FF, S ),
224 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS, S3D, !F, 0x1FF, S ),
225 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS, S3D, !F, 0x1FF, S ),
226 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS, S3D, !F, 0x1FF, S ),
227 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS, S3D, !F, 0x1FF, S ),
228 };
229
230 static const struct drm_i915_cmd_descriptor video_cmds[] = {
231 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
232 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B,
233 .bits = {{
234 .offset = 0,
235 .mask = MI_GLOBAL_GTT,
236 .expected = 0,
237 }}, ),
238 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
239 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
240 .bits = {{
241 .offset = 0,
242 .mask = MI_FLUSH_DW_NOTIFY,
243 .expected = 0,
244 },
245 {
246 .offset = 1,
247 .mask = MI_FLUSH_DW_USE_GTT,
248 .expected = 0,
249 .condition_offset = 0,
250 .condition_mask = MI_FLUSH_DW_OP_MASK,
251 },
252 {
253 .offset = 0,
254 .mask = MI_FLUSH_DW_STORE_INDEX,
255 .expected = 0,
256 .condition_offset = 0,
257 .condition_mask = MI_FLUSH_DW_OP_MASK,
258 }}, ),
259 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,
260 .bits = {{
261 .offset = 0,
262 .mask = MI_GLOBAL_GTT,
263 .expected = 0,
264 }}, ),
265 /*
266 * MFX_WAIT doesn't fit the way we handle length for most commands.
267 * It has a length field but it uses a non-standard length bias.
268 * It is always 1 dword though, so just treat it as fixed length.
269 */
270 CMD( MFX_WAIT, SMFX, F, 1, S ),
271 };
272
273 static const struct drm_i915_cmd_descriptor vecs_cmds[] = {
274 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
275 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B,
276 .bits = {{
277 .offset = 0,
278 .mask = MI_GLOBAL_GTT,
279 .expected = 0,
280 }}, ),
281 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
282 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
283 .bits = {{
284 .offset = 0,
285 .mask = MI_FLUSH_DW_NOTIFY,
286 .expected = 0,
287 },
288 {
289 .offset = 1,
290 .mask = MI_FLUSH_DW_USE_GTT,
291 .expected = 0,
292 .condition_offset = 0,
293 .condition_mask = MI_FLUSH_DW_OP_MASK,
294 },
295 {
296 .offset = 0,
297 .mask = MI_FLUSH_DW_STORE_INDEX,
298 .expected = 0,
299 .condition_offset = 0,
300 .condition_mask = MI_FLUSH_DW_OP_MASK,
301 }}, ),
302 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,
303 .bits = {{
304 .offset = 0,
305 .mask = MI_GLOBAL_GTT,
306 .expected = 0,
307 }}, ),
308 };
309
310 static const struct drm_i915_cmd_descriptor blt_cmds[] = {
311 CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ),
312 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, B,
313 .bits = {{
314 .offset = 0,
315 .mask = MI_GLOBAL_GTT,
316 .expected = 0,
317 }}, ),
318 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
319 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
320 .bits = {{
321 .offset = 0,
322 .mask = MI_FLUSH_DW_NOTIFY,
323 .expected = 0,
324 },
325 {
326 .offset = 1,
327 .mask = MI_FLUSH_DW_USE_GTT,
328 .expected = 0,
329 .condition_offset = 0,
330 .condition_mask = MI_FLUSH_DW_OP_MASK,
331 },
332 {
333 .offset = 0,
334 .mask = MI_FLUSH_DW_STORE_INDEX,
335 .expected = 0,
336 .condition_offset = 0,
337 .condition_mask = MI_FLUSH_DW_OP_MASK,
338 }}, ),
339 CMD( COLOR_BLT, S2D, !F, 0x3F, S ),
340 CMD( SRC_COPY_BLT, S2D, !F, 0x3F, S ),
341 };
342
343 static const struct drm_i915_cmd_descriptor hsw_blt_cmds[] = {
344 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, M ),
345 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ),
346 };
347
348 #undef CMD
349 #undef SMI
350 #undef S3D
351 #undef S2D
352 #undef SMFX
353 #undef F
354 #undef S
355 #undef R
356 #undef W
357 #undef B
358 #undef M
359
360 static const struct drm_i915_cmd_table gen7_render_cmds[] = {
361 { common_cmds, ARRAY_SIZE(common_cmds) },
362 { render_cmds, ARRAY_SIZE(render_cmds) },
363 };
364
365 static const struct drm_i915_cmd_table hsw_render_ring_cmds[] = {
366 { common_cmds, ARRAY_SIZE(common_cmds) },
367 { render_cmds, ARRAY_SIZE(render_cmds) },
368 { hsw_render_cmds, ARRAY_SIZE(hsw_render_cmds) },
369 };
370
371 static const struct drm_i915_cmd_table gen7_video_cmds[] = {
372 { common_cmds, ARRAY_SIZE(common_cmds) },
373 { video_cmds, ARRAY_SIZE(video_cmds) },
374 };
375
376 static const struct drm_i915_cmd_table hsw_vebox_cmds[] = {
377 { common_cmds, ARRAY_SIZE(common_cmds) },
378 { vecs_cmds, ARRAY_SIZE(vecs_cmds) },
379 };
380
381 static const struct drm_i915_cmd_table gen7_blt_cmds[] = {
382 { common_cmds, ARRAY_SIZE(common_cmds) },
383 { blt_cmds, ARRAY_SIZE(blt_cmds) },
384 };
385
386 static const struct drm_i915_cmd_table hsw_blt_ring_cmds[] = {
387 { common_cmds, ARRAY_SIZE(common_cmds) },
388 { blt_cmds, ARRAY_SIZE(blt_cmds) },
389 { hsw_blt_cmds, ARRAY_SIZE(hsw_blt_cmds) },
390 };
391
392 /*
393 * Register whitelists, sorted by increasing register offset.
394 *
395 * Some registers that userspace accesses are 64 bits. The register
396 * access commands only allow 32-bit accesses. Hence, we have to include
397 * entries for both halves of the 64-bit registers.
398 */
399
400 /* Convenience macro for adding 64-bit registers */
401 #define REG64(addr) (addr), (addr + sizeof(u32))
402
403 static const u32 gen7_render_regs[] = {
404 REG64(HS_INVOCATION_COUNT),
405 REG64(DS_INVOCATION_COUNT),
406 REG64(IA_VERTICES_COUNT),
407 REG64(IA_PRIMITIVES_COUNT),
408 REG64(VS_INVOCATION_COUNT),
409 REG64(GS_INVOCATION_COUNT),
410 REG64(GS_PRIMITIVES_COUNT),
411 REG64(CL_INVOCATION_COUNT),
412 REG64(CL_PRIMITIVES_COUNT),
413 REG64(PS_INVOCATION_COUNT),
414 REG64(PS_DEPTH_COUNT),
415 OACONTROL, /* Only allowed for LRI and SRM. See below. */
416 REG64(MI_PREDICATE_SRC0),
417 REG64(MI_PREDICATE_SRC1),
418 GEN7_3DPRIM_END_OFFSET,
419 GEN7_3DPRIM_START_VERTEX,
420 GEN7_3DPRIM_VERTEX_COUNT,
421 GEN7_3DPRIM_INSTANCE_COUNT,
422 GEN7_3DPRIM_START_INSTANCE,
423 GEN7_3DPRIM_BASE_VERTEX,
424 REG64(GEN7_SO_NUM_PRIMS_WRITTEN(0)),
425 REG64(GEN7_SO_NUM_PRIMS_WRITTEN(1)),
426 REG64(GEN7_SO_NUM_PRIMS_WRITTEN(2)),
427 REG64(GEN7_SO_NUM_PRIMS_WRITTEN(3)),
428 REG64(GEN7_SO_PRIM_STORAGE_NEEDED(0)),
429 REG64(GEN7_SO_PRIM_STORAGE_NEEDED(1)),
430 REG64(GEN7_SO_PRIM_STORAGE_NEEDED(2)),
431 REG64(GEN7_SO_PRIM_STORAGE_NEEDED(3)),
432 GEN7_SO_WRITE_OFFSET(0),
433 GEN7_SO_WRITE_OFFSET(1),
434 GEN7_SO_WRITE_OFFSET(2),
435 GEN7_SO_WRITE_OFFSET(3),
436 GEN7_L3SQCREG1,
437 GEN7_L3CNTLREG2,
438 GEN7_L3CNTLREG3,
439 };
440
441 static const u32 gen7_blt_regs[] = {
442 BCS_SWCTRL,
443 };
444
445 static const u32 ivb_master_regs[] = {
446 FORCEWAKE_MT,
447 DERRMR,
448 GEN7_PIPE_DE_LOAD_SL(PIPE_A),
449 GEN7_PIPE_DE_LOAD_SL(PIPE_B),
450 GEN7_PIPE_DE_LOAD_SL(PIPE_C),
451 };
452
453 static const u32 hsw_master_regs[] = {
454 FORCEWAKE_MT,
455 DERRMR,
456 };
457
458 #undef REG64
459
460 static u32 gen7_render_get_cmd_length_mask(u32 cmd_header)
461 {
462 u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT;
463 u32 subclient =
464 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT;
465
466 if (client == INSTR_MI_CLIENT)
467 return 0x3F;
468 else if (client == INSTR_RC_CLIENT) {
469 if (subclient == INSTR_MEDIA_SUBCLIENT)
470 return 0xFFFF;
471 else
472 return 0xFF;
473 }
474
475 DRM_DEBUG_DRIVER("CMD: Abnormal rcs cmd length! 0x%08X\n", cmd_header);
476 return 0;
477 }
478
479 static u32 gen7_bsd_get_cmd_length_mask(u32 cmd_header)
480 {
481 u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT;
482 u32 subclient =
483 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT;
484
485 if (client == INSTR_MI_CLIENT)
486 return 0x3F;
487 else if (client == INSTR_RC_CLIENT) {
488 if (subclient == INSTR_MEDIA_SUBCLIENT)
489 return 0xFFF;
490 else
491 return 0xFF;
492 }
493
494 DRM_DEBUG_DRIVER("CMD: Abnormal bsd cmd length! 0x%08X\n", cmd_header);
495 return 0;
496 }
497
498 static u32 gen7_blt_get_cmd_length_mask(u32 cmd_header)
499 {
500 u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT;
501
502 if (client == INSTR_MI_CLIENT)
503 return 0x3F;
504 else if (client == INSTR_BC_CLIENT)
505 return 0xFF;
506
507 DRM_DEBUG_DRIVER("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header);
508 return 0;
509 }
510
511 static bool validate_cmds_sorted(struct intel_engine_cs *ring,
512 const struct drm_i915_cmd_table *cmd_tables,
513 int cmd_table_count)
514 {
515 int i;
516 bool ret = true;
517
518 if (!cmd_tables || cmd_table_count == 0)
519 return true;
520
521 for (i = 0; i < cmd_table_count; i++) {
522 const struct drm_i915_cmd_table *table = &cmd_tables[i];
523 u32 previous = 0;
524 int j;
525
526 for (j = 0; j < table->count; j++) {
527 const struct drm_i915_cmd_descriptor *desc =
528 &table->table[i];
529 u32 curr = desc->cmd.value & desc->cmd.mask;
530
531 if (curr < previous) {
532 DRM_ERROR("CMD: table not sorted ring=%d table=%d entry=%d cmd=0x%08X prev=0x%08X\n",
533 ring->id, i, j, curr, previous);
534 ret = false;
535 }
536
537 previous = curr;
538 }
539 }
540
541 return ret;
542 }
543
544 static bool check_sorted(int ring_id, const u32 *reg_table, int reg_count)
545 {
546 int i;
547 u32 previous = 0;
548 bool ret = true;
549
550 for (i = 0; i < reg_count; i++) {
551 u32 curr = reg_table[i];
552
553 if (curr < previous) {
554 DRM_ERROR("CMD: table not sorted ring=%d entry=%d reg=0x%08X prev=0x%08X\n",
555 ring_id, i, curr, previous);
556 ret = false;
557 }
558
559 previous = curr;
560 }
561
562 return ret;
563 }
564
565 static bool validate_regs_sorted(struct intel_engine_cs *ring)
566 {
567 return check_sorted(ring->id, ring->reg_table, ring->reg_count) &&
568 check_sorted(ring->id, ring->master_reg_table,
569 ring->master_reg_count);
570 }
571
572 struct cmd_node {
573 const struct drm_i915_cmd_descriptor *desc;
574 struct hlist_node node;
575 };
576
577 /*
578 * Different command ranges have different numbers of bits for the opcode. For
579 * example, MI commands use bits 31:23 while 3D commands use bits 31:16. The
580 * problem is that, for example, MI commands use bits 22:16 for other fields
581 * such as GGTT vs PPGTT bits. If we include those bits in the mask then when
582 * we mask a command from a batch it could hash to the wrong bucket due to
583 * non-opcode bits being set. But if we don't include those bits, some 3D
584 * commands may hash to the same bucket due to not including opcode bits that
585 * make the command unique. For now, we will risk hashing to the same bucket.
586 *
587 * If we attempt to generate a perfect hash, we should be able to look at bits
588 * 31:29 of a command from a batch buffer and use the full mask for that
589 * client. The existing INSTR_CLIENT_MASK/SHIFT defines can be used for this.
590 */
591 #define CMD_HASH_MASK STD_MI_OPCODE_MASK
592
593 static int init_hash_table(struct intel_engine_cs *ring,
594 const struct drm_i915_cmd_table *cmd_tables,
595 int cmd_table_count)
596 {
597 int i, j;
598
599 hash_init(ring->cmd_hash);
600
601 for (i = 0; i < cmd_table_count; i++) {
602 const struct drm_i915_cmd_table *table = &cmd_tables[i];
603
604 for (j = 0; j < table->count; j++) {
605 const struct drm_i915_cmd_descriptor *desc =
606 &table->table[j];
607 struct cmd_node *desc_node =
608 kmalloc(sizeof(*desc_node), GFP_KERNEL);
609
610 if (!desc_node)
611 return -ENOMEM;
612
613 desc_node->desc = desc;
614 hash_add(ring->cmd_hash, &desc_node->node,
615 desc->cmd.value & CMD_HASH_MASK);
616 }
617 }
618
619 return 0;
620 }
621
622 static void fini_hash_table(struct intel_engine_cs *ring)
623 {
624 struct hlist_node *tmp;
625 struct cmd_node *desc_node;
626 int i;
627
628 hash_for_each_safe(ring->cmd_hash, i, tmp, desc_node, node) {
629 hash_del(&desc_node->node);
630 kfree(desc_node);
631 }
632 }
633
634 /**
635 * i915_cmd_parser_init_ring() - set cmd parser related fields for a ringbuffer
636 * @ring: the ringbuffer to initialize
637 *
638 * Optionally initializes fields related to batch buffer command parsing in the
639 * struct intel_engine_cs based on whether the platform requires software
640 * command parsing.
641 *
642 * Return: non-zero if initialization fails
643 */
644 int i915_cmd_parser_init_ring(struct intel_engine_cs *ring)
645 {
646 const struct drm_i915_cmd_table *cmd_tables;
647 int cmd_table_count;
648 int ret;
649
650 if (!IS_GEN7(ring->dev))
651 return 0;
652
653 switch (ring->id) {
654 case RCS:
655 if (IS_HASWELL(ring->dev)) {
656 cmd_tables = hsw_render_ring_cmds;
657 cmd_table_count =
658 ARRAY_SIZE(hsw_render_ring_cmds);
659 } else {
660 cmd_tables = gen7_render_cmds;
661 cmd_table_count = ARRAY_SIZE(gen7_render_cmds);
662 }
663
664 ring->reg_table = gen7_render_regs;
665 ring->reg_count = ARRAY_SIZE(gen7_render_regs);
666
667 if (IS_HASWELL(ring->dev)) {
668 ring->master_reg_table = hsw_master_regs;
669 ring->master_reg_count = ARRAY_SIZE(hsw_master_regs);
670 } else {
671 ring->master_reg_table = ivb_master_regs;
672 ring->master_reg_count = ARRAY_SIZE(ivb_master_regs);
673 }
674
675 ring->get_cmd_length_mask = gen7_render_get_cmd_length_mask;
676 break;
677 case VCS:
678 cmd_tables = gen7_video_cmds;
679 cmd_table_count = ARRAY_SIZE(gen7_video_cmds);
680 ring->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
681 break;
682 case BCS:
683 if (IS_HASWELL(ring->dev)) {
684 cmd_tables = hsw_blt_ring_cmds;
685 cmd_table_count = ARRAY_SIZE(hsw_blt_ring_cmds);
686 } else {
687 cmd_tables = gen7_blt_cmds;
688 cmd_table_count = ARRAY_SIZE(gen7_blt_cmds);
689 }
690
691 ring->reg_table = gen7_blt_regs;
692 ring->reg_count = ARRAY_SIZE(gen7_blt_regs);
693
694 if (IS_HASWELL(ring->dev)) {
695 ring->master_reg_table = hsw_master_regs;
696 ring->master_reg_count = ARRAY_SIZE(hsw_master_regs);
697 } else {
698 ring->master_reg_table = ivb_master_regs;
699 ring->master_reg_count = ARRAY_SIZE(ivb_master_regs);
700 }
701
702 ring->get_cmd_length_mask = gen7_blt_get_cmd_length_mask;
703 break;
704 case VECS:
705 cmd_tables = hsw_vebox_cmds;
706 cmd_table_count = ARRAY_SIZE(hsw_vebox_cmds);
707 /* VECS can use the same length_mask function as VCS */
708 ring->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
709 break;
710 default:
711 DRM_ERROR("CMD: cmd_parser_init with unknown ring: %d\n",
712 ring->id);
713 BUG();
714 }
715
716 BUG_ON(!validate_cmds_sorted(ring, cmd_tables, cmd_table_count));
717 BUG_ON(!validate_regs_sorted(ring));
718
719 WARN_ON(!hash_empty(ring->cmd_hash));
720
721 ret = init_hash_table(ring, cmd_tables, cmd_table_count);
722 if (ret) {
723 DRM_ERROR("CMD: cmd_parser_init failed!\n");
724 fini_hash_table(ring);
725 return ret;
726 }
727
728 ring->needs_cmd_parser = true;
729
730 return 0;
731 }
732
733 /**
734 * i915_cmd_parser_fini_ring() - clean up cmd parser related fields
735 * @ring: the ringbuffer to clean up
736 *
737 * Releases any resources related to command parsing that may have been
738 * initialized for the specified ring.
739 */
740 void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring)
741 {
742 if (!ring->needs_cmd_parser)
743 return;
744
745 fini_hash_table(ring);
746 }
747
748 static const struct drm_i915_cmd_descriptor*
749 find_cmd_in_table(struct intel_engine_cs *ring,
750 u32 cmd_header)
751 {
752 struct cmd_node *desc_node;
753
754 hash_for_each_possible(ring->cmd_hash, desc_node, node,
755 cmd_header & CMD_HASH_MASK) {
756 const struct drm_i915_cmd_descriptor *desc = desc_node->desc;
757 u32 masked_cmd = desc->cmd.mask & cmd_header;
758 u32 masked_value = desc->cmd.value & desc->cmd.mask;
759
760 if (masked_cmd == masked_value)
761 return desc;
762 }
763
764 return NULL;
765 }
766
767 /*
768 * Returns a pointer to a descriptor for the command specified by cmd_header.
769 *
770 * The caller must supply space for a default descriptor via the default_desc
771 * parameter. If no descriptor for the specified command exists in the ring's
772 * command parser tables, this function fills in default_desc based on the
773 * ring's default length encoding and returns default_desc.
774 */
775 static const struct drm_i915_cmd_descriptor*
776 find_cmd(struct intel_engine_cs *ring,
777 u32 cmd_header,
778 struct drm_i915_cmd_descriptor *default_desc)
779 {
780 const struct drm_i915_cmd_descriptor *desc;
781 u32 mask;
782
783 desc = find_cmd_in_table(ring, cmd_header);
784 if (desc)
785 return desc;
786
787 mask = ring->get_cmd_length_mask(cmd_header);
788 if (!mask)
789 return NULL;
790
791 BUG_ON(!default_desc);
792 default_desc->flags = CMD_DESC_SKIP;
793 default_desc->length.mask = mask;
794
795 return default_desc;
796 }
797
798 static bool valid_reg(const u32 *table, int count, u32 addr)
799 {
800 if (table && count != 0) {
801 int i;
802
803 for (i = 0; i < count; i++) {
804 if (table[i] == addr)
805 return true;
806 }
807 }
808
809 return false;
810 }
811
812 static u32 *vmap_batch(struct drm_i915_gem_object *obj)
813 {
814 int i;
815 void *addr = NULL;
816 struct sg_page_iter sg_iter;
817 struct page **pages;
818
819 pages = drm_malloc_ab(obj->base.size >> PAGE_SHIFT, sizeof(*pages));
820 if (pages == NULL) {
821 DRM_DEBUG_DRIVER("Failed to get space for pages\n");
822 goto finish;
823 }
824
825 i = 0;
826 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
827 pages[i] = sg_page_iter_page(&sg_iter);
828 i++;
829 }
830
831 addr = vmap(pages, i, 0, PAGE_KERNEL);
832 if (addr == NULL) {
833 DRM_DEBUG_DRIVER("Failed to vmap pages\n");
834 goto finish;
835 }
836
837 finish:
838 if (pages)
839 drm_free_large(pages);
840 return (u32*)addr;
841 }
842
843 /**
844 * i915_needs_cmd_parser() - should a given ring use software command parsing?
845 * @ring: the ring in question
846 *
847 * Only certain platforms require software batch buffer command parsing, and
848 * only when enabled via module parameter.
849 *
850 * Return: true if the ring requires software command parsing
851 */
852 bool i915_needs_cmd_parser(struct intel_engine_cs *ring)
853 {
854 if (!ring->needs_cmd_parser)
855 return false;
856
857 if (!USES_PPGTT(ring->dev))
858 return false;
859
860 return (i915.enable_cmd_parser == 1);
861 }
862
863 static bool check_cmd(const struct intel_engine_cs *ring,
864 const struct drm_i915_cmd_descriptor *desc,
865 const u32 *cmd,
866 const bool is_master,
867 bool *oacontrol_set)
868 {
869 if (desc->flags & CMD_DESC_REJECT) {
870 DRM_DEBUG_DRIVER("CMD: Rejected command: 0x%08X\n", *cmd);
871 return false;
872 }
873
874 if ((desc->flags & CMD_DESC_MASTER) && !is_master) {
875 DRM_DEBUG_DRIVER("CMD: Rejected master-only command: 0x%08X\n",
876 *cmd);
877 return false;
878 }
879
880 if (desc->flags & CMD_DESC_REGISTER) {
881 u32 reg_addr = cmd[desc->reg.offset] & desc->reg.mask;
882
883 /*
884 * OACONTROL requires some special handling for writes. We
885 * want to make sure that any batch which enables OA also
886 * disables it before the end of the batch. The goal is to
887 * prevent one process from snooping on the perf data from
888 * another process. To do that, we need to check the value
889 * that will be written to the register. Hence, limit
890 * OACONTROL writes to only MI_LOAD_REGISTER_IMM commands.
891 */
892 if (reg_addr == OACONTROL) {
893 if (desc->cmd.value == MI_LOAD_REGISTER_MEM) {
894 DRM_DEBUG_DRIVER("CMD: Rejected LRM to OACONTROL\n");
895 return false;
896 }
897
898 if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1))
899 *oacontrol_set = (cmd[2] != 0);
900 }
901
902 if (!valid_reg(ring->reg_table,
903 ring->reg_count, reg_addr)) {
904 if (!is_master ||
905 !valid_reg(ring->master_reg_table,
906 ring->master_reg_count,
907 reg_addr)) {
908 DRM_DEBUG_DRIVER("CMD: Rejected register 0x%08X in command: 0x%08X (ring=%d)\n",
909 reg_addr,
910 *cmd,
911 ring->id);
912 return false;
913 }
914 }
915 }
916
917 if (desc->flags & CMD_DESC_BITMASK) {
918 int i;
919
920 for (i = 0; i < MAX_CMD_DESC_BITMASKS; i++) {
921 u32 dword;
922
923 if (desc->bits[i].mask == 0)
924 break;
925
926 if (desc->bits[i].condition_mask != 0) {
927 u32 offset =
928 desc->bits[i].condition_offset;
929 u32 condition = cmd[offset] &
930 desc->bits[i].condition_mask;
931
932 if (condition == 0)
933 continue;
934 }
935
936 dword = cmd[desc->bits[i].offset] &
937 desc->bits[i].mask;
938
939 if (dword != desc->bits[i].expected) {
940 DRM_DEBUG_DRIVER("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (ring=%d)\n",
941 *cmd,
942 desc->bits[i].mask,
943 desc->bits[i].expected,
944 dword, ring->id);
945 return false;
946 }
947 }
948 }
949
950 return true;
951 }
952
953 #define LENGTH_BIAS 2
954
955 /**
956 * i915_parse_cmds() - parse a submitted batch buffer for privilege violations
957 * @ring: the ring on which the batch is to execute
958 * @batch_obj: the batch buffer in question
959 * @batch_start_offset: byte offset in the batch at which execution starts
960 * @is_master: is the submitting process the drm master?
961 *
962 * Parses the specified batch buffer looking for privilege violations as
963 * described in the overview.
964 *
965 * Return: non-zero if the parser finds violations or otherwise fails; -EACCES
966 * if the batch appears legal but should use hardware parsing
967 */
968 int i915_parse_cmds(struct intel_engine_cs *ring,
969 struct drm_i915_gem_object *batch_obj,
970 u32 batch_start_offset,
971 bool is_master)
972 {
973 int ret = 0;
974 u32 *cmd, *batch_base, *batch_end;
975 struct drm_i915_cmd_descriptor default_desc = { 0 };
976 int needs_clflush = 0;
977 bool oacontrol_set = false; /* OACONTROL tracking. See check_cmd() */
978
979 ret = i915_gem_obj_prepare_shmem_read(batch_obj, &needs_clflush);
980 if (ret) {
981 DRM_DEBUG_DRIVER("CMD: failed to prep read\n");
982 return ret;
983 }
984
985 batch_base = vmap_batch(batch_obj);
986 if (!batch_base) {
987 DRM_DEBUG_DRIVER("CMD: Failed to vmap batch\n");
988 i915_gem_object_unpin_pages(batch_obj);
989 return -ENOMEM;
990 }
991
992 if (needs_clflush)
993 drm_clflush_virt_range((char *)batch_base, batch_obj->base.size);
994
995 cmd = batch_base + (batch_start_offset / sizeof(*cmd));
996 batch_end = cmd + (batch_obj->base.size / sizeof(*batch_end));
997
998 while (cmd < batch_end) {
999 const struct drm_i915_cmd_descriptor *desc;
1000 u32 length;
1001
1002 if (*cmd == MI_BATCH_BUFFER_END)
1003 break;
1004
1005 desc = find_cmd(ring, *cmd, &default_desc);
1006 if (!desc) {
1007 DRM_DEBUG_DRIVER("CMD: Unrecognized command: 0x%08X\n",
1008 *cmd);
1009 ret = -EINVAL;
1010 break;
1011 }
1012
1013 /*
1014 * If the batch buffer contains a chained batch, return an
1015 * error that tells the caller to abort and dispatch the
1016 * workload as a non-secure batch.
1017 */
1018 if (desc->cmd.value == MI_BATCH_BUFFER_START) {
1019 ret = -EACCES;
1020 break;
1021 }
1022
1023 if (desc->flags & CMD_DESC_FIXED)
1024 length = desc->length.fixed;
1025 else
1026 length = ((*cmd & desc->length.mask) + LENGTH_BIAS);
1027
1028 if ((batch_end - cmd) < length) {
1029 DRM_DEBUG_DRIVER("CMD: Command length exceeds batch length: 0x%08X length=%u batchlen=%td\n",
1030 *cmd,
1031 length,
1032 batch_end - cmd);
1033 ret = -EINVAL;
1034 break;
1035 }
1036
1037 if (!check_cmd(ring, desc, cmd, is_master, &oacontrol_set)) {
1038 ret = -EINVAL;
1039 break;
1040 }
1041
1042 cmd += length;
1043 }
1044
1045 if (oacontrol_set) {
1046 DRM_DEBUG_DRIVER("CMD: batch set OACONTROL but did not clear it\n");
1047 ret = -EINVAL;
1048 }
1049
1050 if (cmd >= batch_end) {
1051 DRM_DEBUG_DRIVER("CMD: Got to the end of the buffer w/o a BBE cmd!\n");
1052 ret = -EINVAL;
1053 }
1054
1055 vunmap(batch_base);
1056
1057 i915_gem_object_unpin_pages(batch_obj);
1058
1059 return ret;
1060 }
1061
1062 /**
1063 * i915_cmd_parser_get_version() - get the cmd parser version number
1064 *
1065 * The cmd parser maintains a simple increasing integer version number suitable
1066 * for passing to userspace clients to determine what operations are permitted.
1067 *
1068 * Return: the current version number of the cmd parser
1069 */
1070 int i915_cmd_parser_get_version(void)
1071 {
1072 /*
1073 * Command parser version history
1074 *
1075 * 1. Initial version. Checks batches and reports violations, but leaves
1076 * hardware parsing enabled (so does not allow new use cases).
1077 * 2. Allow access to the MI_PREDICATE_SRC0 and
1078 * MI_PREDICATE_SRC1 registers.
1079 */
1080 return 2;
1081 }
Linux kernel - Deliverables
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