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drm/i915: Add MI_SET_APPID cmd to cmd parser tables
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_cmd_parser.c
1 /*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Brad Volkin <bradley.d.volkin@intel.com>
25 *
26 */
27
28 #include "i915_drv.h"
29
30 /**
31 * DOC: batch buffer command parser
32 *
33 * Motivation:
34 * Certain OpenGL features (e.g. transform feedback, performance monitoring)
35 * require userspace code to submit batches containing commands such as
36 * MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some
37 * generations of the hardware will noop these commands in "unsecure" batches
38 * (which includes all userspace batches submitted via i915) even though the
39 * commands may be safe and represent the intended programming model of the
40 * device.
41 *
42 * The software command parser is similar in operation to the command parsing
43 * done in hardware for unsecure batches. However, the software parser allows
44 * some operations that would be noop'd by hardware, if the parser determines
45 * the operation is safe, and submits the batch as "secure" to prevent hardware
46 * parsing.
47 *
48 * Threats:
49 * At a high level, the hardware (and software) checks attempt to prevent
50 * granting userspace undue privileges. There are three categories of privilege.
51 *
52 * First, commands which are explicitly defined as privileged or which should
53 * only be used by the kernel driver. The parser generally rejects such
54 * commands, though it may allow some from the drm master process.
55 *
56 * Second, commands which access registers. To support correct/enhanced
57 * userspace functionality, particularly certain OpenGL extensions, the parser
58 * provides a whitelist of registers which userspace may safely access (for both
59 * normal and drm master processes).
60 *
61 * Third, commands which access privileged memory (i.e. GGTT, HWS page, etc).
62 * The parser always rejects such commands.
63 *
64 * The majority of the problematic commands fall in the MI_* range, with only a
65 * few specific commands on each ring (e.g. PIPE_CONTROL and MI_FLUSH_DW).
66 *
67 * Implementation:
68 * Each ring maintains tables of commands and registers which the parser uses in
69 * scanning batch buffers submitted to that ring.
70 *
71 * Since the set of commands that the parser must check for is significantly
72 * smaller than the number of commands supported, the parser tables contain only
73 * those commands required by the parser. This generally works because command
74 * opcode ranges have standard command length encodings. So for commands that
75 * the parser does not need to check, it can easily skip them. This is
76 * implemented via a per-ring length decoding vfunc.
77 *
78 * Unfortunately, there are a number of commands that do not follow the standard
79 * length encoding for their opcode range, primarily amongst the MI_* commands.
80 * To handle this, the parser provides a way to define explicit "skip" entries
81 * in the per-ring command tables.
82 *
83 * Other command table entries map fairly directly to high level categories
84 * mentioned above: rejected, master-only, register whitelist. The parser
85 * implements a number of checks, including the privileged memory checks, via a
86 * general bitmasking mechanism.
87 */
88
89 #define STD_MI_OPCODE_MASK 0xFF800000
90 #define STD_3D_OPCODE_MASK 0xFFFF0000
91 #define STD_2D_OPCODE_MASK 0xFFC00000
92 #define STD_MFX_OPCODE_MASK 0xFFFF0000
93
94 #define CMD(op, opm, f, lm, fl, ...) \
95 { \
96 .flags = (fl) | ((f) ? CMD_DESC_FIXED : 0), \
97 .cmd = { (op), (opm) }, \
98 .length = { (lm) }, \
99 __VA_ARGS__ \
100 }
101
102 /* Convenience macros to compress the tables */
103 #define SMI STD_MI_OPCODE_MASK
104 #define S3D STD_3D_OPCODE_MASK
105 #define S2D STD_2D_OPCODE_MASK
106 #define SMFX STD_MFX_OPCODE_MASK
107 #define F true
108 #define S CMD_DESC_SKIP
109 #define R CMD_DESC_REJECT
110 #define W CMD_DESC_REGISTER
111 #define B CMD_DESC_BITMASK
112 #define M CMD_DESC_MASTER
113
114 /* Command Mask Fixed Len Action
115 ---------------------------------------------------------- */
116 static const struct drm_i915_cmd_descriptor common_cmds[] = {
117 CMD( MI_NOOP, SMI, F, 1, S ),
118 CMD( MI_USER_INTERRUPT, SMI, F, 1, R ),
119 CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, M ),
120 CMD( MI_ARB_CHECK, SMI, F, 1, S ),
121 CMD( MI_REPORT_HEAD, SMI, F, 1, S ),
122 CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ),
123 CMD( MI_SEMAPHORE_MBOX, SMI, !F, 0xFF, R ),
124 CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, R ),
125 CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W,
126 .reg = { .offset = 1, .mask = 0x007FFFFC } ),
127 CMD( MI_STORE_REGISTER_MEM(1), SMI, !F, 0xFF, W | B,
128 .reg = { .offset = 1, .mask = 0x007FFFFC },
129 .bits = {{
130 .offset = 0,
131 .mask = MI_GLOBAL_GTT,
132 .expected = 0,
133 }}, ),
134 CMD( MI_LOAD_REGISTER_MEM, SMI, !F, 0xFF, W | B,
135 .reg = { .offset = 1, .mask = 0x007FFFFC },
136 .bits = {{
137 .offset = 0,
138 .mask = MI_GLOBAL_GTT,
139 .expected = 0,
140 }}, ),
141 /*
142 * MI_BATCH_BUFFER_START requires some special handling. It's not
143 * really a 'skip' action but it doesn't seem like it's worth adding
144 * a new action. See i915_parse_cmds().
145 */
146 CMD( MI_BATCH_BUFFER_START, SMI, !F, 0xFF, S ),
147 };
148
149 static const struct drm_i915_cmd_descriptor render_cmds[] = {
150 CMD( MI_FLUSH, SMI, F, 1, S ),
151 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
152 CMD( MI_PREDICATE, SMI, F, 1, S ),
153 CMD( MI_TOPOLOGY_FILTER, SMI, F, 1, S ),
154 CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ),
155 CMD( MI_SET_APPID, SMI, F, 1, S ),
156 CMD( MI_SET_CONTEXT, SMI, !F, 0xFF, R ),
157 CMD( MI_URB_CLEAR, SMI, !F, 0xFF, S ),
158 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3F, B,
159 .bits = {{
160 .offset = 0,
161 .mask = MI_GLOBAL_GTT,
162 .expected = 0,
163 }}, ),
164 CMD( MI_UPDATE_GTT, SMI, !F, 0xFF, R ),
165 CMD( MI_CLFLUSH, SMI, !F, 0x3FF, B,
166 .bits = {{
167 .offset = 0,
168 .mask = MI_GLOBAL_GTT,
169 .expected = 0,
170 }}, ),
171 CMD( MI_REPORT_PERF_COUNT, SMI, !F, 0x3F, B,
172 .bits = {{
173 .offset = 1,
174 .mask = MI_REPORT_PERF_COUNT_GGTT,
175 .expected = 0,
176 }}, ),
177 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,
178 .bits = {{
179 .offset = 0,
180 .mask = MI_GLOBAL_GTT,
181 .expected = 0,
182 }}, ),
183 CMD( GFX_OP_3DSTATE_VF_STATISTICS, S3D, F, 1, S ),
184 CMD( PIPELINE_SELECT, S3D, F, 1, S ),
185 CMD( MEDIA_VFE_STATE, S3D, !F, 0xFFFF, B,
186 .bits = {{
187 .offset = 2,
188 .mask = MEDIA_VFE_STATE_MMIO_ACCESS_MASK,
189 .expected = 0,
190 }}, ),
191 CMD( GPGPU_OBJECT, S3D, !F, 0xFF, S ),
192 CMD( GPGPU_WALKER, S3D, !F, 0xFF, S ),
193 CMD( GFX_OP_3DSTATE_SO_DECL_LIST, S3D, !F, 0x1FF, S ),
194 CMD( GFX_OP_PIPE_CONTROL(5), S3D, !F, 0xFF, B,
195 .bits = {{
196 .offset = 1,
197 .mask = (PIPE_CONTROL_MMIO_WRITE | PIPE_CONTROL_NOTIFY),
198 .expected = 0,
199 },
200 {
201 .offset = 1,
202 .mask = (PIPE_CONTROL_GLOBAL_GTT_IVB |
203 PIPE_CONTROL_STORE_DATA_INDEX),
204 .expected = 0,
205 .condition_offset = 1,
206 .condition_mask = PIPE_CONTROL_POST_SYNC_OP_MASK,
207 }}, ),
208 };
209
210 static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = {
211 CMD( MI_SET_PREDICATE, SMI, F, 1, S ),
212 CMD( MI_RS_CONTROL, SMI, F, 1, S ),
213 CMD( MI_URB_ATOMIC_ALLOC, SMI, F, 1, S ),
214 CMD( MI_SET_APPID, SMI, F, 1, S ),
215 CMD( MI_RS_CONTEXT, SMI, F, 1, S ),
216 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, M ),
217 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ),
218 CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, R ),
219 CMD( MI_RS_STORE_DATA_IMM, SMI, !F, 0xFF, S ),
220 CMD( MI_LOAD_URB_MEM, SMI, !F, 0xFF, S ),
221 CMD( MI_STORE_URB_MEM, SMI, !F, 0xFF, S ),
222 CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_VS, S3D, !F, 0x7FF, S ),
223 CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_PS, S3D, !F, 0x7FF, S ),
224
225 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS, S3D, !F, 0x1FF, S ),
226 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS, S3D, !F, 0x1FF, S ),
227 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS, S3D, !F, 0x1FF, S ),
228 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS, S3D, !F, 0x1FF, S ),
229 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS, S3D, !F, 0x1FF, S ),
230 };
231
232 static const struct drm_i915_cmd_descriptor video_cmds[] = {
233 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
234 CMD( MI_SET_APPID, SMI, F, 1, S ),
235 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B,
236 .bits = {{
237 .offset = 0,
238 .mask = MI_GLOBAL_GTT,
239 .expected = 0,
240 }}, ),
241 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
242 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
243 .bits = {{
244 .offset = 0,
245 .mask = MI_FLUSH_DW_NOTIFY,
246 .expected = 0,
247 },
248 {
249 .offset = 1,
250 .mask = MI_FLUSH_DW_USE_GTT,
251 .expected = 0,
252 .condition_offset = 0,
253 .condition_mask = MI_FLUSH_DW_OP_MASK,
254 },
255 {
256 .offset = 0,
257 .mask = MI_FLUSH_DW_STORE_INDEX,
258 .expected = 0,
259 .condition_offset = 0,
260 .condition_mask = MI_FLUSH_DW_OP_MASK,
261 }}, ),
262 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,
263 .bits = {{
264 .offset = 0,
265 .mask = MI_GLOBAL_GTT,
266 .expected = 0,
267 }}, ),
268 /*
269 * MFX_WAIT doesn't fit the way we handle length for most commands.
270 * It has a length field but it uses a non-standard length bias.
271 * It is always 1 dword though, so just treat it as fixed length.
272 */
273 CMD( MFX_WAIT, SMFX, F, 1, S ),
274 };
275
276 static const struct drm_i915_cmd_descriptor vecs_cmds[] = {
277 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
278 CMD( MI_SET_APPID, SMI, F, 1, S ),
279 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B,
280 .bits = {{
281 .offset = 0,
282 .mask = MI_GLOBAL_GTT,
283 .expected = 0,
284 }}, ),
285 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
286 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
287 .bits = {{
288 .offset = 0,
289 .mask = MI_FLUSH_DW_NOTIFY,
290 .expected = 0,
291 },
292 {
293 .offset = 1,
294 .mask = MI_FLUSH_DW_USE_GTT,
295 .expected = 0,
296 .condition_offset = 0,
297 .condition_mask = MI_FLUSH_DW_OP_MASK,
298 },
299 {
300 .offset = 0,
301 .mask = MI_FLUSH_DW_STORE_INDEX,
302 .expected = 0,
303 .condition_offset = 0,
304 .condition_mask = MI_FLUSH_DW_OP_MASK,
305 }}, ),
306 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,
307 .bits = {{
308 .offset = 0,
309 .mask = MI_GLOBAL_GTT,
310 .expected = 0,
311 }}, ),
312 };
313
314 static const struct drm_i915_cmd_descriptor blt_cmds[] = {
315 CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ),
316 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, B,
317 .bits = {{
318 .offset = 0,
319 .mask = MI_GLOBAL_GTT,
320 .expected = 0,
321 }}, ),
322 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
323 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
324 .bits = {{
325 .offset = 0,
326 .mask = MI_FLUSH_DW_NOTIFY,
327 .expected = 0,
328 },
329 {
330 .offset = 1,
331 .mask = MI_FLUSH_DW_USE_GTT,
332 .expected = 0,
333 .condition_offset = 0,
334 .condition_mask = MI_FLUSH_DW_OP_MASK,
335 },
336 {
337 .offset = 0,
338 .mask = MI_FLUSH_DW_STORE_INDEX,
339 .expected = 0,
340 .condition_offset = 0,
341 .condition_mask = MI_FLUSH_DW_OP_MASK,
342 }}, ),
343 CMD( COLOR_BLT, S2D, !F, 0x3F, S ),
344 CMD( SRC_COPY_BLT, S2D, !F, 0x3F, S ),
345 };
346
347 static const struct drm_i915_cmd_descriptor hsw_blt_cmds[] = {
348 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, M ),
349 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ),
350 };
351
352 #undef CMD
353 #undef SMI
354 #undef S3D
355 #undef S2D
356 #undef SMFX
357 #undef F
358 #undef S
359 #undef R
360 #undef W
361 #undef B
362 #undef M
363
364 static const struct drm_i915_cmd_table gen7_render_cmds[] = {
365 { common_cmds, ARRAY_SIZE(common_cmds) },
366 { render_cmds, ARRAY_SIZE(render_cmds) },
367 };
368
369 static const struct drm_i915_cmd_table hsw_render_ring_cmds[] = {
370 { common_cmds, ARRAY_SIZE(common_cmds) },
371 { render_cmds, ARRAY_SIZE(render_cmds) },
372 { hsw_render_cmds, ARRAY_SIZE(hsw_render_cmds) },
373 };
374
375 static const struct drm_i915_cmd_table gen7_video_cmds[] = {
376 { common_cmds, ARRAY_SIZE(common_cmds) },
377 { video_cmds, ARRAY_SIZE(video_cmds) },
378 };
379
380 static const struct drm_i915_cmd_table hsw_vebox_cmds[] = {
381 { common_cmds, ARRAY_SIZE(common_cmds) },
382 { vecs_cmds, ARRAY_SIZE(vecs_cmds) },
383 };
384
385 static const struct drm_i915_cmd_table gen7_blt_cmds[] = {
386 { common_cmds, ARRAY_SIZE(common_cmds) },
387 { blt_cmds, ARRAY_SIZE(blt_cmds) },
388 };
389
390 static const struct drm_i915_cmd_table hsw_blt_ring_cmds[] = {
391 { common_cmds, ARRAY_SIZE(common_cmds) },
392 { blt_cmds, ARRAY_SIZE(blt_cmds) },
393 { hsw_blt_cmds, ARRAY_SIZE(hsw_blt_cmds) },
394 };
395
396 /*
397 * Register whitelists, sorted by increasing register offset.
398 *
399 * Some registers that userspace accesses are 64 bits. The register
400 * access commands only allow 32-bit accesses. Hence, we have to include
401 * entries for both halves of the 64-bit registers.
402 */
403
404 /* Convenience macro for adding 64-bit registers */
405 #define REG64(addr) (addr), (addr + sizeof(u32))
406
407 static const u32 gen7_render_regs[] = {
408 REG64(HS_INVOCATION_COUNT),
409 REG64(DS_INVOCATION_COUNT),
410 REG64(IA_VERTICES_COUNT),
411 REG64(IA_PRIMITIVES_COUNT),
412 REG64(VS_INVOCATION_COUNT),
413 REG64(GS_INVOCATION_COUNT),
414 REG64(GS_PRIMITIVES_COUNT),
415 REG64(CL_INVOCATION_COUNT),
416 REG64(CL_PRIMITIVES_COUNT),
417 REG64(PS_INVOCATION_COUNT),
418 REG64(PS_DEPTH_COUNT),
419 OACONTROL, /* Only allowed for LRI and SRM. See below. */
420 REG64(MI_PREDICATE_SRC0),
421 REG64(MI_PREDICATE_SRC1),
422 GEN7_3DPRIM_END_OFFSET,
423 GEN7_3DPRIM_START_VERTEX,
424 GEN7_3DPRIM_VERTEX_COUNT,
425 GEN7_3DPRIM_INSTANCE_COUNT,
426 GEN7_3DPRIM_START_INSTANCE,
427 GEN7_3DPRIM_BASE_VERTEX,
428 REG64(GEN7_SO_NUM_PRIMS_WRITTEN(0)),
429 REG64(GEN7_SO_NUM_PRIMS_WRITTEN(1)),
430 REG64(GEN7_SO_NUM_PRIMS_WRITTEN(2)),
431 REG64(GEN7_SO_NUM_PRIMS_WRITTEN(3)),
432 REG64(GEN7_SO_PRIM_STORAGE_NEEDED(0)),
433 REG64(GEN7_SO_PRIM_STORAGE_NEEDED(1)),
434 REG64(GEN7_SO_PRIM_STORAGE_NEEDED(2)),
435 REG64(GEN7_SO_PRIM_STORAGE_NEEDED(3)),
436 GEN7_SO_WRITE_OFFSET(0),
437 GEN7_SO_WRITE_OFFSET(1),
438 GEN7_SO_WRITE_OFFSET(2),
439 GEN7_SO_WRITE_OFFSET(3),
440 GEN7_L3SQCREG1,
441 GEN7_L3CNTLREG2,
442 GEN7_L3CNTLREG3,
443 };
444
445 static const u32 gen7_blt_regs[] = {
446 BCS_SWCTRL,
447 };
448
449 static const u32 ivb_master_regs[] = {
450 FORCEWAKE_MT,
451 DERRMR,
452 GEN7_PIPE_DE_LOAD_SL(PIPE_A),
453 GEN7_PIPE_DE_LOAD_SL(PIPE_B),
454 GEN7_PIPE_DE_LOAD_SL(PIPE_C),
455 };
456
457 static const u32 hsw_master_regs[] = {
458 FORCEWAKE_MT,
459 DERRMR,
460 };
461
462 #undef REG64
463
464 static u32 gen7_render_get_cmd_length_mask(u32 cmd_header)
465 {
466 u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT;
467 u32 subclient =
468 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT;
469
470 if (client == INSTR_MI_CLIENT)
471 return 0x3F;
472 else if (client == INSTR_RC_CLIENT) {
473 if (subclient == INSTR_MEDIA_SUBCLIENT)
474 return 0xFFFF;
475 else
476 return 0xFF;
477 }
478
479 DRM_DEBUG_DRIVER("CMD: Abnormal rcs cmd length! 0x%08X\n", cmd_header);
480 return 0;
481 }
482
483 static u32 gen7_bsd_get_cmd_length_mask(u32 cmd_header)
484 {
485 u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT;
486 u32 subclient =
487 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT;
488 u32 op = (cmd_header & INSTR_26_TO_24_MASK) >> INSTR_26_TO_24_SHIFT;
489
490 if (client == INSTR_MI_CLIENT)
491 return 0x3F;
492 else if (client == INSTR_RC_CLIENT) {
493 if (subclient == INSTR_MEDIA_SUBCLIENT) {
494 if (op == 6)
495 return 0xFFFF;
496 else
497 return 0xFFF;
498 } else
499 return 0xFF;
500 }
501
502 DRM_DEBUG_DRIVER("CMD: Abnormal bsd cmd length! 0x%08X\n", cmd_header);
503 return 0;
504 }
505
506 static u32 gen7_blt_get_cmd_length_mask(u32 cmd_header)
507 {
508 u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT;
509
510 if (client == INSTR_MI_CLIENT)
511 return 0x3F;
512 else if (client == INSTR_BC_CLIENT)
513 return 0xFF;
514
515 DRM_DEBUG_DRIVER("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header);
516 return 0;
517 }
518
519 static bool validate_cmds_sorted(struct intel_engine_cs *ring,
520 const struct drm_i915_cmd_table *cmd_tables,
521 int cmd_table_count)
522 {
523 int i;
524 bool ret = true;
525
526 if (!cmd_tables || cmd_table_count == 0)
527 return true;
528
529 for (i = 0; i < cmd_table_count; i++) {
530 const struct drm_i915_cmd_table *table = &cmd_tables[i];
531 u32 previous = 0;
532 int j;
533
534 for (j = 0; j < table->count; j++) {
535 const struct drm_i915_cmd_descriptor *desc =
536 &table->table[i];
537 u32 curr = desc->cmd.value & desc->cmd.mask;
538
539 if (curr < previous) {
540 DRM_ERROR("CMD: table not sorted ring=%d table=%d entry=%d cmd=0x%08X prev=0x%08X\n",
541 ring->id, i, j, curr, previous);
542 ret = false;
543 }
544
545 previous = curr;
546 }
547 }
548
549 return ret;
550 }
551
552 static bool check_sorted(int ring_id, const u32 *reg_table, int reg_count)
553 {
554 int i;
555 u32 previous = 0;
556 bool ret = true;
557
558 for (i = 0; i < reg_count; i++) {
559 u32 curr = reg_table[i];
560
561 if (curr < previous) {
562 DRM_ERROR("CMD: table not sorted ring=%d entry=%d reg=0x%08X prev=0x%08X\n",
563 ring_id, i, curr, previous);
564 ret = false;
565 }
566
567 previous = curr;
568 }
569
570 return ret;
571 }
572
573 static bool validate_regs_sorted(struct intel_engine_cs *ring)
574 {
575 return check_sorted(ring->id, ring->reg_table, ring->reg_count) &&
576 check_sorted(ring->id, ring->master_reg_table,
577 ring->master_reg_count);
578 }
579
580 struct cmd_node {
581 const struct drm_i915_cmd_descriptor *desc;
582 struct hlist_node node;
583 };
584
585 /*
586 * Different command ranges have different numbers of bits for the opcode. For
587 * example, MI commands use bits 31:23 while 3D commands use bits 31:16. The
588 * problem is that, for example, MI commands use bits 22:16 for other fields
589 * such as GGTT vs PPGTT bits. If we include those bits in the mask then when
590 * we mask a command from a batch it could hash to the wrong bucket due to
591 * non-opcode bits being set. But if we don't include those bits, some 3D
592 * commands may hash to the same bucket due to not including opcode bits that
593 * make the command unique. For now, we will risk hashing to the same bucket.
594 *
595 * If we attempt to generate a perfect hash, we should be able to look at bits
596 * 31:29 of a command from a batch buffer and use the full mask for that
597 * client. The existing INSTR_CLIENT_MASK/SHIFT defines can be used for this.
598 */
599 #define CMD_HASH_MASK STD_MI_OPCODE_MASK
600
601 static int init_hash_table(struct intel_engine_cs *ring,
602 const struct drm_i915_cmd_table *cmd_tables,
603 int cmd_table_count)
604 {
605 int i, j;
606
607 hash_init(ring->cmd_hash);
608
609 for (i = 0; i < cmd_table_count; i++) {
610 const struct drm_i915_cmd_table *table = &cmd_tables[i];
611
612 for (j = 0; j < table->count; j++) {
613 const struct drm_i915_cmd_descriptor *desc =
614 &table->table[j];
615 struct cmd_node *desc_node =
616 kmalloc(sizeof(*desc_node), GFP_KERNEL);
617
618 if (!desc_node)
619 return -ENOMEM;
620
621 desc_node->desc = desc;
622 hash_add(ring->cmd_hash, &desc_node->node,
623 desc->cmd.value & CMD_HASH_MASK);
624 }
625 }
626
627 return 0;
628 }
629
630 static void fini_hash_table(struct intel_engine_cs *ring)
631 {
632 struct hlist_node *tmp;
633 struct cmd_node *desc_node;
634 int i;
635
636 hash_for_each_safe(ring->cmd_hash, i, tmp, desc_node, node) {
637 hash_del(&desc_node->node);
638 kfree(desc_node);
639 }
640 }
641
642 /**
643 * i915_cmd_parser_init_ring() - set cmd parser related fields for a ringbuffer
644 * @ring: the ringbuffer to initialize
645 *
646 * Optionally initializes fields related to batch buffer command parsing in the
647 * struct intel_engine_cs based on whether the platform requires software
648 * command parsing.
649 *
650 * Return: non-zero if initialization fails
651 */
652 int i915_cmd_parser_init_ring(struct intel_engine_cs *ring)
653 {
654 const struct drm_i915_cmd_table *cmd_tables;
655 int cmd_table_count;
656 int ret;
657
658 if (!IS_GEN7(ring->dev))
659 return 0;
660
661 switch (ring->id) {
662 case RCS:
663 if (IS_HASWELL(ring->dev)) {
664 cmd_tables = hsw_render_ring_cmds;
665 cmd_table_count =
666 ARRAY_SIZE(hsw_render_ring_cmds);
667 } else {
668 cmd_tables = gen7_render_cmds;
669 cmd_table_count = ARRAY_SIZE(gen7_render_cmds);
670 }
671
672 ring->reg_table = gen7_render_regs;
673 ring->reg_count = ARRAY_SIZE(gen7_render_regs);
674
675 if (IS_HASWELL(ring->dev)) {
676 ring->master_reg_table = hsw_master_regs;
677 ring->master_reg_count = ARRAY_SIZE(hsw_master_regs);
678 } else {
679 ring->master_reg_table = ivb_master_regs;
680 ring->master_reg_count = ARRAY_SIZE(ivb_master_regs);
681 }
682
683 ring->get_cmd_length_mask = gen7_render_get_cmd_length_mask;
684 break;
685 case VCS:
686 cmd_tables = gen7_video_cmds;
687 cmd_table_count = ARRAY_SIZE(gen7_video_cmds);
688 ring->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
689 break;
690 case BCS:
691 if (IS_HASWELL(ring->dev)) {
692 cmd_tables = hsw_blt_ring_cmds;
693 cmd_table_count = ARRAY_SIZE(hsw_blt_ring_cmds);
694 } else {
695 cmd_tables = gen7_blt_cmds;
696 cmd_table_count = ARRAY_SIZE(gen7_blt_cmds);
697 }
698
699 ring->reg_table = gen7_blt_regs;
700 ring->reg_count = ARRAY_SIZE(gen7_blt_regs);
701
702 if (IS_HASWELL(ring->dev)) {
703 ring->master_reg_table = hsw_master_regs;
704 ring->master_reg_count = ARRAY_SIZE(hsw_master_regs);
705 } else {
706 ring->master_reg_table = ivb_master_regs;
707 ring->master_reg_count = ARRAY_SIZE(ivb_master_regs);
708 }
709
710 ring->get_cmd_length_mask = gen7_blt_get_cmd_length_mask;
711 break;
712 case VECS:
713 cmd_tables = hsw_vebox_cmds;
714 cmd_table_count = ARRAY_SIZE(hsw_vebox_cmds);
715 /* VECS can use the same length_mask function as VCS */
716 ring->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
717 break;
718 default:
719 DRM_ERROR("CMD: cmd_parser_init with unknown ring: %d\n",
720 ring->id);
721 BUG();
722 }
723
724 BUG_ON(!validate_cmds_sorted(ring, cmd_tables, cmd_table_count));
725 BUG_ON(!validate_regs_sorted(ring));
726
727 WARN_ON(!hash_empty(ring->cmd_hash));
728
729 ret = init_hash_table(ring, cmd_tables, cmd_table_count);
730 if (ret) {
731 DRM_ERROR("CMD: cmd_parser_init failed!\n");
732 fini_hash_table(ring);
733 return ret;
734 }
735
736 ring->needs_cmd_parser = true;
737
738 return 0;
739 }
740
741 /**
742 * i915_cmd_parser_fini_ring() - clean up cmd parser related fields
743 * @ring: the ringbuffer to clean up
744 *
745 * Releases any resources related to command parsing that may have been
746 * initialized for the specified ring.
747 */
748 void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring)
749 {
750 if (!ring->needs_cmd_parser)
751 return;
752
753 fini_hash_table(ring);
754 }
755
756 static const struct drm_i915_cmd_descriptor*
757 find_cmd_in_table(struct intel_engine_cs *ring,
758 u32 cmd_header)
759 {
760 struct cmd_node *desc_node;
761
762 hash_for_each_possible(ring->cmd_hash, desc_node, node,
763 cmd_header & CMD_HASH_MASK) {
764 const struct drm_i915_cmd_descriptor *desc = desc_node->desc;
765 u32 masked_cmd = desc->cmd.mask & cmd_header;
766 u32 masked_value = desc->cmd.value & desc->cmd.mask;
767
768 if (masked_cmd == masked_value)
769 return desc;
770 }
771
772 return NULL;
773 }
774
775 /*
776 * Returns a pointer to a descriptor for the command specified by cmd_header.
777 *
778 * The caller must supply space for a default descriptor via the default_desc
779 * parameter. If no descriptor for the specified command exists in the ring's
780 * command parser tables, this function fills in default_desc based on the
781 * ring's default length encoding and returns default_desc.
782 */
783 static const struct drm_i915_cmd_descriptor*
784 find_cmd(struct intel_engine_cs *ring,
785 u32 cmd_header,
786 struct drm_i915_cmd_descriptor *default_desc)
787 {
788 const struct drm_i915_cmd_descriptor *desc;
789 u32 mask;
790
791 desc = find_cmd_in_table(ring, cmd_header);
792 if (desc)
793 return desc;
794
795 mask = ring->get_cmd_length_mask(cmd_header);
796 if (!mask)
797 return NULL;
798
799 BUG_ON(!default_desc);
800 default_desc->flags = CMD_DESC_SKIP;
801 default_desc->length.mask = mask;
802
803 return default_desc;
804 }
805
806 static bool valid_reg(const u32 *table, int count, u32 addr)
807 {
808 if (table && count != 0) {
809 int i;
810
811 for (i = 0; i < count; i++) {
812 if (table[i] == addr)
813 return true;
814 }
815 }
816
817 return false;
818 }
819
820 static u32 *vmap_batch(struct drm_i915_gem_object *obj)
821 {
822 int i;
823 void *addr = NULL;
824 struct sg_page_iter sg_iter;
825 struct page **pages;
826
827 pages = drm_malloc_ab(obj->base.size >> PAGE_SHIFT, sizeof(*pages));
828 if (pages == NULL) {
829 DRM_DEBUG_DRIVER("Failed to get space for pages\n");
830 goto finish;
831 }
832
833 i = 0;
834 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
835 pages[i] = sg_page_iter_page(&sg_iter);
836 i++;
837 }
838
839 addr = vmap(pages, i, 0, PAGE_KERNEL);
840 if (addr == NULL) {
841 DRM_DEBUG_DRIVER("Failed to vmap pages\n");
842 goto finish;
843 }
844
845 finish:
846 if (pages)
847 drm_free_large(pages);
848 return (u32*)addr;
849 }
850
851 /**
852 * i915_needs_cmd_parser() - should a given ring use software command parsing?
853 * @ring: the ring in question
854 *
855 * Only certain platforms require software batch buffer command parsing, and
856 * only when enabled via module parameter.
857 *
858 * Return: true if the ring requires software command parsing
859 */
860 bool i915_needs_cmd_parser(struct intel_engine_cs *ring)
861 {
862 if (!ring->needs_cmd_parser)
863 return false;
864
865 if (!USES_PPGTT(ring->dev))
866 return false;
867
868 return (i915.enable_cmd_parser == 1);
869 }
870
871 static bool check_cmd(const struct intel_engine_cs *ring,
872 const struct drm_i915_cmd_descriptor *desc,
873 const u32 *cmd,
874 const bool is_master,
875 bool *oacontrol_set)
876 {
877 if (desc->flags & CMD_DESC_REJECT) {
878 DRM_DEBUG_DRIVER("CMD: Rejected command: 0x%08X\n", *cmd);
879 return false;
880 }
881
882 if ((desc->flags & CMD_DESC_MASTER) && !is_master) {
883 DRM_DEBUG_DRIVER("CMD: Rejected master-only command: 0x%08X\n",
884 *cmd);
885 return false;
886 }
887
888 if (desc->flags & CMD_DESC_REGISTER) {
889 u32 reg_addr = cmd[desc->reg.offset] & desc->reg.mask;
890
891 /*
892 * OACONTROL requires some special handling for writes. We
893 * want to make sure that any batch which enables OA also
894 * disables it before the end of the batch. The goal is to
895 * prevent one process from snooping on the perf data from
896 * another process. To do that, we need to check the value
897 * that will be written to the register. Hence, limit
898 * OACONTROL writes to only MI_LOAD_REGISTER_IMM commands.
899 */
900 if (reg_addr == OACONTROL) {
901 if (desc->cmd.value == MI_LOAD_REGISTER_MEM) {
902 DRM_DEBUG_DRIVER("CMD: Rejected LRM to OACONTROL\n");
903 return false;
904 }
905
906 if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1))
907 *oacontrol_set = (cmd[2] != 0);
908 }
909
910 if (!valid_reg(ring->reg_table,
911 ring->reg_count, reg_addr)) {
912 if (!is_master ||
913 !valid_reg(ring->master_reg_table,
914 ring->master_reg_count,
915 reg_addr)) {
916 DRM_DEBUG_DRIVER("CMD: Rejected register 0x%08X in command: 0x%08X (ring=%d)\n",
917 reg_addr,
918 *cmd,
919 ring->id);
920 return false;
921 }
922 }
923 }
924
925 if (desc->flags & CMD_DESC_BITMASK) {
926 int i;
927
928 for (i = 0; i < MAX_CMD_DESC_BITMASKS; i++) {
929 u32 dword;
930
931 if (desc->bits[i].mask == 0)
932 break;
933
934 if (desc->bits[i].condition_mask != 0) {
935 u32 offset =
936 desc->bits[i].condition_offset;
937 u32 condition = cmd[offset] &
938 desc->bits[i].condition_mask;
939
940 if (condition == 0)
941 continue;
942 }
943
944 dword = cmd[desc->bits[i].offset] &
945 desc->bits[i].mask;
946
947 if (dword != desc->bits[i].expected) {
948 DRM_DEBUG_DRIVER("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (ring=%d)\n",
949 *cmd,
950 desc->bits[i].mask,
951 desc->bits[i].expected,
952 dword, ring->id);
953 return false;
954 }
955 }
956 }
957
958 return true;
959 }
960
961 #define LENGTH_BIAS 2
962
963 /**
964 * i915_parse_cmds() - parse a submitted batch buffer for privilege violations
965 * @ring: the ring on which the batch is to execute
966 * @batch_obj: the batch buffer in question
967 * @batch_start_offset: byte offset in the batch at which execution starts
968 * @is_master: is the submitting process the drm master?
969 *
970 * Parses the specified batch buffer looking for privilege violations as
971 * described in the overview.
972 *
973 * Return: non-zero if the parser finds violations or otherwise fails; -EACCES
974 * if the batch appears legal but should use hardware parsing
975 */
976 int i915_parse_cmds(struct intel_engine_cs *ring,
977 struct drm_i915_gem_object *batch_obj,
978 u32 batch_start_offset,
979 bool is_master)
980 {
981 int ret = 0;
982 u32 *cmd, *batch_base, *batch_end;
983 struct drm_i915_cmd_descriptor default_desc = { 0 };
984 int needs_clflush = 0;
985 bool oacontrol_set = false; /* OACONTROL tracking. See check_cmd() */
986
987 ret = i915_gem_obj_prepare_shmem_read(batch_obj, &needs_clflush);
988 if (ret) {
989 DRM_DEBUG_DRIVER("CMD: failed to prep read\n");
990 return ret;
991 }
992
993 batch_base = vmap_batch(batch_obj);
994 if (!batch_base) {
995 DRM_DEBUG_DRIVER("CMD: Failed to vmap batch\n");
996 i915_gem_object_unpin_pages(batch_obj);
997 return -ENOMEM;
998 }
999
1000 if (needs_clflush)
1001 drm_clflush_virt_range((char *)batch_base, batch_obj->base.size);
1002
1003 cmd = batch_base + (batch_start_offset / sizeof(*cmd));
1004 batch_end = cmd + (batch_obj->base.size / sizeof(*batch_end));
1005
1006 while (cmd < batch_end) {
1007 const struct drm_i915_cmd_descriptor *desc;
1008 u32 length;
1009
1010 if (*cmd == MI_BATCH_BUFFER_END)
1011 break;
1012
1013 desc = find_cmd(ring, *cmd, &default_desc);
1014 if (!desc) {
1015 DRM_DEBUG_DRIVER("CMD: Unrecognized command: 0x%08X\n",
1016 *cmd);
1017 ret = -EINVAL;
1018 break;
1019 }
1020
1021 /*
1022 * If the batch buffer contains a chained batch, return an
1023 * error that tells the caller to abort and dispatch the
1024 * workload as a non-secure batch.
1025 */
1026 if (desc->cmd.value == MI_BATCH_BUFFER_START) {
1027 ret = -EACCES;
1028 break;
1029 }
1030
1031 if (desc->flags & CMD_DESC_FIXED)
1032 length = desc->length.fixed;
1033 else
1034 length = ((*cmd & desc->length.mask) + LENGTH_BIAS);
1035
1036 if ((batch_end - cmd) < length) {
1037 DRM_DEBUG_DRIVER("CMD: Command length exceeds batch length: 0x%08X length=%u batchlen=%td\n",
1038 *cmd,
1039 length,
1040 batch_end - cmd);
1041 ret = -EINVAL;
1042 break;
1043 }
1044
1045 if (!check_cmd(ring, desc, cmd, is_master, &oacontrol_set)) {
1046 ret = -EINVAL;
1047 break;
1048 }
1049
1050 cmd += length;
1051 }
1052
1053 if (oacontrol_set) {
1054 DRM_DEBUG_DRIVER("CMD: batch set OACONTROL but did not clear it\n");
1055 ret = -EINVAL;
1056 }
1057
1058 if (cmd >= batch_end) {
1059 DRM_DEBUG_DRIVER("CMD: Got to the end of the buffer w/o a BBE cmd!\n");
1060 ret = -EINVAL;
1061 }
1062
1063 vunmap(batch_base);
1064
1065 i915_gem_object_unpin_pages(batch_obj);
1066
1067 return ret;
1068 }
1069
1070 /**
1071 * i915_cmd_parser_get_version() - get the cmd parser version number
1072 *
1073 * The cmd parser maintains a simple increasing integer version number suitable
1074 * for passing to userspace clients to determine what operations are permitted.
1075 *
1076 * Return: the current version number of the cmd parser
1077 */
1078 int i915_cmd_parser_get_version(void)
1079 {
1080 /*
1081 * Command parser version history
1082 *
1083 * 1. Initial version. Checks batches and reports violations, but leaves
1084 * hardware parsing enabled (so does not allow new use cases).
1085 * 2. Allow access to the MI_PREDICATE_SRC0 and
1086 * MI_PREDICATE_SRC1 registers.
1087 */
1088 return 2;
1089 }
Linux kernel - Deliverables
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