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drm/i915/cmdparser: Add the TIMESTAMP register for the other engines
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_cmd_parser.c
1 /*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Brad Volkin <bradley.d.volkin@intel.com>
25 *
26 */
27
28 #include "i915_drv.h"
29
30 /**
31 * DOC: batch buffer command parser
32 *
33 * Motivation:
34 * Certain OpenGL features (e.g. transform feedback, performance monitoring)
35 * require userspace code to submit batches containing commands such as
36 * MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some
37 * generations of the hardware will noop these commands in "unsecure" batches
38 * (which includes all userspace batches submitted via i915) even though the
39 * commands may be safe and represent the intended programming model of the
40 * device.
41 *
42 * The software command parser is similar in operation to the command parsing
43 * done in hardware for unsecure batches. However, the software parser allows
44 * some operations that would be noop'd by hardware, if the parser determines
45 * the operation is safe, and submits the batch as "secure" to prevent hardware
46 * parsing.
47 *
48 * Threats:
49 * At a high level, the hardware (and software) checks attempt to prevent
50 * granting userspace undue privileges. There are three categories of privilege.
51 *
52 * First, commands which are explicitly defined as privileged or which should
53 * only be used by the kernel driver. The parser generally rejects such
54 * commands, though it may allow some from the drm master process.
55 *
56 * Second, commands which access registers. To support correct/enhanced
57 * userspace functionality, particularly certain OpenGL extensions, the parser
58 * provides a whitelist of registers which userspace may safely access (for both
59 * normal and drm master processes).
60 *
61 * Third, commands which access privileged memory (i.e. GGTT, HWS page, etc).
62 * The parser always rejects such commands.
63 *
64 * The majority of the problematic commands fall in the MI_* range, with only a
65 * few specific commands on each engine (e.g. PIPE_CONTROL and MI_FLUSH_DW).
66 *
67 * Implementation:
68 * Each engine maintains tables of commands and registers which the parser
69 * uses in scanning batch buffers submitted to that engine.
70 *
71 * Since the set of commands that the parser must check for is significantly
72 * smaller than the number of commands supported, the parser tables contain only
73 * those commands required by the parser. This generally works because command
74 * opcode ranges have standard command length encodings. So for commands that
75 * the parser does not need to check, it can easily skip them. This is
76 * implemented via a per-engine length decoding vfunc.
77 *
78 * Unfortunately, there are a number of commands that do not follow the standard
79 * length encoding for their opcode range, primarily amongst the MI_* commands.
80 * To handle this, the parser provides a way to define explicit "skip" entries
81 * in the per-engine command tables.
82 *
83 * Other command table entries map fairly directly to high level categories
84 * mentioned above: rejected, master-only, register whitelist. The parser
85 * implements a number of checks, including the privileged memory checks, via a
86 * general bitmasking mechanism.
87 */
88
89 #define STD_MI_OPCODE_MASK 0xFF800000
90 #define STD_3D_OPCODE_MASK 0xFFFF0000
91 #define STD_2D_OPCODE_MASK 0xFFC00000
92 #define STD_MFX_OPCODE_MASK 0xFFFF0000
93
94 #define CMD(op, opm, f, lm, fl, ...) \
95 { \
96 .flags = (fl) | ((f) ? CMD_DESC_FIXED : 0), \
97 .cmd = { (op), (opm) }, \
98 .length = { (lm) }, \
99 __VA_ARGS__ \
100 }
101
102 /* Convenience macros to compress the tables */
103 #define SMI STD_MI_OPCODE_MASK
104 #define S3D STD_3D_OPCODE_MASK
105 #define S2D STD_2D_OPCODE_MASK
106 #define SMFX STD_MFX_OPCODE_MASK
107 #define F true
108 #define S CMD_DESC_SKIP
109 #define R CMD_DESC_REJECT
110 #define W CMD_DESC_REGISTER
111 #define B CMD_DESC_BITMASK
112 #define M CMD_DESC_MASTER
113
114 /* Command Mask Fixed Len Action
115 ---------------------------------------------------------- */
116 static const struct drm_i915_cmd_descriptor common_cmds[] = {
117 CMD( MI_NOOP, SMI, F, 1, S ),
118 CMD( MI_USER_INTERRUPT, SMI, F, 1, R ),
119 CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, M ),
120 CMD( MI_ARB_CHECK, SMI, F, 1, S ),
121 CMD( MI_REPORT_HEAD, SMI, F, 1, S ),
122 CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ),
123 CMD( MI_SEMAPHORE_MBOX, SMI, !F, 0xFF, R ),
124 CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, R ),
125 CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W,
126 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 } ),
127 CMD( MI_STORE_REGISTER_MEM, SMI, F, 3, W | B,
128 .reg = { .offset = 1, .mask = 0x007FFFFC },
129 .bits = {{
130 .offset = 0,
131 .mask = MI_GLOBAL_GTT,
132 .expected = 0,
133 }}, ),
134 CMD( MI_LOAD_REGISTER_MEM, SMI, F, 3, W | B,
135 .reg = { .offset = 1, .mask = 0x007FFFFC },
136 .bits = {{
137 .offset = 0,
138 .mask = MI_GLOBAL_GTT,
139 .expected = 0,
140 }}, ),
141 /*
142 * MI_BATCH_BUFFER_START requires some special handling. It's not
143 * really a 'skip' action but it doesn't seem like it's worth adding
144 * a new action. See i915_parse_cmds().
145 */
146 CMD( MI_BATCH_BUFFER_START, SMI, !F, 0xFF, S ),
147 };
148
149 static const struct drm_i915_cmd_descriptor render_cmds[] = {
150 CMD( MI_FLUSH, SMI, F, 1, S ),
151 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
152 CMD( MI_PREDICATE, SMI, F, 1, S ),
153 CMD( MI_TOPOLOGY_FILTER, SMI, F, 1, S ),
154 CMD( MI_SET_APPID, SMI, F, 1, S ),
155 CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ),
156 CMD( MI_SET_CONTEXT, SMI, !F, 0xFF, R ),
157 CMD( MI_URB_CLEAR, SMI, !F, 0xFF, S ),
158 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3F, B,
159 .bits = {{
160 .offset = 0,
161 .mask = MI_GLOBAL_GTT,
162 .expected = 0,
163 }}, ),
164 CMD( MI_UPDATE_GTT, SMI, !F, 0xFF, R ),
165 CMD( MI_CLFLUSH, SMI, !F, 0x3FF, B,
166 .bits = {{
167 .offset = 0,
168 .mask = MI_GLOBAL_GTT,
169 .expected = 0,
170 }}, ),
171 CMD( MI_REPORT_PERF_COUNT, SMI, !F, 0x3F, B,
172 .bits = {{
173 .offset = 1,
174 .mask = MI_REPORT_PERF_COUNT_GGTT,
175 .expected = 0,
176 }}, ),
177 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,
178 .bits = {{
179 .offset = 0,
180 .mask = MI_GLOBAL_GTT,
181 .expected = 0,
182 }}, ),
183 CMD( GFX_OP_3DSTATE_VF_STATISTICS, S3D, F, 1, S ),
184 CMD( PIPELINE_SELECT, S3D, F, 1, S ),
185 CMD( MEDIA_VFE_STATE, S3D, !F, 0xFFFF, B,
186 .bits = {{
187 .offset = 2,
188 .mask = MEDIA_VFE_STATE_MMIO_ACCESS_MASK,
189 .expected = 0,
190 }}, ),
191 CMD( GPGPU_OBJECT, S3D, !F, 0xFF, S ),
192 CMD( GPGPU_WALKER, S3D, !F, 0xFF, S ),
193 CMD( GFX_OP_3DSTATE_SO_DECL_LIST, S3D, !F, 0x1FF, S ),
194 CMD( GFX_OP_PIPE_CONTROL(5), S3D, !F, 0xFF, B,
195 .bits = {{
196 .offset = 1,
197 .mask = (PIPE_CONTROL_MMIO_WRITE | PIPE_CONTROL_NOTIFY),
198 .expected = 0,
199 },
200 {
201 .offset = 1,
202 .mask = (PIPE_CONTROL_GLOBAL_GTT_IVB |
203 PIPE_CONTROL_STORE_DATA_INDEX),
204 .expected = 0,
205 .condition_offset = 1,
206 .condition_mask = PIPE_CONTROL_POST_SYNC_OP_MASK,
207 }}, ),
208 };
209
210 static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = {
211 CMD( MI_SET_PREDICATE, SMI, F, 1, S ),
212 CMD( MI_RS_CONTROL, SMI, F, 1, S ),
213 CMD( MI_URB_ATOMIC_ALLOC, SMI, F, 1, S ),
214 CMD( MI_SET_APPID, SMI, F, 1, S ),
215 CMD( MI_RS_CONTEXT, SMI, F, 1, S ),
216 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, M ),
217 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ),
218 CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, W,
219 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 1 } ),
220 CMD( MI_RS_STORE_DATA_IMM, SMI, !F, 0xFF, S ),
221 CMD( MI_LOAD_URB_MEM, SMI, !F, 0xFF, S ),
222 CMD( MI_STORE_URB_MEM, SMI, !F, 0xFF, S ),
223 CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_VS, S3D, !F, 0x7FF, S ),
224 CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_PS, S3D, !F, 0x7FF, S ),
225
226 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS, S3D, !F, 0x1FF, S ),
227 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS, S3D, !F, 0x1FF, S ),
228 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS, S3D, !F, 0x1FF, S ),
229 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS, S3D, !F, 0x1FF, S ),
230 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS, S3D, !F, 0x1FF, S ),
231 };
232
233 static const struct drm_i915_cmd_descriptor video_cmds[] = {
234 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
235 CMD( MI_SET_APPID, SMI, F, 1, S ),
236 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B,
237 .bits = {{
238 .offset = 0,
239 .mask = MI_GLOBAL_GTT,
240 .expected = 0,
241 }}, ),
242 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
243 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
244 .bits = {{
245 .offset = 0,
246 .mask = MI_FLUSH_DW_NOTIFY,
247 .expected = 0,
248 },
249 {
250 .offset = 1,
251 .mask = MI_FLUSH_DW_USE_GTT,
252 .expected = 0,
253 .condition_offset = 0,
254 .condition_mask = MI_FLUSH_DW_OP_MASK,
255 },
256 {
257 .offset = 0,
258 .mask = MI_FLUSH_DW_STORE_INDEX,
259 .expected = 0,
260 .condition_offset = 0,
261 .condition_mask = MI_FLUSH_DW_OP_MASK,
262 }}, ),
263 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,
264 .bits = {{
265 .offset = 0,
266 .mask = MI_GLOBAL_GTT,
267 .expected = 0,
268 }}, ),
269 /*
270 * MFX_WAIT doesn't fit the way we handle length for most commands.
271 * It has a length field but it uses a non-standard length bias.
272 * It is always 1 dword though, so just treat it as fixed length.
273 */
274 CMD( MFX_WAIT, SMFX, F, 1, S ),
275 };
276
277 static const struct drm_i915_cmd_descriptor vecs_cmds[] = {
278 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
279 CMD( MI_SET_APPID, SMI, F, 1, S ),
280 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B,
281 .bits = {{
282 .offset = 0,
283 .mask = MI_GLOBAL_GTT,
284 .expected = 0,
285 }}, ),
286 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
287 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
288 .bits = {{
289 .offset = 0,
290 .mask = MI_FLUSH_DW_NOTIFY,
291 .expected = 0,
292 },
293 {
294 .offset = 1,
295 .mask = MI_FLUSH_DW_USE_GTT,
296 .expected = 0,
297 .condition_offset = 0,
298 .condition_mask = MI_FLUSH_DW_OP_MASK,
299 },
300 {
301 .offset = 0,
302 .mask = MI_FLUSH_DW_STORE_INDEX,
303 .expected = 0,
304 .condition_offset = 0,
305 .condition_mask = MI_FLUSH_DW_OP_MASK,
306 }}, ),
307 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,
308 .bits = {{
309 .offset = 0,
310 .mask = MI_GLOBAL_GTT,
311 .expected = 0,
312 }}, ),
313 };
314
315 static const struct drm_i915_cmd_descriptor blt_cmds[] = {
316 CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ),
317 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, B,
318 .bits = {{
319 .offset = 0,
320 .mask = MI_GLOBAL_GTT,
321 .expected = 0,
322 }}, ),
323 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
324 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
325 .bits = {{
326 .offset = 0,
327 .mask = MI_FLUSH_DW_NOTIFY,
328 .expected = 0,
329 },
330 {
331 .offset = 1,
332 .mask = MI_FLUSH_DW_USE_GTT,
333 .expected = 0,
334 .condition_offset = 0,
335 .condition_mask = MI_FLUSH_DW_OP_MASK,
336 },
337 {
338 .offset = 0,
339 .mask = MI_FLUSH_DW_STORE_INDEX,
340 .expected = 0,
341 .condition_offset = 0,
342 .condition_mask = MI_FLUSH_DW_OP_MASK,
343 }}, ),
344 CMD( COLOR_BLT, S2D, !F, 0x3F, S ),
345 CMD( SRC_COPY_BLT, S2D, !F, 0x3F, S ),
346 };
347
348 static const struct drm_i915_cmd_descriptor hsw_blt_cmds[] = {
349 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, M ),
350 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ),
351 };
352
353 #undef CMD
354 #undef SMI
355 #undef S3D
356 #undef S2D
357 #undef SMFX
358 #undef F
359 #undef S
360 #undef R
361 #undef W
362 #undef B
363 #undef M
364
365 static const struct drm_i915_cmd_table gen7_render_cmds[] = {
366 { common_cmds, ARRAY_SIZE(common_cmds) },
367 { render_cmds, ARRAY_SIZE(render_cmds) },
368 };
369
370 static const struct drm_i915_cmd_table hsw_render_ring_cmds[] = {
371 { common_cmds, ARRAY_SIZE(common_cmds) },
372 { render_cmds, ARRAY_SIZE(render_cmds) },
373 { hsw_render_cmds, ARRAY_SIZE(hsw_render_cmds) },
374 };
375
376 static const struct drm_i915_cmd_table gen7_video_cmds[] = {
377 { common_cmds, ARRAY_SIZE(common_cmds) },
378 { video_cmds, ARRAY_SIZE(video_cmds) },
379 };
380
381 static const struct drm_i915_cmd_table hsw_vebox_cmds[] = {
382 { common_cmds, ARRAY_SIZE(common_cmds) },
383 { vecs_cmds, ARRAY_SIZE(vecs_cmds) },
384 };
385
386 static const struct drm_i915_cmd_table gen7_blt_cmds[] = {
387 { common_cmds, ARRAY_SIZE(common_cmds) },
388 { blt_cmds, ARRAY_SIZE(blt_cmds) },
389 };
390
391 static const struct drm_i915_cmd_table hsw_blt_ring_cmds[] = {
392 { common_cmds, ARRAY_SIZE(common_cmds) },
393 { blt_cmds, ARRAY_SIZE(blt_cmds) },
394 { hsw_blt_cmds, ARRAY_SIZE(hsw_blt_cmds) },
395 };
396
397 /*
398 * Register whitelists, sorted by increasing register offset.
399 */
400
401 /*
402 * An individual whitelist entry granting access to register addr. If
403 * mask is non-zero the argument of immediate register writes will be
404 * AND-ed with mask, and the command will be rejected if the result
405 * doesn't match value.
406 *
407 * Registers with non-zero mask are only allowed to be written using
408 * LRI.
409 */
410 struct drm_i915_reg_descriptor {
411 i915_reg_t addr;
412 u32 mask;
413 u32 value;
414 };
415
416 /* Convenience macro for adding 32-bit registers. */
417 #define REG32(_reg, ...) \
418 { .addr = (_reg), __VA_ARGS__ }
419
420 /*
421 * Convenience macro for adding 64-bit registers.
422 *
423 * Some registers that userspace accesses are 64 bits. The register
424 * access commands only allow 32-bit accesses. Hence, we have to include
425 * entries for both halves of the 64-bit registers.
426 */
427 #define REG64(_reg) \
428 { .addr = _reg }, \
429 { .addr = _reg ## _UDW }
430
431 #define REG64_IDX(_reg, idx) \
432 { .addr = _reg(idx) }, \
433 { .addr = _reg ## _UDW(idx) }
434
435 static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
436 REG64(GPGPU_THREADS_DISPATCHED),
437 REG64(HS_INVOCATION_COUNT),
438 REG64(DS_INVOCATION_COUNT),
439 REG64(IA_VERTICES_COUNT),
440 REG64(IA_PRIMITIVES_COUNT),
441 REG64(VS_INVOCATION_COUNT),
442 REG64(GS_INVOCATION_COUNT),
443 REG64(GS_PRIMITIVES_COUNT),
444 REG64(CL_INVOCATION_COUNT),
445 REG64(CL_PRIMITIVES_COUNT),
446 REG64(PS_INVOCATION_COUNT),
447 REG64(PS_DEPTH_COUNT),
448 REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
449 REG32(OACONTROL), /* Only allowed for LRI and SRM. See below. */
450 REG64(MI_PREDICATE_SRC0),
451 REG64(MI_PREDICATE_SRC1),
452 REG32(GEN7_3DPRIM_END_OFFSET),
453 REG32(GEN7_3DPRIM_START_VERTEX),
454 REG32(GEN7_3DPRIM_VERTEX_COUNT),
455 REG32(GEN7_3DPRIM_INSTANCE_COUNT),
456 REG32(GEN7_3DPRIM_START_INSTANCE),
457 REG32(GEN7_3DPRIM_BASE_VERTEX),
458 REG32(GEN7_GPGPU_DISPATCHDIMX),
459 REG32(GEN7_GPGPU_DISPATCHDIMY),
460 REG32(GEN7_GPGPU_DISPATCHDIMZ),
461 REG64_IDX(RING_TIMESTAMP, BSD_RING_BASE),
462 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 0),
463 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 1),
464 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 2),
465 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 3),
466 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 0),
467 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 1),
468 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 2),
469 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 3),
470 REG32(GEN7_SO_WRITE_OFFSET(0)),
471 REG32(GEN7_SO_WRITE_OFFSET(1)),
472 REG32(GEN7_SO_WRITE_OFFSET(2)),
473 REG32(GEN7_SO_WRITE_OFFSET(3)),
474 REG32(GEN7_L3SQCREG1),
475 REG32(GEN7_L3CNTLREG2),
476 REG32(GEN7_L3CNTLREG3),
477 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
478 };
479
480 static const struct drm_i915_reg_descriptor hsw_render_regs[] = {
481 REG64_IDX(HSW_CS_GPR, 0),
482 REG64_IDX(HSW_CS_GPR, 1),
483 REG64_IDX(HSW_CS_GPR, 2),
484 REG64_IDX(HSW_CS_GPR, 3),
485 REG64_IDX(HSW_CS_GPR, 4),
486 REG64_IDX(HSW_CS_GPR, 5),
487 REG64_IDX(HSW_CS_GPR, 6),
488 REG64_IDX(HSW_CS_GPR, 7),
489 REG64_IDX(HSW_CS_GPR, 8),
490 REG64_IDX(HSW_CS_GPR, 9),
491 REG64_IDX(HSW_CS_GPR, 10),
492 REG64_IDX(HSW_CS_GPR, 11),
493 REG64_IDX(HSW_CS_GPR, 12),
494 REG64_IDX(HSW_CS_GPR, 13),
495 REG64_IDX(HSW_CS_GPR, 14),
496 REG64_IDX(HSW_CS_GPR, 15),
497 REG32(HSW_SCRATCH1,
498 .mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE,
499 .value = 0),
500 REG32(HSW_ROW_CHICKEN3,
501 .mask = ~(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE << 16 |
502 HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE),
503 .value = 0),
504 };
505
506 static const struct drm_i915_reg_descriptor gen7_blt_regs[] = {
507 REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
508 REG64_IDX(RING_TIMESTAMP, BSD_RING_BASE),
509 REG32(BCS_SWCTRL),
510 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
511 };
512
513 static const struct drm_i915_reg_descriptor ivb_master_regs[] = {
514 REG32(FORCEWAKE_MT),
515 REG32(DERRMR),
516 REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_A)),
517 REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_B)),
518 REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_C)),
519 };
520
521 static const struct drm_i915_reg_descriptor hsw_master_regs[] = {
522 REG32(FORCEWAKE_MT),
523 REG32(DERRMR),
524 };
525
526 #undef REG64
527 #undef REG32
528
529 struct drm_i915_reg_table {
530 const struct drm_i915_reg_descriptor *regs;
531 int num_regs;
532 bool master;
533 };
534
535 static const struct drm_i915_reg_table ivb_render_reg_tables[] = {
536 { gen7_render_regs, ARRAY_SIZE(gen7_render_regs), false },
537 { ivb_master_regs, ARRAY_SIZE(ivb_master_regs), true },
538 };
539
540 static const struct drm_i915_reg_table ivb_blt_reg_tables[] = {
541 { gen7_blt_regs, ARRAY_SIZE(gen7_blt_regs), false },
542 { ivb_master_regs, ARRAY_SIZE(ivb_master_regs), true },
543 };
544
545 static const struct drm_i915_reg_table hsw_render_reg_tables[] = {
546 { gen7_render_regs, ARRAY_SIZE(gen7_render_regs), false },
547 { hsw_render_regs, ARRAY_SIZE(hsw_render_regs), false },
548 { hsw_master_regs, ARRAY_SIZE(hsw_master_regs), true },
549 };
550
551 static const struct drm_i915_reg_table hsw_blt_reg_tables[] = {
552 { gen7_blt_regs, ARRAY_SIZE(gen7_blt_regs), false },
553 { hsw_master_regs, ARRAY_SIZE(hsw_master_regs), true },
554 };
555
556 static u32 gen7_render_get_cmd_length_mask(u32 cmd_header)
557 {
558 u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT;
559 u32 subclient =
560 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT;
561
562 if (client == INSTR_MI_CLIENT)
563 return 0x3F;
564 else if (client == INSTR_RC_CLIENT) {
565 if (subclient == INSTR_MEDIA_SUBCLIENT)
566 return 0xFFFF;
567 else
568 return 0xFF;
569 }
570
571 DRM_DEBUG_DRIVER("CMD: Abnormal rcs cmd length! 0x%08X\n", cmd_header);
572 return 0;
573 }
574
575 static u32 gen7_bsd_get_cmd_length_mask(u32 cmd_header)
576 {
577 u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT;
578 u32 subclient =
579 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT;
580 u32 op = (cmd_header & INSTR_26_TO_24_MASK) >> INSTR_26_TO_24_SHIFT;
581
582 if (client == INSTR_MI_CLIENT)
583 return 0x3F;
584 else if (client == INSTR_RC_CLIENT) {
585 if (subclient == INSTR_MEDIA_SUBCLIENT) {
586 if (op == 6)
587 return 0xFFFF;
588 else
589 return 0xFFF;
590 } else
591 return 0xFF;
592 }
593
594 DRM_DEBUG_DRIVER("CMD: Abnormal bsd cmd length! 0x%08X\n", cmd_header);
595 return 0;
596 }
597
598 static u32 gen7_blt_get_cmd_length_mask(u32 cmd_header)
599 {
600 u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT;
601
602 if (client == INSTR_MI_CLIENT)
603 return 0x3F;
604 else if (client == INSTR_BC_CLIENT)
605 return 0xFF;
606
607 DRM_DEBUG_DRIVER("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header);
608 return 0;
609 }
610
611 static bool validate_cmds_sorted(const struct intel_engine_cs *engine,
612 const struct drm_i915_cmd_table *cmd_tables,
613 int cmd_table_count)
614 {
615 int i;
616 bool ret = true;
617
618 if (!cmd_tables || cmd_table_count == 0)
619 return true;
620
621 for (i = 0; i < cmd_table_count; i++) {
622 const struct drm_i915_cmd_table *table = &cmd_tables[i];
623 u32 previous = 0;
624 int j;
625
626 for (j = 0; j < table->count; j++) {
627 const struct drm_i915_cmd_descriptor *desc =
628 &table->table[j];
629 u32 curr = desc->cmd.value & desc->cmd.mask;
630
631 if (curr < previous) {
632 DRM_ERROR("CMD: %s [%d] command table not sorted: "
633 "table=%d entry=%d cmd=0x%08X prev=0x%08X\n",
634 engine->name, engine->id,
635 i, j, curr, previous);
636 ret = false;
637 }
638
639 previous = curr;
640 }
641 }
642
643 return ret;
644 }
645
646 static bool check_sorted(const struct intel_engine_cs *engine,
647 const struct drm_i915_reg_descriptor *reg_table,
648 int reg_count)
649 {
650 int i;
651 u32 previous = 0;
652 bool ret = true;
653
654 for (i = 0; i < reg_count; i++) {
655 u32 curr = i915_mmio_reg_offset(reg_table[i].addr);
656
657 if (curr < previous) {
658 DRM_ERROR("CMD: %s [%d] register table not sorted: "
659 "entry=%d reg=0x%08X prev=0x%08X\n",
660 engine->name, engine->id,
661 i, curr, previous);
662 ret = false;
663 }
664
665 previous = curr;
666 }
667
668 return ret;
669 }
670
671 static bool validate_regs_sorted(struct intel_engine_cs *engine)
672 {
673 int i;
674 const struct drm_i915_reg_table *table;
675
676 for (i = 0; i < engine->reg_table_count; i++) {
677 table = &engine->reg_tables[i];
678 if (!check_sorted(engine, table->regs, table->num_regs))
679 return false;
680 }
681
682 return true;
683 }
684
685 struct cmd_node {
686 const struct drm_i915_cmd_descriptor *desc;
687 struct hlist_node node;
688 };
689
690 /*
691 * Different command ranges have different numbers of bits for the opcode. For
692 * example, MI commands use bits 31:23 while 3D commands use bits 31:16. The
693 * problem is that, for example, MI commands use bits 22:16 for other fields
694 * such as GGTT vs PPGTT bits. If we include those bits in the mask then when
695 * we mask a command from a batch it could hash to the wrong bucket due to
696 * non-opcode bits being set. But if we don't include those bits, some 3D
697 * commands may hash to the same bucket due to not including opcode bits that
698 * make the command unique. For now, we will risk hashing to the same bucket.
699 *
700 * If we attempt to generate a perfect hash, we should be able to look at bits
701 * 31:29 of a command from a batch buffer and use the full mask for that
702 * client. The existing INSTR_CLIENT_MASK/SHIFT defines can be used for this.
703 */
704 #define CMD_HASH_MASK STD_MI_OPCODE_MASK
705
706 static int init_hash_table(struct intel_engine_cs *engine,
707 const struct drm_i915_cmd_table *cmd_tables,
708 int cmd_table_count)
709 {
710 int i, j;
711
712 hash_init(engine->cmd_hash);
713
714 for (i = 0; i < cmd_table_count; i++) {
715 const struct drm_i915_cmd_table *table = &cmd_tables[i];
716
717 for (j = 0; j < table->count; j++) {
718 const struct drm_i915_cmd_descriptor *desc =
719 &table->table[j];
720 struct cmd_node *desc_node =
721 kmalloc(sizeof(*desc_node), GFP_KERNEL);
722
723 if (!desc_node)
724 return -ENOMEM;
725
726 desc_node->desc = desc;
727 hash_add(engine->cmd_hash, &desc_node->node,
728 desc->cmd.value & CMD_HASH_MASK);
729 }
730 }
731
732 return 0;
733 }
734
735 static void fini_hash_table(struct intel_engine_cs *engine)
736 {
737 struct hlist_node *tmp;
738 struct cmd_node *desc_node;
739 int i;
740
741 hash_for_each_safe(engine->cmd_hash, i, tmp, desc_node, node) {
742 hash_del(&desc_node->node);
743 kfree(desc_node);
744 }
745 }
746
747 /**
748 * intel_engine_init_cmd_parser() - set cmd parser related fields for an engine
749 * @engine: the engine to initialize
750 *
751 * Optionally initializes fields related to batch buffer command parsing in the
752 * struct intel_engine_cs based on whether the platform requires software
753 * command parsing.
754 */
755 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine)
756 {
757 const struct drm_i915_cmd_table *cmd_tables;
758 int cmd_table_count;
759 int ret;
760
761 if (!IS_GEN7(engine->i915))
762 return;
763
764 switch (engine->id) {
765 case RCS:
766 if (IS_HASWELL(engine->i915)) {
767 cmd_tables = hsw_render_ring_cmds;
768 cmd_table_count =
769 ARRAY_SIZE(hsw_render_ring_cmds);
770 } else {
771 cmd_tables = gen7_render_cmds;
772 cmd_table_count = ARRAY_SIZE(gen7_render_cmds);
773 }
774
775 if (IS_HASWELL(engine->i915)) {
776 engine->reg_tables = hsw_render_reg_tables;
777 engine->reg_table_count = ARRAY_SIZE(hsw_render_reg_tables);
778 } else {
779 engine->reg_tables = ivb_render_reg_tables;
780 engine->reg_table_count = ARRAY_SIZE(ivb_render_reg_tables);
781 }
782
783 engine->get_cmd_length_mask = gen7_render_get_cmd_length_mask;
784 break;
785 case VCS:
786 cmd_tables = gen7_video_cmds;
787 cmd_table_count = ARRAY_SIZE(gen7_video_cmds);
788 engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
789 break;
790 case BCS:
791 if (IS_HASWELL(engine->i915)) {
792 cmd_tables = hsw_blt_ring_cmds;
793 cmd_table_count = ARRAY_SIZE(hsw_blt_ring_cmds);
794 } else {
795 cmd_tables = gen7_blt_cmds;
796 cmd_table_count = ARRAY_SIZE(gen7_blt_cmds);
797 }
798
799 if (IS_HASWELL(engine->i915)) {
800 engine->reg_tables = hsw_blt_reg_tables;
801 engine->reg_table_count = ARRAY_SIZE(hsw_blt_reg_tables);
802 } else {
803 engine->reg_tables = ivb_blt_reg_tables;
804 engine->reg_table_count = ARRAY_SIZE(ivb_blt_reg_tables);
805 }
806
807 engine->get_cmd_length_mask = gen7_blt_get_cmd_length_mask;
808 break;
809 case VECS:
810 cmd_tables = hsw_vebox_cmds;
811 cmd_table_count = ARRAY_SIZE(hsw_vebox_cmds);
812 /* VECS can use the same length_mask function as VCS */
813 engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
814 break;
815 default:
816 MISSING_CASE(engine->id);
817 return;
818 }
819
820 if (!validate_cmds_sorted(engine, cmd_tables, cmd_table_count)) {
821 DRM_ERROR("%s: command descriptions are not sorted\n",
822 engine->name);
823 return;
824 }
825 if (!validate_regs_sorted(engine)) {
826 DRM_ERROR("%s: registers are not sorted\n", engine->name);
827 return;
828 }
829
830 ret = init_hash_table(engine, cmd_tables, cmd_table_count);
831 if (ret) {
832 DRM_ERROR("%s: initialised failed!\n", engine->name);
833 fini_hash_table(engine);
834 return;
835 }
836
837 engine->needs_cmd_parser = true;
838 }
839
840 /**
841 * intel_engine_cleanup_cmd_parser() - clean up cmd parser related fields
842 * @engine: the engine to clean up
843 *
844 * Releases any resources related to command parsing that may have been
845 * initialized for the specified engine.
846 */
847 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine)
848 {
849 if (!engine->needs_cmd_parser)
850 return;
851
852 fini_hash_table(engine);
853 }
854
855 static const struct drm_i915_cmd_descriptor*
856 find_cmd_in_table(struct intel_engine_cs *engine,
857 u32 cmd_header)
858 {
859 struct cmd_node *desc_node;
860
861 hash_for_each_possible(engine->cmd_hash, desc_node, node,
862 cmd_header & CMD_HASH_MASK) {
863 const struct drm_i915_cmd_descriptor *desc = desc_node->desc;
864 u32 masked_cmd = desc->cmd.mask & cmd_header;
865 u32 masked_value = desc->cmd.value & desc->cmd.mask;
866
867 if (masked_cmd == masked_value)
868 return desc;
869 }
870
871 return NULL;
872 }
873
874 /*
875 * Returns a pointer to a descriptor for the command specified by cmd_header.
876 *
877 * The caller must supply space for a default descriptor via the default_desc
878 * parameter. If no descriptor for the specified command exists in the engine's
879 * command parser tables, this function fills in default_desc based on the
880 * engine's default length encoding and returns default_desc.
881 */
882 static const struct drm_i915_cmd_descriptor*
883 find_cmd(struct intel_engine_cs *engine,
884 u32 cmd_header,
885 struct drm_i915_cmd_descriptor *default_desc)
886 {
887 const struct drm_i915_cmd_descriptor *desc;
888 u32 mask;
889
890 desc = find_cmd_in_table(engine, cmd_header);
891 if (desc)
892 return desc;
893
894 mask = engine->get_cmd_length_mask(cmd_header);
895 if (!mask)
896 return NULL;
897
898 BUG_ON(!default_desc);
899 default_desc->flags = CMD_DESC_SKIP;
900 default_desc->length.mask = mask;
901
902 return default_desc;
903 }
904
905 static const struct drm_i915_reg_descriptor *
906 find_reg(const struct drm_i915_reg_descriptor *table,
907 int count, u32 addr)
908 {
909 int i;
910
911 for (i = 0; i < count; i++) {
912 if (i915_mmio_reg_offset(table[i].addr) == addr)
913 return &table[i];
914 }
915
916 return NULL;
917 }
918
919 static const struct drm_i915_reg_descriptor *
920 find_reg_in_tables(const struct drm_i915_reg_table *tables,
921 int count, bool is_master, u32 addr)
922 {
923 int i;
924 const struct drm_i915_reg_table *table;
925 const struct drm_i915_reg_descriptor *reg;
926
927 for (i = 0; i < count; i++) {
928 table = &tables[i];
929 if (!table->master || is_master) {
930 reg = find_reg(table->regs, table->num_regs,
931 addr);
932 if (reg != NULL)
933 return reg;
934 }
935 }
936
937 return NULL;
938 }
939
940 static u32 *vmap_batch(struct drm_i915_gem_object *obj,
941 unsigned start, unsigned len)
942 {
943 int i;
944 void *addr = NULL;
945 struct sg_page_iter sg_iter;
946 int first_page = start >> PAGE_SHIFT;
947 int last_page = (len + start + 4095) >> PAGE_SHIFT;
948 int npages = last_page - first_page;
949 struct page **pages;
950
951 pages = drm_malloc_ab(npages, sizeof(*pages));
952 if (pages == NULL) {
953 DRM_DEBUG_DRIVER("Failed to get space for pages\n");
954 goto finish;
955 }
956
957 i = 0;
958 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, first_page) {
959 pages[i++] = sg_page_iter_page(&sg_iter);
960 if (i == npages)
961 break;
962 }
963
964 addr = vmap(pages, i, 0, PAGE_KERNEL);
965 if (addr == NULL) {
966 DRM_DEBUG_DRIVER("Failed to vmap pages\n");
967 goto finish;
968 }
969
970 finish:
971 if (pages)
972 drm_free_large(pages);
973 return (u32*)addr;
974 }
975
976 /* Returns a vmap'd pointer to dest_obj, which the caller must unmap */
977 static u32 *copy_batch(struct drm_i915_gem_object *dest_obj,
978 struct drm_i915_gem_object *src_obj,
979 u32 batch_start_offset,
980 u32 batch_len)
981 {
982 unsigned int needs_clflush;
983 void *src_base, *src;
984 void *dst = NULL;
985 int ret;
986
987 if (batch_len > dest_obj->base.size ||
988 batch_len + batch_start_offset > src_obj->base.size)
989 return ERR_PTR(-E2BIG);
990
991 if (WARN_ON(dest_obj->pages_pin_count == 0))
992 return ERR_PTR(-ENODEV);
993
994 ret = i915_gem_obj_prepare_shmem_read(src_obj, &needs_clflush);
995 if (ret) {
996 DRM_DEBUG_DRIVER("CMD: failed to prepare shadow batch\n");
997 return ERR_PTR(ret);
998 }
999
1000 src_base = vmap_batch(src_obj, batch_start_offset, batch_len);
1001 if (!src_base) {
1002 DRM_DEBUG_DRIVER("CMD: Failed to vmap batch\n");
1003 ret = -ENOMEM;
1004 goto unpin_src;
1005 }
1006
1007 ret = i915_gem_object_set_to_cpu_domain(dest_obj, true);
1008 if (ret) {
1009 DRM_DEBUG_DRIVER("CMD: Failed to set shadow batch to CPU\n");
1010 goto unmap_src;
1011 }
1012
1013 dst = vmap_batch(dest_obj, 0, batch_len);
1014 if (!dst) {
1015 DRM_DEBUG_DRIVER("CMD: Failed to vmap shadow batch\n");
1016 ret = -ENOMEM;
1017 goto unmap_src;
1018 }
1019
1020 src = src_base + offset_in_page(batch_start_offset);
1021 if (needs_clflush)
1022 drm_clflush_virt_range(src, batch_len);
1023
1024 memcpy(dst, src, batch_len);
1025
1026 unmap_src:
1027 vunmap(src_base);
1028 unpin_src:
1029 i915_gem_obj_finish_shmem_access(src_obj);
1030
1031 return ret ? ERR_PTR(ret) : dst;
1032 }
1033
1034 /**
1035 * intel_engine_needs_cmd_parser() - should a given engine use software
1036 * command parsing?
1037 * @engine: the engine in question
1038 *
1039 * Only certain platforms require software batch buffer command parsing, and
1040 * only when enabled via module parameter.
1041 *
1042 * Return: true if the engine requires software command parsing
1043 */
1044 bool intel_engine_needs_cmd_parser(struct intel_engine_cs *engine)
1045 {
1046 if (!engine->needs_cmd_parser)
1047 return false;
1048
1049 if (!USES_PPGTT(engine->i915))
1050 return false;
1051
1052 return (i915.enable_cmd_parser == 1);
1053 }
1054
1055 static bool check_cmd(const struct intel_engine_cs *engine,
1056 const struct drm_i915_cmd_descriptor *desc,
1057 const u32 *cmd, u32 length,
1058 const bool is_master,
1059 bool *oacontrol_set)
1060 {
1061 if (desc->flags & CMD_DESC_REJECT) {
1062 DRM_DEBUG_DRIVER("CMD: Rejected command: 0x%08X\n", *cmd);
1063 return false;
1064 }
1065
1066 if ((desc->flags & CMD_DESC_MASTER) && !is_master) {
1067 DRM_DEBUG_DRIVER("CMD: Rejected master-only command: 0x%08X\n",
1068 *cmd);
1069 return false;
1070 }
1071
1072 if (desc->flags & CMD_DESC_REGISTER) {
1073 /*
1074 * Get the distance between individual register offset
1075 * fields if the command can perform more than one
1076 * access at a time.
1077 */
1078 const u32 step = desc->reg.step ? desc->reg.step : length;
1079 u32 offset;
1080
1081 for (offset = desc->reg.offset; offset < length;
1082 offset += step) {
1083 const u32 reg_addr = cmd[offset] & desc->reg.mask;
1084 const struct drm_i915_reg_descriptor *reg =
1085 find_reg_in_tables(engine->reg_tables,
1086 engine->reg_table_count,
1087 is_master,
1088 reg_addr);
1089
1090 if (!reg) {
1091 DRM_DEBUG_DRIVER("CMD: Rejected register 0x%08X in command: 0x%08X (exec_id=%d)\n",
1092 reg_addr, *cmd, engine->exec_id);
1093 return false;
1094 }
1095
1096 /*
1097 * OACONTROL requires some special handling for
1098 * writes. We want to make sure that any batch which
1099 * enables OA also disables it before the end of the
1100 * batch. The goal is to prevent one process from
1101 * snooping on the perf data from another process. To do
1102 * that, we need to check the value that will be written
1103 * to the register. Hence, limit OACONTROL writes to
1104 * only MI_LOAD_REGISTER_IMM commands.
1105 */
1106 if (reg_addr == i915_mmio_reg_offset(OACONTROL)) {
1107 if (desc->cmd.value == MI_LOAD_REGISTER_MEM) {
1108 DRM_DEBUG_DRIVER("CMD: Rejected LRM to OACONTROL\n");
1109 return false;
1110 }
1111
1112 if (desc->cmd.value == MI_LOAD_REGISTER_REG) {
1113 DRM_DEBUG_DRIVER("CMD: Rejected LRR to OACONTROL\n");
1114 return false;
1115 }
1116
1117 if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1))
1118 *oacontrol_set = (cmd[offset + 1] != 0);
1119 }
1120
1121 /*
1122 * Check the value written to the register against the
1123 * allowed mask/value pair given in the whitelist entry.
1124 */
1125 if (reg->mask) {
1126 if (desc->cmd.value == MI_LOAD_REGISTER_MEM) {
1127 DRM_DEBUG_DRIVER("CMD: Rejected LRM to masked register 0x%08X\n",
1128 reg_addr);
1129 return false;
1130 }
1131
1132 if (desc->cmd.value == MI_LOAD_REGISTER_REG) {
1133 DRM_DEBUG_DRIVER("CMD: Rejected LRR to masked register 0x%08X\n",
1134 reg_addr);
1135 return false;
1136 }
1137
1138 if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1) &&
1139 (offset + 2 > length ||
1140 (cmd[offset + 1] & reg->mask) != reg->value)) {
1141 DRM_DEBUG_DRIVER("CMD: Rejected LRI to masked register 0x%08X\n",
1142 reg_addr);
1143 return false;
1144 }
1145 }
1146 }
1147 }
1148
1149 if (desc->flags & CMD_DESC_BITMASK) {
1150 int i;
1151
1152 for (i = 0; i < MAX_CMD_DESC_BITMASKS; i++) {
1153 u32 dword;
1154
1155 if (desc->bits[i].mask == 0)
1156 break;
1157
1158 if (desc->bits[i].condition_mask != 0) {
1159 u32 offset =
1160 desc->bits[i].condition_offset;
1161 u32 condition = cmd[offset] &
1162 desc->bits[i].condition_mask;
1163
1164 if (condition == 0)
1165 continue;
1166 }
1167
1168 dword = cmd[desc->bits[i].offset] &
1169 desc->bits[i].mask;
1170
1171 if (dword != desc->bits[i].expected) {
1172 DRM_DEBUG_DRIVER("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (exec_id=%d)\n",
1173 *cmd,
1174 desc->bits[i].mask,
1175 desc->bits[i].expected,
1176 dword, engine->exec_id);
1177 return false;
1178 }
1179 }
1180 }
1181
1182 return true;
1183 }
1184
1185 #define LENGTH_BIAS 2
1186
1187 /**
1188 * i915_parse_cmds() - parse a submitted batch buffer for privilege violations
1189 * @engine: the engine on which the batch is to execute
1190 * @batch_obj: the batch buffer in question
1191 * @shadow_batch_obj: copy of the batch buffer in question
1192 * @batch_start_offset: byte offset in the batch at which execution starts
1193 * @batch_len: length of the commands in batch_obj
1194 * @is_master: is the submitting process the drm master?
1195 *
1196 * Parses the specified batch buffer looking for privilege violations as
1197 * described in the overview.
1198 *
1199 * Return: non-zero if the parser finds violations or otherwise fails; -EACCES
1200 * if the batch appears legal but should use hardware parsing
1201 */
1202 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
1203 struct drm_i915_gem_object *batch_obj,
1204 struct drm_i915_gem_object *shadow_batch_obj,
1205 u32 batch_start_offset,
1206 u32 batch_len,
1207 bool is_master)
1208 {
1209 u32 *cmd, *batch_base, *batch_end;
1210 struct drm_i915_cmd_descriptor default_desc = { 0 };
1211 bool oacontrol_set = false; /* OACONTROL tracking. See check_cmd() */
1212 int ret = 0;
1213
1214 batch_base = copy_batch(shadow_batch_obj, batch_obj,
1215 batch_start_offset, batch_len);
1216 if (IS_ERR(batch_base)) {
1217 DRM_DEBUG_DRIVER("CMD: Failed to copy batch\n");
1218 return PTR_ERR(batch_base);
1219 }
1220
1221 /*
1222 * We use the batch length as size because the shadow object is as
1223 * large or larger and copy_batch() will write MI_NOPs to the extra
1224 * space. Parsing should be faster in some cases this way.
1225 */
1226 batch_end = batch_base + (batch_len / sizeof(*batch_end));
1227
1228 cmd = batch_base;
1229 while (cmd < batch_end) {
1230 const struct drm_i915_cmd_descriptor *desc;
1231 u32 length;
1232
1233 if (*cmd == MI_BATCH_BUFFER_END)
1234 break;
1235
1236 desc = find_cmd(engine, *cmd, &default_desc);
1237 if (!desc) {
1238 DRM_DEBUG_DRIVER("CMD: Unrecognized command: 0x%08X\n",
1239 *cmd);
1240 ret = -EINVAL;
1241 break;
1242 }
1243
1244 /*
1245 * If the batch buffer contains a chained batch, return an
1246 * error that tells the caller to abort and dispatch the
1247 * workload as a non-secure batch.
1248 */
1249 if (desc->cmd.value == MI_BATCH_BUFFER_START) {
1250 ret = -EACCES;
1251 break;
1252 }
1253
1254 if (desc->flags & CMD_DESC_FIXED)
1255 length = desc->length.fixed;
1256 else
1257 length = ((*cmd & desc->length.mask) + LENGTH_BIAS);
1258
1259 if ((batch_end - cmd) < length) {
1260 DRM_DEBUG_DRIVER("CMD: Command length exceeds batch length: 0x%08X length=%u batchlen=%td\n",
1261 *cmd,
1262 length,
1263 batch_end - cmd);
1264 ret = -EINVAL;
1265 break;
1266 }
1267
1268 if (!check_cmd(engine, desc, cmd, length, is_master,
1269 &oacontrol_set)) {
1270 ret = -EINVAL;
1271 break;
1272 }
1273
1274 cmd += length;
1275 }
1276
1277 if (oacontrol_set) {
1278 DRM_DEBUG_DRIVER("CMD: batch set OACONTROL but did not clear it\n");
1279 ret = -EINVAL;
1280 }
1281
1282 if (cmd >= batch_end) {
1283 DRM_DEBUG_DRIVER("CMD: Got to the end of the buffer w/o a BBE cmd!\n");
1284 ret = -EINVAL;
1285 }
1286
1287 vunmap(batch_base);
1288
1289 return ret;
1290 }
1291
1292 /**
1293 * i915_cmd_parser_get_version() - get the cmd parser version number
1294 * @dev_priv: i915 device private
1295 *
1296 * The cmd parser maintains a simple increasing integer version number suitable
1297 * for passing to userspace clients to determine what operations are permitted.
1298 *
1299 * Return: the current version number of the cmd parser
1300 */
1301 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv)
1302 {
1303 struct intel_engine_cs *engine;
1304 bool active = false;
1305
1306 /* If the command parser is not enabled, report 0 - unsupported */
1307 for_each_engine(engine, dev_priv) {
1308 if (intel_engine_needs_cmd_parser(engine)) {
1309 active = true;
1310 break;
1311 }
1312 }
1313 if (!active)
1314 return 0;
1315
1316 /*
1317 * Command parser version history
1318 *
1319 * 1. Initial version. Checks batches and reports violations, but leaves
1320 * hardware parsing enabled (so does not allow new use cases).
1321 * 2. Allow access to the MI_PREDICATE_SRC0 and
1322 * MI_PREDICATE_SRC1 registers.
1323 * 3. Allow access to the GPGPU_THREADS_DISPATCHED register.
1324 * 4. L3 atomic chicken bits of HSW_SCRATCH1 and HSW_ROW_CHICKEN3.
1325 * 5. GPGPU dispatch compute indirect registers.
1326 * 6. TIMESTAMP register and Haswell CS GPR registers
1327 * 7. Allow MI_LOAD_REGISTER_REG between whitelisted registers.
1328 */
1329 return 7;
1330 }
Linux kernel - Deliverables
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