drivers/gpu/drm/i915/i915_cmd_parser.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Brad Volkin <bradley.d.volkin@intel.com>
  25  *
  26  */
  27
  28 #include "i915_drv.h"
  29
  30 /**
  31  * DOC: i915 batch buffer command parser
  32  *
  33  * Motivation:
  34  * Certain OpenGL features (e.g. transform feedback, performance monitoring)
  35  * require userspace code to submit batches containing commands such as
  36  * MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some
  37  * generations of the hardware will noop these commands in "unsecure" batches
  38  * (which includes all userspace batches submitted via i915) even though the
  39  * commands may be safe and represent the intended programming model of the
  40  * device.
  41  *
  42  * The software command parser is similar in operation to the command parsing
  43  * done in hardware for unsecure batches. However, the software parser allows
  44  * some operations that would be noop'd by hardware, if the parser determines
  45  * the operation is safe, and submits the batch as "secure" to prevent hardware
  46  * parsing.
  47  *
  48  * Threats:
  49  * At a high level, the hardware (and software) checks attempt to prevent
  50  * granting userspace undue privileges. There are three categories of privilege.
  51  *
  52  * First, commands which are explicitly defined as privileged or which should
  53  * only be used by the kernel driver. The parser generally rejects such
  54  * commands, though it may allow some from the drm master process.
  55  *
  56  * Second, commands which access registers. To support correct/enhanced
  57  * userspace functionality, particularly certain OpenGL extensions, the parser
  58  * provides a whitelist of registers which userspace may safely access (for both
  59  * normal and drm master processes).
  60  *
  61  * Third, commands which access privileged memory (i.e. GGTT, HWS page, etc).
  62  * The parser always rejects such commands.
  63  *
  64  * The majority of the problematic commands fall in the MI_* range, with only a
  65  * few specific commands on each ring (e.g. PIPE_CONTROL and MI_FLUSH_DW).
  66  *
  67  * Implementation:
  68  * Each ring maintains tables of commands and registers which the parser uses in
  69  * scanning batch buffers submitted to that ring.
  70  *
  71  * Since the set of commands that the parser must check for is significantly
  72  * smaller than the number of commands supported, the parser tables contain only
  73  * those commands required by the parser. This generally works because command
  74  * opcode ranges have standard command length encodings. So for commands that
  75  * the parser does not need to check, it can easily skip them. This is
  76  * implementated via a per-ring length decoding vfunc.
  77  *
  78  * Unfortunately, there are a number of commands that do not follow the standard
  79  * length encoding for their opcode range, primarily amongst the MI_* commands.
  80  * To handle this, the parser provides a way to define explicit "skip" entries
  81  * in the per-ring command tables.
  82  *
  83  * Other command table entries map fairly directly to high level categories
  84  * mentioned above: rejected, master-only, register whitelist. The parser
  85  * implements a number of checks, including the privileged memory checks, via a
  86  * general bitmasking mechanism.
  87  */
  88
  89 #define STD_MI_OPCODE_MASK  0xFF800000
  90 #define STD_3D_OPCODE_MASK  0xFFFF0000
  91 #define STD_2D_OPCODE_MASK  0xFFC00000
  92 #define STD_MFX_OPCODE_MASK 0xFFFF0000
  93
  94 #define CMD(op, opm, f, lm, fl, ...)                            \
  95         {                                                       \
  96                 .flags = (fl) | ((f) ? CMD_DESC_FIXED : 0),     \
  97                 .cmd = { (op), (opm) },                         \
  98                 .length = { (lm) },                             \
  99                 __VA_ARGS__                                     \
 100         }
 101
 102 /* Convenience macros to compress the tables */
 103 #define SMI STD_MI_OPCODE_MASK
 104 #define S3D STD_3D_OPCODE_MASK
 105 #define S2D STD_2D_OPCODE_MASK
 106 #define SMFX STD_MFX_OPCODE_MASK
 107 #define F true
 108 #define S CMD_DESC_SKIP
 109 #define R CMD_DESC_REJECT
 110 #define W CMD_DESC_REGISTER
 111 #define B CMD_DESC_BITMASK
 112 #define M CMD_DESC_MASTER
 113
 114 /*            Command                          Mask   Fixed Len   Action
 115               ---------------------------------------------------------- */
 116 static const struct drm_i915_cmd_descriptor common_cmds[] = {
 117         CMD(  MI_NOOP,                          SMI,    F,  1,      S  ),
 118         CMD(  MI_USER_INTERRUPT,                SMI,    F,  1,      S  ),
 119         CMD(  MI_WAIT_FOR_EVENT,                SMI,    F,  1,      M  ),
 120         CMD(  MI_ARB_CHECK,                     SMI,    F,  1,      S  ),
 121         CMD(  MI_REPORT_HEAD,                   SMI,    F,  1,      S  ),
 122         CMD(  MI_SUSPEND_FLUSH,                 SMI,    F,  1,      S  ),
 123         CMD(  MI_SEMAPHORE_MBOX,                SMI,   !F,  0xFF,   R  ),
 124         CMD(  MI_STORE_DWORD_INDEX,             SMI,   !F,  0xFF,   R  ),
 125         CMD(  MI_LOAD_REGISTER_IMM(1),          SMI,   !F,  0xFF,   R  ),
 126         CMD(  MI_STORE_REGISTER_MEM(1),         SMI,   !F,  0xFF,   R  ),
 127         CMD(  MI_LOAD_REGISTER_MEM,             SMI,   !F,  0xFF,   R  ),
 128         CMD(  MI_BATCH_BUFFER_START,            SMI,   !F,  0xFF,   S  ),
 129 };
 130
 131 static const struct drm_i915_cmd_descriptor render_cmds[] = {
 132         CMD(  MI_FLUSH,                         SMI,    F,  1,      S  ),
 133         CMD(  MI_ARB_ON_OFF,                    SMI,    F,  1,      R  ),
 134         CMD(  MI_PREDICATE,                     SMI,    F,  1,      S  ),
 135         CMD(  MI_TOPOLOGY_FILTER,               SMI,    F,  1,      S  ),
 136         CMD(  MI_DISPLAY_FLIP,                  SMI,   !F,  0xFF,   R  ),
 137         CMD(  MI_SET_CONTEXT,                   SMI,   !F,  0xFF,   R  ),
 138         CMD(  MI_URB_CLEAR,                     SMI,   !F,  0xFF,   S  ),
 139         CMD(  MI_UPDATE_GTT,                    SMI,   !F,  0xFF,   R  ),
 140         CMD(  MI_CLFLUSH,                       SMI,   !F,  0x3FF,  S  ),
 141         CMD(  MI_CONDITIONAL_BATCH_BUFFER_END,  SMI,   !F,  0xFF,   S  ),
 142         CMD(  GFX_OP_3DSTATE_VF_STATISTICS,     S3D,    F,  1,      S  ),
 143         CMD(  PIPELINE_SELECT,                  S3D,    F,  1,      S  ),
 144         CMD(  GPGPU_OBJECT,                     S3D,   !F,  0xFF,   S  ),
 145         CMD(  GPGPU_WALKER,                     S3D,   !F,  0xFF,   S  ),
 146         CMD(  GFX_OP_3DSTATE_SO_DECL_LIST,      S3D,   !F,  0x1FF,  S  ),
 147 };
 148
 149 static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = {
 150         CMD(  MI_SET_PREDICATE,                 SMI,    F,  1,      S  ),
 151         CMD(  MI_RS_CONTROL,                    SMI,    F,  1,      S  ),
 152         CMD(  MI_URB_ATOMIC_ALLOC,              SMI,    F,  1,      S  ),
 153         CMD(  MI_RS_CONTEXT,                    SMI,    F,  1,      S  ),
 154         CMD(  MI_LOAD_SCAN_LINES_INCL,          SMI,   !F,  0x3F,   M  ),
 155         CMD(  MI_LOAD_SCAN_LINES_EXCL,          SMI,   !F,  0x3F,   R  ),
 156         CMD(  MI_LOAD_REGISTER_REG,             SMI,   !F,  0xFF,   R  ),
 157         CMD(  MI_RS_STORE_DATA_IMM,             SMI,   !F,  0xFF,   S  ),
 158         CMD(  MI_LOAD_URB_MEM,                  SMI,   !F,  0xFF,   S  ),
 159         CMD(  MI_STORE_URB_MEM,                 SMI,   !F,  0xFF,   S  ),
 160         CMD(  GFX_OP_3DSTATE_DX9_CONSTANTF_VS,  S3D,   !F,  0x7FF,  S  ),
 161         CMD(  GFX_OP_3DSTATE_DX9_CONSTANTF_PS,  S3D,   !F,  0x7FF,  S  ),
 162
 163         CMD(  GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS,  S3D,   !F,  0x1FF,  S  ),
 164         CMD(  GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS,  S3D,   !F,  0x1FF,  S  ),
 165         CMD(  GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS,  S3D,   !F,  0x1FF,  S  ),
 166         CMD(  GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS,  S3D,   !F,  0x1FF,  S  ),
 167         CMD(  GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS,  S3D,   !F,  0x1FF,  S  ),
 168 };
 169
 170 static const struct drm_i915_cmd_descriptor video_cmds[] = {
 171         CMD(  MI_ARB_ON_OFF,                    SMI,    F,  1,      R  ),
 172         CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0xFF,   S  ),
 173         CMD(  MI_UPDATE_GTT,                    SMI,   !F,  0x3F,   R  ),
 174         CMD(  MI_CONDITIONAL_BATCH_BUFFER_END,  SMI,   !F,  0xFF,   S  ),
 175         /*
 176          * MFX_WAIT doesn't fit the way we handle length for most commands.
 177          * It has a length field but it uses a non-standard length bias.
 178          * It is always 1 dword though, so just treat it as fixed length.
 179          */
 180         CMD(  MFX_WAIT,                         SMFX,   F,  1,      S  ),
 181 };
 182
 183 static const struct drm_i915_cmd_descriptor vecs_cmds[] = {
 184         CMD(  MI_ARB_ON_OFF,                    SMI,    F,  1,      R  ),
 185         CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0xFF,   S  ),
 186         CMD(  MI_UPDATE_GTT,                    SMI,   !F,  0x3F,   R  ),
 187         CMD(  MI_CONDITIONAL_BATCH_BUFFER_END,  SMI,   !F,  0xFF,   S  ),
 188 };
 189
 190 static const struct drm_i915_cmd_descriptor blt_cmds[] = {
 191         CMD(  MI_DISPLAY_FLIP,                  SMI,   !F,  0xFF,   R  ),
 192         CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0x3FF,  S  ),
 193         CMD(  MI_UPDATE_GTT,                    SMI,   !F,  0x3F,   R  ),
 194         CMD(  COLOR_BLT,                        S2D,   !F,  0x3F,   S  ),
 195         CMD(  SRC_COPY_BLT,                     S2D,   !F,  0x3F,   S  ),
 196 };
 197
 198 static const struct drm_i915_cmd_descriptor hsw_blt_cmds[] = {
 199         CMD(  MI_LOAD_SCAN_LINES_INCL,          SMI,   !F,  0x3F,   M  ),
 200         CMD(  MI_LOAD_SCAN_LINES_EXCL,          SMI,   !F,  0x3F,   R  ),
 201 };
 202
 203 #undef CMD
 204 #undef SMI
 205 #undef S3D
 206 #undef S2D
 207 #undef SMFX
 208 #undef F
 209 #undef S
 210 #undef R
 211 #undef W
 212 #undef B
 213 #undef M
 214
 215 static const struct drm_i915_cmd_table gen7_render_cmds[] = {
 216         { common_cmds, ARRAY_SIZE(common_cmds) },
 217         { render_cmds, ARRAY_SIZE(render_cmds) },
 218 };
 219
 220 static const struct drm_i915_cmd_table hsw_render_ring_cmds[] = {
 221         { common_cmds, ARRAY_SIZE(common_cmds) },
 222         { render_cmds, ARRAY_SIZE(render_cmds) },
 223         { hsw_render_cmds, ARRAY_SIZE(hsw_render_cmds) },
 224 };
 225
 226 static const struct drm_i915_cmd_table gen7_video_cmds[] = {
 227         { common_cmds, ARRAY_SIZE(common_cmds) },
 228         { video_cmds, ARRAY_SIZE(video_cmds) },
 229 };
 230
 231 static const struct drm_i915_cmd_table hsw_vebox_cmds[] = {
 232         { common_cmds, ARRAY_SIZE(common_cmds) },
 233         { vecs_cmds, ARRAY_SIZE(vecs_cmds) },
 234 };
 235
 236 static const struct drm_i915_cmd_table gen7_blt_cmds[] = {
 237         { common_cmds, ARRAY_SIZE(common_cmds) },
 238         { blt_cmds, ARRAY_SIZE(blt_cmds) },
 239 };
 240
 241 static const struct drm_i915_cmd_table hsw_blt_ring_cmds[] = {
 242         { common_cmds, ARRAY_SIZE(common_cmds) },
 243         { blt_cmds, ARRAY_SIZE(blt_cmds) },
 244         { hsw_blt_cmds, ARRAY_SIZE(hsw_blt_cmds) },
 245 };
 246
 247 /*
 248  * Register whitelists, sorted by increasing register offset.
 249  *
 250  * Some registers that userspace accesses are 64 bits. The register
 251  * access commands only allow 32-bit accesses. Hence, we have to include
 252  * entries for both halves of the 64-bit registers.
 253  */
 254
 255 /* Convenience macro for adding 64-bit registers */
 256 #define REG64(addr) (addr), (addr + sizeof(u32))
 257
 258 static const u32 gen7_render_regs[] = {
 259         REG64(HS_INVOCATION_COUNT),
 260         REG64(DS_INVOCATION_COUNT),
 261         REG64(IA_VERTICES_COUNT),
 262         REG64(IA_PRIMITIVES_COUNT),
 263         REG64(VS_INVOCATION_COUNT),
 264         REG64(GS_INVOCATION_COUNT),
 265         REG64(GS_PRIMITIVES_COUNT),
 266         REG64(CL_INVOCATION_COUNT),
 267         REG64(CL_PRIMITIVES_COUNT),
 268         REG64(PS_INVOCATION_COUNT),
 269         REG64(PS_DEPTH_COUNT),
 270         REG64(GEN7_SO_NUM_PRIMS_WRITTEN(0)),
 271         REG64(GEN7_SO_NUM_PRIMS_WRITTEN(1)),
 272         REG64(GEN7_SO_NUM_PRIMS_WRITTEN(2)),
 273         REG64(GEN7_SO_NUM_PRIMS_WRITTEN(3)),
 274         GEN7_SO_WRITE_OFFSET(0),
 275         GEN7_SO_WRITE_OFFSET(1),
 276         GEN7_SO_WRITE_OFFSET(2),
 277         GEN7_SO_WRITE_OFFSET(3),
 278 };
 279
 280 static const u32 gen7_blt_regs[] = {
 281         BCS_SWCTRL,
 282 };
 283
 284 static const u32 ivb_master_regs[] = {
 285         FORCEWAKE_MT,
 286         DERRMR,
 287         GEN7_PIPE_DE_LOAD_SL(PIPE_A),
 288         GEN7_PIPE_DE_LOAD_SL(PIPE_B),
 289         GEN7_PIPE_DE_LOAD_SL(PIPE_C),
 290 };
 291
 292 static const u32 hsw_master_regs[] = {
 293         FORCEWAKE_MT,
 294         DERRMR,
 295 };
 296
 297 #undef REG64
 298
 299 static u32 gen7_render_get_cmd_length_mask(u32 cmd_header)
 300 {
 301         u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT;
 302         u32 subclient =
 303                 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT;
 304
 305         if (client == INSTR_MI_CLIENT)
 306                 return 0x3F;
 307         else if (client == INSTR_RC_CLIENT) {
 308                 if (subclient == INSTR_MEDIA_SUBCLIENT)
 309                         return 0xFFFF;
 310                 else
 311                         return 0xFF;
 312         }
 313
 314         DRM_DEBUG_DRIVER("CMD: Abnormal rcs cmd length! 0x%08X\n", cmd_header);
 315         return 0;
 316 }
 317
 318 static u32 gen7_bsd_get_cmd_length_mask(u32 cmd_header)
 319 {
 320         u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT;
 321         u32 subclient =
 322                 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT;
 323
 324         if (client == INSTR_MI_CLIENT)
 325                 return 0x3F;
 326         else if (client == INSTR_RC_CLIENT) {
 327                 if (subclient == INSTR_MEDIA_SUBCLIENT)
 328                         return 0xFFF;
 329                 else
 330                         return 0xFF;
 331         }
 332
 333         DRM_DEBUG_DRIVER("CMD: Abnormal bsd cmd length! 0x%08X\n", cmd_header);
 334         return 0;
 335 }
 336
 337 static u32 gen7_blt_get_cmd_length_mask(u32 cmd_header)
 338 {
 339         u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT;
 340
 341         if (client == INSTR_MI_CLIENT)
 342                 return 0x3F;
 343         else if (client == INSTR_BC_CLIENT)
 344                 return 0xFF;
 345
 346         DRM_DEBUG_DRIVER("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header);
 347         return 0;
 348 }
 349
 350 static void validate_cmds_sorted(struct intel_ring_buffer *ring)
 351 {
 352         int i;
 353
 354         if (!ring->cmd_tables || ring->cmd_table_count == 0)
 355                 return;
 356
 357         for (i = 0; i < ring->cmd_table_count; i++) {
 358                 const struct drm_i915_cmd_table *table = &ring->cmd_tables[i];
 359                 u32 previous = 0;
 360                 int j;
 361
 362                 for (j = 0; j < table->count; j++) {
 363                         const struct drm_i915_cmd_descriptor *desc =
 364                                 &table->table[i];
 365                         u32 curr = desc->cmd.value & desc->cmd.mask;
 366
 367                         if (curr < previous)
 368                                 DRM_ERROR("CMD: table not sorted ring=%d table=%d entry=%d cmd=0x%08X prev=0x%08X\n",
 369                                           ring->id, i, j, curr, previous);
 370
 371                         previous = curr;
 372                 }
 373         }
 374 }
 375
 376 static void check_sorted(int ring_id, const u32 *reg_table, int reg_count)
 377 {
 378         int i;
 379         u32 previous = 0;
 380
 381         for (i = 0; i < reg_count; i++) {
 382                 u32 curr = reg_table[i];
 383
 384                 if (curr < previous)
 385                         DRM_ERROR("CMD: table not sorted ring=%d entry=%d reg=0x%08X prev=0x%08X\n",
 386                                   ring_id, i, curr, previous);
 387
 388                 previous = curr;
 389         }
 390 }
 391
 392 static void validate_regs_sorted(struct intel_ring_buffer *ring)
 393 {
 394         check_sorted(ring->id, ring->reg_table, ring->reg_count);
 395         check_sorted(ring->id, ring->master_reg_table, ring->master_reg_count);
 396 }
 397
 398 /**
 399  * i915_cmd_parser_init_ring() - set cmd parser related fields for a ringbuffer
 400  * @ring: the ringbuffer to initialize
 401  *
 402  * Optionally initializes fields related to batch buffer command parsing in the
 403  * struct intel_ring_buffer based on whether the platform requires software
 404  * command parsing.
 405  */
 406 void i915_cmd_parser_init_ring(struct intel_ring_buffer *ring)
 407 {
 408         if (!IS_GEN7(ring->dev))
 409                 return;
 410
 411         switch (ring->id) {
 412         case RCS:
 413                 if (IS_HASWELL(ring->dev)) {
 414                         ring->cmd_tables = hsw_render_ring_cmds;
 415                         ring->cmd_table_count =
 416                                 ARRAY_SIZE(hsw_render_ring_cmds);
 417                 } else {
 418                         ring->cmd_tables = gen7_render_cmds;
 419                         ring->cmd_table_count = ARRAY_SIZE(gen7_render_cmds);
 420                 }
 421
 422                 ring->reg_table = gen7_render_regs;
 423                 ring->reg_count = ARRAY_SIZE(gen7_render_regs);
 424
 425                 if (IS_HASWELL(ring->dev)) {
 426                         ring->master_reg_table = hsw_master_regs;
 427                         ring->master_reg_count = ARRAY_SIZE(hsw_master_regs);
 428                 } else {
 429                         ring->master_reg_table = ivb_master_regs;
 430                         ring->master_reg_count = ARRAY_SIZE(ivb_master_regs);
 431                 }
 432
 433                 ring->get_cmd_length_mask = gen7_render_get_cmd_length_mask;
 434                 break;
 435         case VCS:
 436                 ring->cmd_tables = gen7_video_cmds;
 437                 ring->cmd_table_count = ARRAY_SIZE(gen7_video_cmds);
 438                 ring->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
 439                 break;
 440         case BCS:
 441                 if (IS_HASWELL(ring->dev)) {
 442                         ring->cmd_tables = hsw_blt_ring_cmds;
 443                         ring->cmd_table_count = ARRAY_SIZE(hsw_blt_ring_cmds);
 444                 } else {
 445                         ring->cmd_tables = gen7_blt_cmds;
 446                         ring->cmd_table_count = ARRAY_SIZE(gen7_blt_cmds);
 447                 }
 448
 449                 ring->reg_table = gen7_blt_regs;
 450                 ring->reg_count = ARRAY_SIZE(gen7_blt_regs);
 451
 452                 if (IS_HASWELL(ring->dev)) {
 453                         ring->master_reg_table = hsw_master_regs;
 454                         ring->master_reg_count = ARRAY_SIZE(hsw_master_regs);
 455                 } else {
 456                         ring->master_reg_table = ivb_master_regs;
 457                         ring->master_reg_count = ARRAY_SIZE(ivb_master_regs);
 458                 }
 459
 460                 ring->get_cmd_length_mask = gen7_blt_get_cmd_length_mask;
 461                 break;
 462         case VECS:
 463                 ring->cmd_tables = hsw_vebox_cmds;
 464                 ring->cmd_table_count = ARRAY_SIZE(hsw_vebox_cmds);
 465                 /* VECS can use the same length_mask function as VCS */
 466                 ring->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
 467                 break;
 468         default:
 469                 DRM_ERROR("CMD: cmd_parser_init with unknown ring: %d\n",
 470                           ring->id);
 471                 BUG();
 472         }
 473
 474         validate_cmds_sorted(ring);
 475         validate_regs_sorted(ring);
 476 }
 477
 478 static const struct drm_i915_cmd_descriptor*
 479 find_cmd_in_table(const struct drm_i915_cmd_table *table,
 480                   u32 cmd_header)
 481 {
 482         int i;
 483
 484         for (i = 0; i < table->count; i++) {
 485                 const struct drm_i915_cmd_descriptor *desc = &table->table[i];
 486                 u32 masked_cmd = desc->cmd.mask & cmd_header;
 487                 u32 masked_value = desc->cmd.value & desc->cmd.mask;
 488
 489                 if (masked_cmd == masked_value)
 490                         return desc;
 491         }
 492
 493         return NULL;
 494 }
 495
 496 /*
 497  * Returns a pointer to a descriptor for the command specified by cmd_header.
 498  *
 499  * The caller must supply space for a default descriptor via the default_desc
 500  * parameter. If no descriptor for the specified command exists in the ring's
 501  * command parser tables, this function fills in default_desc based on the
 502  * ring's default length encoding and returns default_desc.
 503  */
 504 static const struct drm_i915_cmd_descriptor*
 505 find_cmd(struct intel_ring_buffer *ring,
 506          u32 cmd_header,
 507          struct drm_i915_cmd_descriptor *default_desc)
 508 {
 509         u32 mask;
 510         int i;
 511
 512         for (i = 0; i < ring->cmd_table_count; i++) {
 513                 const struct drm_i915_cmd_descriptor *desc;
 514
 515                 desc = find_cmd_in_table(&ring->cmd_tables[i], cmd_header);
 516                 if (desc)
 517                         return desc;
 518         }
 519
 520         mask = ring->get_cmd_length_mask(cmd_header);
 521         if (!mask)
 522                 return NULL;
 523
 524         BUG_ON(!default_desc);
 525         default_desc->flags = CMD_DESC_SKIP;
 526         default_desc->length.mask = mask;
 527
 528         return default_desc;
 529 }
 530
 531 static bool valid_reg(const u32 *table, int count, u32 addr)
 532 {
 533         if (table && count != 0) {
 534                 int i;
 535
 536                 for (i = 0; i < count; i++) {
 537                         if (table[i] == addr)
 538                                 return true;
 539                 }
 540         }
 541
 542         return false;
 543 }
 544
 545 static u32 *vmap_batch(struct drm_i915_gem_object *obj)
 546 {
 547         int i;
 548         void *addr = NULL;
 549         struct sg_page_iter sg_iter;
 550         struct page **pages;
 551
 552         pages = drm_malloc_ab(obj->base.size >> PAGE_SHIFT, sizeof(*pages));
 553         if (pages == NULL) {
 554                 DRM_DEBUG_DRIVER("Failed to get space for pages\n");
 555                 goto finish;
 556         }
 557
 558         i = 0;
 559         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
 560                 pages[i] = sg_page_iter_page(&sg_iter);
 561                 i++;
 562         }
 563
 564         addr = vmap(pages, i, 0, PAGE_KERNEL);
 565         if (addr == NULL) {
 566                 DRM_DEBUG_DRIVER("Failed to vmap pages\n");
 567                 goto finish;
 568         }
 569
 570 finish:
 571         if (pages)
 572                 drm_free_large(pages);
 573         return (u32*)addr;
 574 }
 575
 576 /**
 577  * i915_needs_cmd_parser() - should a given ring use software command parsing?
 578  * @ring: the ring in question
 579  *
 580  * Only certain platforms require software batch buffer command parsing, and
 581  * only when enabled via module paramter.
 582  *
 583  * Return: true if the ring requires software command parsing
 584  */
 585 bool i915_needs_cmd_parser(struct intel_ring_buffer *ring)
 586 {
 587         /* No command tables indicates a platform without parsing */
 588         if (!ring->cmd_tables)
 589                 return false;
 590
 591         return (i915.enable_cmd_parser == 1);
 592 }
 593
 594 #define LENGTH_BIAS 2
 595
 596 /**
 597  * i915_parse_cmds() - parse a submitted batch buffer for privilege violations
 598  * @ring: the ring on which the batch is to execute
 599  * @batch_obj: the batch buffer in question
 600  * @batch_start_offset: byte offset in the batch at which execution starts
 601  * @is_master: is the submitting process the drm master?
 602  *
 603  * Parses the specified batch buffer looking for privilege violations as
 604  * described in the overview.
 605  *
 606  * Return: non-zero if the parser finds violations or otherwise fails
 607  */
 608 int i915_parse_cmds(struct intel_ring_buffer *ring,
 609                     struct drm_i915_gem_object *batch_obj,
 610                     u32 batch_start_offset,
 611                     bool is_master)
 612 {
 613         int ret = 0;
 614         u32 *cmd, *batch_base, *batch_end;
 615         struct drm_i915_cmd_descriptor default_desc = { 0 };
 616         int needs_clflush = 0;
 617
 618         ret = i915_gem_obj_prepare_shmem_read(batch_obj, &needs_clflush);
 619         if (ret) {
 620                 DRM_DEBUG_DRIVER("CMD: failed to prep read\n");
 621                 return ret;
 622         }
 623
 624         batch_base = vmap_batch(batch_obj);
 625         if (!batch_base) {
 626                 DRM_DEBUG_DRIVER("CMD: Failed to vmap batch\n");
 627                 i915_gem_object_unpin_pages(batch_obj);
 628                 return -ENOMEM;
 629         }
 630
 631         if (needs_clflush)
 632                 drm_clflush_virt_range((char *)batch_base, batch_obj->base.size);
 633
 634         cmd = batch_base + (batch_start_offset / sizeof(*cmd));
 635         batch_end = cmd + (batch_obj->base.size / sizeof(*batch_end));
 636
 637         while (cmd < batch_end) {
 638                 const struct drm_i915_cmd_descriptor *desc;
 639                 u32 length;
 640
 641                 if (*cmd == MI_BATCH_BUFFER_END)
 642                         break;
 643
 644                 desc = find_cmd(ring, *cmd, &default_desc);
 645                 if (!desc) {
 646                         DRM_DEBUG_DRIVER("CMD: Unrecognized command: 0x%08X\n",
 647                                          *cmd);
 648                         ret = -EINVAL;
 649                         break;
 650                 }
 651
 652                 if (desc->flags & CMD_DESC_FIXED)
 653                         length = desc->length.fixed;
 654                 else
 655                         length = ((*cmd & desc->length.mask) + LENGTH_BIAS);
 656
 657                 if ((batch_end - cmd) < length) {
 658                         DRM_DEBUG_DRIVER("CMD: Command length exceeds batch length: 0x%08X length=%d batchlen=%td\n",
 659                                          *cmd,
 660                                          length,
 661                                          batch_end - cmd);
 662                         ret = -EINVAL;
 663                         break;
 664                 }
 665
 666                 if (desc->flags & CMD_DESC_REJECT) {
 667                         DRM_DEBUG_DRIVER("CMD: Rejected command: 0x%08X\n", *cmd);
 668                         ret = -EINVAL;
 669                         break;
 670                 }
 671
 672                 if ((desc->flags & CMD_DESC_MASTER) && !is_master) {
 673                         DRM_DEBUG_DRIVER("CMD: Rejected master-only command: 0x%08X\n",
 674                                          *cmd);
 675                         ret = -EINVAL;
 676                         break;
 677                 }
 678
 679                 if (desc->flags & CMD_DESC_REGISTER) {
 680                         u32 reg_addr = cmd[desc->reg.offset] & desc->reg.mask;
 681
 682                         if (!valid_reg(ring->reg_table,
 683                                        ring->reg_count, reg_addr)) {
 684                                 if (!is_master ||
 685                                     !valid_reg(ring->master_reg_table,
 686                                                ring->master_reg_count,
 687                                                reg_addr)) {
 688                                         DRM_DEBUG_DRIVER("CMD: Rejected register 0x%08X in command: 0x%08X (ring=%d)\n",
 689                                                          reg_addr,
 690                                                          *cmd,
 691                                                          ring->id);
 692                                         ret = -EINVAL;
 693                                         break;
 694                                 }
 695                         }
 696                 }
 697
 698                 if (desc->flags & CMD_DESC_BITMASK) {
 699                         int i;
 700
 701                         for (i = 0; i < MAX_CMD_DESC_BITMASKS; i++) {
 702                                 u32 dword;
 703
 704                                 if (desc->bits[i].mask == 0)
 705                                         break;
 706
 707                                 dword = cmd[desc->bits[i].offset] &
 708                                         desc->bits[i].mask;
 709
 710                                 if (dword != desc->bits[i].expected) {
 711                                         DRM_DEBUG_DRIVER("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (ring=%d)\n",
 712                                                          *cmd,
 713                                                          desc->bits[i].mask,
 714                                                          desc->bits[i].expected,
 715                                                          dword, ring->id);
 716                                         ret = -EINVAL;
 717                                         break;
 718                                 }
 719                         }
 720
 721                         if (ret)
 722                                 break;
 723                 }
 724
 725                 cmd += length;
 726         }
 727
 728         if (cmd >= batch_end) {
 729                 DRM_DEBUG_DRIVER("CMD: Got to the end of the buffer w/o a BBE cmd!\n");
 730                 ret = -EINVAL;
 731         }
 732
 733         vunmap(batch_base);
 734
 735         i915_gem_object_unpin_pages(batch_obj);
 736
 737         return ret;
 738 }