drivers/gpu/drm/i915/i915_cmd_parser.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Brad Volkin <bradley.d.volkin@intel.com>
  25  *
  26  */
  27
  28 #include "i915_drv.h"
  29
  30 /**
  31  * DOC: i915 batch buffer command parser
  32  *
  33  * Motivation:
  34  * Certain OpenGL features (e.g. transform feedback, performance monitoring)
  35  * require userspace code to submit batches containing commands such as
  36  * MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some
  37  * generations of the hardware will noop these commands in "unsecure" batches
  38  * (which includes all userspace batches submitted via i915) even though the
  39  * commands may be safe and represent the intended programming model of the
  40  * device.
  41  *
  42  * The software command parser is similar in operation to the command parsing
  43  * done in hardware for unsecure batches. However, the software parser allows
  44  * some operations that would be noop'd by hardware, if the parser determines
  45  * the operation is safe, and submits the batch as "secure" to prevent hardware
  46  * parsing.
  47  *
  48  * Threats:
  49  * At a high level, the hardware (and software) checks attempt to prevent
  50  * granting userspace undue privileges. There are three categories of privilege.
  51  *
  52  * First, commands which are explicitly defined as privileged or which should
  53  * only be used by the kernel driver. The parser generally rejects such
  54  * commands, though it may allow some from the drm master process.
  55  *
  56  * Second, commands which access registers. To support correct/enhanced
  57  * userspace functionality, particularly certain OpenGL extensions, the parser
  58  * provides a whitelist of registers which userspace may safely access (for both
  59  * normal and drm master processes).
  60  *
  61  * Third, commands which access privileged memory (i.e. GGTT, HWS page, etc).
  62  * The parser always rejects such commands.
  63  *
  64  * The majority of the problematic commands fall in the MI_* range, with only a
  65  * few specific commands on each ring (e.g. PIPE_CONTROL and MI_FLUSH_DW).
  66  *
  67  * Implementation:
  68  * Each ring maintains tables of commands and registers which the parser uses in
  69  * scanning batch buffers submitted to that ring.
  70  *
  71  * Since the set of commands that the parser must check for is significantly
  72  * smaller than the number of commands supported, the parser tables contain only
  73  * those commands required by the parser. This generally works because command
  74  * opcode ranges have standard command length encodings. So for commands that
  75  * the parser does not need to check, it can easily skip them. This is
  76  * implementated via a per-ring length decoding vfunc.
  77  *
  78  * Unfortunately, there are a number of commands that do not follow the standard
  79  * length encoding for their opcode range, primarily amongst the MI_* commands.
  80  * To handle this, the parser provides a way to define explicit "skip" entries
  81  * in the per-ring command tables.
  82  *
  83  * Other command table entries map fairly directly to high level categories
  84  * mentioned above: rejected, master-only, register whitelist. The parser
  85  * implements a number of checks, including the privileged memory checks, via a
  86  * general bitmasking mechanism.
  87  */
  88
  89 #define STD_MI_OPCODE_MASK  0xFF800000
  90 #define STD_3D_OPCODE_MASK  0xFFFF0000
  91 #define STD_2D_OPCODE_MASK  0xFFC00000
  92 #define STD_MFX_OPCODE_MASK 0xFFFF0000
  93
  94 #define CMD(op, opm, f, lm, fl, ...)                            \
  95         {                                                       \
  96                 .flags = (fl) | ((f) ? CMD_DESC_FIXED : 0),     \
  97                 .cmd = { (op), (opm) },                         \
  98                 .length = { (lm) },                             \
  99                 __VA_ARGS__                                     \
 100         }
 101
 102 /* Convenience macros to compress the tables */
 103 #define SMI STD_MI_OPCODE_MASK
 104 #define S3D STD_3D_OPCODE_MASK
 105 #define S2D STD_2D_OPCODE_MASK
 106 #define SMFX STD_MFX_OPCODE_MASK
 107 #define F true
 108 #define S CMD_DESC_SKIP
 109 #define R CMD_DESC_REJECT
 110 #define W CMD_DESC_REGISTER
 111 #define B CMD_DESC_BITMASK
 112 #define M CMD_DESC_MASTER
 113
 114 /*            Command                          Mask   Fixed Len   Action
 115               ---------------------------------------------------------- */
 116 static const struct drm_i915_cmd_descriptor common_cmds[] = {
 117         CMD(  MI_NOOP,                          SMI,    F,  1,      S  ),
 118         CMD(  MI_USER_INTERRUPT,                SMI,    F,  1,      R  ),
 119         CMD(  MI_WAIT_FOR_EVENT,                SMI,    F,  1,      M  ),
 120         CMD(  MI_ARB_CHECK,                     SMI,    F,  1,      S  ),
 121         CMD(  MI_REPORT_HEAD,                   SMI,    F,  1,      S  ),
 122         CMD(  MI_SUSPEND_FLUSH,                 SMI,    F,  1,      S  ),
 123         CMD(  MI_SEMAPHORE_MBOX,                SMI,   !F,  0xFF,   R  ),
 124         CMD(  MI_STORE_DWORD_INDEX,             SMI,   !F,  0xFF,   R  ),
 125         CMD(  MI_LOAD_REGISTER_IMM(1),          SMI,   !F,  0xFF,   W,
 126               .reg = { .offset = 1, .mask = 0x007FFFFC }               ),
 127         CMD(  MI_STORE_REGISTER_MEM(1),         SMI,   !F,  0xFF,   W | B,
 128               .reg = { .offset = 1, .mask = 0x007FFFFC },
 129               .bits = {{
 130                         .offset = 0,
 131                         .mask = MI_GLOBAL_GTT,
 132                         .expected = 0,
 133               }},                                                      ),
 134         CMD(  MI_LOAD_REGISTER_MEM,             SMI,   !F,  0xFF,   W | B,
 135               .reg = { .offset = 1, .mask = 0x007FFFFC },
 136               .bits = {{
 137                         .offset = 0,
 138                         .mask = MI_GLOBAL_GTT,
 139                         .expected = 0,
 140               }},                                                      ),
 141         CMD(  MI_BATCH_BUFFER_START,            SMI,   !F,  0xFF,   S  ),
 142 };
 143
 144 static const struct drm_i915_cmd_descriptor render_cmds[] = {
 145         CMD(  MI_FLUSH,                         SMI,    F,  1,      S  ),
 146         CMD(  MI_ARB_ON_OFF,                    SMI,    F,  1,      R  ),
 147         CMD(  MI_PREDICATE,                     SMI,    F,  1,      S  ),
 148         CMD(  MI_TOPOLOGY_FILTER,               SMI,    F,  1,      S  ),
 149         CMD(  MI_DISPLAY_FLIP,                  SMI,   !F,  0xFF,   R  ),
 150         CMD(  MI_SET_CONTEXT,                   SMI,   !F,  0xFF,   R  ),
 151         CMD(  MI_URB_CLEAR,                     SMI,   !F,  0xFF,   S  ),
 152         CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0x3F,   B,
 153               .bits = {{
 154                         .offset = 0,
 155                         .mask = MI_GLOBAL_GTT,
 156                         .expected = 0,
 157               }},                                                      ),
 158         CMD(  MI_UPDATE_GTT,                    SMI,   !F,  0xFF,   R  ),
 159         CMD(  MI_CLFLUSH,                       SMI,   !F,  0x3FF,  B,
 160               .bits = {{
 161                         .offset = 0,
 162                         .mask = MI_GLOBAL_GTT,
 163                         .expected = 0,
 164               }},                                                      ),
 165         CMD(  MI_REPORT_PERF_COUNT,             SMI,   !F,  0x3F,   B,
 166               .bits = {{
 167                         .offset = 1,
 168                         .mask = MI_REPORT_PERF_COUNT_GGTT,
 169                         .expected = 0,
 170               }},                                                      ),
 171         CMD(  MI_CONDITIONAL_BATCH_BUFFER_END,  SMI,   !F,  0xFF,   B,
 172               .bits = {{
 173                         .offset = 0,
 174                         .mask = MI_GLOBAL_GTT,
 175                         .expected = 0,
 176               }},                                                      ),
 177         CMD(  GFX_OP_3DSTATE_VF_STATISTICS,     S3D,    F,  1,      S  ),
 178         CMD(  PIPELINE_SELECT,                  S3D,    F,  1,      S  ),
 179         CMD(  MEDIA_VFE_STATE,                  S3D,   !F,  0xFFFF, B,
 180               .bits = {{
 181                         .offset = 2,
 182                         .mask = MEDIA_VFE_STATE_MMIO_ACCESS_MASK,
 183                         .expected = 0,
 184               }},                                                      ),
 185         CMD(  GPGPU_OBJECT,                     S3D,   !F,  0xFF,   S  ),
 186         CMD(  GPGPU_WALKER,                     S3D,   !F,  0xFF,   S  ),
 187         CMD(  GFX_OP_3DSTATE_SO_DECL_LIST,      S3D,   !F,  0x1FF,  S  ),
 188         CMD(  GFX_OP_PIPE_CONTROL(5),           S3D,   !F,  0xFF,   B,
 189               .bits = {{
 190                         .offset = 1,
 191                         .mask = (PIPE_CONTROL_MMIO_WRITE | PIPE_CONTROL_NOTIFY),
 192                         .expected = 0,
 193               },
 194               {
 195                         .offset = 1,
 196                         .mask = (PIPE_CONTROL_GLOBAL_GTT_IVB |
 197                                  PIPE_CONTROL_STORE_DATA_INDEX),
 198                         .expected = 0,
 199                         .condition_offset = 1,
 200                         .condition_mask = PIPE_CONTROL_POST_SYNC_OP_MASK,
 201               }},                                                      ),
 202 };
 203
 204 static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = {
 205         CMD(  MI_SET_PREDICATE,                 SMI,    F,  1,      S  ),
 206         CMD(  MI_RS_CONTROL,                    SMI,    F,  1,      S  ),
 207         CMD(  MI_URB_ATOMIC_ALLOC,              SMI,    F,  1,      S  ),
 208         CMD(  MI_RS_CONTEXT,                    SMI,    F,  1,      S  ),
 209         CMD(  MI_LOAD_SCAN_LINES_INCL,          SMI,   !F,  0x3F,   M  ),
 210         CMD(  MI_LOAD_SCAN_LINES_EXCL,          SMI,   !F,  0x3F,   R  ),
 211         CMD(  MI_LOAD_REGISTER_REG,             SMI,   !F,  0xFF,   R  ),
 212         CMD(  MI_RS_STORE_DATA_IMM,             SMI,   !F,  0xFF,   S  ),
 213         CMD(  MI_LOAD_URB_MEM,                  SMI,   !F,  0xFF,   S  ),
 214         CMD(  MI_STORE_URB_MEM,                 SMI,   !F,  0xFF,   S  ),
 215         CMD(  GFX_OP_3DSTATE_DX9_CONSTANTF_VS,  S3D,   !F,  0x7FF,  S  ),
 216         CMD(  GFX_OP_3DSTATE_DX9_CONSTANTF_PS,  S3D,   !F,  0x7FF,  S  ),
 217
 218         CMD(  GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS,  S3D,   !F,  0x1FF,  S  ),
 219         CMD(  GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS,  S3D,   !F,  0x1FF,  S  ),
 220         CMD(  GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS,  S3D,   !F,  0x1FF,  S  ),
 221         CMD(  GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS,  S3D,   !F,  0x1FF,  S  ),
 222         CMD(  GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS,  S3D,   !F,  0x1FF,  S  ),
 223 };
 224
 225 static const struct drm_i915_cmd_descriptor video_cmds[] = {
 226         CMD(  MI_ARB_ON_OFF,                    SMI,    F,  1,      R  ),
 227         CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0xFF,   B,
 228               .bits = {{
 229                         .offset = 0,
 230                         .mask = MI_GLOBAL_GTT,
 231                         .expected = 0,
 232               }},                                                      ),
 233         CMD(  MI_UPDATE_GTT,                    SMI,   !F,  0x3F,   R  ),
 234         CMD(  MI_FLUSH_DW,                      SMI,   !F,  0x3F,   B,
 235               .bits = {{
 236                         .offset = 0,
 237                         .mask = MI_FLUSH_DW_NOTIFY,
 238                         .expected = 0,
 239               },
 240               {
 241                         .offset = 1,
 242                         .mask = MI_FLUSH_DW_USE_GTT,
 243                         .expected = 0,
 244                         .condition_offset = 0,
 245                         .condition_mask = MI_FLUSH_DW_OP_MASK,
 246               },
 247               {
 248                         .offset = 0,
 249                         .mask = MI_FLUSH_DW_STORE_INDEX,
 250                         .expected = 0,
 251                         .condition_offset = 0,
 252                         .condition_mask = MI_FLUSH_DW_OP_MASK,
 253               }},                                                      ),
 254         CMD(  MI_CONDITIONAL_BATCH_BUFFER_END,  SMI,   !F,  0xFF,   B,
 255               .bits = {{
 256                         .offset = 0,
 257                         .mask = MI_GLOBAL_GTT,
 258                         .expected = 0,
 259               }},                                                      ),
 260         /*
 261          * MFX_WAIT doesn't fit the way we handle length for most commands.
 262          * It has a length field but it uses a non-standard length bias.
 263          * It is always 1 dword though, so just treat it as fixed length.
 264          */
 265         CMD(  MFX_WAIT,                         SMFX,   F,  1,      S  ),
 266 };
 267
 268 static const struct drm_i915_cmd_descriptor vecs_cmds[] = {
 269         CMD(  MI_ARB_ON_OFF,                    SMI,    F,  1,      R  ),
 270         CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0xFF,   B,
 271               .bits = {{
 272                         .offset = 0,
 273                         .mask = MI_GLOBAL_GTT,
 274                         .expected = 0,
 275               }},                                                      ),
 276         CMD(  MI_UPDATE_GTT,                    SMI,   !F,  0x3F,   R  ),
 277         CMD(  MI_FLUSH_DW,                      SMI,   !F,  0x3F,   B,
 278               .bits = {{
 279                         .offset = 0,
 280                         .mask = MI_FLUSH_DW_NOTIFY,
 281                         .expected = 0,
 282               },
 283               {
 284                         .offset = 1,
 285                         .mask = MI_FLUSH_DW_USE_GTT,
 286                         .expected = 0,
 287                         .condition_offset = 0,
 288                         .condition_mask = MI_FLUSH_DW_OP_MASK,
 289               },
 290               {
 291                         .offset = 0,
 292                         .mask = MI_FLUSH_DW_STORE_INDEX,
 293                         .expected = 0,
 294                         .condition_offset = 0,
 295                         .condition_mask = MI_FLUSH_DW_OP_MASK,
 296               }},                                                      ),
 297         CMD(  MI_CONDITIONAL_BATCH_BUFFER_END,  SMI,   !F,  0xFF,   B,
 298               .bits = {{
 299                         .offset = 0,
 300                         .mask = MI_GLOBAL_GTT,
 301                         .expected = 0,
 302               }},                                                      ),
 303 };
 304
 305 static const struct drm_i915_cmd_descriptor blt_cmds[] = {
 306         CMD(  MI_DISPLAY_FLIP,                  SMI,   !F,  0xFF,   R  ),
 307         CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0x3FF,  B,
 308               .bits = {{
 309                         .offset = 0,
 310                         .mask = MI_GLOBAL_GTT,
 311                         .expected = 0,
 312               }},                                                      ),
 313         CMD(  MI_UPDATE_GTT,                    SMI,   !F,  0x3F,   R  ),
 314         CMD(  MI_FLUSH_DW,                      SMI,   !F,  0x3F,   B,
 315               .bits = {{
 316                         .offset = 0,
 317                         .mask = MI_FLUSH_DW_NOTIFY,
 318                         .expected = 0,
 319               },
 320               {
 321                         .offset = 1,
 322                         .mask = MI_FLUSH_DW_USE_GTT,
 323                         .expected = 0,
 324                         .condition_offset = 0,
 325                         .condition_mask = MI_FLUSH_DW_OP_MASK,
 326               },
 327               {
 328                         .offset = 0,
 329                         .mask = MI_FLUSH_DW_STORE_INDEX,
 330                         .expected = 0,
 331                         .condition_offset = 0,
 332                         .condition_mask = MI_FLUSH_DW_OP_MASK,
 333               }},                                                      ),
 334         CMD(  COLOR_BLT,                        S2D,   !F,  0x3F,   S  ),
 335         CMD(  SRC_COPY_BLT,                     S2D,   !F,  0x3F,   S  ),
 336 };
 337
 338 static const struct drm_i915_cmd_descriptor hsw_blt_cmds[] = {
 339         CMD(  MI_LOAD_SCAN_LINES_INCL,          SMI,   !F,  0x3F,   M  ),
 340         CMD(  MI_LOAD_SCAN_LINES_EXCL,          SMI,   !F,  0x3F,   R  ),
 341 };
 342
 343 #undef CMD
 344 #undef SMI
 345 #undef S3D
 346 #undef S2D
 347 #undef SMFX
 348 #undef F
 349 #undef S
 350 #undef R
 351 #undef W
 352 #undef B
 353 #undef M
 354
 355 static const struct drm_i915_cmd_table gen7_render_cmds[] = {
 356         { common_cmds, ARRAY_SIZE(common_cmds) },
 357         { render_cmds, ARRAY_SIZE(render_cmds) },
 358 };
 359
 360 static const struct drm_i915_cmd_table hsw_render_ring_cmds[] = {
 361         { common_cmds, ARRAY_SIZE(common_cmds) },
 362         { render_cmds, ARRAY_SIZE(render_cmds) },
 363         { hsw_render_cmds, ARRAY_SIZE(hsw_render_cmds) },
 364 };
 365
 366 static const struct drm_i915_cmd_table gen7_video_cmds[] = {
 367         { common_cmds, ARRAY_SIZE(common_cmds) },
 368         { video_cmds, ARRAY_SIZE(video_cmds) },
 369 };
 370
 371 static const struct drm_i915_cmd_table hsw_vebox_cmds[] = {
 372         { common_cmds, ARRAY_SIZE(common_cmds) },
 373         { vecs_cmds, ARRAY_SIZE(vecs_cmds) },
 374 };
 375
 376 static const struct drm_i915_cmd_table gen7_blt_cmds[] = {
 377         { common_cmds, ARRAY_SIZE(common_cmds) },
 378         { blt_cmds, ARRAY_SIZE(blt_cmds) },
 379 };
 380
 381 static const struct drm_i915_cmd_table hsw_blt_ring_cmds[] = {
 382         { common_cmds, ARRAY_SIZE(common_cmds) },
 383         { blt_cmds, ARRAY_SIZE(blt_cmds) },
 384         { hsw_blt_cmds, ARRAY_SIZE(hsw_blt_cmds) },
 385 };
 386
 387 /*
 388  * Register whitelists, sorted by increasing register offset.
 389  *
 390  * Some registers that userspace accesses are 64 bits. The register
 391  * access commands only allow 32-bit accesses. Hence, we have to include
 392  * entries for both halves of the 64-bit registers.
 393  */
 394
 395 /* Convenience macro for adding 64-bit registers */
 396 #define REG64(addr) (addr), (addr + sizeof(u32))
 397
 398 static const u32 gen7_render_regs[] = {
 399         REG64(HS_INVOCATION_COUNT),
 400         REG64(DS_INVOCATION_COUNT),
 401         REG64(IA_VERTICES_COUNT),
 402         REG64(IA_PRIMITIVES_COUNT),
 403         REG64(VS_INVOCATION_COUNT),
 404         REG64(GS_INVOCATION_COUNT),
 405         REG64(GS_PRIMITIVES_COUNT),
 406         REG64(CL_INVOCATION_COUNT),
 407         REG64(CL_PRIMITIVES_COUNT),
 408         REG64(PS_INVOCATION_COUNT),
 409         REG64(PS_DEPTH_COUNT),
 410         /*
 411          * FIXME: This is just to keep mesa working for now, we need to check
 412          * that mesa resets this again and that it doesn't use any of the
 413          * special modes which write into the gtt.
 414          */
 415         OACONTROL,
 416         REG64(GEN7_SO_NUM_PRIMS_WRITTEN(0)),
 417         REG64(GEN7_SO_NUM_PRIMS_WRITTEN(1)),
 418         REG64(GEN7_SO_NUM_PRIMS_WRITTEN(2)),
 419         REG64(GEN7_SO_NUM_PRIMS_WRITTEN(3)),
 420         GEN7_SO_WRITE_OFFSET(0),
 421         GEN7_SO_WRITE_OFFSET(1),
 422         GEN7_SO_WRITE_OFFSET(2),
 423         GEN7_SO_WRITE_OFFSET(3),
 424 };
 425
 426 static const u32 gen7_blt_regs[] = {
 427         BCS_SWCTRL,
 428 };
 429
 430 static const u32 ivb_master_regs[] = {
 431         FORCEWAKE_MT,
 432         DERRMR,
 433         GEN7_PIPE_DE_LOAD_SL(PIPE_A),
 434         GEN7_PIPE_DE_LOAD_SL(PIPE_B),
 435         GEN7_PIPE_DE_LOAD_SL(PIPE_C),
 436 };
 437
 438 static const u32 hsw_master_regs[] = {
 439         FORCEWAKE_MT,
 440         DERRMR,
 441 };
 442
 443 #undef REG64
 444
 445 static u32 gen7_render_get_cmd_length_mask(u32 cmd_header)
 446 {
 447         u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT;
 448         u32 subclient =
 449                 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT;
 450
 451         if (client == INSTR_MI_CLIENT)
 452                 return 0x3F;
 453         else if (client == INSTR_RC_CLIENT) {
 454                 if (subclient == INSTR_MEDIA_SUBCLIENT)
 455                         return 0xFFFF;
 456                 else
 457                         return 0xFF;
 458         }
 459
 460         DRM_DEBUG_DRIVER("CMD: Abnormal rcs cmd length! 0x%08X\n", cmd_header);
 461         return 0;
 462 }
 463
 464 static u32 gen7_bsd_get_cmd_length_mask(u32 cmd_header)
 465 {
 466         u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT;
 467         u32 subclient =
 468                 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT;
 469
 470         if (client == INSTR_MI_CLIENT)
 471                 return 0x3F;
 472         else if (client == INSTR_RC_CLIENT) {
 473                 if (subclient == INSTR_MEDIA_SUBCLIENT)
 474                         return 0xFFF;
 475                 else
 476                         return 0xFF;
 477         }
 478
 479         DRM_DEBUG_DRIVER("CMD: Abnormal bsd cmd length! 0x%08X\n", cmd_header);
 480         return 0;
 481 }
 482
 483 static u32 gen7_blt_get_cmd_length_mask(u32 cmd_header)
 484 {
 485         u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT;
 486
 487         if (client == INSTR_MI_CLIENT)
 488                 return 0x3F;
 489         else if (client == INSTR_BC_CLIENT)
 490                 return 0xFF;
 491
 492         DRM_DEBUG_DRIVER("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header);
 493         return 0;
 494 }
 495
 496 static bool validate_cmds_sorted(struct intel_ring_buffer *ring)
 497 {
 498         int i;
 499         bool ret = true;
 500
 501         if (!ring->cmd_tables || ring->cmd_table_count == 0)
 502                 return true;
 503
 504         for (i = 0; i < ring->cmd_table_count; i++) {
 505                 const struct drm_i915_cmd_table *table = &ring->cmd_tables[i];
 506                 u32 previous = 0;
 507                 int j;
 508
 509                 for (j = 0; j < table->count; j++) {
 510                         const struct drm_i915_cmd_descriptor *desc =
 511                                 &table->table[i];
 512                         u32 curr = desc->cmd.value & desc->cmd.mask;
 513
 514                         if (curr < previous) {
 515                                 DRM_ERROR("CMD: table not sorted ring=%d table=%d entry=%d cmd=0x%08X prev=0x%08X\n",
 516                                           ring->id, i, j, curr, previous);
 517                                 ret = false;
 518                         }
 519
 520                         previous = curr;
 521                 }
 522         }
 523
 524         return ret;
 525 }
 526
 527 static bool check_sorted(int ring_id, const u32 *reg_table, int reg_count)
 528 {
 529         int i;
 530         u32 previous = 0;
 531         bool ret = true;
 532
 533         for (i = 0; i < reg_count; i++) {
 534                 u32 curr = reg_table[i];
 535
 536                 if (curr < previous) {
 537                         DRM_ERROR("CMD: table not sorted ring=%d entry=%d reg=0x%08X prev=0x%08X\n",
 538                                   ring_id, i, curr, previous);
 539                         ret = false;
 540                 }
 541
 542                 previous = curr;
 543         }
 544
 545         return ret;
 546 }
 547
 548 static bool validate_regs_sorted(struct intel_ring_buffer *ring)
 549 {
 550         return check_sorted(ring->id, ring->reg_table, ring->reg_count) &&
 551                 check_sorted(ring->id, ring->master_reg_table,
 552                              ring->master_reg_count);
 553 }
 554
 555 /**
 556  * i915_cmd_parser_init_ring() - set cmd parser related fields for a ringbuffer
 557  * @ring: the ringbuffer to initialize
 558  *
 559  * Optionally initializes fields related to batch buffer command parsing in the
 560  * struct intel_ring_buffer based on whether the platform requires software
 561  * command parsing.
 562  */
 563 void i915_cmd_parser_init_ring(struct intel_ring_buffer *ring)
 564 {
 565         if (!IS_GEN7(ring->dev))
 566                 return;
 567
 568         switch (ring->id) {
 569         case RCS:
 570                 if (IS_HASWELL(ring->dev)) {
 571                         ring->cmd_tables = hsw_render_ring_cmds;
 572                         ring->cmd_table_count =
 573                                 ARRAY_SIZE(hsw_render_ring_cmds);
 574                 } else {
 575                         ring->cmd_tables = gen7_render_cmds;
 576                         ring->cmd_table_count = ARRAY_SIZE(gen7_render_cmds);
 577                 }
 578
 579                 ring->reg_table = gen7_render_regs;
 580                 ring->reg_count = ARRAY_SIZE(gen7_render_regs);
 581
 582                 if (IS_HASWELL(ring->dev)) {
 583                         ring->master_reg_table = hsw_master_regs;
 584                         ring->master_reg_count = ARRAY_SIZE(hsw_master_regs);
 585                 } else {
 586                         ring->master_reg_table = ivb_master_regs;
 587                         ring->master_reg_count = ARRAY_SIZE(ivb_master_regs);
 588                 }
 589
 590                 ring->get_cmd_length_mask = gen7_render_get_cmd_length_mask;
 591                 break;
 592         case VCS:
 593                 ring->cmd_tables = gen7_video_cmds;
 594                 ring->cmd_table_count = ARRAY_SIZE(gen7_video_cmds);
 595                 ring->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
 596                 break;
 597         case BCS:
 598                 if (IS_HASWELL(ring->dev)) {
 599                         ring->cmd_tables = hsw_blt_ring_cmds;
 600                         ring->cmd_table_count = ARRAY_SIZE(hsw_blt_ring_cmds);
 601                 } else {
 602                         ring->cmd_tables = gen7_blt_cmds;
 603                         ring->cmd_table_count = ARRAY_SIZE(gen7_blt_cmds);
 604                 }
 605
 606                 ring->reg_table = gen7_blt_regs;
 607                 ring->reg_count = ARRAY_SIZE(gen7_blt_regs);
 608
 609                 if (IS_HASWELL(ring->dev)) {
 610                         ring->master_reg_table = hsw_master_regs;
 611                         ring->master_reg_count = ARRAY_SIZE(hsw_master_regs);
 612                 } else {
 613                         ring->master_reg_table = ivb_master_regs;
 614                         ring->master_reg_count = ARRAY_SIZE(ivb_master_regs);
 615                 }
 616
 617                 ring->get_cmd_length_mask = gen7_blt_get_cmd_length_mask;
 618                 break;
 619         case VECS:
 620                 ring->cmd_tables = hsw_vebox_cmds;
 621                 ring->cmd_table_count = ARRAY_SIZE(hsw_vebox_cmds);
 622                 /* VECS can use the same length_mask function as VCS */
 623                 ring->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
 624                 break;
 625         default:
 626                 DRM_ERROR("CMD: cmd_parser_init with unknown ring: %d\n",
 627                           ring->id);
 628                 BUG();
 629         }
 630
 631         BUG_ON(!validate_cmds_sorted(ring));
 632         BUG_ON(!validate_regs_sorted(ring));
 633 }
 634
 635 static const struct drm_i915_cmd_descriptor*
 636 find_cmd_in_table(const struct drm_i915_cmd_table *table,
 637                   u32 cmd_header)
 638 {
 639         int i;
 640
 641         for (i = 0; i < table->count; i++) {
 642                 const struct drm_i915_cmd_descriptor *desc = &table->table[i];
 643                 u32 masked_cmd = desc->cmd.mask & cmd_header;
 644                 u32 masked_value = desc->cmd.value & desc->cmd.mask;
 645
 646                 if (masked_cmd == masked_value)
 647                         return desc;
 648         }
 649
 650         return NULL;
 651 }
 652
 653 /*
 654  * Returns a pointer to a descriptor for the command specified by cmd_header.
 655  *
 656  * The caller must supply space for a default descriptor via the default_desc
 657  * parameter. If no descriptor for the specified command exists in the ring's
 658  * command parser tables, this function fills in default_desc based on the
 659  * ring's default length encoding and returns default_desc.
 660  */
 661 static const struct drm_i915_cmd_descriptor*
 662 find_cmd(struct intel_ring_buffer *ring,
 663          u32 cmd_header,
 664          struct drm_i915_cmd_descriptor *default_desc)
 665 {
 666         u32 mask;
 667         int i;
 668
 669         for (i = 0; i < ring->cmd_table_count; i++) {
 670                 const struct drm_i915_cmd_descriptor *desc;
 671
 672                 desc = find_cmd_in_table(&ring->cmd_tables[i], cmd_header);
 673                 if (desc)
 674                         return desc;
 675         }
 676
 677         mask = ring->get_cmd_length_mask(cmd_header);
 678         if (!mask)
 679                 return NULL;
 680
 681         BUG_ON(!default_desc);
 682         default_desc->flags = CMD_DESC_SKIP;
 683         default_desc->length.mask = mask;
 684
 685         return default_desc;
 686 }
 687
 688 static bool valid_reg(const u32 *table, int count, u32 addr)
 689 {
 690         if (table && count != 0) {
 691                 int i;
 692
 693                 for (i = 0; i < count; i++) {
 694                         if (table[i] == addr)
 695                                 return true;
 696                 }
 697         }
 698
 699         return false;
 700 }
 701
 702 static u32 *vmap_batch(struct drm_i915_gem_object *obj)
 703 {
 704         int i;
 705         void *addr = NULL;
 706         struct sg_page_iter sg_iter;
 707         struct page **pages;
 708
 709         pages = drm_malloc_ab(obj->base.size >> PAGE_SHIFT, sizeof(*pages));
 710         if (pages == NULL) {
 711                 DRM_DEBUG_DRIVER("Failed to get space for pages\n");
 712                 goto finish;
 713         }
 714
 715         i = 0;
 716         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
 717                 pages[i] = sg_page_iter_page(&sg_iter);
 718                 i++;
 719         }
 720
 721         addr = vmap(pages, i, 0, PAGE_KERNEL);
 722         if (addr == NULL) {
 723                 DRM_DEBUG_DRIVER("Failed to vmap pages\n");
 724                 goto finish;
 725         }
 726
 727 finish:
 728         if (pages)
 729                 drm_free_large(pages);
 730         return (u32*)addr;
 731 }
 732
 733 /**
 734  * i915_needs_cmd_parser() - should a given ring use software command parsing?
 735  * @ring: the ring in question
 736  *
 737  * Only certain platforms require software batch buffer command parsing, and
 738  * only when enabled via module paramter.
 739  *
 740  * Return: true if the ring requires software command parsing
 741  */
 742 bool i915_needs_cmd_parser(struct intel_ring_buffer *ring)
 743 {
 744         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 745
 746         /* No command tables indicates a platform without parsing */
 747         if (!ring->cmd_tables)
 748                 return false;
 749
 750         /*
 751          * XXX: VLV is Gen7 and therefore has cmd_tables, but has PPGTT
 752          * disabled. That will cause all of the parser's PPGTT checks to
 753          * fail. For now, disable parsing when PPGTT is off.
 754          */
 755         if (!dev_priv->mm.aliasing_ppgtt)
 756                 return false;
 757
 758         return (i915.enable_cmd_parser == 1);
 759 }
 760
 761 #define LENGTH_BIAS 2
 762
 763 /**
 764  * i915_parse_cmds() - parse a submitted batch buffer for privilege violations
 765  * @ring: the ring on which the batch is to execute
 766  * @batch_obj: the batch buffer in question
 767  * @batch_start_offset: byte offset in the batch at which execution starts
 768  * @is_master: is the submitting process the drm master?
 769  *
 770  * Parses the specified batch buffer looking for privilege violations as
 771  * described in the overview.
 772  *
 773  * Return: non-zero if the parser finds violations or otherwise fails
 774  */
 775 int i915_parse_cmds(struct intel_ring_buffer *ring,
 776                     struct drm_i915_gem_object *batch_obj,
 777                     u32 batch_start_offset,
 778                     bool is_master)
 779 {
 780         int ret = 0;
 781         u32 *cmd, *batch_base, *batch_end;
 782         struct drm_i915_cmd_descriptor default_desc = { 0 };
 783         int needs_clflush = 0;
 784
 785         ret = i915_gem_obj_prepare_shmem_read(batch_obj, &needs_clflush);
 786         if (ret) {
 787                 DRM_DEBUG_DRIVER("CMD: failed to prep read\n");
 788                 return ret;
 789         }
 790
 791         batch_base = vmap_batch(batch_obj);
 792         if (!batch_base) {
 793                 DRM_DEBUG_DRIVER("CMD: Failed to vmap batch\n");
 794                 i915_gem_object_unpin_pages(batch_obj);
 795                 return -ENOMEM;
 796         }
 797
 798         if (needs_clflush)
 799                 drm_clflush_virt_range((char *)batch_base, batch_obj->base.size);
 800
 801         cmd = batch_base + (batch_start_offset / sizeof(*cmd));
 802         batch_end = cmd + (batch_obj->base.size / sizeof(*batch_end));
 803
 804         while (cmd < batch_end) {
 805                 const struct drm_i915_cmd_descriptor *desc;
 806                 u32 length;
 807
 808                 if (*cmd == MI_BATCH_BUFFER_END)
 809                         break;
 810
 811                 desc = find_cmd(ring, *cmd, &default_desc);
 812                 if (!desc) {
 813                         DRM_DEBUG_DRIVER("CMD: Unrecognized command: 0x%08X\n",
 814                                          *cmd);
 815                         ret = -EINVAL;
 816                         break;
 817                 }
 818
 819                 if (desc->flags & CMD_DESC_FIXED)
 820                         length = desc->length.fixed;
 821                 else
 822                         length = ((*cmd & desc->length.mask) + LENGTH_BIAS);
 823
 824                 if ((batch_end - cmd) < length) {
 825                         DRM_DEBUG_DRIVER("CMD: Command length exceeds batch length: 0x%08X length=%d batchlen=%td\n",
 826                                          *cmd,
 827                                          length,
 828                                          batch_end - cmd);
 829                         ret = -EINVAL;
 830                         break;
 831                 }
 832
 833                 if (desc->flags & CMD_DESC_REJECT) {
 834                         DRM_DEBUG_DRIVER("CMD: Rejected command: 0x%08X\n", *cmd);
 835                         ret = -EINVAL;
 836                         break;
 837                 }
 838
 839                 if ((desc->flags & CMD_DESC_MASTER) && !is_master) {
 840                         DRM_DEBUG_DRIVER("CMD: Rejected master-only command: 0x%08X\n",
 841                                          *cmd);
 842                         ret = -EINVAL;
 843                         break;
 844                 }
 845
 846                 if (desc->flags & CMD_DESC_REGISTER) {
 847                         u32 reg_addr = cmd[desc->reg.offset] & desc->reg.mask;
 848
 849                         if (!valid_reg(ring->reg_table,
 850                                        ring->reg_count, reg_addr)) {
 851                                 if (!is_master ||
 852                                     !valid_reg(ring->master_reg_table,
 853                                                ring->master_reg_count,
 854                                                reg_addr)) {
 855                                         DRM_DEBUG_DRIVER("CMD: Rejected register 0x%08X in command: 0x%08X (ring=%d)\n",
 856                                                          reg_addr,
 857                                                          *cmd,
 858                                                          ring->id);
 859                                         ret = -EINVAL;
 860                                         break;
 861                                 }
 862                         }
 863                 }
 864
 865                 if (desc->flags & CMD_DESC_BITMASK) {
 866                         int i;
 867
 868                         for (i = 0; i < MAX_CMD_DESC_BITMASKS; i++) {
 869                                 u32 dword;
 870
 871                                 if (desc->bits[i].mask == 0)
 872                                         break;
 873
 874                                 if (desc->bits[i].condition_mask != 0) {
 875                                         u32 offset =
 876                                                 desc->bits[i].condition_offset;
 877                                         u32 condition = cmd[offset] &
 878                                                 desc->bits[i].condition_mask;
 879
 880                                         if (condition == 0)
 881                                                 continue;
 882                                 }
 883
 884                                 dword = cmd[desc->bits[i].offset] &
 885                                         desc->bits[i].mask;
 886
 887                                 if (dword != desc->bits[i].expected) {
 888                                         DRM_DEBUG_DRIVER("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (ring=%d)\n",
 889                                                          *cmd,
 890                                                          desc->bits[i].mask,
 891                                                          desc->bits[i].expected,
 892                                                          dword, ring->id);
 893                                         ret = -EINVAL;
 894                                         break;
 895                                 }
 896                         }
 897
 898                         if (ret)
 899                                 break;
 900                 }
 901
 902                 cmd += length;
 903         }
 904
 905         if (cmd >= batch_end) {
 906                 DRM_DEBUG_DRIVER("CMD: Got to the end of the buffer w/o a BBE cmd!\n");
 907                 ret = -EINVAL;
 908         }
 909
 910         vunmap(batch_base);
 911
 912         i915_gem_object_unpin_pages(batch_obj);
 913
 914         return ret;
 915 }
 916
 917 /**
 918  * i915_cmd_parser_get_version() - get the cmd parser version number
 919  *
 920  * The cmd parser maintains a simple increasing integer version number suitable
 921  * for passing to userspace clients to determine what operations are permitted.
 922  *
 923  * Return: the current version number of the cmd parser
 924  */
 925 int i915_cmd_parser_get_version(void)
 926 {
 927         /*
 928          * Command parser version history
 929          *
 930          * 1. Initial version. Checks batches and reports violations, but leaves
 931          *    hardware parsing enabled (so does not allow new use cases).
 932          */
 933         return 1;
 934 }