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Merge branches 'for-4.8/alps', 'for-4.8/apple', 'for-4.8/i2c-hid', 'for-4.8/uhid...
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_cmd_parser.c
1 /*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Brad Volkin <bradley.d.volkin@intel.com>
25 *
26 */
27
28 #include "i915_drv.h"
29
30 /**
31 * DOC: batch buffer command parser
32 *
33 * Motivation:
34 * Certain OpenGL features (e.g. transform feedback, performance monitoring)
35 * require userspace code to submit batches containing commands such as
36 * MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some
37 * generations of the hardware will noop these commands in "unsecure" batches
38 * (which includes all userspace batches submitted via i915) even though the
39 * commands may be safe and represent the intended programming model of the
40 * device.
41 *
42 * The software command parser is similar in operation to the command parsing
43 * done in hardware for unsecure batches. However, the software parser allows
44 * some operations that would be noop'd by hardware, if the parser determines
45 * the operation is safe, and submits the batch as "secure" to prevent hardware
46 * parsing.
47 *
48 * Threats:
49 * At a high level, the hardware (and software) checks attempt to prevent
50 * granting userspace undue privileges. There are three categories of privilege.
51 *
52 * First, commands which are explicitly defined as privileged or which should
53 * only be used by the kernel driver. The parser generally rejects such
54 * commands, though it may allow some from the drm master process.
55 *
56 * Second, commands which access registers. To support correct/enhanced
57 * userspace functionality, particularly certain OpenGL extensions, the parser
58 * provides a whitelist of registers which userspace may safely access (for both
59 * normal and drm master processes).
60 *
61 * Third, commands which access privileged memory (i.e. GGTT, HWS page, etc).
62 * The parser always rejects such commands.
63 *
64 * The majority of the problematic commands fall in the MI_* range, with only a
65 * few specific commands on each ring (e.g. PIPE_CONTROL and MI_FLUSH_DW).
66 *
67 * Implementation:
68 * Each ring maintains tables of commands and registers which the parser uses in
69 * scanning batch buffers submitted to that ring.
70 *
71 * Since the set of commands that the parser must check for is significantly
72 * smaller than the number of commands supported, the parser tables contain only
73 * those commands required by the parser. This generally works because command
74 * opcode ranges have standard command length encodings. So for commands that
75 * the parser does not need to check, it can easily skip them. This is
76 * implemented via a per-ring length decoding vfunc.
77 *
78 * Unfortunately, there are a number of commands that do not follow the standard
79 * length encoding for their opcode range, primarily amongst the MI_* commands.
80 * To handle this, the parser provides a way to define explicit "skip" entries
81 * in the per-ring command tables.
82 *
83 * Other command table entries map fairly directly to high level categories
84 * mentioned above: rejected, master-only, register whitelist. The parser
85 * implements a number of checks, including the privileged memory checks, via a
86 * general bitmasking mechanism.
87 */
88
89 #define STD_MI_OPCODE_MASK 0xFF800000
90 #define STD_3D_OPCODE_MASK 0xFFFF0000
91 #define STD_2D_OPCODE_MASK 0xFFC00000
92 #define STD_MFX_OPCODE_MASK 0xFFFF0000
93
94 #define CMD(op, opm, f, lm, fl, ...) \
95 { \
96 .flags = (fl) | ((f) ? CMD_DESC_FIXED : 0), \
97 .cmd = { (op), (opm) }, \
98 .length = { (lm) }, \
99 __VA_ARGS__ \
100 }
101
102 /* Convenience macros to compress the tables */
103 #define SMI STD_MI_OPCODE_MASK
104 #define S3D STD_3D_OPCODE_MASK
105 #define S2D STD_2D_OPCODE_MASK
106 #define SMFX STD_MFX_OPCODE_MASK
107 #define F true
108 #define S CMD_DESC_SKIP
109 #define R CMD_DESC_REJECT
110 #define W CMD_DESC_REGISTER
111 #define B CMD_DESC_BITMASK
112 #define M CMD_DESC_MASTER
113
114 /* Command Mask Fixed Len Action
115 ---------------------------------------------------------- */
116 static const struct drm_i915_cmd_descriptor common_cmds[] = {
117 CMD( MI_NOOP, SMI, F, 1, S ),
118 CMD( MI_USER_INTERRUPT, SMI, F, 1, R ),
119 CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, M ),
120 CMD( MI_ARB_CHECK, SMI, F, 1, S ),
121 CMD( MI_REPORT_HEAD, SMI, F, 1, S ),
122 CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ),
123 CMD( MI_SEMAPHORE_MBOX, SMI, !F, 0xFF, R ),
124 CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, R ),
125 CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W,
126 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 } ),
127 CMD( MI_STORE_REGISTER_MEM, SMI, F, 3, W | B,
128 .reg = { .offset = 1, .mask = 0x007FFFFC },
129 .bits = {{
130 .offset = 0,
131 .mask = MI_GLOBAL_GTT,
132 .expected = 0,
133 }}, ),
134 CMD( MI_LOAD_REGISTER_MEM, SMI, F, 3, W | B,
135 .reg = { .offset = 1, .mask = 0x007FFFFC },
136 .bits = {{
137 .offset = 0,
138 .mask = MI_GLOBAL_GTT,
139 .expected = 0,
140 }}, ),
141 /*
142 * MI_BATCH_BUFFER_START requires some special handling. It's not
143 * really a 'skip' action but it doesn't seem like it's worth adding
144 * a new action. See i915_parse_cmds().
145 */
146 CMD( MI_BATCH_BUFFER_START, SMI, !F, 0xFF, S ),
147 };
148
149 static const struct drm_i915_cmd_descriptor render_cmds[] = {
150 CMD( MI_FLUSH, SMI, F, 1, S ),
151 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
152 CMD( MI_PREDICATE, SMI, F, 1, S ),
153 CMD( MI_TOPOLOGY_FILTER, SMI, F, 1, S ),
154 CMD( MI_SET_APPID, SMI, F, 1, S ),
155 CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ),
156 CMD( MI_SET_CONTEXT, SMI, !F, 0xFF, R ),
157 CMD( MI_URB_CLEAR, SMI, !F, 0xFF, S ),
158 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3F, B,
159 .bits = {{
160 .offset = 0,
161 .mask = MI_GLOBAL_GTT,
162 .expected = 0,
163 }}, ),
164 CMD( MI_UPDATE_GTT, SMI, !F, 0xFF, R ),
165 CMD( MI_CLFLUSH, SMI, !F, 0x3FF, B,
166 .bits = {{
167 .offset = 0,
168 .mask = MI_GLOBAL_GTT,
169 .expected = 0,
170 }}, ),
171 CMD( MI_REPORT_PERF_COUNT, SMI, !F, 0x3F, B,
172 .bits = {{
173 .offset = 1,
174 .mask = MI_REPORT_PERF_COUNT_GGTT,
175 .expected = 0,
176 }}, ),
177 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,
178 .bits = {{
179 .offset = 0,
180 .mask = MI_GLOBAL_GTT,
181 .expected = 0,
182 }}, ),
183 CMD( GFX_OP_3DSTATE_VF_STATISTICS, S3D, F, 1, S ),
184 CMD( PIPELINE_SELECT, S3D, F, 1, S ),
185 CMD( MEDIA_VFE_STATE, S3D, !F, 0xFFFF, B,
186 .bits = {{
187 .offset = 2,
188 .mask = MEDIA_VFE_STATE_MMIO_ACCESS_MASK,
189 .expected = 0,
190 }}, ),
191 CMD( GPGPU_OBJECT, S3D, !F, 0xFF, S ),
192 CMD( GPGPU_WALKER, S3D, !F, 0xFF, S ),
193 CMD( GFX_OP_3DSTATE_SO_DECL_LIST, S3D, !F, 0x1FF, S ),
194 CMD( GFX_OP_PIPE_CONTROL(5), S3D, !F, 0xFF, B,
195 .bits = {{
196 .offset = 1,
197 .mask = (PIPE_CONTROL_MMIO_WRITE | PIPE_CONTROL_NOTIFY),
198 .expected = 0,
199 },
200 {
201 .offset = 1,
202 .mask = (PIPE_CONTROL_GLOBAL_GTT_IVB |
203 PIPE_CONTROL_STORE_DATA_INDEX),
204 .expected = 0,
205 .condition_offset = 1,
206 .condition_mask = PIPE_CONTROL_POST_SYNC_OP_MASK,
207 }}, ),
208 };
209
210 static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = {
211 CMD( MI_SET_PREDICATE, SMI, F, 1, S ),
212 CMD( MI_RS_CONTROL, SMI, F, 1, S ),
213 CMD( MI_URB_ATOMIC_ALLOC, SMI, F, 1, S ),
214 CMD( MI_SET_APPID, SMI, F, 1, S ),
215 CMD( MI_RS_CONTEXT, SMI, F, 1, S ),
216 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, M ),
217 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ),
218 CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, R ),
219 CMD( MI_RS_STORE_DATA_IMM, SMI, !F, 0xFF, S ),
220 CMD( MI_LOAD_URB_MEM, SMI, !F, 0xFF, S ),
221 CMD( MI_STORE_URB_MEM, SMI, !F, 0xFF, S ),
222 CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_VS, S3D, !F, 0x7FF, S ),
223 CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_PS, S3D, !F, 0x7FF, S ),
224
225 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS, S3D, !F, 0x1FF, S ),
226 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS, S3D, !F, 0x1FF, S ),
227 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS, S3D, !F, 0x1FF, S ),
228 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS, S3D, !F, 0x1FF, S ),
229 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS, S3D, !F, 0x1FF, S ),
230 };
231
232 static const struct drm_i915_cmd_descriptor video_cmds[] = {
233 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
234 CMD( MI_SET_APPID, SMI, F, 1, S ),
235 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B,
236 .bits = {{
237 .offset = 0,
238 .mask = MI_GLOBAL_GTT,
239 .expected = 0,
240 }}, ),
241 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
242 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
243 .bits = {{
244 .offset = 0,
245 .mask = MI_FLUSH_DW_NOTIFY,
246 .expected = 0,
247 },
248 {
249 .offset = 1,
250 .mask = MI_FLUSH_DW_USE_GTT,
251 .expected = 0,
252 .condition_offset = 0,
253 .condition_mask = MI_FLUSH_DW_OP_MASK,
254 },
255 {
256 .offset = 0,
257 .mask = MI_FLUSH_DW_STORE_INDEX,
258 .expected = 0,
259 .condition_offset = 0,
260 .condition_mask = MI_FLUSH_DW_OP_MASK,
261 }}, ),
262 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,
263 .bits = {{
264 .offset = 0,
265 .mask = MI_GLOBAL_GTT,
266 .expected = 0,
267 }}, ),
268 /*
269 * MFX_WAIT doesn't fit the way we handle length for most commands.
270 * It has a length field but it uses a non-standard length bias.
271 * It is always 1 dword though, so just treat it as fixed length.
272 */
273 CMD( MFX_WAIT, SMFX, F, 1, S ),
274 };
275
276 static const struct drm_i915_cmd_descriptor vecs_cmds[] = {
277 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
278 CMD( MI_SET_APPID, SMI, F, 1, S ),
279 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B,
280 .bits = {{
281 .offset = 0,
282 .mask = MI_GLOBAL_GTT,
283 .expected = 0,
284 }}, ),
285 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
286 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
287 .bits = {{
288 .offset = 0,
289 .mask = MI_FLUSH_DW_NOTIFY,
290 .expected = 0,
291 },
292 {
293 .offset = 1,
294 .mask = MI_FLUSH_DW_USE_GTT,
295 .expected = 0,
296 .condition_offset = 0,
297 .condition_mask = MI_FLUSH_DW_OP_MASK,
298 },
299 {
300 .offset = 0,
301 .mask = MI_FLUSH_DW_STORE_INDEX,
302 .expected = 0,
303 .condition_offset = 0,
304 .condition_mask = MI_FLUSH_DW_OP_MASK,
305 }}, ),
306 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,
307 .bits = {{
308 .offset = 0,
309 .mask = MI_GLOBAL_GTT,
310 .expected = 0,
311 }}, ),
312 };
313
314 static const struct drm_i915_cmd_descriptor blt_cmds[] = {
315 CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ),
316 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, B,
317 .bits = {{
318 .offset = 0,
319 .mask = MI_GLOBAL_GTT,
320 .expected = 0,
321 }}, ),
322 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
323 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
324 .bits = {{
325 .offset = 0,
326 .mask = MI_FLUSH_DW_NOTIFY,
327 .expected = 0,
328 },
329 {
330 .offset = 1,
331 .mask = MI_FLUSH_DW_USE_GTT,
332 .expected = 0,
333 .condition_offset = 0,
334 .condition_mask = MI_FLUSH_DW_OP_MASK,
335 },
336 {
337 .offset = 0,
338 .mask = MI_FLUSH_DW_STORE_INDEX,
339 .expected = 0,
340 .condition_offset = 0,
341 .condition_mask = MI_FLUSH_DW_OP_MASK,
342 }}, ),
343 CMD( COLOR_BLT, S2D, !F, 0x3F, S ),
344 CMD( SRC_COPY_BLT, S2D, !F, 0x3F, S ),
345 };
346
347 static const struct drm_i915_cmd_descriptor hsw_blt_cmds[] = {
348 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, M ),
349 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ),
350 };
351
352 #undef CMD
353 #undef SMI
354 #undef S3D
355 #undef S2D
356 #undef SMFX
357 #undef F
358 #undef S
359 #undef R
360 #undef W
361 #undef B
362 #undef M
363
364 static const struct drm_i915_cmd_table gen7_render_cmds[] = {
365 { common_cmds, ARRAY_SIZE(common_cmds) },
366 { render_cmds, ARRAY_SIZE(render_cmds) },
367 };
368
369 static const struct drm_i915_cmd_table hsw_render_ring_cmds[] = {
370 { common_cmds, ARRAY_SIZE(common_cmds) },
371 { render_cmds, ARRAY_SIZE(render_cmds) },
372 { hsw_render_cmds, ARRAY_SIZE(hsw_render_cmds) },
373 };
374
375 static const struct drm_i915_cmd_table gen7_video_cmds[] = {
376 { common_cmds, ARRAY_SIZE(common_cmds) },
377 { video_cmds, ARRAY_SIZE(video_cmds) },
378 };
379
380 static const struct drm_i915_cmd_table hsw_vebox_cmds[] = {
381 { common_cmds, ARRAY_SIZE(common_cmds) },
382 { vecs_cmds, ARRAY_SIZE(vecs_cmds) },
383 };
384
385 static const struct drm_i915_cmd_table gen7_blt_cmds[] = {
386 { common_cmds, ARRAY_SIZE(common_cmds) },
387 { blt_cmds, ARRAY_SIZE(blt_cmds) },
388 };
389
390 static const struct drm_i915_cmd_table hsw_blt_ring_cmds[] = {
391 { common_cmds, ARRAY_SIZE(common_cmds) },
392 { blt_cmds, ARRAY_SIZE(blt_cmds) },
393 { hsw_blt_cmds, ARRAY_SIZE(hsw_blt_cmds) },
394 };
395
396 /*
397 * Register whitelists, sorted by increasing register offset.
398 */
399
400 /*
401 * An individual whitelist entry granting access to register addr. If
402 * mask is non-zero the argument of immediate register writes will be
403 * AND-ed with mask, and the command will be rejected if the result
404 * doesn't match value.
405 *
406 * Registers with non-zero mask are only allowed to be written using
407 * LRI.
408 */
409 struct drm_i915_reg_descriptor {
410 i915_reg_t addr;
411 u32 mask;
412 u32 value;
413 };
414
415 /* Convenience macro for adding 32-bit registers. */
416 #define REG32(_reg, ...) \
417 { .addr = (_reg), __VA_ARGS__ }
418
419 /*
420 * Convenience macro for adding 64-bit registers.
421 *
422 * Some registers that userspace accesses are 64 bits. The register
423 * access commands only allow 32-bit accesses. Hence, we have to include
424 * entries for both halves of the 64-bit registers.
425 */
426 #define REG64(_reg) \
427 { .addr = _reg }, \
428 { .addr = _reg ## _UDW }
429
430 #define REG64_IDX(_reg, idx) \
431 { .addr = _reg(idx) }, \
432 { .addr = _reg ## _UDW(idx) }
433
434 static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
435 REG64(GPGPU_THREADS_DISPATCHED),
436 REG64(HS_INVOCATION_COUNT),
437 REG64(DS_INVOCATION_COUNT),
438 REG64(IA_VERTICES_COUNT),
439 REG64(IA_PRIMITIVES_COUNT),
440 REG64(VS_INVOCATION_COUNT),
441 REG64(GS_INVOCATION_COUNT),
442 REG64(GS_PRIMITIVES_COUNT),
443 REG64(CL_INVOCATION_COUNT),
444 REG64(CL_PRIMITIVES_COUNT),
445 REG64(PS_INVOCATION_COUNT),
446 REG64(PS_DEPTH_COUNT),
447 REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
448 REG32(OACONTROL), /* Only allowed for LRI and SRM. See below. */
449 REG64(MI_PREDICATE_SRC0),
450 REG64(MI_PREDICATE_SRC1),
451 REG32(GEN7_3DPRIM_END_OFFSET),
452 REG32(GEN7_3DPRIM_START_VERTEX),
453 REG32(GEN7_3DPRIM_VERTEX_COUNT),
454 REG32(GEN7_3DPRIM_INSTANCE_COUNT),
455 REG32(GEN7_3DPRIM_START_INSTANCE),
456 REG32(GEN7_3DPRIM_BASE_VERTEX),
457 REG32(GEN7_GPGPU_DISPATCHDIMX),
458 REG32(GEN7_GPGPU_DISPATCHDIMY),
459 REG32(GEN7_GPGPU_DISPATCHDIMZ),
460 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 0),
461 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 1),
462 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 2),
463 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 3),
464 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 0),
465 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 1),
466 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 2),
467 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 3),
468 REG32(GEN7_SO_WRITE_OFFSET(0)),
469 REG32(GEN7_SO_WRITE_OFFSET(1)),
470 REG32(GEN7_SO_WRITE_OFFSET(2)),
471 REG32(GEN7_SO_WRITE_OFFSET(3)),
472 REG32(GEN7_L3SQCREG1),
473 REG32(GEN7_L3CNTLREG2),
474 REG32(GEN7_L3CNTLREG3),
475 };
476
477 static const struct drm_i915_reg_descriptor hsw_render_regs[] = {
478 REG64_IDX(HSW_CS_GPR, 0),
479 REG64_IDX(HSW_CS_GPR, 1),
480 REG64_IDX(HSW_CS_GPR, 2),
481 REG64_IDX(HSW_CS_GPR, 3),
482 REG64_IDX(HSW_CS_GPR, 4),
483 REG64_IDX(HSW_CS_GPR, 5),
484 REG64_IDX(HSW_CS_GPR, 6),
485 REG64_IDX(HSW_CS_GPR, 7),
486 REG64_IDX(HSW_CS_GPR, 8),
487 REG64_IDX(HSW_CS_GPR, 9),
488 REG64_IDX(HSW_CS_GPR, 10),
489 REG64_IDX(HSW_CS_GPR, 11),
490 REG64_IDX(HSW_CS_GPR, 12),
491 REG64_IDX(HSW_CS_GPR, 13),
492 REG64_IDX(HSW_CS_GPR, 14),
493 REG64_IDX(HSW_CS_GPR, 15),
494 REG32(HSW_SCRATCH1,
495 .mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE,
496 .value = 0),
497 REG32(HSW_ROW_CHICKEN3,
498 .mask = ~(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE << 16 |
499 HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE),
500 .value = 0),
501 };
502
503 static const struct drm_i915_reg_descriptor gen7_blt_regs[] = {
504 REG32(BCS_SWCTRL),
505 };
506
507 static const struct drm_i915_reg_descriptor ivb_master_regs[] = {
508 REG32(FORCEWAKE_MT),
509 REG32(DERRMR),
510 REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_A)),
511 REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_B)),
512 REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_C)),
513 };
514
515 static const struct drm_i915_reg_descriptor hsw_master_regs[] = {
516 REG32(FORCEWAKE_MT),
517 REG32(DERRMR),
518 };
519
520 #undef REG64
521 #undef REG32
522
523 struct drm_i915_reg_table {
524 const struct drm_i915_reg_descriptor *regs;
525 int num_regs;
526 bool master;
527 };
528
529 static const struct drm_i915_reg_table ivb_render_reg_tables[] = {
530 { gen7_render_regs, ARRAY_SIZE(gen7_render_regs), false },
531 { ivb_master_regs, ARRAY_SIZE(ivb_master_regs), true },
532 };
533
534 static const struct drm_i915_reg_table ivb_blt_reg_tables[] = {
535 { gen7_blt_regs, ARRAY_SIZE(gen7_blt_regs), false },
536 { ivb_master_regs, ARRAY_SIZE(ivb_master_regs), true },
537 };
538
539 static const struct drm_i915_reg_table hsw_render_reg_tables[] = {
540 { gen7_render_regs, ARRAY_SIZE(gen7_render_regs), false },
541 { hsw_render_regs, ARRAY_SIZE(hsw_render_regs), false },
542 { hsw_master_regs, ARRAY_SIZE(hsw_master_regs), true },
543 };
544
545 static const struct drm_i915_reg_table hsw_blt_reg_tables[] = {
546 { gen7_blt_regs, ARRAY_SIZE(gen7_blt_regs), false },
547 { hsw_master_regs, ARRAY_SIZE(hsw_master_regs), true },
548 };
549
550 static u32 gen7_render_get_cmd_length_mask(u32 cmd_header)
551 {
552 u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT;
553 u32 subclient =
554 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT;
555
556 if (client == INSTR_MI_CLIENT)
557 return 0x3F;
558 else if (client == INSTR_RC_CLIENT) {
559 if (subclient == INSTR_MEDIA_SUBCLIENT)
560 return 0xFFFF;
561 else
562 return 0xFF;
563 }
564
565 DRM_DEBUG_DRIVER("CMD: Abnormal rcs cmd length! 0x%08X\n", cmd_header);
566 return 0;
567 }
568
569 static u32 gen7_bsd_get_cmd_length_mask(u32 cmd_header)
570 {
571 u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT;
572 u32 subclient =
573 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT;
574 u32 op = (cmd_header & INSTR_26_TO_24_MASK) >> INSTR_26_TO_24_SHIFT;
575
576 if (client == INSTR_MI_CLIENT)
577 return 0x3F;
578 else if (client == INSTR_RC_CLIENT) {
579 if (subclient == INSTR_MEDIA_SUBCLIENT) {
580 if (op == 6)
581 return 0xFFFF;
582 else
583 return 0xFFF;
584 } else
585 return 0xFF;
586 }
587
588 DRM_DEBUG_DRIVER("CMD: Abnormal bsd cmd length! 0x%08X\n", cmd_header);
589 return 0;
590 }
591
592 static u32 gen7_blt_get_cmd_length_mask(u32 cmd_header)
593 {
594 u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT;
595
596 if (client == INSTR_MI_CLIENT)
597 return 0x3F;
598 else if (client == INSTR_BC_CLIENT)
599 return 0xFF;
600
601 DRM_DEBUG_DRIVER("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header);
602 return 0;
603 }
604
605 static bool validate_cmds_sorted(struct intel_engine_cs *engine,
606 const struct drm_i915_cmd_table *cmd_tables,
607 int cmd_table_count)
608 {
609 int i;
610 bool ret = true;
611
612 if (!cmd_tables || cmd_table_count == 0)
613 return true;
614
615 for (i = 0; i < cmd_table_count; i++) {
616 const struct drm_i915_cmd_table *table = &cmd_tables[i];
617 u32 previous = 0;
618 int j;
619
620 for (j = 0; j < table->count; j++) {
621 const struct drm_i915_cmd_descriptor *desc =
622 &table->table[j];
623 u32 curr = desc->cmd.value & desc->cmd.mask;
624
625 if (curr < previous) {
626 DRM_ERROR("CMD: table not sorted ring=%d table=%d entry=%d cmd=0x%08X prev=0x%08X\n",
627 engine->id, i, j, curr, previous);
628 ret = false;
629 }
630
631 previous = curr;
632 }
633 }
634
635 return ret;
636 }
637
638 static bool check_sorted(int ring_id,
639 const struct drm_i915_reg_descriptor *reg_table,
640 int reg_count)
641 {
642 int i;
643 u32 previous = 0;
644 bool ret = true;
645
646 for (i = 0; i < reg_count; i++) {
647 u32 curr = i915_mmio_reg_offset(reg_table[i].addr);
648
649 if (curr < previous) {
650 DRM_ERROR("CMD: table not sorted ring=%d entry=%d reg=0x%08X prev=0x%08X\n",
651 ring_id, i, curr, previous);
652 ret = false;
653 }
654
655 previous = curr;
656 }
657
658 return ret;
659 }
660
661 static bool validate_regs_sorted(struct intel_engine_cs *engine)
662 {
663 int i;
664 const struct drm_i915_reg_table *table;
665
666 for (i = 0; i < engine->reg_table_count; i++) {
667 table = &engine->reg_tables[i];
668 if (!check_sorted(engine->id, table->regs, table->num_regs))
669 return false;
670 }
671
672 return true;
673 }
674
675 struct cmd_node {
676 const struct drm_i915_cmd_descriptor *desc;
677 struct hlist_node node;
678 };
679
680 /*
681 * Different command ranges have different numbers of bits for the opcode. For
682 * example, MI commands use bits 31:23 while 3D commands use bits 31:16. The
683 * problem is that, for example, MI commands use bits 22:16 for other fields
684 * such as GGTT vs PPGTT bits. If we include those bits in the mask then when
685 * we mask a command from a batch it could hash to the wrong bucket due to
686 * non-opcode bits being set. But if we don't include those bits, some 3D
687 * commands may hash to the same bucket due to not including opcode bits that
688 * make the command unique. For now, we will risk hashing to the same bucket.
689 *
690 * If we attempt to generate a perfect hash, we should be able to look at bits
691 * 31:29 of a command from a batch buffer and use the full mask for that
692 * client. The existing INSTR_CLIENT_MASK/SHIFT defines can be used for this.
693 */
694 #define CMD_HASH_MASK STD_MI_OPCODE_MASK
695
696 static int init_hash_table(struct intel_engine_cs *engine,
697 const struct drm_i915_cmd_table *cmd_tables,
698 int cmd_table_count)
699 {
700 int i, j;
701
702 hash_init(engine->cmd_hash);
703
704 for (i = 0; i < cmd_table_count; i++) {
705 const struct drm_i915_cmd_table *table = &cmd_tables[i];
706
707 for (j = 0; j < table->count; j++) {
708 const struct drm_i915_cmd_descriptor *desc =
709 &table->table[j];
710 struct cmd_node *desc_node =
711 kmalloc(sizeof(*desc_node), GFP_KERNEL);
712
713 if (!desc_node)
714 return -ENOMEM;
715
716 desc_node->desc = desc;
717 hash_add(engine->cmd_hash, &desc_node->node,
718 desc->cmd.value & CMD_HASH_MASK);
719 }
720 }
721
722 return 0;
723 }
724
725 static void fini_hash_table(struct intel_engine_cs *engine)
726 {
727 struct hlist_node *tmp;
728 struct cmd_node *desc_node;
729 int i;
730
731 hash_for_each_safe(engine->cmd_hash, i, tmp, desc_node, node) {
732 hash_del(&desc_node->node);
733 kfree(desc_node);
734 }
735 }
736
737 /**
738 * i915_cmd_parser_init_ring() - set cmd parser related fields for a ringbuffer
739 * @ring: the ringbuffer to initialize
740 *
741 * Optionally initializes fields related to batch buffer command parsing in the
742 * struct intel_engine_cs based on whether the platform requires software
743 * command parsing.
744 *
745 * Return: non-zero if initialization fails
746 */
747 int i915_cmd_parser_init_ring(struct intel_engine_cs *engine)
748 {
749 const struct drm_i915_cmd_table *cmd_tables;
750 int cmd_table_count;
751 int ret;
752
753 if (!IS_GEN7(engine->dev))
754 return 0;
755
756 switch (engine->id) {
757 case RCS:
758 if (IS_HASWELL(engine->dev)) {
759 cmd_tables = hsw_render_ring_cmds;
760 cmd_table_count =
761 ARRAY_SIZE(hsw_render_ring_cmds);
762 } else {
763 cmd_tables = gen7_render_cmds;
764 cmd_table_count = ARRAY_SIZE(gen7_render_cmds);
765 }
766
767 if (IS_HASWELL(engine->dev)) {
768 engine->reg_tables = hsw_render_reg_tables;
769 engine->reg_table_count = ARRAY_SIZE(hsw_render_reg_tables);
770 } else {
771 engine->reg_tables = ivb_render_reg_tables;
772 engine->reg_table_count = ARRAY_SIZE(ivb_render_reg_tables);
773 }
774
775 engine->get_cmd_length_mask = gen7_render_get_cmd_length_mask;
776 break;
777 case VCS:
778 cmd_tables = gen7_video_cmds;
779 cmd_table_count = ARRAY_SIZE(gen7_video_cmds);
780 engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
781 break;
782 case BCS:
783 if (IS_HASWELL(engine->dev)) {
784 cmd_tables = hsw_blt_ring_cmds;
785 cmd_table_count = ARRAY_SIZE(hsw_blt_ring_cmds);
786 } else {
787 cmd_tables = gen7_blt_cmds;
788 cmd_table_count = ARRAY_SIZE(gen7_blt_cmds);
789 }
790
791 if (IS_HASWELL(engine->dev)) {
792 engine->reg_tables = hsw_blt_reg_tables;
793 engine->reg_table_count = ARRAY_SIZE(hsw_blt_reg_tables);
794 } else {
795 engine->reg_tables = ivb_blt_reg_tables;
796 engine->reg_table_count = ARRAY_SIZE(ivb_blt_reg_tables);
797 }
798
799 engine->get_cmd_length_mask = gen7_blt_get_cmd_length_mask;
800 break;
801 case VECS:
802 cmd_tables = hsw_vebox_cmds;
803 cmd_table_count = ARRAY_SIZE(hsw_vebox_cmds);
804 /* VECS can use the same length_mask function as VCS */
805 engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
806 break;
807 default:
808 DRM_ERROR("CMD: cmd_parser_init with unknown ring: %d\n",
809 engine->id);
810 BUG();
811 }
812
813 BUG_ON(!validate_cmds_sorted(engine, cmd_tables, cmd_table_count));
814 BUG_ON(!validate_regs_sorted(engine));
815
816 WARN_ON(!hash_empty(engine->cmd_hash));
817
818 ret = init_hash_table(engine, cmd_tables, cmd_table_count);
819 if (ret) {
820 DRM_ERROR("CMD: cmd_parser_init failed!\n");
821 fini_hash_table(engine);
822 return ret;
823 }
824
825 engine->needs_cmd_parser = true;
826
827 return 0;
828 }
829
830 /**
831 * i915_cmd_parser_fini_ring() - clean up cmd parser related fields
832 * @ring: the ringbuffer to clean up
833 *
834 * Releases any resources related to command parsing that may have been
835 * initialized for the specified ring.
836 */
837 void i915_cmd_parser_fini_ring(struct intel_engine_cs *engine)
838 {
839 if (!engine->needs_cmd_parser)
840 return;
841
842 fini_hash_table(engine);
843 }
844
845 static const struct drm_i915_cmd_descriptor*
846 find_cmd_in_table(struct intel_engine_cs *engine,
847 u32 cmd_header)
848 {
849 struct cmd_node *desc_node;
850
851 hash_for_each_possible(engine->cmd_hash, desc_node, node,
852 cmd_header & CMD_HASH_MASK) {
853 const struct drm_i915_cmd_descriptor *desc = desc_node->desc;
854 u32 masked_cmd = desc->cmd.mask & cmd_header;
855 u32 masked_value = desc->cmd.value & desc->cmd.mask;
856
857 if (masked_cmd == masked_value)
858 return desc;
859 }
860
861 return NULL;
862 }
863
864 /*
865 * Returns a pointer to a descriptor for the command specified by cmd_header.
866 *
867 * The caller must supply space for a default descriptor via the default_desc
868 * parameter. If no descriptor for the specified command exists in the ring's
869 * command parser tables, this function fills in default_desc based on the
870 * ring's default length encoding and returns default_desc.
871 */
872 static const struct drm_i915_cmd_descriptor*
873 find_cmd(struct intel_engine_cs *engine,
874 u32 cmd_header,
875 struct drm_i915_cmd_descriptor *default_desc)
876 {
877 const struct drm_i915_cmd_descriptor *desc;
878 u32 mask;
879
880 desc = find_cmd_in_table(engine, cmd_header);
881 if (desc)
882 return desc;
883
884 mask = engine->get_cmd_length_mask(cmd_header);
885 if (!mask)
886 return NULL;
887
888 BUG_ON(!default_desc);
889 default_desc->flags = CMD_DESC_SKIP;
890 default_desc->length.mask = mask;
891
892 return default_desc;
893 }
894
895 static const struct drm_i915_reg_descriptor *
896 find_reg(const struct drm_i915_reg_descriptor *table,
897 int count, u32 addr)
898 {
899 int i;
900
901 for (i = 0; i < count; i++) {
902 if (i915_mmio_reg_offset(table[i].addr) == addr)
903 return &table[i];
904 }
905
906 return NULL;
907 }
908
909 static const struct drm_i915_reg_descriptor *
910 find_reg_in_tables(const struct drm_i915_reg_table *tables,
911 int count, bool is_master, u32 addr)
912 {
913 int i;
914 const struct drm_i915_reg_table *table;
915 const struct drm_i915_reg_descriptor *reg;
916
917 for (i = 0; i < count; i++) {
918 table = &tables[i];
919 if (!table->master || is_master) {
920 reg = find_reg(table->regs, table->num_regs,
921 addr);
922 if (reg != NULL)
923 return reg;
924 }
925 }
926
927 return NULL;
928 }
929
930 static u32 *vmap_batch(struct drm_i915_gem_object *obj,
931 unsigned start, unsigned len)
932 {
933 int i;
934 void *addr = NULL;
935 struct sg_page_iter sg_iter;
936 int first_page = start >> PAGE_SHIFT;
937 int last_page = (len + start + 4095) >> PAGE_SHIFT;
938 int npages = last_page - first_page;
939 struct page **pages;
940
941 pages = drm_malloc_ab(npages, sizeof(*pages));
942 if (pages == NULL) {
943 DRM_DEBUG_DRIVER("Failed to get space for pages\n");
944 goto finish;
945 }
946
947 i = 0;
948 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, first_page) {
949 pages[i++] = sg_page_iter_page(&sg_iter);
950 if (i == npages)
951 break;
952 }
953
954 addr = vmap(pages, i, 0, PAGE_KERNEL);
955 if (addr == NULL) {
956 DRM_DEBUG_DRIVER("Failed to vmap pages\n");
957 goto finish;
958 }
959
960 finish:
961 if (pages)
962 drm_free_large(pages);
963 return (u32*)addr;
964 }
965
966 /* Returns a vmap'd pointer to dest_obj, which the caller must unmap */
967 static u32 *copy_batch(struct drm_i915_gem_object *dest_obj,
968 struct drm_i915_gem_object *src_obj,
969 u32 batch_start_offset,
970 u32 batch_len)
971 {
972 int needs_clflush = 0;
973 void *src_base, *src;
974 void *dst = NULL;
975 int ret;
976
977 if (batch_len > dest_obj->base.size ||
978 batch_len + batch_start_offset > src_obj->base.size)
979 return ERR_PTR(-E2BIG);
980
981 if (WARN_ON(dest_obj->pages_pin_count == 0))
982 return ERR_PTR(-ENODEV);
983
984 ret = i915_gem_obj_prepare_shmem_read(src_obj, &needs_clflush);
985 if (ret) {
986 DRM_DEBUG_DRIVER("CMD: failed to prepare shadow batch\n");
987 return ERR_PTR(ret);
988 }
989
990 src_base = vmap_batch(src_obj, batch_start_offset, batch_len);
991 if (!src_base) {
992 DRM_DEBUG_DRIVER("CMD: Failed to vmap batch\n");
993 ret = -ENOMEM;
994 goto unpin_src;
995 }
996
997 ret = i915_gem_object_set_to_cpu_domain(dest_obj, true);
998 if (ret) {
999 DRM_DEBUG_DRIVER("CMD: Failed to set shadow batch to CPU\n");
1000 goto unmap_src;
1001 }
1002
1003 dst = vmap_batch(dest_obj, 0, batch_len);
1004 if (!dst) {
1005 DRM_DEBUG_DRIVER("CMD: Failed to vmap shadow batch\n");
1006 ret = -ENOMEM;
1007 goto unmap_src;
1008 }
1009
1010 src = src_base + offset_in_page(batch_start_offset);
1011 if (needs_clflush)
1012 drm_clflush_virt_range(src, batch_len);
1013
1014 memcpy(dst, src, batch_len);
1015
1016 unmap_src:
1017 vunmap(src_base);
1018 unpin_src:
1019 i915_gem_object_unpin_pages(src_obj);
1020
1021 return ret ? ERR_PTR(ret) : dst;
1022 }
1023
1024 /**
1025 * i915_needs_cmd_parser() - should a given ring use software command parsing?
1026 * @ring: the ring in question
1027 *
1028 * Only certain platforms require software batch buffer command parsing, and
1029 * only when enabled via module parameter.
1030 *
1031 * Return: true if the ring requires software command parsing
1032 */
1033 bool i915_needs_cmd_parser(struct intel_engine_cs *engine)
1034 {
1035 if (!engine->needs_cmd_parser)
1036 return false;
1037
1038 if (!USES_PPGTT(engine->dev))
1039 return false;
1040
1041 return (i915.enable_cmd_parser == 1);
1042 }
1043
1044 static bool check_cmd(const struct intel_engine_cs *engine,
1045 const struct drm_i915_cmd_descriptor *desc,
1046 const u32 *cmd, u32 length,
1047 const bool is_master,
1048 bool *oacontrol_set)
1049 {
1050 if (desc->flags & CMD_DESC_REJECT) {
1051 DRM_DEBUG_DRIVER("CMD: Rejected command: 0x%08X\n", *cmd);
1052 return false;
1053 }
1054
1055 if ((desc->flags & CMD_DESC_MASTER) && !is_master) {
1056 DRM_DEBUG_DRIVER("CMD: Rejected master-only command: 0x%08X\n",
1057 *cmd);
1058 return false;
1059 }
1060
1061 if (desc->flags & CMD_DESC_REGISTER) {
1062 /*
1063 * Get the distance between individual register offset
1064 * fields if the command can perform more than one
1065 * access at a time.
1066 */
1067 const u32 step = desc->reg.step ? desc->reg.step : length;
1068 u32 offset;
1069
1070 for (offset = desc->reg.offset; offset < length;
1071 offset += step) {
1072 const u32 reg_addr = cmd[offset] & desc->reg.mask;
1073 const struct drm_i915_reg_descriptor *reg =
1074 find_reg_in_tables(engine->reg_tables,
1075 engine->reg_table_count,
1076 is_master,
1077 reg_addr);
1078
1079 if (!reg) {
1080 DRM_DEBUG_DRIVER("CMD: Rejected register 0x%08X in command: 0x%08X (ring=%d)\n",
1081 reg_addr, *cmd, engine->id);
1082 return false;
1083 }
1084
1085 /*
1086 * OACONTROL requires some special handling for
1087 * writes. We want to make sure that any batch which
1088 * enables OA also disables it before the end of the
1089 * batch. The goal is to prevent one process from
1090 * snooping on the perf data from another process. To do
1091 * that, we need to check the value that will be written
1092 * to the register. Hence, limit OACONTROL writes to
1093 * only MI_LOAD_REGISTER_IMM commands.
1094 */
1095 if (reg_addr == i915_mmio_reg_offset(OACONTROL)) {
1096 if (desc->cmd.value == MI_LOAD_REGISTER_MEM) {
1097 DRM_DEBUG_DRIVER("CMD: Rejected LRM to OACONTROL\n");
1098 return false;
1099 }
1100
1101 if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1))
1102 *oacontrol_set = (cmd[offset + 1] != 0);
1103 }
1104
1105 /*
1106 * Check the value written to the register against the
1107 * allowed mask/value pair given in the whitelist entry.
1108 */
1109 if (reg->mask) {
1110 if (desc->cmd.value == MI_LOAD_REGISTER_MEM) {
1111 DRM_DEBUG_DRIVER("CMD: Rejected LRM to masked register 0x%08X\n",
1112 reg_addr);
1113 return false;
1114 }
1115
1116 if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1) &&
1117 (offset + 2 > length ||
1118 (cmd[offset + 1] & reg->mask) != reg->value)) {
1119 DRM_DEBUG_DRIVER("CMD: Rejected LRI to masked register 0x%08X\n",
1120 reg_addr);
1121 return false;
1122 }
1123 }
1124 }
1125 }
1126
1127 if (desc->flags & CMD_DESC_BITMASK) {
1128 int i;
1129
1130 for (i = 0; i < MAX_CMD_DESC_BITMASKS; i++) {
1131 u32 dword;
1132
1133 if (desc->bits[i].mask == 0)
1134 break;
1135
1136 if (desc->bits[i].condition_mask != 0) {
1137 u32 offset =
1138 desc->bits[i].condition_offset;
1139 u32 condition = cmd[offset] &
1140 desc->bits[i].condition_mask;
1141
1142 if (condition == 0)
1143 continue;
1144 }
1145
1146 dword = cmd[desc->bits[i].offset] &
1147 desc->bits[i].mask;
1148
1149 if (dword != desc->bits[i].expected) {
1150 DRM_DEBUG_DRIVER("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (ring=%d)\n",
1151 *cmd,
1152 desc->bits[i].mask,
1153 desc->bits[i].expected,
1154 dword, engine->id);
1155 return false;
1156 }
1157 }
1158 }
1159
1160 return true;
1161 }
1162
1163 #define LENGTH_BIAS 2
1164
1165 /**
1166 * i915_parse_cmds() - parse a submitted batch buffer for privilege violations
1167 * @ring: the ring on which the batch is to execute
1168 * @batch_obj: the batch buffer in question
1169 * @shadow_batch_obj: copy of the batch buffer in question
1170 * @batch_start_offset: byte offset in the batch at which execution starts
1171 * @batch_len: length of the commands in batch_obj
1172 * @is_master: is the submitting process the drm master?
1173 *
1174 * Parses the specified batch buffer looking for privilege violations as
1175 * described in the overview.
1176 *
1177 * Return: non-zero if the parser finds violations or otherwise fails; -EACCES
1178 * if the batch appears legal but should use hardware parsing
1179 */
1180 int i915_parse_cmds(struct intel_engine_cs *engine,
1181 struct drm_i915_gem_object *batch_obj,
1182 struct drm_i915_gem_object *shadow_batch_obj,
1183 u32 batch_start_offset,
1184 u32 batch_len,
1185 bool is_master)
1186 {
1187 u32 *cmd, *batch_base, *batch_end;
1188 struct drm_i915_cmd_descriptor default_desc = { 0 };
1189 bool oacontrol_set = false; /* OACONTROL tracking. See check_cmd() */
1190 int ret = 0;
1191
1192 batch_base = copy_batch(shadow_batch_obj, batch_obj,
1193 batch_start_offset, batch_len);
1194 if (IS_ERR(batch_base)) {
1195 DRM_DEBUG_DRIVER("CMD: Failed to copy batch\n");
1196 return PTR_ERR(batch_base);
1197 }
1198
1199 /*
1200 * We use the batch length as size because the shadow object is as
1201 * large or larger and copy_batch() will write MI_NOPs to the extra
1202 * space. Parsing should be faster in some cases this way.
1203 */
1204 batch_end = batch_base + (batch_len / sizeof(*batch_end));
1205
1206 cmd = batch_base;
1207 while (cmd < batch_end) {
1208 const struct drm_i915_cmd_descriptor *desc;
1209 u32 length;
1210
1211 if (*cmd == MI_BATCH_BUFFER_END)
1212 break;
1213
1214 desc = find_cmd(engine, *cmd, &default_desc);
1215 if (!desc) {
1216 DRM_DEBUG_DRIVER("CMD: Unrecognized command: 0x%08X\n",
1217 *cmd);
1218 ret = -EINVAL;
1219 break;
1220 }
1221
1222 /*
1223 * If the batch buffer contains a chained batch, return an
1224 * error that tells the caller to abort and dispatch the
1225 * workload as a non-secure batch.
1226 */
1227 if (desc->cmd.value == MI_BATCH_BUFFER_START) {
1228 ret = -EACCES;
1229 break;
1230 }
1231
1232 if (desc->flags & CMD_DESC_FIXED)
1233 length = desc->length.fixed;
1234 else
1235 length = ((*cmd & desc->length.mask) + LENGTH_BIAS);
1236
1237 if ((batch_end - cmd) < length) {
1238 DRM_DEBUG_DRIVER("CMD: Command length exceeds batch length: 0x%08X length=%u batchlen=%td\n",
1239 *cmd,
1240 length,
1241 batch_end - cmd);
1242 ret = -EINVAL;
1243 break;
1244 }
1245
1246 if (!check_cmd(engine, desc, cmd, length, is_master,
1247 &oacontrol_set)) {
1248 ret = -EINVAL;
1249 break;
1250 }
1251
1252 cmd += length;
1253 }
1254
1255 if (oacontrol_set) {
1256 DRM_DEBUG_DRIVER("CMD: batch set OACONTROL but did not clear it\n");
1257 ret = -EINVAL;
1258 }
1259
1260 if (cmd >= batch_end) {
1261 DRM_DEBUG_DRIVER("CMD: Got to the end of the buffer w/o a BBE cmd!\n");
1262 ret = -EINVAL;
1263 }
1264
1265 vunmap(batch_base);
1266
1267 return ret;
1268 }
1269
1270 /**
1271 * i915_cmd_parser_get_version() - get the cmd parser version number
1272 *
1273 * The cmd parser maintains a simple increasing integer version number suitable
1274 * for passing to userspace clients to determine what operations are permitted.
1275 *
1276 * Return: the current version number of the cmd parser
1277 */
1278 int i915_cmd_parser_get_version(void)
1279 {
1280 /*
1281 * Command parser version history
1282 *
1283 * 1. Initial version. Checks batches and reports violations, but leaves
1284 * hardware parsing enabled (so does not allow new use cases).
1285 * 2. Allow access to the MI_PREDICATE_SRC0 and
1286 * MI_PREDICATE_SRC1 registers.
1287 * 3. Allow access to the GPGPU_THREADS_DISPATCHED register.
1288 * 4. L3 atomic chicken bits of HSW_SCRATCH1 and HSW_ROW_CHICKEN3.
1289 * 5. GPGPU dispatch compute indirect registers.
1290 * 6. TIMESTAMP register and Haswell CS GPR registers
1291 */
1292 return 6;
1293 }
Linux kernel - Deliverables
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