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drm/i915: add interface to simulate gpu hangs
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29 #include <linux/seq_file.h>
30 #include <linux/debugfs.h>
31 #include <linux/slab.h>
32 #include <linux/export.h>
33 #include "drmP.h"
34 #include "drm.h"
35 #include "intel_drv.h"
36 #include "intel_ringbuffer.h"
37 #include "i915_drm.h"
38 #include "i915_drv.h"
39
40 #define DRM_I915_RING_DEBUG 1
41
42
43 #if defined(CONFIG_DEBUG_FS)
44
45 enum {
46 ACTIVE_LIST,
47 FLUSHING_LIST,
48 INACTIVE_LIST,
49 PINNED_LIST,
50 };
51
52 static const char *yesno(int v)
53 {
54 return v ? "yes" : "no";
55 }
56
57 static int i915_capabilities(struct seq_file *m, void *data)
58 {
59 struct drm_info_node *node = (struct drm_info_node *) m->private;
60 struct drm_device *dev = node->minor->dev;
61 const struct intel_device_info *info = INTEL_INFO(dev);
62
63 seq_printf(m, "gen: %d\n", info->gen);
64 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
65 #define B(x) seq_printf(m, #x ": %s\n", yesno(info->x))
66 B(is_mobile);
67 B(is_i85x);
68 B(is_i915g);
69 B(is_i945gm);
70 B(is_g33);
71 B(need_gfx_hws);
72 B(is_g4x);
73 B(is_pineview);
74 B(is_broadwater);
75 B(is_crestline);
76 B(has_fbc);
77 B(has_pipe_cxsr);
78 B(has_hotplug);
79 B(cursor_needs_physical);
80 B(has_overlay);
81 B(overlay_needs_physical);
82 B(supports_tv);
83 B(has_bsd_ring);
84 B(has_blt_ring);
85 B(has_llc);
86 #undef B
87
88 return 0;
89 }
90
91 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
92 {
93 if (obj->user_pin_count > 0)
94 return "P";
95 else if (obj->pin_count > 0)
96 return "p";
97 else
98 return " ";
99 }
100
101 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
102 {
103 switch (obj->tiling_mode) {
104 default:
105 case I915_TILING_NONE: return " ";
106 case I915_TILING_X: return "X";
107 case I915_TILING_Y: return "Y";
108 }
109 }
110
111 static const char *cache_level_str(int type)
112 {
113 switch (type) {
114 case I915_CACHE_NONE: return " uncached";
115 case I915_CACHE_LLC: return " snooped (LLC)";
116 case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)";
117 default: return "";
118 }
119 }
120
121 static void
122 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
123 {
124 seq_printf(m, "%p: %s%s %8zdKiB %04x %04x %d %d%s%s%s",
125 &obj->base,
126 get_pin_flag(obj),
127 get_tiling_flag(obj),
128 obj->base.size / 1024,
129 obj->base.read_domains,
130 obj->base.write_domain,
131 obj->last_rendering_seqno,
132 obj->last_fenced_seqno,
133 cache_level_str(obj->cache_level),
134 obj->dirty ? " dirty" : "",
135 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
136 if (obj->base.name)
137 seq_printf(m, " (name: %d)", obj->base.name);
138 if (obj->fence_reg != I915_FENCE_REG_NONE)
139 seq_printf(m, " (fence: %d)", obj->fence_reg);
140 if (obj->gtt_space != NULL)
141 seq_printf(m, " (gtt offset: %08x, size: %08x)",
142 obj->gtt_offset, (unsigned int)obj->gtt_space->size);
143 if (obj->pin_mappable || obj->fault_mappable) {
144 char s[3], *t = s;
145 if (obj->pin_mappable)
146 *t++ = 'p';
147 if (obj->fault_mappable)
148 *t++ = 'f';
149 *t = '\0';
150 seq_printf(m, " (%s mappable)", s);
151 }
152 if (obj->ring != NULL)
153 seq_printf(m, " (%s)", obj->ring->name);
154 }
155
156 static int i915_gem_object_list_info(struct seq_file *m, void *data)
157 {
158 struct drm_info_node *node = (struct drm_info_node *) m->private;
159 uintptr_t list = (uintptr_t) node->info_ent->data;
160 struct list_head *head;
161 struct drm_device *dev = node->minor->dev;
162 drm_i915_private_t *dev_priv = dev->dev_private;
163 struct drm_i915_gem_object *obj;
164 size_t total_obj_size, total_gtt_size;
165 int count, ret;
166
167 ret = mutex_lock_interruptible(&dev->struct_mutex);
168 if (ret)
169 return ret;
170
171 switch (list) {
172 case ACTIVE_LIST:
173 seq_printf(m, "Active:\n");
174 head = &dev_priv->mm.active_list;
175 break;
176 case INACTIVE_LIST:
177 seq_printf(m, "Inactive:\n");
178 head = &dev_priv->mm.inactive_list;
179 break;
180 case FLUSHING_LIST:
181 seq_printf(m, "Flushing:\n");
182 head = &dev_priv->mm.flushing_list;
183 break;
184 default:
185 mutex_unlock(&dev->struct_mutex);
186 return -EINVAL;
187 }
188
189 total_obj_size = total_gtt_size = count = 0;
190 list_for_each_entry(obj, head, mm_list) {
191 seq_printf(m, " ");
192 describe_obj(m, obj);
193 seq_printf(m, "\n");
194 total_obj_size += obj->base.size;
195 total_gtt_size += obj->gtt_space->size;
196 count++;
197 }
198 mutex_unlock(&dev->struct_mutex);
199
200 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
201 count, total_obj_size, total_gtt_size);
202 return 0;
203 }
204
205 #define count_objects(list, member) do { \
206 list_for_each_entry(obj, list, member) { \
207 size += obj->gtt_space->size; \
208 ++count; \
209 if (obj->map_and_fenceable) { \
210 mappable_size += obj->gtt_space->size; \
211 ++mappable_count; \
212 } \
213 } \
214 } while (0)
215
216 static int i915_gem_object_info(struct seq_file *m, void* data)
217 {
218 struct drm_info_node *node = (struct drm_info_node *) m->private;
219 struct drm_device *dev = node->minor->dev;
220 struct drm_i915_private *dev_priv = dev->dev_private;
221 u32 count, mappable_count;
222 size_t size, mappable_size;
223 struct drm_i915_gem_object *obj;
224 int ret;
225
226 ret = mutex_lock_interruptible(&dev->struct_mutex);
227 if (ret)
228 return ret;
229
230 seq_printf(m, "%u objects, %zu bytes\n",
231 dev_priv->mm.object_count,
232 dev_priv->mm.object_memory);
233
234 size = count = mappable_size = mappable_count = 0;
235 count_objects(&dev_priv->mm.gtt_list, gtt_list);
236 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
237 count, mappable_count, size, mappable_size);
238
239 size = count = mappable_size = mappable_count = 0;
240 count_objects(&dev_priv->mm.active_list, mm_list);
241 count_objects(&dev_priv->mm.flushing_list, mm_list);
242 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
243 count, mappable_count, size, mappable_size);
244
245 size = count = mappable_size = mappable_count = 0;
246 count_objects(&dev_priv->mm.inactive_list, mm_list);
247 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
248 count, mappable_count, size, mappable_size);
249
250 size = count = mappable_size = mappable_count = 0;
251 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
252 if (obj->fault_mappable) {
253 size += obj->gtt_space->size;
254 ++count;
255 }
256 if (obj->pin_mappable) {
257 mappable_size += obj->gtt_space->size;
258 ++mappable_count;
259 }
260 }
261 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
262 mappable_count, mappable_size);
263 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
264 count, size);
265
266 seq_printf(m, "%zu [%zu] gtt total\n",
267 dev_priv->mm.gtt_total, dev_priv->mm.mappable_gtt_total);
268
269 mutex_unlock(&dev->struct_mutex);
270
271 return 0;
272 }
273
274 static int i915_gem_gtt_info(struct seq_file *m, void* data)
275 {
276 struct drm_info_node *node = (struct drm_info_node *) m->private;
277 struct drm_device *dev = node->minor->dev;
278 uintptr_t list = (uintptr_t) node->info_ent->data;
279 struct drm_i915_private *dev_priv = dev->dev_private;
280 struct drm_i915_gem_object *obj;
281 size_t total_obj_size, total_gtt_size;
282 int count, ret;
283
284 ret = mutex_lock_interruptible(&dev->struct_mutex);
285 if (ret)
286 return ret;
287
288 total_obj_size = total_gtt_size = count = 0;
289 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
290 if (list == PINNED_LIST && obj->pin_count == 0)
291 continue;
292
293 seq_printf(m, " ");
294 describe_obj(m, obj);
295 seq_printf(m, "\n");
296 total_obj_size += obj->base.size;
297 total_gtt_size += obj->gtt_space->size;
298 count++;
299 }
300
301 mutex_unlock(&dev->struct_mutex);
302
303 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
304 count, total_obj_size, total_gtt_size);
305
306 return 0;
307 }
308
309 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
310 {
311 struct drm_info_node *node = (struct drm_info_node *) m->private;
312 struct drm_device *dev = node->minor->dev;
313 unsigned long flags;
314 struct intel_crtc *crtc;
315
316 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
317 const char pipe = pipe_name(crtc->pipe);
318 const char plane = plane_name(crtc->plane);
319 struct intel_unpin_work *work;
320
321 spin_lock_irqsave(&dev->event_lock, flags);
322 work = crtc->unpin_work;
323 if (work == NULL) {
324 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
325 pipe, plane);
326 } else {
327 if (!work->pending) {
328 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
329 pipe, plane);
330 } else {
331 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
332 pipe, plane);
333 }
334 if (work->enable_stall_check)
335 seq_printf(m, "Stall check enabled, ");
336 else
337 seq_printf(m, "Stall check waiting for page flip ioctl, ");
338 seq_printf(m, "%d prepares\n", work->pending);
339
340 if (work->old_fb_obj) {
341 struct drm_i915_gem_object *obj = work->old_fb_obj;
342 if (obj)
343 seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
344 }
345 if (work->pending_flip_obj) {
346 struct drm_i915_gem_object *obj = work->pending_flip_obj;
347 if (obj)
348 seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
349 }
350 }
351 spin_unlock_irqrestore(&dev->event_lock, flags);
352 }
353
354 return 0;
355 }
356
357 static int i915_gem_request_info(struct seq_file *m, void *data)
358 {
359 struct drm_info_node *node = (struct drm_info_node *) m->private;
360 struct drm_device *dev = node->minor->dev;
361 drm_i915_private_t *dev_priv = dev->dev_private;
362 struct drm_i915_gem_request *gem_request;
363 int ret, count;
364
365 ret = mutex_lock_interruptible(&dev->struct_mutex);
366 if (ret)
367 return ret;
368
369 count = 0;
370 if (!list_empty(&dev_priv->ring[RCS].request_list)) {
371 seq_printf(m, "Render requests:\n");
372 list_for_each_entry(gem_request,
373 &dev_priv->ring[RCS].request_list,
374 list) {
375 seq_printf(m, " %d @ %d\n",
376 gem_request->seqno,
377 (int) (jiffies - gem_request->emitted_jiffies));
378 }
379 count++;
380 }
381 if (!list_empty(&dev_priv->ring[VCS].request_list)) {
382 seq_printf(m, "BSD requests:\n");
383 list_for_each_entry(gem_request,
384 &dev_priv->ring[VCS].request_list,
385 list) {
386 seq_printf(m, " %d @ %d\n",
387 gem_request->seqno,
388 (int) (jiffies - gem_request->emitted_jiffies));
389 }
390 count++;
391 }
392 if (!list_empty(&dev_priv->ring[BCS].request_list)) {
393 seq_printf(m, "BLT requests:\n");
394 list_for_each_entry(gem_request,
395 &dev_priv->ring[BCS].request_list,
396 list) {
397 seq_printf(m, " %d @ %d\n",
398 gem_request->seqno,
399 (int) (jiffies - gem_request->emitted_jiffies));
400 }
401 count++;
402 }
403 mutex_unlock(&dev->struct_mutex);
404
405 if (count == 0)
406 seq_printf(m, "No requests\n");
407
408 return 0;
409 }
410
411 static void i915_ring_seqno_info(struct seq_file *m,
412 struct intel_ring_buffer *ring)
413 {
414 if (ring->get_seqno) {
415 seq_printf(m, "Current sequence (%s): %d\n",
416 ring->name, ring->get_seqno(ring));
417 }
418 }
419
420 static int i915_gem_seqno_info(struct seq_file *m, void *data)
421 {
422 struct drm_info_node *node = (struct drm_info_node *) m->private;
423 struct drm_device *dev = node->minor->dev;
424 drm_i915_private_t *dev_priv = dev->dev_private;
425 int ret, i;
426
427 ret = mutex_lock_interruptible(&dev->struct_mutex);
428 if (ret)
429 return ret;
430
431 for (i = 0; i < I915_NUM_RINGS; i++)
432 i915_ring_seqno_info(m, &dev_priv->ring[i]);
433
434 mutex_unlock(&dev->struct_mutex);
435
436 return 0;
437 }
438
439
440 static int i915_interrupt_info(struct seq_file *m, void *data)
441 {
442 struct drm_info_node *node = (struct drm_info_node *) m->private;
443 struct drm_device *dev = node->minor->dev;
444 drm_i915_private_t *dev_priv = dev->dev_private;
445 int ret, i, pipe;
446
447 ret = mutex_lock_interruptible(&dev->struct_mutex);
448 if (ret)
449 return ret;
450
451 if (IS_VALLEYVIEW(dev)) {
452 seq_printf(m, "Display IER:\t%08x\n",
453 I915_READ(VLV_IER));
454 seq_printf(m, "Display IIR:\t%08x\n",
455 I915_READ(VLV_IIR));
456 seq_printf(m, "Display IIR_RW:\t%08x\n",
457 I915_READ(VLV_IIR_RW));
458 seq_printf(m, "Display IMR:\t%08x\n",
459 I915_READ(VLV_IMR));
460 for_each_pipe(pipe)
461 seq_printf(m, "Pipe %c stat:\t%08x\n",
462 pipe_name(pipe),
463 I915_READ(PIPESTAT(pipe)));
464
465 seq_printf(m, "Master IER:\t%08x\n",
466 I915_READ(VLV_MASTER_IER));
467
468 seq_printf(m, "Render IER:\t%08x\n",
469 I915_READ(GTIER));
470 seq_printf(m, "Render IIR:\t%08x\n",
471 I915_READ(GTIIR));
472 seq_printf(m, "Render IMR:\t%08x\n",
473 I915_READ(GTIMR));
474
475 seq_printf(m, "PM IER:\t\t%08x\n",
476 I915_READ(GEN6_PMIER));
477 seq_printf(m, "PM IIR:\t\t%08x\n",
478 I915_READ(GEN6_PMIIR));
479 seq_printf(m, "PM IMR:\t\t%08x\n",
480 I915_READ(GEN6_PMIMR));
481
482 seq_printf(m, "Port hotplug:\t%08x\n",
483 I915_READ(PORT_HOTPLUG_EN));
484 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
485 I915_READ(VLV_DPFLIPSTAT));
486 seq_printf(m, "DPINVGTT:\t%08x\n",
487 I915_READ(DPINVGTT));
488
489 } else if (!HAS_PCH_SPLIT(dev)) {
490 seq_printf(m, "Interrupt enable: %08x\n",
491 I915_READ(IER));
492 seq_printf(m, "Interrupt identity: %08x\n",
493 I915_READ(IIR));
494 seq_printf(m, "Interrupt mask: %08x\n",
495 I915_READ(IMR));
496 for_each_pipe(pipe)
497 seq_printf(m, "Pipe %c stat: %08x\n",
498 pipe_name(pipe),
499 I915_READ(PIPESTAT(pipe)));
500 } else {
501 seq_printf(m, "North Display Interrupt enable: %08x\n",
502 I915_READ(DEIER));
503 seq_printf(m, "North Display Interrupt identity: %08x\n",
504 I915_READ(DEIIR));
505 seq_printf(m, "North Display Interrupt mask: %08x\n",
506 I915_READ(DEIMR));
507 seq_printf(m, "South Display Interrupt enable: %08x\n",
508 I915_READ(SDEIER));
509 seq_printf(m, "South Display Interrupt identity: %08x\n",
510 I915_READ(SDEIIR));
511 seq_printf(m, "South Display Interrupt mask: %08x\n",
512 I915_READ(SDEIMR));
513 seq_printf(m, "Graphics Interrupt enable: %08x\n",
514 I915_READ(GTIER));
515 seq_printf(m, "Graphics Interrupt identity: %08x\n",
516 I915_READ(GTIIR));
517 seq_printf(m, "Graphics Interrupt mask: %08x\n",
518 I915_READ(GTIMR));
519 }
520 seq_printf(m, "Interrupts received: %d\n",
521 atomic_read(&dev_priv->irq_received));
522 for (i = 0; i < I915_NUM_RINGS; i++) {
523 if (IS_GEN6(dev) || IS_GEN7(dev)) {
524 seq_printf(m, "Graphics Interrupt mask (%s): %08x\n",
525 dev_priv->ring[i].name,
526 I915_READ_IMR(&dev_priv->ring[i]));
527 }
528 i915_ring_seqno_info(m, &dev_priv->ring[i]);
529 }
530 mutex_unlock(&dev->struct_mutex);
531
532 return 0;
533 }
534
535 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
536 {
537 struct drm_info_node *node = (struct drm_info_node *) m->private;
538 struct drm_device *dev = node->minor->dev;
539 drm_i915_private_t *dev_priv = dev->dev_private;
540 int i, ret;
541
542 ret = mutex_lock_interruptible(&dev->struct_mutex);
543 if (ret)
544 return ret;
545
546 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
547 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
548 for (i = 0; i < dev_priv->num_fence_regs; i++) {
549 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
550
551 seq_printf(m, "Fenced object[%2d] = ", i);
552 if (obj == NULL)
553 seq_printf(m, "unused");
554 else
555 describe_obj(m, obj);
556 seq_printf(m, "\n");
557 }
558
559 mutex_unlock(&dev->struct_mutex);
560 return 0;
561 }
562
563 static int i915_hws_info(struct seq_file *m, void *data)
564 {
565 struct drm_info_node *node = (struct drm_info_node *) m->private;
566 struct drm_device *dev = node->minor->dev;
567 drm_i915_private_t *dev_priv = dev->dev_private;
568 struct intel_ring_buffer *ring;
569 const volatile u32 __iomem *hws;
570 int i;
571
572 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
573 hws = (volatile u32 __iomem *)ring->status_page.page_addr;
574 if (hws == NULL)
575 return 0;
576
577 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
578 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
579 i * 4,
580 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
581 }
582 return 0;
583 }
584
585 static const char *ring_str(int ring)
586 {
587 switch (ring) {
588 case RCS: return "render";
589 case VCS: return "bsd";
590 case BCS: return "blt";
591 default: return "";
592 }
593 }
594
595 static const char *pin_flag(int pinned)
596 {
597 if (pinned > 0)
598 return " P";
599 else if (pinned < 0)
600 return " p";
601 else
602 return "";
603 }
604
605 static const char *tiling_flag(int tiling)
606 {
607 switch (tiling) {
608 default:
609 case I915_TILING_NONE: return "";
610 case I915_TILING_X: return " X";
611 case I915_TILING_Y: return " Y";
612 }
613 }
614
615 static const char *dirty_flag(int dirty)
616 {
617 return dirty ? " dirty" : "";
618 }
619
620 static const char *purgeable_flag(int purgeable)
621 {
622 return purgeable ? " purgeable" : "";
623 }
624
625 static void print_error_buffers(struct seq_file *m,
626 const char *name,
627 struct drm_i915_error_buffer *err,
628 int count)
629 {
630 seq_printf(m, "%s [%d]:\n", name, count);
631
632 while (count--) {
633 seq_printf(m, " %08x %8u %04x %04x %08x%s%s%s%s%s%s%s",
634 err->gtt_offset,
635 err->size,
636 err->read_domains,
637 err->write_domain,
638 err->seqno,
639 pin_flag(err->pinned),
640 tiling_flag(err->tiling),
641 dirty_flag(err->dirty),
642 purgeable_flag(err->purgeable),
643 err->ring != -1 ? " " : "",
644 ring_str(err->ring),
645 cache_level_str(err->cache_level));
646
647 if (err->name)
648 seq_printf(m, " (name: %d)", err->name);
649 if (err->fence_reg != I915_FENCE_REG_NONE)
650 seq_printf(m, " (fence: %d)", err->fence_reg);
651
652 seq_printf(m, "\n");
653 err++;
654 }
655 }
656
657 static void i915_ring_error_state(struct seq_file *m,
658 struct drm_device *dev,
659 struct drm_i915_error_state *error,
660 unsigned ring)
661 {
662 BUG_ON(ring >= I915_NUM_RINGS); /* shut up confused gcc */
663 seq_printf(m, "%s command stream:\n", ring_str(ring));
664 seq_printf(m, " HEAD: 0x%08x\n", error->head[ring]);
665 seq_printf(m, " TAIL: 0x%08x\n", error->tail[ring]);
666 seq_printf(m, " ACTHD: 0x%08x\n", error->acthd[ring]);
667 seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]);
668 seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]);
669 seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone[ring]);
670 if (ring == RCS && INTEL_INFO(dev)->gen >= 4) {
671 seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1);
672 seq_printf(m, " BBADDR: 0x%08llx\n", error->bbaddr);
673 }
674 if (INTEL_INFO(dev)->gen >= 4)
675 seq_printf(m, " INSTPS: 0x%08x\n", error->instps[ring]);
676 seq_printf(m, " INSTPM: 0x%08x\n", error->instpm[ring]);
677 seq_printf(m, " FADDR: 0x%08x\n", error->faddr[ring]);
678 if (INTEL_INFO(dev)->gen >= 6) {
679 seq_printf(m, " FAULT_REG: 0x%08x\n", error->fault_reg[ring]);
680 seq_printf(m, " SYNC_0: 0x%08x\n",
681 error->semaphore_mboxes[ring][0]);
682 seq_printf(m, " SYNC_1: 0x%08x\n",
683 error->semaphore_mboxes[ring][1]);
684 }
685 seq_printf(m, " seqno: 0x%08x\n", error->seqno[ring]);
686 seq_printf(m, " waiting: %s\n", yesno(error->waiting[ring]));
687 seq_printf(m, " ring->head: 0x%08x\n", error->cpu_ring_head[ring]);
688 seq_printf(m, " ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]);
689 }
690
691 static int i915_error_state(struct seq_file *m, void *unused)
692 {
693 struct drm_info_node *node = (struct drm_info_node *) m->private;
694 struct drm_device *dev = node->minor->dev;
695 drm_i915_private_t *dev_priv = dev->dev_private;
696 struct drm_i915_error_state *error;
697 unsigned long flags;
698 int i, j, page, offset, elt;
699
700 spin_lock_irqsave(&dev_priv->error_lock, flags);
701 if (!dev_priv->first_error) {
702 seq_printf(m, "no error state collected\n");
703 goto out;
704 }
705
706 error = dev_priv->first_error;
707
708 seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
709 error->time.tv_usec);
710 seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
711 seq_printf(m, "EIR: 0x%08x\n", error->eir);
712 seq_printf(m, "IER: 0x%08x\n", error->ier);
713 seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
714
715 for (i = 0; i < dev_priv->num_fence_regs; i++)
716 seq_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
717
718 if (INTEL_INFO(dev)->gen >= 6) {
719 seq_printf(m, "ERROR: 0x%08x\n", error->error);
720 seq_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
721 }
722
723 i915_ring_error_state(m, dev, error, RCS);
724 if (HAS_BLT(dev))
725 i915_ring_error_state(m, dev, error, BCS);
726 if (HAS_BSD(dev))
727 i915_ring_error_state(m, dev, error, VCS);
728
729 if (error->active_bo)
730 print_error_buffers(m, "Active",
731 error->active_bo,
732 error->active_bo_count);
733
734 if (error->pinned_bo)
735 print_error_buffers(m, "Pinned",
736 error->pinned_bo,
737 error->pinned_bo_count);
738
739 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
740 struct drm_i915_error_object *obj;
741
742 if ((obj = error->ring[i].batchbuffer)) {
743 seq_printf(m, "%s --- gtt_offset = 0x%08x\n",
744 dev_priv->ring[i].name,
745 obj->gtt_offset);
746 offset = 0;
747 for (page = 0; page < obj->page_count; page++) {
748 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
749 seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]);
750 offset += 4;
751 }
752 }
753 }
754
755 if (error->ring[i].num_requests) {
756 seq_printf(m, "%s --- %d requests\n",
757 dev_priv->ring[i].name,
758 error->ring[i].num_requests);
759 for (j = 0; j < error->ring[i].num_requests; j++) {
760 seq_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
761 error->ring[i].requests[j].seqno,
762 error->ring[i].requests[j].jiffies,
763 error->ring[i].requests[j].tail);
764 }
765 }
766
767 if ((obj = error->ring[i].ringbuffer)) {
768 seq_printf(m, "%s --- ringbuffer = 0x%08x\n",
769 dev_priv->ring[i].name,
770 obj->gtt_offset);
771 offset = 0;
772 for (page = 0; page < obj->page_count; page++) {
773 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
774 seq_printf(m, "%08x : %08x\n",
775 offset,
776 obj->pages[page][elt]);
777 offset += 4;
778 }
779 }
780 }
781 }
782
783 if (error->overlay)
784 intel_overlay_print_error_state(m, error->overlay);
785
786 if (error->display)
787 intel_display_print_error_state(m, dev, error->display);
788
789 out:
790 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
791
792 return 0;
793 }
794
795 static int i915_rstdby_delays(struct seq_file *m, void *unused)
796 {
797 struct drm_info_node *node = (struct drm_info_node *) m->private;
798 struct drm_device *dev = node->minor->dev;
799 drm_i915_private_t *dev_priv = dev->dev_private;
800 u16 crstanddelay;
801 int ret;
802
803 ret = mutex_lock_interruptible(&dev->struct_mutex);
804 if (ret)
805 return ret;
806
807 crstanddelay = I915_READ16(CRSTANDVID);
808
809 mutex_unlock(&dev->struct_mutex);
810
811 seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
812
813 return 0;
814 }
815
816 static int i915_cur_delayinfo(struct seq_file *m, void *unused)
817 {
818 struct drm_info_node *node = (struct drm_info_node *) m->private;
819 struct drm_device *dev = node->minor->dev;
820 drm_i915_private_t *dev_priv = dev->dev_private;
821 int ret;
822
823 if (IS_GEN5(dev)) {
824 u16 rgvswctl = I915_READ16(MEMSWCTL);
825 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
826
827 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
828 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
829 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
830 MEMSTAT_VID_SHIFT);
831 seq_printf(m, "Current P-state: %d\n",
832 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
833 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
834 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
835 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
836 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
837 u32 rpstat;
838 u32 rpupei, rpcurup, rpprevup;
839 u32 rpdownei, rpcurdown, rpprevdown;
840 int max_freq;
841
842 /* RPSTAT1 is in the GT power well */
843 ret = mutex_lock_interruptible(&dev->struct_mutex);
844 if (ret)
845 return ret;
846
847 gen6_gt_force_wake_get(dev_priv);
848
849 rpstat = I915_READ(GEN6_RPSTAT1);
850 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
851 rpcurup = I915_READ(GEN6_RP_CUR_UP);
852 rpprevup = I915_READ(GEN6_RP_PREV_UP);
853 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
854 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
855 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
856
857 gen6_gt_force_wake_put(dev_priv);
858 mutex_unlock(&dev->struct_mutex);
859
860 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
861 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
862 seq_printf(m, "Render p-state ratio: %d\n",
863 (gt_perf_status & 0xff00) >> 8);
864 seq_printf(m, "Render p-state VID: %d\n",
865 gt_perf_status & 0xff);
866 seq_printf(m, "Render p-state limit: %d\n",
867 rp_state_limits & 0xff);
868 seq_printf(m, "CAGF: %dMHz\n", ((rpstat & GEN6_CAGF_MASK) >>
869 GEN6_CAGF_SHIFT) * 50);
870 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
871 GEN6_CURICONT_MASK);
872 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
873 GEN6_CURBSYTAVG_MASK);
874 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
875 GEN6_CURBSYTAVG_MASK);
876 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
877 GEN6_CURIAVG_MASK);
878 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
879 GEN6_CURBSYTAVG_MASK);
880 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
881 GEN6_CURBSYTAVG_MASK);
882
883 max_freq = (rp_state_cap & 0xff0000) >> 16;
884 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
885 max_freq * 50);
886
887 max_freq = (rp_state_cap & 0xff00) >> 8;
888 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
889 max_freq * 50);
890
891 max_freq = rp_state_cap & 0xff;
892 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
893 max_freq * 50);
894 } else {
895 seq_printf(m, "no P-state info available\n");
896 }
897
898 return 0;
899 }
900
901 static int i915_delayfreq_table(struct seq_file *m, void *unused)
902 {
903 struct drm_info_node *node = (struct drm_info_node *) m->private;
904 struct drm_device *dev = node->minor->dev;
905 drm_i915_private_t *dev_priv = dev->dev_private;
906 u32 delayfreq;
907 int ret, i;
908
909 ret = mutex_lock_interruptible(&dev->struct_mutex);
910 if (ret)
911 return ret;
912
913 for (i = 0; i < 16; i++) {
914 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
915 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
916 (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
917 }
918
919 mutex_unlock(&dev->struct_mutex);
920
921 return 0;
922 }
923
924 static inline int MAP_TO_MV(int map)
925 {
926 return 1250 - (map * 25);
927 }
928
929 static int i915_inttoext_table(struct seq_file *m, void *unused)
930 {
931 struct drm_info_node *node = (struct drm_info_node *) m->private;
932 struct drm_device *dev = node->minor->dev;
933 drm_i915_private_t *dev_priv = dev->dev_private;
934 u32 inttoext;
935 int ret, i;
936
937 ret = mutex_lock_interruptible(&dev->struct_mutex);
938 if (ret)
939 return ret;
940
941 for (i = 1; i <= 32; i++) {
942 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
943 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
944 }
945
946 mutex_unlock(&dev->struct_mutex);
947
948 return 0;
949 }
950
951 static int ironlake_drpc_info(struct seq_file *m)
952 {
953 struct drm_info_node *node = (struct drm_info_node *) m->private;
954 struct drm_device *dev = node->minor->dev;
955 drm_i915_private_t *dev_priv = dev->dev_private;
956 u32 rgvmodectl, rstdbyctl;
957 u16 crstandvid;
958 int ret;
959
960 ret = mutex_lock_interruptible(&dev->struct_mutex);
961 if (ret)
962 return ret;
963
964 rgvmodectl = I915_READ(MEMMODECTL);
965 rstdbyctl = I915_READ(RSTDBYCTL);
966 crstandvid = I915_READ16(CRSTANDVID);
967
968 mutex_unlock(&dev->struct_mutex);
969
970 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
971 "yes" : "no");
972 seq_printf(m, "Boost freq: %d\n",
973 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
974 MEMMODE_BOOST_FREQ_SHIFT);
975 seq_printf(m, "HW control enabled: %s\n",
976 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
977 seq_printf(m, "SW control enabled: %s\n",
978 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
979 seq_printf(m, "Gated voltage change: %s\n",
980 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
981 seq_printf(m, "Starting frequency: P%d\n",
982 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
983 seq_printf(m, "Max P-state: P%d\n",
984 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
985 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
986 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
987 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
988 seq_printf(m, "Render standby enabled: %s\n",
989 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
990 seq_printf(m, "Current RS state: ");
991 switch (rstdbyctl & RSX_STATUS_MASK) {
992 case RSX_STATUS_ON:
993 seq_printf(m, "on\n");
994 break;
995 case RSX_STATUS_RC1:
996 seq_printf(m, "RC1\n");
997 break;
998 case RSX_STATUS_RC1E:
999 seq_printf(m, "RC1E\n");
1000 break;
1001 case RSX_STATUS_RS1:
1002 seq_printf(m, "RS1\n");
1003 break;
1004 case RSX_STATUS_RS2:
1005 seq_printf(m, "RS2 (RC6)\n");
1006 break;
1007 case RSX_STATUS_RS3:
1008 seq_printf(m, "RC3 (RC6+)\n");
1009 break;
1010 default:
1011 seq_printf(m, "unknown\n");
1012 break;
1013 }
1014
1015 return 0;
1016 }
1017
1018 static int gen6_drpc_info(struct seq_file *m)
1019 {
1020
1021 struct drm_info_node *node = (struct drm_info_node *) m->private;
1022 struct drm_device *dev = node->minor->dev;
1023 struct drm_i915_private *dev_priv = dev->dev_private;
1024 u32 rpmodectl1, gt_core_status, rcctl1;
1025 unsigned forcewake_count;
1026 int count=0, ret;
1027
1028
1029 ret = mutex_lock_interruptible(&dev->struct_mutex);
1030 if (ret)
1031 return ret;
1032
1033 spin_lock_irq(&dev_priv->gt_lock);
1034 forcewake_count = dev_priv->forcewake_count;
1035 spin_unlock_irq(&dev_priv->gt_lock);
1036
1037 if (forcewake_count) {
1038 seq_printf(m, "RC information inaccurate because somebody "
1039 "holds a forcewake reference \n");
1040 } else {
1041 /* NB: we cannot use forcewake, else we read the wrong values */
1042 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1043 udelay(10);
1044 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1045 }
1046
1047 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1048 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4);
1049
1050 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1051 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1052 mutex_unlock(&dev->struct_mutex);
1053
1054 seq_printf(m, "Video Turbo Mode: %s\n",
1055 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1056 seq_printf(m, "HW control enabled: %s\n",
1057 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1058 seq_printf(m, "SW control enabled: %s\n",
1059 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1060 GEN6_RP_MEDIA_SW_MODE));
1061 seq_printf(m, "RC1e Enabled: %s\n",
1062 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1063 seq_printf(m, "RC6 Enabled: %s\n",
1064 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1065 seq_printf(m, "Deep RC6 Enabled: %s\n",
1066 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1067 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1068 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1069 seq_printf(m, "Current RC state: ");
1070 switch (gt_core_status & GEN6_RCn_MASK) {
1071 case GEN6_RC0:
1072 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1073 seq_printf(m, "Core Power Down\n");
1074 else
1075 seq_printf(m, "on\n");
1076 break;
1077 case GEN6_RC3:
1078 seq_printf(m, "RC3\n");
1079 break;
1080 case GEN6_RC6:
1081 seq_printf(m, "RC6\n");
1082 break;
1083 case GEN6_RC7:
1084 seq_printf(m, "RC7\n");
1085 break;
1086 default:
1087 seq_printf(m, "Unknown\n");
1088 break;
1089 }
1090
1091 seq_printf(m, "Core Power Down: %s\n",
1092 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1093
1094 /* Not exactly sure what this is */
1095 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1096 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1097 seq_printf(m, "RC6 residency since boot: %u\n",
1098 I915_READ(GEN6_GT_GFX_RC6));
1099 seq_printf(m, "RC6+ residency since boot: %u\n",
1100 I915_READ(GEN6_GT_GFX_RC6p));
1101 seq_printf(m, "RC6++ residency since boot: %u\n",
1102 I915_READ(GEN6_GT_GFX_RC6pp));
1103
1104 return 0;
1105 }
1106
1107 static int i915_drpc_info(struct seq_file *m, void *unused)
1108 {
1109 struct drm_info_node *node = (struct drm_info_node *) m->private;
1110 struct drm_device *dev = node->minor->dev;
1111
1112 if (IS_GEN6(dev) || IS_GEN7(dev))
1113 return gen6_drpc_info(m);
1114 else
1115 return ironlake_drpc_info(m);
1116 }
1117
1118 static int i915_fbc_status(struct seq_file *m, void *unused)
1119 {
1120 struct drm_info_node *node = (struct drm_info_node *) m->private;
1121 struct drm_device *dev = node->minor->dev;
1122 drm_i915_private_t *dev_priv = dev->dev_private;
1123
1124 if (!I915_HAS_FBC(dev)) {
1125 seq_printf(m, "FBC unsupported on this chipset\n");
1126 return 0;
1127 }
1128
1129 if (intel_fbc_enabled(dev)) {
1130 seq_printf(m, "FBC enabled\n");
1131 } else {
1132 seq_printf(m, "FBC disabled: ");
1133 switch (dev_priv->no_fbc_reason) {
1134 case FBC_NO_OUTPUT:
1135 seq_printf(m, "no outputs");
1136 break;
1137 case FBC_STOLEN_TOO_SMALL:
1138 seq_printf(m, "not enough stolen memory");
1139 break;
1140 case FBC_UNSUPPORTED_MODE:
1141 seq_printf(m, "mode not supported");
1142 break;
1143 case FBC_MODE_TOO_LARGE:
1144 seq_printf(m, "mode too large");
1145 break;
1146 case FBC_BAD_PLANE:
1147 seq_printf(m, "FBC unsupported on plane");
1148 break;
1149 case FBC_NOT_TILED:
1150 seq_printf(m, "scanout buffer not tiled");
1151 break;
1152 case FBC_MULTIPLE_PIPES:
1153 seq_printf(m, "multiple pipes are enabled");
1154 break;
1155 case FBC_MODULE_PARAM:
1156 seq_printf(m, "disabled per module param (default off)");
1157 break;
1158 default:
1159 seq_printf(m, "unknown reason");
1160 }
1161 seq_printf(m, "\n");
1162 }
1163 return 0;
1164 }
1165
1166 static int i915_sr_status(struct seq_file *m, void *unused)
1167 {
1168 struct drm_info_node *node = (struct drm_info_node *) m->private;
1169 struct drm_device *dev = node->minor->dev;
1170 drm_i915_private_t *dev_priv = dev->dev_private;
1171 bool sr_enabled = false;
1172
1173 if (HAS_PCH_SPLIT(dev))
1174 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1175 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1176 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1177 else if (IS_I915GM(dev))
1178 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1179 else if (IS_PINEVIEW(dev))
1180 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1181
1182 seq_printf(m, "self-refresh: %s\n",
1183 sr_enabled ? "enabled" : "disabled");
1184
1185 return 0;
1186 }
1187
1188 static int i915_emon_status(struct seq_file *m, void *unused)
1189 {
1190 struct drm_info_node *node = (struct drm_info_node *) m->private;
1191 struct drm_device *dev = node->minor->dev;
1192 drm_i915_private_t *dev_priv = dev->dev_private;
1193 unsigned long temp, chipset, gfx;
1194 int ret;
1195
1196 if (!IS_GEN5(dev))
1197 return -ENODEV;
1198
1199 ret = mutex_lock_interruptible(&dev->struct_mutex);
1200 if (ret)
1201 return ret;
1202
1203 temp = i915_mch_val(dev_priv);
1204 chipset = i915_chipset_val(dev_priv);
1205 gfx = i915_gfx_val(dev_priv);
1206 mutex_unlock(&dev->struct_mutex);
1207
1208 seq_printf(m, "GMCH temp: %ld\n", temp);
1209 seq_printf(m, "Chipset power: %ld\n", chipset);
1210 seq_printf(m, "GFX power: %ld\n", gfx);
1211 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1212
1213 return 0;
1214 }
1215
1216 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1217 {
1218 struct drm_info_node *node = (struct drm_info_node *) m->private;
1219 struct drm_device *dev = node->minor->dev;
1220 drm_i915_private_t *dev_priv = dev->dev_private;
1221 int ret;
1222 int gpu_freq, ia_freq;
1223
1224 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1225 seq_printf(m, "unsupported on this chipset\n");
1226 return 0;
1227 }
1228
1229 ret = mutex_lock_interruptible(&dev->struct_mutex);
1230 if (ret)
1231 return ret;
1232
1233 seq_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\n");
1234
1235 for (gpu_freq = dev_priv->min_delay; gpu_freq <= dev_priv->max_delay;
1236 gpu_freq++) {
1237 I915_WRITE(GEN6_PCODE_DATA, gpu_freq);
1238 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
1239 GEN6_PCODE_READ_MIN_FREQ_TABLE);
1240 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
1241 GEN6_PCODE_READY) == 0, 10)) {
1242 DRM_ERROR("pcode read of freq table timed out\n");
1243 continue;
1244 }
1245 ia_freq = I915_READ(GEN6_PCODE_DATA);
1246 seq_printf(m, "%d\t\t%d\n", gpu_freq * 50, ia_freq * 100);
1247 }
1248
1249 mutex_unlock(&dev->struct_mutex);
1250
1251 return 0;
1252 }
1253
1254 static int i915_gfxec(struct seq_file *m, void *unused)
1255 {
1256 struct drm_info_node *node = (struct drm_info_node *) m->private;
1257 struct drm_device *dev = node->minor->dev;
1258 drm_i915_private_t *dev_priv = dev->dev_private;
1259 int ret;
1260
1261 ret = mutex_lock_interruptible(&dev->struct_mutex);
1262 if (ret)
1263 return ret;
1264
1265 seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1266
1267 mutex_unlock(&dev->struct_mutex);
1268
1269 return 0;
1270 }
1271
1272 static int i915_opregion(struct seq_file *m, void *unused)
1273 {
1274 struct drm_info_node *node = (struct drm_info_node *) m->private;
1275 struct drm_device *dev = node->minor->dev;
1276 drm_i915_private_t *dev_priv = dev->dev_private;
1277 struct intel_opregion *opregion = &dev_priv->opregion;
1278 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1279 int ret;
1280
1281 if (data == NULL)
1282 return -ENOMEM;
1283
1284 ret = mutex_lock_interruptible(&dev->struct_mutex);
1285 if (ret)
1286 goto out;
1287
1288 if (opregion->header) {
1289 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1290 seq_write(m, data, OPREGION_SIZE);
1291 }
1292
1293 mutex_unlock(&dev->struct_mutex);
1294
1295 out:
1296 kfree(data);
1297 return 0;
1298 }
1299
1300 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1301 {
1302 struct drm_info_node *node = (struct drm_info_node *) m->private;
1303 struct drm_device *dev = node->minor->dev;
1304 drm_i915_private_t *dev_priv = dev->dev_private;
1305 struct intel_fbdev *ifbdev;
1306 struct intel_framebuffer *fb;
1307 int ret;
1308
1309 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1310 if (ret)
1311 return ret;
1312
1313 ifbdev = dev_priv->fbdev;
1314 fb = to_intel_framebuffer(ifbdev->helper.fb);
1315
1316 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ",
1317 fb->base.width,
1318 fb->base.height,
1319 fb->base.depth,
1320 fb->base.bits_per_pixel);
1321 describe_obj(m, fb->obj);
1322 seq_printf(m, "\n");
1323
1324 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1325 if (&fb->base == ifbdev->helper.fb)
1326 continue;
1327
1328 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ",
1329 fb->base.width,
1330 fb->base.height,
1331 fb->base.depth,
1332 fb->base.bits_per_pixel);
1333 describe_obj(m, fb->obj);
1334 seq_printf(m, "\n");
1335 }
1336
1337 mutex_unlock(&dev->mode_config.mutex);
1338
1339 return 0;
1340 }
1341
1342 static int i915_context_status(struct seq_file *m, void *unused)
1343 {
1344 struct drm_info_node *node = (struct drm_info_node *) m->private;
1345 struct drm_device *dev = node->minor->dev;
1346 drm_i915_private_t *dev_priv = dev->dev_private;
1347 int ret;
1348
1349 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1350 if (ret)
1351 return ret;
1352
1353 if (dev_priv->pwrctx) {
1354 seq_printf(m, "power context ");
1355 describe_obj(m, dev_priv->pwrctx);
1356 seq_printf(m, "\n");
1357 }
1358
1359 if (dev_priv->renderctx) {
1360 seq_printf(m, "render context ");
1361 describe_obj(m, dev_priv->renderctx);
1362 seq_printf(m, "\n");
1363 }
1364
1365 mutex_unlock(&dev->mode_config.mutex);
1366
1367 return 0;
1368 }
1369
1370 static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1371 {
1372 struct drm_info_node *node = (struct drm_info_node *) m->private;
1373 struct drm_device *dev = node->minor->dev;
1374 struct drm_i915_private *dev_priv = dev->dev_private;
1375 unsigned forcewake_count;
1376
1377 spin_lock_irq(&dev_priv->gt_lock);
1378 forcewake_count = dev_priv->forcewake_count;
1379 spin_unlock_irq(&dev_priv->gt_lock);
1380
1381 seq_printf(m, "forcewake count = %u\n", forcewake_count);
1382
1383 return 0;
1384 }
1385
1386 static const char *swizzle_string(unsigned swizzle)
1387 {
1388 switch(swizzle) {
1389 case I915_BIT_6_SWIZZLE_NONE:
1390 return "none";
1391 case I915_BIT_6_SWIZZLE_9:
1392 return "bit9";
1393 case I915_BIT_6_SWIZZLE_9_10:
1394 return "bit9/bit10";
1395 case I915_BIT_6_SWIZZLE_9_11:
1396 return "bit9/bit11";
1397 case I915_BIT_6_SWIZZLE_9_10_11:
1398 return "bit9/bit10/bit11";
1399 case I915_BIT_6_SWIZZLE_9_17:
1400 return "bit9/bit17";
1401 case I915_BIT_6_SWIZZLE_9_10_17:
1402 return "bit9/bit10/bit17";
1403 case I915_BIT_6_SWIZZLE_UNKNOWN:
1404 return "unkown";
1405 }
1406
1407 return "bug";
1408 }
1409
1410 static int i915_swizzle_info(struct seq_file *m, void *data)
1411 {
1412 struct drm_info_node *node = (struct drm_info_node *) m->private;
1413 struct drm_device *dev = node->minor->dev;
1414 struct drm_i915_private *dev_priv = dev->dev_private;
1415
1416 mutex_lock(&dev->struct_mutex);
1417 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1418 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1419 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1420 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1421
1422 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1423 seq_printf(m, "DDC = 0x%08x\n",
1424 I915_READ(DCC));
1425 seq_printf(m, "C0DRB3 = 0x%04x\n",
1426 I915_READ16(C0DRB3));
1427 seq_printf(m, "C1DRB3 = 0x%04x\n",
1428 I915_READ16(C1DRB3));
1429 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1430 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1431 I915_READ(MAD_DIMM_C0));
1432 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1433 I915_READ(MAD_DIMM_C1));
1434 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1435 I915_READ(MAD_DIMM_C2));
1436 seq_printf(m, "TILECTL = 0x%08x\n",
1437 I915_READ(TILECTL));
1438 seq_printf(m, "ARB_MODE = 0x%08x\n",
1439 I915_READ(ARB_MODE));
1440 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1441 I915_READ(DISP_ARB_CTL));
1442 }
1443 mutex_unlock(&dev->struct_mutex);
1444
1445 return 0;
1446 }
1447
1448 static int i915_ppgtt_info(struct seq_file *m, void *data)
1449 {
1450 struct drm_info_node *node = (struct drm_info_node *) m->private;
1451 struct drm_device *dev = node->minor->dev;
1452 struct drm_i915_private *dev_priv = dev->dev_private;
1453 struct intel_ring_buffer *ring;
1454 int i, ret;
1455
1456
1457 ret = mutex_lock_interruptible(&dev->struct_mutex);
1458 if (ret)
1459 return ret;
1460 if (INTEL_INFO(dev)->gen == 6)
1461 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1462
1463 for (i = 0; i < I915_NUM_RINGS; i++) {
1464 ring = &dev_priv->ring[i];
1465
1466 seq_printf(m, "%s\n", ring->name);
1467 if (INTEL_INFO(dev)->gen == 7)
1468 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1469 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1470 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1471 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1472 }
1473 if (dev_priv->mm.aliasing_ppgtt) {
1474 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1475
1476 seq_printf(m, "aliasing PPGTT:\n");
1477 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1478 }
1479 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
1480 mutex_unlock(&dev->struct_mutex);
1481
1482 return 0;
1483 }
1484
1485 static int i915_dpio_info(struct seq_file *m, void *data)
1486 {
1487 struct drm_info_node *node = (struct drm_info_node *) m->private;
1488 struct drm_device *dev = node->minor->dev;
1489 struct drm_i915_private *dev_priv = dev->dev_private;
1490 int ret;
1491
1492
1493 if (!IS_VALLEYVIEW(dev)) {
1494 seq_printf(m, "unsupported\n");
1495 return 0;
1496 }
1497
1498 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1499 if (ret)
1500 return ret;
1501
1502 seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
1503
1504 seq_printf(m, "DPIO_DIV_A: 0x%08x\n",
1505 intel_dpio_read(dev_priv, _DPIO_DIV_A));
1506 seq_printf(m, "DPIO_DIV_B: 0x%08x\n",
1507 intel_dpio_read(dev_priv, _DPIO_DIV_B));
1508
1509 seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n",
1510 intel_dpio_read(dev_priv, _DPIO_REFSFR_A));
1511 seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n",
1512 intel_dpio_read(dev_priv, _DPIO_REFSFR_B));
1513
1514 seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n",
1515 intel_dpio_read(dev_priv, _DPIO_CORE_CLK_A));
1516 seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n",
1517 intel_dpio_read(dev_priv, _DPIO_CORE_CLK_B));
1518
1519 seq_printf(m, "DPIO_LFP_COEFF_A: 0x%08x\n",
1520 intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_A));
1521 seq_printf(m, "DPIO_LFP_COEFF_B: 0x%08x\n",
1522 intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_B));
1523
1524 seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
1525 intel_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE));
1526
1527 mutex_unlock(&dev->mode_config.mutex);
1528
1529 return 0;
1530 }
1531
1532 static ssize_t
1533 i915_wedged_read(struct file *filp,
1534 char __user *ubuf,
1535 size_t max,
1536 loff_t *ppos)
1537 {
1538 struct drm_device *dev = filp->private_data;
1539 drm_i915_private_t *dev_priv = dev->dev_private;
1540 char buf[80];
1541 int len;
1542
1543 len = snprintf(buf, sizeof(buf),
1544 "wedged : %d\n",
1545 atomic_read(&dev_priv->mm.wedged));
1546
1547 if (len > sizeof(buf))
1548 len = sizeof(buf);
1549
1550 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1551 }
1552
1553 static ssize_t
1554 i915_wedged_write(struct file *filp,
1555 const char __user *ubuf,
1556 size_t cnt,
1557 loff_t *ppos)
1558 {
1559 struct drm_device *dev = filp->private_data;
1560 char buf[20];
1561 int val = 1;
1562
1563 if (cnt > 0) {
1564 if (cnt > sizeof(buf) - 1)
1565 return -EINVAL;
1566
1567 if (copy_from_user(buf, ubuf, cnt))
1568 return -EFAULT;
1569 buf[cnt] = 0;
1570
1571 val = simple_strtoul(buf, NULL, 0);
1572 }
1573
1574 DRM_INFO("Manually setting wedged to %d\n", val);
1575 i915_handle_error(dev, val);
1576
1577 return cnt;
1578 }
1579
1580 static const struct file_operations i915_wedged_fops = {
1581 .owner = THIS_MODULE,
1582 .open = simple_open,
1583 .read = i915_wedged_read,
1584 .write = i915_wedged_write,
1585 .llseek = default_llseek,
1586 };
1587
1588 static ssize_t
1589 i915_ring_stop_read(struct file *filp,
1590 char __user *ubuf,
1591 size_t max,
1592 loff_t *ppos)
1593 {
1594 struct drm_device *dev = filp->private_data;
1595 drm_i915_private_t *dev_priv = dev->dev_private;
1596 char buf[20];
1597 int len;
1598
1599 len = snprintf(buf, sizeof(buf),
1600 "0x%08x\n", dev_priv->stop_rings);
1601
1602 if (len > sizeof(buf))
1603 len = sizeof(buf);
1604
1605 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1606 }
1607
1608 static ssize_t
1609 i915_ring_stop_write(struct file *filp,
1610 const char __user *ubuf,
1611 size_t cnt,
1612 loff_t *ppos)
1613 {
1614 struct drm_device *dev = filp->private_data;
1615 struct drm_i915_private *dev_priv = dev->dev_private;
1616 char buf[20];
1617 int val = 0;
1618
1619 if (cnt > 0) {
1620 if (cnt > sizeof(buf) - 1)
1621 return -EINVAL;
1622
1623 if (copy_from_user(buf, ubuf, cnt))
1624 return -EFAULT;
1625 buf[cnt] = 0;
1626
1627 val = simple_strtoul(buf, NULL, 0);
1628 }
1629
1630 DRM_DEBUG_DRIVER("Stopping rings 0x%08x\n", val);
1631
1632 mutex_lock(&dev->struct_mutex);
1633 dev_priv->stop_rings = val;
1634 mutex_unlock(&dev->struct_mutex);
1635
1636 return cnt;
1637 }
1638
1639 static const struct file_operations i915_ring_stop_fops = {
1640 .owner = THIS_MODULE,
1641 .open = simple_open,
1642 .read = i915_ring_stop_read,
1643 .write = i915_ring_stop_write,
1644 .llseek = default_llseek,
1645 };
1646 static ssize_t
1647 i915_max_freq_read(struct file *filp,
1648 char __user *ubuf,
1649 size_t max,
1650 loff_t *ppos)
1651 {
1652 struct drm_device *dev = filp->private_data;
1653 drm_i915_private_t *dev_priv = dev->dev_private;
1654 char buf[80];
1655 int len;
1656
1657 len = snprintf(buf, sizeof(buf),
1658 "max freq: %d\n", dev_priv->max_delay * 50);
1659
1660 if (len > sizeof(buf))
1661 len = sizeof(buf);
1662
1663 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1664 }
1665
1666 static ssize_t
1667 i915_max_freq_write(struct file *filp,
1668 const char __user *ubuf,
1669 size_t cnt,
1670 loff_t *ppos)
1671 {
1672 struct drm_device *dev = filp->private_data;
1673 struct drm_i915_private *dev_priv = dev->dev_private;
1674 char buf[20];
1675 int val = 1;
1676
1677 if (cnt > 0) {
1678 if (cnt > sizeof(buf) - 1)
1679 return -EINVAL;
1680
1681 if (copy_from_user(buf, ubuf, cnt))
1682 return -EFAULT;
1683 buf[cnt] = 0;
1684
1685 val = simple_strtoul(buf, NULL, 0);
1686 }
1687
1688 DRM_DEBUG_DRIVER("Manually setting max freq to %d\n", val);
1689
1690 /*
1691 * Turbo will still be enabled, but won't go above the set value.
1692 */
1693 dev_priv->max_delay = val / 50;
1694
1695 gen6_set_rps(dev, val / 50);
1696
1697 return cnt;
1698 }
1699
1700 static const struct file_operations i915_max_freq_fops = {
1701 .owner = THIS_MODULE,
1702 .open = simple_open,
1703 .read = i915_max_freq_read,
1704 .write = i915_max_freq_write,
1705 .llseek = default_llseek,
1706 };
1707
1708 static ssize_t
1709 i915_cache_sharing_read(struct file *filp,
1710 char __user *ubuf,
1711 size_t max,
1712 loff_t *ppos)
1713 {
1714 struct drm_device *dev = filp->private_data;
1715 drm_i915_private_t *dev_priv = dev->dev_private;
1716 char buf[80];
1717 u32 snpcr;
1718 int len;
1719
1720 mutex_lock(&dev_priv->dev->struct_mutex);
1721 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
1722 mutex_unlock(&dev_priv->dev->struct_mutex);
1723
1724 len = snprintf(buf, sizeof(buf),
1725 "%d\n", (snpcr & GEN6_MBC_SNPCR_MASK) >>
1726 GEN6_MBC_SNPCR_SHIFT);
1727
1728 if (len > sizeof(buf))
1729 len = sizeof(buf);
1730
1731 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1732 }
1733
1734 static ssize_t
1735 i915_cache_sharing_write(struct file *filp,
1736 const char __user *ubuf,
1737 size_t cnt,
1738 loff_t *ppos)
1739 {
1740 struct drm_device *dev = filp->private_data;
1741 struct drm_i915_private *dev_priv = dev->dev_private;
1742 char buf[20];
1743 u32 snpcr;
1744 int val = 1;
1745
1746 if (cnt > 0) {
1747 if (cnt > sizeof(buf) - 1)
1748 return -EINVAL;
1749
1750 if (copy_from_user(buf, ubuf, cnt))
1751 return -EFAULT;
1752 buf[cnt] = 0;
1753
1754 val = simple_strtoul(buf, NULL, 0);
1755 }
1756
1757 if (val < 0 || val > 3)
1758 return -EINVAL;
1759
1760 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %d\n", val);
1761
1762 /* Update the cache sharing policy here as well */
1763 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
1764 snpcr &= ~GEN6_MBC_SNPCR_MASK;
1765 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
1766 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
1767
1768 return cnt;
1769 }
1770
1771 static const struct file_operations i915_cache_sharing_fops = {
1772 .owner = THIS_MODULE,
1773 .open = simple_open,
1774 .read = i915_cache_sharing_read,
1775 .write = i915_cache_sharing_write,
1776 .llseek = default_llseek,
1777 };
1778
1779 /* As the drm_debugfs_init() routines are called before dev->dev_private is
1780 * allocated we need to hook into the minor for release. */
1781 static int
1782 drm_add_fake_info_node(struct drm_minor *minor,
1783 struct dentry *ent,
1784 const void *key)
1785 {
1786 struct drm_info_node *node;
1787
1788 node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL);
1789 if (node == NULL) {
1790 debugfs_remove(ent);
1791 return -ENOMEM;
1792 }
1793
1794 node->minor = minor;
1795 node->dent = ent;
1796 node->info_ent = (void *) key;
1797
1798 mutex_lock(&minor->debugfs_lock);
1799 list_add(&node->list, &minor->debugfs_list);
1800 mutex_unlock(&minor->debugfs_lock);
1801
1802 return 0;
1803 }
1804
1805 static int i915_forcewake_open(struct inode *inode, struct file *file)
1806 {
1807 struct drm_device *dev = inode->i_private;
1808 struct drm_i915_private *dev_priv = dev->dev_private;
1809 int ret;
1810
1811 if (INTEL_INFO(dev)->gen < 6)
1812 return 0;
1813
1814 ret = mutex_lock_interruptible(&dev->struct_mutex);
1815 if (ret)
1816 return ret;
1817 gen6_gt_force_wake_get(dev_priv);
1818 mutex_unlock(&dev->struct_mutex);
1819
1820 return 0;
1821 }
1822
1823 static int i915_forcewake_release(struct inode *inode, struct file *file)
1824 {
1825 struct drm_device *dev = inode->i_private;
1826 struct drm_i915_private *dev_priv = dev->dev_private;
1827
1828 if (INTEL_INFO(dev)->gen < 6)
1829 return 0;
1830
1831 /*
1832 * It's bad that we can potentially hang userspace if struct_mutex gets
1833 * forever stuck. However, if we cannot acquire this lock it means that
1834 * almost certainly the driver has hung, is not unload-able. Therefore
1835 * hanging here is probably a minor inconvenience not to be seen my
1836 * almost every user.
1837 */
1838 mutex_lock(&dev->struct_mutex);
1839 gen6_gt_force_wake_put(dev_priv);
1840 mutex_unlock(&dev->struct_mutex);
1841
1842 return 0;
1843 }
1844
1845 static const struct file_operations i915_forcewake_fops = {
1846 .owner = THIS_MODULE,
1847 .open = i915_forcewake_open,
1848 .release = i915_forcewake_release,
1849 };
1850
1851 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
1852 {
1853 struct drm_device *dev = minor->dev;
1854 struct dentry *ent;
1855
1856 ent = debugfs_create_file("i915_forcewake_user",
1857 S_IRUSR,
1858 root, dev,
1859 &i915_forcewake_fops);
1860 if (IS_ERR(ent))
1861 return PTR_ERR(ent);
1862
1863 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
1864 }
1865
1866 static int i915_debugfs_create(struct dentry *root,
1867 struct drm_minor *minor,
1868 const char *name,
1869 const struct file_operations *fops)
1870 {
1871 struct drm_device *dev = minor->dev;
1872 struct dentry *ent;
1873
1874 ent = debugfs_create_file(name,
1875 S_IRUGO | S_IWUSR,
1876 root, dev,
1877 fops);
1878 if (IS_ERR(ent))
1879 return PTR_ERR(ent);
1880
1881 return drm_add_fake_info_node(minor, ent, fops);
1882 }
1883
1884 static struct drm_info_list i915_debugfs_list[] = {
1885 {"i915_capabilities", i915_capabilities, 0},
1886 {"i915_gem_objects", i915_gem_object_info, 0},
1887 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1888 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
1889 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
1890 {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST},
1891 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
1892 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
1893 {"i915_gem_request", i915_gem_request_info, 0},
1894 {"i915_gem_seqno", i915_gem_seqno_info, 0},
1895 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
1896 {"i915_gem_interrupt", i915_interrupt_info, 0},
1897 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
1898 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
1899 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
1900 {"i915_error_state", i915_error_state, 0},
1901 {"i915_rstdby_delays", i915_rstdby_delays, 0},
1902 {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
1903 {"i915_delayfreq_table", i915_delayfreq_table, 0},
1904 {"i915_inttoext_table", i915_inttoext_table, 0},
1905 {"i915_drpc_info", i915_drpc_info, 0},
1906 {"i915_emon_status", i915_emon_status, 0},
1907 {"i915_ring_freq_table", i915_ring_freq_table, 0},
1908 {"i915_gfxec", i915_gfxec, 0},
1909 {"i915_fbc_status", i915_fbc_status, 0},
1910 {"i915_sr_status", i915_sr_status, 0},
1911 {"i915_opregion", i915_opregion, 0},
1912 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
1913 {"i915_context_status", i915_context_status, 0},
1914 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
1915 {"i915_swizzle_info", i915_swizzle_info, 0},
1916 {"i915_ppgtt_info", i915_ppgtt_info, 0},
1917 {"i915_dpio", i915_dpio_info, 0},
1918 };
1919 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
1920
1921 int i915_debugfs_init(struct drm_minor *minor)
1922 {
1923 int ret;
1924
1925 ret = i915_debugfs_create(minor->debugfs_root, minor,
1926 "i915_wedged",
1927 &i915_wedged_fops);
1928 if (ret)
1929 return ret;
1930
1931 ret = i915_forcewake_create(minor->debugfs_root, minor);
1932 if (ret)
1933 return ret;
1934
1935 ret = i915_debugfs_create(minor->debugfs_root, minor,
1936 "i915_max_freq",
1937 &i915_max_freq_fops);
1938 if (ret)
1939 return ret;
1940
1941 ret = i915_debugfs_create(minor->debugfs_root, minor,
1942 "i915_cache_sharing",
1943 &i915_cache_sharing_fops);
1944 if (ret)
1945 return ret;
1946 ret = i915_debugfs_create(minor->debugfs_root, minor,
1947 "i915_ring_stop",
1948 &i915_ring_stop_fops);
1949 if (ret)
1950 return ret;
1951
1952 return drm_debugfs_create_files(i915_debugfs_list,
1953 I915_DEBUGFS_ENTRIES,
1954 minor->debugfs_root, minor);
1955 }
1956
1957 void i915_debugfs_cleanup(struct drm_minor *minor)
1958 {
1959 drm_debugfs_remove_files(i915_debugfs_list,
1960 I915_DEBUGFS_ENTRIES, minor);
1961 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
1962 1, minor);
1963 drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops,
1964 1, minor);
1965 drm_debugfs_remove_files((struct drm_info_list *) &i915_max_freq_fops,
1966 1, minor);
1967 drm_debugfs_remove_files((struct drm_info_list *) &i915_cache_sharing_fops,
1968 1, minor);
1969 drm_debugfs_remove_files((struct drm_info_list *) &i915_ring_stop_fops,
1970 1, minor);
1971 }
1972
1973 #endif /* CONFIG_DEBUG_FS */
Linux kernel - Deliverables
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