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drm/i915: Add power well arguments to force wake routines.
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
37 #include <drm/drmP.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
41 #include "i915_drv.h"
42
43 #if defined(CONFIG_DEBUG_FS)
44
45 enum {
46 ACTIVE_LIST,
47 INACTIVE_LIST,
48 PINNED_LIST,
49 };
50
51 static const char *yesno(int v)
52 {
53 return v ? "yes" : "no";
54 }
55
56 /* As the drm_debugfs_init() routines are called before dev->dev_private is
57 * allocated we need to hook into the minor for release. */
58 static int
59 drm_add_fake_info_node(struct drm_minor *minor,
60 struct dentry *ent,
61 const void *key)
62 {
63 struct drm_info_node *node;
64
65 node = kmalloc(sizeof(*node), GFP_KERNEL);
66 if (node == NULL) {
67 debugfs_remove(ent);
68 return -ENOMEM;
69 }
70
71 node->minor = minor;
72 node->dent = ent;
73 node->info_ent = (void *) key;
74
75 mutex_lock(&minor->debugfs_lock);
76 list_add(&node->list, &minor->debugfs_list);
77 mutex_unlock(&minor->debugfs_lock);
78
79 return 0;
80 }
81
82 static int i915_capabilities(struct seq_file *m, void *data)
83 {
84 struct drm_info_node *node = (struct drm_info_node *) m->private;
85 struct drm_device *dev = node->minor->dev;
86 const struct intel_device_info *info = INTEL_INFO(dev);
87
88 seq_printf(m, "gen: %d\n", info->gen);
89 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
90 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
91 #define SEP_SEMICOLON ;
92 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
93 #undef PRINT_FLAG
94 #undef SEP_SEMICOLON
95
96 return 0;
97 }
98
99 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
100 {
101 if (obj->user_pin_count > 0)
102 return "P";
103 else if (obj->pin_count > 0)
104 return "p";
105 else
106 return " ";
107 }
108
109 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
110 {
111 switch (obj->tiling_mode) {
112 default:
113 case I915_TILING_NONE: return " ";
114 case I915_TILING_X: return "X";
115 case I915_TILING_Y: return "Y";
116 }
117 }
118
119 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
120 {
121 return obj->has_global_gtt_mapping ? "g" : " ";
122 }
123
124 static void
125 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
126 {
127 struct i915_vma *vma;
128 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
129 &obj->base,
130 get_pin_flag(obj),
131 get_tiling_flag(obj),
132 get_global_flag(obj),
133 obj->base.size / 1024,
134 obj->base.read_domains,
135 obj->base.write_domain,
136 obj->last_read_seqno,
137 obj->last_write_seqno,
138 obj->last_fenced_seqno,
139 i915_cache_level_str(obj->cache_level),
140 obj->dirty ? " dirty" : "",
141 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
142 if (obj->base.name)
143 seq_printf(m, " (name: %d)", obj->base.name);
144 if (obj->pin_count)
145 seq_printf(m, " (pinned x %d)", obj->pin_count);
146 if (obj->pin_display)
147 seq_printf(m, " (display)");
148 if (obj->fence_reg != I915_FENCE_REG_NONE)
149 seq_printf(m, " (fence: %d)", obj->fence_reg);
150 list_for_each_entry(vma, &obj->vma_list, vma_link) {
151 if (!i915_is_ggtt(vma->vm))
152 seq_puts(m, " (pp");
153 else
154 seq_puts(m, " (g");
155 seq_printf(m, "gtt offset: %08lx, size: %08lx)",
156 vma->node.start, vma->node.size);
157 }
158 if (obj->stolen)
159 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
160 if (obj->pin_mappable || obj->fault_mappable) {
161 char s[3], *t = s;
162 if (obj->pin_mappable)
163 *t++ = 'p';
164 if (obj->fault_mappable)
165 *t++ = 'f';
166 *t = '\0';
167 seq_printf(m, " (%s mappable)", s);
168 }
169 if (obj->ring != NULL)
170 seq_printf(m, " (%s)", obj->ring->name);
171 }
172
173 static void describe_ctx(struct seq_file *m, struct i915_hw_context *ctx)
174 {
175 seq_putc(m, ctx->is_initialized ? 'I' : 'i');
176 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
177 seq_putc(m, ' ');
178 }
179
180 static int i915_gem_object_list_info(struct seq_file *m, void *data)
181 {
182 struct drm_info_node *node = (struct drm_info_node *) m->private;
183 uintptr_t list = (uintptr_t) node->info_ent->data;
184 struct list_head *head;
185 struct drm_device *dev = node->minor->dev;
186 struct drm_i915_private *dev_priv = dev->dev_private;
187 struct i915_address_space *vm = &dev_priv->gtt.base;
188 struct i915_vma *vma;
189 size_t total_obj_size, total_gtt_size;
190 int count, ret;
191
192 ret = mutex_lock_interruptible(&dev->struct_mutex);
193 if (ret)
194 return ret;
195
196 /* FIXME: the user of this interface might want more than just GGTT */
197 switch (list) {
198 case ACTIVE_LIST:
199 seq_puts(m, "Active:\n");
200 head = &vm->active_list;
201 break;
202 case INACTIVE_LIST:
203 seq_puts(m, "Inactive:\n");
204 head = &vm->inactive_list;
205 break;
206 default:
207 mutex_unlock(&dev->struct_mutex);
208 return -EINVAL;
209 }
210
211 total_obj_size = total_gtt_size = count = 0;
212 list_for_each_entry(vma, head, mm_list) {
213 seq_printf(m, " ");
214 describe_obj(m, vma->obj);
215 seq_printf(m, "\n");
216 total_obj_size += vma->obj->base.size;
217 total_gtt_size += vma->node.size;
218 count++;
219 }
220 mutex_unlock(&dev->struct_mutex);
221
222 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
223 count, total_obj_size, total_gtt_size);
224 return 0;
225 }
226
227 static int obj_rank_by_stolen(void *priv,
228 struct list_head *A, struct list_head *B)
229 {
230 struct drm_i915_gem_object *a =
231 container_of(A, struct drm_i915_gem_object, obj_exec_link);
232 struct drm_i915_gem_object *b =
233 container_of(B, struct drm_i915_gem_object, obj_exec_link);
234
235 return a->stolen->start - b->stolen->start;
236 }
237
238 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
239 {
240 struct drm_info_node *node = (struct drm_info_node *) m->private;
241 struct drm_device *dev = node->minor->dev;
242 struct drm_i915_private *dev_priv = dev->dev_private;
243 struct drm_i915_gem_object *obj;
244 size_t total_obj_size, total_gtt_size;
245 LIST_HEAD(stolen);
246 int count, ret;
247
248 ret = mutex_lock_interruptible(&dev->struct_mutex);
249 if (ret)
250 return ret;
251
252 total_obj_size = total_gtt_size = count = 0;
253 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
254 if (obj->stolen == NULL)
255 continue;
256
257 list_add(&obj->obj_exec_link, &stolen);
258
259 total_obj_size += obj->base.size;
260 total_gtt_size += i915_gem_obj_ggtt_size(obj);
261 count++;
262 }
263 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
264 if (obj->stolen == NULL)
265 continue;
266
267 list_add(&obj->obj_exec_link, &stolen);
268
269 total_obj_size += obj->base.size;
270 count++;
271 }
272 list_sort(NULL, &stolen, obj_rank_by_stolen);
273 seq_puts(m, "Stolen:\n");
274 while (!list_empty(&stolen)) {
275 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
276 seq_puts(m, " ");
277 describe_obj(m, obj);
278 seq_putc(m, '\n');
279 list_del_init(&obj->obj_exec_link);
280 }
281 mutex_unlock(&dev->struct_mutex);
282
283 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
284 count, total_obj_size, total_gtt_size);
285 return 0;
286 }
287
288 #define count_objects(list, member) do { \
289 list_for_each_entry(obj, list, member) { \
290 size += i915_gem_obj_ggtt_size(obj); \
291 ++count; \
292 if (obj->map_and_fenceable) { \
293 mappable_size += i915_gem_obj_ggtt_size(obj); \
294 ++mappable_count; \
295 } \
296 } \
297 } while (0)
298
299 struct file_stats {
300 int count;
301 size_t total, active, inactive, unbound;
302 };
303
304 static int per_file_stats(int id, void *ptr, void *data)
305 {
306 struct drm_i915_gem_object *obj = ptr;
307 struct file_stats *stats = data;
308
309 stats->count++;
310 stats->total += obj->base.size;
311
312 if (i915_gem_obj_ggtt_bound(obj)) {
313 if (!list_empty(&obj->ring_list))
314 stats->active += obj->base.size;
315 else
316 stats->inactive += obj->base.size;
317 } else {
318 if (!list_empty(&obj->global_list))
319 stats->unbound += obj->base.size;
320 }
321
322 return 0;
323 }
324
325 #define count_vmas(list, member) do { \
326 list_for_each_entry(vma, list, member) { \
327 size += i915_gem_obj_ggtt_size(vma->obj); \
328 ++count; \
329 if (vma->obj->map_and_fenceable) { \
330 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
331 ++mappable_count; \
332 } \
333 } \
334 } while (0)
335
336 static int i915_gem_object_info(struct seq_file *m, void* data)
337 {
338 struct drm_info_node *node = (struct drm_info_node *) m->private;
339 struct drm_device *dev = node->minor->dev;
340 struct drm_i915_private *dev_priv = dev->dev_private;
341 u32 count, mappable_count, purgeable_count;
342 size_t size, mappable_size, purgeable_size;
343 struct drm_i915_gem_object *obj;
344 struct i915_address_space *vm = &dev_priv->gtt.base;
345 struct drm_file *file;
346 struct i915_vma *vma;
347 int ret;
348
349 ret = mutex_lock_interruptible(&dev->struct_mutex);
350 if (ret)
351 return ret;
352
353 seq_printf(m, "%u objects, %zu bytes\n",
354 dev_priv->mm.object_count,
355 dev_priv->mm.object_memory);
356
357 size = count = mappable_size = mappable_count = 0;
358 count_objects(&dev_priv->mm.bound_list, global_list);
359 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
360 count, mappable_count, size, mappable_size);
361
362 size = count = mappable_size = mappable_count = 0;
363 count_vmas(&vm->active_list, mm_list);
364 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
365 count, mappable_count, size, mappable_size);
366
367 size = count = mappable_size = mappable_count = 0;
368 count_vmas(&vm->inactive_list, mm_list);
369 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
370 count, mappable_count, size, mappable_size);
371
372 size = count = purgeable_size = purgeable_count = 0;
373 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
374 size += obj->base.size, ++count;
375 if (obj->madv == I915_MADV_DONTNEED)
376 purgeable_size += obj->base.size, ++purgeable_count;
377 }
378 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
379
380 size = count = mappable_size = mappable_count = 0;
381 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
382 if (obj->fault_mappable) {
383 size += i915_gem_obj_ggtt_size(obj);
384 ++count;
385 }
386 if (obj->pin_mappable) {
387 mappable_size += i915_gem_obj_ggtt_size(obj);
388 ++mappable_count;
389 }
390 if (obj->madv == I915_MADV_DONTNEED) {
391 purgeable_size += obj->base.size;
392 ++purgeable_count;
393 }
394 }
395 seq_printf(m, "%u purgeable objects, %zu bytes\n",
396 purgeable_count, purgeable_size);
397 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
398 mappable_count, mappable_size);
399 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
400 count, size);
401
402 seq_printf(m, "%zu [%lu] gtt total\n",
403 dev_priv->gtt.base.total,
404 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
405
406 seq_putc(m, '\n');
407 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
408 struct file_stats stats;
409
410 memset(&stats, 0, sizeof(stats));
411 idr_for_each(&file->object_idr, per_file_stats, &stats);
412 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n",
413 get_pid_task(file->pid, PIDTYPE_PID)->comm,
414 stats.count,
415 stats.total,
416 stats.active,
417 stats.inactive,
418 stats.unbound);
419 }
420
421 mutex_unlock(&dev->struct_mutex);
422
423 return 0;
424 }
425
426 static int i915_gem_gtt_info(struct seq_file *m, void *data)
427 {
428 struct drm_info_node *node = (struct drm_info_node *) m->private;
429 struct drm_device *dev = node->minor->dev;
430 uintptr_t list = (uintptr_t) node->info_ent->data;
431 struct drm_i915_private *dev_priv = dev->dev_private;
432 struct drm_i915_gem_object *obj;
433 size_t total_obj_size, total_gtt_size;
434 int count, ret;
435
436 ret = mutex_lock_interruptible(&dev->struct_mutex);
437 if (ret)
438 return ret;
439
440 total_obj_size = total_gtt_size = count = 0;
441 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
442 if (list == PINNED_LIST && obj->pin_count == 0)
443 continue;
444
445 seq_puts(m, " ");
446 describe_obj(m, obj);
447 seq_putc(m, '\n');
448 total_obj_size += obj->base.size;
449 total_gtt_size += i915_gem_obj_ggtt_size(obj);
450 count++;
451 }
452
453 mutex_unlock(&dev->struct_mutex);
454
455 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
456 count, total_obj_size, total_gtt_size);
457
458 return 0;
459 }
460
461 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
462 {
463 struct drm_info_node *node = (struct drm_info_node *) m->private;
464 struct drm_device *dev = node->minor->dev;
465 unsigned long flags;
466 struct intel_crtc *crtc;
467
468 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
469 const char pipe = pipe_name(crtc->pipe);
470 const char plane = plane_name(crtc->plane);
471 struct intel_unpin_work *work;
472
473 spin_lock_irqsave(&dev->event_lock, flags);
474 work = crtc->unpin_work;
475 if (work == NULL) {
476 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
477 pipe, plane);
478 } else {
479 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
480 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
481 pipe, plane);
482 } else {
483 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
484 pipe, plane);
485 }
486 if (work->enable_stall_check)
487 seq_puts(m, "Stall check enabled, ");
488 else
489 seq_puts(m, "Stall check waiting for page flip ioctl, ");
490 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
491
492 if (work->old_fb_obj) {
493 struct drm_i915_gem_object *obj = work->old_fb_obj;
494 if (obj)
495 seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n",
496 i915_gem_obj_ggtt_offset(obj));
497 }
498 if (work->pending_flip_obj) {
499 struct drm_i915_gem_object *obj = work->pending_flip_obj;
500 if (obj)
501 seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n",
502 i915_gem_obj_ggtt_offset(obj));
503 }
504 }
505 spin_unlock_irqrestore(&dev->event_lock, flags);
506 }
507
508 return 0;
509 }
510
511 static int i915_gem_request_info(struct seq_file *m, void *data)
512 {
513 struct drm_info_node *node = (struct drm_info_node *) m->private;
514 struct drm_device *dev = node->minor->dev;
515 drm_i915_private_t *dev_priv = dev->dev_private;
516 struct intel_ring_buffer *ring;
517 struct drm_i915_gem_request *gem_request;
518 int ret, count, i;
519
520 ret = mutex_lock_interruptible(&dev->struct_mutex);
521 if (ret)
522 return ret;
523
524 count = 0;
525 for_each_ring(ring, dev_priv, i) {
526 if (list_empty(&ring->request_list))
527 continue;
528
529 seq_printf(m, "%s requests:\n", ring->name);
530 list_for_each_entry(gem_request,
531 &ring->request_list,
532 list) {
533 seq_printf(m, " %d @ %d\n",
534 gem_request->seqno,
535 (int) (jiffies - gem_request->emitted_jiffies));
536 }
537 count++;
538 }
539 mutex_unlock(&dev->struct_mutex);
540
541 if (count == 0)
542 seq_puts(m, "No requests\n");
543
544 return 0;
545 }
546
547 static void i915_ring_seqno_info(struct seq_file *m,
548 struct intel_ring_buffer *ring)
549 {
550 if (ring->get_seqno) {
551 seq_printf(m, "Current sequence (%s): %u\n",
552 ring->name, ring->get_seqno(ring, false));
553 }
554 }
555
556 static int i915_gem_seqno_info(struct seq_file *m, void *data)
557 {
558 struct drm_info_node *node = (struct drm_info_node *) m->private;
559 struct drm_device *dev = node->minor->dev;
560 drm_i915_private_t *dev_priv = dev->dev_private;
561 struct intel_ring_buffer *ring;
562 int ret, i;
563
564 ret = mutex_lock_interruptible(&dev->struct_mutex);
565 if (ret)
566 return ret;
567
568 for_each_ring(ring, dev_priv, i)
569 i915_ring_seqno_info(m, ring);
570
571 mutex_unlock(&dev->struct_mutex);
572
573 return 0;
574 }
575
576
577 static int i915_interrupt_info(struct seq_file *m, void *data)
578 {
579 struct drm_info_node *node = (struct drm_info_node *) m->private;
580 struct drm_device *dev = node->minor->dev;
581 drm_i915_private_t *dev_priv = dev->dev_private;
582 struct intel_ring_buffer *ring;
583 int ret, i, pipe;
584
585 ret = mutex_lock_interruptible(&dev->struct_mutex);
586 if (ret)
587 return ret;
588
589 if (INTEL_INFO(dev)->gen >= 8) {
590 int i;
591 seq_printf(m, "Master Interrupt Control:\t%08x\n",
592 I915_READ(GEN8_MASTER_IRQ));
593
594 for (i = 0; i < 4; i++) {
595 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
596 i, I915_READ(GEN8_GT_IMR(i)));
597 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
598 i, I915_READ(GEN8_GT_IIR(i)));
599 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
600 i, I915_READ(GEN8_GT_IER(i)));
601 }
602
603 for_each_pipe(i) {
604 seq_printf(m, "Pipe %c IMR:\t%08x\n",
605 pipe_name(i),
606 I915_READ(GEN8_DE_PIPE_IMR(i)));
607 seq_printf(m, "Pipe %c IIR:\t%08x\n",
608 pipe_name(i),
609 I915_READ(GEN8_DE_PIPE_IIR(i)));
610 seq_printf(m, "Pipe %c IER:\t%08x\n",
611 pipe_name(i),
612 I915_READ(GEN8_DE_PIPE_IER(i)));
613 }
614
615 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
616 I915_READ(GEN8_DE_PORT_IMR));
617 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
618 I915_READ(GEN8_DE_PORT_IIR));
619 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
620 I915_READ(GEN8_DE_PORT_IER));
621
622 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
623 I915_READ(GEN8_DE_MISC_IMR));
624 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
625 I915_READ(GEN8_DE_MISC_IIR));
626 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
627 I915_READ(GEN8_DE_MISC_IER));
628
629 seq_printf(m, "PCU interrupt mask:\t%08x\n",
630 I915_READ(GEN8_PCU_IMR));
631 seq_printf(m, "PCU interrupt identity:\t%08x\n",
632 I915_READ(GEN8_PCU_IIR));
633 seq_printf(m, "PCU interrupt enable:\t%08x\n",
634 I915_READ(GEN8_PCU_IER));
635 } else if (IS_VALLEYVIEW(dev)) {
636 seq_printf(m, "Display IER:\t%08x\n",
637 I915_READ(VLV_IER));
638 seq_printf(m, "Display IIR:\t%08x\n",
639 I915_READ(VLV_IIR));
640 seq_printf(m, "Display IIR_RW:\t%08x\n",
641 I915_READ(VLV_IIR_RW));
642 seq_printf(m, "Display IMR:\t%08x\n",
643 I915_READ(VLV_IMR));
644 for_each_pipe(pipe)
645 seq_printf(m, "Pipe %c stat:\t%08x\n",
646 pipe_name(pipe),
647 I915_READ(PIPESTAT(pipe)));
648
649 seq_printf(m, "Master IER:\t%08x\n",
650 I915_READ(VLV_MASTER_IER));
651
652 seq_printf(m, "Render IER:\t%08x\n",
653 I915_READ(GTIER));
654 seq_printf(m, "Render IIR:\t%08x\n",
655 I915_READ(GTIIR));
656 seq_printf(m, "Render IMR:\t%08x\n",
657 I915_READ(GTIMR));
658
659 seq_printf(m, "PM IER:\t\t%08x\n",
660 I915_READ(GEN6_PMIER));
661 seq_printf(m, "PM IIR:\t\t%08x\n",
662 I915_READ(GEN6_PMIIR));
663 seq_printf(m, "PM IMR:\t\t%08x\n",
664 I915_READ(GEN6_PMIMR));
665
666 seq_printf(m, "Port hotplug:\t%08x\n",
667 I915_READ(PORT_HOTPLUG_EN));
668 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
669 I915_READ(VLV_DPFLIPSTAT));
670 seq_printf(m, "DPINVGTT:\t%08x\n",
671 I915_READ(DPINVGTT));
672
673 } else if (!HAS_PCH_SPLIT(dev)) {
674 seq_printf(m, "Interrupt enable: %08x\n",
675 I915_READ(IER));
676 seq_printf(m, "Interrupt identity: %08x\n",
677 I915_READ(IIR));
678 seq_printf(m, "Interrupt mask: %08x\n",
679 I915_READ(IMR));
680 for_each_pipe(pipe)
681 seq_printf(m, "Pipe %c stat: %08x\n",
682 pipe_name(pipe),
683 I915_READ(PIPESTAT(pipe)));
684 } else {
685 seq_printf(m, "North Display Interrupt enable: %08x\n",
686 I915_READ(DEIER));
687 seq_printf(m, "North Display Interrupt identity: %08x\n",
688 I915_READ(DEIIR));
689 seq_printf(m, "North Display Interrupt mask: %08x\n",
690 I915_READ(DEIMR));
691 seq_printf(m, "South Display Interrupt enable: %08x\n",
692 I915_READ(SDEIER));
693 seq_printf(m, "South Display Interrupt identity: %08x\n",
694 I915_READ(SDEIIR));
695 seq_printf(m, "South Display Interrupt mask: %08x\n",
696 I915_READ(SDEIMR));
697 seq_printf(m, "Graphics Interrupt enable: %08x\n",
698 I915_READ(GTIER));
699 seq_printf(m, "Graphics Interrupt identity: %08x\n",
700 I915_READ(GTIIR));
701 seq_printf(m, "Graphics Interrupt mask: %08x\n",
702 I915_READ(GTIMR));
703 }
704 seq_printf(m, "Interrupts received: %d\n",
705 atomic_read(&dev_priv->irq_received));
706 for_each_ring(ring, dev_priv, i) {
707 if (INTEL_INFO(dev)->gen >= 6) {
708 seq_printf(m,
709 "Graphics Interrupt mask (%s): %08x\n",
710 ring->name, I915_READ_IMR(ring));
711 }
712 i915_ring_seqno_info(m, ring);
713 }
714 mutex_unlock(&dev->struct_mutex);
715
716 return 0;
717 }
718
719 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
720 {
721 struct drm_info_node *node = (struct drm_info_node *) m->private;
722 struct drm_device *dev = node->minor->dev;
723 drm_i915_private_t *dev_priv = dev->dev_private;
724 int i, ret;
725
726 ret = mutex_lock_interruptible(&dev->struct_mutex);
727 if (ret)
728 return ret;
729
730 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
731 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
732 for (i = 0; i < dev_priv->num_fence_regs; i++) {
733 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
734
735 seq_printf(m, "Fence %d, pin count = %d, object = ",
736 i, dev_priv->fence_regs[i].pin_count);
737 if (obj == NULL)
738 seq_puts(m, "unused");
739 else
740 describe_obj(m, obj);
741 seq_putc(m, '\n');
742 }
743
744 mutex_unlock(&dev->struct_mutex);
745 return 0;
746 }
747
748 static int i915_hws_info(struct seq_file *m, void *data)
749 {
750 struct drm_info_node *node = (struct drm_info_node *) m->private;
751 struct drm_device *dev = node->minor->dev;
752 drm_i915_private_t *dev_priv = dev->dev_private;
753 struct intel_ring_buffer *ring;
754 const u32 *hws;
755 int i;
756
757 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
758 hws = ring->status_page.page_addr;
759 if (hws == NULL)
760 return 0;
761
762 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
763 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
764 i * 4,
765 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
766 }
767 return 0;
768 }
769
770 static ssize_t
771 i915_error_state_write(struct file *filp,
772 const char __user *ubuf,
773 size_t cnt,
774 loff_t *ppos)
775 {
776 struct i915_error_state_file_priv *error_priv = filp->private_data;
777 struct drm_device *dev = error_priv->dev;
778 int ret;
779
780 DRM_DEBUG_DRIVER("Resetting error state\n");
781
782 ret = mutex_lock_interruptible(&dev->struct_mutex);
783 if (ret)
784 return ret;
785
786 i915_destroy_error_state(dev);
787 mutex_unlock(&dev->struct_mutex);
788
789 return cnt;
790 }
791
792 static int i915_error_state_open(struct inode *inode, struct file *file)
793 {
794 struct drm_device *dev = inode->i_private;
795 struct i915_error_state_file_priv *error_priv;
796
797 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
798 if (!error_priv)
799 return -ENOMEM;
800
801 error_priv->dev = dev;
802
803 i915_error_state_get(dev, error_priv);
804
805 file->private_data = error_priv;
806
807 return 0;
808 }
809
810 static int i915_error_state_release(struct inode *inode, struct file *file)
811 {
812 struct i915_error_state_file_priv *error_priv = file->private_data;
813
814 i915_error_state_put(error_priv);
815 kfree(error_priv);
816
817 return 0;
818 }
819
820 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
821 size_t count, loff_t *pos)
822 {
823 struct i915_error_state_file_priv *error_priv = file->private_data;
824 struct drm_i915_error_state_buf error_str;
825 loff_t tmp_pos = 0;
826 ssize_t ret_count = 0;
827 int ret;
828
829 ret = i915_error_state_buf_init(&error_str, count, *pos);
830 if (ret)
831 return ret;
832
833 ret = i915_error_state_to_str(&error_str, error_priv);
834 if (ret)
835 goto out;
836
837 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
838 error_str.buf,
839 error_str.bytes);
840
841 if (ret_count < 0)
842 ret = ret_count;
843 else
844 *pos = error_str.start + ret_count;
845 out:
846 i915_error_state_buf_release(&error_str);
847 return ret ?: ret_count;
848 }
849
850 static const struct file_operations i915_error_state_fops = {
851 .owner = THIS_MODULE,
852 .open = i915_error_state_open,
853 .read = i915_error_state_read,
854 .write = i915_error_state_write,
855 .llseek = default_llseek,
856 .release = i915_error_state_release,
857 };
858
859 static int
860 i915_next_seqno_get(void *data, u64 *val)
861 {
862 struct drm_device *dev = data;
863 drm_i915_private_t *dev_priv = dev->dev_private;
864 int ret;
865
866 ret = mutex_lock_interruptible(&dev->struct_mutex);
867 if (ret)
868 return ret;
869
870 *val = dev_priv->next_seqno;
871 mutex_unlock(&dev->struct_mutex);
872
873 return 0;
874 }
875
876 static int
877 i915_next_seqno_set(void *data, u64 val)
878 {
879 struct drm_device *dev = data;
880 int ret;
881
882 ret = mutex_lock_interruptible(&dev->struct_mutex);
883 if (ret)
884 return ret;
885
886 ret = i915_gem_set_seqno(dev, val);
887 mutex_unlock(&dev->struct_mutex);
888
889 return ret;
890 }
891
892 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
893 i915_next_seqno_get, i915_next_seqno_set,
894 "0x%llx\n");
895
896 static int i915_rstdby_delays(struct seq_file *m, void *unused)
897 {
898 struct drm_info_node *node = (struct drm_info_node *) m->private;
899 struct drm_device *dev = node->minor->dev;
900 drm_i915_private_t *dev_priv = dev->dev_private;
901 u16 crstanddelay;
902 int ret;
903
904 ret = mutex_lock_interruptible(&dev->struct_mutex);
905 if (ret)
906 return ret;
907
908 crstanddelay = I915_READ16(CRSTANDVID);
909
910 mutex_unlock(&dev->struct_mutex);
911
912 seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
913
914 return 0;
915 }
916
917 static int i915_cur_delayinfo(struct seq_file *m, void *unused)
918 {
919 struct drm_info_node *node = (struct drm_info_node *) m->private;
920 struct drm_device *dev = node->minor->dev;
921 drm_i915_private_t *dev_priv = dev->dev_private;
922 int ret;
923
924 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
925
926 if (IS_GEN5(dev)) {
927 u16 rgvswctl = I915_READ16(MEMSWCTL);
928 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
929
930 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
931 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
932 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
933 MEMSTAT_VID_SHIFT);
934 seq_printf(m, "Current P-state: %d\n",
935 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
936 } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
937 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
938 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
939 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
940 u32 rpstat, cagf, reqf;
941 u32 rpupei, rpcurup, rpprevup;
942 u32 rpdownei, rpcurdown, rpprevdown;
943 int max_freq;
944
945 /* RPSTAT1 is in the GT power well */
946 ret = mutex_lock_interruptible(&dev->struct_mutex);
947 if (ret)
948 return ret;
949
950 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
951
952 reqf = I915_READ(GEN6_RPNSWREQ);
953 reqf &= ~GEN6_TURBO_DISABLE;
954 if (IS_HASWELL(dev))
955 reqf >>= 24;
956 else
957 reqf >>= 25;
958 reqf *= GT_FREQUENCY_MULTIPLIER;
959
960 rpstat = I915_READ(GEN6_RPSTAT1);
961 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
962 rpcurup = I915_READ(GEN6_RP_CUR_UP);
963 rpprevup = I915_READ(GEN6_RP_PREV_UP);
964 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
965 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
966 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
967 if (IS_HASWELL(dev))
968 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
969 else
970 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
971 cagf *= GT_FREQUENCY_MULTIPLIER;
972
973 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
974 mutex_unlock(&dev->struct_mutex);
975
976 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
977 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
978 seq_printf(m, "Render p-state ratio: %d\n",
979 (gt_perf_status & 0xff00) >> 8);
980 seq_printf(m, "Render p-state VID: %d\n",
981 gt_perf_status & 0xff);
982 seq_printf(m, "Render p-state limit: %d\n",
983 rp_state_limits & 0xff);
984 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
985 seq_printf(m, "CAGF: %dMHz\n", cagf);
986 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
987 GEN6_CURICONT_MASK);
988 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
989 GEN6_CURBSYTAVG_MASK);
990 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
991 GEN6_CURBSYTAVG_MASK);
992 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
993 GEN6_CURIAVG_MASK);
994 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
995 GEN6_CURBSYTAVG_MASK);
996 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
997 GEN6_CURBSYTAVG_MASK);
998
999 max_freq = (rp_state_cap & 0xff0000) >> 16;
1000 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1001 max_freq * GT_FREQUENCY_MULTIPLIER);
1002
1003 max_freq = (rp_state_cap & 0xff00) >> 8;
1004 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1005 max_freq * GT_FREQUENCY_MULTIPLIER);
1006
1007 max_freq = rp_state_cap & 0xff;
1008 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1009 max_freq * GT_FREQUENCY_MULTIPLIER);
1010
1011 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1012 dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER);
1013 } else if (IS_VALLEYVIEW(dev)) {
1014 u32 freq_sts, val;
1015
1016 mutex_lock(&dev_priv->rps.hw_lock);
1017 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1018 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1019 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1020
1021 val = valleyview_rps_max_freq(dev_priv);
1022 seq_printf(m, "max GPU freq: %d MHz\n",
1023 vlv_gpu_freq(dev_priv, val));
1024
1025 val = valleyview_rps_min_freq(dev_priv);
1026 seq_printf(m, "min GPU freq: %d MHz\n",
1027 vlv_gpu_freq(dev_priv, val));
1028
1029 seq_printf(m, "current GPU freq: %d MHz\n",
1030 vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1031 mutex_unlock(&dev_priv->rps.hw_lock);
1032 } else {
1033 seq_puts(m, "no P-state info available\n");
1034 }
1035
1036 return 0;
1037 }
1038
1039 static int i915_delayfreq_table(struct seq_file *m, void *unused)
1040 {
1041 struct drm_info_node *node = (struct drm_info_node *) m->private;
1042 struct drm_device *dev = node->minor->dev;
1043 drm_i915_private_t *dev_priv = dev->dev_private;
1044 u32 delayfreq;
1045 int ret, i;
1046
1047 ret = mutex_lock_interruptible(&dev->struct_mutex);
1048 if (ret)
1049 return ret;
1050
1051 for (i = 0; i < 16; i++) {
1052 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
1053 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
1054 (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
1055 }
1056
1057 mutex_unlock(&dev->struct_mutex);
1058
1059 return 0;
1060 }
1061
1062 static inline int MAP_TO_MV(int map)
1063 {
1064 return 1250 - (map * 25);
1065 }
1066
1067 static int i915_inttoext_table(struct seq_file *m, void *unused)
1068 {
1069 struct drm_info_node *node = (struct drm_info_node *) m->private;
1070 struct drm_device *dev = node->minor->dev;
1071 drm_i915_private_t *dev_priv = dev->dev_private;
1072 u32 inttoext;
1073 int ret, i;
1074
1075 ret = mutex_lock_interruptible(&dev->struct_mutex);
1076 if (ret)
1077 return ret;
1078
1079 for (i = 1; i <= 32; i++) {
1080 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
1081 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
1082 }
1083
1084 mutex_unlock(&dev->struct_mutex);
1085
1086 return 0;
1087 }
1088
1089 static int ironlake_drpc_info(struct seq_file *m)
1090 {
1091 struct drm_info_node *node = (struct drm_info_node *) m->private;
1092 struct drm_device *dev = node->minor->dev;
1093 drm_i915_private_t *dev_priv = dev->dev_private;
1094 u32 rgvmodectl, rstdbyctl;
1095 u16 crstandvid;
1096 int ret;
1097
1098 ret = mutex_lock_interruptible(&dev->struct_mutex);
1099 if (ret)
1100 return ret;
1101
1102 rgvmodectl = I915_READ(MEMMODECTL);
1103 rstdbyctl = I915_READ(RSTDBYCTL);
1104 crstandvid = I915_READ16(CRSTANDVID);
1105
1106 mutex_unlock(&dev->struct_mutex);
1107
1108 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1109 "yes" : "no");
1110 seq_printf(m, "Boost freq: %d\n",
1111 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1112 MEMMODE_BOOST_FREQ_SHIFT);
1113 seq_printf(m, "HW control enabled: %s\n",
1114 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1115 seq_printf(m, "SW control enabled: %s\n",
1116 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1117 seq_printf(m, "Gated voltage change: %s\n",
1118 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1119 seq_printf(m, "Starting frequency: P%d\n",
1120 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1121 seq_printf(m, "Max P-state: P%d\n",
1122 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1123 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1124 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1125 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1126 seq_printf(m, "Render standby enabled: %s\n",
1127 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1128 seq_puts(m, "Current RS state: ");
1129 switch (rstdbyctl & RSX_STATUS_MASK) {
1130 case RSX_STATUS_ON:
1131 seq_puts(m, "on\n");
1132 break;
1133 case RSX_STATUS_RC1:
1134 seq_puts(m, "RC1\n");
1135 break;
1136 case RSX_STATUS_RC1E:
1137 seq_puts(m, "RC1E\n");
1138 break;
1139 case RSX_STATUS_RS1:
1140 seq_puts(m, "RS1\n");
1141 break;
1142 case RSX_STATUS_RS2:
1143 seq_puts(m, "RS2 (RC6)\n");
1144 break;
1145 case RSX_STATUS_RS3:
1146 seq_puts(m, "RC3 (RC6+)\n");
1147 break;
1148 default:
1149 seq_puts(m, "unknown\n");
1150 break;
1151 }
1152
1153 return 0;
1154 }
1155
1156 static int gen6_drpc_info(struct seq_file *m)
1157 {
1158
1159 struct drm_info_node *node = (struct drm_info_node *) m->private;
1160 struct drm_device *dev = node->minor->dev;
1161 struct drm_i915_private *dev_priv = dev->dev_private;
1162 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1163 unsigned forcewake_count;
1164 int count = 0, ret;
1165
1166 ret = mutex_lock_interruptible(&dev->struct_mutex);
1167 if (ret)
1168 return ret;
1169
1170 spin_lock_irq(&dev_priv->uncore.lock);
1171 forcewake_count = dev_priv->uncore.forcewake_count;
1172 spin_unlock_irq(&dev_priv->uncore.lock);
1173
1174 if (forcewake_count) {
1175 seq_puts(m, "RC information inaccurate because somebody "
1176 "holds a forcewake reference \n");
1177 } else {
1178 /* NB: we cannot use forcewake, else we read the wrong values */
1179 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1180 udelay(10);
1181 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1182 }
1183
1184 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1185 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1186
1187 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1188 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1189 mutex_unlock(&dev->struct_mutex);
1190 mutex_lock(&dev_priv->rps.hw_lock);
1191 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1192 mutex_unlock(&dev_priv->rps.hw_lock);
1193
1194 seq_printf(m, "Video Turbo Mode: %s\n",
1195 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1196 seq_printf(m, "HW control enabled: %s\n",
1197 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1198 seq_printf(m, "SW control enabled: %s\n",
1199 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1200 GEN6_RP_MEDIA_SW_MODE));
1201 seq_printf(m, "RC1e Enabled: %s\n",
1202 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1203 seq_printf(m, "RC6 Enabled: %s\n",
1204 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1205 seq_printf(m, "Deep RC6 Enabled: %s\n",
1206 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1207 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1208 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1209 seq_puts(m, "Current RC state: ");
1210 switch (gt_core_status & GEN6_RCn_MASK) {
1211 case GEN6_RC0:
1212 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1213 seq_puts(m, "Core Power Down\n");
1214 else
1215 seq_puts(m, "on\n");
1216 break;
1217 case GEN6_RC3:
1218 seq_puts(m, "RC3\n");
1219 break;
1220 case GEN6_RC6:
1221 seq_puts(m, "RC6\n");
1222 break;
1223 case GEN6_RC7:
1224 seq_puts(m, "RC7\n");
1225 break;
1226 default:
1227 seq_puts(m, "Unknown\n");
1228 break;
1229 }
1230
1231 seq_printf(m, "Core Power Down: %s\n",
1232 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1233
1234 /* Not exactly sure what this is */
1235 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1236 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1237 seq_printf(m, "RC6 residency since boot: %u\n",
1238 I915_READ(GEN6_GT_GFX_RC6));
1239 seq_printf(m, "RC6+ residency since boot: %u\n",
1240 I915_READ(GEN6_GT_GFX_RC6p));
1241 seq_printf(m, "RC6++ residency since boot: %u\n",
1242 I915_READ(GEN6_GT_GFX_RC6pp));
1243
1244 seq_printf(m, "RC6 voltage: %dmV\n",
1245 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1246 seq_printf(m, "RC6+ voltage: %dmV\n",
1247 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1248 seq_printf(m, "RC6++ voltage: %dmV\n",
1249 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1250 return 0;
1251 }
1252
1253 static int i915_drpc_info(struct seq_file *m, void *unused)
1254 {
1255 struct drm_info_node *node = (struct drm_info_node *) m->private;
1256 struct drm_device *dev = node->minor->dev;
1257
1258 if (IS_GEN6(dev) || IS_GEN7(dev))
1259 return gen6_drpc_info(m);
1260 else
1261 return ironlake_drpc_info(m);
1262 }
1263
1264 static int i915_fbc_status(struct seq_file *m, void *unused)
1265 {
1266 struct drm_info_node *node = (struct drm_info_node *) m->private;
1267 struct drm_device *dev = node->minor->dev;
1268 drm_i915_private_t *dev_priv = dev->dev_private;
1269
1270 if (!I915_HAS_FBC(dev)) {
1271 seq_puts(m, "FBC unsupported on this chipset\n");
1272 return 0;
1273 }
1274
1275 if (intel_fbc_enabled(dev)) {
1276 seq_puts(m, "FBC enabled\n");
1277 } else {
1278 seq_puts(m, "FBC disabled: ");
1279 switch (dev_priv->fbc.no_fbc_reason) {
1280 case FBC_OK:
1281 seq_puts(m, "FBC actived, but currently disabled in hardware");
1282 break;
1283 case FBC_UNSUPPORTED:
1284 seq_puts(m, "unsupported by this chipset");
1285 break;
1286 case FBC_NO_OUTPUT:
1287 seq_puts(m, "no outputs");
1288 break;
1289 case FBC_STOLEN_TOO_SMALL:
1290 seq_puts(m, "not enough stolen memory");
1291 break;
1292 case FBC_UNSUPPORTED_MODE:
1293 seq_puts(m, "mode not supported");
1294 break;
1295 case FBC_MODE_TOO_LARGE:
1296 seq_puts(m, "mode too large");
1297 break;
1298 case FBC_BAD_PLANE:
1299 seq_puts(m, "FBC unsupported on plane");
1300 break;
1301 case FBC_NOT_TILED:
1302 seq_puts(m, "scanout buffer not tiled");
1303 break;
1304 case FBC_MULTIPLE_PIPES:
1305 seq_puts(m, "multiple pipes are enabled");
1306 break;
1307 case FBC_MODULE_PARAM:
1308 seq_puts(m, "disabled per module param (default off)");
1309 break;
1310 case FBC_CHIP_DEFAULT:
1311 seq_puts(m, "disabled per chip default");
1312 break;
1313 default:
1314 seq_puts(m, "unknown reason");
1315 }
1316 seq_putc(m, '\n');
1317 }
1318 return 0;
1319 }
1320
1321 static int i915_ips_status(struct seq_file *m, void *unused)
1322 {
1323 struct drm_info_node *node = (struct drm_info_node *) m->private;
1324 struct drm_device *dev = node->minor->dev;
1325 struct drm_i915_private *dev_priv = dev->dev_private;
1326
1327 if (!HAS_IPS(dev)) {
1328 seq_puts(m, "not supported\n");
1329 return 0;
1330 }
1331
1332 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1333 seq_puts(m, "enabled\n");
1334 else
1335 seq_puts(m, "disabled\n");
1336
1337 return 0;
1338 }
1339
1340 static int i915_sr_status(struct seq_file *m, void *unused)
1341 {
1342 struct drm_info_node *node = (struct drm_info_node *) m->private;
1343 struct drm_device *dev = node->minor->dev;
1344 drm_i915_private_t *dev_priv = dev->dev_private;
1345 bool sr_enabled = false;
1346
1347 if (HAS_PCH_SPLIT(dev))
1348 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1349 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1350 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1351 else if (IS_I915GM(dev))
1352 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1353 else if (IS_PINEVIEW(dev))
1354 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1355
1356 seq_printf(m, "self-refresh: %s\n",
1357 sr_enabled ? "enabled" : "disabled");
1358
1359 return 0;
1360 }
1361
1362 static int i915_emon_status(struct seq_file *m, void *unused)
1363 {
1364 struct drm_info_node *node = (struct drm_info_node *) m->private;
1365 struct drm_device *dev = node->minor->dev;
1366 drm_i915_private_t *dev_priv = dev->dev_private;
1367 unsigned long temp, chipset, gfx;
1368 int ret;
1369
1370 if (!IS_GEN5(dev))
1371 return -ENODEV;
1372
1373 ret = mutex_lock_interruptible(&dev->struct_mutex);
1374 if (ret)
1375 return ret;
1376
1377 temp = i915_mch_val(dev_priv);
1378 chipset = i915_chipset_val(dev_priv);
1379 gfx = i915_gfx_val(dev_priv);
1380 mutex_unlock(&dev->struct_mutex);
1381
1382 seq_printf(m, "GMCH temp: %ld\n", temp);
1383 seq_printf(m, "Chipset power: %ld\n", chipset);
1384 seq_printf(m, "GFX power: %ld\n", gfx);
1385 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1386
1387 return 0;
1388 }
1389
1390 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1391 {
1392 struct drm_info_node *node = (struct drm_info_node *) m->private;
1393 struct drm_device *dev = node->minor->dev;
1394 drm_i915_private_t *dev_priv = dev->dev_private;
1395 int ret;
1396 int gpu_freq, ia_freq;
1397
1398 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1399 seq_puts(m, "unsupported on this chipset\n");
1400 return 0;
1401 }
1402
1403 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1404
1405 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1406 if (ret)
1407 return ret;
1408
1409 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1410
1411 for (gpu_freq = dev_priv->rps.min_delay;
1412 gpu_freq <= dev_priv->rps.max_delay;
1413 gpu_freq++) {
1414 ia_freq = gpu_freq;
1415 sandybridge_pcode_read(dev_priv,
1416 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1417 &ia_freq);
1418 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1419 gpu_freq * GT_FREQUENCY_MULTIPLIER,
1420 ((ia_freq >> 0) & 0xff) * 100,
1421 ((ia_freq >> 8) & 0xff) * 100);
1422 }
1423
1424 mutex_unlock(&dev_priv->rps.hw_lock);
1425
1426 return 0;
1427 }
1428
1429 static int i915_gfxec(struct seq_file *m, void *unused)
1430 {
1431 struct drm_info_node *node = (struct drm_info_node *) m->private;
1432 struct drm_device *dev = node->minor->dev;
1433 drm_i915_private_t *dev_priv = dev->dev_private;
1434 int ret;
1435
1436 ret = mutex_lock_interruptible(&dev->struct_mutex);
1437 if (ret)
1438 return ret;
1439
1440 seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1441
1442 mutex_unlock(&dev->struct_mutex);
1443
1444 return 0;
1445 }
1446
1447 static int i915_opregion(struct seq_file *m, void *unused)
1448 {
1449 struct drm_info_node *node = (struct drm_info_node *) m->private;
1450 struct drm_device *dev = node->minor->dev;
1451 drm_i915_private_t *dev_priv = dev->dev_private;
1452 struct intel_opregion *opregion = &dev_priv->opregion;
1453 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1454 int ret;
1455
1456 if (data == NULL)
1457 return -ENOMEM;
1458
1459 ret = mutex_lock_interruptible(&dev->struct_mutex);
1460 if (ret)
1461 goto out;
1462
1463 if (opregion->header) {
1464 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1465 seq_write(m, data, OPREGION_SIZE);
1466 }
1467
1468 mutex_unlock(&dev->struct_mutex);
1469
1470 out:
1471 kfree(data);
1472 return 0;
1473 }
1474
1475 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1476 {
1477 struct drm_info_node *node = (struct drm_info_node *) m->private;
1478 struct drm_device *dev = node->minor->dev;
1479 struct intel_fbdev *ifbdev = NULL;
1480 struct intel_framebuffer *fb;
1481
1482 #ifdef CONFIG_DRM_I915_FBDEV
1483 struct drm_i915_private *dev_priv = dev->dev_private;
1484 int ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1485 if (ret)
1486 return ret;
1487
1488 ifbdev = dev_priv->fbdev;
1489 fb = to_intel_framebuffer(ifbdev->helper.fb);
1490
1491 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1492 fb->base.width,
1493 fb->base.height,
1494 fb->base.depth,
1495 fb->base.bits_per_pixel,
1496 atomic_read(&fb->base.refcount.refcount));
1497 describe_obj(m, fb->obj);
1498 seq_putc(m, '\n');
1499 mutex_unlock(&dev->mode_config.mutex);
1500 #endif
1501
1502 mutex_lock(&dev->mode_config.fb_lock);
1503 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1504 if (ifbdev && &fb->base == ifbdev->helper.fb)
1505 continue;
1506
1507 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1508 fb->base.width,
1509 fb->base.height,
1510 fb->base.depth,
1511 fb->base.bits_per_pixel,
1512 atomic_read(&fb->base.refcount.refcount));
1513 describe_obj(m, fb->obj);
1514 seq_putc(m, '\n');
1515 }
1516 mutex_unlock(&dev->mode_config.fb_lock);
1517
1518 return 0;
1519 }
1520
1521 static int i915_context_status(struct seq_file *m, void *unused)
1522 {
1523 struct drm_info_node *node = (struct drm_info_node *) m->private;
1524 struct drm_device *dev = node->minor->dev;
1525 drm_i915_private_t *dev_priv = dev->dev_private;
1526 struct intel_ring_buffer *ring;
1527 struct i915_hw_context *ctx;
1528 int ret, i;
1529
1530 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1531 if (ret)
1532 return ret;
1533
1534 if (dev_priv->ips.pwrctx) {
1535 seq_puts(m, "power context ");
1536 describe_obj(m, dev_priv->ips.pwrctx);
1537 seq_putc(m, '\n');
1538 }
1539
1540 if (dev_priv->ips.renderctx) {
1541 seq_puts(m, "render context ");
1542 describe_obj(m, dev_priv->ips.renderctx);
1543 seq_putc(m, '\n');
1544 }
1545
1546 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1547 seq_puts(m, "HW context ");
1548 describe_ctx(m, ctx);
1549 for_each_ring(ring, dev_priv, i)
1550 if (ring->default_context == ctx)
1551 seq_printf(m, "(default context %s) ", ring->name);
1552
1553 describe_obj(m, ctx->obj);
1554 seq_putc(m, '\n');
1555 }
1556
1557 mutex_unlock(&dev->mode_config.mutex);
1558
1559 return 0;
1560 }
1561
1562 static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1563 {
1564 struct drm_info_node *node = (struct drm_info_node *) m->private;
1565 struct drm_device *dev = node->minor->dev;
1566 struct drm_i915_private *dev_priv = dev->dev_private;
1567 unsigned forcewake_count;
1568
1569 spin_lock_irq(&dev_priv->uncore.lock);
1570 forcewake_count = dev_priv->uncore.forcewake_count;
1571 spin_unlock_irq(&dev_priv->uncore.lock);
1572
1573 seq_printf(m, "forcewake count = %u\n", forcewake_count);
1574
1575 return 0;
1576 }
1577
1578 static const char *swizzle_string(unsigned swizzle)
1579 {
1580 switch (swizzle) {
1581 case I915_BIT_6_SWIZZLE_NONE:
1582 return "none";
1583 case I915_BIT_6_SWIZZLE_9:
1584 return "bit9";
1585 case I915_BIT_6_SWIZZLE_9_10:
1586 return "bit9/bit10";
1587 case I915_BIT_6_SWIZZLE_9_11:
1588 return "bit9/bit11";
1589 case I915_BIT_6_SWIZZLE_9_10_11:
1590 return "bit9/bit10/bit11";
1591 case I915_BIT_6_SWIZZLE_9_17:
1592 return "bit9/bit17";
1593 case I915_BIT_6_SWIZZLE_9_10_17:
1594 return "bit9/bit10/bit17";
1595 case I915_BIT_6_SWIZZLE_UNKNOWN:
1596 return "unknown";
1597 }
1598
1599 return "bug";
1600 }
1601
1602 static int i915_swizzle_info(struct seq_file *m, void *data)
1603 {
1604 struct drm_info_node *node = (struct drm_info_node *) m->private;
1605 struct drm_device *dev = node->minor->dev;
1606 struct drm_i915_private *dev_priv = dev->dev_private;
1607 int ret;
1608
1609 ret = mutex_lock_interruptible(&dev->struct_mutex);
1610 if (ret)
1611 return ret;
1612
1613 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1614 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1615 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1616 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1617
1618 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1619 seq_printf(m, "DDC = 0x%08x\n",
1620 I915_READ(DCC));
1621 seq_printf(m, "C0DRB3 = 0x%04x\n",
1622 I915_READ16(C0DRB3));
1623 seq_printf(m, "C1DRB3 = 0x%04x\n",
1624 I915_READ16(C1DRB3));
1625 } else if (INTEL_INFO(dev)->gen >= 6) {
1626 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1627 I915_READ(MAD_DIMM_C0));
1628 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1629 I915_READ(MAD_DIMM_C1));
1630 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1631 I915_READ(MAD_DIMM_C2));
1632 seq_printf(m, "TILECTL = 0x%08x\n",
1633 I915_READ(TILECTL));
1634 if (IS_GEN8(dev))
1635 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
1636 I915_READ(GAMTARBMODE));
1637 else
1638 seq_printf(m, "ARB_MODE = 0x%08x\n",
1639 I915_READ(ARB_MODE));
1640 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1641 I915_READ(DISP_ARB_CTL));
1642 }
1643 mutex_unlock(&dev->struct_mutex);
1644
1645 return 0;
1646 }
1647
1648 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
1649 {
1650 struct drm_i915_private *dev_priv = dev->dev_private;
1651 struct intel_ring_buffer *ring;
1652 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1653 int unused, i;
1654
1655 if (!ppgtt)
1656 return;
1657
1658 seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
1659 seq_printf(m, "Page tables: %d\n", ppgtt->num_pt_pages);
1660 for_each_ring(ring, dev_priv, unused) {
1661 seq_printf(m, "%s\n", ring->name);
1662 for (i = 0; i < 4; i++) {
1663 u32 offset = 0x270 + i * 8;
1664 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
1665 pdp <<= 32;
1666 pdp |= I915_READ(ring->mmio_base + offset);
1667 for (i = 0; i < 4; i++)
1668 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
1669 }
1670 }
1671 }
1672
1673 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
1674 {
1675 struct drm_i915_private *dev_priv = dev->dev_private;
1676 struct intel_ring_buffer *ring;
1677 int i;
1678
1679 if (INTEL_INFO(dev)->gen == 6)
1680 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1681
1682 for_each_ring(ring, dev_priv, i) {
1683 seq_printf(m, "%s\n", ring->name);
1684 if (INTEL_INFO(dev)->gen == 7)
1685 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1686 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1687 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1688 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1689 }
1690 if (dev_priv->mm.aliasing_ppgtt) {
1691 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1692
1693 seq_puts(m, "aliasing PPGTT:\n");
1694 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1695 }
1696 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
1697 }
1698
1699 static int i915_ppgtt_info(struct seq_file *m, void *data)
1700 {
1701 struct drm_info_node *node = (struct drm_info_node *) m->private;
1702 struct drm_device *dev = node->minor->dev;
1703
1704 int ret = mutex_lock_interruptible(&dev->struct_mutex);
1705 if (ret)
1706 return ret;
1707
1708 if (INTEL_INFO(dev)->gen >= 8)
1709 gen8_ppgtt_info(m, dev);
1710 else if (INTEL_INFO(dev)->gen >= 6)
1711 gen6_ppgtt_info(m, dev);
1712
1713 mutex_unlock(&dev->struct_mutex);
1714
1715 return 0;
1716 }
1717
1718 static int i915_dpio_info(struct seq_file *m, void *data)
1719 {
1720 struct drm_info_node *node = (struct drm_info_node *) m->private;
1721 struct drm_device *dev = node->minor->dev;
1722 struct drm_i915_private *dev_priv = dev->dev_private;
1723 int ret;
1724
1725
1726 if (!IS_VALLEYVIEW(dev)) {
1727 seq_puts(m, "unsupported\n");
1728 return 0;
1729 }
1730
1731 ret = mutex_lock_interruptible(&dev_priv->dpio_lock);
1732 if (ret)
1733 return ret;
1734
1735 seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
1736
1737 seq_printf(m, "DPIO PLL DW3 CH0 : 0x%08x\n",
1738 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(0)));
1739 seq_printf(m, "DPIO PLL DW3 CH1: 0x%08x\n",
1740 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(1)));
1741
1742 seq_printf(m, "DPIO PLL DW5 CH0: 0x%08x\n",
1743 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(0)));
1744 seq_printf(m, "DPIO PLL DW5 CH1: 0x%08x\n",
1745 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(1)));
1746
1747 seq_printf(m, "DPIO PLL DW7 CH0: 0x%08x\n",
1748 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(0)));
1749 seq_printf(m, "DPIO PLL DW7 CH1: 0x%08x\n",
1750 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(1)));
1751
1752 seq_printf(m, "DPIO PLL DW10 CH0: 0x%08x\n",
1753 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW10(0)));
1754 seq_printf(m, "DPIO PLL DW10 CH1: 0x%08x\n",
1755 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW10(1)));
1756
1757 seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
1758 vlv_dpio_read(dev_priv, PIPE_A, VLV_CMN_DW0));
1759
1760 mutex_unlock(&dev_priv->dpio_lock);
1761
1762 return 0;
1763 }
1764
1765 static int i915_llc(struct seq_file *m, void *data)
1766 {
1767 struct drm_info_node *node = (struct drm_info_node *) m->private;
1768 struct drm_device *dev = node->minor->dev;
1769 struct drm_i915_private *dev_priv = dev->dev_private;
1770
1771 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
1772 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
1773 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
1774
1775 return 0;
1776 }
1777
1778 static int i915_edp_psr_status(struct seq_file *m, void *data)
1779 {
1780 struct drm_info_node *node = m->private;
1781 struct drm_device *dev = node->minor->dev;
1782 struct drm_i915_private *dev_priv = dev->dev_private;
1783 u32 psrperf = 0;
1784 bool enabled = false;
1785
1786 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
1787 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
1788
1789 enabled = HAS_PSR(dev) &&
1790 I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1791 seq_printf(m, "Enabled: %s\n", yesno(enabled));
1792
1793 if (HAS_PSR(dev))
1794 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
1795 EDP_PSR_PERF_CNT_MASK;
1796 seq_printf(m, "Performance_Counter: %u\n", psrperf);
1797
1798 return 0;
1799 }
1800
1801 static int i915_energy_uJ(struct seq_file *m, void *data)
1802 {
1803 struct drm_info_node *node = m->private;
1804 struct drm_device *dev = node->minor->dev;
1805 struct drm_i915_private *dev_priv = dev->dev_private;
1806 u64 power;
1807 u32 units;
1808
1809 if (INTEL_INFO(dev)->gen < 6)
1810 return -ENODEV;
1811
1812 rdmsrl(MSR_RAPL_POWER_UNIT, power);
1813 power = (power & 0x1f00) >> 8;
1814 units = 1000000 / (1 << power); /* convert to uJ */
1815 power = I915_READ(MCH_SECP_NRG_STTS);
1816 power *= units;
1817
1818 seq_printf(m, "%llu", (long long unsigned)power);
1819
1820 return 0;
1821 }
1822
1823 static int i915_pc8_status(struct seq_file *m, void *unused)
1824 {
1825 struct drm_info_node *node = (struct drm_info_node *) m->private;
1826 struct drm_device *dev = node->minor->dev;
1827 struct drm_i915_private *dev_priv = dev->dev_private;
1828
1829 if (!IS_HASWELL(dev)) {
1830 seq_puts(m, "not supported\n");
1831 return 0;
1832 }
1833
1834 mutex_lock(&dev_priv->pc8.lock);
1835 seq_printf(m, "Requirements met: %s\n",
1836 yesno(dev_priv->pc8.requirements_met));
1837 seq_printf(m, "GPU idle: %s\n", yesno(dev_priv->pc8.gpu_idle));
1838 seq_printf(m, "Disable count: %d\n", dev_priv->pc8.disable_count);
1839 seq_printf(m, "IRQs disabled: %s\n",
1840 yesno(dev_priv->pc8.irqs_disabled));
1841 seq_printf(m, "Enabled: %s\n", yesno(dev_priv->pc8.enabled));
1842 mutex_unlock(&dev_priv->pc8.lock);
1843
1844 return 0;
1845 }
1846
1847 static const char *power_domain_str(enum intel_display_power_domain domain)
1848 {
1849 switch (domain) {
1850 case POWER_DOMAIN_PIPE_A:
1851 return "PIPE_A";
1852 case POWER_DOMAIN_PIPE_B:
1853 return "PIPE_B";
1854 case POWER_DOMAIN_PIPE_C:
1855 return "PIPE_C";
1856 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
1857 return "PIPE_A_PANEL_FITTER";
1858 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
1859 return "PIPE_B_PANEL_FITTER";
1860 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
1861 return "PIPE_C_PANEL_FITTER";
1862 case POWER_DOMAIN_TRANSCODER_A:
1863 return "TRANSCODER_A";
1864 case POWER_DOMAIN_TRANSCODER_B:
1865 return "TRANSCODER_B";
1866 case POWER_DOMAIN_TRANSCODER_C:
1867 return "TRANSCODER_C";
1868 case POWER_DOMAIN_TRANSCODER_EDP:
1869 return "TRANSCODER_EDP";
1870 case POWER_DOMAIN_VGA:
1871 return "VGA";
1872 case POWER_DOMAIN_AUDIO:
1873 return "AUDIO";
1874 case POWER_DOMAIN_INIT:
1875 return "INIT";
1876 default:
1877 WARN_ON(1);
1878 return "?";
1879 }
1880 }
1881
1882 static int i915_power_domain_info(struct seq_file *m, void *unused)
1883 {
1884 struct drm_info_node *node = (struct drm_info_node *) m->private;
1885 struct drm_device *dev = node->minor->dev;
1886 struct drm_i915_private *dev_priv = dev->dev_private;
1887 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1888 int i;
1889
1890 mutex_lock(&power_domains->lock);
1891
1892 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
1893 for (i = 0; i < power_domains->power_well_count; i++) {
1894 struct i915_power_well *power_well;
1895 enum intel_display_power_domain power_domain;
1896
1897 power_well = &power_domains->power_wells[i];
1898 seq_printf(m, "%-25s %d\n", power_well->name,
1899 power_well->count);
1900
1901 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
1902 power_domain++) {
1903 if (!(BIT(power_domain) & power_well->domains))
1904 continue;
1905
1906 seq_printf(m, " %-23s %d\n",
1907 power_domain_str(power_domain),
1908 power_domains->domain_use_count[power_domain]);
1909 }
1910 }
1911
1912 mutex_unlock(&power_domains->lock);
1913
1914 return 0;
1915 }
1916
1917 struct pipe_crc_info {
1918 const char *name;
1919 struct drm_device *dev;
1920 enum pipe pipe;
1921 };
1922
1923 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
1924 {
1925 struct pipe_crc_info *info = inode->i_private;
1926 struct drm_i915_private *dev_priv = info->dev->dev_private;
1927 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
1928
1929 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
1930 return -ENODEV;
1931
1932 spin_lock_irq(&pipe_crc->lock);
1933
1934 if (pipe_crc->opened) {
1935 spin_unlock_irq(&pipe_crc->lock);
1936 return -EBUSY; /* already open */
1937 }
1938
1939 pipe_crc->opened = true;
1940 filep->private_data = inode->i_private;
1941
1942 spin_unlock_irq(&pipe_crc->lock);
1943
1944 return 0;
1945 }
1946
1947 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
1948 {
1949 struct pipe_crc_info *info = inode->i_private;
1950 struct drm_i915_private *dev_priv = info->dev->dev_private;
1951 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
1952
1953 spin_lock_irq(&pipe_crc->lock);
1954 pipe_crc->opened = false;
1955 spin_unlock_irq(&pipe_crc->lock);
1956
1957 return 0;
1958 }
1959
1960 /* (6 fields, 8 chars each, space separated (5) + '\n') */
1961 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
1962 /* account for \'0' */
1963 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
1964
1965 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
1966 {
1967 assert_spin_locked(&pipe_crc->lock);
1968 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
1969 INTEL_PIPE_CRC_ENTRIES_NR);
1970 }
1971
1972 static ssize_t
1973 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
1974 loff_t *pos)
1975 {
1976 struct pipe_crc_info *info = filep->private_data;
1977 struct drm_device *dev = info->dev;
1978 struct drm_i915_private *dev_priv = dev->dev_private;
1979 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
1980 char buf[PIPE_CRC_BUFFER_LEN];
1981 int head, tail, n_entries, n;
1982 ssize_t bytes_read;
1983
1984 /*
1985 * Don't allow user space to provide buffers not big enough to hold
1986 * a line of data.
1987 */
1988 if (count < PIPE_CRC_LINE_LEN)
1989 return -EINVAL;
1990
1991 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
1992 return 0;
1993
1994 /* nothing to read */
1995 spin_lock_irq(&pipe_crc->lock);
1996 while (pipe_crc_data_count(pipe_crc) == 0) {
1997 int ret;
1998
1999 if (filep->f_flags & O_NONBLOCK) {
2000 spin_unlock_irq(&pipe_crc->lock);
2001 return -EAGAIN;
2002 }
2003
2004 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2005 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2006 if (ret) {
2007 spin_unlock_irq(&pipe_crc->lock);
2008 return ret;
2009 }
2010 }
2011
2012 /* We now have one or more entries to read */
2013 head = pipe_crc->head;
2014 tail = pipe_crc->tail;
2015 n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR),
2016 count / PIPE_CRC_LINE_LEN);
2017 spin_unlock_irq(&pipe_crc->lock);
2018
2019 bytes_read = 0;
2020 n = 0;
2021 do {
2022 struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail];
2023 int ret;
2024
2025 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
2026 "%8u %8x %8x %8x %8x %8x\n",
2027 entry->frame, entry->crc[0],
2028 entry->crc[1], entry->crc[2],
2029 entry->crc[3], entry->crc[4]);
2030
2031 ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN,
2032 buf, PIPE_CRC_LINE_LEN);
2033 if (ret == PIPE_CRC_LINE_LEN)
2034 return -EFAULT;
2035
2036 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
2037 tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
2038 n++;
2039 } while (--n_entries);
2040
2041 spin_lock_irq(&pipe_crc->lock);
2042 pipe_crc->tail = tail;
2043 spin_unlock_irq(&pipe_crc->lock);
2044
2045 return bytes_read;
2046 }
2047
2048 static const struct file_operations i915_pipe_crc_fops = {
2049 .owner = THIS_MODULE,
2050 .open = i915_pipe_crc_open,
2051 .read = i915_pipe_crc_read,
2052 .release = i915_pipe_crc_release,
2053 };
2054
2055 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
2056 {
2057 .name = "i915_pipe_A_crc",
2058 .pipe = PIPE_A,
2059 },
2060 {
2061 .name = "i915_pipe_B_crc",
2062 .pipe = PIPE_B,
2063 },
2064 {
2065 .name = "i915_pipe_C_crc",
2066 .pipe = PIPE_C,
2067 },
2068 };
2069
2070 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
2071 enum pipe pipe)
2072 {
2073 struct drm_device *dev = minor->dev;
2074 struct dentry *ent;
2075 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
2076
2077 info->dev = dev;
2078 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
2079 &i915_pipe_crc_fops);
2080 if (IS_ERR(ent))
2081 return PTR_ERR(ent);
2082
2083 return drm_add_fake_info_node(minor, ent, info);
2084 }
2085
2086 static const char * const pipe_crc_sources[] = {
2087 "none",
2088 "plane1",
2089 "plane2",
2090 "pf",
2091 "pipe",
2092 "TV",
2093 "DP-B",
2094 "DP-C",
2095 "DP-D",
2096 "auto",
2097 };
2098
2099 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
2100 {
2101 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
2102 return pipe_crc_sources[source];
2103 }
2104
2105 static int display_crc_ctl_show(struct seq_file *m, void *data)
2106 {
2107 struct drm_device *dev = m->private;
2108 struct drm_i915_private *dev_priv = dev->dev_private;
2109 int i;
2110
2111 for (i = 0; i < I915_MAX_PIPES; i++)
2112 seq_printf(m, "%c %s\n", pipe_name(i),
2113 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
2114
2115 return 0;
2116 }
2117
2118 static int display_crc_ctl_open(struct inode *inode, struct file *file)
2119 {
2120 struct drm_device *dev = inode->i_private;
2121
2122 return single_open(file, display_crc_ctl_show, dev);
2123 }
2124
2125 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
2126 uint32_t *val)
2127 {
2128 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2129 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2130
2131 switch (*source) {
2132 case INTEL_PIPE_CRC_SOURCE_PIPE:
2133 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
2134 break;
2135 case INTEL_PIPE_CRC_SOURCE_NONE:
2136 *val = 0;
2137 break;
2138 default:
2139 return -EINVAL;
2140 }
2141
2142 return 0;
2143 }
2144
2145 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
2146 enum intel_pipe_crc_source *source)
2147 {
2148 struct intel_encoder *encoder;
2149 struct intel_crtc *crtc;
2150 struct intel_digital_port *dig_port;
2151 int ret = 0;
2152
2153 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2154
2155 mutex_lock(&dev->mode_config.mutex);
2156 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2157 base.head) {
2158 if (!encoder->base.crtc)
2159 continue;
2160
2161 crtc = to_intel_crtc(encoder->base.crtc);
2162
2163 if (crtc->pipe != pipe)
2164 continue;
2165
2166 switch (encoder->type) {
2167 case INTEL_OUTPUT_TVOUT:
2168 *source = INTEL_PIPE_CRC_SOURCE_TV;
2169 break;
2170 case INTEL_OUTPUT_DISPLAYPORT:
2171 case INTEL_OUTPUT_EDP:
2172 dig_port = enc_to_dig_port(&encoder->base);
2173 switch (dig_port->port) {
2174 case PORT_B:
2175 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
2176 break;
2177 case PORT_C:
2178 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
2179 break;
2180 case PORT_D:
2181 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
2182 break;
2183 default:
2184 WARN(1, "nonexisting DP port %c\n",
2185 port_name(dig_port->port));
2186 break;
2187 }
2188 break;
2189 }
2190 }
2191 mutex_unlock(&dev->mode_config.mutex);
2192
2193 return ret;
2194 }
2195
2196 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
2197 enum pipe pipe,
2198 enum intel_pipe_crc_source *source,
2199 uint32_t *val)
2200 {
2201 struct drm_i915_private *dev_priv = dev->dev_private;
2202 bool need_stable_symbols = false;
2203
2204 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2205 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2206 if (ret)
2207 return ret;
2208 }
2209
2210 switch (*source) {
2211 case INTEL_PIPE_CRC_SOURCE_PIPE:
2212 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
2213 break;
2214 case INTEL_PIPE_CRC_SOURCE_DP_B:
2215 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
2216 need_stable_symbols = true;
2217 break;
2218 case INTEL_PIPE_CRC_SOURCE_DP_C:
2219 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
2220 need_stable_symbols = true;
2221 break;
2222 case INTEL_PIPE_CRC_SOURCE_NONE:
2223 *val = 0;
2224 break;
2225 default:
2226 return -EINVAL;
2227 }
2228
2229 /*
2230 * When the pipe CRC tap point is after the transcoders we need
2231 * to tweak symbol-level features to produce a deterministic series of
2232 * symbols for a given frame. We need to reset those features only once
2233 * a frame (instead of every nth symbol):
2234 * - DC-balance: used to ensure a better clock recovery from the data
2235 * link (SDVO)
2236 * - DisplayPort scrambling: used for EMI reduction
2237 */
2238 if (need_stable_symbols) {
2239 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2240
2241 WARN_ON(!IS_G4X(dev));
2242
2243 tmp |= DC_BALANCE_RESET_VLV;
2244 if (pipe == PIPE_A)
2245 tmp |= PIPE_A_SCRAMBLE_RESET;
2246 else
2247 tmp |= PIPE_B_SCRAMBLE_RESET;
2248
2249 I915_WRITE(PORT_DFT2_G4X, tmp);
2250 }
2251
2252 return 0;
2253 }
2254
2255 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
2256 enum pipe pipe,
2257 enum intel_pipe_crc_source *source,
2258 uint32_t *val)
2259 {
2260 struct drm_i915_private *dev_priv = dev->dev_private;
2261 bool need_stable_symbols = false;
2262
2263 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2264 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2265 if (ret)
2266 return ret;
2267 }
2268
2269 switch (*source) {
2270 case INTEL_PIPE_CRC_SOURCE_PIPE:
2271 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
2272 break;
2273 case INTEL_PIPE_CRC_SOURCE_TV:
2274 if (!SUPPORTS_TV(dev))
2275 return -EINVAL;
2276 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
2277 break;
2278 case INTEL_PIPE_CRC_SOURCE_DP_B:
2279 if (!IS_G4X(dev))
2280 return -EINVAL;
2281 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
2282 need_stable_symbols = true;
2283 break;
2284 case INTEL_PIPE_CRC_SOURCE_DP_C:
2285 if (!IS_G4X(dev))
2286 return -EINVAL;
2287 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
2288 need_stable_symbols = true;
2289 break;
2290 case INTEL_PIPE_CRC_SOURCE_DP_D:
2291 if (!IS_G4X(dev))
2292 return -EINVAL;
2293 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
2294 need_stable_symbols = true;
2295 break;
2296 case INTEL_PIPE_CRC_SOURCE_NONE:
2297 *val = 0;
2298 break;
2299 default:
2300 return -EINVAL;
2301 }
2302
2303 /*
2304 * When the pipe CRC tap point is after the transcoders we need
2305 * to tweak symbol-level features to produce a deterministic series of
2306 * symbols for a given frame. We need to reset those features only once
2307 * a frame (instead of every nth symbol):
2308 * - DC-balance: used to ensure a better clock recovery from the data
2309 * link (SDVO)
2310 * - DisplayPort scrambling: used for EMI reduction
2311 */
2312 if (need_stable_symbols) {
2313 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2314
2315 WARN_ON(!IS_G4X(dev));
2316
2317 I915_WRITE(PORT_DFT_I9XX,
2318 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
2319
2320 if (pipe == PIPE_A)
2321 tmp |= PIPE_A_SCRAMBLE_RESET;
2322 else
2323 tmp |= PIPE_B_SCRAMBLE_RESET;
2324
2325 I915_WRITE(PORT_DFT2_G4X, tmp);
2326 }
2327
2328 return 0;
2329 }
2330
2331 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
2332 enum pipe pipe)
2333 {
2334 struct drm_i915_private *dev_priv = dev->dev_private;
2335 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2336
2337 if (pipe == PIPE_A)
2338 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2339 else
2340 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2341 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
2342 tmp &= ~DC_BALANCE_RESET_VLV;
2343 I915_WRITE(PORT_DFT2_G4X, tmp);
2344
2345 }
2346
2347 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
2348 enum pipe pipe)
2349 {
2350 struct drm_i915_private *dev_priv = dev->dev_private;
2351 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2352
2353 if (pipe == PIPE_A)
2354 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2355 else
2356 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2357 I915_WRITE(PORT_DFT2_G4X, tmp);
2358
2359 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
2360 I915_WRITE(PORT_DFT_I9XX,
2361 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
2362 }
2363 }
2364
2365 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
2366 uint32_t *val)
2367 {
2368 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2369 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2370
2371 switch (*source) {
2372 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2373 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
2374 break;
2375 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2376 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
2377 break;
2378 case INTEL_PIPE_CRC_SOURCE_PIPE:
2379 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
2380 break;
2381 case INTEL_PIPE_CRC_SOURCE_NONE:
2382 *val = 0;
2383 break;
2384 default:
2385 return -EINVAL;
2386 }
2387
2388 return 0;
2389 }
2390
2391 static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
2392 uint32_t *val)
2393 {
2394 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2395 *source = INTEL_PIPE_CRC_SOURCE_PF;
2396
2397 switch (*source) {
2398 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2399 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
2400 break;
2401 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2402 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
2403 break;
2404 case INTEL_PIPE_CRC_SOURCE_PF:
2405 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
2406 break;
2407 case INTEL_PIPE_CRC_SOURCE_NONE:
2408 *val = 0;
2409 break;
2410 default:
2411 return -EINVAL;
2412 }
2413
2414 return 0;
2415 }
2416
2417 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
2418 enum intel_pipe_crc_source source)
2419 {
2420 struct drm_i915_private *dev_priv = dev->dev_private;
2421 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
2422 u32 val = 0; /* shut up gcc */
2423 int ret;
2424
2425 if (pipe_crc->source == source)
2426 return 0;
2427
2428 /* forbid changing the source without going back to 'none' */
2429 if (pipe_crc->source && source)
2430 return -EINVAL;
2431
2432 if (IS_GEN2(dev))
2433 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
2434 else if (INTEL_INFO(dev)->gen < 5)
2435 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
2436 else if (IS_VALLEYVIEW(dev))
2437 ret = vlv_pipe_crc_ctl_reg(dev,pipe, &source, &val);
2438 else if (IS_GEN5(dev) || IS_GEN6(dev))
2439 ret = ilk_pipe_crc_ctl_reg(&source, &val);
2440 else
2441 ret = ivb_pipe_crc_ctl_reg(&source, &val);
2442
2443 if (ret != 0)
2444 return ret;
2445
2446 /* none -> real source transition */
2447 if (source) {
2448 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
2449 pipe_name(pipe), pipe_crc_source_name(source));
2450
2451 pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) *
2452 INTEL_PIPE_CRC_ENTRIES_NR,
2453 GFP_KERNEL);
2454 if (!pipe_crc->entries)
2455 return -ENOMEM;
2456
2457 spin_lock_irq(&pipe_crc->lock);
2458 pipe_crc->head = 0;
2459 pipe_crc->tail = 0;
2460 spin_unlock_irq(&pipe_crc->lock);
2461 }
2462
2463 pipe_crc->source = source;
2464
2465 I915_WRITE(PIPE_CRC_CTL(pipe), val);
2466 POSTING_READ(PIPE_CRC_CTL(pipe));
2467
2468 /* real source -> none transition */
2469 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
2470 struct intel_pipe_crc_entry *entries;
2471
2472 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
2473 pipe_name(pipe));
2474
2475 intel_wait_for_vblank(dev, pipe);
2476
2477 spin_lock_irq(&pipe_crc->lock);
2478 entries = pipe_crc->entries;
2479 pipe_crc->entries = NULL;
2480 spin_unlock_irq(&pipe_crc->lock);
2481
2482 kfree(entries);
2483
2484 if (IS_G4X(dev))
2485 g4x_undo_pipe_scramble_reset(dev, pipe);
2486 else if (IS_VALLEYVIEW(dev))
2487 vlv_undo_pipe_scramble_reset(dev, pipe);
2488 }
2489
2490 return 0;
2491 }
2492
2493 /*
2494 * Parse pipe CRC command strings:
2495 * command: wsp* object wsp+ name wsp+ source wsp*
2496 * object: 'pipe'
2497 * name: (A | B | C)
2498 * source: (none | plane1 | plane2 | pf)
2499 * wsp: (#0x20 | #0x9 | #0xA)+
2500 *
2501 * eg.:
2502 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
2503 * "pipe A none" -> Stop CRC
2504 */
2505 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
2506 {
2507 int n_words = 0;
2508
2509 while (*buf) {
2510 char *end;
2511
2512 /* skip leading white space */
2513 buf = skip_spaces(buf);
2514 if (!*buf)
2515 break; /* end of buffer */
2516
2517 /* find end of word */
2518 for (end = buf; *end && !isspace(*end); end++)
2519 ;
2520
2521 if (n_words == max_words) {
2522 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
2523 max_words);
2524 return -EINVAL; /* ran out of words[] before bytes */
2525 }
2526
2527 if (*end)
2528 *end++ = '\0';
2529 words[n_words++] = buf;
2530 buf = end;
2531 }
2532
2533 return n_words;
2534 }
2535
2536 enum intel_pipe_crc_object {
2537 PIPE_CRC_OBJECT_PIPE,
2538 };
2539
2540 static const char * const pipe_crc_objects[] = {
2541 "pipe",
2542 };
2543
2544 static int
2545 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
2546 {
2547 int i;
2548
2549 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
2550 if (!strcmp(buf, pipe_crc_objects[i])) {
2551 *o = i;
2552 return 0;
2553 }
2554
2555 return -EINVAL;
2556 }
2557
2558 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
2559 {
2560 const char name = buf[0];
2561
2562 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
2563 return -EINVAL;
2564
2565 *pipe = name - 'A';
2566
2567 return 0;
2568 }
2569
2570 static int
2571 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
2572 {
2573 int i;
2574
2575 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
2576 if (!strcmp(buf, pipe_crc_sources[i])) {
2577 *s = i;
2578 return 0;
2579 }
2580
2581 return -EINVAL;
2582 }
2583
2584 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
2585 {
2586 #define N_WORDS 3
2587 int n_words;
2588 char *words[N_WORDS];
2589 enum pipe pipe;
2590 enum intel_pipe_crc_object object;
2591 enum intel_pipe_crc_source source;
2592
2593 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
2594 if (n_words != N_WORDS) {
2595 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
2596 N_WORDS);
2597 return -EINVAL;
2598 }
2599
2600 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
2601 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
2602 return -EINVAL;
2603 }
2604
2605 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
2606 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
2607 return -EINVAL;
2608 }
2609
2610 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
2611 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
2612 return -EINVAL;
2613 }
2614
2615 return pipe_crc_set_source(dev, pipe, source);
2616 }
2617
2618 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
2619 size_t len, loff_t *offp)
2620 {
2621 struct seq_file *m = file->private_data;
2622 struct drm_device *dev = m->private;
2623 char *tmpbuf;
2624 int ret;
2625
2626 if (len == 0)
2627 return 0;
2628
2629 if (len > PAGE_SIZE - 1) {
2630 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
2631 PAGE_SIZE);
2632 return -E2BIG;
2633 }
2634
2635 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
2636 if (!tmpbuf)
2637 return -ENOMEM;
2638
2639 if (copy_from_user(tmpbuf, ubuf, len)) {
2640 ret = -EFAULT;
2641 goto out;
2642 }
2643 tmpbuf[len] = '\0';
2644
2645 ret = display_crc_ctl_parse(dev, tmpbuf, len);
2646
2647 out:
2648 kfree(tmpbuf);
2649 if (ret < 0)
2650 return ret;
2651
2652 *offp += len;
2653 return len;
2654 }
2655
2656 static const struct file_operations i915_display_crc_ctl_fops = {
2657 .owner = THIS_MODULE,
2658 .open = display_crc_ctl_open,
2659 .read = seq_read,
2660 .llseek = seq_lseek,
2661 .release = single_release,
2662 .write = display_crc_ctl_write
2663 };
2664
2665 static int
2666 i915_wedged_get(void *data, u64 *val)
2667 {
2668 struct drm_device *dev = data;
2669 drm_i915_private_t *dev_priv = dev->dev_private;
2670
2671 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
2672
2673 return 0;
2674 }
2675
2676 static int
2677 i915_wedged_set(void *data, u64 val)
2678 {
2679 struct drm_device *dev = data;
2680
2681 DRM_INFO("Manually setting wedged to %llu\n", val);
2682 i915_handle_error(dev, val);
2683
2684 return 0;
2685 }
2686
2687 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
2688 i915_wedged_get, i915_wedged_set,
2689 "%llu\n");
2690
2691 static int
2692 i915_ring_stop_get(void *data, u64 *val)
2693 {
2694 struct drm_device *dev = data;
2695 drm_i915_private_t *dev_priv = dev->dev_private;
2696
2697 *val = dev_priv->gpu_error.stop_rings;
2698
2699 return 0;
2700 }
2701
2702 static int
2703 i915_ring_stop_set(void *data, u64 val)
2704 {
2705 struct drm_device *dev = data;
2706 struct drm_i915_private *dev_priv = dev->dev_private;
2707 int ret;
2708
2709 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
2710
2711 ret = mutex_lock_interruptible(&dev->struct_mutex);
2712 if (ret)
2713 return ret;
2714
2715 dev_priv->gpu_error.stop_rings = val;
2716 mutex_unlock(&dev->struct_mutex);
2717
2718 return 0;
2719 }
2720
2721 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
2722 i915_ring_stop_get, i915_ring_stop_set,
2723 "0x%08llx\n");
2724
2725 static int
2726 i915_ring_missed_irq_get(void *data, u64 *val)
2727 {
2728 struct drm_device *dev = data;
2729 struct drm_i915_private *dev_priv = dev->dev_private;
2730
2731 *val = dev_priv->gpu_error.missed_irq_rings;
2732 return 0;
2733 }
2734
2735 static int
2736 i915_ring_missed_irq_set(void *data, u64 val)
2737 {
2738 struct drm_device *dev = data;
2739 struct drm_i915_private *dev_priv = dev->dev_private;
2740 int ret;
2741
2742 /* Lock against concurrent debugfs callers */
2743 ret = mutex_lock_interruptible(&dev->struct_mutex);
2744 if (ret)
2745 return ret;
2746 dev_priv->gpu_error.missed_irq_rings = val;
2747 mutex_unlock(&dev->struct_mutex);
2748
2749 return 0;
2750 }
2751
2752 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
2753 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
2754 "0x%08llx\n");
2755
2756 static int
2757 i915_ring_test_irq_get(void *data, u64 *val)
2758 {
2759 struct drm_device *dev = data;
2760 struct drm_i915_private *dev_priv = dev->dev_private;
2761
2762 *val = dev_priv->gpu_error.test_irq_rings;
2763
2764 return 0;
2765 }
2766
2767 static int
2768 i915_ring_test_irq_set(void *data, u64 val)
2769 {
2770 struct drm_device *dev = data;
2771 struct drm_i915_private *dev_priv = dev->dev_private;
2772 int ret;
2773
2774 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
2775
2776 /* Lock against concurrent debugfs callers */
2777 ret = mutex_lock_interruptible(&dev->struct_mutex);
2778 if (ret)
2779 return ret;
2780
2781 dev_priv->gpu_error.test_irq_rings = val;
2782 mutex_unlock(&dev->struct_mutex);
2783
2784 return 0;
2785 }
2786
2787 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
2788 i915_ring_test_irq_get, i915_ring_test_irq_set,
2789 "0x%08llx\n");
2790
2791 #define DROP_UNBOUND 0x1
2792 #define DROP_BOUND 0x2
2793 #define DROP_RETIRE 0x4
2794 #define DROP_ACTIVE 0x8
2795 #define DROP_ALL (DROP_UNBOUND | \
2796 DROP_BOUND | \
2797 DROP_RETIRE | \
2798 DROP_ACTIVE)
2799 static int
2800 i915_drop_caches_get(void *data, u64 *val)
2801 {
2802 *val = DROP_ALL;
2803
2804 return 0;
2805 }
2806
2807 static int
2808 i915_drop_caches_set(void *data, u64 val)
2809 {
2810 struct drm_device *dev = data;
2811 struct drm_i915_private *dev_priv = dev->dev_private;
2812 struct drm_i915_gem_object *obj, *next;
2813 struct i915_address_space *vm;
2814 struct i915_vma *vma, *x;
2815 int ret;
2816
2817 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
2818
2819 /* No need to check and wait for gpu resets, only libdrm auto-restarts
2820 * on ioctls on -EAGAIN. */
2821 ret = mutex_lock_interruptible(&dev->struct_mutex);
2822 if (ret)
2823 return ret;
2824
2825 if (val & DROP_ACTIVE) {
2826 ret = i915_gpu_idle(dev);
2827 if (ret)
2828 goto unlock;
2829 }
2830
2831 if (val & (DROP_RETIRE | DROP_ACTIVE))
2832 i915_gem_retire_requests(dev);
2833
2834 if (val & DROP_BOUND) {
2835 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2836 list_for_each_entry_safe(vma, x, &vm->inactive_list,
2837 mm_list) {
2838 if (vma->obj->pin_count)
2839 continue;
2840
2841 ret = i915_vma_unbind(vma);
2842 if (ret)
2843 goto unlock;
2844 }
2845 }
2846 }
2847
2848 if (val & DROP_UNBOUND) {
2849 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
2850 global_list)
2851 if (obj->pages_pin_count == 0) {
2852 ret = i915_gem_object_put_pages(obj);
2853 if (ret)
2854 goto unlock;
2855 }
2856 }
2857
2858 unlock:
2859 mutex_unlock(&dev->struct_mutex);
2860
2861 return ret;
2862 }
2863
2864 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
2865 i915_drop_caches_get, i915_drop_caches_set,
2866 "0x%08llx\n");
2867
2868 static int
2869 i915_max_freq_get(void *data, u64 *val)
2870 {
2871 struct drm_device *dev = data;
2872 drm_i915_private_t *dev_priv = dev->dev_private;
2873 int ret;
2874
2875 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2876 return -ENODEV;
2877
2878 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
2879
2880 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2881 if (ret)
2882 return ret;
2883
2884 if (IS_VALLEYVIEW(dev))
2885 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay);
2886 else
2887 *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
2888 mutex_unlock(&dev_priv->rps.hw_lock);
2889
2890 return 0;
2891 }
2892
2893 static int
2894 i915_max_freq_set(void *data, u64 val)
2895 {
2896 struct drm_device *dev = data;
2897 struct drm_i915_private *dev_priv = dev->dev_private;
2898 int ret;
2899
2900 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2901 return -ENODEV;
2902
2903 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
2904
2905 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
2906
2907 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2908 if (ret)
2909 return ret;
2910
2911 /*
2912 * Turbo will still be enabled, but won't go above the set value.
2913 */
2914 if (IS_VALLEYVIEW(dev)) {
2915 val = vlv_freq_opcode(dev_priv, val);
2916 dev_priv->rps.max_delay = val;
2917 valleyview_set_rps(dev, val);
2918 } else {
2919 do_div(val, GT_FREQUENCY_MULTIPLIER);
2920 dev_priv->rps.max_delay = val;
2921 gen6_set_rps(dev, val);
2922 }
2923
2924 mutex_unlock(&dev_priv->rps.hw_lock);
2925
2926 return 0;
2927 }
2928
2929 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
2930 i915_max_freq_get, i915_max_freq_set,
2931 "%llu\n");
2932
2933 static int
2934 i915_min_freq_get(void *data, u64 *val)
2935 {
2936 struct drm_device *dev = data;
2937 drm_i915_private_t *dev_priv = dev->dev_private;
2938 int ret;
2939
2940 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2941 return -ENODEV;
2942
2943 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
2944
2945 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2946 if (ret)
2947 return ret;
2948
2949 if (IS_VALLEYVIEW(dev))
2950 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay);
2951 else
2952 *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
2953 mutex_unlock(&dev_priv->rps.hw_lock);
2954
2955 return 0;
2956 }
2957
2958 static int
2959 i915_min_freq_set(void *data, u64 val)
2960 {
2961 struct drm_device *dev = data;
2962 struct drm_i915_private *dev_priv = dev->dev_private;
2963 int ret;
2964
2965 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2966 return -ENODEV;
2967
2968 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
2969
2970 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
2971
2972 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2973 if (ret)
2974 return ret;
2975
2976 /*
2977 * Turbo will still be enabled, but won't go below the set value.
2978 */
2979 if (IS_VALLEYVIEW(dev)) {
2980 val = vlv_freq_opcode(dev_priv, val);
2981 dev_priv->rps.min_delay = val;
2982 valleyview_set_rps(dev, val);
2983 } else {
2984 do_div(val, GT_FREQUENCY_MULTIPLIER);
2985 dev_priv->rps.min_delay = val;
2986 gen6_set_rps(dev, val);
2987 }
2988 mutex_unlock(&dev_priv->rps.hw_lock);
2989
2990 return 0;
2991 }
2992
2993 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
2994 i915_min_freq_get, i915_min_freq_set,
2995 "%llu\n");
2996
2997 static int
2998 i915_cache_sharing_get(void *data, u64 *val)
2999 {
3000 struct drm_device *dev = data;
3001 drm_i915_private_t *dev_priv = dev->dev_private;
3002 u32 snpcr;
3003 int ret;
3004
3005 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3006 return -ENODEV;
3007
3008 ret = mutex_lock_interruptible(&dev->struct_mutex);
3009 if (ret)
3010 return ret;
3011
3012 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3013 mutex_unlock(&dev_priv->dev->struct_mutex);
3014
3015 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
3016
3017 return 0;
3018 }
3019
3020 static int
3021 i915_cache_sharing_set(void *data, u64 val)
3022 {
3023 struct drm_device *dev = data;
3024 struct drm_i915_private *dev_priv = dev->dev_private;
3025 u32 snpcr;
3026
3027 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3028 return -ENODEV;
3029
3030 if (val > 3)
3031 return -EINVAL;
3032
3033 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
3034
3035 /* Update the cache sharing policy here as well */
3036 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3037 snpcr &= ~GEN6_MBC_SNPCR_MASK;
3038 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
3039 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3040
3041 return 0;
3042 }
3043
3044 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
3045 i915_cache_sharing_get, i915_cache_sharing_set,
3046 "%llu\n");
3047
3048 static int i915_forcewake_open(struct inode *inode, struct file *file)
3049 {
3050 struct drm_device *dev = inode->i_private;
3051 struct drm_i915_private *dev_priv = dev->dev_private;
3052
3053 if (INTEL_INFO(dev)->gen < 6)
3054 return 0;
3055
3056 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3057
3058 return 0;
3059 }
3060
3061 static int i915_forcewake_release(struct inode *inode, struct file *file)
3062 {
3063 struct drm_device *dev = inode->i_private;
3064 struct drm_i915_private *dev_priv = dev->dev_private;
3065
3066 if (INTEL_INFO(dev)->gen < 6)
3067 return 0;
3068
3069 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3070
3071 return 0;
3072 }
3073
3074 static const struct file_operations i915_forcewake_fops = {
3075 .owner = THIS_MODULE,
3076 .open = i915_forcewake_open,
3077 .release = i915_forcewake_release,
3078 };
3079
3080 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
3081 {
3082 struct drm_device *dev = minor->dev;
3083 struct dentry *ent;
3084
3085 ent = debugfs_create_file("i915_forcewake_user",
3086 S_IRUSR,
3087 root, dev,
3088 &i915_forcewake_fops);
3089 if (IS_ERR(ent))
3090 return PTR_ERR(ent);
3091
3092 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
3093 }
3094
3095 static int i915_debugfs_create(struct dentry *root,
3096 struct drm_minor *minor,
3097 const char *name,
3098 const struct file_operations *fops)
3099 {
3100 struct drm_device *dev = minor->dev;
3101 struct dentry *ent;
3102
3103 ent = debugfs_create_file(name,
3104 S_IRUGO | S_IWUSR,
3105 root, dev,
3106 fops);
3107 if (IS_ERR(ent))
3108 return PTR_ERR(ent);
3109
3110 return drm_add_fake_info_node(minor, ent, fops);
3111 }
3112
3113 static const struct drm_info_list i915_debugfs_list[] = {
3114 {"i915_capabilities", i915_capabilities, 0},
3115 {"i915_gem_objects", i915_gem_object_info, 0},
3116 {"i915_gem_gtt", i915_gem_gtt_info, 0},
3117 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
3118 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
3119 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
3120 {"i915_gem_stolen", i915_gem_stolen_list_info },
3121 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
3122 {"i915_gem_request", i915_gem_request_info, 0},
3123 {"i915_gem_seqno", i915_gem_seqno_info, 0},
3124 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
3125 {"i915_gem_interrupt", i915_interrupt_info, 0},
3126 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
3127 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
3128 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
3129 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
3130 {"i915_rstdby_delays", i915_rstdby_delays, 0},
3131 {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
3132 {"i915_delayfreq_table", i915_delayfreq_table, 0},
3133 {"i915_inttoext_table", i915_inttoext_table, 0},
3134 {"i915_drpc_info", i915_drpc_info, 0},
3135 {"i915_emon_status", i915_emon_status, 0},
3136 {"i915_ring_freq_table", i915_ring_freq_table, 0},
3137 {"i915_gfxec", i915_gfxec, 0},
3138 {"i915_fbc_status", i915_fbc_status, 0},
3139 {"i915_ips_status", i915_ips_status, 0},
3140 {"i915_sr_status", i915_sr_status, 0},
3141 {"i915_opregion", i915_opregion, 0},
3142 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
3143 {"i915_context_status", i915_context_status, 0},
3144 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
3145 {"i915_swizzle_info", i915_swizzle_info, 0},
3146 {"i915_ppgtt_info", i915_ppgtt_info, 0},
3147 {"i915_dpio", i915_dpio_info, 0},
3148 {"i915_llc", i915_llc, 0},
3149 {"i915_edp_psr_status", i915_edp_psr_status, 0},
3150 {"i915_energy_uJ", i915_energy_uJ, 0},
3151 {"i915_pc8_status", i915_pc8_status, 0},
3152 {"i915_power_domain_info", i915_power_domain_info, 0},
3153 };
3154 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
3155
3156 static const struct i915_debugfs_files {
3157 const char *name;
3158 const struct file_operations *fops;
3159 } i915_debugfs_files[] = {
3160 {"i915_wedged", &i915_wedged_fops},
3161 {"i915_max_freq", &i915_max_freq_fops},
3162 {"i915_min_freq", &i915_min_freq_fops},
3163 {"i915_cache_sharing", &i915_cache_sharing_fops},
3164 {"i915_ring_stop", &i915_ring_stop_fops},
3165 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
3166 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
3167 {"i915_gem_drop_caches", &i915_drop_caches_fops},
3168 {"i915_error_state", &i915_error_state_fops},
3169 {"i915_next_seqno", &i915_next_seqno_fops},
3170 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
3171 };
3172
3173 void intel_display_crc_init(struct drm_device *dev)
3174 {
3175 struct drm_i915_private *dev_priv = dev->dev_private;
3176 enum pipe pipe;
3177
3178 for_each_pipe(pipe) {
3179 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3180
3181 pipe_crc->opened = false;
3182 spin_lock_init(&pipe_crc->lock);
3183 init_waitqueue_head(&pipe_crc->wq);
3184 }
3185 }
3186
3187 int i915_debugfs_init(struct drm_minor *minor)
3188 {
3189 int ret, i;
3190
3191 ret = i915_forcewake_create(minor->debugfs_root, minor);
3192 if (ret)
3193 return ret;
3194
3195 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
3196 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
3197 if (ret)
3198 return ret;
3199 }
3200
3201 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3202 ret = i915_debugfs_create(minor->debugfs_root, minor,
3203 i915_debugfs_files[i].name,
3204 i915_debugfs_files[i].fops);
3205 if (ret)
3206 return ret;
3207 }
3208
3209 return drm_debugfs_create_files(i915_debugfs_list,
3210 I915_DEBUGFS_ENTRIES,
3211 minor->debugfs_root, minor);
3212 }
3213
3214 void i915_debugfs_cleanup(struct drm_minor *minor)
3215 {
3216 int i;
3217
3218 drm_debugfs_remove_files(i915_debugfs_list,
3219 I915_DEBUGFS_ENTRIES, minor);
3220
3221 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
3222 1, minor);
3223
3224 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
3225 struct drm_info_list *info_list =
3226 (struct drm_info_list *)&i915_pipe_crc_data[i];
3227
3228 drm_debugfs_remove_files(info_list, 1, minor);
3229 }
3230
3231 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3232 struct drm_info_list *info_list =
3233 (struct drm_info_list *) i915_debugfs_files[i].fops;
3234
3235 drm_debugfs_remove_files(info_list, 1, minor);
3236 }
3237 }
3238
3239 #endif /* CONFIG_DEBUG_FS */
Linux kernel - Deliverables
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