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drm/i915/bdw: Check for slice, subslice and EU count for BDW
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
37 #include <drm/drmP.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
41 #include "i915_drv.h"
42
43 enum {
44 ACTIVE_LIST,
45 INACTIVE_LIST,
46 PINNED_LIST,
47 };
48
49 /* As the drm_debugfs_init() routines are called before dev->dev_private is
50 * allocated we need to hook into the minor for release. */
51 static int
52 drm_add_fake_info_node(struct drm_minor *minor,
53 struct dentry *ent,
54 const void *key)
55 {
56 struct drm_info_node *node;
57
58 node = kmalloc(sizeof(*node), GFP_KERNEL);
59 if (node == NULL) {
60 debugfs_remove(ent);
61 return -ENOMEM;
62 }
63
64 node->minor = minor;
65 node->dent = ent;
66 node->info_ent = (void *) key;
67
68 mutex_lock(&minor->debugfs_lock);
69 list_add(&node->list, &minor->debugfs_list);
70 mutex_unlock(&minor->debugfs_lock);
71
72 return 0;
73 }
74
75 static int i915_capabilities(struct seq_file *m, void *data)
76 {
77 struct drm_info_node *node = m->private;
78 struct drm_device *dev = node->minor->dev;
79 const struct intel_device_info *info = INTEL_INFO(dev);
80
81 seq_printf(m, "gen: %d\n", info->gen);
82 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
83 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
84 #define SEP_SEMICOLON ;
85 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
86 #undef PRINT_FLAG
87 #undef SEP_SEMICOLON
88
89 return 0;
90 }
91
92 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
93 {
94 if (obj->pin_display)
95 return "p";
96 else
97 return " ";
98 }
99
100 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
101 {
102 switch (obj->tiling_mode) {
103 default:
104 case I915_TILING_NONE: return " ";
105 case I915_TILING_X: return "X";
106 case I915_TILING_Y: return "Y";
107 }
108 }
109
110 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
111 {
112 return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
113 }
114
115 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
116 {
117 u64 size = 0;
118 struct i915_vma *vma;
119
120 list_for_each_entry(vma, &obj->vma_list, vma_link) {
121 if (i915_is_ggtt(vma->vm) &&
122 drm_mm_node_allocated(&vma->node))
123 size += vma->node.size;
124 }
125
126 return size;
127 }
128
129 static void
130 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
131 {
132 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
133 struct intel_engine_cs *ring;
134 struct i915_vma *vma;
135 int pin_count = 0;
136 int i;
137
138 seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ",
139 &obj->base,
140 obj->active ? "*" : " ",
141 get_pin_flag(obj),
142 get_tiling_flag(obj),
143 get_global_flag(obj),
144 obj->base.size / 1024,
145 obj->base.read_domains,
146 obj->base.write_domain);
147 for_each_ring(ring, dev_priv, i)
148 seq_printf(m, "%x ",
149 i915_gem_request_get_seqno(obj->last_read_req[i]));
150 seq_printf(m, "] %x %x%s%s%s",
151 i915_gem_request_get_seqno(obj->last_write_req),
152 i915_gem_request_get_seqno(obj->last_fenced_req),
153 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
154 obj->dirty ? " dirty" : "",
155 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
156 if (obj->base.name)
157 seq_printf(m, " (name: %d)", obj->base.name);
158 list_for_each_entry(vma, &obj->vma_list, vma_link) {
159 if (vma->pin_count > 0)
160 pin_count++;
161 }
162 seq_printf(m, " (pinned x %d)", pin_count);
163 if (obj->pin_display)
164 seq_printf(m, " (display)");
165 if (obj->fence_reg != I915_FENCE_REG_NONE)
166 seq_printf(m, " (fence: %d)", obj->fence_reg);
167 list_for_each_entry(vma, &obj->vma_list, vma_link) {
168 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
169 i915_is_ggtt(vma->vm) ? "g" : "pp",
170 vma->node.start, vma->node.size);
171 if (i915_is_ggtt(vma->vm))
172 seq_printf(m, ", type: %u)", vma->ggtt_view.type);
173 else
174 seq_puts(m, ")");
175 }
176 if (obj->stolen)
177 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
178 if (obj->pin_display || obj->fault_mappable) {
179 char s[3], *t = s;
180 if (obj->pin_display)
181 *t++ = 'p';
182 if (obj->fault_mappable)
183 *t++ = 'f';
184 *t = '\0';
185 seq_printf(m, " (%s mappable)", s);
186 }
187 if (obj->last_write_req != NULL)
188 seq_printf(m, " (%s)",
189 i915_gem_request_get_ring(obj->last_write_req)->name);
190 if (obj->frontbuffer_bits)
191 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
192 }
193
194 static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
195 {
196 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
197 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
198 seq_putc(m, ' ');
199 }
200
201 static int i915_gem_object_list_info(struct seq_file *m, void *data)
202 {
203 struct drm_info_node *node = m->private;
204 uintptr_t list = (uintptr_t) node->info_ent->data;
205 struct list_head *head;
206 struct drm_device *dev = node->minor->dev;
207 struct drm_i915_private *dev_priv = dev->dev_private;
208 struct i915_address_space *vm = &dev_priv->gtt.base;
209 struct i915_vma *vma;
210 u64 total_obj_size, total_gtt_size;
211 int count, ret;
212
213 ret = mutex_lock_interruptible(&dev->struct_mutex);
214 if (ret)
215 return ret;
216
217 /* FIXME: the user of this interface might want more than just GGTT */
218 switch (list) {
219 case ACTIVE_LIST:
220 seq_puts(m, "Active:\n");
221 head = &vm->active_list;
222 break;
223 case INACTIVE_LIST:
224 seq_puts(m, "Inactive:\n");
225 head = &vm->inactive_list;
226 break;
227 default:
228 mutex_unlock(&dev->struct_mutex);
229 return -EINVAL;
230 }
231
232 total_obj_size = total_gtt_size = count = 0;
233 list_for_each_entry(vma, head, mm_list) {
234 seq_printf(m, " ");
235 describe_obj(m, vma->obj);
236 seq_printf(m, "\n");
237 total_obj_size += vma->obj->base.size;
238 total_gtt_size += vma->node.size;
239 count++;
240 }
241 mutex_unlock(&dev->struct_mutex);
242
243 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
244 count, total_obj_size, total_gtt_size);
245 return 0;
246 }
247
248 static int obj_rank_by_stolen(void *priv,
249 struct list_head *A, struct list_head *B)
250 {
251 struct drm_i915_gem_object *a =
252 container_of(A, struct drm_i915_gem_object, obj_exec_link);
253 struct drm_i915_gem_object *b =
254 container_of(B, struct drm_i915_gem_object, obj_exec_link);
255
256 if (a->stolen->start < b->stolen->start)
257 return -1;
258 if (a->stolen->start > b->stolen->start)
259 return 1;
260 return 0;
261 }
262
263 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
264 {
265 struct drm_info_node *node = m->private;
266 struct drm_device *dev = node->minor->dev;
267 struct drm_i915_private *dev_priv = dev->dev_private;
268 struct drm_i915_gem_object *obj;
269 u64 total_obj_size, total_gtt_size;
270 LIST_HEAD(stolen);
271 int count, ret;
272
273 ret = mutex_lock_interruptible(&dev->struct_mutex);
274 if (ret)
275 return ret;
276
277 total_obj_size = total_gtt_size = count = 0;
278 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
279 if (obj->stolen == NULL)
280 continue;
281
282 list_add(&obj->obj_exec_link, &stolen);
283
284 total_obj_size += obj->base.size;
285 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
286 count++;
287 }
288 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
289 if (obj->stolen == NULL)
290 continue;
291
292 list_add(&obj->obj_exec_link, &stolen);
293
294 total_obj_size += obj->base.size;
295 count++;
296 }
297 list_sort(NULL, &stolen, obj_rank_by_stolen);
298 seq_puts(m, "Stolen:\n");
299 while (!list_empty(&stolen)) {
300 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
301 seq_puts(m, " ");
302 describe_obj(m, obj);
303 seq_putc(m, '\n');
304 list_del_init(&obj->obj_exec_link);
305 }
306 mutex_unlock(&dev->struct_mutex);
307
308 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
309 count, total_obj_size, total_gtt_size);
310 return 0;
311 }
312
313 #define count_objects(list, member) do { \
314 list_for_each_entry(obj, list, member) { \
315 size += i915_gem_obj_total_ggtt_size(obj); \
316 ++count; \
317 if (obj->map_and_fenceable) { \
318 mappable_size += i915_gem_obj_ggtt_size(obj); \
319 ++mappable_count; \
320 } \
321 } \
322 } while (0)
323
324 struct file_stats {
325 struct drm_i915_file_private *file_priv;
326 unsigned long count;
327 u64 total, unbound;
328 u64 global, shared;
329 u64 active, inactive;
330 };
331
332 static int per_file_stats(int id, void *ptr, void *data)
333 {
334 struct drm_i915_gem_object *obj = ptr;
335 struct file_stats *stats = data;
336 struct i915_vma *vma;
337
338 stats->count++;
339 stats->total += obj->base.size;
340
341 if (obj->base.name || obj->base.dma_buf)
342 stats->shared += obj->base.size;
343
344 if (USES_FULL_PPGTT(obj->base.dev)) {
345 list_for_each_entry(vma, &obj->vma_list, vma_link) {
346 struct i915_hw_ppgtt *ppgtt;
347
348 if (!drm_mm_node_allocated(&vma->node))
349 continue;
350
351 if (i915_is_ggtt(vma->vm)) {
352 stats->global += obj->base.size;
353 continue;
354 }
355
356 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
357 if (ppgtt->file_priv != stats->file_priv)
358 continue;
359
360 if (obj->active) /* XXX per-vma statistic */
361 stats->active += obj->base.size;
362 else
363 stats->inactive += obj->base.size;
364
365 return 0;
366 }
367 } else {
368 if (i915_gem_obj_ggtt_bound(obj)) {
369 stats->global += obj->base.size;
370 if (obj->active)
371 stats->active += obj->base.size;
372 else
373 stats->inactive += obj->base.size;
374 return 0;
375 }
376 }
377
378 if (!list_empty(&obj->global_list))
379 stats->unbound += obj->base.size;
380
381 return 0;
382 }
383
384 #define print_file_stats(m, name, stats) do { \
385 if (stats.count) \
386 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
387 name, \
388 stats.count, \
389 stats.total, \
390 stats.active, \
391 stats.inactive, \
392 stats.global, \
393 stats.shared, \
394 stats.unbound); \
395 } while (0)
396
397 static void print_batch_pool_stats(struct seq_file *m,
398 struct drm_i915_private *dev_priv)
399 {
400 struct drm_i915_gem_object *obj;
401 struct file_stats stats;
402 struct intel_engine_cs *ring;
403 int i, j;
404
405 memset(&stats, 0, sizeof(stats));
406
407 for_each_ring(ring, dev_priv, i) {
408 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
409 list_for_each_entry(obj,
410 &ring->batch_pool.cache_list[j],
411 batch_pool_link)
412 per_file_stats(0, obj, &stats);
413 }
414 }
415
416 print_file_stats(m, "[k]batch pool", stats);
417 }
418
419 #define count_vmas(list, member) do { \
420 list_for_each_entry(vma, list, member) { \
421 size += i915_gem_obj_total_ggtt_size(vma->obj); \
422 ++count; \
423 if (vma->obj->map_and_fenceable) { \
424 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
425 ++mappable_count; \
426 } \
427 } \
428 } while (0)
429
430 static int i915_gem_object_info(struct seq_file *m, void* data)
431 {
432 struct drm_info_node *node = m->private;
433 struct drm_device *dev = node->minor->dev;
434 struct drm_i915_private *dev_priv = dev->dev_private;
435 u32 count, mappable_count, purgeable_count;
436 u64 size, mappable_size, purgeable_size;
437 struct drm_i915_gem_object *obj;
438 struct i915_address_space *vm = &dev_priv->gtt.base;
439 struct drm_file *file;
440 struct i915_vma *vma;
441 int ret;
442
443 ret = mutex_lock_interruptible(&dev->struct_mutex);
444 if (ret)
445 return ret;
446
447 seq_printf(m, "%u objects, %zu bytes\n",
448 dev_priv->mm.object_count,
449 dev_priv->mm.object_memory);
450
451 size = count = mappable_size = mappable_count = 0;
452 count_objects(&dev_priv->mm.bound_list, global_list);
453 seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
454 count, mappable_count, size, mappable_size);
455
456 size = count = mappable_size = mappable_count = 0;
457 count_vmas(&vm->active_list, mm_list);
458 seq_printf(m, " %u [%u] active objects, %llu [%llu] bytes\n",
459 count, mappable_count, size, mappable_size);
460
461 size = count = mappable_size = mappable_count = 0;
462 count_vmas(&vm->inactive_list, mm_list);
463 seq_printf(m, " %u [%u] inactive objects, %llu [%llu] bytes\n",
464 count, mappable_count, size, mappable_size);
465
466 size = count = purgeable_size = purgeable_count = 0;
467 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
468 size += obj->base.size, ++count;
469 if (obj->madv == I915_MADV_DONTNEED)
470 purgeable_size += obj->base.size, ++purgeable_count;
471 }
472 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
473
474 size = count = mappable_size = mappable_count = 0;
475 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
476 if (obj->fault_mappable) {
477 size += i915_gem_obj_ggtt_size(obj);
478 ++count;
479 }
480 if (obj->pin_display) {
481 mappable_size += i915_gem_obj_ggtt_size(obj);
482 ++mappable_count;
483 }
484 if (obj->madv == I915_MADV_DONTNEED) {
485 purgeable_size += obj->base.size;
486 ++purgeable_count;
487 }
488 }
489 seq_printf(m, "%u purgeable objects, %llu bytes\n",
490 purgeable_count, purgeable_size);
491 seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
492 mappable_count, mappable_size);
493 seq_printf(m, "%u fault mappable objects, %llu bytes\n",
494 count, size);
495
496 seq_printf(m, "%llu [%llu] gtt total\n",
497 dev_priv->gtt.base.total,
498 (u64)dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
499
500 seq_putc(m, '\n');
501 print_batch_pool_stats(m, dev_priv);
502 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
503 struct file_stats stats;
504 struct task_struct *task;
505
506 memset(&stats, 0, sizeof(stats));
507 stats.file_priv = file->driver_priv;
508 spin_lock(&file->table_lock);
509 idr_for_each(&file->object_idr, per_file_stats, &stats);
510 spin_unlock(&file->table_lock);
511 /*
512 * Although we have a valid reference on file->pid, that does
513 * not guarantee that the task_struct who called get_pid() is
514 * still alive (e.g. get_pid(current) => fork() => exit()).
515 * Therefore, we need to protect this ->comm access using RCU.
516 */
517 rcu_read_lock();
518 task = pid_task(file->pid, PIDTYPE_PID);
519 print_file_stats(m, task ? task->comm : "<unknown>", stats);
520 rcu_read_unlock();
521 }
522
523 mutex_unlock(&dev->struct_mutex);
524
525 return 0;
526 }
527
528 static int i915_gem_gtt_info(struct seq_file *m, void *data)
529 {
530 struct drm_info_node *node = m->private;
531 struct drm_device *dev = node->minor->dev;
532 uintptr_t list = (uintptr_t) node->info_ent->data;
533 struct drm_i915_private *dev_priv = dev->dev_private;
534 struct drm_i915_gem_object *obj;
535 u64 total_obj_size, total_gtt_size;
536 int count, ret;
537
538 ret = mutex_lock_interruptible(&dev->struct_mutex);
539 if (ret)
540 return ret;
541
542 total_obj_size = total_gtt_size = count = 0;
543 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
544 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
545 continue;
546
547 seq_puts(m, " ");
548 describe_obj(m, obj);
549 seq_putc(m, '\n');
550 total_obj_size += obj->base.size;
551 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
552 count++;
553 }
554
555 mutex_unlock(&dev->struct_mutex);
556
557 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
558 count, total_obj_size, total_gtt_size);
559
560 return 0;
561 }
562
563 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
564 {
565 struct drm_info_node *node = m->private;
566 struct drm_device *dev = node->minor->dev;
567 struct drm_i915_private *dev_priv = dev->dev_private;
568 struct intel_crtc *crtc;
569 int ret;
570
571 ret = mutex_lock_interruptible(&dev->struct_mutex);
572 if (ret)
573 return ret;
574
575 for_each_intel_crtc(dev, crtc) {
576 const char pipe = pipe_name(crtc->pipe);
577 const char plane = plane_name(crtc->plane);
578 struct intel_unpin_work *work;
579
580 spin_lock_irq(&dev->event_lock);
581 work = crtc->unpin_work;
582 if (work == NULL) {
583 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
584 pipe, plane);
585 } else {
586 u32 addr;
587
588 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
589 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
590 pipe, plane);
591 } else {
592 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
593 pipe, plane);
594 }
595 if (work->flip_queued_req) {
596 struct intel_engine_cs *ring =
597 i915_gem_request_get_ring(work->flip_queued_req);
598
599 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
600 ring->name,
601 i915_gem_request_get_seqno(work->flip_queued_req),
602 dev_priv->next_seqno,
603 ring->get_seqno(ring, true),
604 i915_gem_request_completed(work->flip_queued_req, true));
605 } else
606 seq_printf(m, "Flip not associated with any ring\n");
607 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
608 work->flip_queued_vblank,
609 work->flip_ready_vblank,
610 drm_crtc_vblank_count(&crtc->base));
611 if (work->enable_stall_check)
612 seq_puts(m, "Stall check enabled, ");
613 else
614 seq_puts(m, "Stall check waiting for page flip ioctl, ");
615 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
616
617 if (INTEL_INFO(dev)->gen >= 4)
618 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
619 else
620 addr = I915_READ(DSPADDR(crtc->plane));
621 seq_printf(m, "Current scanout address 0x%08x\n", addr);
622
623 if (work->pending_flip_obj) {
624 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
625 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
626 }
627 }
628 spin_unlock_irq(&dev->event_lock);
629 }
630
631 mutex_unlock(&dev->struct_mutex);
632
633 return 0;
634 }
635
636 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
637 {
638 struct drm_info_node *node = m->private;
639 struct drm_device *dev = node->minor->dev;
640 struct drm_i915_private *dev_priv = dev->dev_private;
641 struct drm_i915_gem_object *obj;
642 struct intel_engine_cs *ring;
643 int total = 0;
644 int ret, i, j;
645
646 ret = mutex_lock_interruptible(&dev->struct_mutex);
647 if (ret)
648 return ret;
649
650 for_each_ring(ring, dev_priv, i) {
651 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
652 int count;
653
654 count = 0;
655 list_for_each_entry(obj,
656 &ring->batch_pool.cache_list[j],
657 batch_pool_link)
658 count++;
659 seq_printf(m, "%s cache[%d]: %d objects\n",
660 ring->name, j, count);
661
662 list_for_each_entry(obj,
663 &ring->batch_pool.cache_list[j],
664 batch_pool_link) {
665 seq_puts(m, " ");
666 describe_obj(m, obj);
667 seq_putc(m, '\n');
668 }
669
670 total += count;
671 }
672 }
673
674 seq_printf(m, "total: %d\n", total);
675
676 mutex_unlock(&dev->struct_mutex);
677
678 return 0;
679 }
680
681 static int i915_gem_request_info(struct seq_file *m, void *data)
682 {
683 struct drm_info_node *node = m->private;
684 struct drm_device *dev = node->minor->dev;
685 struct drm_i915_private *dev_priv = dev->dev_private;
686 struct intel_engine_cs *ring;
687 struct drm_i915_gem_request *req;
688 int ret, any, i;
689
690 ret = mutex_lock_interruptible(&dev->struct_mutex);
691 if (ret)
692 return ret;
693
694 any = 0;
695 for_each_ring(ring, dev_priv, i) {
696 int count;
697
698 count = 0;
699 list_for_each_entry(req, &ring->request_list, list)
700 count++;
701 if (count == 0)
702 continue;
703
704 seq_printf(m, "%s requests: %d\n", ring->name, count);
705 list_for_each_entry(req, &ring->request_list, list) {
706 struct task_struct *task;
707
708 rcu_read_lock();
709 task = NULL;
710 if (req->pid)
711 task = pid_task(req->pid, PIDTYPE_PID);
712 seq_printf(m, " %x @ %d: %s [%d]\n",
713 req->seqno,
714 (int) (jiffies - req->emitted_jiffies),
715 task ? task->comm : "<unknown>",
716 task ? task->pid : -1);
717 rcu_read_unlock();
718 }
719
720 any++;
721 }
722 mutex_unlock(&dev->struct_mutex);
723
724 if (any == 0)
725 seq_puts(m, "No requests\n");
726
727 return 0;
728 }
729
730 static void i915_ring_seqno_info(struct seq_file *m,
731 struct intel_engine_cs *ring)
732 {
733 if (ring->get_seqno) {
734 seq_printf(m, "Current sequence (%s): %x\n",
735 ring->name, ring->get_seqno(ring, false));
736 }
737 }
738
739 static int i915_gem_seqno_info(struct seq_file *m, void *data)
740 {
741 struct drm_info_node *node = m->private;
742 struct drm_device *dev = node->minor->dev;
743 struct drm_i915_private *dev_priv = dev->dev_private;
744 struct intel_engine_cs *ring;
745 int ret, i;
746
747 ret = mutex_lock_interruptible(&dev->struct_mutex);
748 if (ret)
749 return ret;
750 intel_runtime_pm_get(dev_priv);
751
752 for_each_ring(ring, dev_priv, i)
753 i915_ring_seqno_info(m, ring);
754
755 intel_runtime_pm_put(dev_priv);
756 mutex_unlock(&dev->struct_mutex);
757
758 return 0;
759 }
760
761
762 static int i915_interrupt_info(struct seq_file *m, void *data)
763 {
764 struct drm_info_node *node = m->private;
765 struct drm_device *dev = node->minor->dev;
766 struct drm_i915_private *dev_priv = dev->dev_private;
767 struct intel_engine_cs *ring;
768 int ret, i, pipe;
769
770 ret = mutex_lock_interruptible(&dev->struct_mutex);
771 if (ret)
772 return ret;
773 intel_runtime_pm_get(dev_priv);
774
775 if (IS_CHERRYVIEW(dev)) {
776 seq_printf(m, "Master Interrupt Control:\t%08x\n",
777 I915_READ(GEN8_MASTER_IRQ));
778
779 seq_printf(m, "Display IER:\t%08x\n",
780 I915_READ(VLV_IER));
781 seq_printf(m, "Display IIR:\t%08x\n",
782 I915_READ(VLV_IIR));
783 seq_printf(m, "Display IIR_RW:\t%08x\n",
784 I915_READ(VLV_IIR_RW));
785 seq_printf(m, "Display IMR:\t%08x\n",
786 I915_READ(VLV_IMR));
787 for_each_pipe(dev_priv, pipe)
788 seq_printf(m, "Pipe %c stat:\t%08x\n",
789 pipe_name(pipe),
790 I915_READ(PIPESTAT(pipe)));
791
792 seq_printf(m, "Port hotplug:\t%08x\n",
793 I915_READ(PORT_HOTPLUG_EN));
794 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
795 I915_READ(VLV_DPFLIPSTAT));
796 seq_printf(m, "DPINVGTT:\t%08x\n",
797 I915_READ(DPINVGTT));
798
799 for (i = 0; i < 4; i++) {
800 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
801 i, I915_READ(GEN8_GT_IMR(i)));
802 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
803 i, I915_READ(GEN8_GT_IIR(i)));
804 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
805 i, I915_READ(GEN8_GT_IER(i)));
806 }
807
808 seq_printf(m, "PCU interrupt mask:\t%08x\n",
809 I915_READ(GEN8_PCU_IMR));
810 seq_printf(m, "PCU interrupt identity:\t%08x\n",
811 I915_READ(GEN8_PCU_IIR));
812 seq_printf(m, "PCU interrupt enable:\t%08x\n",
813 I915_READ(GEN8_PCU_IER));
814 } else if (INTEL_INFO(dev)->gen >= 8) {
815 seq_printf(m, "Master Interrupt Control:\t%08x\n",
816 I915_READ(GEN8_MASTER_IRQ));
817
818 for (i = 0; i < 4; i++) {
819 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
820 i, I915_READ(GEN8_GT_IMR(i)));
821 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
822 i, I915_READ(GEN8_GT_IIR(i)));
823 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
824 i, I915_READ(GEN8_GT_IER(i)));
825 }
826
827 for_each_pipe(dev_priv, pipe) {
828 if (!intel_display_power_is_enabled(dev_priv,
829 POWER_DOMAIN_PIPE(pipe))) {
830 seq_printf(m, "Pipe %c power disabled\n",
831 pipe_name(pipe));
832 continue;
833 }
834 seq_printf(m, "Pipe %c IMR:\t%08x\n",
835 pipe_name(pipe),
836 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
837 seq_printf(m, "Pipe %c IIR:\t%08x\n",
838 pipe_name(pipe),
839 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
840 seq_printf(m, "Pipe %c IER:\t%08x\n",
841 pipe_name(pipe),
842 I915_READ(GEN8_DE_PIPE_IER(pipe)));
843 }
844
845 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
846 I915_READ(GEN8_DE_PORT_IMR));
847 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
848 I915_READ(GEN8_DE_PORT_IIR));
849 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
850 I915_READ(GEN8_DE_PORT_IER));
851
852 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
853 I915_READ(GEN8_DE_MISC_IMR));
854 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
855 I915_READ(GEN8_DE_MISC_IIR));
856 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
857 I915_READ(GEN8_DE_MISC_IER));
858
859 seq_printf(m, "PCU interrupt mask:\t%08x\n",
860 I915_READ(GEN8_PCU_IMR));
861 seq_printf(m, "PCU interrupt identity:\t%08x\n",
862 I915_READ(GEN8_PCU_IIR));
863 seq_printf(m, "PCU interrupt enable:\t%08x\n",
864 I915_READ(GEN8_PCU_IER));
865 } else if (IS_VALLEYVIEW(dev)) {
866 seq_printf(m, "Display IER:\t%08x\n",
867 I915_READ(VLV_IER));
868 seq_printf(m, "Display IIR:\t%08x\n",
869 I915_READ(VLV_IIR));
870 seq_printf(m, "Display IIR_RW:\t%08x\n",
871 I915_READ(VLV_IIR_RW));
872 seq_printf(m, "Display IMR:\t%08x\n",
873 I915_READ(VLV_IMR));
874 for_each_pipe(dev_priv, pipe)
875 seq_printf(m, "Pipe %c stat:\t%08x\n",
876 pipe_name(pipe),
877 I915_READ(PIPESTAT(pipe)));
878
879 seq_printf(m, "Master IER:\t%08x\n",
880 I915_READ(VLV_MASTER_IER));
881
882 seq_printf(m, "Render IER:\t%08x\n",
883 I915_READ(GTIER));
884 seq_printf(m, "Render IIR:\t%08x\n",
885 I915_READ(GTIIR));
886 seq_printf(m, "Render IMR:\t%08x\n",
887 I915_READ(GTIMR));
888
889 seq_printf(m, "PM IER:\t\t%08x\n",
890 I915_READ(GEN6_PMIER));
891 seq_printf(m, "PM IIR:\t\t%08x\n",
892 I915_READ(GEN6_PMIIR));
893 seq_printf(m, "PM IMR:\t\t%08x\n",
894 I915_READ(GEN6_PMIMR));
895
896 seq_printf(m, "Port hotplug:\t%08x\n",
897 I915_READ(PORT_HOTPLUG_EN));
898 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
899 I915_READ(VLV_DPFLIPSTAT));
900 seq_printf(m, "DPINVGTT:\t%08x\n",
901 I915_READ(DPINVGTT));
902
903 } else if (!HAS_PCH_SPLIT(dev)) {
904 seq_printf(m, "Interrupt enable: %08x\n",
905 I915_READ(IER));
906 seq_printf(m, "Interrupt identity: %08x\n",
907 I915_READ(IIR));
908 seq_printf(m, "Interrupt mask: %08x\n",
909 I915_READ(IMR));
910 for_each_pipe(dev_priv, pipe)
911 seq_printf(m, "Pipe %c stat: %08x\n",
912 pipe_name(pipe),
913 I915_READ(PIPESTAT(pipe)));
914 } else {
915 seq_printf(m, "North Display Interrupt enable: %08x\n",
916 I915_READ(DEIER));
917 seq_printf(m, "North Display Interrupt identity: %08x\n",
918 I915_READ(DEIIR));
919 seq_printf(m, "North Display Interrupt mask: %08x\n",
920 I915_READ(DEIMR));
921 seq_printf(m, "South Display Interrupt enable: %08x\n",
922 I915_READ(SDEIER));
923 seq_printf(m, "South Display Interrupt identity: %08x\n",
924 I915_READ(SDEIIR));
925 seq_printf(m, "South Display Interrupt mask: %08x\n",
926 I915_READ(SDEIMR));
927 seq_printf(m, "Graphics Interrupt enable: %08x\n",
928 I915_READ(GTIER));
929 seq_printf(m, "Graphics Interrupt identity: %08x\n",
930 I915_READ(GTIIR));
931 seq_printf(m, "Graphics Interrupt mask: %08x\n",
932 I915_READ(GTIMR));
933 }
934 for_each_ring(ring, dev_priv, i) {
935 if (INTEL_INFO(dev)->gen >= 6) {
936 seq_printf(m,
937 "Graphics Interrupt mask (%s): %08x\n",
938 ring->name, I915_READ_IMR(ring));
939 }
940 i915_ring_seqno_info(m, ring);
941 }
942 intel_runtime_pm_put(dev_priv);
943 mutex_unlock(&dev->struct_mutex);
944
945 return 0;
946 }
947
948 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
949 {
950 struct drm_info_node *node = m->private;
951 struct drm_device *dev = node->minor->dev;
952 struct drm_i915_private *dev_priv = dev->dev_private;
953 int i, ret;
954
955 ret = mutex_lock_interruptible(&dev->struct_mutex);
956 if (ret)
957 return ret;
958
959 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
960 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
961 for (i = 0; i < dev_priv->num_fence_regs; i++) {
962 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
963
964 seq_printf(m, "Fence %d, pin count = %d, object = ",
965 i, dev_priv->fence_regs[i].pin_count);
966 if (obj == NULL)
967 seq_puts(m, "unused");
968 else
969 describe_obj(m, obj);
970 seq_putc(m, '\n');
971 }
972
973 mutex_unlock(&dev->struct_mutex);
974 return 0;
975 }
976
977 static int i915_hws_info(struct seq_file *m, void *data)
978 {
979 struct drm_info_node *node = m->private;
980 struct drm_device *dev = node->minor->dev;
981 struct drm_i915_private *dev_priv = dev->dev_private;
982 struct intel_engine_cs *ring;
983 const u32 *hws;
984 int i;
985
986 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
987 hws = ring->status_page.page_addr;
988 if (hws == NULL)
989 return 0;
990
991 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
992 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
993 i * 4,
994 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
995 }
996 return 0;
997 }
998
999 static ssize_t
1000 i915_error_state_write(struct file *filp,
1001 const char __user *ubuf,
1002 size_t cnt,
1003 loff_t *ppos)
1004 {
1005 struct i915_error_state_file_priv *error_priv = filp->private_data;
1006 struct drm_device *dev = error_priv->dev;
1007 int ret;
1008
1009 DRM_DEBUG_DRIVER("Resetting error state\n");
1010
1011 ret = mutex_lock_interruptible(&dev->struct_mutex);
1012 if (ret)
1013 return ret;
1014
1015 i915_destroy_error_state(dev);
1016 mutex_unlock(&dev->struct_mutex);
1017
1018 return cnt;
1019 }
1020
1021 static int i915_error_state_open(struct inode *inode, struct file *file)
1022 {
1023 struct drm_device *dev = inode->i_private;
1024 struct i915_error_state_file_priv *error_priv;
1025
1026 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1027 if (!error_priv)
1028 return -ENOMEM;
1029
1030 error_priv->dev = dev;
1031
1032 i915_error_state_get(dev, error_priv);
1033
1034 file->private_data = error_priv;
1035
1036 return 0;
1037 }
1038
1039 static int i915_error_state_release(struct inode *inode, struct file *file)
1040 {
1041 struct i915_error_state_file_priv *error_priv = file->private_data;
1042
1043 i915_error_state_put(error_priv);
1044 kfree(error_priv);
1045
1046 return 0;
1047 }
1048
1049 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1050 size_t count, loff_t *pos)
1051 {
1052 struct i915_error_state_file_priv *error_priv = file->private_data;
1053 struct drm_i915_error_state_buf error_str;
1054 loff_t tmp_pos = 0;
1055 ssize_t ret_count = 0;
1056 int ret;
1057
1058 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1059 if (ret)
1060 return ret;
1061
1062 ret = i915_error_state_to_str(&error_str, error_priv);
1063 if (ret)
1064 goto out;
1065
1066 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1067 error_str.buf,
1068 error_str.bytes);
1069
1070 if (ret_count < 0)
1071 ret = ret_count;
1072 else
1073 *pos = error_str.start + ret_count;
1074 out:
1075 i915_error_state_buf_release(&error_str);
1076 return ret ?: ret_count;
1077 }
1078
1079 static const struct file_operations i915_error_state_fops = {
1080 .owner = THIS_MODULE,
1081 .open = i915_error_state_open,
1082 .read = i915_error_state_read,
1083 .write = i915_error_state_write,
1084 .llseek = default_llseek,
1085 .release = i915_error_state_release,
1086 };
1087
1088 static int
1089 i915_next_seqno_get(void *data, u64 *val)
1090 {
1091 struct drm_device *dev = data;
1092 struct drm_i915_private *dev_priv = dev->dev_private;
1093 int ret;
1094
1095 ret = mutex_lock_interruptible(&dev->struct_mutex);
1096 if (ret)
1097 return ret;
1098
1099 *val = dev_priv->next_seqno;
1100 mutex_unlock(&dev->struct_mutex);
1101
1102 return 0;
1103 }
1104
1105 static int
1106 i915_next_seqno_set(void *data, u64 val)
1107 {
1108 struct drm_device *dev = data;
1109 int ret;
1110
1111 ret = mutex_lock_interruptible(&dev->struct_mutex);
1112 if (ret)
1113 return ret;
1114
1115 ret = i915_gem_set_seqno(dev, val);
1116 mutex_unlock(&dev->struct_mutex);
1117
1118 return ret;
1119 }
1120
1121 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1122 i915_next_seqno_get, i915_next_seqno_set,
1123 "0x%llx\n");
1124
1125 static int i915_frequency_info(struct seq_file *m, void *unused)
1126 {
1127 struct drm_info_node *node = m->private;
1128 struct drm_device *dev = node->minor->dev;
1129 struct drm_i915_private *dev_priv = dev->dev_private;
1130 int ret = 0;
1131
1132 intel_runtime_pm_get(dev_priv);
1133
1134 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1135
1136 if (IS_GEN5(dev)) {
1137 u16 rgvswctl = I915_READ16(MEMSWCTL);
1138 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1139
1140 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1141 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1142 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1143 MEMSTAT_VID_SHIFT);
1144 seq_printf(m, "Current P-state: %d\n",
1145 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1146 } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1147 IS_BROADWELL(dev) || IS_GEN9(dev)) {
1148 u32 rp_state_limits;
1149 u32 gt_perf_status;
1150 u32 rp_state_cap;
1151 u32 rpmodectl, rpinclimit, rpdeclimit;
1152 u32 rpstat, cagf, reqf;
1153 u32 rpupei, rpcurup, rpprevup;
1154 u32 rpdownei, rpcurdown, rpprevdown;
1155 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1156 int max_freq;
1157
1158 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1159 if (IS_BROXTON(dev)) {
1160 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1161 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1162 } else {
1163 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1164 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1165 }
1166
1167 /* RPSTAT1 is in the GT power well */
1168 ret = mutex_lock_interruptible(&dev->struct_mutex);
1169 if (ret)
1170 goto out;
1171
1172 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1173
1174 reqf = I915_READ(GEN6_RPNSWREQ);
1175 if (IS_GEN9(dev))
1176 reqf >>= 23;
1177 else {
1178 reqf &= ~GEN6_TURBO_DISABLE;
1179 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1180 reqf >>= 24;
1181 else
1182 reqf >>= 25;
1183 }
1184 reqf = intel_gpu_freq(dev_priv, reqf);
1185
1186 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1187 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1188 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1189
1190 rpstat = I915_READ(GEN6_RPSTAT1);
1191 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1192 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1193 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1194 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1195 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1196 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1197 if (IS_GEN9(dev))
1198 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1199 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1200 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1201 else
1202 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1203 cagf = intel_gpu_freq(dev_priv, cagf);
1204
1205 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1206 mutex_unlock(&dev->struct_mutex);
1207
1208 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1209 pm_ier = I915_READ(GEN6_PMIER);
1210 pm_imr = I915_READ(GEN6_PMIMR);
1211 pm_isr = I915_READ(GEN6_PMISR);
1212 pm_iir = I915_READ(GEN6_PMIIR);
1213 pm_mask = I915_READ(GEN6_PMINTRMSK);
1214 } else {
1215 pm_ier = I915_READ(GEN8_GT_IER(2));
1216 pm_imr = I915_READ(GEN8_GT_IMR(2));
1217 pm_isr = I915_READ(GEN8_GT_ISR(2));
1218 pm_iir = I915_READ(GEN8_GT_IIR(2));
1219 pm_mask = I915_READ(GEN6_PMINTRMSK);
1220 }
1221 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1222 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1223 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1224 seq_printf(m, "Render p-state ratio: %d\n",
1225 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
1226 seq_printf(m, "Render p-state VID: %d\n",
1227 gt_perf_status & 0xff);
1228 seq_printf(m, "Render p-state limit: %d\n",
1229 rp_state_limits & 0xff);
1230 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1231 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1232 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1233 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1234 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1235 seq_printf(m, "CAGF: %dMHz\n", cagf);
1236 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1237 GEN6_CURICONT_MASK);
1238 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1239 GEN6_CURBSYTAVG_MASK);
1240 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1241 GEN6_CURBSYTAVG_MASK);
1242 seq_printf(m, "Up threshold: %d%%\n",
1243 dev_priv->rps.up_threshold);
1244
1245 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1246 GEN6_CURIAVG_MASK);
1247 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1248 GEN6_CURBSYTAVG_MASK);
1249 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1250 GEN6_CURBSYTAVG_MASK);
1251 seq_printf(m, "Down threshold: %d%%\n",
1252 dev_priv->rps.down_threshold);
1253
1254 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1255 rp_state_cap >> 16) & 0xff;
1256 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
1257 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1258 intel_gpu_freq(dev_priv, max_freq));
1259
1260 max_freq = (rp_state_cap & 0xff00) >> 8;
1261 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
1262 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1263 intel_gpu_freq(dev_priv, max_freq));
1264
1265 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1266 rp_state_cap >> 0) & 0xff;
1267 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
1268 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1269 intel_gpu_freq(dev_priv, max_freq));
1270 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1271 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1272
1273 seq_printf(m, "Current freq: %d MHz\n",
1274 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1275 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1276 seq_printf(m, "Idle freq: %d MHz\n",
1277 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1278 seq_printf(m, "Min freq: %d MHz\n",
1279 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1280 seq_printf(m, "Max freq: %d MHz\n",
1281 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1282 seq_printf(m,
1283 "efficient (RPe) frequency: %d MHz\n",
1284 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1285 } else if (IS_VALLEYVIEW(dev)) {
1286 u32 freq_sts;
1287
1288 mutex_lock(&dev_priv->rps.hw_lock);
1289 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1290 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1291 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1292
1293 seq_printf(m, "actual GPU freq: %d MHz\n",
1294 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1295
1296 seq_printf(m, "current GPU freq: %d MHz\n",
1297 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1298
1299 seq_printf(m, "max GPU freq: %d MHz\n",
1300 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1301
1302 seq_printf(m, "min GPU freq: %d MHz\n",
1303 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1304
1305 seq_printf(m, "idle GPU freq: %d MHz\n",
1306 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1307
1308 seq_printf(m,
1309 "efficient (RPe) frequency: %d MHz\n",
1310 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1311 mutex_unlock(&dev_priv->rps.hw_lock);
1312 } else {
1313 seq_puts(m, "no P-state info available\n");
1314 }
1315
1316 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1317 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1318 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1319
1320 out:
1321 intel_runtime_pm_put(dev_priv);
1322 return ret;
1323 }
1324
1325 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1326 {
1327 struct drm_info_node *node = m->private;
1328 struct drm_device *dev = node->minor->dev;
1329 struct drm_i915_private *dev_priv = dev->dev_private;
1330 struct intel_engine_cs *ring;
1331 u64 acthd[I915_NUM_RINGS];
1332 u32 seqno[I915_NUM_RINGS];
1333 int i;
1334
1335 if (!i915.enable_hangcheck) {
1336 seq_printf(m, "Hangcheck disabled\n");
1337 return 0;
1338 }
1339
1340 intel_runtime_pm_get(dev_priv);
1341
1342 for_each_ring(ring, dev_priv, i) {
1343 seqno[i] = ring->get_seqno(ring, false);
1344 acthd[i] = intel_ring_get_active_head(ring);
1345 }
1346
1347 intel_runtime_pm_put(dev_priv);
1348
1349 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1350 seq_printf(m, "Hangcheck active, fires in %dms\n",
1351 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1352 jiffies));
1353 } else
1354 seq_printf(m, "Hangcheck inactive\n");
1355
1356 for_each_ring(ring, dev_priv, i) {
1357 seq_printf(m, "%s:\n", ring->name);
1358 seq_printf(m, "\tseqno = %x [current %x]\n",
1359 ring->hangcheck.seqno, seqno[i]);
1360 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1361 (long long)ring->hangcheck.acthd,
1362 (long long)acthd[i]);
1363 seq_printf(m, "\tmax ACTHD = 0x%08llx\n",
1364 (long long)ring->hangcheck.max_acthd);
1365 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score);
1366 seq_printf(m, "\taction = %d\n", ring->hangcheck.action);
1367 }
1368
1369 return 0;
1370 }
1371
1372 static int ironlake_drpc_info(struct seq_file *m)
1373 {
1374 struct drm_info_node *node = m->private;
1375 struct drm_device *dev = node->minor->dev;
1376 struct drm_i915_private *dev_priv = dev->dev_private;
1377 u32 rgvmodectl, rstdbyctl;
1378 u16 crstandvid;
1379 int ret;
1380
1381 ret = mutex_lock_interruptible(&dev->struct_mutex);
1382 if (ret)
1383 return ret;
1384 intel_runtime_pm_get(dev_priv);
1385
1386 rgvmodectl = I915_READ(MEMMODECTL);
1387 rstdbyctl = I915_READ(RSTDBYCTL);
1388 crstandvid = I915_READ16(CRSTANDVID);
1389
1390 intel_runtime_pm_put(dev_priv);
1391 mutex_unlock(&dev->struct_mutex);
1392
1393 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1394 seq_printf(m, "Boost freq: %d\n",
1395 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1396 MEMMODE_BOOST_FREQ_SHIFT);
1397 seq_printf(m, "HW control enabled: %s\n",
1398 yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1399 seq_printf(m, "SW control enabled: %s\n",
1400 yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1401 seq_printf(m, "Gated voltage change: %s\n",
1402 yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1403 seq_printf(m, "Starting frequency: P%d\n",
1404 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1405 seq_printf(m, "Max P-state: P%d\n",
1406 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1407 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1408 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1409 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1410 seq_printf(m, "Render standby enabled: %s\n",
1411 yesno(!(rstdbyctl & RCX_SW_EXIT)));
1412 seq_puts(m, "Current RS state: ");
1413 switch (rstdbyctl & RSX_STATUS_MASK) {
1414 case RSX_STATUS_ON:
1415 seq_puts(m, "on\n");
1416 break;
1417 case RSX_STATUS_RC1:
1418 seq_puts(m, "RC1\n");
1419 break;
1420 case RSX_STATUS_RC1E:
1421 seq_puts(m, "RC1E\n");
1422 break;
1423 case RSX_STATUS_RS1:
1424 seq_puts(m, "RS1\n");
1425 break;
1426 case RSX_STATUS_RS2:
1427 seq_puts(m, "RS2 (RC6)\n");
1428 break;
1429 case RSX_STATUS_RS3:
1430 seq_puts(m, "RC3 (RC6+)\n");
1431 break;
1432 default:
1433 seq_puts(m, "unknown\n");
1434 break;
1435 }
1436
1437 return 0;
1438 }
1439
1440 static int i915_forcewake_domains(struct seq_file *m, void *data)
1441 {
1442 struct drm_info_node *node = m->private;
1443 struct drm_device *dev = node->minor->dev;
1444 struct drm_i915_private *dev_priv = dev->dev_private;
1445 struct intel_uncore_forcewake_domain *fw_domain;
1446 int i;
1447
1448 spin_lock_irq(&dev_priv->uncore.lock);
1449 for_each_fw_domain(fw_domain, dev_priv, i) {
1450 seq_printf(m, "%s.wake_count = %u\n",
1451 intel_uncore_forcewake_domain_to_str(i),
1452 fw_domain->wake_count);
1453 }
1454 spin_unlock_irq(&dev_priv->uncore.lock);
1455
1456 return 0;
1457 }
1458
1459 static int vlv_drpc_info(struct seq_file *m)
1460 {
1461 struct drm_info_node *node = m->private;
1462 struct drm_device *dev = node->minor->dev;
1463 struct drm_i915_private *dev_priv = dev->dev_private;
1464 u32 rpmodectl1, rcctl1, pw_status;
1465
1466 intel_runtime_pm_get(dev_priv);
1467
1468 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1469 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1470 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1471
1472 intel_runtime_pm_put(dev_priv);
1473
1474 seq_printf(m, "Video Turbo Mode: %s\n",
1475 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1476 seq_printf(m, "Turbo enabled: %s\n",
1477 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1478 seq_printf(m, "HW control enabled: %s\n",
1479 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1480 seq_printf(m, "SW control enabled: %s\n",
1481 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1482 GEN6_RP_MEDIA_SW_MODE));
1483 seq_printf(m, "RC6 Enabled: %s\n",
1484 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1485 GEN6_RC_CTL_EI_MODE(1))));
1486 seq_printf(m, "Render Power Well: %s\n",
1487 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1488 seq_printf(m, "Media Power Well: %s\n",
1489 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1490
1491 seq_printf(m, "Render RC6 residency since boot: %u\n",
1492 I915_READ(VLV_GT_RENDER_RC6));
1493 seq_printf(m, "Media RC6 residency since boot: %u\n",
1494 I915_READ(VLV_GT_MEDIA_RC6));
1495
1496 return i915_forcewake_domains(m, NULL);
1497 }
1498
1499 static int gen6_drpc_info(struct seq_file *m)
1500 {
1501 struct drm_info_node *node = m->private;
1502 struct drm_device *dev = node->minor->dev;
1503 struct drm_i915_private *dev_priv = dev->dev_private;
1504 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1505 unsigned forcewake_count;
1506 int count = 0, ret;
1507
1508 ret = mutex_lock_interruptible(&dev->struct_mutex);
1509 if (ret)
1510 return ret;
1511 intel_runtime_pm_get(dev_priv);
1512
1513 spin_lock_irq(&dev_priv->uncore.lock);
1514 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1515 spin_unlock_irq(&dev_priv->uncore.lock);
1516
1517 if (forcewake_count) {
1518 seq_puts(m, "RC information inaccurate because somebody "
1519 "holds a forcewake reference \n");
1520 } else {
1521 /* NB: we cannot use forcewake, else we read the wrong values */
1522 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1523 udelay(10);
1524 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1525 }
1526
1527 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1528 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1529
1530 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1531 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1532 mutex_unlock(&dev->struct_mutex);
1533 mutex_lock(&dev_priv->rps.hw_lock);
1534 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1535 mutex_unlock(&dev_priv->rps.hw_lock);
1536
1537 intel_runtime_pm_put(dev_priv);
1538
1539 seq_printf(m, "Video Turbo Mode: %s\n",
1540 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1541 seq_printf(m, "HW control enabled: %s\n",
1542 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1543 seq_printf(m, "SW control enabled: %s\n",
1544 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1545 GEN6_RP_MEDIA_SW_MODE));
1546 seq_printf(m, "RC1e Enabled: %s\n",
1547 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1548 seq_printf(m, "RC6 Enabled: %s\n",
1549 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1550 seq_printf(m, "Deep RC6 Enabled: %s\n",
1551 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1552 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1553 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1554 seq_puts(m, "Current RC state: ");
1555 switch (gt_core_status & GEN6_RCn_MASK) {
1556 case GEN6_RC0:
1557 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1558 seq_puts(m, "Core Power Down\n");
1559 else
1560 seq_puts(m, "on\n");
1561 break;
1562 case GEN6_RC3:
1563 seq_puts(m, "RC3\n");
1564 break;
1565 case GEN6_RC6:
1566 seq_puts(m, "RC6\n");
1567 break;
1568 case GEN6_RC7:
1569 seq_puts(m, "RC7\n");
1570 break;
1571 default:
1572 seq_puts(m, "Unknown\n");
1573 break;
1574 }
1575
1576 seq_printf(m, "Core Power Down: %s\n",
1577 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1578
1579 /* Not exactly sure what this is */
1580 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1581 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1582 seq_printf(m, "RC6 residency since boot: %u\n",
1583 I915_READ(GEN6_GT_GFX_RC6));
1584 seq_printf(m, "RC6+ residency since boot: %u\n",
1585 I915_READ(GEN6_GT_GFX_RC6p));
1586 seq_printf(m, "RC6++ residency since boot: %u\n",
1587 I915_READ(GEN6_GT_GFX_RC6pp));
1588
1589 seq_printf(m, "RC6 voltage: %dmV\n",
1590 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1591 seq_printf(m, "RC6+ voltage: %dmV\n",
1592 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1593 seq_printf(m, "RC6++ voltage: %dmV\n",
1594 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1595 return 0;
1596 }
1597
1598 static int i915_drpc_info(struct seq_file *m, void *unused)
1599 {
1600 struct drm_info_node *node = m->private;
1601 struct drm_device *dev = node->minor->dev;
1602
1603 if (IS_VALLEYVIEW(dev))
1604 return vlv_drpc_info(m);
1605 else if (INTEL_INFO(dev)->gen >= 6)
1606 return gen6_drpc_info(m);
1607 else
1608 return ironlake_drpc_info(m);
1609 }
1610
1611 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1612 {
1613 struct drm_info_node *node = m->private;
1614 struct drm_device *dev = node->minor->dev;
1615 struct drm_i915_private *dev_priv = dev->dev_private;
1616
1617 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1618 dev_priv->fb_tracking.busy_bits);
1619
1620 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1621 dev_priv->fb_tracking.flip_bits);
1622
1623 return 0;
1624 }
1625
1626 static int i915_fbc_status(struct seq_file *m, void *unused)
1627 {
1628 struct drm_info_node *node = m->private;
1629 struct drm_device *dev = node->minor->dev;
1630 struct drm_i915_private *dev_priv = dev->dev_private;
1631
1632 if (!HAS_FBC(dev)) {
1633 seq_puts(m, "FBC unsupported on this chipset\n");
1634 return 0;
1635 }
1636
1637 intel_runtime_pm_get(dev_priv);
1638 mutex_lock(&dev_priv->fbc.lock);
1639
1640 if (intel_fbc_enabled(dev_priv))
1641 seq_puts(m, "FBC enabled\n");
1642 else
1643 seq_printf(m, "FBC disabled: %s\n",
1644 intel_no_fbc_reason_str(dev_priv->fbc.no_fbc_reason));
1645
1646 if (INTEL_INFO(dev_priv)->gen >= 7)
1647 seq_printf(m, "Compressing: %s\n",
1648 yesno(I915_READ(FBC_STATUS2) &
1649 FBC_COMPRESSION_MASK));
1650
1651 mutex_unlock(&dev_priv->fbc.lock);
1652 intel_runtime_pm_put(dev_priv);
1653
1654 return 0;
1655 }
1656
1657 static int i915_fbc_fc_get(void *data, u64 *val)
1658 {
1659 struct drm_device *dev = data;
1660 struct drm_i915_private *dev_priv = dev->dev_private;
1661
1662 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1663 return -ENODEV;
1664
1665 *val = dev_priv->fbc.false_color;
1666
1667 return 0;
1668 }
1669
1670 static int i915_fbc_fc_set(void *data, u64 val)
1671 {
1672 struct drm_device *dev = data;
1673 struct drm_i915_private *dev_priv = dev->dev_private;
1674 u32 reg;
1675
1676 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1677 return -ENODEV;
1678
1679 mutex_lock(&dev_priv->fbc.lock);
1680
1681 reg = I915_READ(ILK_DPFC_CONTROL);
1682 dev_priv->fbc.false_color = val;
1683
1684 I915_WRITE(ILK_DPFC_CONTROL, val ?
1685 (reg | FBC_CTL_FALSE_COLOR) :
1686 (reg & ~FBC_CTL_FALSE_COLOR));
1687
1688 mutex_unlock(&dev_priv->fbc.lock);
1689 return 0;
1690 }
1691
1692 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1693 i915_fbc_fc_get, i915_fbc_fc_set,
1694 "%llu\n");
1695
1696 static int i915_ips_status(struct seq_file *m, void *unused)
1697 {
1698 struct drm_info_node *node = m->private;
1699 struct drm_device *dev = node->minor->dev;
1700 struct drm_i915_private *dev_priv = dev->dev_private;
1701
1702 if (!HAS_IPS(dev)) {
1703 seq_puts(m, "not supported\n");
1704 return 0;
1705 }
1706
1707 intel_runtime_pm_get(dev_priv);
1708
1709 seq_printf(m, "Enabled by kernel parameter: %s\n",
1710 yesno(i915.enable_ips));
1711
1712 if (INTEL_INFO(dev)->gen >= 8) {
1713 seq_puts(m, "Currently: unknown\n");
1714 } else {
1715 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1716 seq_puts(m, "Currently: enabled\n");
1717 else
1718 seq_puts(m, "Currently: disabled\n");
1719 }
1720
1721 intel_runtime_pm_put(dev_priv);
1722
1723 return 0;
1724 }
1725
1726 static int i915_sr_status(struct seq_file *m, void *unused)
1727 {
1728 struct drm_info_node *node = m->private;
1729 struct drm_device *dev = node->minor->dev;
1730 struct drm_i915_private *dev_priv = dev->dev_private;
1731 bool sr_enabled = false;
1732
1733 intel_runtime_pm_get(dev_priv);
1734
1735 if (HAS_PCH_SPLIT(dev))
1736 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1737 else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1738 IS_I945G(dev) || IS_I945GM(dev))
1739 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1740 else if (IS_I915GM(dev))
1741 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1742 else if (IS_PINEVIEW(dev))
1743 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1744 else if (IS_VALLEYVIEW(dev))
1745 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1746
1747 intel_runtime_pm_put(dev_priv);
1748
1749 seq_printf(m, "self-refresh: %s\n",
1750 sr_enabled ? "enabled" : "disabled");
1751
1752 return 0;
1753 }
1754
1755 static int i915_emon_status(struct seq_file *m, void *unused)
1756 {
1757 struct drm_info_node *node = m->private;
1758 struct drm_device *dev = node->minor->dev;
1759 struct drm_i915_private *dev_priv = dev->dev_private;
1760 unsigned long temp, chipset, gfx;
1761 int ret;
1762
1763 if (!IS_GEN5(dev))
1764 return -ENODEV;
1765
1766 ret = mutex_lock_interruptible(&dev->struct_mutex);
1767 if (ret)
1768 return ret;
1769
1770 temp = i915_mch_val(dev_priv);
1771 chipset = i915_chipset_val(dev_priv);
1772 gfx = i915_gfx_val(dev_priv);
1773 mutex_unlock(&dev->struct_mutex);
1774
1775 seq_printf(m, "GMCH temp: %ld\n", temp);
1776 seq_printf(m, "Chipset power: %ld\n", chipset);
1777 seq_printf(m, "GFX power: %ld\n", gfx);
1778 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1779
1780 return 0;
1781 }
1782
1783 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1784 {
1785 struct drm_info_node *node = m->private;
1786 struct drm_device *dev = node->minor->dev;
1787 struct drm_i915_private *dev_priv = dev->dev_private;
1788 int ret = 0;
1789 int gpu_freq, ia_freq;
1790 unsigned int max_gpu_freq, min_gpu_freq;
1791
1792 if (!HAS_CORE_RING_FREQ(dev)) {
1793 seq_puts(m, "unsupported on this chipset\n");
1794 return 0;
1795 }
1796
1797 intel_runtime_pm_get(dev_priv);
1798
1799 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1800
1801 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1802 if (ret)
1803 goto out;
1804
1805 if (IS_SKYLAKE(dev)) {
1806 /* Convert GT frequency to 50 HZ units */
1807 min_gpu_freq =
1808 dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1809 max_gpu_freq =
1810 dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1811 } else {
1812 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1813 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1814 }
1815
1816 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1817
1818 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1819 ia_freq = gpu_freq;
1820 sandybridge_pcode_read(dev_priv,
1821 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1822 &ia_freq);
1823 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1824 intel_gpu_freq(dev_priv, (gpu_freq *
1825 (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1))),
1826 ((ia_freq >> 0) & 0xff) * 100,
1827 ((ia_freq >> 8) & 0xff) * 100);
1828 }
1829
1830 mutex_unlock(&dev_priv->rps.hw_lock);
1831
1832 out:
1833 intel_runtime_pm_put(dev_priv);
1834 return ret;
1835 }
1836
1837 static int i915_opregion(struct seq_file *m, void *unused)
1838 {
1839 struct drm_info_node *node = m->private;
1840 struct drm_device *dev = node->minor->dev;
1841 struct drm_i915_private *dev_priv = dev->dev_private;
1842 struct intel_opregion *opregion = &dev_priv->opregion;
1843 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1844 int ret;
1845
1846 if (data == NULL)
1847 return -ENOMEM;
1848
1849 ret = mutex_lock_interruptible(&dev->struct_mutex);
1850 if (ret)
1851 goto out;
1852
1853 if (opregion->header) {
1854 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1855 seq_write(m, data, OPREGION_SIZE);
1856 }
1857
1858 mutex_unlock(&dev->struct_mutex);
1859
1860 out:
1861 kfree(data);
1862 return 0;
1863 }
1864
1865 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1866 {
1867 struct drm_info_node *node = m->private;
1868 struct drm_device *dev = node->minor->dev;
1869 struct intel_fbdev *ifbdev = NULL;
1870 struct intel_framebuffer *fb;
1871 struct drm_framebuffer *drm_fb;
1872
1873 #ifdef CONFIG_DRM_FBDEV_EMULATION
1874 struct drm_i915_private *dev_priv = dev->dev_private;
1875
1876 ifbdev = dev_priv->fbdev;
1877 fb = to_intel_framebuffer(ifbdev->helper.fb);
1878
1879 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1880 fb->base.width,
1881 fb->base.height,
1882 fb->base.depth,
1883 fb->base.bits_per_pixel,
1884 fb->base.modifier[0],
1885 atomic_read(&fb->base.refcount.refcount));
1886 describe_obj(m, fb->obj);
1887 seq_putc(m, '\n');
1888 #endif
1889
1890 mutex_lock(&dev->mode_config.fb_lock);
1891 drm_for_each_fb(drm_fb, dev) {
1892 fb = to_intel_framebuffer(drm_fb);
1893 if (ifbdev && &fb->base == ifbdev->helper.fb)
1894 continue;
1895
1896 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1897 fb->base.width,
1898 fb->base.height,
1899 fb->base.depth,
1900 fb->base.bits_per_pixel,
1901 fb->base.modifier[0],
1902 atomic_read(&fb->base.refcount.refcount));
1903 describe_obj(m, fb->obj);
1904 seq_putc(m, '\n');
1905 }
1906 mutex_unlock(&dev->mode_config.fb_lock);
1907
1908 return 0;
1909 }
1910
1911 static void describe_ctx_ringbuf(struct seq_file *m,
1912 struct intel_ringbuffer *ringbuf)
1913 {
1914 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1915 ringbuf->space, ringbuf->head, ringbuf->tail,
1916 ringbuf->last_retired_head);
1917 }
1918
1919 static int i915_context_status(struct seq_file *m, void *unused)
1920 {
1921 struct drm_info_node *node = m->private;
1922 struct drm_device *dev = node->minor->dev;
1923 struct drm_i915_private *dev_priv = dev->dev_private;
1924 struct intel_engine_cs *ring;
1925 struct intel_context *ctx;
1926 int ret, i;
1927
1928 ret = mutex_lock_interruptible(&dev->struct_mutex);
1929 if (ret)
1930 return ret;
1931
1932 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1933 if (!i915.enable_execlists &&
1934 ctx->legacy_hw_ctx.rcs_state == NULL)
1935 continue;
1936
1937 seq_puts(m, "HW context ");
1938 describe_ctx(m, ctx);
1939 for_each_ring(ring, dev_priv, i) {
1940 if (ring->default_context == ctx)
1941 seq_printf(m, "(default context %s) ",
1942 ring->name);
1943 }
1944
1945 if (i915.enable_execlists) {
1946 seq_putc(m, '\n');
1947 for_each_ring(ring, dev_priv, i) {
1948 struct drm_i915_gem_object *ctx_obj =
1949 ctx->engine[i].state;
1950 struct intel_ringbuffer *ringbuf =
1951 ctx->engine[i].ringbuf;
1952
1953 seq_printf(m, "%s: ", ring->name);
1954 if (ctx_obj)
1955 describe_obj(m, ctx_obj);
1956 if (ringbuf)
1957 describe_ctx_ringbuf(m, ringbuf);
1958 seq_putc(m, '\n');
1959 }
1960 } else {
1961 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1962 }
1963
1964 seq_putc(m, '\n');
1965 }
1966
1967 mutex_unlock(&dev->struct_mutex);
1968
1969 return 0;
1970 }
1971
1972 static void i915_dump_lrc_obj(struct seq_file *m,
1973 struct intel_engine_cs *ring,
1974 struct drm_i915_gem_object *ctx_obj)
1975 {
1976 struct page *page;
1977 uint32_t *reg_state;
1978 int j;
1979 unsigned long ggtt_offset = 0;
1980
1981 if (ctx_obj == NULL) {
1982 seq_printf(m, "Context on %s with no gem object\n",
1983 ring->name);
1984 return;
1985 }
1986
1987 seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1988 intel_execlists_ctx_id(ctx_obj));
1989
1990 if (!i915_gem_obj_ggtt_bound(ctx_obj))
1991 seq_puts(m, "\tNot bound in GGTT\n");
1992 else
1993 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1994
1995 if (i915_gem_object_get_pages(ctx_obj)) {
1996 seq_puts(m, "\tFailed to get pages for context object\n");
1997 return;
1998 }
1999
2000 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
2001 if (!WARN_ON(page == NULL)) {
2002 reg_state = kmap_atomic(page);
2003
2004 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2005 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2006 ggtt_offset + 4096 + (j * 4),
2007 reg_state[j], reg_state[j + 1],
2008 reg_state[j + 2], reg_state[j + 3]);
2009 }
2010 kunmap_atomic(reg_state);
2011 }
2012
2013 seq_putc(m, '\n');
2014 }
2015
2016 static int i915_dump_lrc(struct seq_file *m, void *unused)
2017 {
2018 struct drm_info_node *node = (struct drm_info_node *) m->private;
2019 struct drm_device *dev = node->minor->dev;
2020 struct drm_i915_private *dev_priv = dev->dev_private;
2021 struct intel_engine_cs *ring;
2022 struct intel_context *ctx;
2023 int ret, i;
2024
2025 if (!i915.enable_execlists) {
2026 seq_printf(m, "Logical Ring Contexts are disabled\n");
2027 return 0;
2028 }
2029
2030 ret = mutex_lock_interruptible(&dev->struct_mutex);
2031 if (ret)
2032 return ret;
2033
2034 list_for_each_entry(ctx, &dev_priv->context_list, link) {
2035 for_each_ring(ring, dev_priv, i) {
2036 if (ring->default_context != ctx)
2037 i915_dump_lrc_obj(m, ring,
2038 ctx->engine[i].state);
2039 }
2040 }
2041
2042 mutex_unlock(&dev->struct_mutex);
2043
2044 return 0;
2045 }
2046
2047 static int i915_execlists(struct seq_file *m, void *data)
2048 {
2049 struct drm_info_node *node = (struct drm_info_node *)m->private;
2050 struct drm_device *dev = node->minor->dev;
2051 struct drm_i915_private *dev_priv = dev->dev_private;
2052 struct intel_engine_cs *ring;
2053 u32 status_pointer;
2054 u8 read_pointer;
2055 u8 write_pointer;
2056 u32 status;
2057 u32 ctx_id;
2058 struct list_head *cursor;
2059 int ring_id, i;
2060 int ret;
2061
2062 if (!i915.enable_execlists) {
2063 seq_puts(m, "Logical Ring Contexts are disabled\n");
2064 return 0;
2065 }
2066
2067 ret = mutex_lock_interruptible(&dev->struct_mutex);
2068 if (ret)
2069 return ret;
2070
2071 intel_runtime_pm_get(dev_priv);
2072
2073 for_each_ring(ring, dev_priv, ring_id) {
2074 struct drm_i915_gem_request *head_req = NULL;
2075 int count = 0;
2076 unsigned long flags;
2077
2078 seq_printf(m, "%s\n", ring->name);
2079
2080 status = I915_READ(RING_EXECLIST_STATUS_LO(ring));
2081 ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(ring));
2082 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2083 status, ctx_id);
2084
2085 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
2086 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2087
2088 read_pointer = ring->next_context_status_buffer;
2089 write_pointer = status_pointer & 0x07;
2090 if (read_pointer > write_pointer)
2091 write_pointer += 6;
2092 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2093 read_pointer, write_pointer);
2094
2095 for (i = 0; i < 6; i++) {
2096 status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(ring, i));
2097 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(ring, i));
2098
2099 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2100 i, status, ctx_id);
2101 }
2102
2103 spin_lock_irqsave(&ring->execlist_lock, flags);
2104 list_for_each(cursor, &ring->execlist_queue)
2105 count++;
2106 head_req = list_first_entry_or_null(&ring->execlist_queue,
2107 struct drm_i915_gem_request, execlist_link);
2108 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2109
2110 seq_printf(m, "\t%d requests in queue\n", count);
2111 if (head_req) {
2112 struct drm_i915_gem_object *ctx_obj;
2113
2114 ctx_obj = head_req->ctx->engine[ring_id].state;
2115 seq_printf(m, "\tHead request id: %u\n",
2116 intel_execlists_ctx_id(ctx_obj));
2117 seq_printf(m, "\tHead request tail: %u\n",
2118 head_req->tail);
2119 }
2120
2121 seq_putc(m, '\n');
2122 }
2123
2124 intel_runtime_pm_put(dev_priv);
2125 mutex_unlock(&dev->struct_mutex);
2126
2127 return 0;
2128 }
2129
2130 static const char *swizzle_string(unsigned swizzle)
2131 {
2132 switch (swizzle) {
2133 case I915_BIT_6_SWIZZLE_NONE:
2134 return "none";
2135 case I915_BIT_6_SWIZZLE_9:
2136 return "bit9";
2137 case I915_BIT_6_SWIZZLE_9_10:
2138 return "bit9/bit10";
2139 case I915_BIT_6_SWIZZLE_9_11:
2140 return "bit9/bit11";
2141 case I915_BIT_6_SWIZZLE_9_10_11:
2142 return "bit9/bit10/bit11";
2143 case I915_BIT_6_SWIZZLE_9_17:
2144 return "bit9/bit17";
2145 case I915_BIT_6_SWIZZLE_9_10_17:
2146 return "bit9/bit10/bit17";
2147 case I915_BIT_6_SWIZZLE_UNKNOWN:
2148 return "unknown";
2149 }
2150
2151 return "bug";
2152 }
2153
2154 static int i915_swizzle_info(struct seq_file *m, void *data)
2155 {
2156 struct drm_info_node *node = m->private;
2157 struct drm_device *dev = node->minor->dev;
2158 struct drm_i915_private *dev_priv = dev->dev_private;
2159 int ret;
2160
2161 ret = mutex_lock_interruptible(&dev->struct_mutex);
2162 if (ret)
2163 return ret;
2164 intel_runtime_pm_get(dev_priv);
2165
2166 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2167 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2168 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2169 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2170
2171 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2172 seq_printf(m, "DDC = 0x%08x\n",
2173 I915_READ(DCC));
2174 seq_printf(m, "DDC2 = 0x%08x\n",
2175 I915_READ(DCC2));
2176 seq_printf(m, "C0DRB3 = 0x%04x\n",
2177 I915_READ16(C0DRB3));
2178 seq_printf(m, "C1DRB3 = 0x%04x\n",
2179 I915_READ16(C1DRB3));
2180 } else if (INTEL_INFO(dev)->gen >= 6) {
2181 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2182 I915_READ(MAD_DIMM_C0));
2183 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2184 I915_READ(MAD_DIMM_C1));
2185 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2186 I915_READ(MAD_DIMM_C2));
2187 seq_printf(m, "TILECTL = 0x%08x\n",
2188 I915_READ(TILECTL));
2189 if (INTEL_INFO(dev)->gen >= 8)
2190 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2191 I915_READ(GAMTARBMODE));
2192 else
2193 seq_printf(m, "ARB_MODE = 0x%08x\n",
2194 I915_READ(ARB_MODE));
2195 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2196 I915_READ(DISP_ARB_CTL));
2197 }
2198
2199 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2200 seq_puts(m, "L-shaped memory detected\n");
2201
2202 intel_runtime_pm_put(dev_priv);
2203 mutex_unlock(&dev->struct_mutex);
2204
2205 return 0;
2206 }
2207
2208 static int per_file_ctx(int id, void *ptr, void *data)
2209 {
2210 struct intel_context *ctx = ptr;
2211 struct seq_file *m = data;
2212 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2213
2214 if (!ppgtt) {
2215 seq_printf(m, " no ppgtt for context %d\n",
2216 ctx->user_handle);
2217 return 0;
2218 }
2219
2220 if (i915_gem_context_is_default(ctx))
2221 seq_puts(m, " default context:\n");
2222 else
2223 seq_printf(m, " context %d:\n", ctx->user_handle);
2224 ppgtt->debug_dump(ppgtt, m);
2225
2226 return 0;
2227 }
2228
2229 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2230 {
2231 struct drm_i915_private *dev_priv = dev->dev_private;
2232 struct intel_engine_cs *ring;
2233 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2234 int unused, i;
2235
2236 if (!ppgtt)
2237 return;
2238
2239 for_each_ring(ring, dev_priv, unused) {
2240 seq_printf(m, "%s\n", ring->name);
2241 for (i = 0; i < 4; i++) {
2242 u64 pdp = I915_READ(GEN8_RING_PDP_UDW(ring, i));
2243 pdp <<= 32;
2244 pdp |= I915_READ(GEN8_RING_PDP_LDW(ring, i));
2245 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2246 }
2247 }
2248 }
2249
2250 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2251 {
2252 struct drm_i915_private *dev_priv = dev->dev_private;
2253 struct intel_engine_cs *ring;
2254 int i;
2255
2256 if (INTEL_INFO(dev)->gen == 6)
2257 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2258
2259 for_each_ring(ring, dev_priv, i) {
2260 seq_printf(m, "%s\n", ring->name);
2261 if (INTEL_INFO(dev)->gen == 7)
2262 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2263 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2264 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2265 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2266 }
2267 if (dev_priv->mm.aliasing_ppgtt) {
2268 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2269
2270 seq_puts(m, "aliasing PPGTT:\n");
2271 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2272
2273 ppgtt->debug_dump(ppgtt, m);
2274 }
2275
2276 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2277 }
2278
2279 static int i915_ppgtt_info(struct seq_file *m, void *data)
2280 {
2281 struct drm_info_node *node = m->private;
2282 struct drm_device *dev = node->minor->dev;
2283 struct drm_i915_private *dev_priv = dev->dev_private;
2284 struct drm_file *file;
2285
2286 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2287 if (ret)
2288 return ret;
2289 intel_runtime_pm_get(dev_priv);
2290
2291 if (INTEL_INFO(dev)->gen >= 8)
2292 gen8_ppgtt_info(m, dev);
2293 else if (INTEL_INFO(dev)->gen >= 6)
2294 gen6_ppgtt_info(m, dev);
2295
2296 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2297 struct drm_i915_file_private *file_priv = file->driver_priv;
2298 struct task_struct *task;
2299
2300 task = get_pid_task(file->pid, PIDTYPE_PID);
2301 if (!task)
2302 return -ESRCH;
2303 seq_printf(m, "\nproc: %s\n", task->comm);
2304 put_task_struct(task);
2305 idr_for_each(&file_priv->context_idr, per_file_ctx,
2306 (void *)(unsigned long)m);
2307 }
2308
2309 intel_runtime_pm_put(dev_priv);
2310 mutex_unlock(&dev->struct_mutex);
2311
2312 return 0;
2313 }
2314
2315 static int count_irq_waiters(struct drm_i915_private *i915)
2316 {
2317 struct intel_engine_cs *ring;
2318 int count = 0;
2319 int i;
2320
2321 for_each_ring(ring, i915, i)
2322 count += ring->irq_refcount;
2323
2324 return count;
2325 }
2326
2327 static int i915_rps_boost_info(struct seq_file *m, void *data)
2328 {
2329 struct drm_info_node *node = m->private;
2330 struct drm_device *dev = node->minor->dev;
2331 struct drm_i915_private *dev_priv = dev->dev_private;
2332 struct drm_file *file;
2333
2334 seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2335 seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
2336 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2337 seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2338 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2339 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2340 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2341 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2342 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2343 spin_lock(&dev_priv->rps.client_lock);
2344 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2345 struct drm_i915_file_private *file_priv = file->driver_priv;
2346 struct task_struct *task;
2347
2348 rcu_read_lock();
2349 task = pid_task(file->pid, PIDTYPE_PID);
2350 seq_printf(m, "%s [%d]: %d boosts%s\n",
2351 task ? task->comm : "<unknown>",
2352 task ? task->pid : -1,
2353 file_priv->rps.boosts,
2354 list_empty(&file_priv->rps.link) ? "" : ", active");
2355 rcu_read_unlock();
2356 }
2357 seq_printf(m, "Semaphore boosts: %d%s\n",
2358 dev_priv->rps.semaphores.boosts,
2359 list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");
2360 seq_printf(m, "MMIO flip boosts: %d%s\n",
2361 dev_priv->rps.mmioflips.boosts,
2362 list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
2363 seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
2364 spin_unlock(&dev_priv->rps.client_lock);
2365
2366 return 0;
2367 }
2368
2369 static int i915_llc(struct seq_file *m, void *data)
2370 {
2371 struct drm_info_node *node = m->private;
2372 struct drm_device *dev = node->minor->dev;
2373 struct drm_i915_private *dev_priv = dev->dev_private;
2374
2375 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2376 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2377 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2378
2379 return 0;
2380 }
2381
2382 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2383 {
2384 struct drm_info_node *node = m->private;
2385 struct drm_i915_private *dev_priv = node->minor->dev->dev_private;
2386 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2387 u32 tmp, i;
2388
2389 if (!HAS_GUC_UCODE(dev_priv->dev))
2390 return 0;
2391
2392 seq_printf(m, "GuC firmware status:\n");
2393 seq_printf(m, "\tpath: %s\n",
2394 guc_fw->guc_fw_path);
2395 seq_printf(m, "\tfetch: %s\n",
2396 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2397 seq_printf(m, "\tload: %s\n",
2398 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2399 seq_printf(m, "\tversion wanted: %d.%d\n",
2400 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2401 seq_printf(m, "\tversion found: %d.%d\n",
2402 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2403
2404 tmp = I915_READ(GUC_STATUS);
2405
2406 seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2407 seq_printf(m, "\tBootrom status = 0x%x\n",
2408 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2409 seq_printf(m, "\tuKernel status = 0x%x\n",
2410 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2411 seq_printf(m, "\tMIA Core status = 0x%x\n",
2412 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2413 seq_puts(m, "\nScratch registers:\n");
2414 for (i = 0; i < 16; i++)
2415 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2416
2417 return 0;
2418 }
2419
2420 static void i915_guc_client_info(struct seq_file *m,
2421 struct drm_i915_private *dev_priv,
2422 struct i915_guc_client *client)
2423 {
2424 struct intel_engine_cs *ring;
2425 uint64_t tot = 0;
2426 uint32_t i;
2427
2428 seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2429 client->priority, client->ctx_index, client->proc_desc_offset);
2430 seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2431 client->doorbell_id, client->doorbell_offset, client->cookie);
2432 seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2433 client->wq_size, client->wq_offset, client->wq_tail);
2434
2435 seq_printf(m, "\tFailed to queue: %u\n", client->q_fail);
2436 seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2437 seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2438
2439 for_each_ring(ring, dev_priv, i) {
2440 seq_printf(m, "\tSubmissions: %llu %s\n",
2441 client->submissions[i],
2442 ring->name);
2443 tot += client->submissions[i];
2444 }
2445 seq_printf(m, "\tTotal: %llu\n", tot);
2446 }
2447
2448 static int i915_guc_info(struct seq_file *m, void *data)
2449 {
2450 struct drm_info_node *node = m->private;
2451 struct drm_device *dev = node->minor->dev;
2452 struct drm_i915_private *dev_priv = dev->dev_private;
2453 struct intel_guc guc;
2454 struct i915_guc_client client = {};
2455 struct intel_engine_cs *ring;
2456 enum intel_ring_id i;
2457 u64 total = 0;
2458
2459 if (!HAS_GUC_SCHED(dev_priv->dev))
2460 return 0;
2461
2462 /* Take a local copy of the GuC data, so we can dump it at leisure */
2463 spin_lock(&dev_priv->guc.host2guc_lock);
2464 guc = dev_priv->guc;
2465 if (guc.execbuf_client) {
2466 spin_lock(&guc.execbuf_client->wq_lock);
2467 client = *guc.execbuf_client;
2468 spin_unlock(&guc.execbuf_client->wq_lock);
2469 }
2470 spin_unlock(&dev_priv->guc.host2guc_lock);
2471
2472 seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2473 seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2474 seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2475 seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2476 seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2477
2478 seq_printf(m, "\nGuC submissions:\n");
2479 for_each_ring(ring, dev_priv, i) {
2480 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x %9d\n",
2481 ring->name, guc.submissions[i],
2482 guc.last_seqno[i], guc.last_seqno[i]);
2483 total += guc.submissions[i];
2484 }
2485 seq_printf(m, "\t%s: %llu\n", "Total", total);
2486
2487 seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2488 i915_guc_client_info(m, dev_priv, &client);
2489
2490 /* Add more as required ... */
2491
2492 return 0;
2493 }
2494
2495 static int i915_guc_log_dump(struct seq_file *m, void *data)
2496 {
2497 struct drm_info_node *node = m->private;
2498 struct drm_device *dev = node->minor->dev;
2499 struct drm_i915_private *dev_priv = dev->dev_private;
2500 struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;
2501 u32 *log;
2502 int i = 0, pg;
2503
2504 if (!log_obj)
2505 return 0;
2506
2507 for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) {
2508 log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));
2509
2510 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2511 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2512 *(log + i), *(log + i + 1),
2513 *(log + i + 2), *(log + i + 3));
2514
2515 kunmap_atomic(log);
2516 }
2517
2518 seq_putc(m, '\n');
2519
2520 return 0;
2521 }
2522
2523 static int i915_edp_psr_status(struct seq_file *m, void *data)
2524 {
2525 struct drm_info_node *node = m->private;
2526 struct drm_device *dev = node->minor->dev;
2527 struct drm_i915_private *dev_priv = dev->dev_private;
2528 u32 psrperf = 0;
2529 u32 stat[3];
2530 enum pipe pipe;
2531 bool enabled = false;
2532
2533 if (!HAS_PSR(dev)) {
2534 seq_puts(m, "PSR not supported\n");
2535 return 0;
2536 }
2537
2538 intel_runtime_pm_get(dev_priv);
2539
2540 mutex_lock(&dev_priv->psr.lock);
2541 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2542 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2543 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2544 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2545 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2546 dev_priv->psr.busy_frontbuffer_bits);
2547 seq_printf(m, "Re-enable work scheduled: %s\n",
2548 yesno(work_busy(&dev_priv->psr.work.work)));
2549
2550 if (HAS_DDI(dev))
2551 enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2552 else {
2553 for_each_pipe(dev_priv, pipe) {
2554 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2555 VLV_EDP_PSR_CURR_STATE_MASK;
2556 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2557 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2558 enabled = true;
2559 }
2560 }
2561 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2562
2563 if (!HAS_DDI(dev))
2564 for_each_pipe(dev_priv, pipe) {
2565 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2566 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2567 seq_printf(m, " pipe %c", pipe_name(pipe));
2568 }
2569 seq_puts(m, "\n");
2570
2571 /* CHV PSR has no kind of performance counter */
2572 if (HAS_DDI(dev)) {
2573 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2574 EDP_PSR_PERF_CNT_MASK;
2575
2576 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2577 }
2578 mutex_unlock(&dev_priv->psr.lock);
2579
2580 intel_runtime_pm_put(dev_priv);
2581 return 0;
2582 }
2583
2584 static int i915_sink_crc(struct seq_file *m, void *data)
2585 {
2586 struct drm_info_node *node = m->private;
2587 struct drm_device *dev = node->minor->dev;
2588 struct intel_encoder *encoder;
2589 struct intel_connector *connector;
2590 struct intel_dp *intel_dp = NULL;
2591 int ret;
2592 u8 crc[6];
2593
2594 drm_modeset_lock_all(dev);
2595 for_each_intel_connector(dev, connector) {
2596
2597 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2598 continue;
2599
2600 if (!connector->base.encoder)
2601 continue;
2602
2603 encoder = to_intel_encoder(connector->base.encoder);
2604 if (encoder->type != INTEL_OUTPUT_EDP)
2605 continue;
2606
2607 intel_dp = enc_to_intel_dp(&encoder->base);
2608
2609 ret = intel_dp_sink_crc(intel_dp, crc);
2610 if (ret)
2611 goto out;
2612
2613 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2614 crc[0], crc[1], crc[2],
2615 crc[3], crc[4], crc[5]);
2616 goto out;
2617 }
2618 ret = -ENODEV;
2619 out:
2620 drm_modeset_unlock_all(dev);
2621 return ret;
2622 }
2623
2624 static int i915_energy_uJ(struct seq_file *m, void *data)
2625 {
2626 struct drm_info_node *node = m->private;
2627 struct drm_device *dev = node->minor->dev;
2628 struct drm_i915_private *dev_priv = dev->dev_private;
2629 u64 power;
2630 u32 units;
2631
2632 if (INTEL_INFO(dev)->gen < 6)
2633 return -ENODEV;
2634
2635 intel_runtime_pm_get(dev_priv);
2636
2637 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2638 power = (power & 0x1f00) >> 8;
2639 units = 1000000 / (1 << power); /* convert to uJ */
2640 power = I915_READ(MCH_SECP_NRG_STTS);
2641 power *= units;
2642
2643 intel_runtime_pm_put(dev_priv);
2644
2645 seq_printf(m, "%llu", (long long unsigned)power);
2646
2647 return 0;
2648 }
2649
2650 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2651 {
2652 struct drm_info_node *node = m->private;
2653 struct drm_device *dev = node->minor->dev;
2654 struct drm_i915_private *dev_priv = dev->dev_private;
2655
2656 if (!HAS_RUNTIME_PM(dev)) {
2657 seq_puts(m, "not supported\n");
2658 return 0;
2659 }
2660
2661 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2662 seq_printf(m, "IRQs disabled: %s\n",
2663 yesno(!intel_irqs_enabled(dev_priv)));
2664 #ifdef CONFIG_PM
2665 seq_printf(m, "Usage count: %d\n",
2666 atomic_read(&dev->dev->power.usage_count));
2667 #else
2668 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2669 #endif
2670
2671 return 0;
2672 }
2673
2674 static const char *power_domain_str(enum intel_display_power_domain domain)
2675 {
2676 switch (domain) {
2677 case POWER_DOMAIN_PIPE_A:
2678 return "PIPE_A";
2679 case POWER_DOMAIN_PIPE_B:
2680 return "PIPE_B";
2681 case POWER_DOMAIN_PIPE_C:
2682 return "PIPE_C";
2683 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2684 return "PIPE_A_PANEL_FITTER";
2685 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2686 return "PIPE_B_PANEL_FITTER";
2687 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2688 return "PIPE_C_PANEL_FITTER";
2689 case POWER_DOMAIN_TRANSCODER_A:
2690 return "TRANSCODER_A";
2691 case POWER_DOMAIN_TRANSCODER_B:
2692 return "TRANSCODER_B";
2693 case POWER_DOMAIN_TRANSCODER_C:
2694 return "TRANSCODER_C";
2695 case POWER_DOMAIN_TRANSCODER_EDP:
2696 return "TRANSCODER_EDP";
2697 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2698 return "PORT_DDI_A_2_LANES";
2699 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2700 return "PORT_DDI_A_4_LANES";
2701 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2702 return "PORT_DDI_B_2_LANES";
2703 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2704 return "PORT_DDI_B_4_LANES";
2705 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2706 return "PORT_DDI_C_2_LANES";
2707 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2708 return "PORT_DDI_C_4_LANES";
2709 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2710 return "PORT_DDI_D_2_LANES";
2711 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2712 return "PORT_DDI_D_4_LANES";
2713 case POWER_DOMAIN_PORT_DDI_E_2_LANES:
2714 return "PORT_DDI_E_2_LANES";
2715 case POWER_DOMAIN_PORT_DSI:
2716 return "PORT_DSI";
2717 case POWER_DOMAIN_PORT_CRT:
2718 return "PORT_CRT";
2719 case POWER_DOMAIN_PORT_OTHER:
2720 return "PORT_OTHER";
2721 case POWER_DOMAIN_VGA:
2722 return "VGA";
2723 case POWER_DOMAIN_AUDIO:
2724 return "AUDIO";
2725 case POWER_DOMAIN_PLLS:
2726 return "PLLS";
2727 case POWER_DOMAIN_AUX_A:
2728 return "AUX_A";
2729 case POWER_DOMAIN_AUX_B:
2730 return "AUX_B";
2731 case POWER_DOMAIN_AUX_C:
2732 return "AUX_C";
2733 case POWER_DOMAIN_AUX_D:
2734 return "AUX_D";
2735 case POWER_DOMAIN_INIT:
2736 return "INIT";
2737 default:
2738 MISSING_CASE(domain);
2739 return "?";
2740 }
2741 }
2742
2743 static int i915_power_domain_info(struct seq_file *m, void *unused)
2744 {
2745 struct drm_info_node *node = m->private;
2746 struct drm_device *dev = node->minor->dev;
2747 struct drm_i915_private *dev_priv = dev->dev_private;
2748 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2749 int i;
2750
2751 mutex_lock(&power_domains->lock);
2752
2753 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2754 for (i = 0; i < power_domains->power_well_count; i++) {
2755 struct i915_power_well *power_well;
2756 enum intel_display_power_domain power_domain;
2757
2758 power_well = &power_domains->power_wells[i];
2759 seq_printf(m, "%-25s %d\n", power_well->name,
2760 power_well->count);
2761
2762 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2763 power_domain++) {
2764 if (!(BIT(power_domain) & power_well->domains))
2765 continue;
2766
2767 seq_printf(m, " %-23s %d\n",
2768 power_domain_str(power_domain),
2769 power_domains->domain_use_count[power_domain]);
2770 }
2771 }
2772
2773 mutex_unlock(&power_domains->lock);
2774
2775 return 0;
2776 }
2777
2778 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2779 struct drm_display_mode *mode)
2780 {
2781 int i;
2782
2783 for (i = 0; i < tabs; i++)
2784 seq_putc(m, '\t');
2785
2786 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2787 mode->base.id, mode->name,
2788 mode->vrefresh, mode->clock,
2789 mode->hdisplay, mode->hsync_start,
2790 mode->hsync_end, mode->htotal,
2791 mode->vdisplay, mode->vsync_start,
2792 mode->vsync_end, mode->vtotal,
2793 mode->type, mode->flags);
2794 }
2795
2796 static void intel_encoder_info(struct seq_file *m,
2797 struct intel_crtc *intel_crtc,
2798 struct intel_encoder *intel_encoder)
2799 {
2800 struct drm_info_node *node = m->private;
2801 struct drm_device *dev = node->minor->dev;
2802 struct drm_crtc *crtc = &intel_crtc->base;
2803 struct intel_connector *intel_connector;
2804 struct drm_encoder *encoder;
2805
2806 encoder = &intel_encoder->base;
2807 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2808 encoder->base.id, encoder->name);
2809 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2810 struct drm_connector *connector = &intel_connector->base;
2811 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2812 connector->base.id,
2813 connector->name,
2814 drm_get_connector_status_name(connector->status));
2815 if (connector->status == connector_status_connected) {
2816 struct drm_display_mode *mode = &crtc->mode;
2817 seq_printf(m, ", mode:\n");
2818 intel_seq_print_mode(m, 2, mode);
2819 } else {
2820 seq_putc(m, '\n');
2821 }
2822 }
2823 }
2824
2825 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2826 {
2827 struct drm_info_node *node = m->private;
2828 struct drm_device *dev = node->minor->dev;
2829 struct drm_crtc *crtc = &intel_crtc->base;
2830 struct intel_encoder *intel_encoder;
2831 struct drm_plane_state *plane_state = crtc->primary->state;
2832 struct drm_framebuffer *fb = plane_state->fb;
2833
2834 if (fb)
2835 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2836 fb->base.id, plane_state->src_x >> 16,
2837 plane_state->src_y >> 16, fb->width, fb->height);
2838 else
2839 seq_puts(m, "\tprimary plane disabled\n");
2840 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2841 intel_encoder_info(m, intel_crtc, intel_encoder);
2842 }
2843
2844 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2845 {
2846 struct drm_display_mode *mode = panel->fixed_mode;
2847
2848 seq_printf(m, "\tfixed mode:\n");
2849 intel_seq_print_mode(m, 2, mode);
2850 }
2851
2852 static void intel_dp_info(struct seq_file *m,
2853 struct intel_connector *intel_connector)
2854 {
2855 struct intel_encoder *intel_encoder = intel_connector->encoder;
2856 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2857
2858 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2859 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2860 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2861 intel_panel_info(m, &intel_connector->panel);
2862 }
2863
2864 static void intel_hdmi_info(struct seq_file *m,
2865 struct intel_connector *intel_connector)
2866 {
2867 struct intel_encoder *intel_encoder = intel_connector->encoder;
2868 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2869
2870 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2871 }
2872
2873 static void intel_lvds_info(struct seq_file *m,
2874 struct intel_connector *intel_connector)
2875 {
2876 intel_panel_info(m, &intel_connector->panel);
2877 }
2878
2879 static void intel_connector_info(struct seq_file *m,
2880 struct drm_connector *connector)
2881 {
2882 struct intel_connector *intel_connector = to_intel_connector(connector);
2883 struct intel_encoder *intel_encoder = intel_connector->encoder;
2884 struct drm_display_mode *mode;
2885
2886 seq_printf(m, "connector %d: type %s, status: %s\n",
2887 connector->base.id, connector->name,
2888 drm_get_connector_status_name(connector->status));
2889 if (connector->status == connector_status_connected) {
2890 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2891 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2892 connector->display_info.width_mm,
2893 connector->display_info.height_mm);
2894 seq_printf(m, "\tsubpixel order: %s\n",
2895 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2896 seq_printf(m, "\tCEA rev: %d\n",
2897 connector->display_info.cea_rev);
2898 }
2899 if (intel_encoder) {
2900 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2901 intel_encoder->type == INTEL_OUTPUT_EDP)
2902 intel_dp_info(m, intel_connector);
2903 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2904 intel_hdmi_info(m, intel_connector);
2905 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2906 intel_lvds_info(m, intel_connector);
2907 }
2908
2909 seq_printf(m, "\tmodes:\n");
2910 list_for_each_entry(mode, &connector->modes, head)
2911 intel_seq_print_mode(m, 2, mode);
2912 }
2913
2914 static bool cursor_active(struct drm_device *dev, int pipe)
2915 {
2916 struct drm_i915_private *dev_priv = dev->dev_private;
2917 u32 state;
2918
2919 if (IS_845G(dev) || IS_I865G(dev))
2920 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
2921 else
2922 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2923
2924 return state;
2925 }
2926
2927 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2928 {
2929 struct drm_i915_private *dev_priv = dev->dev_private;
2930 u32 pos;
2931
2932 pos = I915_READ(CURPOS(pipe));
2933
2934 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2935 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2936 *x = -*x;
2937
2938 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2939 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2940 *y = -*y;
2941
2942 return cursor_active(dev, pipe);
2943 }
2944
2945 static int i915_display_info(struct seq_file *m, void *unused)
2946 {
2947 struct drm_info_node *node = m->private;
2948 struct drm_device *dev = node->minor->dev;
2949 struct drm_i915_private *dev_priv = dev->dev_private;
2950 struct intel_crtc *crtc;
2951 struct drm_connector *connector;
2952
2953 intel_runtime_pm_get(dev_priv);
2954 drm_modeset_lock_all(dev);
2955 seq_printf(m, "CRTC info\n");
2956 seq_printf(m, "---------\n");
2957 for_each_intel_crtc(dev, crtc) {
2958 bool active;
2959 struct intel_crtc_state *pipe_config;
2960 int x, y;
2961
2962 pipe_config = to_intel_crtc_state(crtc->base.state);
2963
2964 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
2965 crtc->base.base.id, pipe_name(crtc->pipe),
2966 yesno(pipe_config->base.active),
2967 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
2968 if (pipe_config->base.active) {
2969 intel_crtc_info(m, crtc);
2970
2971 active = cursor_position(dev, crtc->pipe, &x, &y);
2972 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
2973 yesno(crtc->cursor_base),
2974 x, y, crtc->base.cursor->state->crtc_w,
2975 crtc->base.cursor->state->crtc_h,
2976 crtc->cursor_addr, yesno(active));
2977 }
2978
2979 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2980 yesno(!crtc->cpu_fifo_underrun_disabled),
2981 yesno(!crtc->pch_fifo_underrun_disabled));
2982 }
2983
2984 seq_printf(m, "\n");
2985 seq_printf(m, "Connector info\n");
2986 seq_printf(m, "--------------\n");
2987 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2988 intel_connector_info(m, connector);
2989 }
2990 drm_modeset_unlock_all(dev);
2991 intel_runtime_pm_put(dev_priv);
2992
2993 return 0;
2994 }
2995
2996 static int i915_semaphore_status(struct seq_file *m, void *unused)
2997 {
2998 struct drm_info_node *node = (struct drm_info_node *) m->private;
2999 struct drm_device *dev = node->minor->dev;
3000 struct drm_i915_private *dev_priv = dev->dev_private;
3001 struct intel_engine_cs *ring;
3002 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
3003 int i, j, ret;
3004
3005 if (!i915_semaphore_is_enabled(dev)) {
3006 seq_puts(m, "Semaphores are disabled\n");
3007 return 0;
3008 }
3009
3010 ret = mutex_lock_interruptible(&dev->struct_mutex);
3011 if (ret)
3012 return ret;
3013 intel_runtime_pm_get(dev_priv);
3014
3015 if (IS_BROADWELL(dev)) {
3016 struct page *page;
3017 uint64_t *seqno;
3018
3019 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
3020
3021 seqno = (uint64_t *)kmap_atomic(page);
3022 for_each_ring(ring, dev_priv, i) {
3023 uint64_t offset;
3024
3025 seq_printf(m, "%s\n", ring->name);
3026
3027 seq_puts(m, " Last signal:");
3028 for (j = 0; j < num_rings; j++) {
3029 offset = i * I915_NUM_RINGS + j;
3030 seq_printf(m, "0x%08llx (0x%02llx) ",
3031 seqno[offset], offset * 8);
3032 }
3033 seq_putc(m, '\n');
3034
3035 seq_puts(m, " Last wait: ");
3036 for (j = 0; j < num_rings; j++) {
3037 offset = i + (j * I915_NUM_RINGS);
3038 seq_printf(m, "0x%08llx (0x%02llx) ",
3039 seqno[offset], offset * 8);
3040 }
3041 seq_putc(m, '\n');
3042
3043 }
3044 kunmap_atomic(seqno);
3045 } else {
3046 seq_puts(m, " Last signal:");
3047 for_each_ring(ring, dev_priv, i)
3048 for (j = 0; j < num_rings; j++)
3049 seq_printf(m, "0x%08x\n",
3050 I915_READ(ring->semaphore.mbox.signal[j]));
3051 seq_putc(m, '\n');
3052 }
3053
3054 seq_puts(m, "\nSync seqno:\n");
3055 for_each_ring(ring, dev_priv, i) {
3056 for (j = 0; j < num_rings; j++) {
3057 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]);
3058 }
3059 seq_putc(m, '\n');
3060 }
3061 seq_putc(m, '\n');
3062
3063 intel_runtime_pm_put(dev_priv);
3064 mutex_unlock(&dev->struct_mutex);
3065 return 0;
3066 }
3067
3068 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3069 {
3070 struct drm_info_node *node = (struct drm_info_node *) m->private;
3071 struct drm_device *dev = node->minor->dev;
3072 struct drm_i915_private *dev_priv = dev->dev_private;
3073 int i;
3074
3075 drm_modeset_lock_all(dev);
3076 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3077 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3078
3079 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3080 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
3081 pll->config.crtc_mask, pll->active, yesno(pll->on));
3082 seq_printf(m, " tracked hardware state:\n");
3083 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
3084 seq_printf(m, " dpll_md: 0x%08x\n",
3085 pll->config.hw_state.dpll_md);
3086 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
3087 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
3088 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
3089 }
3090 drm_modeset_unlock_all(dev);
3091
3092 return 0;
3093 }
3094
3095 static int i915_wa_registers(struct seq_file *m, void *unused)
3096 {
3097 int i;
3098 int ret;
3099 struct drm_info_node *node = (struct drm_info_node *) m->private;
3100 struct drm_device *dev = node->minor->dev;
3101 struct drm_i915_private *dev_priv = dev->dev_private;
3102
3103 ret = mutex_lock_interruptible(&dev->struct_mutex);
3104 if (ret)
3105 return ret;
3106
3107 intel_runtime_pm_get(dev_priv);
3108
3109 seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
3110 for (i = 0; i < dev_priv->workarounds.count; ++i) {
3111 u32 addr, mask, value, read;
3112 bool ok;
3113
3114 addr = dev_priv->workarounds.reg[i].addr;
3115 mask = dev_priv->workarounds.reg[i].mask;
3116 value = dev_priv->workarounds.reg[i].value;
3117 read = I915_READ(addr);
3118 ok = (value & mask) == (read & mask);
3119 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3120 addr, value, mask, read, ok ? "OK" : "FAIL");
3121 }
3122
3123 intel_runtime_pm_put(dev_priv);
3124 mutex_unlock(&dev->struct_mutex);
3125
3126 return 0;
3127 }
3128
3129 static int i915_ddb_info(struct seq_file *m, void *unused)
3130 {
3131 struct drm_info_node *node = m->private;
3132 struct drm_device *dev = node->minor->dev;
3133 struct drm_i915_private *dev_priv = dev->dev_private;
3134 struct skl_ddb_allocation *ddb;
3135 struct skl_ddb_entry *entry;
3136 enum pipe pipe;
3137 int plane;
3138
3139 if (INTEL_INFO(dev)->gen < 9)
3140 return 0;
3141
3142 drm_modeset_lock_all(dev);
3143
3144 ddb = &dev_priv->wm.skl_hw.ddb;
3145
3146 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3147
3148 for_each_pipe(dev_priv, pipe) {
3149 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3150
3151 for_each_plane(dev_priv, pipe, plane) {
3152 entry = &ddb->plane[pipe][plane];
3153 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
3154 entry->start, entry->end,
3155 skl_ddb_entry_size(entry));
3156 }
3157
3158 entry = &ddb->cursor[pipe];
3159 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
3160 entry->end, skl_ddb_entry_size(entry));
3161 }
3162
3163 drm_modeset_unlock_all(dev);
3164
3165 return 0;
3166 }
3167
3168 static void drrs_status_per_crtc(struct seq_file *m,
3169 struct drm_device *dev, struct intel_crtc *intel_crtc)
3170 {
3171 struct intel_encoder *intel_encoder;
3172 struct drm_i915_private *dev_priv = dev->dev_private;
3173 struct i915_drrs *drrs = &dev_priv->drrs;
3174 int vrefresh = 0;
3175
3176 for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
3177 /* Encoder connected on this CRTC */
3178 switch (intel_encoder->type) {
3179 case INTEL_OUTPUT_EDP:
3180 seq_puts(m, "eDP:\n");
3181 break;
3182 case INTEL_OUTPUT_DSI:
3183 seq_puts(m, "DSI:\n");
3184 break;
3185 case INTEL_OUTPUT_HDMI:
3186 seq_puts(m, "HDMI:\n");
3187 break;
3188 case INTEL_OUTPUT_DISPLAYPORT:
3189 seq_puts(m, "DP:\n");
3190 break;
3191 default:
3192 seq_printf(m, "Other encoder (id=%d).\n",
3193 intel_encoder->type);
3194 return;
3195 }
3196 }
3197
3198 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3199 seq_puts(m, "\tVBT: DRRS_type: Static");
3200 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3201 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3202 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3203 seq_puts(m, "\tVBT: DRRS_type: None");
3204 else
3205 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3206
3207 seq_puts(m, "\n\n");
3208
3209 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3210 struct intel_panel *panel;
3211
3212 mutex_lock(&drrs->mutex);
3213 /* DRRS Supported */
3214 seq_puts(m, "\tDRRS Supported: Yes\n");
3215
3216 /* disable_drrs() will make drrs->dp NULL */
3217 if (!drrs->dp) {
3218 seq_puts(m, "Idleness DRRS: Disabled");
3219 mutex_unlock(&drrs->mutex);
3220 return;
3221 }
3222
3223 panel = &drrs->dp->attached_connector->panel;
3224 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3225 drrs->busy_frontbuffer_bits);
3226
3227 seq_puts(m, "\n\t\t");
3228 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3229 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3230 vrefresh = panel->fixed_mode->vrefresh;
3231 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3232 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3233 vrefresh = panel->downclock_mode->vrefresh;
3234 } else {
3235 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3236 drrs->refresh_rate_type);
3237 mutex_unlock(&drrs->mutex);
3238 return;
3239 }
3240 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3241
3242 seq_puts(m, "\n\t\t");
3243 mutex_unlock(&drrs->mutex);
3244 } else {
3245 /* DRRS not supported. Print the VBT parameter*/
3246 seq_puts(m, "\tDRRS Supported : No");
3247 }
3248 seq_puts(m, "\n");
3249 }
3250
3251 static int i915_drrs_status(struct seq_file *m, void *unused)
3252 {
3253 struct drm_info_node *node = m->private;
3254 struct drm_device *dev = node->minor->dev;
3255 struct intel_crtc *intel_crtc;
3256 int active_crtc_cnt = 0;
3257
3258 for_each_intel_crtc(dev, intel_crtc) {
3259 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3260
3261 if (intel_crtc->base.state->active) {
3262 active_crtc_cnt++;
3263 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3264
3265 drrs_status_per_crtc(m, dev, intel_crtc);
3266 }
3267
3268 drm_modeset_unlock(&intel_crtc->base.mutex);
3269 }
3270
3271 if (!active_crtc_cnt)
3272 seq_puts(m, "No active crtc found\n");
3273
3274 return 0;
3275 }
3276
3277 struct pipe_crc_info {
3278 const char *name;
3279 struct drm_device *dev;
3280 enum pipe pipe;
3281 };
3282
3283 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3284 {
3285 struct drm_info_node *node = (struct drm_info_node *) m->private;
3286 struct drm_device *dev = node->minor->dev;
3287 struct drm_encoder *encoder;
3288 struct intel_encoder *intel_encoder;
3289 struct intel_digital_port *intel_dig_port;
3290 drm_modeset_lock_all(dev);
3291 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3292 intel_encoder = to_intel_encoder(encoder);
3293 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3294 continue;
3295 intel_dig_port = enc_to_dig_port(encoder);
3296 if (!intel_dig_port->dp.can_mst)
3297 continue;
3298
3299 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3300 }
3301 drm_modeset_unlock_all(dev);
3302 return 0;
3303 }
3304
3305 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3306 {
3307 struct pipe_crc_info *info = inode->i_private;
3308 struct drm_i915_private *dev_priv = info->dev->dev_private;
3309 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3310
3311 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3312 return -ENODEV;
3313
3314 spin_lock_irq(&pipe_crc->lock);
3315
3316 if (pipe_crc->opened) {
3317 spin_unlock_irq(&pipe_crc->lock);
3318 return -EBUSY; /* already open */
3319 }
3320
3321 pipe_crc->opened = true;
3322 filep->private_data = inode->i_private;
3323
3324 spin_unlock_irq(&pipe_crc->lock);
3325
3326 return 0;
3327 }
3328
3329 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3330 {
3331 struct pipe_crc_info *info = inode->i_private;
3332 struct drm_i915_private *dev_priv = info->dev->dev_private;
3333 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3334
3335 spin_lock_irq(&pipe_crc->lock);
3336 pipe_crc->opened = false;
3337 spin_unlock_irq(&pipe_crc->lock);
3338
3339 return 0;
3340 }
3341
3342 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3343 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3344 /* account for \'0' */
3345 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3346
3347 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3348 {
3349 assert_spin_locked(&pipe_crc->lock);
3350 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3351 INTEL_PIPE_CRC_ENTRIES_NR);
3352 }
3353
3354 static ssize_t
3355 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3356 loff_t *pos)
3357 {
3358 struct pipe_crc_info *info = filep->private_data;
3359 struct drm_device *dev = info->dev;
3360 struct drm_i915_private *dev_priv = dev->dev_private;
3361 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3362 char buf[PIPE_CRC_BUFFER_LEN];
3363 int n_entries;
3364 ssize_t bytes_read;
3365
3366 /*
3367 * Don't allow user space to provide buffers not big enough to hold
3368 * a line of data.
3369 */
3370 if (count < PIPE_CRC_LINE_LEN)
3371 return -EINVAL;
3372
3373 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3374 return 0;
3375
3376 /* nothing to read */
3377 spin_lock_irq(&pipe_crc->lock);
3378 while (pipe_crc_data_count(pipe_crc) == 0) {
3379 int ret;
3380
3381 if (filep->f_flags & O_NONBLOCK) {
3382 spin_unlock_irq(&pipe_crc->lock);
3383 return -EAGAIN;
3384 }
3385
3386 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3387 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3388 if (ret) {
3389 spin_unlock_irq(&pipe_crc->lock);
3390 return ret;
3391 }
3392 }
3393
3394 /* We now have one or more entries to read */
3395 n_entries = count / PIPE_CRC_LINE_LEN;
3396
3397 bytes_read = 0;
3398 while (n_entries > 0) {
3399 struct intel_pipe_crc_entry *entry =
3400 &pipe_crc->entries[pipe_crc->tail];
3401 int ret;
3402
3403 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3404 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3405 break;
3406
3407 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3408 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3409
3410 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3411 "%8u %8x %8x %8x %8x %8x\n",
3412 entry->frame, entry->crc[0],
3413 entry->crc[1], entry->crc[2],
3414 entry->crc[3], entry->crc[4]);
3415
3416 spin_unlock_irq(&pipe_crc->lock);
3417
3418 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
3419 if (ret == PIPE_CRC_LINE_LEN)
3420 return -EFAULT;
3421
3422 user_buf += PIPE_CRC_LINE_LEN;
3423 n_entries--;
3424
3425 spin_lock_irq(&pipe_crc->lock);
3426 }
3427
3428 spin_unlock_irq(&pipe_crc->lock);
3429
3430 return bytes_read;
3431 }
3432
3433 static const struct file_operations i915_pipe_crc_fops = {
3434 .owner = THIS_MODULE,
3435 .open = i915_pipe_crc_open,
3436 .read = i915_pipe_crc_read,
3437 .release = i915_pipe_crc_release,
3438 };
3439
3440 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3441 {
3442 .name = "i915_pipe_A_crc",
3443 .pipe = PIPE_A,
3444 },
3445 {
3446 .name = "i915_pipe_B_crc",
3447 .pipe = PIPE_B,
3448 },
3449 {
3450 .name = "i915_pipe_C_crc",
3451 .pipe = PIPE_C,
3452 },
3453 };
3454
3455 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3456 enum pipe pipe)
3457 {
3458 struct drm_device *dev = minor->dev;
3459 struct dentry *ent;
3460 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3461
3462 info->dev = dev;
3463 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3464 &i915_pipe_crc_fops);
3465 if (!ent)
3466 return -ENOMEM;
3467
3468 return drm_add_fake_info_node(minor, ent, info);
3469 }
3470
3471 static const char * const pipe_crc_sources[] = {
3472 "none",
3473 "plane1",
3474 "plane2",
3475 "pf",
3476 "pipe",
3477 "TV",
3478 "DP-B",
3479 "DP-C",
3480 "DP-D",
3481 "auto",
3482 };
3483
3484 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3485 {
3486 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3487 return pipe_crc_sources[source];
3488 }
3489
3490 static int display_crc_ctl_show(struct seq_file *m, void *data)
3491 {
3492 struct drm_device *dev = m->private;
3493 struct drm_i915_private *dev_priv = dev->dev_private;
3494 int i;
3495
3496 for (i = 0; i < I915_MAX_PIPES; i++)
3497 seq_printf(m, "%c %s\n", pipe_name(i),
3498 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3499
3500 return 0;
3501 }
3502
3503 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3504 {
3505 struct drm_device *dev = inode->i_private;
3506
3507 return single_open(file, display_crc_ctl_show, dev);
3508 }
3509
3510 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3511 uint32_t *val)
3512 {
3513 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3514 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3515
3516 switch (*source) {
3517 case INTEL_PIPE_CRC_SOURCE_PIPE:
3518 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3519 break;
3520 case INTEL_PIPE_CRC_SOURCE_NONE:
3521 *val = 0;
3522 break;
3523 default:
3524 return -EINVAL;
3525 }
3526
3527 return 0;
3528 }
3529
3530 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3531 enum intel_pipe_crc_source *source)
3532 {
3533 struct intel_encoder *encoder;
3534 struct intel_crtc *crtc;
3535 struct intel_digital_port *dig_port;
3536 int ret = 0;
3537
3538 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3539
3540 drm_modeset_lock_all(dev);
3541 for_each_intel_encoder(dev, encoder) {
3542 if (!encoder->base.crtc)
3543 continue;
3544
3545 crtc = to_intel_crtc(encoder->base.crtc);
3546
3547 if (crtc->pipe != pipe)
3548 continue;
3549
3550 switch (encoder->type) {
3551 case INTEL_OUTPUT_TVOUT:
3552 *source = INTEL_PIPE_CRC_SOURCE_TV;
3553 break;
3554 case INTEL_OUTPUT_DISPLAYPORT:
3555 case INTEL_OUTPUT_EDP:
3556 dig_port = enc_to_dig_port(&encoder->base);
3557 switch (dig_port->port) {
3558 case PORT_B:
3559 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3560 break;
3561 case PORT_C:
3562 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3563 break;
3564 case PORT_D:
3565 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3566 break;
3567 default:
3568 WARN(1, "nonexisting DP port %c\n",
3569 port_name(dig_port->port));
3570 break;
3571 }
3572 break;
3573 default:
3574 break;
3575 }
3576 }
3577 drm_modeset_unlock_all(dev);
3578
3579 return ret;
3580 }
3581
3582 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3583 enum pipe pipe,
3584 enum intel_pipe_crc_source *source,
3585 uint32_t *val)
3586 {
3587 struct drm_i915_private *dev_priv = dev->dev_private;
3588 bool need_stable_symbols = false;
3589
3590 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3591 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3592 if (ret)
3593 return ret;
3594 }
3595
3596 switch (*source) {
3597 case INTEL_PIPE_CRC_SOURCE_PIPE:
3598 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3599 break;
3600 case INTEL_PIPE_CRC_SOURCE_DP_B:
3601 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3602 need_stable_symbols = true;
3603 break;
3604 case INTEL_PIPE_CRC_SOURCE_DP_C:
3605 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3606 need_stable_symbols = true;
3607 break;
3608 case INTEL_PIPE_CRC_SOURCE_DP_D:
3609 if (!IS_CHERRYVIEW(dev))
3610 return -EINVAL;
3611 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3612 need_stable_symbols = true;
3613 break;
3614 case INTEL_PIPE_CRC_SOURCE_NONE:
3615 *val = 0;
3616 break;
3617 default:
3618 return -EINVAL;
3619 }
3620
3621 /*
3622 * When the pipe CRC tap point is after the transcoders we need
3623 * to tweak symbol-level features to produce a deterministic series of
3624 * symbols for a given frame. We need to reset those features only once
3625 * a frame (instead of every nth symbol):
3626 * - DC-balance: used to ensure a better clock recovery from the data
3627 * link (SDVO)
3628 * - DisplayPort scrambling: used for EMI reduction
3629 */
3630 if (need_stable_symbols) {
3631 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3632
3633 tmp |= DC_BALANCE_RESET_VLV;
3634 switch (pipe) {
3635 case PIPE_A:
3636 tmp |= PIPE_A_SCRAMBLE_RESET;
3637 break;
3638 case PIPE_B:
3639 tmp |= PIPE_B_SCRAMBLE_RESET;
3640 break;
3641 case PIPE_C:
3642 tmp |= PIPE_C_SCRAMBLE_RESET;
3643 break;
3644 default:
3645 return -EINVAL;
3646 }
3647 I915_WRITE(PORT_DFT2_G4X, tmp);
3648 }
3649
3650 return 0;
3651 }
3652
3653 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3654 enum pipe pipe,
3655 enum intel_pipe_crc_source *source,
3656 uint32_t *val)
3657 {
3658 struct drm_i915_private *dev_priv = dev->dev_private;
3659 bool need_stable_symbols = false;
3660
3661 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3662 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3663 if (ret)
3664 return ret;
3665 }
3666
3667 switch (*source) {
3668 case INTEL_PIPE_CRC_SOURCE_PIPE:
3669 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3670 break;
3671 case INTEL_PIPE_CRC_SOURCE_TV:
3672 if (!SUPPORTS_TV(dev))
3673 return -EINVAL;
3674 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3675 break;
3676 case INTEL_PIPE_CRC_SOURCE_DP_B:
3677 if (!IS_G4X(dev))
3678 return -EINVAL;
3679 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3680 need_stable_symbols = true;
3681 break;
3682 case INTEL_PIPE_CRC_SOURCE_DP_C:
3683 if (!IS_G4X(dev))
3684 return -EINVAL;
3685 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3686 need_stable_symbols = true;
3687 break;
3688 case INTEL_PIPE_CRC_SOURCE_DP_D:
3689 if (!IS_G4X(dev))
3690 return -EINVAL;
3691 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3692 need_stable_symbols = true;
3693 break;
3694 case INTEL_PIPE_CRC_SOURCE_NONE:
3695 *val = 0;
3696 break;
3697 default:
3698 return -EINVAL;
3699 }
3700
3701 /*
3702 * When the pipe CRC tap point is after the transcoders we need
3703 * to tweak symbol-level features to produce a deterministic series of
3704 * symbols for a given frame. We need to reset those features only once
3705 * a frame (instead of every nth symbol):
3706 * - DC-balance: used to ensure a better clock recovery from the data
3707 * link (SDVO)
3708 * - DisplayPort scrambling: used for EMI reduction
3709 */
3710 if (need_stable_symbols) {
3711 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3712
3713 WARN_ON(!IS_G4X(dev));
3714
3715 I915_WRITE(PORT_DFT_I9XX,
3716 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3717
3718 if (pipe == PIPE_A)
3719 tmp |= PIPE_A_SCRAMBLE_RESET;
3720 else
3721 tmp |= PIPE_B_SCRAMBLE_RESET;
3722
3723 I915_WRITE(PORT_DFT2_G4X, tmp);
3724 }
3725
3726 return 0;
3727 }
3728
3729 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3730 enum pipe pipe)
3731 {
3732 struct drm_i915_private *dev_priv = dev->dev_private;
3733 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3734
3735 switch (pipe) {
3736 case PIPE_A:
3737 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3738 break;
3739 case PIPE_B:
3740 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3741 break;
3742 case PIPE_C:
3743 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3744 break;
3745 default:
3746 return;
3747 }
3748 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3749 tmp &= ~DC_BALANCE_RESET_VLV;
3750 I915_WRITE(PORT_DFT2_G4X, tmp);
3751
3752 }
3753
3754 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3755 enum pipe pipe)
3756 {
3757 struct drm_i915_private *dev_priv = dev->dev_private;
3758 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3759
3760 if (pipe == PIPE_A)
3761 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3762 else
3763 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3764 I915_WRITE(PORT_DFT2_G4X, tmp);
3765
3766 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3767 I915_WRITE(PORT_DFT_I9XX,
3768 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3769 }
3770 }
3771
3772 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3773 uint32_t *val)
3774 {
3775 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3776 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3777
3778 switch (*source) {
3779 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3780 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3781 break;
3782 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3783 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3784 break;
3785 case INTEL_PIPE_CRC_SOURCE_PIPE:
3786 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3787 break;
3788 case INTEL_PIPE_CRC_SOURCE_NONE:
3789 *val = 0;
3790 break;
3791 default:
3792 return -EINVAL;
3793 }
3794
3795 return 0;
3796 }
3797
3798 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
3799 {
3800 struct drm_i915_private *dev_priv = dev->dev_private;
3801 struct intel_crtc *crtc =
3802 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3803 struct intel_crtc_state *pipe_config;
3804 struct drm_atomic_state *state;
3805 int ret = 0;
3806
3807 drm_modeset_lock_all(dev);
3808 state = drm_atomic_state_alloc(dev);
3809 if (!state) {
3810 ret = -ENOMEM;
3811 goto out;
3812 }
3813
3814 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
3815 pipe_config = intel_atomic_get_crtc_state(state, crtc);
3816 if (IS_ERR(pipe_config)) {
3817 ret = PTR_ERR(pipe_config);
3818 goto out;
3819 }
3820
3821 pipe_config->pch_pfit.force_thru = enable;
3822 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
3823 pipe_config->pch_pfit.enabled != enable)
3824 pipe_config->base.connectors_changed = true;
3825
3826 ret = drm_atomic_commit(state);
3827 out:
3828 drm_modeset_unlock_all(dev);
3829 WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
3830 if (ret)
3831 drm_atomic_state_free(state);
3832 }
3833
3834 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3835 enum pipe pipe,
3836 enum intel_pipe_crc_source *source,
3837 uint32_t *val)
3838 {
3839 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3840 *source = INTEL_PIPE_CRC_SOURCE_PF;
3841
3842 switch (*source) {
3843 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3844 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3845 break;
3846 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3847 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3848 break;
3849 case INTEL_PIPE_CRC_SOURCE_PF:
3850 if (IS_HASWELL(dev) && pipe == PIPE_A)
3851 hsw_trans_edp_pipe_A_crc_wa(dev, true);
3852
3853 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3854 break;
3855 case INTEL_PIPE_CRC_SOURCE_NONE:
3856 *val = 0;
3857 break;
3858 default:
3859 return -EINVAL;
3860 }
3861
3862 return 0;
3863 }
3864
3865 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3866 enum intel_pipe_crc_source source)
3867 {
3868 struct drm_i915_private *dev_priv = dev->dev_private;
3869 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3870 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3871 pipe));
3872 u32 val = 0; /* shut up gcc */
3873 int ret;
3874
3875 if (pipe_crc->source == source)
3876 return 0;
3877
3878 /* forbid changing the source without going back to 'none' */
3879 if (pipe_crc->source && source)
3880 return -EINVAL;
3881
3882 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3883 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3884 return -EIO;
3885 }
3886
3887 if (IS_GEN2(dev))
3888 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
3889 else if (INTEL_INFO(dev)->gen < 5)
3890 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3891 else if (IS_VALLEYVIEW(dev))
3892 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3893 else if (IS_GEN5(dev) || IS_GEN6(dev))
3894 ret = ilk_pipe_crc_ctl_reg(&source, &val);
3895 else
3896 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3897
3898 if (ret != 0)
3899 return ret;
3900
3901 /* none -> real source transition */
3902 if (source) {
3903 struct intel_pipe_crc_entry *entries;
3904
3905 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3906 pipe_name(pipe), pipe_crc_source_name(source));
3907
3908 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
3909 sizeof(pipe_crc->entries[0]),
3910 GFP_KERNEL);
3911 if (!entries)
3912 return -ENOMEM;
3913
3914 /*
3915 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3916 * enabled and disabled dynamically based on package C states,
3917 * user space can't make reliable use of the CRCs, so let's just
3918 * completely disable it.
3919 */
3920 hsw_disable_ips(crtc);
3921
3922 spin_lock_irq(&pipe_crc->lock);
3923 kfree(pipe_crc->entries);
3924 pipe_crc->entries = entries;
3925 pipe_crc->head = 0;
3926 pipe_crc->tail = 0;
3927 spin_unlock_irq(&pipe_crc->lock);
3928 }
3929
3930 pipe_crc->source = source;
3931
3932 I915_WRITE(PIPE_CRC_CTL(pipe), val);
3933 POSTING_READ(PIPE_CRC_CTL(pipe));
3934
3935 /* real source -> none transition */
3936 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
3937 struct intel_pipe_crc_entry *entries;
3938 struct intel_crtc *crtc =
3939 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3940
3941 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3942 pipe_name(pipe));
3943
3944 drm_modeset_lock(&crtc->base.mutex, NULL);
3945 if (crtc->base.state->active)
3946 intel_wait_for_vblank(dev, pipe);
3947 drm_modeset_unlock(&crtc->base.mutex);
3948
3949 spin_lock_irq(&pipe_crc->lock);
3950 entries = pipe_crc->entries;
3951 pipe_crc->entries = NULL;
3952 pipe_crc->head = 0;
3953 pipe_crc->tail = 0;
3954 spin_unlock_irq(&pipe_crc->lock);
3955
3956 kfree(entries);
3957
3958 if (IS_G4X(dev))
3959 g4x_undo_pipe_scramble_reset(dev, pipe);
3960 else if (IS_VALLEYVIEW(dev))
3961 vlv_undo_pipe_scramble_reset(dev, pipe);
3962 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3963 hsw_trans_edp_pipe_A_crc_wa(dev, false);
3964
3965 hsw_enable_ips(crtc);
3966 }
3967
3968 return 0;
3969 }
3970
3971 /*
3972 * Parse pipe CRC command strings:
3973 * command: wsp* object wsp+ name wsp+ source wsp*
3974 * object: 'pipe'
3975 * name: (A | B | C)
3976 * source: (none | plane1 | plane2 | pf)
3977 * wsp: (#0x20 | #0x9 | #0xA)+
3978 *
3979 * eg.:
3980 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3981 * "pipe A none" -> Stop CRC
3982 */
3983 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
3984 {
3985 int n_words = 0;
3986
3987 while (*buf) {
3988 char *end;
3989
3990 /* skip leading white space */
3991 buf = skip_spaces(buf);
3992 if (!*buf)
3993 break; /* end of buffer */
3994
3995 /* find end of word */
3996 for (end = buf; *end && !isspace(*end); end++)
3997 ;
3998
3999 if (n_words == max_words) {
4000 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4001 max_words);
4002 return -EINVAL; /* ran out of words[] before bytes */
4003 }
4004
4005 if (*end)
4006 *end++ = '\0';
4007 words[n_words++] = buf;
4008 buf = end;
4009 }
4010
4011 return n_words;
4012 }
4013
4014 enum intel_pipe_crc_object {
4015 PIPE_CRC_OBJECT_PIPE,
4016 };
4017
4018 static const char * const pipe_crc_objects[] = {
4019 "pipe",
4020 };
4021
4022 static int
4023 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4024 {
4025 int i;
4026
4027 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4028 if (!strcmp(buf, pipe_crc_objects[i])) {
4029 *o = i;
4030 return 0;
4031 }
4032
4033 return -EINVAL;
4034 }
4035
4036 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4037 {
4038 const char name = buf[0];
4039
4040 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4041 return -EINVAL;
4042
4043 *pipe = name - 'A';
4044
4045 return 0;
4046 }
4047
4048 static int
4049 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4050 {
4051 int i;
4052
4053 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4054 if (!strcmp(buf, pipe_crc_sources[i])) {
4055 *s = i;
4056 return 0;
4057 }
4058
4059 return -EINVAL;
4060 }
4061
4062 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
4063 {
4064 #define N_WORDS 3
4065 int n_words;
4066 char *words[N_WORDS];
4067 enum pipe pipe;
4068 enum intel_pipe_crc_object object;
4069 enum intel_pipe_crc_source source;
4070
4071 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4072 if (n_words != N_WORDS) {
4073 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4074 N_WORDS);
4075 return -EINVAL;
4076 }
4077
4078 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4079 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4080 return -EINVAL;
4081 }
4082
4083 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4084 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4085 return -EINVAL;
4086 }
4087
4088 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4089 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4090 return -EINVAL;
4091 }
4092
4093 return pipe_crc_set_source(dev, pipe, source);
4094 }
4095
4096 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4097 size_t len, loff_t *offp)
4098 {
4099 struct seq_file *m = file->private_data;
4100 struct drm_device *dev = m->private;
4101 char *tmpbuf;
4102 int ret;
4103
4104 if (len == 0)
4105 return 0;
4106
4107 if (len > PAGE_SIZE - 1) {
4108 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4109 PAGE_SIZE);
4110 return -E2BIG;
4111 }
4112
4113 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4114 if (!tmpbuf)
4115 return -ENOMEM;
4116
4117 if (copy_from_user(tmpbuf, ubuf, len)) {
4118 ret = -EFAULT;
4119 goto out;
4120 }
4121 tmpbuf[len] = '\0';
4122
4123 ret = display_crc_ctl_parse(dev, tmpbuf, len);
4124
4125 out:
4126 kfree(tmpbuf);
4127 if (ret < 0)
4128 return ret;
4129
4130 *offp += len;
4131 return len;
4132 }
4133
4134 static const struct file_operations i915_display_crc_ctl_fops = {
4135 .owner = THIS_MODULE,
4136 .open = display_crc_ctl_open,
4137 .read = seq_read,
4138 .llseek = seq_lseek,
4139 .release = single_release,
4140 .write = display_crc_ctl_write
4141 };
4142
4143 static ssize_t i915_displayport_test_active_write(struct file *file,
4144 const char __user *ubuf,
4145 size_t len, loff_t *offp)
4146 {
4147 char *input_buffer;
4148 int status = 0;
4149 struct drm_device *dev;
4150 struct drm_connector *connector;
4151 struct list_head *connector_list;
4152 struct intel_dp *intel_dp;
4153 int val = 0;
4154
4155 dev = ((struct seq_file *)file->private_data)->private;
4156
4157 connector_list = &dev->mode_config.connector_list;
4158
4159 if (len == 0)
4160 return 0;
4161
4162 input_buffer = kmalloc(len + 1, GFP_KERNEL);
4163 if (!input_buffer)
4164 return -ENOMEM;
4165
4166 if (copy_from_user(input_buffer, ubuf, len)) {
4167 status = -EFAULT;
4168 goto out;
4169 }
4170
4171 input_buffer[len] = '\0';
4172 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4173
4174 list_for_each_entry(connector, connector_list, head) {
4175
4176 if (connector->connector_type !=
4177 DRM_MODE_CONNECTOR_DisplayPort)
4178 continue;
4179
4180 if (connector->status == connector_status_connected &&
4181 connector->encoder != NULL) {
4182 intel_dp = enc_to_intel_dp(connector->encoder);
4183 status = kstrtoint(input_buffer, 10, &val);
4184 if (status < 0)
4185 goto out;
4186 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4187 /* To prevent erroneous activation of the compliance
4188 * testing code, only accept an actual value of 1 here
4189 */
4190 if (val == 1)
4191 intel_dp->compliance_test_active = 1;
4192 else
4193 intel_dp->compliance_test_active = 0;
4194 }
4195 }
4196 out:
4197 kfree(input_buffer);
4198 if (status < 0)
4199 return status;
4200
4201 *offp += len;
4202 return len;
4203 }
4204
4205 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4206 {
4207 struct drm_device *dev = m->private;
4208 struct drm_connector *connector;
4209 struct list_head *connector_list = &dev->mode_config.connector_list;
4210 struct intel_dp *intel_dp;
4211
4212 list_for_each_entry(connector, connector_list, head) {
4213
4214 if (connector->connector_type !=
4215 DRM_MODE_CONNECTOR_DisplayPort)
4216 continue;
4217
4218 if (connector->status == connector_status_connected &&
4219 connector->encoder != NULL) {
4220 intel_dp = enc_to_intel_dp(connector->encoder);
4221 if (intel_dp->compliance_test_active)
4222 seq_puts(m, "1");
4223 else
4224 seq_puts(m, "0");
4225 } else
4226 seq_puts(m, "0");
4227 }
4228
4229 return 0;
4230 }
4231
4232 static int i915_displayport_test_active_open(struct inode *inode,
4233 struct file *file)
4234 {
4235 struct drm_device *dev = inode->i_private;
4236
4237 return single_open(file, i915_displayport_test_active_show, dev);
4238 }
4239
4240 static const struct file_operations i915_displayport_test_active_fops = {
4241 .owner = THIS_MODULE,
4242 .open = i915_displayport_test_active_open,
4243 .read = seq_read,
4244 .llseek = seq_lseek,
4245 .release = single_release,
4246 .write = i915_displayport_test_active_write
4247 };
4248
4249 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4250 {
4251 struct drm_device *dev = m->private;
4252 struct drm_connector *connector;
4253 struct list_head *connector_list = &dev->mode_config.connector_list;
4254 struct intel_dp *intel_dp;
4255
4256 list_for_each_entry(connector, connector_list, head) {
4257
4258 if (connector->connector_type !=
4259 DRM_MODE_CONNECTOR_DisplayPort)
4260 continue;
4261
4262 if (connector->status == connector_status_connected &&
4263 connector->encoder != NULL) {
4264 intel_dp = enc_to_intel_dp(connector->encoder);
4265 seq_printf(m, "%lx", intel_dp->compliance_test_data);
4266 } else
4267 seq_puts(m, "0");
4268 }
4269
4270 return 0;
4271 }
4272 static int i915_displayport_test_data_open(struct inode *inode,
4273 struct file *file)
4274 {
4275 struct drm_device *dev = inode->i_private;
4276
4277 return single_open(file, i915_displayport_test_data_show, dev);
4278 }
4279
4280 static const struct file_operations i915_displayport_test_data_fops = {
4281 .owner = THIS_MODULE,
4282 .open = i915_displayport_test_data_open,
4283 .read = seq_read,
4284 .llseek = seq_lseek,
4285 .release = single_release
4286 };
4287
4288 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4289 {
4290 struct drm_device *dev = m->private;
4291 struct drm_connector *connector;
4292 struct list_head *connector_list = &dev->mode_config.connector_list;
4293 struct intel_dp *intel_dp;
4294
4295 list_for_each_entry(connector, connector_list, head) {
4296
4297 if (connector->connector_type !=
4298 DRM_MODE_CONNECTOR_DisplayPort)
4299 continue;
4300
4301 if (connector->status == connector_status_connected &&
4302 connector->encoder != NULL) {
4303 intel_dp = enc_to_intel_dp(connector->encoder);
4304 seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4305 } else
4306 seq_puts(m, "0");
4307 }
4308
4309 return 0;
4310 }
4311
4312 static int i915_displayport_test_type_open(struct inode *inode,
4313 struct file *file)
4314 {
4315 struct drm_device *dev = inode->i_private;
4316
4317 return single_open(file, i915_displayport_test_type_show, dev);
4318 }
4319
4320 static const struct file_operations i915_displayport_test_type_fops = {
4321 .owner = THIS_MODULE,
4322 .open = i915_displayport_test_type_open,
4323 .read = seq_read,
4324 .llseek = seq_lseek,
4325 .release = single_release
4326 };
4327
4328 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4329 {
4330 struct drm_device *dev = m->private;
4331 int level;
4332 int num_levels;
4333
4334 if (IS_CHERRYVIEW(dev))
4335 num_levels = 3;
4336 else if (IS_VALLEYVIEW(dev))
4337 num_levels = 1;
4338 else
4339 num_levels = ilk_wm_max_level(dev) + 1;
4340
4341 drm_modeset_lock_all(dev);
4342
4343 for (level = 0; level < num_levels; level++) {
4344 unsigned int latency = wm[level];
4345
4346 /*
4347 * - WM1+ latency values in 0.5us units
4348 * - latencies are in us on gen9/vlv/chv
4349 */
4350 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev))
4351 latency *= 10;
4352 else if (level > 0)
4353 latency *= 5;
4354
4355 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4356 level, wm[level], latency / 10, latency % 10);
4357 }
4358
4359 drm_modeset_unlock_all(dev);
4360 }
4361
4362 static int pri_wm_latency_show(struct seq_file *m, void *data)
4363 {
4364 struct drm_device *dev = m->private;
4365 struct drm_i915_private *dev_priv = dev->dev_private;
4366 const uint16_t *latencies;
4367
4368 if (INTEL_INFO(dev)->gen >= 9)
4369 latencies = dev_priv->wm.skl_latency;
4370 else
4371 latencies = to_i915(dev)->wm.pri_latency;
4372
4373 wm_latency_show(m, latencies);
4374
4375 return 0;
4376 }
4377
4378 static int spr_wm_latency_show(struct seq_file *m, void *data)
4379 {
4380 struct drm_device *dev = m->private;
4381 struct drm_i915_private *dev_priv = dev->dev_private;
4382 const uint16_t *latencies;
4383
4384 if (INTEL_INFO(dev)->gen >= 9)
4385 latencies = dev_priv->wm.skl_latency;
4386 else
4387 latencies = to_i915(dev)->wm.spr_latency;
4388
4389 wm_latency_show(m, latencies);
4390
4391 return 0;
4392 }
4393
4394 static int cur_wm_latency_show(struct seq_file *m, void *data)
4395 {
4396 struct drm_device *dev = m->private;
4397 struct drm_i915_private *dev_priv = dev->dev_private;
4398 const uint16_t *latencies;
4399
4400 if (INTEL_INFO(dev)->gen >= 9)
4401 latencies = dev_priv->wm.skl_latency;
4402 else
4403 latencies = to_i915(dev)->wm.cur_latency;
4404
4405 wm_latency_show(m, latencies);
4406
4407 return 0;
4408 }
4409
4410 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4411 {
4412 struct drm_device *dev = inode->i_private;
4413
4414 if (INTEL_INFO(dev)->gen < 5)
4415 return -ENODEV;
4416
4417 return single_open(file, pri_wm_latency_show, dev);
4418 }
4419
4420 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4421 {
4422 struct drm_device *dev = inode->i_private;
4423
4424 if (HAS_GMCH_DISPLAY(dev))
4425 return -ENODEV;
4426
4427 return single_open(file, spr_wm_latency_show, dev);
4428 }
4429
4430 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4431 {
4432 struct drm_device *dev = inode->i_private;
4433
4434 if (HAS_GMCH_DISPLAY(dev))
4435 return -ENODEV;
4436
4437 return single_open(file, cur_wm_latency_show, dev);
4438 }
4439
4440 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4441 size_t len, loff_t *offp, uint16_t wm[8])
4442 {
4443 struct seq_file *m = file->private_data;
4444 struct drm_device *dev = m->private;
4445 uint16_t new[8] = { 0 };
4446 int num_levels;
4447 int level;
4448 int ret;
4449 char tmp[32];
4450
4451 if (IS_CHERRYVIEW(dev))
4452 num_levels = 3;
4453 else if (IS_VALLEYVIEW(dev))
4454 num_levels = 1;
4455 else
4456 num_levels = ilk_wm_max_level(dev) + 1;
4457
4458 if (len >= sizeof(tmp))
4459 return -EINVAL;
4460
4461 if (copy_from_user(tmp, ubuf, len))
4462 return -EFAULT;
4463
4464 tmp[len] = '\0';
4465
4466 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4467 &new[0], &new[1], &new[2], &new[3],
4468 &new[4], &new[5], &new[6], &new[7]);
4469 if (ret != num_levels)
4470 return -EINVAL;
4471
4472 drm_modeset_lock_all(dev);
4473
4474 for (level = 0; level < num_levels; level++)
4475 wm[level] = new[level];
4476
4477 drm_modeset_unlock_all(dev);
4478
4479 return len;
4480 }
4481
4482
4483 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4484 size_t len, loff_t *offp)
4485 {
4486 struct seq_file *m = file->private_data;
4487 struct drm_device *dev = m->private;
4488 struct drm_i915_private *dev_priv = dev->dev_private;
4489 uint16_t *latencies;
4490
4491 if (INTEL_INFO(dev)->gen >= 9)
4492 latencies = dev_priv->wm.skl_latency;
4493 else
4494 latencies = to_i915(dev)->wm.pri_latency;
4495
4496 return wm_latency_write(file, ubuf, len, offp, latencies);
4497 }
4498
4499 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4500 size_t len, loff_t *offp)
4501 {
4502 struct seq_file *m = file->private_data;
4503 struct drm_device *dev = m->private;
4504 struct drm_i915_private *dev_priv = dev->dev_private;
4505 uint16_t *latencies;
4506
4507 if (INTEL_INFO(dev)->gen >= 9)
4508 latencies = dev_priv->wm.skl_latency;
4509 else
4510 latencies = to_i915(dev)->wm.spr_latency;
4511
4512 return wm_latency_write(file, ubuf, len, offp, latencies);
4513 }
4514
4515 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4516 size_t len, loff_t *offp)
4517 {
4518 struct seq_file *m = file->private_data;
4519 struct drm_device *dev = m->private;
4520 struct drm_i915_private *dev_priv = dev->dev_private;
4521 uint16_t *latencies;
4522
4523 if (INTEL_INFO(dev)->gen >= 9)
4524 latencies = dev_priv->wm.skl_latency;
4525 else
4526 latencies = to_i915(dev)->wm.cur_latency;
4527
4528 return wm_latency_write(file, ubuf, len, offp, latencies);
4529 }
4530
4531 static const struct file_operations i915_pri_wm_latency_fops = {
4532 .owner = THIS_MODULE,
4533 .open = pri_wm_latency_open,
4534 .read = seq_read,
4535 .llseek = seq_lseek,
4536 .release = single_release,
4537 .write = pri_wm_latency_write
4538 };
4539
4540 static const struct file_operations i915_spr_wm_latency_fops = {
4541 .owner = THIS_MODULE,
4542 .open = spr_wm_latency_open,
4543 .read = seq_read,
4544 .llseek = seq_lseek,
4545 .release = single_release,
4546 .write = spr_wm_latency_write
4547 };
4548
4549 static const struct file_operations i915_cur_wm_latency_fops = {
4550 .owner = THIS_MODULE,
4551 .open = cur_wm_latency_open,
4552 .read = seq_read,
4553 .llseek = seq_lseek,
4554 .release = single_release,
4555 .write = cur_wm_latency_write
4556 };
4557
4558 static int
4559 i915_wedged_get(void *data, u64 *val)
4560 {
4561 struct drm_device *dev = data;
4562 struct drm_i915_private *dev_priv = dev->dev_private;
4563
4564 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
4565
4566 return 0;
4567 }
4568
4569 static int
4570 i915_wedged_set(void *data, u64 val)
4571 {
4572 struct drm_device *dev = data;
4573 struct drm_i915_private *dev_priv = dev->dev_private;
4574
4575 /*
4576 * There is no safeguard against this debugfs entry colliding
4577 * with the hangcheck calling same i915_handle_error() in
4578 * parallel, causing an explosion. For now we assume that the
4579 * test harness is responsible enough not to inject gpu hangs
4580 * while it is writing to 'i915_wedged'
4581 */
4582
4583 if (i915_reset_in_progress(&dev_priv->gpu_error))
4584 return -EAGAIN;
4585
4586 intel_runtime_pm_get(dev_priv);
4587
4588 i915_handle_error(dev, val,
4589 "Manually setting wedged to %llu", val);
4590
4591 intel_runtime_pm_put(dev_priv);
4592
4593 return 0;
4594 }
4595
4596 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4597 i915_wedged_get, i915_wedged_set,
4598 "%llu\n");
4599
4600 static int
4601 i915_ring_stop_get(void *data, u64 *val)
4602 {
4603 struct drm_device *dev = data;
4604 struct drm_i915_private *dev_priv = dev->dev_private;
4605
4606 *val = dev_priv->gpu_error.stop_rings;
4607
4608 return 0;
4609 }
4610
4611 static int
4612 i915_ring_stop_set(void *data, u64 val)
4613 {
4614 struct drm_device *dev = data;
4615 struct drm_i915_private *dev_priv = dev->dev_private;
4616 int ret;
4617
4618 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
4619
4620 ret = mutex_lock_interruptible(&dev->struct_mutex);
4621 if (ret)
4622 return ret;
4623
4624 dev_priv->gpu_error.stop_rings = val;
4625 mutex_unlock(&dev->struct_mutex);
4626
4627 return 0;
4628 }
4629
4630 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4631 i915_ring_stop_get, i915_ring_stop_set,
4632 "0x%08llx\n");
4633
4634 static int
4635 i915_ring_missed_irq_get(void *data, u64 *val)
4636 {
4637 struct drm_device *dev = data;
4638 struct drm_i915_private *dev_priv = dev->dev_private;
4639
4640 *val = dev_priv->gpu_error.missed_irq_rings;
4641 return 0;
4642 }
4643
4644 static int
4645 i915_ring_missed_irq_set(void *data, u64 val)
4646 {
4647 struct drm_device *dev = data;
4648 struct drm_i915_private *dev_priv = dev->dev_private;
4649 int ret;
4650
4651 /* Lock against concurrent debugfs callers */
4652 ret = mutex_lock_interruptible(&dev->struct_mutex);
4653 if (ret)
4654 return ret;
4655 dev_priv->gpu_error.missed_irq_rings = val;
4656 mutex_unlock(&dev->struct_mutex);
4657
4658 return 0;
4659 }
4660
4661 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4662 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4663 "0x%08llx\n");
4664
4665 static int
4666 i915_ring_test_irq_get(void *data, u64 *val)
4667 {
4668 struct drm_device *dev = data;
4669 struct drm_i915_private *dev_priv = dev->dev_private;
4670
4671 *val = dev_priv->gpu_error.test_irq_rings;
4672
4673 return 0;
4674 }
4675
4676 static int
4677 i915_ring_test_irq_set(void *data, u64 val)
4678 {
4679 struct drm_device *dev = data;
4680 struct drm_i915_private *dev_priv = dev->dev_private;
4681 int ret;
4682
4683 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4684
4685 /* Lock against concurrent debugfs callers */
4686 ret = mutex_lock_interruptible(&dev->struct_mutex);
4687 if (ret)
4688 return ret;
4689
4690 dev_priv->gpu_error.test_irq_rings = val;
4691 mutex_unlock(&dev->struct_mutex);
4692
4693 return 0;
4694 }
4695
4696 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4697 i915_ring_test_irq_get, i915_ring_test_irq_set,
4698 "0x%08llx\n");
4699
4700 #define DROP_UNBOUND 0x1
4701 #define DROP_BOUND 0x2
4702 #define DROP_RETIRE 0x4
4703 #define DROP_ACTIVE 0x8
4704 #define DROP_ALL (DROP_UNBOUND | \
4705 DROP_BOUND | \
4706 DROP_RETIRE | \
4707 DROP_ACTIVE)
4708 static int
4709 i915_drop_caches_get(void *data, u64 *val)
4710 {
4711 *val = DROP_ALL;
4712
4713 return 0;
4714 }
4715
4716 static int
4717 i915_drop_caches_set(void *data, u64 val)
4718 {
4719 struct drm_device *dev = data;
4720 struct drm_i915_private *dev_priv = dev->dev_private;
4721 int ret;
4722
4723 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4724
4725 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4726 * on ioctls on -EAGAIN. */
4727 ret = mutex_lock_interruptible(&dev->struct_mutex);
4728 if (ret)
4729 return ret;
4730
4731 if (val & DROP_ACTIVE) {
4732 ret = i915_gpu_idle(dev);
4733 if (ret)
4734 goto unlock;
4735 }
4736
4737 if (val & (DROP_RETIRE | DROP_ACTIVE))
4738 i915_gem_retire_requests(dev);
4739
4740 if (val & DROP_BOUND)
4741 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4742
4743 if (val & DROP_UNBOUND)
4744 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4745
4746 unlock:
4747 mutex_unlock(&dev->struct_mutex);
4748
4749 return ret;
4750 }
4751
4752 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4753 i915_drop_caches_get, i915_drop_caches_set,
4754 "0x%08llx\n");
4755
4756 static int
4757 i915_max_freq_get(void *data, u64 *val)
4758 {
4759 struct drm_device *dev = data;
4760 struct drm_i915_private *dev_priv = dev->dev_private;
4761 int ret;
4762
4763 if (INTEL_INFO(dev)->gen < 6)
4764 return -ENODEV;
4765
4766 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4767
4768 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4769 if (ret)
4770 return ret;
4771
4772 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4773 mutex_unlock(&dev_priv->rps.hw_lock);
4774
4775 return 0;
4776 }
4777
4778 static int
4779 i915_max_freq_set(void *data, u64 val)
4780 {
4781 struct drm_device *dev = data;
4782 struct drm_i915_private *dev_priv = dev->dev_private;
4783 u32 hw_max, hw_min;
4784 int ret;
4785
4786 if (INTEL_INFO(dev)->gen < 6)
4787 return -ENODEV;
4788
4789 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4790
4791 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4792
4793 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4794 if (ret)
4795 return ret;
4796
4797 /*
4798 * Turbo will still be enabled, but won't go above the set value.
4799 */
4800 val = intel_freq_opcode(dev_priv, val);
4801
4802 hw_max = dev_priv->rps.max_freq;
4803 hw_min = dev_priv->rps.min_freq;
4804
4805 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4806 mutex_unlock(&dev_priv->rps.hw_lock);
4807 return -EINVAL;
4808 }
4809
4810 dev_priv->rps.max_freq_softlimit = val;
4811
4812 intel_set_rps(dev, val);
4813
4814 mutex_unlock(&dev_priv->rps.hw_lock);
4815
4816 return 0;
4817 }
4818
4819 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4820 i915_max_freq_get, i915_max_freq_set,
4821 "%llu\n");
4822
4823 static int
4824 i915_min_freq_get(void *data, u64 *val)
4825 {
4826 struct drm_device *dev = data;
4827 struct drm_i915_private *dev_priv = dev->dev_private;
4828 int ret;
4829
4830 if (INTEL_INFO(dev)->gen < 6)
4831 return -ENODEV;
4832
4833 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4834
4835 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4836 if (ret)
4837 return ret;
4838
4839 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4840 mutex_unlock(&dev_priv->rps.hw_lock);
4841
4842 return 0;
4843 }
4844
4845 static int
4846 i915_min_freq_set(void *data, u64 val)
4847 {
4848 struct drm_device *dev = data;
4849 struct drm_i915_private *dev_priv = dev->dev_private;
4850 u32 hw_max, hw_min;
4851 int ret;
4852
4853 if (INTEL_INFO(dev)->gen < 6)
4854 return -ENODEV;
4855
4856 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4857
4858 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4859
4860 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4861 if (ret)
4862 return ret;
4863
4864 /*
4865 * Turbo will still be enabled, but won't go below the set value.
4866 */
4867 val = intel_freq_opcode(dev_priv, val);
4868
4869 hw_max = dev_priv->rps.max_freq;
4870 hw_min = dev_priv->rps.min_freq;
4871
4872 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
4873 mutex_unlock(&dev_priv->rps.hw_lock);
4874 return -EINVAL;
4875 }
4876
4877 dev_priv->rps.min_freq_softlimit = val;
4878
4879 intel_set_rps(dev, val);
4880
4881 mutex_unlock(&dev_priv->rps.hw_lock);
4882
4883 return 0;
4884 }
4885
4886 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4887 i915_min_freq_get, i915_min_freq_set,
4888 "%llu\n");
4889
4890 static int
4891 i915_cache_sharing_get(void *data, u64 *val)
4892 {
4893 struct drm_device *dev = data;
4894 struct drm_i915_private *dev_priv = dev->dev_private;
4895 u32 snpcr;
4896 int ret;
4897
4898 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4899 return -ENODEV;
4900
4901 ret = mutex_lock_interruptible(&dev->struct_mutex);
4902 if (ret)
4903 return ret;
4904 intel_runtime_pm_get(dev_priv);
4905
4906 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4907
4908 intel_runtime_pm_put(dev_priv);
4909 mutex_unlock(&dev_priv->dev->struct_mutex);
4910
4911 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
4912
4913 return 0;
4914 }
4915
4916 static int
4917 i915_cache_sharing_set(void *data, u64 val)
4918 {
4919 struct drm_device *dev = data;
4920 struct drm_i915_private *dev_priv = dev->dev_private;
4921 u32 snpcr;
4922
4923 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4924 return -ENODEV;
4925
4926 if (val > 3)
4927 return -EINVAL;
4928
4929 intel_runtime_pm_get(dev_priv);
4930 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
4931
4932 /* Update the cache sharing policy here as well */
4933 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4934 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4935 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4936 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4937
4938 intel_runtime_pm_put(dev_priv);
4939 return 0;
4940 }
4941
4942 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4943 i915_cache_sharing_get, i915_cache_sharing_set,
4944 "%llu\n");
4945
4946 struct sseu_dev_status {
4947 unsigned int slice_total;
4948 unsigned int subslice_total;
4949 unsigned int subslice_per_slice;
4950 unsigned int eu_total;
4951 unsigned int eu_per_subslice;
4952 };
4953
4954 static void cherryview_sseu_device_status(struct drm_device *dev,
4955 struct sseu_dev_status *stat)
4956 {
4957 struct drm_i915_private *dev_priv = dev->dev_private;
4958 int ss_max = 2;
4959 int ss;
4960 u32 sig1[ss_max], sig2[ss_max];
4961
4962 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
4963 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
4964 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
4965 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
4966
4967 for (ss = 0; ss < ss_max; ss++) {
4968 unsigned int eu_cnt;
4969
4970 if (sig1[ss] & CHV_SS_PG_ENABLE)
4971 /* skip disabled subslice */
4972 continue;
4973
4974 stat->slice_total = 1;
4975 stat->subslice_per_slice++;
4976 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
4977 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
4978 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
4979 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
4980 stat->eu_total += eu_cnt;
4981 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
4982 }
4983 stat->subslice_total = stat->subslice_per_slice;
4984 }
4985
4986 static void gen9_sseu_device_status(struct drm_device *dev,
4987 struct sseu_dev_status *stat)
4988 {
4989 struct drm_i915_private *dev_priv = dev->dev_private;
4990 int s_max = 3, ss_max = 4;
4991 int s, ss;
4992 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
4993
4994 /* BXT has a single slice and at most 3 subslices. */
4995 if (IS_BROXTON(dev)) {
4996 s_max = 1;
4997 ss_max = 3;
4998 }
4999
5000 for (s = 0; s < s_max; s++) {
5001 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5002 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5003 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5004 }
5005
5006 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5007 GEN9_PGCTL_SSA_EU19_ACK |
5008 GEN9_PGCTL_SSA_EU210_ACK |
5009 GEN9_PGCTL_SSA_EU311_ACK;
5010 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5011 GEN9_PGCTL_SSB_EU19_ACK |
5012 GEN9_PGCTL_SSB_EU210_ACK |
5013 GEN9_PGCTL_SSB_EU311_ACK;
5014
5015 for (s = 0; s < s_max; s++) {
5016 unsigned int ss_cnt = 0;
5017
5018 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5019 /* skip disabled slice */
5020 continue;
5021
5022 stat->slice_total++;
5023
5024 if (IS_SKYLAKE(dev))
5025 ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
5026
5027 for (ss = 0; ss < ss_max; ss++) {
5028 unsigned int eu_cnt;
5029
5030 if (IS_BROXTON(dev) &&
5031 !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5032 /* skip disabled subslice */
5033 continue;
5034
5035 if (IS_BROXTON(dev))
5036 ss_cnt++;
5037
5038 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5039 eu_mask[ss%2]);
5040 stat->eu_total += eu_cnt;
5041 stat->eu_per_subslice = max(stat->eu_per_subslice,
5042 eu_cnt);
5043 }
5044
5045 stat->subslice_total += ss_cnt;
5046 stat->subslice_per_slice = max(stat->subslice_per_slice,
5047 ss_cnt);
5048 }
5049 }
5050
5051 static void broadwell_sseu_device_status(struct drm_device *dev,
5052 struct sseu_dev_status *stat)
5053 {
5054 struct drm_i915_private *dev_priv = dev->dev_private;
5055 int s;
5056 u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5057
5058 stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK);
5059
5060 if (stat->slice_total) {
5061 stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice;
5062 stat->subslice_total = stat->slice_total *
5063 stat->subslice_per_slice;
5064 stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice;
5065 stat->eu_total = stat->eu_per_subslice * stat->subslice_total;
5066
5067 /* subtract fused off EU(s) from enabled slice(s) */
5068 for (s = 0; s < stat->slice_total; s++) {
5069 u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s];
5070
5071 stat->eu_total -= hweight8(subslice_7eu);
5072 }
5073 }
5074 }
5075
5076 static int i915_sseu_status(struct seq_file *m, void *unused)
5077 {
5078 struct drm_info_node *node = (struct drm_info_node *) m->private;
5079 struct drm_device *dev = node->minor->dev;
5080 struct sseu_dev_status stat;
5081
5082 if (INTEL_INFO(dev)->gen < 8)
5083 return -ENODEV;
5084
5085 seq_puts(m, "SSEU Device Info\n");
5086 seq_printf(m, " Available Slice Total: %u\n",
5087 INTEL_INFO(dev)->slice_total);
5088 seq_printf(m, " Available Subslice Total: %u\n",
5089 INTEL_INFO(dev)->subslice_total);
5090 seq_printf(m, " Available Subslice Per Slice: %u\n",
5091 INTEL_INFO(dev)->subslice_per_slice);
5092 seq_printf(m, " Available EU Total: %u\n",
5093 INTEL_INFO(dev)->eu_total);
5094 seq_printf(m, " Available EU Per Subslice: %u\n",
5095 INTEL_INFO(dev)->eu_per_subslice);
5096 seq_printf(m, " Has Slice Power Gating: %s\n",
5097 yesno(INTEL_INFO(dev)->has_slice_pg));
5098 seq_printf(m, " Has Subslice Power Gating: %s\n",
5099 yesno(INTEL_INFO(dev)->has_subslice_pg));
5100 seq_printf(m, " Has EU Power Gating: %s\n",
5101 yesno(INTEL_INFO(dev)->has_eu_pg));
5102
5103 seq_puts(m, "SSEU Device Status\n");
5104 memset(&stat, 0, sizeof(stat));
5105 if (IS_CHERRYVIEW(dev)) {
5106 cherryview_sseu_device_status(dev, &stat);
5107 } else if (IS_BROADWELL(dev)) {
5108 broadwell_sseu_device_status(dev, &stat);
5109 } else if (INTEL_INFO(dev)->gen >= 9) {
5110 gen9_sseu_device_status(dev, &stat);
5111 }
5112 seq_printf(m, " Enabled Slice Total: %u\n",
5113 stat.slice_total);
5114 seq_printf(m, " Enabled Subslice Total: %u\n",
5115 stat.subslice_total);
5116 seq_printf(m, " Enabled Subslice Per Slice: %u\n",
5117 stat.subslice_per_slice);
5118 seq_printf(m, " Enabled EU Total: %u\n",
5119 stat.eu_total);
5120 seq_printf(m, " Enabled EU Per Subslice: %u\n",
5121 stat.eu_per_subslice);
5122
5123 return 0;
5124 }
5125
5126 static int i915_forcewake_open(struct inode *inode, struct file *file)
5127 {
5128 struct drm_device *dev = inode->i_private;
5129 struct drm_i915_private *dev_priv = dev->dev_private;
5130
5131 if (INTEL_INFO(dev)->gen < 6)
5132 return 0;
5133
5134 intel_runtime_pm_get(dev_priv);
5135 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5136
5137 return 0;
5138 }
5139
5140 static int i915_forcewake_release(struct inode *inode, struct file *file)
5141 {
5142 struct drm_device *dev = inode->i_private;
5143 struct drm_i915_private *dev_priv = dev->dev_private;
5144
5145 if (INTEL_INFO(dev)->gen < 6)
5146 return 0;
5147
5148 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5149 intel_runtime_pm_put(dev_priv);
5150
5151 return 0;
5152 }
5153
5154 static const struct file_operations i915_forcewake_fops = {
5155 .owner = THIS_MODULE,
5156 .open = i915_forcewake_open,
5157 .release = i915_forcewake_release,
5158 };
5159
5160 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5161 {
5162 struct drm_device *dev = minor->dev;
5163 struct dentry *ent;
5164
5165 ent = debugfs_create_file("i915_forcewake_user",
5166 S_IRUSR,
5167 root, dev,
5168 &i915_forcewake_fops);
5169 if (!ent)
5170 return -ENOMEM;
5171
5172 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5173 }
5174
5175 static int i915_debugfs_create(struct dentry *root,
5176 struct drm_minor *minor,
5177 const char *name,
5178 const struct file_operations *fops)
5179 {
5180 struct drm_device *dev = minor->dev;
5181 struct dentry *ent;
5182
5183 ent = debugfs_create_file(name,
5184 S_IRUGO | S_IWUSR,
5185 root, dev,
5186 fops);
5187 if (!ent)
5188 return -ENOMEM;
5189
5190 return drm_add_fake_info_node(minor, ent, fops);
5191 }
5192
5193 static const struct drm_info_list i915_debugfs_list[] = {
5194 {"i915_capabilities", i915_capabilities, 0},
5195 {"i915_gem_objects", i915_gem_object_info, 0},
5196 {"i915_gem_gtt", i915_gem_gtt_info, 0},
5197 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
5198 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
5199 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
5200 {"i915_gem_stolen", i915_gem_stolen_list_info },
5201 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5202 {"i915_gem_request", i915_gem_request_info, 0},
5203 {"i915_gem_seqno", i915_gem_seqno_info, 0},
5204 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5205 {"i915_gem_interrupt", i915_interrupt_info, 0},
5206 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5207 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5208 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5209 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5210 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5211 {"i915_guc_info", i915_guc_info, 0},
5212 {"i915_guc_load_status", i915_guc_load_status_info, 0},
5213 {"i915_guc_log_dump", i915_guc_log_dump, 0},
5214 {"i915_frequency_info", i915_frequency_info, 0},
5215 {"i915_hangcheck_info", i915_hangcheck_info, 0},
5216 {"i915_drpc_info", i915_drpc_info, 0},
5217 {"i915_emon_status", i915_emon_status, 0},
5218 {"i915_ring_freq_table", i915_ring_freq_table, 0},
5219 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5220 {"i915_fbc_status", i915_fbc_status, 0},
5221 {"i915_ips_status", i915_ips_status, 0},
5222 {"i915_sr_status", i915_sr_status, 0},
5223 {"i915_opregion", i915_opregion, 0},
5224 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5225 {"i915_context_status", i915_context_status, 0},
5226 {"i915_dump_lrc", i915_dump_lrc, 0},
5227 {"i915_execlists", i915_execlists, 0},
5228 {"i915_forcewake_domains", i915_forcewake_domains, 0},
5229 {"i915_swizzle_info", i915_swizzle_info, 0},
5230 {"i915_ppgtt_info", i915_ppgtt_info, 0},
5231 {"i915_llc", i915_llc, 0},
5232 {"i915_edp_psr_status", i915_edp_psr_status, 0},
5233 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5234 {"i915_energy_uJ", i915_energy_uJ, 0},
5235 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5236 {"i915_power_domain_info", i915_power_domain_info, 0},
5237 {"i915_display_info", i915_display_info, 0},
5238 {"i915_semaphore_status", i915_semaphore_status, 0},
5239 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5240 {"i915_dp_mst_info", i915_dp_mst_info, 0},
5241 {"i915_wa_registers", i915_wa_registers, 0},
5242 {"i915_ddb_info", i915_ddb_info, 0},
5243 {"i915_sseu_status", i915_sseu_status, 0},
5244 {"i915_drrs_status", i915_drrs_status, 0},
5245 {"i915_rps_boost_info", i915_rps_boost_info, 0},
5246 };
5247 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5248
5249 static const struct i915_debugfs_files {
5250 const char *name;
5251 const struct file_operations *fops;
5252 } i915_debugfs_files[] = {
5253 {"i915_wedged", &i915_wedged_fops},
5254 {"i915_max_freq", &i915_max_freq_fops},
5255 {"i915_min_freq", &i915_min_freq_fops},
5256 {"i915_cache_sharing", &i915_cache_sharing_fops},
5257 {"i915_ring_stop", &i915_ring_stop_fops},
5258 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5259 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5260 {"i915_gem_drop_caches", &i915_drop_caches_fops},
5261 {"i915_error_state", &i915_error_state_fops},
5262 {"i915_next_seqno", &i915_next_seqno_fops},
5263 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5264 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5265 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5266 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5267 {"i915_fbc_false_color", &i915_fbc_fc_fops},
5268 {"i915_dp_test_data", &i915_displayport_test_data_fops},
5269 {"i915_dp_test_type", &i915_displayport_test_type_fops},
5270 {"i915_dp_test_active", &i915_displayport_test_active_fops}
5271 };
5272
5273 void intel_display_crc_init(struct drm_device *dev)
5274 {
5275 struct drm_i915_private *dev_priv = dev->dev_private;
5276 enum pipe pipe;
5277
5278 for_each_pipe(dev_priv, pipe) {
5279 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5280
5281 pipe_crc->opened = false;
5282 spin_lock_init(&pipe_crc->lock);
5283 init_waitqueue_head(&pipe_crc->wq);
5284 }
5285 }
5286
5287 int i915_debugfs_init(struct drm_minor *minor)
5288 {
5289 int ret, i;
5290
5291 ret = i915_forcewake_create(minor->debugfs_root, minor);
5292 if (ret)
5293 return ret;
5294
5295 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5296 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5297 if (ret)
5298 return ret;
5299 }
5300
5301 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5302 ret = i915_debugfs_create(minor->debugfs_root, minor,
5303 i915_debugfs_files[i].name,
5304 i915_debugfs_files[i].fops);
5305 if (ret)
5306 return ret;
5307 }
5308
5309 return drm_debugfs_create_files(i915_debugfs_list,
5310 I915_DEBUGFS_ENTRIES,
5311 minor->debugfs_root, minor);
5312 }
5313
5314 void i915_debugfs_cleanup(struct drm_minor *minor)
5315 {
5316 int i;
5317
5318 drm_debugfs_remove_files(i915_debugfs_list,
5319 I915_DEBUGFS_ENTRIES, minor);
5320
5321 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5322 1, minor);
5323
5324 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5325 struct drm_info_list *info_list =
5326 (struct drm_info_list *)&i915_pipe_crc_data[i];
5327
5328 drm_debugfs_remove_files(info_list, 1, minor);
5329 }
5330
5331 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5332 struct drm_info_list *info_list =
5333 (struct drm_info_list *) i915_debugfs_files[i].fops;
5334
5335 drm_debugfs_remove_files(info_list, 1, minor);
5336 }
5337 }
5338
5339 struct dpcd_block {
5340 /* DPCD dump start address. */
5341 unsigned int offset;
5342 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5343 unsigned int end;
5344 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5345 size_t size;
5346 /* Only valid for eDP. */
5347 bool edp;
5348 };
5349
5350 static const struct dpcd_block i915_dpcd_debug[] = {
5351 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5352 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5353 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5354 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5355 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5356 { .offset = DP_SET_POWER },
5357 { .offset = DP_EDP_DPCD_REV },
5358 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5359 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5360 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5361 };
5362
5363 static int i915_dpcd_show(struct seq_file *m, void *data)
5364 {
5365 struct drm_connector *connector = m->private;
5366 struct intel_dp *intel_dp =
5367 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5368 uint8_t buf[16];
5369 ssize_t err;
5370 int i;
5371
5372 if (connector->status != connector_status_connected)
5373 return -ENODEV;
5374
5375 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5376 const struct dpcd_block *b = &i915_dpcd_debug[i];
5377 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5378
5379 if (b->edp &&
5380 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5381 continue;
5382
5383 /* low tech for now */
5384 if (WARN_ON(size > sizeof(buf)))
5385 continue;
5386
5387 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5388 if (err <= 0) {
5389 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5390 size, b->offset, err);
5391 continue;
5392 }
5393
5394 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5395 }
5396
5397 return 0;
5398 }
5399
5400 static int i915_dpcd_open(struct inode *inode, struct file *file)
5401 {
5402 return single_open(file, i915_dpcd_show, inode->i_private);
5403 }
5404
5405 static const struct file_operations i915_dpcd_fops = {
5406 .owner = THIS_MODULE,
5407 .open = i915_dpcd_open,
5408 .read = seq_read,
5409 .llseek = seq_lseek,
5410 .release = single_release,
5411 };
5412
5413 /**
5414 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5415 * @connector: pointer to a registered drm_connector
5416 *
5417 * Cleanup will be done by drm_connector_unregister() through a call to
5418 * drm_debugfs_connector_remove().
5419 *
5420 * Returns 0 on success, negative error codes on error.
5421 */
5422 int i915_debugfs_connector_add(struct drm_connector *connector)
5423 {
5424 struct dentry *root = connector->debugfs_entry;
5425
5426 /* The connector must have been registered beforehands. */
5427 if (!root)
5428 return -ENODEV;
5429
5430 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5431 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5432 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5433 &i915_dpcd_fops);
5434
5435 return 0;
5436 }
Linux kernel - Deliverables
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