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[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
37 #include <drm/drmP.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
41 #include "i915_drv.h"
42
43 enum {
44 ACTIVE_LIST,
45 INACTIVE_LIST,
46 PINNED_LIST,
47 };
48
49 /* As the drm_debugfs_init() routines are called before dev->dev_private is
50 * allocated we need to hook into the minor for release. */
51 static int
52 drm_add_fake_info_node(struct drm_minor *minor,
53 struct dentry *ent,
54 const void *key)
55 {
56 struct drm_info_node *node;
57
58 node = kmalloc(sizeof(*node), GFP_KERNEL);
59 if (node == NULL) {
60 debugfs_remove(ent);
61 return -ENOMEM;
62 }
63
64 node->minor = minor;
65 node->dent = ent;
66 node->info_ent = (void *) key;
67
68 mutex_lock(&minor->debugfs_lock);
69 list_add(&node->list, &minor->debugfs_list);
70 mutex_unlock(&minor->debugfs_lock);
71
72 return 0;
73 }
74
75 static int i915_capabilities(struct seq_file *m, void *data)
76 {
77 struct drm_info_node *node = m->private;
78 struct drm_device *dev = node->minor->dev;
79 const struct intel_device_info *info = INTEL_INFO(dev);
80
81 seq_printf(m, "gen: %d\n", info->gen);
82 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
83 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
84 #define SEP_SEMICOLON ;
85 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
86 #undef PRINT_FLAG
87 #undef SEP_SEMICOLON
88
89 return 0;
90 }
91
92 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
93 {
94 if (obj->pin_display)
95 return "p";
96 else
97 return " ";
98 }
99
100 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
101 {
102 switch (obj->tiling_mode) {
103 default:
104 case I915_TILING_NONE: return " ";
105 case I915_TILING_X: return "X";
106 case I915_TILING_Y: return "Y";
107 }
108 }
109
110 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
111 {
112 return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
113 }
114
115 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
116 {
117 u64 size = 0;
118 struct i915_vma *vma;
119
120 list_for_each_entry(vma, &obj->vma_list, obj_link) {
121 if (vma->is_ggtt && drm_mm_node_allocated(&vma->node))
122 size += vma->node.size;
123 }
124
125 return size;
126 }
127
128 static void
129 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
130 {
131 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
132 struct intel_engine_cs *engine;
133 struct i915_vma *vma;
134 int pin_count = 0;
135 enum intel_engine_id id;
136
137 lockdep_assert_held(&obj->base.dev->struct_mutex);
138
139 seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ",
140 &obj->base,
141 obj->active ? "*" : " ",
142 get_pin_flag(obj),
143 get_tiling_flag(obj),
144 get_global_flag(obj),
145 obj->base.size / 1024,
146 obj->base.read_domains,
147 obj->base.write_domain);
148 for_each_engine_id(engine, dev_priv, id)
149 seq_printf(m, "%x ",
150 i915_gem_request_get_seqno(obj->last_read_req[id]));
151 seq_printf(m, "] %x %x%s%s%s",
152 i915_gem_request_get_seqno(obj->last_write_req),
153 i915_gem_request_get_seqno(obj->last_fenced_req),
154 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
155 obj->dirty ? " dirty" : "",
156 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
157 if (obj->base.name)
158 seq_printf(m, " (name: %d)", obj->base.name);
159 list_for_each_entry(vma, &obj->vma_list, obj_link) {
160 if (vma->pin_count > 0)
161 pin_count++;
162 }
163 seq_printf(m, " (pinned x %d)", pin_count);
164 if (obj->pin_display)
165 seq_printf(m, " (display)");
166 if (obj->fence_reg != I915_FENCE_REG_NONE)
167 seq_printf(m, " (fence: %d)", obj->fence_reg);
168 list_for_each_entry(vma, &obj->vma_list, obj_link) {
169 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
170 vma->is_ggtt ? "g" : "pp",
171 vma->node.start, vma->node.size);
172 if (vma->is_ggtt)
173 seq_printf(m, ", type: %u", vma->ggtt_view.type);
174 seq_puts(m, ")");
175 }
176 if (obj->stolen)
177 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
178 if (obj->pin_display || obj->fault_mappable) {
179 char s[3], *t = s;
180 if (obj->pin_display)
181 *t++ = 'p';
182 if (obj->fault_mappable)
183 *t++ = 'f';
184 *t = '\0';
185 seq_printf(m, " (%s mappable)", s);
186 }
187 if (obj->last_write_req != NULL)
188 seq_printf(m, " (%s)",
189 i915_gem_request_get_engine(obj->last_write_req)->name);
190 if (obj->frontbuffer_bits)
191 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
192 }
193
194 static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
195 {
196 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
197 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
198 seq_putc(m, ' ');
199 }
200
201 static int i915_gem_object_list_info(struct seq_file *m, void *data)
202 {
203 struct drm_info_node *node = m->private;
204 uintptr_t list = (uintptr_t) node->info_ent->data;
205 struct list_head *head;
206 struct drm_device *dev = node->minor->dev;
207 struct drm_i915_private *dev_priv = to_i915(dev);
208 struct i915_ggtt *ggtt = &dev_priv->ggtt;
209 struct i915_vma *vma;
210 u64 total_obj_size, total_gtt_size;
211 int count, ret;
212
213 ret = mutex_lock_interruptible(&dev->struct_mutex);
214 if (ret)
215 return ret;
216
217 /* FIXME: the user of this interface might want more than just GGTT */
218 switch (list) {
219 case ACTIVE_LIST:
220 seq_puts(m, "Active:\n");
221 head = &ggtt->base.active_list;
222 break;
223 case INACTIVE_LIST:
224 seq_puts(m, "Inactive:\n");
225 head = &ggtt->base.inactive_list;
226 break;
227 default:
228 mutex_unlock(&dev->struct_mutex);
229 return -EINVAL;
230 }
231
232 total_obj_size = total_gtt_size = count = 0;
233 list_for_each_entry(vma, head, vm_link) {
234 seq_printf(m, " ");
235 describe_obj(m, vma->obj);
236 seq_printf(m, "\n");
237 total_obj_size += vma->obj->base.size;
238 total_gtt_size += vma->node.size;
239 count++;
240 }
241 mutex_unlock(&dev->struct_mutex);
242
243 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
244 count, total_obj_size, total_gtt_size);
245 return 0;
246 }
247
248 static int obj_rank_by_stolen(void *priv,
249 struct list_head *A, struct list_head *B)
250 {
251 struct drm_i915_gem_object *a =
252 container_of(A, struct drm_i915_gem_object, obj_exec_link);
253 struct drm_i915_gem_object *b =
254 container_of(B, struct drm_i915_gem_object, obj_exec_link);
255
256 if (a->stolen->start < b->stolen->start)
257 return -1;
258 if (a->stolen->start > b->stolen->start)
259 return 1;
260 return 0;
261 }
262
263 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
264 {
265 struct drm_info_node *node = m->private;
266 struct drm_device *dev = node->minor->dev;
267 struct drm_i915_private *dev_priv = dev->dev_private;
268 struct drm_i915_gem_object *obj;
269 u64 total_obj_size, total_gtt_size;
270 LIST_HEAD(stolen);
271 int count, ret;
272
273 ret = mutex_lock_interruptible(&dev->struct_mutex);
274 if (ret)
275 return ret;
276
277 total_obj_size = total_gtt_size = count = 0;
278 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
279 if (obj->stolen == NULL)
280 continue;
281
282 list_add(&obj->obj_exec_link, &stolen);
283
284 total_obj_size += obj->base.size;
285 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
286 count++;
287 }
288 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
289 if (obj->stolen == NULL)
290 continue;
291
292 list_add(&obj->obj_exec_link, &stolen);
293
294 total_obj_size += obj->base.size;
295 count++;
296 }
297 list_sort(NULL, &stolen, obj_rank_by_stolen);
298 seq_puts(m, "Stolen:\n");
299 while (!list_empty(&stolen)) {
300 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
301 seq_puts(m, " ");
302 describe_obj(m, obj);
303 seq_putc(m, '\n');
304 list_del_init(&obj->obj_exec_link);
305 }
306 mutex_unlock(&dev->struct_mutex);
307
308 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
309 count, total_obj_size, total_gtt_size);
310 return 0;
311 }
312
313 #define count_objects(list, member) do { \
314 list_for_each_entry(obj, list, member) { \
315 size += i915_gem_obj_total_ggtt_size(obj); \
316 ++count; \
317 if (obj->map_and_fenceable) { \
318 mappable_size += i915_gem_obj_ggtt_size(obj); \
319 ++mappable_count; \
320 } \
321 } \
322 } while (0)
323
324 struct file_stats {
325 struct drm_i915_file_private *file_priv;
326 unsigned long count;
327 u64 total, unbound;
328 u64 global, shared;
329 u64 active, inactive;
330 };
331
332 static int per_file_stats(int id, void *ptr, void *data)
333 {
334 struct drm_i915_gem_object *obj = ptr;
335 struct file_stats *stats = data;
336 struct i915_vma *vma;
337
338 stats->count++;
339 stats->total += obj->base.size;
340
341 if (obj->base.name || obj->base.dma_buf)
342 stats->shared += obj->base.size;
343
344 if (USES_FULL_PPGTT(obj->base.dev)) {
345 list_for_each_entry(vma, &obj->vma_list, obj_link) {
346 struct i915_hw_ppgtt *ppgtt;
347
348 if (!drm_mm_node_allocated(&vma->node))
349 continue;
350
351 if (vma->is_ggtt) {
352 stats->global += obj->base.size;
353 continue;
354 }
355
356 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
357 if (ppgtt->file_priv != stats->file_priv)
358 continue;
359
360 if (obj->active) /* XXX per-vma statistic */
361 stats->active += obj->base.size;
362 else
363 stats->inactive += obj->base.size;
364
365 return 0;
366 }
367 } else {
368 if (i915_gem_obj_ggtt_bound(obj)) {
369 stats->global += obj->base.size;
370 if (obj->active)
371 stats->active += obj->base.size;
372 else
373 stats->inactive += obj->base.size;
374 return 0;
375 }
376 }
377
378 if (!list_empty(&obj->global_list))
379 stats->unbound += obj->base.size;
380
381 return 0;
382 }
383
384 #define print_file_stats(m, name, stats) do { \
385 if (stats.count) \
386 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
387 name, \
388 stats.count, \
389 stats.total, \
390 stats.active, \
391 stats.inactive, \
392 stats.global, \
393 stats.shared, \
394 stats.unbound); \
395 } while (0)
396
397 static void print_batch_pool_stats(struct seq_file *m,
398 struct drm_i915_private *dev_priv)
399 {
400 struct drm_i915_gem_object *obj;
401 struct file_stats stats;
402 struct intel_engine_cs *engine;
403 int j;
404
405 memset(&stats, 0, sizeof(stats));
406
407 for_each_engine(engine, dev_priv) {
408 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
409 list_for_each_entry(obj,
410 &engine->batch_pool.cache_list[j],
411 batch_pool_link)
412 per_file_stats(0, obj, &stats);
413 }
414 }
415
416 print_file_stats(m, "[k]batch pool", stats);
417 }
418
419 #define count_vmas(list, member) do { \
420 list_for_each_entry(vma, list, member) { \
421 size += i915_gem_obj_total_ggtt_size(vma->obj); \
422 ++count; \
423 if (vma->obj->map_and_fenceable) { \
424 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
425 ++mappable_count; \
426 } \
427 } \
428 } while (0)
429
430 static int i915_gem_object_info(struct seq_file *m, void* data)
431 {
432 struct drm_info_node *node = m->private;
433 struct drm_device *dev = node->minor->dev;
434 struct drm_i915_private *dev_priv = to_i915(dev);
435 struct i915_ggtt *ggtt = &dev_priv->ggtt;
436 u32 count, mappable_count, purgeable_count;
437 u64 size, mappable_size, purgeable_size;
438 struct drm_i915_gem_object *obj;
439 struct drm_file *file;
440 struct i915_vma *vma;
441 int ret;
442
443 ret = mutex_lock_interruptible(&dev->struct_mutex);
444 if (ret)
445 return ret;
446
447 seq_printf(m, "%u objects, %zu bytes\n",
448 dev_priv->mm.object_count,
449 dev_priv->mm.object_memory);
450
451 size = count = mappable_size = mappable_count = 0;
452 count_objects(&dev_priv->mm.bound_list, global_list);
453 seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
454 count, mappable_count, size, mappable_size);
455
456 size = count = mappable_size = mappable_count = 0;
457 count_vmas(&ggtt->base.active_list, vm_link);
458 seq_printf(m, " %u [%u] active objects, %llu [%llu] bytes\n",
459 count, mappable_count, size, mappable_size);
460
461 size = count = mappable_size = mappable_count = 0;
462 count_vmas(&ggtt->base.inactive_list, vm_link);
463 seq_printf(m, " %u [%u] inactive objects, %llu [%llu] bytes\n",
464 count, mappable_count, size, mappable_size);
465
466 size = count = purgeable_size = purgeable_count = 0;
467 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
468 size += obj->base.size, ++count;
469 if (obj->madv == I915_MADV_DONTNEED)
470 purgeable_size += obj->base.size, ++purgeable_count;
471 }
472 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
473
474 size = count = mappable_size = mappable_count = 0;
475 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
476 if (obj->fault_mappable) {
477 size += i915_gem_obj_ggtt_size(obj);
478 ++count;
479 }
480 if (obj->pin_display) {
481 mappable_size += i915_gem_obj_ggtt_size(obj);
482 ++mappable_count;
483 }
484 if (obj->madv == I915_MADV_DONTNEED) {
485 purgeable_size += obj->base.size;
486 ++purgeable_count;
487 }
488 }
489 seq_printf(m, "%u purgeable objects, %llu bytes\n",
490 purgeable_count, purgeable_size);
491 seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
492 mappable_count, mappable_size);
493 seq_printf(m, "%u fault mappable objects, %llu bytes\n",
494 count, size);
495
496 seq_printf(m, "%llu [%llu] gtt total\n",
497 ggtt->base.total, ggtt->mappable_end - ggtt->base.start);
498
499 seq_putc(m, '\n');
500 print_batch_pool_stats(m, dev_priv);
501 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
502 struct file_stats stats;
503 struct task_struct *task;
504
505 memset(&stats, 0, sizeof(stats));
506 stats.file_priv = file->driver_priv;
507 spin_lock(&file->table_lock);
508 idr_for_each(&file->object_idr, per_file_stats, &stats);
509 spin_unlock(&file->table_lock);
510 /*
511 * Although we have a valid reference on file->pid, that does
512 * not guarantee that the task_struct who called get_pid() is
513 * still alive (e.g. get_pid(current) => fork() => exit()).
514 * Therefore, we need to protect this ->comm access using RCU.
515 */
516 rcu_read_lock();
517 task = pid_task(file->pid, PIDTYPE_PID);
518 print_file_stats(m, task ? task->comm : "<unknown>", stats);
519 rcu_read_unlock();
520 }
521
522 mutex_unlock(&dev->struct_mutex);
523
524 return 0;
525 }
526
527 static int i915_gem_gtt_info(struct seq_file *m, void *data)
528 {
529 struct drm_info_node *node = m->private;
530 struct drm_device *dev = node->minor->dev;
531 uintptr_t list = (uintptr_t) node->info_ent->data;
532 struct drm_i915_private *dev_priv = dev->dev_private;
533 struct drm_i915_gem_object *obj;
534 u64 total_obj_size, total_gtt_size;
535 int count, ret;
536
537 ret = mutex_lock_interruptible(&dev->struct_mutex);
538 if (ret)
539 return ret;
540
541 total_obj_size = total_gtt_size = count = 0;
542 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
543 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
544 continue;
545
546 seq_puts(m, " ");
547 describe_obj(m, obj);
548 seq_putc(m, '\n');
549 total_obj_size += obj->base.size;
550 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
551 count++;
552 }
553
554 mutex_unlock(&dev->struct_mutex);
555
556 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
557 count, total_obj_size, total_gtt_size);
558
559 return 0;
560 }
561
562 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
563 {
564 struct drm_info_node *node = m->private;
565 struct drm_device *dev = node->minor->dev;
566 struct drm_i915_private *dev_priv = dev->dev_private;
567 struct intel_crtc *crtc;
568 int ret;
569
570 ret = mutex_lock_interruptible(&dev->struct_mutex);
571 if (ret)
572 return ret;
573
574 for_each_intel_crtc(dev, crtc) {
575 const char pipe = pipe_name(crtc->pipe);
576 const char plane = plane_name(crtc->plane);
577 struct intel_unpin_work *work;
578
579 spin_lock_irq(&dev->event_lock);
580 work = crtc->unpin_work;
581 if (work == NULL) {
582 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
583 pipe, plane);
584 } else {
585 u32 addr;
586
587 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
588 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
589 pipe, plane);
590 } else {
591 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
592 pipe, plane);
593 }
594 if (work->flip_queued_req) {
595 struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req);
596
597 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
598 engine->name,
599 i915_gem_request_get_seqno(work->flip_queued_req),
600 dev_priv->next_seqno,
601 engine->get_seqno(engine),
602 i915_gem_request_completed(work->flip_queued_req, true));
603 } else
604 seq_printf(m, "Flip not associated with any ring\n");
605 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
606 work->flip_queued_vblank,
607 work->flip_ready_vblank,
608 drm_crtc_vblank_count(&crtc->base));
609 if (work->enable_stall_check)
610 seq_puts(m, "Stall check enabled, ");
611 else
612 seq_puts(m, "Stall check waiting for page flip ioctl, ");
613 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
614
615 if (INTEL_INFO(dev)->gen >= 4)
616 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
617 else
618 addr = I915_READ(DSPADDR(crtc->plane));
619 seq_printf(m, "Current scanout address 0x%08x\n", addr);
620
621 if (work->pending_flip_obj) {
622 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
623 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
624 }
625 }
626 spin_unlock_irq(&dev->event_lock);
627 }
628
629 mutex_unlock(&dev->struct_mutex);
630
631 return 0;
632 }
633
634 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
635 {
636 struct drm_info_node *node = m->private;
637 struct drm_device *dev = node->minor->dev;
638 struct drm_i915_private *dev_priv = dev->dev_private;
639 struct drm_i915_gem_object *obj;
640 struct intel_engine_cs *engine;
641 int total = 0;
642 int ret, j;
643
644 ret = mutex_lock_interruptible(&dev->struct_mutex);
645 if (ret)
646 return ret;
647
648 for_each_engine(engine, dev_priv) {
649 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
650 int count;
651
652 count = 0;
653 list_for_each_entry(obj,
654 &engine->batch_pool.cache_list[j],
655 batch_pool_link)
656 count++;
657 seq_printf(m, "%s cache[%d]: %d objects\n",
658 engine->name, j, count);
659
660 list_for_each_entry(obj,
661 &engine->batch_pool.cache_list[j],
662 batch_pool_link) {
663 seq_puts(m, " ");
664 describe_obj(m, obj);
665 seq_putc(m, '\n');
666 }
667
668 total += count;
669 }
670 }
671
672 seq_printf(m, "total: %d\n", total);
673
674 mutex_unlock(&dev->struct_mutex);
675
676 return 0;
677 }
678
679 static int i915_gem_request_info(struct seq_file *m, void *data)
680 {
681 struct drm_info_node *node = m->private;
682 struct drm_device *dev = node->minor->dev;
683 struct drm_i915_private *dev_priv = dev->dev_private;
684 struct intel_engine_cs *engine;
685 struct drm_i915_gem_request *req;
686 int ret, any;
687
688 ret = mutex_lock_interruptible(&dev->struct_mutex);
689 if (ret)
690 return ret;
691
692 any = 0;
693 for_each_engine(engine, dev_priv) {
694 int count;
695
696 count = 0;
697 list_for_each_entry(req, &engine->request_list, list)
698 count++;
699 if (count == 0)
700 continue;
701
702 seq_printf(m, "%s requests: %d\n", engine->name, count);
703 list_for_each_entry(req, &engine->request_list, list) {
704 struct task_struct *task;
705
706 rcu_read_lock();
707 task = NULL;
708 if (req->pid)
709 task = pid_task(req->pid, PIDTYPE_PID);
710 seq_printf(m, " %x @ %d: %s [%d]\n",
711 req->seqno,
712 (int) (jiffies - req->emitted_jiffies),
713 task ? task->comm : "<unknown>",
714 task ? task->pid : -1);
715 rcu_read_unlock();
716 }
717
718 any++;
719 }
720 mutex_unlock(&dev->struct_mutex);
721
722 if (any == 0)
723 seq_puts(m, "No requests\n");
724
725 return 0;
726 }
727
728 static void i915_ring_seqno_info(struct seq_file *m,
729 struct intel_engine_cs *engine)
730 {
731 seq_printf(m, "Current sequence (%s): %x\n",
732 engine->name, engine->get_seqno(engine));
733 seq_printf(m, "Current user interrupts (%s): %x\n",
734 engine->name, READ_ONCE(engine->user_interrupts));
735 }
736
737 static int i915_gem_seqno_info(struct seq_file *m, void *data)
738 {
739 struct drm_info_node *node = m->private;
740 struct drm_device *dev = node->minor->dev;
741 struct drm_i915_private *dev_priv = dev->dev_private;
742 struct intel_engine_cs *engine;
743 int ret;
744
745 ret = mutex_lock_interruptible(&dev->struct_mutex);
746 if (ret)
747 return ret;
748 intel_runtime_pm_get(dev_priv);
749
750 for_each_engine(engine, dev_priv)
751 i915_ring_seqno_info(m, engine);
752
753 intel_runtime_pm_put(dev_priv);
754 mutex_unlock(&dev->struct_mutex);
755
756 return 0;
757 }
758
759
760 static int i915_interrupt_info(struct seq_file *m, void *data)
761 {
762 struct drm_info_node *node = m->private;
763 struct drm_device *dev = node->minor->dev;
764 struct drm_i915_private *dev_priv = dev->dev_private;
765 struct intel_engine_cs *engine;
766 int ret, i, pipe;
767
768 ret = mutex_lock_interruptible(&dev->struct_mutex);
769 if (ret)
770 return ret;
771 intel_runtime_pm_get(dev_priv);
772
773 if (IS_CHERRYVIEW(dev)) {
774 seq_printf(m, "Master Interrupt Control:\t%08x\n",
775 I915_READ(GEN8_MASTER_IRQ));
776
777 seq_printf(m, "Display IER:\t%08x\n",
778 I915_READ(VLV_IER));
779 seq_printf(m, "Display IIR:\t%08x\n",
780 I915_READ(VLV_IIR));
781 seq_printf(m, "Display IIR_RW:\t%08x\n",
782 I915_READ(VLV_IIR_RW));
783 seq_printf(m, "Display IMR:\t%08x\n",
784 I915_READ(VLV_IMR));
785 for_each_pipe(dev_priv, pipe)
786 seq_printf(m, "Pipe %c stat:\t%08x\n",
787 pipe_name(pipe),
788 I915_READ(PIPESTAT(pipe)));
789
790 seq_printf(m, "Port hotplug:\t%08x\n",
791 I915_READ(PORT_HOTPLUG_EN));
792 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
793 I915_READ(VLV_DPFLIPSTAT));
794 seq_printf(m, "DPINVGTT:\t%08x\n",
795 I915_READ(DPINVGTT));
796
797 for (i = 0; i < 4; i++) {
798 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
799 i, I915_READ(GEN8_GT_IMR(i)));
800 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
801 i, I915_READ(GEN8_GT_IIR(i)));
802 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
803 i, I915_READ(GEN8_GT_IER(i)));
804 }
805
806 seq_printf(m, "PCU interrupt mask:\t%08x\n",
807 I915_READ(GEN8_PCU_IMR));
808 seq_printf(m, "PCU interrupt identity:\t%08x\n",
809 I915_READ(GEN8_PCU_IIR));
810 seq_printf(m, "PCU interrupt enable:\t%08x\n",
811 I915_READ(GEN8_PCU_IER));
812 } else if (INTEL_INFO(dev)->gen >= 8) {
813 seq_printf(m, "Master Interrupt Control:\t%08x\n",
814 I915_READ(GEN8_MASTER_IRQ));
815
816 for (i = 0; i < 4; i++) {
817 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
818 i, I915_READ(GEN8_GT_IMR(i)));
819 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
820 i, I915_READ(GEN8_GT_IIR(i)));
821 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
822 i, I915_READ(GEN8_GT_IER(i)));
823 }
824
825 for_each_pipe(dev_priv, pipe) {
826 enum intel_display_power_domain power_domain;
827
828 power_domain = POWER_DOMAIN_PIPE(pipe);
829 if (!intel_display_power_get_if_enabled(dev_priv,
830 power_domain)) {
831 seq_printf(m, "Pipe %c power disabled\n",
832 pipe_name(pipe));
833 continue;
834 }
835 seq_printf(m, "Pipe %c IMR:\t%08x\n",
836 pipe_name(pipe),
837 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
838 seq_printf(m, "Pipe %c IIR:\t%08x\n",
839 pipe_name(pipe),
840 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
841 seq_printf(m, "Pipe %c IER:\t%08x\n",
842 pipe_name(pipe),
843 I915_READ(GEN8_DE_PIPE_IER(pipe)));
844
845 intel_display_power_put(dev_priv, power_domain);
846 }
847
848 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
849 I915_READ(GEN8_DE_PORT_IMR));
850 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
851 I915_READ(GEN8_DE_PORT_IIR));
852 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
853 I915_READ(GEN8_DE_PORT_IER));
854
855 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
856 I915_READ(GEN8_DE_MISC_IMR));
857 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
858 I915_READ(GEN8_DE_MISC_IIR));
859 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
860 I915_READ(GEN8_DE_MISC_IER));
861
862 seq_printf(m, "PCU interrupt mask:\t%08x\n",
863 I915_READ(GEN8_PCU_IMR));
864 seq_printf(m, "PCU interrupt identity:\t%08x\n",
865 I915_READ(GEN8_PCU_IIR));
866 seq_printf(m, "PCU interrupt enable:\t%08x\n",
867 I915_READ(GEN8_PCU_IER));
868 } else if (IS_VALLEYVIEW(dev)) {
869 seq_printf(m, "Display IER:\t%08x\n",
870 I915_READ(VLV_IER));
871 seq_printf(m, "Display IIR:\t%08x\n",
872 I915_READ(VLV_IIR));
873 seq_printf(m, "Display IIR_RW:\t%08x\n",
874 I915_READ(VLV_IIR_RW));
875 seq_printf(m, "Display IMR:\t%08x\n",
876 I915_READ(VLV_IMR));
877 for_each_pipe(dev_priv, pipe)
878 seq_printf(m, "Pipe %c stat:\t%08x\n",
879 pipe_name(pipe),
880 I915_READ(PIPESTAT(pipe)));
881
882 seq_printf(m, "Master IER:\t%08x\n",
883 I915_READ(VLV_MASTER_IER));
884
885 seq_printf(m, "Render IER:\t%08x\n",
886 I915_READ(GTIER));
887 seq_printf(m, "Render IIR:\t%08x\n",
888 I915_READ(GTIIR));
889 seq_printf(m, "Render IMR:\t%08x\n",
890 I915_READ(GTIMR));
891
892 seq_printf(m, "PM IER:\t\t%08x\n",
893 I915_READ(GEN6_PMIER));
894 seq_printf(m, "PM IIR:\t\t%08x\n",
895 I915_READ(GEN6_PMIIR));
896 seq_printf(m, "PM IMR:\t\t%08x\n",
897 I915_READ(GEN6_PMIMR));
898
899 seq_printf(m, "Port hotplug:\t%08x\n",
900 I915_READ(PORT_HOTPLUG_EN));
901 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
902 I915_READ(VLV_DPFLIPSTAT));
903 seq_printf(m, "DPINVGTT:\t%08x\n",
904 I915_READ(DPINVGTT));
905
906 } else if (!HAS_PCH_SPLIT(dev)) {
907 seq_printf(m, "Interrupt enable: %08x\n",
908 I915_READ(IER));
909 seq_printf(m, "Interrupt identity: %08x\n",
910 I915_READ(IIR));
911 seq_printf(m, "Interrupt mask: %08x\n",
912 I915_READ(IMR));
913 for_each_pipe(dev_priv, pipe)
914 seq_printf(m, "Pipe %c stat: %08x\n",
915 pipe_name(pipe),
916 I915_READ(PIPESTAT(pipe)));
917 } else {
918 seq_printf(m, "North Display Interrupt enable: %08x\n",
919 I915_READ(DEIER));
920 seq_printf(m, "North Display Interrupt identity: %08x\n",
921 I915_READ(DEIIR));
922 seq_printf(m, "North Display Interrupt mask: %08x\n",
923 I915_READ(DEIMR));
924 seq_printf(m, "South Display Interrupt enable: %08x\n",
925 I915_READ(SDEIER));
926 seq_printf(m, "South Display Interrupt identity: %08x\n",
927 I915_READ(SDEIIR));
928 seq_printf(m, "South Display Interrupt mask: %08x\n",
929 I915_READ(SDEIMR));
930 seq_printf(m, "Graphics Interrupt enable: %08x\n",
931 I915_READ(GTIER));
932 seq_printf(m, "Graphics Interrupt identity: %08x\n",
933 I915_READ(GTIIR));
934 seq_printf(m, "Graphics Interrupt mask: %08x\n",
935 I915_READ(GTIMR));
936 }
937 for_each_engine(engine, dev_priv) {
938 if (INTEL_INFO(dev)->gen >= 6) {
939 seq_printf(m,
940 "Graphics Interrupt mask (%s): %08x\n",
941 engine->name, I915_READ_IMR(engine));
942 }
943 i915_ring_seqno_info(m, engine);
944 }
945 intel_runtime_pm_put(dev_priv);
946 mutex_unlock(&dev->struct_mutex);
947
948 return 0;
949 }
950
951 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
952 {
953 struct drm_info_node *node = m->private;
954 struct drm_device *dev = node->minor->dev;
955 struct drm_i915_private *dev_priv = dev->dev_private;
956 int i, ret;
957
958 ret = mutex_lock_interruptible(&dev->struct_mutex);
959 if (ret)
960 return ret;
961
962 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
963 for (i = 0; i < dev_priv->num_fence_regs; i++) {
964 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
965
966 seq_printf(m, "Fence %d, pin count = %d, object = ",
967 i, dev_priv->fence_regs[i].pin_count);
968 if (obj == NULL)
969 seq_puts(m, "unused");
970 else
971 describe_obj(m, obj);
972 seq_putc(m, '\n');
973 }
974
975 mutex_unlock(&dev->struct_mutex);
976 return 0;
977 }
978
979 static int i915_hws_info(struct seq_file *m, void *data)
980 {
981 struct drm_info_node *node = m->private;
982 struct drm_device *dev = node->minor->dev;
983 struct drm_i915_private *dev_priv = dev->dev_private;
984 struct intel_engine_cs *engine;
985 const u32 *hws;
986 int i;
987
988 engine = &dev_priv->engine[(uintptr_t)node->info_ent->data];
989 hws = engine->status_page.page_addr;
990 if (hws == NULL)
991 return 0;
992
993 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
994 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
995 i * 4,
996 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
997 }
998 return 0;
999 }
1000
1001 static ssize_t
1002 i915_error_state_write(struct file *filp,
1003 const char __user *ubuf,
1004 size_t cnt,
1005 loff_t *ppos)
1006 {
1007 struct i915_error_state_file_priv *error_priv = filp->private_data;
1008 struct drm_device *dev = error_priv->dev;
1009 int ret;
1010
1011 DRM_DEBUG_DRIVER("Resetting error state\n");
1012
1013 ret = mutex_lock_interruptible(&dev->struct_mutex);
1014 if (ret)
1015 return ret;
1016
1017 i915_destroy_error_state(dev);
1018 mutex_unlock(&dev->struct_mutex);
1019
1020 return cnt;
1021 }
1022
1023 static int i915_error_state_open(struct inode *inode, struct file *file)
1024 {
1025 struct drm_device *dev = inode->i_private;
1026 struct i915_error_state_file_priv *error_priv;
1027
1028 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1029 if (!error_priv)
1030 return -ENOMEM;
1031
1032 error_priv->dev = dev;
1033
1034 i915_error_state_get(dev, error_priv);
1035
1036 file->private_data = error_priv;
1037
1038 return 0;
1039 }
1040
1041 static int i915_error_state_release(struct inode *inode, struct file *file)
1042 {
1043 struct i915_error_state_file_priv *error_priv = file->private_data;
1044
1045 i915_error_state_put(error_priv);
1046 kfree(error_priv);
1047
1048 return 0;
1049 }
1050
1051 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1052 size_t count, loff_t *pos)
1053 {
1054 struct i915_error_state_file_priv *error_priv = file->private_data;
1055 struct drm_i915_error_state_buf error_str;
1056 loff_t tmp_pos = 0;
1057 ssize_t ret_count = 0;
1058 int ret;
1059
1060 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1061 if (ret)
1062 return ret;
1063
1064 ret = i915_error_state_to_str(&error_str, error_priv);
1065 if (ret)
1066 goto out;
1067
1068 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1069 error_str.buf,
1070 error_str.bytes);
1071
1072 if (ret_count < 0)
1073 ret = ret_count;
1074 else
1075 *pos = error_str.start + ret_count;
1076 out:
1077 i915_error_state_buf_release(&error_str);
1078 return ret ?: ret_count;
1079 }
1080
1081 static const struct file_operations i915_error_state_fops = {
1082 .owner = THIS_MODULE,
1083 .open = i915_error_state_open,
1084 .read = i915_error_state_read,
1085 .write = i915_error_state_write,
1086 .llseek = default_llseek,
1087 .release = i915_error_state_release,
1088 };
1089
1090 static int
1091 i915_next_seqno_get(void *data, u64 *val)
1092 {
1093 struct drm_device *dev = data;
1094 struct drm_i915_private *dev_priv = dev->dev_private;
1095 int ret;
1096
1097 ret = mutex_lock_interruptible(&dev->struct_mutex);
1098 if (ret)
1099 return ret;
1100
1101 *val = dev_priv->next_seqno;
1102 mutex_unlock(&dev->struct_mutex);
1103
1104 return 0;
1105 }
1106
1107 static int
1108 i915_next_seqno_set(void *data, u64 val)
1109 {
1110 struct drm_device *dev = data;
1111 int ret;
1112
1113 ret = mutex_lock_interruptible(&dev->struct_mutex);
1114 if (ret)
1115 return ret;
1116
1117 ret = i915_gem_set_seqno(dev, val);
1118 mutex_unlock(&dev->struct_mutex);
1119
1120 return ret;
1121 }
1122
1123 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1124 i915_next_seqno_get, i915_next_seqno_set,
1125 "0x%llx\n");
1126
1127 static int i915_frequency_info(struct seq_file *m, void *unused)
1128 {
1129 struct drm_info_node *node = m->private;
1130 struct drm_device *dev = node->minor->dev;
1131 struct drm_i915_private *dev_priv = dev->dev_private;
1132 int ret = 0;
1133
1134 intel_runtime_pm_get(dev_priv);
1135
1136 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1137
1138 if (IS_GEN5(dev)) {
1139 u16 rgvswctl = I915_READ16(MEMSWCTL);
1140 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1141
1142 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1143 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1144 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1145 MEMSTAT_VID_SHIFT);
1146 seq_printf(m, "Current P-state: %d\n",
1147 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1148 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1149 u32 freq_sts;
1150
1151 mutex_lock(&dev_priv->rps.hw_lock);
1152 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1153 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1154 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1155
1156 seq_printf(m, "actual GPU freq: %d MHz\n",
1157 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1158
1159 seq_printf(m, "current GPU freq: %d MHz\n",
1160 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1161
1162 seq_printf(m, "max GPU freq: %d MHz\n",
1163 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1164
1165 seq_printf(m, "min GPU freq: %d MHz\n",
1166 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1167
1168 seq_printf(m, "idle GPU freq: %d MHz\n",
1169 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1170
1171 seq_printf(m,
1172 "efficient (RPe) frequency: %d MHz\n",
1173 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1174 mutex_unlock(&dev_priv->rps.hw_lock);
1175 } else if (INTEL_INFO(dev)->gen >= 6) {
1176 u32 rp_state_limits;
1177 u32 gt_perf_status;
1178 u32 rp_state_cap;
1179 u32 rpmodectl, rpinclimit, rpdeclimit;
1180 u32 rpstat, cagf, reqf;
1181 u32 rpupei, rpcurup, rpprevup;
1182 u32 rpdownei, rpcurdown, rpprevdown;
1183 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1184 int max_freq;
1185
1186 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1187 if (IS_BROXTON(dev)) {
1188 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1189 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1190 } else {
1191 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1192 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1193 }
1194
1195 /* RPSTAT1 is in the GT power well */
1196 ret = mutex_lock_interruptible(&dev->struct_mutex);
1197 if (ret)
1198 goto out;
1199
1200 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1201
1202 reqf = I915_READ(GEN6_RPNSWREQ);
1203 if (IS_GEN9(dev))
1204 reqf >>= 23;
1205 else {
1206 reqf &= ~GEN6_TURBO_DISABLE;
1207 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1208 reqf >>= 24;
1209 else
1210 reqf >>= 25;
1211 }
1212 reqf = intel_gpu_freq(dev_priv, reqf);
1213
1214 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1215 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1216 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1217
1218 rpstat = I915_READ(GEN6_RPSTAT1);
1219 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1220 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1221 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1222 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1223 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1224 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1225 if (IS_GEN9(dev))
1226 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1227 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1228 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1229 else
1230 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1231 cagf = intel_gpu_freq(dev_priv, cagf);
1232
1233 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1234 mutex_unlock(&dev->struct_mutex);
1235
1236 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1237 pm_ier = I915_READ(GEN6_PMIER);
1238 pm_imr = I915_READ(GEN6_PMIMR);
1239 pm_isr = I915_READ(GEN6_PMISR);
1240 pm_iir = I915_READ(GEN6_PMIIR);
1241 pm_mask = I915_READ(GEN6_PMINTRMSK);
1242 } else {
1243 pm_ier = I915_READ(GEN8_GT_IER(2));
1244 pm_imr = I915_READ(GEN8_GT_IMR(2));
1245 pm_isr = I915_READ(GEN8_GT_ISR(2));
1246 pm_iir = I915_READ(GEN8_GT_IIR(2));
1247 pm_mask = I915_READ(GEN6_PMINTRMSK);
1248 }
1249 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1250 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1251 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1252 seq_printf(m, "Render p-state ratio: %d\n",
1253 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
1254 seq_printf(m, "Render p-state VID: %d\n",
1255 gt_perf_status & 0xff);
1256 seq_printf(m, "Render p-state limit: %d\n",
1257 rp_state_limits & 0xff);
1258 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1259 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1260 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1261 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1262 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1263 seq_printf(m, "CAGF: %dMHz\n", cagf);
1264 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1265 GEN6_CURICONT_MASK);
1266 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1267 GEN6_CURBSYTAVG_MASK);
1268 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1269 GEN6_CURBSYTAVG_MASK);
1270 seq_printf(m, "Up threshold: %d%%\n",
1271 dev_priv->rps.up_threshold);
1272
1273 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1274 GEN6_CURIAVG_MASK);
1275 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1276 GEN6_CURBSYTAVG_MASK);
1277 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1278 GEN6_CURBSYTAVG_MASK);
1279 seq_printf(m, "Down threshold: %d%%\n",
1280 dev_priv->rps.down_threshold);
1281
1282 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1283 rp_state_cap >> 16) & 0xff;
1284 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1285 GEN9_FREQ_SCALER : 1);
1286 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1287 intel_gpu_freq(dev_priv, max_freq));
1288
1289 max_freq = (rp_state_cap & 0xff00) >> 8;
1290 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1291 GEN9_FREQ_SCALER : 1);
1292 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1293 intel_gpu_freq(dev_priv, max_freq));
1294
1295 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1296 rp_state_cap >> 0) & 0xff;
1297 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1298 GEN9_FREQ_SCALER : 1);
1299 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1300 intel_gpu_freq(dev_priv, max_freq));
1301 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1302 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1303
1304 seq_printf(m, "Current freq: %d MHz\n",
1305 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1306 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1307 seq_printf(m, "Idle freq: %d MHz\n",
1308 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1309 seq_printf(m, "Min freq: %d MHz\n",
1310 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1311 seq_printf(m, "Max freq: %d MHz\n",
1312 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1313 seq_printf(m,
1314 "efficient (RPe) frequency: %d MHz\n",
1315 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1316 } else {
1317 seq_puts(m, "no P-state info available\n");
1318 }
1319
1320 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1321 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1322 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1323
1324 out:
1325 intel_runtime_pm_put(dev_priv);
1326 return ret;
1327 }
1328
1329 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1330 {
1331 struct drm_info_node *node = m->private;
1332 struct drm_device *dev = node->minor->dev;
1333 struct drm_i915_private *dev_priv = dev->dev_private;
1334 struct intel_engine_cs *engine;
1335 u64 acthd[I915_NUM_ENGINES];
1336 u32 seqno[I915_NUM_ENGINES];
1337 u32 instdone[I915_NUM_INSTDONE_REG];
1338 enum intel_engine_id id;
1339 int j;
1340
1341 if (!i915.enable_hangcheck) {
1342 seq_printf(m, "Hangcheck disabled\n");
1343 return 0;
1344 }
1345
1346 intel_runtime_pm_get(dev_priv);
1347
1348 for_each_engine_id(engine, dev_priv, id) {
1349 acthd[id] = intel_ring_get_active_head(engine);
1350 seqno[id] = engine->get_seqno(engine);
1351 }
1352
1353 i915_get_extra_instdone(dev, instdone);
1354
1355 intel_runtime_pm_put(dev_priv);
1356
1357 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1358 seq_printf(m, "Hangcheck active, fires in %dms\n",
1359 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1360 jiffies));
1361 } else
1362 seq_printf(m, "Hangcheck inactive\n");
1363
1364 for_each_engine_id(engine, dev_priv, id) {
1365 seq_printf(m, "%s:\n", engine->name);
1366 seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
1367 engine->hangcheck.seqno,
1368 seqno[id],
1369 engine->last_submitted_seqno);
1370 seq_printf(m, "\tuser interrupts = %x [current %x]\n",
1371 engine->hangcheck.user_interrupts,
1372 READ_ONCE(engine->user_interrupts));
1373 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1374 (long long)engine->hangcheck.acthd,
1375 (long long)acthd[id]);
1376 seq_printf(m, "\tscore = %d\n", engine->hangcheck.score);
1377 seq_printf(m, "\taction = %d\n", engine->hangcheck.action);
1378
1379 if (engine->id == RCS) {
1380 seq_puts(m, "\tinstdone read =");
1381
1382 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1383 seq_printf(m, " 0x%08x", instdone[j]);
1384
1385 seq_puts(m, "\n\tinstdone accu =");
1386
1387 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1388 seq_printf(m, " 0x%08x",
1389 engine->hangcheck.instdone[j]);
1390
1391 seq_puts(m, "\n");
1392 }
1393 }
1394
1395 return 0;
1396 }
1397
1398 static int ironlake_drpc_info(struct seq_file *m)
1399 {
1400 struct drm_info_node *node = m->private;
1401 struct drm_device *dev = node->minor->dev;
1402 struct drm_i915_private *dev_priv = dev->dev_private;
1403 u32 rgvmodectl, rstdbyctl;
1404 u16 crstandvid;
1405 int ret;
1406
1407 ret = mutex_lock_interruptible(&dev->struct_mutex);
1408 if (ret)
1409 return ret;
1410 intel_runtime_pm_get(dev_priv);
1411
1412 rgvmodectl = I915_READ(MEMMODECTL);
1413 rstdbyctl = I915_READ(RSTDBYCTL);
1414 crstandvid = I915_READ16(CRSTANDVID);
1415
1416 intel_runtime_pm_put(dev_priv);
1417 mutex_unlock(&dev->struct_mutex);
1418
1419 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1420 seq_printf(m, "Boost freq: %d\n",
1421 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1422 MEMMODE_BOOST_FREQ_SHIFT);
1423 seq_printf(m, "HW control enabled: %s\n",
1424 yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1425 seq_printf(m, "SW control enabled: %s\n",
1426 yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1427 seq_printf(m, "Gated voltage change: %s\n",
1428 yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1429 seq_printf(m, "Starting frequency: P%d\n",
1430 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1431 seq_printf(m, "Max P-state: P%d\n",
1432 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1433 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1434 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1435 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1436 seq_printf(m, "Render standby enabled: %s\n",
1437 yesno(!(rstdbyctl & RCX_SW_EXIT)));
1438 seq_puts(m, "Current RS state: ");
1439 switch (rstdbyctl & RSX_STATUS_MASK) {
1440 case RSX_STATUS_ON:
1441 seq_puts(m, "on\n");
1442 break;
1443 case RSX_STATUS_RC1:
1444 seq_puts(m, "RC1\n");
1445 break;
1446 case RSX_STATUS_RC1E:
1447 seq_puts(m, "RC1E\n");
1448 break;
1449 case RSX_STATUS_RS1:
1450 seq_puts(m, "RS1\n");
1451 break;
1452 case RSX_STATUS_RS2:
1453 seq_puts(m, "RS2 (RC6)\n");
1454 break;
1455 case RSX_STATUS_RS3:
1456 seq_puts(m, "RC3 (RC6+)\n");
1457 break;
1458 default:
1459 seq_puts(m, "unknown\n");
1460 break;
1461 }
1462
1463 return 0;
1464 }
1465
1466 static int i915_forcewake_domains(struct seq_file *m, void *data)
1467 {
1468 struct drm_info_node *node = m->private;
1469 struct drm_device *dev = node->minor->dev;
1470 struct drm_i915_private *dev_priv = dev->dev_private;
1471 struct intel_uncore_forcewake_domain *fw_domain;
1472
1473 spin_lock_irq(&dev_priv->uncore.lock);
1474 for_each_fw_domain(fw_domain, dev_priv) {
1475 seq_printf(m, "%s.wake_count = %u\n",
1476 intel_uncore_forcewake_domain_to_str(fw_domain->id),
1477 fw_domain->wake_count);
1478 }
1479 spin_unlock_irq(&dev_priv->uncore.lock);
1480
1481 return 0;
1482 }
1483
1484 static int vlv_drpc_info(struct seq_file *m)
1485 {
1486 struct drm_info_node *node = m->private;
1487 struct drm_device *dev = node->minor->dev;
1488 struct drm_i915_private *dev_priv = dev->dev_private;
1489 u32 rpmodectl1, rcctl1, pw_status;
1490
1491 intel_runtime_pm_get(dev_priv);
1492
1493 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1494 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1495 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1496
1497 intel_runtime_pm_put(dev_priv);
1498
1499 seq_printf(m, "Video Turbo Mode: %s\n",
1500 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1501 seq_printf(m, "Turbo enabled: %s\n",
1502 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1503 seq_printf(m, "HW control enabled: %s\n",
1504 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1505 seq_printf(m, "SW control enabled: %s\n",
1506 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1507 GEN6_RP_MEDIA_SW_MODE));
1508 seq_printf(m, "RC6 Enabled: %s\n",
1509 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1510 GEN6_RC_CTL_EI_MODE(1))));
1511 seq_printf(m, "Render Power Well: %s\n",
1512 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1513 seq_printf(m, "Media Power Well: %s\n",
1514 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1515
1516 seq_printf(m, "Render RC6 residency since boot: %u\n",
1517 I915_READ(VLV_GT_RENDER_RC6));
1518 seq_printf(m, "Media RC6 residency since boot: %u\n",
1519 I915_READ(VLV_GT_MEDIA_RC6));
1520
1521 return i915_forcewake_domains(m, NULL);
1522 }
1523
1524 static int gen6_drpc_info(struct seq_file *m)
1525 {
1526 struct drm_info_node *node = m->private;
1527 struct drm_device *dev = node->minor->dev;
1528 struct drm_i915_private *dev_priv = dev->dev_private;
1529 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1530 unsigned forcewake_count;
1531 int count = 0, ret;
1532
1533 ret = mutex_lock_interruptible(&dev->struct_mutex);
1534 if (ret)
1535 return ret;
1536 intel_runtime_pm_get(dev_priv);
1537
1538 spin_lock_irq(&dev_priv->uncore.lock);
1539 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1540 spin_unlock_irq(&dev_priv->uncore.lock);
1541
1542 if (forcewake_count) {
1543 seq_puts(m, "RC information inaccurate because somebody "
1544 "holds a forcewake reference \n");
1545 } else {
1546 /* NB: we cannot use forcewake, else we read the wrong values */
1547 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1548 udelay(10);
1549 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1550 }
1551
1552 gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1553 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1554
1555 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1556 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1557 mutex_unlock(&dev->struct_mutex);
1558 mutex_lock(&dev_priv->rps.hw_lock);
1559 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1560 mutex_unlock(&dev_priv->rps.hw_lock);
1561
1562 intel_runtime_pm_put(dev_priv);
1563
1564 seq_printf(m, "Video Turbo Mode: %s\n",
1565 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1566 seq_printf(m, "HW control enabled: %s\n",
1567 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1568 seq_printf(m, "SW control enabled: %s\n",
1569 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1570 GEN6_RP_MEDIA_SW_MODE));
1571 seq_printf(m, "RC1e Enabled: %s\n",
1572 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1573 seq_printf(m, "RC6 Enabled: %s\n",
1574 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1575 seq_printf(m, "Deep RC6 Enabled: %s\n",
1576 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1577 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1578 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1579 seq_puts(m, "Current RC state: ");
1580 switch (gt_core_status & GEN6_RCn_MASK) {
1581 case GEN6_RC0:
1582 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1583 seq_puts(m, "Core Power Down\n");
1584 else
1585 seq_puts(m, "on\n");
1586 break;
1587 case GEN6_RC3:
1588 seq_puts(m, "RC3\n");
1589 break;
1590 case GEN6_RC6:
1591 seq_puts(m, "RC6\n");
1592 break;
1593 case GEN6_RC7:
1594 seq_puts(m, "RC7\n");
1595 break;
1596 default:
1597 seq_puts(m, "Unknown\n");
1598 break;
1599 }
1600
1601 seq_printf(m, "Core Power Down: %s\n",
1602 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1603
1604 /* Not exactly sure what this is */
1605 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1606 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1607 seq_printf(m, "RC6 residency since boot: %u\n",
1608 I915_READ(GEN6_GT_GFX_RC6));
1609 seq_printf(m, "RC6+ residency since boot: %u\n",
1610 I915_READ(GEN6_GT_GFX_RC6p));
1611 seq_printf(m, "RC6++ residency since boot: %u\n",
1612 I915_READ(GEN6_GT_GFX_RC6pp));
1613
1614 seq_printf(m, "RC6 voltage: %dmV\n",
1615 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1616 seq_printf(m, "RC6+ voltage: %dmV\n",
1617 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1618 seq_printf(m, "RC6++ voltage: %dmV\n",
1619 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1620 return 0;
1621 }
1622
1623 static int i915_drpc_info(struct seq_file *m, void *unused)
1624 {
1625 struct drm_info_node *node = m->private;
1626 struct drm_device *dev = node->minor->dev;
1627
1628 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1629 return vlv_drpc_info(m);
1630 else if (INTEL_INFO(dev)->gen >= 6)
1631 return gen6_drpc_info(m);
1632 else
1633 return ironlake_drpc_info(m);
1634 }
1635
1636 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1637 {
1638 struct drm_info_node *node = m->private;
1639 struct drm_device *dev = node->minor->dev;
1640 struct drm_i915_private *dev_priv = dev->dev_private;
1641
1642 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1643 dev_priv->fb_tracking.busy_bits);
1644
1645 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1646 dev_priv->fb_tracking.flip_bits);
1647
1648 return 0;
1649 }
1650
1651 static int i915_fbc_status(struct seq_file *m, void *unused)
1652 {
1653 struct drm_info_node *node = m->private;
1654 struct drm_device *dev = node->minor->dev;
1655 struct drm_i915_private *dev_priv = dev->dev_private;
1656
1657 if (!HAS_FBC(dev)) {
1658 seq_puts(m, "FBC unsupported on this chipset\n");
1659 return 0;
1660 }
1661
1662 intel_runtime_pm_get(dev_priv);
1663 mutex_lock(&dev_priv->fbc.lock);
1664
1665 if (intel_fbc_is_active(dev_priv))
1666 seq_puts(m, "FBC enabled\n");
1667 else
1668 seq_printf(m, "FBC disabled: %s\n",
1669 dev_priv->fbc.no_fbc_reason);
1670
1671 if (INTEL_INFO(dev_priv)->gen >= 7)
1672 seq_printf(m, "Compressing: %s\n",
1673 yesno(I915_READ(FBC_STATUS2) &
1674 FBC_COMPRESSION_MASK));
1675
1676 mutex_unlock(&dev_priv->fbc.lock);
1677 intel_runtime_pm_put(dev_priv);
1678
1679 return 0;
1680 }
1681
1682 static int i915_fbc_fc_get(void *data, u64 *val)
1683 {
1684 struct drm_device *dev = data;
1685 struct drm_i915_private *dev_priv = dev->dev_private;
1686
1687 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1688 return -ENODEV;
1689
1690 *val = dev_priv->fbc.false_color;
1691
1692 return 0;
1693 }
1694
1695 static int i915_fbc_fc_set(void *data, u64 val)
1696 {
1697 struct drm_device *dev = data;
1698 struct drm_i915_private *dev_priv = dev->dev_private;
1699 u32 reg;
1700
1701 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1702 return -ENODEV;
1703
1704 mutex_lock(&dev_priv->fbc.lock);
1705
1706 reg = I915_READ(ILK_DPFC_CONTROL);
1707 dev_priv->fbc.false_color = val;
1708
1709 I915_WRITE(ILK_DPFC_CONTROL, val ?
1710 (reg | FBC_CTL_FALSE_COLOR) :
1711 (reg & ~FBC_CTL_FALSE_COLOR));
1712
1713 mutex_unlock(&dev_priv->fbc.lock);
1714 return 0;
1715 }
1716
1717 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1718 i915_fbc_fc_get, i915_fbc_fc_set,
1719 "%llu\n");
1720
1721 static int i915_ips_status(struct seq_file *m, void *unused)
1722 {
1723 struct drm_info_node *node = m->private;
1724 struct drm_device *dev = node->minor->dev;
1725 struct drm_i915_private *dev_priv = dev->dev_private;
1726
1727 if (!HAS_IPS(dev)) {
1728 seq_puts(m, "not supported\n");
1729 return 0;
1730 }
1731
1732 intel_runtime_pm_get(dev_priv);
1733
1734 seq_printf(m, "Enabled by kernel parameter: %s\n",
1735 yesno(i915.enable_ips));
1736
1737 if (INTEL_INFO(dev)->gen >= 8) {
1738 seq_puts(m, "Currently: unknown\n");
1739 } else {
1740 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1741 seq_puts(m, "Currently: enabled\n");
1742 else
1743 seq_puts(m, "Currently: disabled\n");
1744 }
1745
1746 intel_runtime_pm_put(dev_priv);
1747
1748 return 0;
1749 }
1750
1751 static int i915_sr_status(struct seq_file *m, void *unused)
1752 {
1753 struct drm_info_node *node = m->private;
1754 struct drm_device *dev = node->minor->dev;
1755 struct drm_i915_private *dev_priv = dev->dev_private;
1756 bool sr_enabled = false;
1757
1758 intel_runtime_pm_get(dev_priv);
1759
1760 if (HAS_PCH_SPLIT(dev))
1761 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1762 else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1763 IS_I945G(dev) || IS_I945GM(dev))
1764 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1765 else if (IS_I915GM(dev))
1766 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1767 else if (IS_PINEVIEW(dev))
1768 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1769 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1770 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1771
1772 intel_runtime_pm_put(dev_priv);
1773
1774 seq_printf(m, "self-refresh: %s\n",
1775 sr_enabled ? "enabled" : "disabled");
1776
1777 return 0;
1778 }
1779
1780 static int i915_emon_status(struct seq_file *m, void *unused)
1781 {
1782 struct drm_info_node *node = m->private;
1783 struct drm_device *dev = node->minor->dev;
1784 struct drm_i915_private *dev_priv = dev->dev_private;
1785 unsigned long temp, chipset, gfx;
1786 int ret;
1787
1788 if (!IS_GEN5(dev))
1789 return -ENODEV;
1790
1791 ret = mutex_lock_interruptible(&dev->struct_mutex);
1792 if (ret)
1793 return ret;
1794
1795 temp = i915_mch_val(dev_priv);
1796 chipset = i915_chipset_val(dev_priv);
1797 gfx = i915_gfx_val(dev_priv);
1798 mutex_unlock(&dev->struct_mutex);
1799
1800 seq_printf(m, "GMCH temp: %ld\n", temp);
1801 seq_printf(m, "Chipset power: %ld\n", chipset);
1802 seq_printf(m, "GFX power: %ld\n", gfx);
1803 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1804
1805 return 0;
1806 }
1807
1808 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1809 {
1810 struct drm_info_node *node = m->private;
1811 struct drm_device *dev = node->minor->dev;
1812 struct drm_i915_private *dev_priv = dev->dev_private;
1813 int ret = 0;
1814 int gpu_freq, ia_freq;
1815 unsigned int max_gpu_freq, min_gpu_freq;
1816
1817 if (!HAS_CORE_RING_FREQ(dev)) {
1818 seq_puts(m, "unsupported on this chipset\n");
1819 return 0;
1820 }
1821
1822 intel_runtime_pm_get(dev_priv);
1823
1824 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1825
1826 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1827 if (ret)
1828 goto out;
1829
1830 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
1831 /* Convert GT frequency to 50 HZ units */
1832 min_gpu_freq =
1833 dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1834 max_gpu_freq =
1835 dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1836 } else {
1837 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1838 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1839 }
1840
1841 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1842
1843 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1844 ia_freq = gpu_freq;
1845 sandybridge_pcode_read(dev_priv,
1846 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1847 &ia_freq);
1848 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1849 intel_gpu_freq(dev_priv, (gpu_freq *
1850 (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1851 GEN9_FREQ_SCALER : 1))),
1852 ((ia_freq >> 0) & 0xff) * 100,
1853 ((ia_freq >> 8) & 0xff) * 100);
1854 }
1855
1856 mutex_unlock(&dev_priv->rps.hw_lock);
1857
1858 out:
1859 intel_runtime_pm_put(dev_priv);
1860 return ret;
1861 }
1862
1863 static int i915_opregion(struct seq_file *m, void *unused)
1864 {
1865 struct drm_info_node *node = m->private;
1866 struct drm_device *dev = node->minor->dev;
1867 struct drm_i915_private *dev_priv = dev->dev_private;
1868 struct intel_opregion *opregion = &dev_priv->opregion;
1869 int ret;
1870
1871 ret = mutex_lock_interruptible(&dev->struct_mutex);
1872 if (ret)
1873 goto out;
1874
1875 if (opregion->header)
1876 seq_write(m, opregion->header, OPREGION_SIZE);
1877
1878 mutex_unlock(&dev->struct_mutex);
1879
1880 out:
1881 return 0;
1882 }
1883
1884 static int i915_vbt(struct seq_file *m, void *unused)
1885 {
1886 struct drm_info_node *node = m->private;
1887 struct drm_device *dev = node->minor->dev;
1888 struct drm_i915_private *dev_priv = dev->dev_private;
1889 struct intel_opregion *opregion = &dev_priv->opregion;
1890
1891 if (opregion->vbt)
1892 seq_write(m, opregion->vbt, opregion->vbt_size);
1893
1894 return 0;
1895 }
1896
1897 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1898 {
1899 struct drm_info_node *node = m->private;
1900 struct drm_device *dev = node->minor->dev;
1901 struct intel_framebuffer *fbdev_fb = NULL;
1902 struct drm_framebuffer *drm_fb;
1903 int ret;
1904
1905 ret = mutex_lock_interruptible(&dev->struct_mutex);
1906 if (ret)
1907 return ret;
1908
1909 #ifdef CONFIG_DRM_FBDEV_EMULATION
1910 if (to_i915(dev)->fbdev) {
1911 fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb);
1912
1913 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1914 fbdev_fb->base.width,
1915 fbdev_fb->base.height,
1916 fbdev_fb->base.depth,
1917 fbdev_fb->base.bits_per_pixel,
1918 fbdev_fb->base.modifier[0],
1919 atomic_read(&fbdev_fb->base.refcount.refcount));
1920 describe_obj(m, fbdev_fb->obj);
1921 seq_putc(m, '\n');
1922 }
1923 #endif
1924
1925 mutex_lock(&dev->mode_config.fb_lock);
1926 drm_for_each_fb(drm_fb, dev) {
1927 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1928 if (fb == fbdev_fb)
1929 continue;
1930
1931 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1932 fb->base.width,
1933 fb->base.height,
1934 fb->base.depth,
1935 fb->base.bits_per_pixel,
1936 fb->base.modifier[0],
1937 atomic_read(&fb->base.refcount.refcount));
1938 describe_obj(m, fb->obj);
1939 seq_putc(m, '\n');
1940 }
1941 mutex_unlock(&dev->mode_config.fb_lock);
1942 mutex_unlock(&dev->struct_mutex);
1943
1944 return 0;
1945 }
1946
1947 static void describe_ctx_ringbuf(struct seq_file *m,
1948 struct intel_ringbuffer *ringbuf)
1949 {
1950 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1951 ringbuf->space, ringbuf->head, ringbuf->tail,
1952 ringbuf->last_retired_head);
1953 }
1954
1955 static int i915_context_status(struct seq_file *m, void *unused)
1956 {
1957 struct drm_info_node *node = m->private;
1958 struct drm_device *dev = node->minor->dev;
1959 struct drm_i915_private *dev_priv = dev->dev_private;
1960 struct intel_engine_cs *engine;
1961 struct intel_context *ctx;
1962 enum intel_engine_id id;
1963 int ret;
1964
1965 ret = mutex_lock_interruptible(&dev->struct_mutex);
1966 if (ret)
1967 return ret;
1968
1969 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1970 if (!i915.enable_execlists &&
1971 ctx->legacy_hw_ctx.rcs_state == NULL)
1972 continue;
1973
1974 seq_puts(m, "HW context ");
1975 describe_ctx(m, ctx);
1976 if (ctx == dev_priv->kernel_context)
1977 seq_printf(m, "(kernel context) ");
1978
1979 if (i915.enable_execlists) {
1980 seq_putc(m, '\n');
1981 for_each_engine_id(engine, dev_priv, id) {
1982 struct drm_i915_gem_object *ctx_obj =
1983 ctx->engine[id].state;
1984 struct intel_ringbuffer *ringbuf =
1985 ctx->engine[id].ringbuf;
1986
1987 seq_printf(m, "%s: ", engine->name);
1988 if (ctx_obj)
1989 describe_obj(m, ctx_obj);
1990 if (ringbuf)
1991 describe_ctx_ringbuf(m, ringbuf);
1992 seq_putc(m, '\n');
1993 }
1994 } else {
1995 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1996 }
1997
1998 seq_putc(m, '\n');
1999 }
2000
2001 mutex_unlock(&dev->struct_mutex);
2002
2003 return 0;
2004 }
2005
2006 static void i915_dump_lrc_obj(struct seq_file *m,
2007 struct intel_context *ctx,
2008 struct intel_engine_cs *engine)
2009 {
2010 struct page *page;
2011 uint32_t *reg_state;
2012 int j;
2013 struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state;
2014 unsigned long ggtt_offset = 0;
2015
2016 if (ctx_obj == NULL) {
2017 seq_printf(m, "Context on %s with no gem object\n",
2018 engine->name);
2019 return;
2020 }
2021
2022 seq_printf(m, "CONTEXT: %s %u\n", engine->name,
2023 intel_execlists_ctx_id(ctx, engine));
2024
2025 if (!i915_gem_obj_ggtt_bound(ctx_obj))
2026 seq_puts(m, "\tNot bound in GGTT\n");
2027 else
2028 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
2029
2030 if (i915_gem_object_get_pages(ctx_obj)) {
2031 seq_puts(m, "\tFailed to get pages for context object\n");
2032 return;
2033 }
2034
2035 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
2036 if (!WARN_ON(page == NULL)) {
2037 reg_state = kmap_atomic(page);
2038
2039 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2040 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2041 ggtt_offset + 4096 + (j * 4),
2042 reg_state[j], reg_state[j + 1],
2043 reg_state[j + 2], reg_state[j + 3]);
2044 }
2045 kunmap_atomic(reg_state);
2046 }
2047
2048 seq_putc(m, '\n');
2049 }
2050
2051 static int i915_dump_lrc(struct seq_file *m, void *unused)
2052 {
2053 struct drm_info_node *node = (struct drm_info_node *) m->private;
2054 struct drm_device *dev = node->minor->dev;
2055 struct drm_i915_private *dev_priv = dev->dev_private;
2056 struct intel_engine_cs *engine;
2057 struct intel_context *ctx;
2058 int ret;
2059
2060 if (!i915.enable_execlists) {
2061 seq_printf(m, "Logical Ring Contexts are disabled\n");
2062 return 0;
2063 }
2064
2065 ret = mutex_lock_interruptible(&dev->struct_mutex);
2066 if (ret)
2067 return ret;
2068
2069 list_for_each_entry(ctx, &dev_priv->context_list, link)
2070 if (ctx != dev_priv->kernel_context)
2071 for_each_engine(engine, dev_priv)
2072 i915_dump_lrc_obj(m, ctx, engine);
2073
2074 mutex_unlock(&dev->struct_mutex);
2075
2076 return 0;
2077 }
2078
2079 static int i915_execlists(struct seq_file *m, void *data)
2080 {
2081 struct drm_info_node *node = (struct drm_info_node *)m->private;
2082 struct drm_device *dev = node->minor->dev;
2083 struct drm_i915_private *dev_priv = dev->dev_private;
2084 struct intel_engine_cs *engine;
2085 u32 status_pointer;
2086 u8 read_pointer;
2087 u8 write_pointer;
2088 u32 status;
2089 u32 ctx_id;
2090 struct list_head *cursor;
2091 int i, ret;
2092
2093 if (!i915.enable_execlists) {
2094 seq_puts(m, "Logical Ring Contexts are disabled\n");
2095 return 0;
2096 }
2097
2098 ret = mutex_lock_interruptible(&dev->struct_mutex);
2099 if (ret)
2100 return ret;
2101
2102 intel_runtime_pm_get(dev_priv);
2103
2104 for_each_engine(engine, dev_priv) {
2105 struct drm_i915_gem_request *head_req = NULL;
2106 int count = 0;
2107
2108 seq_printf(m, "%s\n", engine->name);
2109
2110 status = I915_READ(RING_EXECLIST_STATUS_LO(engine));
2111 ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(engine));
2112 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2113 status, ctx_id);
2114
2115 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
2116 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2117
2118 read_pointer = engine->next_context_status_buffer;
2119 write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
2120 if (read_pointer > write_pointer)
2121 write_pointer += GEN8_CSB_ENTRIES;
2122 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2123 read_pointer, write_pointer);
2124
2125 for (i = 0; i < GEN8_CSB_ENTRIES; i++) {
2126 status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, i));
2127 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, i));
2128
2129 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2130 i, status, ctx_id);
2131 }
2132
2133 spin_lock_bh(&engine->execlist_lock);
2134 list_for_each(cursor, &engine->execlist_queue)
2135 count++;
2136 head_req = list_first_entry_or_null(&engine->execlist_queue,
2137 struct drm_i915_gem_request,
2138 execlist_link);
2139 spin_unlock_bh(&engine->execlist_lock);
2140
2141 seq_printf(m, "\t%d requests in queue\n", count);
2142 if (head_req) {
2143 seq_printf(m, "\tHead request id: %u\n",
2144 intel_execlists_ctx_id(head_req->ctx, engine));
2145 seq_printf(m, "\tHead request tail: %u\n",
2146 head_req->tail);
2147 }
2148
2149 seq_putc(m, '\n');
2150 }
2151
2152 intel_runtime_pm_put(dev_priv);
2153 mutex_unlock(&dev->struct_mutex);
2154
2155 return 0;
2156 }
2157
2158 static const char *swizzle_string(unsigned swizzle)
2159 {
2160 switch (swizzle) {
2161 case I915_BIT_6_SWIZZLE_NONE:
2162 return "none";
2163 case I915_BIT_6_SWIZZLE_9:
2164 return "bit9";
2165 case I915_BIT_6_SWIZZLE_9_10:
2166 return "bit9/bit10";
2167 case I915_BIT_6_SWIZZLE_9_11:
2168 return "bit9/bit11";
2169 case I915_BIT_6_SWIZZLE_9_10_11:
2170 return "bit9/bit10/bit11";
2171 case I915_BIT_6_SWIZZLE_9_17:
2172 return "bit9/bit17";
2173 case I915_BIT_6_SWIZZLE_9_10_17:
2174 return "bit9/bit10/bit17";
2175 case I915_BIT_6_SWIZZLE_UNKNOWN:
2176 return "unknown";
2177 }
2178
2179 return "bug";
2180 }
2181
2182 static int i915_swizzle_info(struct seq_file *m, void *data)
2183 {
2184 struct drm_info_node *node = m->private;
2185 struct drm_device *dev = node->minor->dev;
2186 struct drm_i915_private *dev_priv = dev->dev_private;
2187 int ret;
2188
2189 ret = mutex_lock_interruptible(&dev->struct_mutex);
2190 if (ret)
2191 return ret;
2192 intel_runtime_pm_get(dev_priv);
2193
2194 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2195 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2196 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2197 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2198
2199 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2200 seq_printf(m, "DDC = 0x%08x\n",
2201 I915_READ(DCC));
2202 seq_printf(m, "DDC2 = 0x%08x\n",
2203 I915_READ(DCC2));
2204 seq_printf(m, "C0DRB3 = 0x%04x\n",
2205 I915_READ16(C0DRB3));
2206 seq_printf(m, "C1DRB3 = 0x%04x\n",
2207 I915_READ16(C1DRB3));
2208 } else if (INTEL_INFO(dev)->gen >= 6) {
2209 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2210 I915_READ(MAD_DIMM_C0));
2211 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2212 I915_READ(MAD_DIMM_C1));
2213 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2214 I915_READ(MAD_DIMM_C2));
2215 seq_printf(m, "TILECTL = 0x%08x\n",
2216 I915_READ(TILECTL));
2217 if (INTEL_INFO(dev)->gen >= 8)
2218 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2219 I915_READ(GAMTARBMODE));
2220 else
2221 seq_printf(m, "ARB_MODE = 0x%08x\n",
2222 I915_READ(ARB_MODE));
2223 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2224 I915_READ(DISP_ARB_CTL));
2225 }
2226
2227 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2228 seq_puts(m, "L-shaped memory detected\n");
2229
2230 intel_runtime_pm_put(dev_priv);
2231 mutex_unlock(&dev->struct_mutex);
2232
2233 return 0;
2234 }
2235
2236 static int per_file_ctx(int id, void *ptr, void *data)
2237 {
2238 struct intel_context *ctx = ptr;
2239 struct seq_file *m = data;
2240 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2241
2242 if (!ppgtt) {
2243 seq_printf(m, " no ppgtt for context %d\n",
2244 ctx->user_handle);
2245 return 0;
2246 }
2247
2248 if (i915_gem_context_is_default(ctx))
2249 seq_puts(m, " default context:\n");
2250 else
2251 seq_printf(m, " context %d:\n", ctx->user_handle);
2252 ppgtt->debug_dump(ppgtt, m);
2253
2254 return 0;
2255 }
2256
2257 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2258 {
2259 struct drm_i915_private *dev_priv = dev->dev_private;
2260 struct intel_engine_cs *engine;
2261 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2262 int i;
2263
2264 if (!ppgtt)
2265 return;
2266
2267 for_each_engine(engine, dev_priv) {
2268 seq_printf(m, "%s\n", engine->name);
2269 for (i = 0; i < 4; i++) {
2270 u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2271 pdp <<= 32;
2272 pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2273 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2274 }
2275 }
2276 }
2277
2278 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2279 {
2280 struct drm_i915_private *dev_priv = dev->dev_private;
2281 struct intel_engine_cs *engine;
2282
2283 if (INTEL_INFO(dev)->gen == 6)
2284 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2285
2286 for_each_engine(engine, dev_priv) {
2287 seq_printf(m, "%s\n", engine->name);
2288 if (INTEL_INFO(dev)->gen == 7)
2289 seq_printf(m, "GFX_MODE: 0x%08x\n",
2290 I915_READ(RING_MODE_GEN7(engine)));
2291 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2292 I915_READ(RING_PP_DIR_BASE(engine)));
2293 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2294 I915_READ(RING_PP_DIR_BASE_READ(engine)));
2295 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2296 I915_READ(RING_PP_DIR_DCLV(engine)));
2297 }
2298 if (dev_priv->mm.aliasing_ppgtt) {
2299 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2300
2301 seq_puts(m, "aliasing PPGTT:\n");
2302 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2303
2304 ppgtt->debug_dump(ppgtt, m);
2305 }
2306
2307 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2308 }
2309
2310 static int i915_ppgtt_info(struct seq_file *m, void *data)
2311 {
2312 struct drm_info_node *node = m->private;
2313 struct drm_device *dev = node->minor->dev;
2314 struct drm_i915_private *dev_priv = dev->dev_private;
2315 struct drm_file *file;
2316
2317 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2318 if (ret)
2319 return ret;
2320 intel_runtime_pm_get(dev_priv);
2321
2322 if (INTEL_INFO(dev)->gen >= 8)
2323 gen8_ppgtt_info(m, dev);
2324 else if (INTEL_INFO(dev)->gen >= 6)
2325 gen6_ppgtt_info(m, dev);
2326
2327 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2328 struct drm_i915_file_private *file_priv = file->driver_priv;
2329 struct task_struct *task;
2330
2331 task = get_pid_task(file->pid, PIDTYPE_PID);
2332 if (!task) {
2333 ret = -ESRCH;
2334 goto out_put;
2335 }
2336 seq_printf(m, "\nproc: %s\n", task->comm);
2337 put_task_struct(task);
2338 idr_for_each(&file_priv->context_idr, per_file_ctx,
2339 (void *)(unsigned long)m);
2340 }
2341
2342 out_put:
2343 intel_runtime_pm_put(dev_priv);
2344 mutex_unlock(&dev->struct_mutex);
2345
2346 return ret;
2347 }
2348
2349 static int count_irq_waiters(struct drm_i915_private *i915)
2350 {
2351 struct intel_engine_cs *engine;
2352 int count = 0;
2353
2354 for_each_engine(engine, i915)
2355 count += engine->irq_refcount;
2356
2357 return count;
2358 }
2359
2360 static int i915_rps_boost_info(struct seq_file *m, void *data)
2361 {
2362 struct drm_info_node *node = m->private;
2363 struct drm_device *dev = node->minor->dev;
2364 struct drm_i915_private *dev_priv = dev->dev_private;
2365 struct drm_file *file;
2366
2367 seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2368 seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
2369 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2370 seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2371 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2372 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2373 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2374 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2375 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2376 spin_lock(&dev_priv->rps.client_lock);
2377 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2378 struct drm_i915_file_private *file_priv = file->driver_priv;
2379 struct task_struct *task;
2380
2381 rcu_read_lock();
2382 task = pid_task(file->pid, PIDTYPE_PID);
2383 seq_printf(m, "%s [%d]: %d boosts%s\n",
2384 task ? task->comm : "<unknown>",
2385 task ? task->pid : -1,
2386 file_priv->rps.boosts,
2387 list_empty(&file_priv->rps.link) ? "" : ", active");
2388 rcu_read_unlock();
2389 }
2390 seq_printf(m, "Semaphore boosts: %d%s\n",
2391 dev_priv->rps.semaphores.boosts,
2392 list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");
2393 seq_printf(m, "MMIO flip boosts: %d%s\n",
2394 dev_priv->rps.mmioflips.boosts,
2395 list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
2396 seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
2397 spin_unlock(&dev_priv->rps.client_lock);
2398
2399 return 0;
2400 }
2401
2402 static int i915_llc(struct seq_file *m, void *data)
2403 {
2404 struct drm_info_node *node = m->private;
2405 struct drm_device *dev = node->minor->dev;
2406 struct drm_i915_private *dev_priv = dev->dev_private;
2407 const bool edram = INTEL_GEN(dev_priv) > 8;
2408
2409 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2410 seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2411 intel_uncore_edram_size(dev_priv)/1024/1024);
2412
2413 return 0;
2414 }
2415
2416 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2417 {
2418 struct drm_info_node *node = m->private;
2419 struct drm_i915_private *dev_priv = node->minor->dev->dev_private;
2420 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2421 u32 tmp, i;
2422
2423 if (!HAS_GUC_UCODE(dev_priv))
2424 return 0;
2425
2426 seq_printf(m, "GuC firmware status:\n");
2427 seq_printf(m, "\tpath: %s\n",
2428 guc_fw->guc_fw_path);
2429 seq_printf(m, "\tfetch: %s\n",
2430 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2431 seq_printf(m, "\tload: %s\n",
2432 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2433 seq_printf(m, "\tversion wanted: %d.%d\n",
2434 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2435 seq_printf(m, "\tversion found: %d.%d\n",
2436 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2437 seq_printf(m, "\theader: offset is %d; size = %d\n",
2438 guc_fw->header_offset, guc_fw->header_size);
2439 seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2440 guc_fw->ucode_offset, guc_fw->ucode_size);
2441 seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2442 guc_fw->rsa_offset, guc_fw->rsa_size);
2443
2444 tmp = I915_READ(GUC_STATUS);
2445
2446 seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2447 seq_printf(m, "\tBootrom status = 0x%x\n",
2448 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2449 seq_printf(m, "\tuKernel status = 0x%x\n",
2450 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2451 seq_printf(m, "\tMIA Core status = 0x%x\n",
2452 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2453 seq_puts(m, "\nScratch registers:\n");
2454 for (i = 0; i < 16; i++)
2455 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2456
2457 return 0;
2458 }
2459
2460 static void i915_guc_client_info(struct seq_file *m,
2461 struct drm_i915_private *dev_priv,
2462 struct i915_guc_client *client)
2463 {
2464 struct intel_engine_cs *engine;
2465 uint64_t tot = 0;
2466
2467 seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2468 client->priority, client->ctx_index, client->proc_desc_offset);
2469 seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2470 client->doorbell_id, client->doorbell_offset, client->cookie);
2471 seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2472 client->wq_size, client->wq_offset, client->wq_tail);
2473
2474 seq_printf(m, "\tFailed to queue: %u\n", client->q_fail);
2475 seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2476 seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2477
2478 for_each_engine(engine, dev_priv) {
2479 seq_printf(m, "\tSubmissions: %llu %s\n",
2480 client->submissions[engine->guc_id],
2481 engine->name);
2482 tot += client->submissions[engine->guc_id];
2483 }
2484 seq_printf(m, "\tTotal: %llu\n", tot);
2485 }
2486
2487 static int i915_guc_info(struct seq_file *m, void *data)
2488 {
2489 struct drm_info_node *node = m->private;
2490 struct drm_device *dev = node->minor->dev;
2491 struct drm_i915_private *dev_priv = dev->dev_private;
2492 struct intel_guc guc;
2493 struct i915_guc_client client = {};
2494 struct intel_engine_cs *engine;
2495 u64 total = 0;
2496
2497 if (!HAS_GUC_SCHED(dev_priv))
2498 return 0;
2499
2500 if (mutex_lock_interruptible(&dev->struct_mutex))
2501 return 0;
2502
2503 /* Take a local copy of the GuC data, so we can dump it at leisure */
2504 guc = dev_priv->guc;
2505 if (guc.execbuf_client)
2506 client = *guc.execbuf_client;
2507
2508 mutex_unlock(&dev->struct_mutex);
2509
2510 seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2511 seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2512 seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2513 seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2514 seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2515
2516 seq_printf(m, "\nGuC submissions:\n");
2517 for_each_engine(engine, dev_priv) {
2518 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
2519 engine->name, guc.submissions[engine->guc_id],
2520 guc.last_seqno[engine->guc_id]);
2521 total += guc.submissions[engine->guc_id];
2522 }
2523 seq_printf(m, "\t%s: %llu\n", "Total", total);
2524
2525 seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2526 i915_guc_client_info(m, dev_priv, &client);
2527
2528 /* Add more as required ... */
2529
2530 return 0;
2531 }
2532
2533 static int i915_guc_log_dump(struct seq_file *m, void *data)
2534 {
2535 struct drm_info_node *node = m->private;
2536 struct drm_device *dev = node->minor->dev;
2537 struct drm_i915_private *dev_priv = dev->dev_private;
2538 struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;
2539 u32 *log;
2540 int i = 0, pg;
2541
2542 if (!log_obj)
2543 return 0;
2544
2545 for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) {
2546 log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));
2547
2548 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2549 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2550 *(log + i), *(log + i + 1),
2551 *(log + i + 2), *(log + i + 3));
2552
2553 kunmap_atomic(log);
2554 }
2555
2556 seq_putc(m, '\n');
2557
2558 return 0;
2559 }
2560
2561 static int i915_edp_psr_status(struct seq_file *m, void *data)
2562 {
2563 struct drm_info_node *node = m->private;
2564 struct drm_device *dev = node->minor->dev;
2565 struct drm_i915_private *dev_priv = dev->dev_private;
2566 u32 psrperf = 0;
2567 u32 stat[3];
2568 enum pipe pipe;
2569 bool enabled = false;
2570
2571 if (!HAS_PSR(dev)) {
2572 seq_puts(m, "PSR not supported\n");
2573 return 0;
2574 }
2575
2576 intel_runtime_pm_get(dev_priv);
2577
2578 mutex_lock(&dev_priv->psr.lock);
2579 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2580 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2581 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2582 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2583 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2584 dev_priv->psr.busy_frontbuffer_bits);
2585 seq_printf(m, "Re-enable work scheduled: %s\n",
2586 yesno(work_busy(&dev_priv->psr.work.work)));
2587
2588 if (HAS_DDI(dev))
2589 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2590 else {
2591 for_each_pipe(dev_priv, pipe) {
2592 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2593 VLV_EDP_PSR_CURR_STATE_MASK;
2594 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2595 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2596 enabled = true;
2597 }
2598 }
2599
2600 seq_printf(m, "Main link in standby mode: %s\n",
2601 yesno(dev_priv->psr.link_standby));
2602
2603 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2604
2605 if (!HAS_DDI(dev))
2606 for_each_pipe(dev_priv, pipe) {
2607 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2608 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2609 seq_printf(m, " pipe %c", pipe_name(pipe));
2610 }
2611 seq_puts(m, "\n");
2612
2613 /*
2614 * VLV/CHV PSR has no kind of performance counter
2615 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2616 */
2617 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2618 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2619 EDP_PSR_PERF_CNT_MASK;
2620
2621 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2622 }
2623 mutex_unlock(&dev_priv->psr.lock);
2624
2625 intel_runtime_pm_put(dev_priv);
2626 return 0;
2627 }
2628
2629 static int i915_sink_crc(struct seq_file *m, void *data)
2630 {
2631 struct drm_info_node *node = m->private;
2632 struct drm_device *dev = node->minor->dev;
2633 struct intel_encoder *encoder;
2634 struct intel_connector *connector;
2635 struct intel_dp *intel_dp = NULL;
2636 int ret;
2637 u8 crc[6];
2638
2639 drm_modeset_lock_all(dev);
2640 for_each_intel_connector(dev, connector) {
2641
2642 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2643 continue;
2644
2645 if (!connector->base.encoder)
2646 continue;
2647
2648 encoder = to_intel_encoder(connector->base.encoder);
2649 if (encoder->type != INTEL_OUTPUT_EDP)
2650 continue;
2651
2652 intel_dp = enc_to_intel_dp(&encoder->base);
2653
2654 ret = intel_dp_sink_crc(intel_dp, crc);
2655 if (ret)
2656 goto out;
2657
2658 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2659 crc[0], crc[1], crc[2],
2660 crc[3], crc[4], crc[5]);
2661 goto out;
2662 }
2663 ret = -ENODEV;
2664 out:
2665 drm_modeset_unlock_all(dev);
2666 return ret;
2667 }
2668
2669 static int i915_energy_uJ(struct seq_file *m, void *data)
2670 {
2671 struct drm_info_node *node = m->private;
2672 struct drm_device *dev = node->minor->dev;
2673 struct drm_i915_private *dev_priv = dev->dev_private;
2674 u64 power;
2675 u32 units;
2676
2677 if (INTEL_INFO(dev)->gen < 6)
2678 return -ENODEV;
2679
2680 intel_runtime_pm_get(dev_priv);
2681
2682 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2683 power = (power & 0x1f00) >> 8;
2684 units = 1000000 / (1 << power); /* convert to uJ */
2685 power = I915_READ(MCH_SECP_NRG_STTS);
2686 power *= units;
2687
2688 intel_runtime_pm_put(dev_priv);
2689
2690 seq_printf(m, "%llu", (long long unsigned)power);
2691
2692 return 0;
2693 }
2694
2695 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2696 {
2697 struct drm_info_node *node = m->private;
2698 struct drm_device *dev = node->minor->dev;
2699 struct drm_i915_private *dev_priv = dev->dev_private;
2700
2701 if (!HAS_RUNTIME_PM(dev_priv))
2702 seq_puts(m, "Runtime power management not supported\n");
2703
2704 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2705 seq_printf(m, "IRQs disabled: %s\n",
2706 yesno(!intel_irqs_enabled(dev_priv)));
2707 #ifdef CONFIG_PM
2708 seq_printf(m, "Usage count: %d\n",
2709 atomic_read(&dev->dev->power.usage_count));
2710 #else
2711 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2712 #endif
2713 seq_printf(m, "PCI device power state: %s [%d]\n",
2714 pci_power_name(dev_priv->dev->pdev->current_state),
2715 dev_priv->dev->pdev->current_state);
2716
2717 return 0;
2718 }
2719
2720 static int i915_power_domain_info(struct seq_file *m, void *unused)
2721 {
2722 struct drm_info_node *node = m->private;
2723 struct drm_device *dev = node->minor->dev;
2724 struct drm_i915_private *dev_priv = dev->dev_private;
2725 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2726 int i;
2727
2728 mutex_lock(&power_domains->lock);
2729
2730 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2731 for (i = 0; i < power_domains->power_well_count; i++) {
2732 struct i915_power_well *power_well;
2733 enum intel_display_power_domain power_domain;
2734
2735 power_well = &power_domains->power_wells[i];
2736 seq_printf(m, "%-25s %d\n", power_well->name,
2737 power_well->count);
2738
2739 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2740 power_domain++) {
2741 if (!(BIT(power_domain) & power_well->domains))
2742 continue;
2743
2744 seq_printf(m, " %-23s %d\n",
2745 intel_display_power_domain_str(power_domain),
2746 power_domains->domain_use_count[power_domain]);
2747 }
2748 }
2749
2750 mutex_unlock(&power_domains->lock);
2751
2752 return 0;
2753 }
2754
2755 static int i915_dmc_info(struct seq_file *m, void *unused)
2756 {
2757 struct drm_info_node *node = m->private;
2758 struct drm_device *dev = node->minor->dev;
2759 struct drm_i915_private *dev_priv = dev->dev_private;
2760 struct intel_csr *csr;
2761
2762 if (!HAS_CSR(dev)) {
2763 seq_puts(m, "not supported\n");
2764 return 0;
2765 }
2766
2767 csr = &dev_priv->csr;
2768
2769 intel_runtime_pm_get(dev_priv);
2770
2771 seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2772 seq_printf(m, "path: %s\n", csr->fw_path);
2773
2774 if (!csr->dmc_payload)
2775 goto out;
2776
2777 seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2778 CSR_VERSION_MINOR(csr->version));
2779
2780 if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
2781 seq_printf(m, "DC3 -> DC5 count: %d\n",
2782 I915_READ(SKL_CSR_DC3_DC5_COUNT));
2783 seq_printf(m, "DC5 -> DC6 count: %d\n",
2784 I915_READ(SKL_CSR_DC5_DC6_COUNT));
2785 } else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) {
2786 seq_printf(m, "DC3 -> DC5 count: %d\n",
2787 I915_READ(BXT_CSR_DC3_DC5_COUNT));
2788 }
2789
2790 out:
2791 seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2792 seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2793 seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2794
2795 intel_runtime_pm_put(dev_priv);
2796
2797 return 0;
2798 }
2799
2800 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2801 struct drm_display_mode *mode)
2802 {
2803 int i;
2804
2805 for (i = 0; i < tabs; i++)
2806 seq_putc(m, '\t');
2807
2808 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2809 mode->base.id, mode->name,
2810 mode->vrefresh, mode->clock,
2811 mode->hdisplay, mode->hsync_start,
2812 mode->hsync_end, mode->htotal,
2813 mode->vdisplay, mode->vsync_start,
2814 mode->vsync_end, mode->vtotal,
2815 mode->type, mode->flags);
2816 }
2817
2818 static void intel_encoder_info(struct seq_file *m,
2819 struct intel_crtc *intel_crtc,
2820 struct intel_encoder *intel_encoder)
2821 {
2822 struct drm_info_node *node = m->private;
2823 struct drm_device *dev = node->minor->dev;
2824 struct drm_crtc *crtc = &intel_crtc->base;
2825 struct intel_connector *intel_connector;
2826 struct drm_encoder *encoder;
2827
2828 encoder = &intel_encoder->base;
2829 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2830 encoder->base.id, encoder->name);
2831 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2832 struct drm_connector *connector = &intel_connector->base;
2833 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2834 connector->base.id,
2835 connector->name,
2836 drm_get_connector_status_name(connector->status));
2837 if (connector->status == connector_status_connected) {
2838 struct drm_display_mode *mode = &crtc->mode;
2839 seq_printf(m, ", mode:\n");
2840 intel_seq_print_mode(m, 2, mode);
2841 } else {
2842 seq_putc(m, '\n');
2843 }
2844 }
2845 }
2846
2847 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2848 {
2849 struct drm_info_node *node = m->private;
2850 struct drm_device *dev = node->minor->dev;
2851 struct drm_crtc *crtc = &intel_crtc->base;
2852 struct intel_encoder *intel_encoder;
2853 struct drm_plane_state *plane_state = crtc->primary->state;
2854 struct drm_framebuffer *fb = plane_state->fb;
2855
2856 if (fb)
2857 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2858 fb->base.id, plane_state->src_x >> 16,
2859 plane_state->src_y >> 16, fb->width, fb->height);
2860 else
2861 seq_puts(m, "\tprimary plane disabled\n");
2862 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2863 intel_encoder_info(m, intel_crtc, intel_encoder);
2864 }
2865
2866 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2867 {
2868 struct drm_display_mode *mode = panel->fixed_mode;
2869
2870 seq_printf(m, "\tfixed mode:\n");
2871 intel_seq_print_mode(m, 2, mode);
2872 }
2873
2874 static void intel_dp_info(struct seq_file *m,
2875 struct intel_connector *intel_connector)
2876 {
2877 struct intel_encoder *intel_encoder = intel_connector->encoder;
2878 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2879
2880 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2881 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2882 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2883 intel_panel_info(m, &intel_connector->panel);
2884 }
2885
2886 static void intel_dp_mst_info(struct seq_file *m,
2887 struct intel_connector *intel_connector)
2888 {
2889 struct intel_encoder *intel_encoder = intel_connector->encoder;
2890 struct intel_dp_mst_encoder *intel_mst =
2891 enc_to_mst(&intel_encoder->base);
2892 struct intel_digital_port *intel_dig_port = intel_mst->primary;
2893 struct intel_dp *intel_dp = &intel_dig_port->dp;
2894 bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr,
2895 intel_connector->port);
2896
2897 seq_printf(m, "\taudio support: %s\n", yesno(has_audio));
2898 }
2899
2900 static void intel_hdmi_info(struct seq_file *m,
2901 struct intel_connector *intel_connector)
2902 {
2903 struct intel_encoder *intel_encoder = intel_connector->encoder;
2904 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2905
2906 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2907 }
2908
2909 static void intel_lvds_info(struct seq_file *m,
2910 struct intel_connector *intel_connector)
2911 {
2912 intel_panel_info(m, &intel_connector->panel);
2913 }
2914
2915 static void intel_connector_info(struct seq_file *m,
2916 struct drm_connector *connector)
2917 {
2918 struct intel_connector *intel_connector = to_intel_connector(connector);
2919 struct intel_encoder *intel_encoder = intel_connector->encoder;
2920 struct drm_display_mode *mode;
2921
2922 seq_printf(m, "connector %d: type %s, status: %s\n",
2923 connector->base.id, connector->name,
2924 drm_get_connector_status_name(connector->status));
2925 if (connector->status == connector_status_connected) {
2926 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2927 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2928 connector->display_info.width_mm,
2929 connector->display_info.height_mm);
2930 seq_printf(m, "\tsubpixel order: %s\n",
2931 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2932 seq_printf(m, "\tCEA rev: %d\n",
2933 connector->display_info.cea_rev);
2934 }
2935 if (intel_encoder) {
2936 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2937 intel_encoder->type == INTEL_OUTPUT_EDP)
2938 intel_dp_info(m, intel_connector);
2939 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2940 intel_hdmi_info(m, intel_connector);
2941 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2942 intel_lvds_info(m, intel_connector);
2943 else if (intel_encoder->type == INTEL_OUTPUT_DP_MST)
2944 intel_dp_mst_info(m, intel_connector);
2945 }
2946
2947 seq_printf(m, "\tmodes:\n");
2948 list_for_each_entry(mode, &connector->modes, head)
2949 intel_seq_print_mode(m, 2, mode);
2950 }
2951
2952 static bool cursor_active(struct drm_device *dev, int pipe)
2953 {
2954 struct drm_i915_private *dev_priv = dev->dev_private;
2955 u32 state;
2956
2957 if (IS_845G(dev) || IS_I865G(dev))
2958 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
2959 else
2960 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2961
2962 return state;
2963 }
2964
2965 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2966 {
2967 struct drm_i915_private *dev_priv = dev->dev_private;
2968 u32 pos;
2969
2970 pos = I915_READ(CURPOS(pipe));
2971
2972 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2973 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2974 *x = -*x;
2975
2976 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2977 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2978 *y = -*y;
2979
2980 return cursor_active(dev, pipe);
2981 }
2982
2983 static const char *plane_type(enum drm_plane_type type)
2984 {
2985 switch (type) {
2986 case DRM_PLANE_TYPE_OVERLAY:
2987 return "OVL";
2988 case DRM_PLANE_TYPE_PRIMARY:
2989 return "PRI";
2990 case DRM_PLANE_TYPE_CURSOR:
2991 return "CUR";
2992 /*
2993 * Deliberately omitting default: to generate compiler warnings
2994 * when a new drm_plane_type gets added.
2995 */
2996 }
2997
2998 return "unknown";
2999 }
3000
3001 static const char *plane_rotation(unsigned int rotation)
3002 {
3003 static char buf[48];
3004 /*
3005 * According to doc only one DRM_ROTATE_ is allowed but this
3006 * will print them all to visualize if the values are misused
3007 */
3008 snprintf(buf, sizeof(buf),
3009 "%s%s%s%s%s%s(0x%08x)",
3010 (rotation & BIT(DRM_ROTATE_0)) ? "0 " : "",
3011 (rotation & BIT(DRM_ROTATE_90)) ? "90 " : "",
3012 (rotation & BIT(DRM_ROTATE_180)) ? "180 " : "",
3013 (rotation & BIT(DRM_ROTATE_270)) ? "270 " : "",
3014 (rotation & BIT(DRM_REFLECT_X)) ? "FLIPX " : "",
3015 (rotation & BIT(DRM_REFLECT_Y)) ? "FLIPY " : "",
3016 rotation);
3017
3018 return buf;
3019 }
3020
3021 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3022 {
3023 struct drm_info_node *node = m->private;
3024 struct drm_device *dev = node->minor->dev;
3025 struct intel_plane *intel_plane;
3026
3027 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3028 struct drm_plane_state *state;
3029 struct drm_plane *plane = &intel_plane->base;
3030
3031 if (!plane->state) {
3032 seq_puts(m, "plane->state is NULL!\n");
3033 continue;
3034 }
3035
3036 state = plane->state;
3037
3038 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3039 plane->base.id,
3040 plane_type(intel_plane->base.type),
3041 state->crtc_x, state->crtc_y,
3042 state->crtc_w, state->crtc_h,
3043 (state->src_x >> 16),
3044 ((state->src_x & 0xffff) * 15625) >> 10,
3045 (state->src_y >> 16),
3046 ((state->src_y & 0xffff) * 15625) >> 10,
3047 (state->src_w >> 16),
3048 ((state->src_w & 0xffff) * 15625) >> 10,
3049 (state->src_h >> 16),
3050 ((state->src_h & 0xffff) * 15625) >> 10,
3051 state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A",
3052 plane_rotation(state->rotation));
3053 }
3054 }
3055
3056 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3057 {
3058 struct intel_crtc_state *pipe_config;
3059 int num_scalers = intel_crtc->num_scalers;
3060 int i;
3061
3062 pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3063
3064 /* Not all platformas have a scaler */
3065 if (num_scalers) {
3066 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3067 num_scalers,
3068 pipe_config->scaler_state.scaler_users,
3069 pipe_config->scaler_state.scaler_id);
3070
3071 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3072 struct intel_scaler *sc =
3073 &pipe_config->scaler_state.scalers[i];
3074
3075 seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3076 i, yesno(sc->in_use), sc->mode);
3077 }
3078 seq_puts(m, "\n");
3079 } else {
3080 seq_puts(m, "\tNo scalers available on this platform\n");
3081 }
3082 }
3083
3084 static int i915_display_info(struct seq_file *m, void *unused)
3085 {
3086 struct drm_info_node *node = m->private;
3087 struct drm_device *dev = node->minor->dev;
3088 struct drm_i915_private *dev_priv = dev->dev_private;
3089 struct intel_crtc *crtc;
3090 struct drm_connector *connector;
3091
3092 intel_runtime_pm_get(dev_priv);
3093 drm_modeset_lock_all(dev);
3094 seq_printf(m, "CRTC info\n");
3095 seq_printf(m, "---------\n");
3096 for_each_intel_crtc(dev, crtc) {
3097 bool active;
3098 struct intel_crtc_state *pipe_config;
3099 int x, y;
3100
3101 pipe_config = to_intel_crtc_state(crtc->base.state);
3102
3103 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3104 crtc->base.base.id, pipe_name(crtc->pipe),
3105 yesno(pipe_config->base.active),
3106 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3107 yesno(pipe_config->dither), pipe_config->pipe_bpp);
3108
3109 if (pipe_config->base.active) {
3110 intel_crtc_info(m, crtc);
3111
3112 active = cursor_position(dev, crtc->pipe, &x, &y);
3113 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3114 yesno(crtc->cursor_base),
3115 x, y, crtc->base.cursor->state->crtc_w,
3116 crtc->base.cursor->state->crtc_h,
3117 crtc->cursor_addr, yesno(active));
3118 intel_scaler_info(m, crtc);
3119 intel_plane_info(m, crtc);
3120 }
3121
3122 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3123 yesno(!crtc->cpu_fifo_underrun_disabled),
3124 yesno(!crtc->pch_fifo_underrun_disabled));
3125 }
3126
3127 seq_printf(m, "\n");
3128 seq_printf(m, "Connector info\n");
3129 seq_printf(m, "--------------\n");
3130 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3131 intel_connector_info(m, connector);
3132 }
3133 drm_modeset_unlock_all(dev);
3134 intel_runtime_pm_put(dev_priv);
3135
3136 return 0;
3137 }
3138
3139 static int i915_semaphore_status(struct seq_file *m, void *unused)
3140 {
3141 struct drm_info_node *node = (struct drm_info_node *) m->private;
3142 struct drm_device *dev = node->minor->dev;
3143 struct drm_i915_private *dev_priv = dev->dev_private;
3144 struct intel_engine_cs *engine;
3145 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
3146 enum intel_engine_id id;
3147 int j, ret;
3148
3149 if (!i915_semaphore_is_enabled(dev)) {
3150 seq_puts(m, "Semaphores are disabled\n");
3151 return 0;
3152 }
3153
3154 ret = mutex_lock_interruptible(&dev->struct_mutex);
3155 if (ret)
3156 return ret;
3157 intel_runtime_pm_get(dev_priv);
3158
3159 if (IS_BROADWELL(dev)) {
3160 struct page *page;
3161 uint64_t *seqno;
3162
3163 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
3164
3165 seqno = (uint64_t *)kmap_atomic(page);
3166 for_each_engine_id(engine, dev_priv, id) {
3167 uint64_t offset;
3168
3169 seq_printf(m, "%s\n", engine->name);
3170
3171 seq_puts(m, " Last signal:");
3172 for (j = 0; j < num_rings; j++) {
3173 offset = id * I915_NUM_ENGINES + j;
3174 seq_printf(m, "0x%08llx (0x%02llx) ",
3175 seqno[offset], offset * 8);
3176 }
3177 seq_putc(m, '\n');
3178
3179 seq_puts(m, " Last wait: ");
3180 for (j = 0; j < num_rings; j++) {
3181 offset = id + (j * I915_NUM_ENGINES);
3182 seq_printf(m, "0x%08llx (0x%02llx) ",
3183 seqno[offset], offset * 8);
3184 }
3185 seq_putc(m, '\n');
3186
3187 }
3188 kunmap_atomic(seqno);
3189 } else {
3190 seq_puts(m, " Last signal:");
3191 for_each_engine(engine, dev_priv)
3192 for (j = 0; j < num_rings; j++)
3193 seq_printf(m, "0x%08x\n",
3194 I915_READ(engine->semaphore.mbox.signal[j]));
3195 seq_putc(m, '\n');
3196 }
3197
3198 seq_puts(m, "\nSync seqno:\n");
3199 for_each_engine(engine, dev_priv) {
3200 for (j = 0; j < num_rings; j++)
3201 seq_printf(m, " 0x%08x ",
3202 engine->semaphore.sync_seqno[j]);
3203 seq_putc(m, '\n');
3204 }
3205 seq_putc(m, '\n');
3206
3207 intel_runtime_pm_put(dev_priv);
3208 mutex_unlock(&dev->struct_mutex);
3209 return 0;
3210 }
3211
3212 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3213 {
3214 struct drm_info_node *node = (struct drm_info_node *) m->private;
3215 struct drm_device *dev = node->minor->dev;
3216 struct drm_i915_private *dev_priv = dev->dev_private;
3217 int i;
3218
3219 drm_modeset_lock_all(dev);
3220 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3221 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3222
3223 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3224 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3225 pll->config.crtc_mask, pll->active_mask, yesno(pll->on));
3226 seq_printf(m, " tracked hardware state:\n");
3227 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
3228 seq_printf(m, " dpll_md: 0x%08x\n",
3229 pll->config.hw_state.dpll_md);
3230 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
3231 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
3232 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
3233 }
3234 drm_modeset_unlock_all(dev);
3235
3236 return 0;
3237 }
3238
3239 static int i915_wa_registers(struct seq_file *m, void *unused)
3240 {
3241 int i;
3242 int ret;
3243 struct intel_engine_cs *engine;
3244 struct drm_info_node *node = (struct drm_info_node *) m->private;
3245 struct drm_device *dev = node->minor->dev;
3246 struct drm_i915_private *dev_priv = dev->dev_private;
3247 struct i915_workarounds *workarounds = &dev_priv->workarounds;
3248 enum intel_engine_id id;
3249
3250 ret = mutex_lock_interruptible(&dev->struct_mutex);
3251 if (ret)
3252 return ret;
3253
3254 intel_runtime_pm_get(dev_priv);
3255
3256 seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3257 for_each_engine_id(engine, dev_priv, id)
3258 seq_printf(m, "HW whitelist count for %s: %d\n",
3259 engine->name, workarounds->hw_whitelist_count[id]);
3260 for (i = 0; i < workarounds->count; ++i) {
3261 i915_reg_t addr;
3262 u32 mask, value, read;
3263 bool ok;
3264
3265 addr = workarounds->reg[i].addr;
3266 mask = workarounds->reg[i].mask;
3267 value = workarounds->reg[i].value;
3268 read = I915_READ(addr);
3269 ok = (value & mask) == (read & mask);
3270 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3271 i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3272 }
3273
3274 intel_runtime_pm_put(dev_priv);
3275 mutex_unlock(&dev->struct_mutex);
3276
3277 return 0;
3278 }
3279
3280 static int i915_ddb_info(struct seq_file *m, void *unused)
3281 {
3282 struct drm_info_node *node = m->private;
3283 struct drm_device *dev = node->minor->dev;
3284 struct drm_i915_private *dev_priv = dev->dev_private;
3285 struct skl_ddb_allocation *ddb;
3286 struct skl_ddb_entry *entry;
3287 enum pipe pipe;
3288 int plane;
3289
3290 if (INTEL_INFO(dev)->gen < 9)
3291 return 0;
3292
3293 drm_modeset_lock_all(dev);
3294
3295 ddb = &dev_priv->wm.skl_hw.ddb;
3296
3297 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3298
3299 for_each_pipe(dev_priv, pipe) {
3300 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3301
3302 for_each_plane(dev_priv, pipe, plane) {
3303 entry = &ddb->plane[pipe][plane];
3304 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
3305 entry->start, entry->end,
3306 skl_ddb_entry_size(entry));
3307 }
3308
3309 entry = &ddb->plane[pipe][PLANE_CURSOR];
3310 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
3311 entry->end, skl_ddb_entry_size(entry));
3312 }
3313
3314 drm_modeset_unlock_all(dev);
3315
3316 return 0;
3317 }
3318
3319 static void drrs_status_per_crtc(struct seq_file *m,
3320 struct drm_device *dev, struct intel_crtc *intel_crtc)
3321 {
3322 struct intel_encoder *intel_encoder;
3323 struct drm_i915_private *dev_priv = dev->dev_private;
3324 struct i915_drrs *drrs = &dev_priv->drrs;
3325 int vrefresh = 0;
3326
3327 for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
3328 /* Encoder connected on this CRTC */
3329 switch (intel_encoder->type) {
3330 case INTEL_OUTPUT_EDP:
3331 seq_puts(m, "eDP:\n");
3332 break;
3333 case INTEL_OUTPUT_DSI:
3334 seq_puts(m, "DSI:\n");
3335 break;
3336 case INTEL_OUTPUT_HDMI:
3337 seq_puts(m, "HDMI:\n");
3338 break;
3339 case INTEL_OUTPUT_DISPLAYPORT:
3340 seq_puts(m, "DP:\n");
3341 break;
3342 default:
3343 seq_printf(m, "Other encoder (id=%d).\n",
3344 intel_encoder->type);
3345 return;
3346 }
3347 }
3348
3349 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3350 seq_puts(m, "\tVBT: DRRS_type: Static");
3351 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3352 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3353 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3354 seq_puts(m, "\tVBT: DRRS_type: None");
3355 else
3356 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3357
3358 seq_puts(m, "\n\n");
3359
3360 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3361 struct intel_panel *panel;
3362
3363 mutex_lock(&drrs->mutex);
3364 /* DRRS Supported */
3365 seq_puts(m, "\tDRRS Supported: Yes\n");
3366
3367 /* disable_drrs() will make drrs->dp NULL */
3368 if (!drrs->dp) {
3369 seq_puts(m, "Idleness DRRS: Disabled");
3370 mutex_unlock(&drrs->mutex);
3371 return;
3372 }
3373
3374 panel = &drrs->dp->attached_connector->panel;
3375 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3376 drrs->busy_frontbuffer_bits);
3377
3378 seq_puts(m, "\n\t\t");
3379 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3380 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3381 vrefresh = panel->fixed_mode->vrefresh;
3382 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3383 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3384 vrefresh = panel->downclock_mode->vrefresh;
3385 } else {
3386 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3387 drrs->refresh_rate_type);
3388 mutex_unlock(&drrs->mutex);
3389 return;
3390 }
3391 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3392
3393 seq_puts(m, "\n\t\t");
3394 mutex_unlock(&drrs->mutex);
3395 } else {
3396 /* DRRS not supported. Print the VBT parameter*/
3397 seq_puts(m, "\tDRRS Supported : No");
3398 }
3399 seq_puts(m, "\n");
3400 }
3401
3402 static int i915_drrs_status(struct seq_file *m, void *unused)
3403 {
3404 struct drm_info_node *node = m->private;
3405 struct drm_device *dev = node->minor->dev;
3406 struct intel_crtc *intel_crtc;
3407 int active_crtc_cnt = 0;
3408
3409 for_each_intel_crtc(dev, intel_crtc) {
3410 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3411
3412 if (intel_crtc->base.state->active) {
3413 active_crtc_cnt++;
3414 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3415
3416 drrs_status_per_crtc(m, dev, intel_crtc);
3417 }
3418
3419 drm_modeset_unlock(&intel_crtc->base.mutex);
3420 }
3421
3422 if (!active_crtc_cnt)
3423 seq_puts(m, "No active crtc found\n");
3424
3425 return 0;
3426 }
3427
3428 struct pipe_crc_info {
3429 const char *name;
3430 struct drm_device *dev;
3431 enum pipe pipe;
3432 };
3433
3434 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3435 {
3436 struct drm_info_node *node = (struct drm_info_node *) m->private;
3437 struct drm_device *dev = node->minor->dev;
3438 struct drm_encoder *encoder;
3439 struct intel_encoder *intel_encoder;
3440 struct intel_digital_port *intel_dig_port;
3441 drm_modeset_lock_all(dev);
3442 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3443 intel_encoder = to_intel_encoder(encoder);
3444 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3445 continue;
3446 intel_dig_port = enc_to_dig_port(encoder);
3447 if (!intel_dig_port->dp.can_mst)
3448 continue;
3449
3450 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3451 }
3452 drm_modeset_unlock_all(dev);
3453 return 0;
3454 }
3455
3456 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3457 {
3458 struct pipe_crc_info *info = inode->i_private;
3459 struct drm_i915_private *dev_priv = info->dev->dev_private;
3460 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3461
3462 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3463 return -ENODEV;
3464
3465 spin_lock_irq(&pipe_crc->lock);
3466
3467 if (pipe_crc->opened) {
3468 spin_unlock_irq(&pipe_crc->lock);
3469 return -EBUSY; /* already open */
3470 }
3471
3472 pipe_crc->opened = true;
3473 filep->private_data = inode->i_private;
3474
3475 spin_unlock_irq(&pipe_crc->lock);
3476
3477 return 0;
3478 }
3479
3480 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3481 {
3482 struct pipe_crc_info *info = inode->i_private;
3483 struct drm_i915_private *dev_priv = info->dev->dev_private;
3484 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3485
3486 spin_lock_irq(&pipe_crc->lock);
3487 pipe_crc->opened = false;
3488 spin_unlock_irq(&pipe_crc->lock);
3489
3490 return 0;
3491 }
3492
3493 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3494 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3495 /* account for \'0' */
3496 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3497
3498 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3499 {
3500 assert_spin_locked(&pipe_crc->lock);
3501 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3502 INTEL_PIPE_CRC_ENTRIES_NR);
3503 }
3504
3505 static ssize_t
3506 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3507 loff_t *pos)
3508 {
3509 struct pipe_crc_info *info = filep->private_data;
3510 struct drm_device *dev = info->dev;
3511 struct drm_i915_private *dev_priv = dev->dev_private;
3512 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3513 char buf[PIPE_CRC_BUFFER_LEN];
3514 int n_entries;
3515 ssize_t bytes_read;
3516
3517 /*
3518 * Don't allow user space to provide buffers not big enough to hold
3519 * a line of data.
3520 */
3521 if (count < PIPE_CRC_LINE_LEN)
3522 return -EINVAL;
3523
3524 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3525 return 0;
3526
3527 /* nothing to read */
3528 spin_lock_irq(&pipe_crc->lock);
3529 while (pipe_crc_data_count(pipe_crc) == 0) {
3530 int ret;
3531
3532 if (filep->f_flags & O_NONBLOCK) {
3533 spin_unlock_irq(&pipe_crc->lock);
3534 return -EAGAIN;
3535 }
3536
3537 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3538 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3539 if (ret) {
3540 spin_unlock_irq(&pipe_crc->lock);
3541 return ret;
3542 }
3543 }
3544
3545 /* We now have one or more entries to read */
3546 n_entries = count / PIPE_CRC_LINE_LEN;
3547
3548 bytes_read = 0;
3549 while (n_entries > 0) {
3550 struct intel_pipe_crc_entry *entry =
3551 &pipe_crc->entries[pipe_crc->tail];
3552 int ret;
3553
3554 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3555 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3556 break;
3557
3558 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3559 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3560
3561 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3562 "%8u %8x %8x %8x %8x %8x\n",
3563 entry->frame, entry->crc[0],
3564 entry->crc[1], entry->crc[2],
3565 entry->crc[3], entry->crc[4]);
3566
3567 spin_unlock_irq(&pipe_crc->lock);
3568
3569 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
3570 if (ret == PIPE_CRC_LINE_LEN)
3571 return -EFAULT;
3572
3573 user_buf += PIPE_CRC_LINE_LEN;
3574 n_entries--;
3575
3576 spin_lock_irq(&pipe_crc->lock);
3577 }
3578
3579 spin_unlock_irq(&pipe_crc->lock);
3580
3581 return bytes_read;
3582 }
3583
3584 static const struct file_operations i915_pipe_crc_fops = {
3585 .owner = THIS_MODULE,
3586 .open = i915_pipe_crc_open,
3587 .read = i915_pipe_crc_read,
3588 .release = i915_pipe_crc_release,
3589 };
3590
3591 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3592 {
3593 .name = "i915_pipe_A_crc",
3594 .pipe = PIPE_A,
3595 },
3596 {
3597 .name = "i915_pipe_B_crc",
3598 .pipe = PIPE_B,
3599 },
3600 {
3601 .name = "i915_pipe_C_crc",
3602 .pipe = PIPE_C,
3603 },
3604 };
3605
3606 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3607 enum pipe pipe)
3608 {
3609 struct drm_device *dev = minor->dev;
3610 struct dentry *ent;
3611 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3612
3613 info->dev = dev;
3614 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3615 &i915_pipe_crc_fops);
3616 if (!ent)
3617 return -ENOMEM;
3618
3619 return drm_add_fake_info_node(minor, ent, info);
3620 }
3621
3622 static const char * const pipe_crc_sources[] = {
3623 "none",
3624 "plane1",
3625 "plane2",
3626 "pf",
3627 "pipe",
3628 "TV",
3629 "DP-B",
3630 "DP-C",
3631 "DP-D",
3632 "auto",
3633 };
3634
3635 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3636 {
3637 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3638 return pipe_crc_sources[source];
3639 }
3640
3641 static int display_crc_ctl_show(struct seq_file *m, void *data)
3642 {
3643 struct drm_device *dev = m->private;
3644 struct drm_i915_private *dev_priv = dev->dev_private;
3645 int i;
3646
3647 for (i = 0; i < I915_MAX_PIPES; i++)
3648 seq_printf(m, "%c %s\n", pipe_name(i),
3649 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3650
3651 return 0;
3652 }
3653
3654 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3655 {
3656 struct drm_device *dev = inode->i_private;
3657
3658 return single_open(file, display_crc_ctl_show, dev);
3659 }
3660
3661 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3662 uint32_t *val)
3663 {
3664 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3665 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3666
3667 switch (*source) {
3668 case INTEL_PIPE_CRC_SOURCE_PIPE:
3669 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3670 break;
3671 case INTEL_PIPE_CRC_SOURCE_NONE:
3672 *val = 0;
3673 break;
3674 default:
3675 return -EINVAL;
3676 }
3677
3678 return 0;
3679 }
3680
3681 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3682 enum intel_pipe_crc_source *source)
3683 {
3684 struct intel_encoder *encoder;
3685 struct intel_crtc *crtc;
3686 struct intel_digital_port *dig_port;
3687 int ret = 0;
3688
3689 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3690
3691 drm_modeset_lock_all(dev);
3692 for_each_intel_encoder(dev, encoder) {
3693 if (!encoder->base.crtc)
3694 continue;
3695
3696 crtc = to_intel_crtc(encoder->base.crtc);
3697
3698 if (crtc->pipe != pipe)
3699 continue;
3700
3701 switch (encoder->type) {
3702 case INTEL_OUTPUT_TVOUT:
3703 *source = INTEL_PIPE_CRC_SOURCE_TV;
3704 break;
3705 case INTEL_OUTPUT_DISPLAYPORT:
3706 case INTEL_OUTPUT_EDP:
3707 dig_port = enc_to_dig_port(&encoder->base);
3708 switch (dig_port->port) {
3709 case PORT_B:
3710 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3711 break;
3712 case PORT_C:
3713 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3714 break;
3715 case PORT_D:
3716 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3717 break;
3718 default:
3719 WARN(1, "nonexisting DP port %c\n",
3720 port_name(dig_port->port));
3721 break;
3722 }
3723 break;
3724 default:
3725 break;
3726 }
3727 }
3728 drm_modeset_unlock_all(dev);
3729
3730 return ret;
3731 }
3732
3733 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3734 enum pipe pipe,
3735 enum intel_pipe_crc_source *source,
3736 uint32_t *val)
3737 {
3738 struct drm_i915_private *dev_priv = dev->dev_private;
3739 bool need_stable_symbols = false;
3740
3741 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3742 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3743 if (ret)
3744 return ret;
3745 }
3746
3747 switch (*source) {
3748 case INTEL_PIPE_CRC_SOURCE_PIPE:
3749 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3750 break;
3751 case INTEL_PIPE_CRC_SOURCE_DP_B:
3752 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3753 need_stable_symbols = true;
3754 break;
3755 case INTEL_PIPE_CRC_SOURCE_DP_C:
3756 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3757 need_stable_symbols = true;
3758 break;
3759 case INTEL_PIPE_CRC_SOURCE_DP_D:
3760 if (!IS_CHERRYVIEW(dev))
3761 return -EINVAL;
3762 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3763 need_stable_symbols = true;
3764 break;
3765 case INTEL_PIPE_CRC_SOURCE_NONE:
3766 *val = 0;
3767 break;
3768 default:
3769 return -EINVAL;
3770 }
3771
3772 /*
3773 * When the pipe CRC tap point is after the transcoders we need
3774 * to tweak symbol-level features to produce a deterministic series of
3775 * symbols for a given frame. We need to reset those features only once
3776 * a frame (instead of every nth symbol):
3777 * - DC-balance: used to ensure a better clock recovery from the data
3778 * link (SDVO)
3779 * - DisplayPort scrambling: used for EMI reduction
3780 */
3781 if (need_stable_symbols) {
3782 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3783
3784 tmp |= DC_BALANCE_RESET_VLV;
3785 switch (pipe) {
3786 case PIPE_A:
3787 tmp |= PIPE_A_SCRAMBLE_RESET;
3788 break;
3789 case PIPE_B:
3790 tmp |= PIPE_B_SCRAMBLE_RESET;
3791 break;
3792 case PIPE_C:
3793 tmp |= PIPE_C_SCRAMBLE_RESET;
3794 break;
3795 default:
3796 return -EINVAL;
3797 }
3798 I915_WRITE(PORT_DFT2_G4X, tmp);
3799 }
3800
3801 return 0;
3802 }
3803
3804 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3805 enum pipe pipe,
3806 enum intel_pipe_crc_source *source,
3807 uint32_t *val)
3808 {
3809 struct drm_i915_private *dev_priv = dev->dev_private;
3810 bool need_stable_symbols = false;
3811
3812 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3813 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3814 if (ret)
3815 return ret;
3816 }
3817
3818 switch (*source) {
3819 case INTEL_PIPE_CRC_SOURCE_PIPE:
3820 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3821 break;
3822 case INTEL_PIPE_CRC_SOURCE_TV:
3823 if (!SUPPORTS_TV(dev))
3824 return -EINVAL;
3825 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3826 break;
3827 case INTEL_PIPE_CRC_SOURCE_DP_B:
3828 if (!IS_G4X(dev))
3829 return -EINVAL;
3830 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3831 need_stable_symbols = true;
3832 break;
3833 case INTEL_PIPE_CRC_SOURCE_DP_C:
3834 if (!IS_G4X(dev))
3835 return -EINVAL;
3836 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3837 need_stable_symbols = true;
3838 break;
3839 case INTEL_PIPE_CRC_SOURCE_DP_D:
3840 if (!IS_G4X(dev))
3841 return -EINVAL;
3842 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3843 need_stable_symbols = true;
3844 break;
3845 case INTEL_PIPE_CRC_SOURCE_NONE:
3846 *val = 0;
3847 break;
3848 default:
3849 return -EINVAL;
3850 }
3851
3852 /*
3853 * When the pipe CRC tap point is after the transcoders we need
3854 * to tweak symbol-level features to produce a deterministic series of
3855 * symbols for a given frame. We need to reset those features only once
3856 * a frame (instead of every nth symbol):
3857 * - DC-balance: used to ensure a better clock recovery from the data
3858 * link (SDVO)
3859 * - DisplayPort scrambling: used for EMI reduction
3860 */
3861 if (need_stable_symbols) {
3862 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3863
3864 WARN_ON(!IS_G4X(dev));
3865
3866 I915_WRITE(PORT_DFT_I9XX,
3867 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3868
3869 if (pipe == PIPE_A)
3870 tmp |= PIPE_A_SCRAMBLE_RESET;
3871 else
3872 tmp |= PIPE_B_SCRAMBLE_RESET;
3873
3874 I915_WRITE(PORT_DFT2_G4X, tmp);
3875 }
3876
3877 return 0;
3878 }
3879
3880 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3881 enum pipe pipe)
3882 {
3883 struct drm_i915_private *dev_priv = dev->dev_private;
3884 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3885
3886 switch (pipe) {
3887 case PIPE_A:
3888 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3889 break;
3890 case PIPE_B:
3891 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3892 break;
3893 case PIPE_C:
3894 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3895 break;
3896 default:
3897 return;
3898 }
3899 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3900 tmp &= ~DC_BALANCE_RESET_VLV;
3901 I915_WRITE(PORT_DFT2_G4X, tmp);
3902
3903 }
3904
3905 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3906 enum pipe pipe)
3907 {
3908 struct drm_i915_private *dev_priv = dev->dev_private;
3909 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3910
3911 if (pipe == PIPE_A)
3912 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3913 else
3914 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3915 I915_WRITE(PORT_DFT2_G4X, tmp);
3916
3917 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3918 I915_WRITE(PORT_DFT_I9XX,
3919 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3920 }
3921 }
3922
3923 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3924 uint32_t *val)
3925 {
3926 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3927 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3928
3929 switch (*source) {
3930 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3931 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3932 break;
3933 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3934 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3935 break;
3936 case INTEL_PIPE_CRC_SOURCE_PIPE:
3937 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3938 break;
3939 case INTEL_PIPE_CRC_SOURCE_NONE:
3940 *val = 0;
3941 break;
3942 default:
3943 return -EINVAL;
3944 }
3945
3946 return 0;
3947 }
3948
3949 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
3950 {
3951 struct drm_i915_private *dev_priv = dev->dev_private;
3952 struct intel_crtc *crtc =
3953 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3954 struct intel_crtc_state *pipe_config;
3955 struct drm_atomic_state *state;
3956 int ret = 0;
3957
3958 drm_modeset_lock_all(dev);
3959 state = drm_atomic_state_alloc(dev);
3960 if (!state) {
3961 ret = -ENOMEM;
3962 goto out;
3963 }
3964
3965 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
3966 pipe_config = intel_atomic_get_crtc_state(state, crtc);
3967 if (IS_ERR(pipe_config)) {
3968 ret = PTR_ERR(pipe_config);
3969 goto out;
3970 }
3971
3972 pipe_config->pch_pfit.force_thru = enable;
3973 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
3974 pipe_config->pch_pfit.enabled != enable)
3975 pipe_config->base.connectors_changed = true;
3976
3977 ret = drm_atomic_commit(state);
3978 out:
3979 drm_modeset_unlock_all(dev);
3980 WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
3981 if (ret)
3982 drm_atomic_state_free(state);
3983 }
3984
3985 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3986 enum pipe pipe,
3987 enum intel_pipe_crc_source *source,
3988 uint32_t *val)
3989 {
3990 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3991 *source = INTEL_PIPE_CRC_SOURCE_PF;
3992
3993 switch (*source) {
3994 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3995 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3996 break;
3997 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3998 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3999 break;
4000 case INTEL_PIPE_CRC_SOURCE_PF:
4001 if (IS_HASWELL(dev) && pipe == PIPE_A)
4002 hsw_trans_edp_pipe_A_crc_wa(dev, true);
4003
4004 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
4005 break;
4006 case INTEL_PIPE_CRC_SOURCE_NONE:
4007 *val = 0;
4008 break;
4009 default:
4010 return -EINVAL;
4011 }
4012
4013 return 0;
4014 }
4015
4016 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
4017 enum intel_pipe_crc_source source)
4018 {
4019 struct drm_i915_private *dev_priv = dev->dev_private;
4020 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4021 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
4022 pipe));
4023 enum intel_display_power_domain power_domain;
4024 u32 val = 0; /* shut up gcc */
4025 int ret;
4026
4027 if (pipe_crc->source == source)
4028 return 0;
4029
4030 /* forbid changing the source without going back to 'none' */
4031 if (pipe_crc->source && source)
4032 return -EINVAL;
4033
4034 power_domain = POWER_DOMAIN_PIPE(pipe);
4035 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
4036 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4037 return -EIO;
4038 }
4039
4040 if (IS_GEN2(dev))
4041 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
4042 else if (INTEL_INFO(dev)->gen < 5)
4043 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4044 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4045 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4046 else if (IS_GEN5(dev) || IS_GEN6(dev))
4047 ret = ilk_pipe_crc_ctl_reg(&source, &val);
4048 else
4049 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4050
4051 if (ret != 0)
4052 goto out;
4053
4054 /* none -> real source transition */
4055 if (source) {
4056 struct intel_pipe_crc_entry *entries;
4057
4058 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4059 pipe_name(pipe), pipe_crc_source_name(source));
4060
4061 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4062 sizeof(pipe_crc->entries[0]),
4063 GFP_KERNEL);
4064 if (!entries) {
4065 ret = -ENOMEM;
4066 goto out;
4067 }
4068
4069 /*
4070 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4071 * enabled and disabled dynamically based on package C states,
4072 * user space can't make reliable use of the CRCs, so let's just
4073 * completely disable it.
4074 */
4075 hsw_disable_ips(crtc);
4076
4077 spin_lock_irq(&pipe_crc->lock);
4078 kfree(pipe_crc->entries);
4079 pipe_crc->entries = entries;
4080 pipe_crc->head = 0;
4081 pipe_crc->tail = 0;
4082 spin_unlock_irq(&pipe_crc->lock);
4083 }
4084
4085 pipe_crc->source = source;
4086
4087 I915_WRITE(PIPE_CRC_CTL(pipe), val);
4088 POSTING_READ(PIPE_CRC_CTL(pipe));
4089
4090 /* real source -> none transition */
4091 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
4092 struct intel_pipe_crc_entry *entries;
4093 struct intel_crtc *crtc =
4094 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
4095
4096 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4097 pipe_name(pipe));
4098
4099 drm_modeset_lock(&crtc->base.mutex, NULL);
4100 if (crtc->base.state->active)
4101 intel_wait_for_vblank(dev, pipe);
4102 drm_modeset_unlock(&crtc->base.mutex);
4103
4104 spin_lock_irq(&pipe_crc->lock);
4105 entries = pipe_crc->entries;
4106 pipe_crc->entries = NULL;
4107 pipe_crc->head = 0;
4108 pipe_crc->tail = 0;
4109 spin_unlock_irq(&pipe_crc->lock);
4110
4111 kfree(entries);
4112
4113 if (IS_G4X(dev))
4114 g4x_undo_pipe_scramble_reset(dev, pipe);
4115 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4116 vlv_undo_pipe_scramble_reset(dev, pipe);
4117 else if (IS_HASWELL(dev) && pipe == PIPE_A)
4118 hsw_trans_edp_pipe_A_crc_wa(dev, false);
4119
4120 hsw_enable_ips(crtc);
4121 }
4122
4123 ret = 0;
4124
4125 out:
4126 intel_display_power_put(dev_priv, power_domain);
4127
4128 return ret;
4129 }
4130
4131 /*
4132 * Parse pipe CRC command strings:
4133 * command: wsp* object wsp+ name wsp+ source wsp*
4134 * object: 'pipe'
4135 * name: (A | B | C)
4136 * source: (none | plane1 | plane2 | pf)
4137 * wsp: (#0x20 | #0x9 | #0xA)+
4138 *
4139 * eg.:
4140 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
4141 * "pipe A none" -> Stop CRC
4142 */
4143 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
4144 {
4145 int n_words = 0;
4146
4147 while (*buf) {
4148 char *end;
4149
4150 /* skip leading white space */
4151 buf = skip_spaces(buf);
4152 if (!*buf)
4153 break; /* end of buffer */
4154
4155 /* find end of word */
4156 for (end = buf; *end && !isspace(*end); end++)
4157 ;
4158
4159 if (n_words == max_words) {
4160 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4161 max_words);
4162 return -EINVAL; /* ran out of words[] before bytes */
4163 }
4164
4165 if (*end)
4166 *end++ = '\0';
4167 words[n_words++] = buf;
4168 buf = end;
4169 }
4170
4171 return n_words;
4172 }
4173
4174 enum intel_pipe_crc_object {
4175 PIPE_CRC_OBJECT_PIPE,
4176 };
4177
4178 static const char * const pipe_crc_objects[] = {
4179 "pipe",
4180 };
4181
4182 static int
4183 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4184 {
4185 int i;
4186
4187 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4188 if (!strcmp(buf, pipe_crc_objects[i])) {
4189 *o = i;
4190 return 0;
4191 }
4192
4193 return -EINVAL;
4194 }
4195
4196 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4197 {
4198 const char name = buf[0];
4199
4200 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4201 return -EINVAL;
4202
4203 *pipe = name - 'A';
4204
4205 return 0;
4206 }
4207
4208 static int
4209 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4210 {
4211 int i;
4212
4213 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4214 if (!strcmp(buf, pipe_crc_sources[i])) {
4215 *s = i;
4216 return 0;
4217 }
4218
4219 return -EINVAL;
4220 }
4221
4222 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
4223 {
4224 #define N_WORDS 3
4225 int n_words;
4226 char *words[N_WORDS];
4227 enum pipe pipe;
4228 enum intel_pipe_crc_object object;
4229 enum intel_pipe_crc_source source;
4230
4231 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4232 if (n_words != N_WORDS) {
4233 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4234 N_WORDS);
4235 return -EINVAL;
4236 }
4237
4238 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4239 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4240 return -EINVAL;
4241 }
4242
4243 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4244 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4245 return -EINVAL;
4246 }
4247
4248 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4249 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4250 return -EINVAL;
4251 }
4252
4253 return pipe_crc_set_source(dev, pipe, source);
4254 }
4255
4256 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4257 size_t len, loff_t *offp)
4258 {
4259 struct seq_file *m = file->private_data;
4260 struct drm_device *dev = m->private;
4261 char *tmpbuf;
4262 int ret;
4263
4264 if (len == 0)
4265 return 0;
4266
4267 if (len > PAGE_SIZE - 1) {
4268 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4269 PAGE_SIZE);
4270 return -E2BIG;
4271 }
4272
4273 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4274 if (!tmpbuf)
4275 return -ENOMEM;
4276
4277 if (copy_from_user(tmpbuf, ubuf, len)) {
4278 ret = -EFAULT;
4279 goto out;
4280 }
4281 tmpbuf[len] = '\0';
4282
4283 ret = display_crc_ctl_parse(dev, tmpbuf, len);
4284
4285 out:
4286 kfree(tmpbuf);
4287 if (ret < 0)
4288 return ret;
4289
4290 *offp += len;
4291 return len;
4292 }
4293
4294 static const struct file_operations i915_display_crc_ctl_fops = {
4295 .owner = THIS_MODULE,
4296 .open = display_crc_ctl_open,
4297 .read = seq_read,
4298 .llseek = seq_lseek,
4299 .release = single_release,
4300 .write = display_crc_ctl_write
4301 };
4302
4303 static ssize_t i915_displayport_test_active_write(struct file *file,
4304 const char __user *ubuf,
4305 size_t len, loff_t *offp)
4306 {
4307 char *input_buffer;
4308 int status = 0;
4309 struct drm_device *dev;
4310 struct drm_connector *connector;
4311 struct list_head *connector_list;
4312 struct intel_dp *intel_dp;
4313 int val = 0;
4314
4315 dev = ((struct seq_file *)file->private_data)->private;
4316
4317 connector_list = &dev->mode_config.connector_list;
4318
4319 if (len == 0)
4320 return 0;
4321
4322 input_buffer = kmalloc(len + 1, GFP_KERNEL);
4323 if (!input_buffer)
4324 return -ENOMEM;
4325
4326 if (copy_from_user(input_buffer, ubuf, len)) {
4327 status = -EFAULT;
4328 goto out;
4329 }
4330
4331 input_buffer[len] = '\0';
4332 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4333
4334 list_for_each_entry(connector, connector_list, head) {
4335
4336 if (connector->connector_type !=
4337 DRM_MODE_CONNECTOR_DisplayPort)
4338 continue;
4339
4340 if (connector->status == connector_status_connected &&
4341 connector->encoder != NULL) {
4342 intel_dp = enc_to_intel_dp(connector->encoder);
4343 status = kstrtoint(input_buffer, 10, &val);
4344 if (status < 0)
4345 goto out;
4346 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4347 /* To prevent erroneous activation of the compliance
4348 * testing code, only accept an actual value of 1 here
4349 */
4350 if (val == 1)
4351 intel_dp->compliance_test_active = 1;
4352 else
4353 intel_dp->compliance_test_active = 0;
4354 }
4355 }
4356 out:
4357 kfree(input_buffer);
4358 if (status < 0)
4359 return status;
4360
4361 *offp += len;
4362 return len;
4363 }
4364
4365 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4366 {
4367 struct drm_device *dev = m->private;
4368 struct drm_connector *connector;
4369 struct list_head *connector_list = &dev->mode_config.connector_list;
4370 struct intel_dp *intel_dp;
4371
4372 list_for_each_entry(connector, connector_list, head) {
4373
4374 if (connector->connector_type !=
4375 DRM_MODE_CONNECTOR_DisplayPort)
4376 continue;
4377
4378 if (connector->status == connector_status_connected &&
4379 connector->encoder != NULL) {
4380 intel_dp = enc_to_intel_dp(connector->encoder);
4381 if (intel_dp->compliance_test_active)
4382 seq_puts(m, "1");
4383 else
4384 seq_puts(m, "0");
4385 } else
4386 seq_puts(m, "0");
4387 }
4388
4389 return 0;
4390 }
4391
4392 static int i915_displayport_test_active_open(struct inode *inode,
4393 struct file *file)
4394 {
4395 struct drm_device *dev = inode->i_private;
4396
4397 return single_open(file, i915_displayport_test_active_show, dev);
4398 }
4399
4400 static const struct file_operations i915_displayport_test_active_fops = {
4401 .owner = THIS_MODULE,
4402 .open = i915_displayport_test_active_open,
4403 .read = seq_read,
4404 .llseek = seq_lseek,
4405 .release = single_release,
4406 .write = i915_displayport_test_active_write
4407 };
4408
4409 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4410 {
4411 struct drm_device *dev = m->private;
4412 struct drm_connector *connector;
4413 struct list_head *connector_list = &dev->mode_config.connector_list;
4414 struct intel_dp *intel_dp;
4415
4416 list_for_each_entry(connector, connector_list, head) {
4417
4418 if (connector->connector_type !=
4419 DRM_MODE_CONNECTOR_DisplayPort)
4420 continue;
4421
4422 if (connector->status == connector_status_connected &&
4423 connector->encoder != NULL) {
4424 intel_dp = enc_to_intel_dp(connector->encoder);
4425 seq_printf(m, "%lx", intel_dp->compliance_test_data);
4426 } else
4427 seq_puts(m, "0");
4428 }
4429
4430 return 0;
4431 }
4432 static int i915_displayport_test_data_open(struct inode *inode,
4433 struct file *file)
4434 {
4435 struct drm_device *dev = inode->i_private;
4436
4437 return single_open(file, i915_displayport_test_data_show, dev);
4438 }
4439
4440 static const struct file_operations i915_displayport_test_data_fops = {
4441 .owner = THIS_MODULE,
4442 .open = i915_displayport_test_data_open,
4443 .read = seq_read,
4444 .llseek = seq_lseek,
4445 .release = single_release
4446 };
4447
4448 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4449 {
4450 struct drm_device *dev = m->private;
4451 struct drm_connector *connector;
4452 struct list_head *connector_list = &dev->mode_config.connector_list;
4453 struct intel_dp *intel_dp;
4454
4455 list_for_each_entry(connector, connector_list, head) {
4456
4457 if (connector->connector_type !=
4458 DRM_MODE_CONNECTOR_DisplayPort)
4459 continue;
4460
4461 if (connector->status == connector_status_connected &&
4462 connector->encoder != NULL) {
4463 intel_dp = enc_to_intel_dp(connector->encoder);
4464 seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4465 } else
4466 seq_puts(m, "0");
4467 }
4468
4469 return 0;
4470 }
4471
4472 static int i915_displayport_test_type_open(struct inode *inode,
4473 struct file *file)
4474 {
4475 struct drm_device *dev = inode->i_private;
4476
4477 return single_open(file, i915_displayport_test_type_show, dev);
4478 }
4479
4480 static const struct file_operations i915_displayport_test_type_fops = {
4481 .owner = THIS_MODULE,
4482 .open = i915_displayport_test_type_open,
4483 .read = seq_read,
4484 .llseek = seq_lseek,
4485 .release = single_release
4486 };
4487
4488 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4489 {
4490 struct drm_device *dev = m->private;
4491 int level;
4492 int num_levels;
4493
4494 if (IS_CHERRYVIEW(dev))
4495 num_levels = 3;
4496 else if (IS_VALLEYVIEW(dev))
4497 num_levels = 1;
4498 else
4499 num_levels = ilk_wm_max_level(dev) + 1;
4500
4501 drm_modeset_lock_all(dev);
4502
4503 for (level = 0; level < num_levels; level++) {
4504 unsigned int latency = wm[level];
4505
4506 /*
4507 * - WM1+ latency values in 0.5us units
4508 * - latencies are in us on gen9/vlv/chv
4509 */
4510 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) ||
4511 IS_CHERRYVIEW(dev))
4512 latency *= 10;
4513 else if (level > 0)
4514 latency *= 5;
4515
4516 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4517 level, wm[level], latency / 10, latency % 10);
4518 }
4519
4520 drm_modeset_unlock_all(dev);
4521 }
4522
4523 static int pri_wm_latency_show(struct seq_file *m, void *data)
4524 {
4525 struct drm_device *dev = m->private;
4526 struct drm_i915_private *dev_priv = dev->dev_private;
4527 const uint16_t *latencies;
4528
4529 if (INTEL_INFO(dev)->gen >= 9)
4530 latencies = dev_priv->wm.skl_latency;
4531 else
4532 latencies = to_i915(dev)->wm.pri_latency;
4533
4534 wm_latency_show(m, latencies);
4535
4536 return 0;
4537 }
4538
4539 static int spr_wm_latency_show(struct seq_file *m, void *data)
4540 {
4541 struct drm_device *dev = m->private;
4542 struct drm_i915_private *dev_priv = dev->dev_private;
4543 const uint16_t *latencies;
4544
4545 if (INTEL_INFO(dev)->gen >= 9)
4546 latencies = dev_priv->wm.skl_latency;
4547 else
4548 latencies = to_i915(dev)->wm.spr_latency;
4549
4550 wm_latency_show(m, latencies);
4551
4552 return 0;
4553 }
4554
4555 static int cur_wm_latency_show(struct seq_file *m, void *data)
4556 {
4557 struct drm_device *dev = m->private;
4558 struct drm_i915_private *dev_priv = dev->dev_private;
4559 const uint16_t *latencies;
4560
4561 if (INTEL_INFO(dev)->gen >= 9)
4562 latencies = dev_priv->wm.skl_latency;
4563 else
4564 latencies = to_i915(dev)->wm.cur_latency;
4565
4566 wm_latency_show(m, latencies);
4567
4568 return 0;
4569 }
4570
4571 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4572 {
4573 struct drm_device *dev = inode->i_private;
4574
4575 if (INTEL_INFO(dev)->gen < 5)
4576 return -ENODEV;
4577
4578 return single_open(file, pri_wm_latency_show, dev);
4579 }
4580
4581 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4582 {
4583 struct drm_device *dev = inode->i_private;
4584
4585 if (HAS_GMCH_DISPLAY(dev))
4586 return -ENODEV;
4587
4588 return single_open(file, spr_wm_latency_show, dev);
4589 }
4590
4591 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4592 {
4593 struct drm_device *dev = inode->i_private;
4594
4595 if (HAS_GMCH_DISPLAY(dev))
4596 return -ENODEV;
4597
4598 return single_open(file, cur_wm_latency_show, dev);
4599 }
4600
4601 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4602 size_t len, loff_t *offp, uint16_t wm[8])
4603 {
4604 struct seq_file *m = file->private_data;
4605 struct drm_device *dev = m->private;
4606 uint16_t new[8] = { 0 };
4607 int num_levels;
4608 int level;
4609 int ret;
4610 char tmp[32];
4611
4612 if (IS_CHERRYVIEW(dev))
4613 num_levels = 3;
4614 else if (IS_VALLEYVIEW(dev))
4615 num_levels = 1;
4616 else
4617 num_levels = ilk_wm_max_level(dev) + 1;
4618
4619 if (len >= sizeof(tmp))
4620 return -EINVAL;
4621
4622 if (copy_from_user(tmp, ubuf, len))
4623 return -EFAULT;
4624
4625 tmp[len] = '\0';
4626
4627 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4628 &new[0], &new[1], &new[2], &new[3],
4629 &new[4], &new[5], &new[6], &new[7]);
4630 if (ret != num_levels)
4631 return -EINVAL;
4632
4633 drm_modeset_lock_all(dev);
4634
4635 for (level = 0; level < num_levels; level++)
4636 wm[level] = new[level];
4637
4638 drm_modeset_unlock_all(dev);
4639
4640 return len;
4641 }
4642
4643
4644 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4645 size_t len, loff_t *offp)
4646 {
4647 struct seq_file *m = file->private_data;
4648 struct drm_device *dev = m->private;
4649 struct drm_i915_private *dev_priv = dev->dev_private;
4650 uint16_t *latencies;
4651
4652 if (INTEL_INFO(dev)->gen >= 9)
4653 latencies = dev_priv->wm.skl_latency;
4654 else
4655 latencies = to_i915(dev)->wm.pri_latency;
4656
4657 return wm_latency_write(file, ubuf, len, offp, latencies);
4658 }
4659
4660 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4661 size_t len, loff_t *offp)
4662 {
4663 struct seq_file *m = file->private_data;
4664 struct drm_device *dev = m->private;
4665 struct drm_i915_private *dev_priv = dev->dev_private;
4666 uint16_t *latencies;
4667
4668 if (INTEL_INFO(dev)->gen >= 9)
4669 latencies = dev_priv->wm.skl_latency;
4670 else
4671 latencies = to_i915(dev)->wm.spr_latency;
4672
4673 return wm_latency_write(file, ubuf, len, offp, latencies);
4674 }
4675
4676 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4677 size_t len, loff_t *offp)
4678 {
4679 struct seq_file *m = file->private_data;
4680 struct drm_device *dev = m->private;
4681 struct drm_i915_private *dev_priv = dev->dev_private;
4682 uint16_t *latencies;
4683
4684 if (INTEL_INFO(dev)->gen >= 9)
4685 latencies = dev_priv->wm.skl_latency;
4686 else
4687 latencies = to_i915(dev)->wm.cur_latency;
4688
4689 return wm_latency_write(file, ubuf, len, offp, latencies);
4690 }
4691
4692 static const struct file_operations i915_pri_wm_latency_fops = {
4693 .owner = THIS_MODULE,
4694 .open = pri_wm_latency_open,
4695 .read = seq_read,
4696 .llseek = seq_lseek,
4697 .release = single_release,
4698 .write = pri_wm_latency_write
4699 };
4700
4701 static const struct file_operations i915_spr_wm_latency_fops = {
4702 .owner = THIS_MODULE,
4703 .open = spr_wm_latency_open,
4704 .read = seq_read,
4705 .llseek = seq_lseek,
4706 .release = single_release,
4707 .write = spr_wm_latency_write
4708 };
4709
4710 static const struct file_operations i915_cur_wm_latency_fops = {
4711 .owner = THIS_MODULE,
4712 .open = cur_wm_latency_open,
4713 .read = seq_read,
4714 .llseek = seq_lseek,
4715 .release = single_release,
4716 .write = cur_wm_latency_write
4717 };
4718
4719 static int
4720 i915_wedged_get(void *data, u64 *val)
4721 {
4722 struct drm_device *dev = data;
4723 struct drm_i915_private *dev_priv = dev->dev_private;
4724
4725 *val = i915_terminally_wedged(&dev_priv->gpu_error);
4726
4727 return 0;
4728 }
4729
4730 static int
4731 i915_wedged_set(void *data, u64 val)
4732 {
4733 struct drm_device *dev = data;
4734 struct drm_i915_private *dev_priv = dev->dev_private;
4735
4736 /*
4737 * There is no safeguard against this debugfs entry colliding
4738 * with the hangcheck calling same i915_handle_error() in
4739 * parallel, causing an explosion. For now we assume that the
4740 * test harness is responsible enough not to inject gpu hangs
4741 * while it is writing to 'i915_wedged'
4742 */
4743
4744 if (i915_reset_in_progress(&dev_priv->gpu_error))
4745 return -EAGAIN;
4746
4747 intel_runtime_pm_get(dev_priv);
4748
4749 i915_handle_error(dev, val,
4750 "Manually setting wedged to %llu", val);
4751
4752 intel_runtime_pm_put(dev_priv);
4753
4754 return 0;
4755 }
4756
4757 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4758 i915_wedged_get, i915_wedged_set,
4759 "%llu\n");
4760
4761 static int
4762 i915_ring_stop_get(void *data, u64 *val)
4763 {
4764 struct drm_device *dev = data;
4765 struct drm_i915_private *dev_priv = dev->dev_private;
4766
4767 *val = dev_priv->gpu_error.stop_rings;
4768
4769 return 0;
4770 }
4771
4772 static int
4773 i915_ring_stop_set(void *data, u64 val)
4774 {
4775 struct drm_device *dev = data;
4776 struct drm_i915_private *dev_priv = dev->dev_private;
4777 int ret;
4778
4779 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
4780
4781 ret = mutex_lock_interruptible(&dev->struct_mutex);
4782 if (ret)
4783 return ret;
4784
4785 dev_priv->gpu_error.stop_rings = val;
4786 mutex_unlock(&dev->struct_mutex);
4787
4788 return 0;
4789 }
4790
4791 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4792 i915_ring_stop_get, i915_ring_stop_set,
4793 "0x%08llx\n");
4794
4795 static int
4796 i915_ring_missed_irq_get(void *data, u64 *val)
4797 {
4798 struct drm_device *dev = data;
4799 struct drm_i915_private *dev_priv = dev->dev_private;
4800
4801 *val = dev_priv->gpu_error.missed_irq_rings;
4802 return 0;
4803 }
4804
4805 static int
4806 i915_ring_missed_irq_set(void *data, u64 val)
4807 {
4808 struct drm_device *dev = data;
4809 struct drm_i915_private *dev_priv = dev->dev_private;
4810 int ret;
4811
4812 /* Lock against concurrent debugfs callers */
4813 ret = mutex_lock_interruptible(&dev->struct_mutex);
4814 if (ret)
4815 return ret;
4816 dev_priv->gpu_error.missed_irq_rings = val;
4817 mutex_unlock(&dev->struct_mutex);
4818
4819 return 0;
4820 }
4821
4822 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4823 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4824 "0x%08llx\n");
4825
4826 static int
4827 i915_ring_test_irq_get(void *data, u64 *val)
4828 {
4829 struct drm_device *dev = data;
4830 struct drm_i915_private *dev_priv = dev->dev_private;
4831
4832 *val = dev_priv->gpu_error.test_irq_rings;
4833
4834 return 0;
4835 }
4836
4837 static int
4838 i915_ring_test_irq_set(void *data, u64 val)
4839 {
4840 struct drm_device *dev = data;
4841 struct drm_i915_private *dev_priv = dev->dev_private;
4842 int ret;
4843
4844 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4845
4846 /* Lock against concurrent debugfs callers */
4847 ret = mutex_lock_interruptible(&dev->struct_mutex);
4848 if (ret)
4849 return ret;
4850
4851 dev_priv->gpu_error.test_irq_rings = val;
4852 mutex_unlock(&dev->struct_mutex);
4853
4854 return 0;
4855 }
4856
4857 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4858 i915_ring_test_irq_get, i915_ring_test_irq_set,
4859 "0x%08llx\n");
4860
4861 #define DROP_UNBOUND 0x1
4862 #define DROP_BOUND 0x2
4863 #define DROP_RETIRE 0x4
4864 #define DROP_ACTIVE 0x8
4865 #define DROP_ALL (DROP_UNBOUND | \
4866 DROP_BOUND | \
4867 DROP_RETIRE | \
4868 DROP_ACTIVE)
4869 static int
4870 i915_drop_caches_get(void *data, u64 *val)
4871 {
4872 *val = DROP_ALL;
4873
4874 return 0;
4875 }
4876
4877 static int
4878 i915_drop_caches_set(void *data, u64 val)
4879 {
4880 struct drm_device *dev = data;
4881 struct drm_i915_private *dev_priv = dev->dev_private;
4882 int ret;
4883
4884 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4885
4886 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4887 * on ioctls on -EAGAIN. */
4888 ret = mutex_lock_interruptible(&dev->struct_mutex);
4889 if (ret)
4890 return ret;
4891
4892 if (val & DROP_ACTIVE) {
4893 ret = i915_gpu_idle(dev);
4894 if (ret)
4895 goto unlock;
4896 }
4897
4898 if (val & (DROP_RETIRE | DROP_ACTIVE))
4899 i915_gem_retire_requests(dev);
4900
4901 if (val & DROP_BOUND)
4902 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4903
4904 if (val & DROP_UNBOUND)
4905 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4906
4907 unlock:
4908 mutex_unlock(&dev->struct_mutex);
4909
4910 return ret;
4911 }
4912
4913 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4914 i915_drop_caches_get, i915_drop_caches_set,
4915 "0x%08llx\n");
4916
4917 static int
4918 i915_max_freq_get(void *data, u64 *val)
4919 {
4920 struct drm_device *dev = data;
4921 struct drm_i915_private *dev_priv = dev->dev_private;
4922 int ret;
4923
4924 if (INTEL_INFO(dev)->gen < 6)
4925 return -ENODEV;
4926
4927 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4928
4929 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4930 if (ret)
4931 return ret;
4932
4933 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4934 mutex_unlock(&dev_priv->rps.hw_lock);
4935
4936 return 0;
4937 }
4938
4939 static int
4940 i915_max_freq_set(void *data, u64 val)
4941 {
4942 struct drm_device *dev = data;
4943 struct drm_i915_private *dev_priv = dev->dev_private;
4944 u32 hw_max, hw_min;
4945 int ret;
4946
4947 if (INTEL_INFO(dev)->gen < 6)
4948 return -ENODEV;
4949
4950 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4951
4952 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4953
4954 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4955 if (ret)
4956 return ret;
4957
4958 /*
4959 * Turbo will still be enabled, but won't go above the set value.
4960 */
4961 val = intel_freq_opcode(dev_priv, val);
4962
4963 hw_max = dev_priv->rps.max_freq;
4964 hw_min = dev_priv->rps.min_freq;
4965
4966 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4967 mutex_unlock(&dev_priv->rps.hw_lock);
4968 return -EINVAL;
4969 }
4970
4971 dev_priv->rps.max_freq_softlimit = val;
4972
4973 intel_set_rps(dev, val);
4974
4975 mutex_unlock(&dev_priv->rps.hw_lock);
4976
4977 return 0;
4978 }
4979
4980 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4981 i915_max_freq_get, i915_max_freq_set,
4982 "%llu\n");
4983
4984 static int
4985 i915_min_freq_get(void *data, u64 *val)
4986 {
4987 struct drm_device *dev = data;
4988 struct drm_i915_private *dev_priv = dev->dev_private;
4989 int ret;
4990
4991 if (INTEL_INFO(dev)->gen < 6)
4992 return -ENODEV;
4993
4994 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4995
4996 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4997 if (ret)
4998 return ret;
4999
5000 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
5001 mutex_unlock(&dev_priv->rps.hw_lock);
5002
5003 return 0;
5004 }
5005
5006 static int
5007 i915_min_freq_set(void *data, u64 val)
5008 {
5009 struct drm_device *dev = data;
5010 struct drm_i915_private *dev_priv = dev->dev_private;
5011 u32 hw_max, hw_min;
5012 int ret;
5013
5014 if (INTEL_INFO(dev)->gen < 6)
5015 return -ENODEV;
5016
5017 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5018
5019 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
5020
5021 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5022 if (ret)
5023 return ret;
5024
5025 /*
5026 * Turbo will still be enabled, but won't go below the set value.
5027 */
5028 val = intel_freq_opcode(dev_priv, val);
5029
5030 hw_max = dev_priv->rps.max_freq;
5031 hw_min = dev_priv->rps.min_freq;
5032
5033 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
5034 mutex_unlock(&dev_priv->rps.hw_lock);
5035 return -EINVAL;
5036 }
5037
5038 dev_priv->rps.min_freq_softlimit = val;
5039
5040 intel_set_rps(dev, val);
5041
5042 mutex_unlock(&dev_priv->rps.hw_lock);
5043
5044 return 0;
5045 }
5046
5047 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
5048 i915_min_freq_get, i915_min_freq_set,
5049 "%llu\n");
5050
5051 static int
5052 i915_cache_sharing_get(void *data, u64 *val)
5053 {
5054 struct drm_device *dev = data;
5055 struct drm_i915_private *dev_priv = dev->dev_private;
5056 u32 snpcr;
5057 int ret;
5058
5059 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5060 return -ENODEV;
5061
5062 ret = mutex_lock_interruptible(&dev->struct_mutex);
5063 if (ret)
5064 return ret;
5065 intel_runtime_pm_get(dev_priv);
5066
5067 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5068
5069 intel_runtime_pm_put(dev_priv);
5070 mutex_unlock(&dev_priv->dev->struct_mutex);
5071
5072 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
5073
5074 return 0;
5075 }
5076
5077 static int
5078 i915_cache_sharing_set(void *data, u64 val)
5079 {
5080 struct drm_device *dev = data;
5081 struct drm_i915_private *dev_priv = dev->dev_private;
5082 u32 snpcr;
5083
5084 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5085 return -ENODEV;
5086
5087 if (val > 3)
5088 return -EINVAL;
5089
5090 intel_runtime_pm_get(dev_priv);
5091 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
5092
5093 /* Update the cache sharing policy here as well */
5094 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5095 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5096 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5097 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5098
5099 intel_runtime_pm_put(dev_priv);
5100 return 0;
5101 }
5102
5103 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5104 i915_cache_sharing_get, i915_cache_sharing_set,
5105 "%llu\n");
5106
5107 struct sseu_dev_status {
5108 unsigned int slice_total;
5109 unsigned int subslice_total;
5110 unsigned int subslice_per_slice;
5111 unsigned int eu_total;
5112 unsigned int eu_per_subslice;
5113 };
5114
5115 static void cherryview_sseu_device_status(struct drm_device *dev,
5116 struct sseu_dev_status *stat)
5117 {
5118 struct drm_i915_private *dev_priv = dev->dev_private;
5119 int ss_max = 2;
5120 int ss;
5121 u32 sig1[ss_max], sig2[ss_max];
5122
5123 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5124 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5125 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5126 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5127
5128 for (ss = 0; ss < ss_max; ss++) {
5129 unsigned int eu_cnt;
5130
5131 if (sig1[ss] & CHV_SS_PG_ENABLE)
5132 /* skip disabled subslice */
5133 continue;
5134
5135 stat->slice_total = 1;
5136 stat->subslice_per_slice++;
5137 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5138 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5139 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5140 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5141 stat->eu_total += eu_cnt;
5142 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
5143 }
5144 stat->subslice_total = stat->subslice_per_slice;
5145 }
5146
5147 static void gen9_sseu_device_status(struct drm_device *dev,
5148 struct sseu_dev_status *stat)
5149 {
5150 struct drm_i915_private *dev_priv = dev->dev_private;
5151 int s_max = 3, ss_max = 4;
5152 int s, ss;
5153 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5154
5155 /* BXT has a single slice and at most 3 subslices. */
5156 if (IS_BROXTON(dev)) {
5157 s_max = 1;
5158 ss_max = 3;
5159 }
5160
5161 for (s = 0; s < s_max; s++) {
5162 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5163 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5164 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5165 }
5166
5167 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5168 GEN9_PGCTL_SSA_EU19_ACK |
5169 GEN9_PGCTL_SSA_EU210_ACK |
5170 GEN9_PGCTL_SSA_EU311_ACK;
5171 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5172 GEN9_PGCTL_SSB_EU19_ACK |
5173 GEN9_PGCTL_SSB_EU210_ACK |
5174 GEN9_PGCTL_SSB_EU311_ACK;
5175
5176 for (s = 0; s < s_max; s++) {
5177 unsigned int ss_cnt = 0;
5178
5179 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5180 /* skip disabled slice */
5181 continue;
5182
5183 stat->slice_total++;
5184
5185 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
5186 ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
5187
5188 for (ss = 0; ss < ss_max; ss++) {
5189 unsigned int eu_cnt;
5190
5191 if (IS_BROXTON(dev) &&
5192 !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5193 /* skip disabled subslice */
5194 continue;
5195
5196 if (IS_BROXTON(dev))
5197 ss_cnt++;
5198
5199 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5200 eu_mask[ss%2]);
5201 stat->eu_total += eu_cnt;
5202 stat->eu_per_subslice = max(stat->eu_per_subslice,
5203 eu_cnt);
5204 }
5205
5206 stat->subslice_total += ss_cnt;
5207 stat->subslice_per_slice = max(stat->subslice_per_slice,
5208 ss_cnt);
5209 }
5210 }
5211
5212 static void broadwell_sseu_device_status(struct drm_device *dev,
5213 struct sseu_dev_status *stat)
5214 {
5215 struct drm_i915_private *dev_priv = dev->dev_private;
5216 int s;
5217 u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5218
5219 stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK);
5220
5221 if (stat->slice_total) {
5222 stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice;
5223 stat->subslice_total = stat->slice_total *
5224 stat->subslice_per_slice;
5225 stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice;
5226 stat->eu_total = stat->eu_per_subslice * stat->subslice_total;
5227
5228 /* subtract fused off EU(s) from enabled slice(s) */
5229 for (s = 0; s < stat->slice_total; s++) {
5230 u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s];
5231
5232 stat->eu_total -= hweight8(subslice_7eu);
5233 }
5234 }
5235 }
5236
5237 static int i915_sseu_status(struct seq_file *m, void *unused)
5238 {
5239 struct drm_info_node *node = (struct drm_info_node *) m->private;
5240 struct drm_device *dev = node->minor->dev;
5241 struct sseu_dev_status stat;
5242
5243 if (INTEL_INFO(dev)->gen < 8)
5244 return -ENODEV;
5245
5246 seq_puts(m, "SSEU Device Info\n");
5247 seq_printf(m, " Available Slice Total: %u\n",
5248 INTEL_INFO(dev)->slice_total);
5249 seq_printf(m, " Available Subslice Total: %u\n",
5250 INTEL_INFO(dev)->subslice_total);
5251 seq_printf(m, " Available Subslice Per Slice: %u\n",
5252 INTEL_INFO(dev)->subslice_per_slice);
5253 seq_printf(m, " Available EU Total: %u\n",
5254 INTEL_INFO(dev)->eu_total);
5255 seq_printf(m, " Available EU Per Subslice: %u\n",
5256 INTEL_INFO(dev)->eu_per_subslice);
5257 seq_printf(m, " Has Slice Power Gating: %s\n",
5258 yesno(INTEL_INFO(dev)->has_slice_pg));
5259 seq_printf(m, " Has Subslice Power Gating: %s\n",
5260 yesno(INTEL_INFO(dev)->has_subslice_pg));
5261 seq_printf(m, " Has EU Power Gating: %s\n",
5262 yesno(INTEL_INFO(dev)->has_eu_pg));
5263
5264 seq_puts(m, "SSEU Device Status\n");
5265 memset(&stat, 0, sizeof(stat));
5266 if (IS_CHERRYVIEW(dev)) {
5267 cherryview_sseu_device_status(dev, &stat);
5268 } else if (IS_BROADWELL(dev)) {
5269 broadwell_sseu_device_status(dev, &stat);
5270 } else if (INTEL_INFO(dev)->gen >= 9) {
5271 gen9_sseu_device_status(dev, &stat);
5272 }
5273 seq_printf(m, " Enabled Slice Total: %u\n",
5274 stat.slice_total);
5275 seq_printf(m, " Enabled Subslice Total: %u\n",
5276 stat.subslice_total);
5277 seq_printf(m, " Enabled Subslice Per Slice: %u\n",
5278 stat.subslice_per_slice);
5279 seq_printf(m, " Enabled EU Total: %u\n",
5280 stat.eu_total);
5281 seq_printf(m, " Enabled EU Per Subslice: %u\n",
5282 stat.eu_per_subslice);
5283
5284 return 0;
5285 }
5286
5287 static int i915_forcewake_open(struct inode *inode, struct file *file)
5288 {
5289 struct drm_device *dev = inode->i_private;
5290 struct drm_i915_private *dev_priv = dev->dev_private;
5291
5292 if (INTEL_INFO(dev)->gen < 6)
5293 return 0;
5294
5295 intel_runtime_pm_get(dev_priv);
5296 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5297
5298 return 0;
5299 }
5300
5301 static int i915_forcewake_release(struct inode *inode, struct file *file)
5302 {
5303 struct drm_device *dev = inode->i_private;
5304 struct drm_i915_private *dev_priv = dev->dev_private;
5305
5306 if (INTEL_INFO(dev)->gen < 6)
5307 return 0;
5308
5309 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5310 intel_runtime_pm_put(dev_priv);
5311
5312 return 0;
5313 }
5314
5315 static const struct file_operations i915_forcewake_fops = {
5316 .owner = THIS_MODULE,
5317 .open = i915_forcewake_open,
5318 .release = i915_forcewake_release,
5319 };
5320
5321 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5322 {
5323 struct drm_device *dev = minor->dev;
5324 struct dentry *ent;
5325
5326 ent = debugfs_create_file("i915_forcewake_user",
5327 S_IRUSR,
5328 root, dev,
5329 &i915_forcewake_fops);
5330 if (!ent)
5331 return -ENOMEM;
5332
5333 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5334 }
5335
5336 static int i915_debugfs_create(struct dentry *root,
5337 struct drm_minor *minor,
5338 const char *name,
5339 const struct file_operations *fops)
5340 {
5341 struct drm_device *dev = minor->dev;
5342 struct dentry *ent;
5343
5344 ent = debugfs_create_file(name,
5345 S_IRUGO | S_IWUSR,
5346 root, dev,
5347 fops);
5348 if (!ent)
5349 return -ENOMEM;
5350
5351 return drm_add_fake_info_node(minor, ent, fops);
5352 }
5353
5354 static const struct drm_info_list i915_debugfs_list[] = {
5355 {"i915_capabilities", i915_capabilities, 0},
5356 {"i915_gem_objects", i915_gem_object_info, 0},
5357 {"i915_gem_gtt", i915_gem_gtt_info, 0},
5358 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
5359 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
5360 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
5361 {"i915_gem_stolen", i915_gem_stolen_list_info },
5362 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5363 {"i915_gem_request", i915_gem_request_info, 0},
5364 {"i915_gem_seqno", i915_gem_seqno_info, 0},
5365 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5366 {"i915_gem_interrupt", i915_interrupt_info, 0},
5367 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5368 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5369 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5370 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5371 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5372 {"i915_guc_info", i915_guc_info, 0},
5373 {"i915_guc_load_status", i915_guc_load_status_info, 0},
5374 {"i915_guc_log_dump", i915_guc_log_dump, 0},
5375 {"i915_frequency_info", i915_frequency_info, 0},
5376 {"i915_hangcheck_info", i915_hangcheck_info, 0},
5377 {"i915_drpc_info", i915_drpc_info, 0},
5378 {"i915_emon_status", i915_emon_status, 0},
5379 {"i915_ring_freq_table", i915_ring_freq_table, 0},
5380 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5381 {"i915_fbc_status", i915_fbc_status, 0},
5382 {"i915_ips_status", i915_ips_status, 0},
5383 {"i915_sr_status", i915_sr_status, 0},
5384 {"i915_opregion", i915_opregion, 0},
5385 {"i915_vbt", i915_vbt, 0},
5386 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5387 {"i915_context_status", i915_context_status, 0},
5388 {"i915_dump_lrc", i915_dump_lrc, 0},
5389 {"i915_execlists", i915_execlists, 0},
5390 {"i915_forcewake_domains", i915_forcewake_domains, 0},
5391 {"i915_swizzle_info", i915_swizzle_info, 0},
5392 {"i915_ppgtt_info", i915_ppgtt_info, 0},
5393 {"i915_llc", i915_llc, 0},
5394 {"i915_edp_psr_status", i915_edp_psr_status, 0},
5395 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5396 {"i915_energy_uJ", i915_energy_uJ, 0},
5397 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5398 {"i915_power_domain_info", i915_power_domain_info, 0},
5399 {"i915_dmc_info", i915_dmc_info, 0},
5400 {"i915_display_info", i915_display_info, 0},
5401 {"i915_semaphore_status", i915_semaphore_status, 0},
5402 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5403 {"i915_dp_mst_info", i915_dp_mst_info, 0},
5404 {"i915_wa_registers", i915_wa_registers, 0},
5405 {"i915_ddb_info", i915_ddb_info, 0},
5406 {"i915_sseu_status", i915_sseu_status, 0},
5407 {"i915_drrs_status", i915_drrs_status, 0},
5408 {"i915_rps_boost_info", i915_rps_boost_info, 0},
5409 };
5410 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5411
5412 static const struct i915_debugfs_files {
5413 const char *name;
5414 const struct file_operations *fops;
5415 } i915_debugfs_files[] = {
5416 {"i915_wedged", &i915_wedged_fops},
5417 {"i915_max_freq", &i915_max_freq_fops},
5418 {"i915_min_freq", &i915_min_freq_fops},
5419 {"i915_cache_sharing", &i915_cache_sharing_fops},
5420 {"i915_ring_stop", &i915_ring_stop_fops},
5421 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5422 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5423 {"i915_gem_drop_caches", &i915_drop_caches_fops},
5424 {"i915_error_state", &i915_error_state_fops},
5425 {"i915_next_seqno", &i915_next_seqno_fops},
5426 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5427 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5428 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5429 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5430 {"i915_fbc_false_color", &i915_fbc_fc_fops},
5431 {"i915_dp_test_data", &i915_displayport_test_data_fops},
5432 {"i915_dp_test_type", &i915_displayport_test_type_fops},
5433 {"i915_dp_test_active", &i915_displayport_test_active_fops}
5434 };
5435
5436 void intel_display_crc_init(struct drm_device *dev)
5437 {
5438 struct drm_i915_private *dev_priv = dev->dev_private;
5439 enum pipe pipe;
5440
5441 for_each_pipe(dev_priv, pipe) {
5442 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5443
5444 pipe_crc->opened = false;
5445 spin_lock_init(&pipe_crc->lock);
5446 init_waitqueue_head(&pipe_crc->wq);
5447 }
5448 }
5449
5450 int i915_debugfs_init(struct drm_minor *minor)
5451 {
5452 int ret, i;
5453
5454 ret = i915_forcewake_create(minor->debugfs_root, minor);
5455 if (ret)
5456 return ret;
5457
5458 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5459 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5460 if (ret)
5461 return ret;
5462 }
5463
5464 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5465 ret = i915_debugfs_create(minor->debugfs_root, minor,
5466 i915_debugfs_files[i].name,
5467 i915_debugfs_files[i].fops);
5468 if (ret)
5469 return ret;
5470 }
5471
5472 return drm_debugfs_create_files(i915_debugfs_list,
5473 I915_DEBUGFS_ENTRIES,
5474 minor->debugfs_root, minor);
5475 }
5476
5477 void i915_debugfs_cleanup(struct drm_minor *minor)
5478 {
5479 int i;
5480
5481 drm_debugfs_remove_files(i915_debugfs_list,
5482 I915_DEBUGFS_ENTRIES, minor);
5483
5484 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5485 1, minor);
5486
5487 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5488 struct drm_info_list *info_list =
5489 (struct drm_info_list *)&i915_pipe_crc_data[i];
5490
5491 drm_debugfs_remove_files(info_list, 1, minor);
5492 }
5493
5494 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5495 struct drm_info_list *info_list =
5496 (struct drm_info_list *) i915_debugfs_files[i].fops;
5497
5498 drm_debugfs_remove_files(info_list, 1, minor);
5499 }
5500 }
5501
5502 struct dpcd_block {
5503 /* DPCD dump start address. */
5504 unsigned int offset;
5505 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5506 unsigned int end;
5507 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5508 size_t size;
5509 /* Only valid for eDP. */
5510 bool edp;
5511 };
5512
5513 static const struct dpcd_block i915_dpcd_debug[] = {
5514 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5515 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5516 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5517 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5518 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5519 { .offset = DP_SET_POWER },
5520 { .offset = DP_EDP_DPCD_REV },
5521 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5522 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5523 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5524 };
5525
5526 static int i915_dpcd_show(struct seq_file *m, void *data)
5527 {
5528 struct drm_connector *connector = m->private;
5529 struct intel_dp *intel_dp =
5530 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5531 uint8_t buf[16];
5532 ssize_t err;
5533 int i;
5534
5535 if (connector->status != connector_status_connected)
5536 return -ENODEV;
5537
5538 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5539 const struct dpcd_block *b = &i915_dpcd_debug[i];
5540 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5541
5542 if (b->edp &&
5543 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5544 continue;
5545
5546 /* low tech for now */
5547 if (WARN_ON(size > sizeof(buf)))
5548 continue;
5549
5550 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5551 if (err <= 0) {
5552 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5553 size, b->offset, err);
5554 continue;
5555 }
5556
5557 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5558 }
5559
5560 return 0;
5561 }
5562
5563 static int i915_dpcd_open(struct inode *inode, struct file *file)
5564 {
5565 return single_open(file, i915_dpcd_show, inode->i_private);
5566 }
5567
5568 static const struct file_operations i915_dpcd_fops = {
5569 .owner = THIS_MODULE,
5570 .open = i915_dpcd_open,
5571 .read = seq_read,
5572 .llseek = seq_lseek,
5573 .release = single_release,
5574 };
5575
5576 /**
5577 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5578 * @connector: pointer to a registered drm_connector
5579 *
5580 * Cleanup will be done by drm_connector_unregister() through a call to
5581 * drm_debugfs_connector_remove().
5582 *
5583 * Returns 0 on success, negative error codes on error.
5584 */
5585 int i915_debugfs_connector_add(struct drm_connector *connector)
5586 {
5587 struct dentry *root = connector->debugfs_entry;
5588
5589 /* The connector must have been registered beforehands. */
5590 if (!root)
5591 return -ENODEV;
5592
5593 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5594 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5595 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5596 &i915_dpcd_fops);
5597
5598 return 0;
5599 }
Linux kernel - Deliverables
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