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drm/i915: s/obj->exec_list/obj->obj_exec_link in debugfs
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29 #include <linux/seq_file.h>
30 #include <linux/debugfs.h>
31 #include <linux/slab.h>
32 #include <linux/export.h>
33 #include <linux/list_sort.h>
34 #include <drm/drmP.h>
35 #include "intel_drv.h"
36 #include "intel_ringbuffer.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39
40 #define DRM_I915_RING_DEBUG 1
41
42
43 #if defined(CONFIG_DEBUG_FS)
44
45 enum {
46 ACTIVE_LIST,
47 INACTIVE_LIST,
48 PINNED_LIST,
49 };
50
51 static const char *yesno(int v)
52 {
53 return v ? "yes" : "no";
54 }
55
56 static int i915_capabilities(struct seq_file *m, void *data)
57 {
58 struct drm_info_node *node = (struct drm_info_node *) m->private;
59 struct drm_device *dev = node->minor->dev;
60 const struct intel_device_info *info = INTEL_INFO(dev);
61
62 seq_printf(m, "gen: %d\n", info->gen);
63 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
64 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
65 #define SEP_SEMICOLON ;
66 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
67 #undef PRINT_FLAG
68 #undef SEP_SEMICOLON
69
70 return 0;
71 }
72
73 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
74 {
75 if (obj->user_pin_count > 0)
76 return "P";
77 else if (obj->pin_count > 0)
78 return "p";
79 else
80 return " ";
81 }
82
83 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
84 {
85 switch (obj->tiling_mode) {
86 default:
87 case I915_TILING_NONE: return " ";
88 case I915_TILING_X: return "X";
89 case I915_TILING_Y: return "Y";
90 }
91 }
92
93 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
94 {
95 return obj->has_global_gtt_mapping ? "g" : " ";
96 }
97
98 static void
99 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
100 {
101 struct i915_vma *vma;
102 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %d %d %d%s%s%s",
103 &obj->base,
104 get_pin_flag(obj),
105 get_tiling_flag(obj),
106 get_global_flag(obj),
107 obj->base.size / 1024,
108 obj->base.read_domains,
109 obj->base.write_domain,
110 obj->last_read_seqno,
111 obj->last_write_seqno,
112 obj->last_fenced_seqno,
113 i915_cache_level_str(obj->cache_level),
114 obj->dirty ? " dirty" : "",
115 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
116 if (obj->base.name)
117 seq_printf(m, " (name: %d)", obj->base.name);
118 if (obj->pin_count)
119 seq_printf(m, " (pinned x %d)", obj->pin_count);
120 if (obj->pin_display)
121 seq_printf(m, " (display)");
122 if (obj->fence_reg != I915_FENCE_REG_NONE)
123 seq_printf(m, " (fence: %d)", obj->fence_reg);
124 list_for_each_entry(vma, &obj->vma_list, vma_link) {
125 if (!i915_is_ggtt(vma->vm))
126 seq_puts(m, " (pp");
127 else
128 seq_puts(m, " (g");
129 seq_printf(m, "gtt offset: %08lx, size: %08lx)",
130 vma->node.start, vma->node.size);
131 }
132 if (obj->stolen)
133 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
134 if (obj->pin_mappable || obj->fault_mappable) {
135 char s[3], *t = s;
136 if (obj->pin_mappable)
137 *t++ = 'p';
138 if (obj->fault_mappable)
139 *t++ = 'f';
140 *t = '\0';
141 seq_printf(m, " (%s mappable)", s);
142 }
143 if (obj->ring != NULL)
144 seq_printf(m, " (%s)", obj->ring->name);
145 }
146
147 static int i915_gem_object_list_info(struct seq_file *m, void *data)
148 {
149 struct drm_info_node *node = (struct drm_info_node *) m->private;
150 uintptr_t list = (uintptr_t) node->info_ent->data;
151 struct list_head *head;
152 struct drm_device *dev = node->minor->dev;
153 struct drm_i915_private *dev_priv = dev->dev_private;
154 struct i915_address_space *vm = &dev_priv->gtt.base;
155 struct i915_vma *vma;
156 size_t total_obj_size, total_gtt_size;
157 int count, ret;
158
159 ret = mutex_lock_interruptible(&dev->struct_mutex);
160 if (ret)
161 return ret;
162
163 /* FIXME: the user of this interface might want more than just GGTT */
164 switch (list) {
165 case ACTIVE_LIST:
166 seq_puts(m, "Active:\n");
167 head = &vm->active_list;
168 break;
169 case INACTIVE_LIST:
170 seq_puts(m, "Inactive:\n");
171 head = &vm->inactive_list;
172 break;
173 default:
174 mutex_unlock(&dev->struct_mutex);
175 return -EINVAL;
176 }
177
178 total_obj_size = total_gtt_size = count = 0;
179 list_for_each_entry(vma, head, mm_list) {
180 seq_printf(m, " ");
181 describe_obj(m, vma->obj);
182 seq_printf(m, "\n");
183 total_obj_size += vma->obj->base.size;
184 total_gtt_size += vma->node.size;
185 count++;
186 }
187 mutex_unlock(&dev->struct_mutex);
188
189 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
190 count, total_obj_size, total_gtt_size);
191 return 0;
192 }
193
194 static int obj_rank_by_stolen(void *priv,
195 struct list_head *A, struct list_head *B)
196 {
197 struct drm_i915_gem_object *a =
198 container_of(A, struct drm_i915_gem_object, obj_exec_link);
199 struct drm_i915_gem_object *b =
200 container_of(B, struct drm_i915_gem_object, obj_exec_link);
201
202 return a->stolen->start - b->stolen->start;
203 }
204
205 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
206 {
207 struct drm_info_node *node = (struct drm_info_node *) m->private;
208 struct drm_device *dev = node->minor->dev;
209 struct drm_i915_private *dev_priv = dev->dev_private;
210 struct drm_i915_gem_object *obj;
211 size_t total_obj_size, total_gtt_size;
212 LIST_HEAD(stolen);
213 int count, ret;
214
215 ret = mutex_lock_interruptible(&dev->struct_mutex);
216 if (ret)
217 return ret;
218
219 total_obj_size = total_gtt_size = count = 0;
220 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
221 if (obj->stolen == NULL)
222 continue;
223
224 list_add(&obj->obj_exec_link, &stolen);
225
226 total_obj_size += obj->base.size;
227 total_gtt_size += i915_gem_obj_ggtt_size(obj);
228 count++;
229 }
230 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
231 if (obj->stolen == NULL)
232 continue;
233
234 list_add(&obj->obj_exec_link, &stolen);
235
236 total_obj_size += obj->base.size;
237 count++;
238 }
239 list_sort(NULL, &stolen, obj_rank_by_stolen);
240 seq_puts(m, "Stolen:\n");
241 while (!list_empty(&stolen)) {
242 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
243 seq_puts(m, " ");
244 describe_obj(m, obj);
245 seq_putc(m, '\n');
246 list_del_init(&obj->obj_exec_link);
247 }
248 mutex_unlock(&dev->struct_mutex);
249
250 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
251 count, total_obj_size, total_gtt_size);
252 return 0;
253 }
254
255 #define count_objects(list, member) do { \
256 list_for_each_entry(obj, list, member) { \
257 size += i915_gem_obj_ggtt_size(obj); \
258 ++count; \
259 if (obj->map_and_fenceable) { \
260 mappable_size += i915_gem_obj_ggtt_size(obj); \
261 ++mappable_count; \
262 } \
263 } \
264 } while (0)
265
266 struct file_stats {
267 int count;
268 size_t total, active, inactive, unbound;
269 };
270
271 static int per_file_stats(int id, void *ptr, void *data)
272 {
273 struct drm_i915_gem_object *obj = ptr;
274 struct file_stats *stats = data;
275
276 stats->count++;
277 stats->total += obj->base.size;
278
279 if (i915_gem_obj_ggtt_bound(obj)) {
280 if (!list_empty(&obj->ring_list))
281 stats->active += obj->base.size;
282 else
283 stats->inactive += obj->base.size;
284 } else {
285 if (!list_empty(&obj->global_list))
286 stats->unbound += obj->base.size;
287 }
288
289 return 0;
290 }
291
292 #define count_vmas(list, member) do { \
293 list_for_each_entry(vma, list, member) { \
294 size += i915_gem_obj_ggtt_size(vma->obj); \
295 ++count; \
296 if (vma->obj->map_and_fenceable) { \
297 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
298 ++mappable_count; \
299 } \
300 } \
301 } while (0)
302
303 static int i915_gem_object_info(struct seq_file *m, void* data)
304 {
305 struct drm_info_node *node = (struct drm_info_node *) m->private;
306 struct drm_device *dev = node->minor->dev;
307 struct drm_i915_private *dev_priv = dev->dev_private;
308 u32 count, mappable_count, purgeable_count;
309 size_t size, mappable_size, purgeable_size;
310 struct drm_i915_gem_object *obj;
311 struct i915_address_space *vm = &dev_priv->gtt.base;
312 struct drm_file *file;
313 struct i915_vma *vma;
314 int ret;
315
316 ret = mutex_lock_interruptible(&dev->struct_mutex);
317 if (ret)
318 return ret;
319
320 seq_printf(m, "%u objects, %zu bytes\n",
321 dev_priv->mm.object_count,
322 dev_priv->mm.object_memory);
323
324 size = count = mappable_size = mappable_count = 0;
325 count_objects(&dev_priv->mm.bound_list, global_list);
326 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
327 count, mappable_count, size, mappable_size);
328
329 size = count = mappable_size = mappable_count = 0;
330 count_vmas(&vm->active_list, mm_list);
331 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
332 count, mappable_count, size, mappable_size);
333
334 size = count = mappable_size = mappable_count = 0;
335 count_vmas(&vm->inactive_list, mm_list);
336 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
337 count, mappable_count, size, mappable_size);
338
339 size = count = purgeable_size = purgeable_count = 0;
340 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
341 size += obj->base.size, ++count;
342 if (obj->madv == I915_MADV_DONTNEED)
343 purgeable_size += obj->base.size, ++purgeable_count;
344 }
345 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
346
347 size = count = mappable_size = mappable_count = 0;
348 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
349 if (obj->fault_mappable) {
350 size += i915_gem_obj_ggtt_size(obj);
351 ++count;
352 }
353 if (obj->pin_mappable) {
354 mappable_size += i915_gem_obj_ggtt_size(obj);
355 ++mappable_count;
356 }
357 if (obj->madv == I915_MADV_DONTNEED) {
358 purgeable_size += obj->base.size;
359 ++purgeable_count;
360 }
361 }
362 seq_printf(m, "%u purgeable objects, %zu bytes\n",
363 purgeable_count, purgeable_size);
364 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
365 mappable_count, mappable_size);
366 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
367 count, size);
368
369 seq_printf(m, "%zu [%lu] gtt total\n",
370 dev_priv->gtt.base.total,
371 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
372
373 seq_putc(m, '\n');
374 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
375 struct file_stats stats;
376
377 memset(&stats, 0, sizeof(stats));
378 idr_for_each(&file->object_idr, per_file_stats, &stats);
379 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n",
380 get_pid_task(file->pid, PIDTYPE_PID)->comm,
381 stats.count,
382 stats.total,
383 stats.active,
384 stats.inactive,
385 stats.unbound);
386 }
387
388 mutex_unlock(&dev->struct_mutex);
389
390 return 0;
391 }
392
393 static int i915_gem_gtt_info(struct seq_file *m, void *data)
394 {
395 struct drm_info_node *node = (struct drm_info_node *) m->private;
396 struct drm_device *dev = node->minor->dev;
397 uintptr_t list = (uintptr_t) node->info_ent->data;
398 struct drm_i915_private *dev_priv = dev->dev_private;
399 struct drm_i915_gem_object *obj;
400 size_t total_obj_size, total_gtt_size;
401 int count, ret;
402
403 ret = mutex_lock_interruptible(&dev->struct_mutex);
404 if (ret)
405 return ret;
406
407 total_obj_size = total_gtt_size = count = 0;
408 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
409 if (list == PINNED_LIST && obj->pin_count == 0)
410 continue;
411
412 seq_puts(m, " ");
413 describe_obj(m, obj);
414 seq_putc(m, '\n');
415 total_obj_size += obj->base.size;
416 total_gtt_size += i915_gem_obj_ggtt_size(obj);
417 count++;
418 }
419
420 mutex_unlock(&dev->struct_mutex);
421
422 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
423 count, total_obj_size, total_gtt_size);
424
425 return 0;
426 }
427
428 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
429 {
430 struct drm_info_node *node = (struct drm_info_node *) m->private;
431 struct drm_device *dev = node->minor->dev;
432 unsigned long flags;
433 struct intel_crtc *crtc;
434
435 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
436 const char pipe = pipe_name(crtc->pipe);
437 const char plane = plane_name(crtc->plane);
438 struct intel_unpin_work *work;
439
440 spin_lock_irqsave(&dev->event_lock, flags);
441 work = crtc->unpin_work;
442 if (work == NULL) {
443 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
444 pipe, plane);
445 } else {
446 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
447 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
448 pipe, plane);
449 } else {
450 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
451 pipe, plane);
452 }
453 if (work->enable_stall_check)
454 seq_puts(m, "Stall check enabled, ");
455 else
456 seq_puts(m, "Stall check waiting for page flip ioctl, ");
457 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
458
459 if (work->old_fb_obj) {
460 struct drm_i915_gem_object *obj = work->old_fb_obj;
461 if (obj)
462 seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n",
463 i915_gem_obj_ggtt_offset(obj));
464 }
465 if (work->pending_flip_obj) {
466 struct drm_i915_gem_object *obj = work->pending_flip_obj;
467 if (obj)
468 seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n",
469 i915_gem_obj_ggtt_offset(obj));
470 }
471 }
472 spin_unlock_irqrestore(&dev->event_lock, flags);
473 }
474
475 return 0;
476 }
477
478 static int i915_gem_request_info(struct seq_file *m, void *data)
479 {
480 struct drm_info_node *node = (struct drm_info_node *) m->private;
481 struct drm_device *dev = node->minor->dev;
482 drm_i915_private_t *dev_priv = dev->dev_private;
483 struct intel_ring_buffer *ring;
484 struct drm_i915_gem_request *gem_request;
485 int ret, count, i;
486
487 ret = mutex_lock_interruptible(&dev->struct_mutex);
488 if (ret)
489 return ret;
490
491 count = 0;
492 for_each_ring(ring, dev_priv, i) {
493 if (list_empty(&ring->request_list))
494 continue;
495
496 seq_printf(m, "%s requests:\n", ring->name);
497 list_for_each_entry(gem_request,
498 &ring->request_list,
499 list) {
500 seq_printf(m, " %d @ %d\n",
501 gem_request->seqno,
502 (int) (jiffies - gem_request->emitted_jiffies));
503 }
504 count++;
505 }
506 mutex_unlock(&dev->struct_mutex);
507
508 if (count == 0)
509 seq_puts(m, "No requests\n");
510
511 return 0;
512 }
513
514 static void i915_ring_seqno_info(struct seq_file *m,
515 struct intel_ring_buffer *ring)
516 {
517 if (ring->get_seqno) {
518 seq_printf(m, "Current sequence (%s): %u\n",
519 ring->name, ring->get_seqno(ring, false));
520 }
521 }
522
523 static int i915_gem_seqno_info(struct seq_file *m, void *data)
524 {
525 struct drm_info_node *node = (struct drm_info_node *) m->private;
526 struct drm_device *dev = node->minor->dev;
527 drm_i915_private_t *dev_priv = dev->dev_private;
528 struct intel_ring_buffer *ring;
529 int ret, i;
530
531 ret = mutex_lock_interruptible(&dev->struct_mutex);
532 if (ret)
533 return ret;
534
535 for_each_ring(ring, dev_priv, i)
536 i915_ring_seqno_info(m, ring);
537
538 mutex_unlock(&dev->struct_mutex);
539
540 return 0;
541 }
542
543
544 static int i915_interrupt_info(struct seq_file *m, void *data)
545 {
546 struct drm_info_node *node = (struct drm_info_node *) m->private;
547 struct drm_device *dev = node->minor->dev;
548 drm_i915_private_t *dev_priv = dev->dev_private;
549 struct intel_ring_buffer *ring;
550 int ret, i, pipe;
551
552 ret = mutex_lock_interruptible(&dev->struct_mutex);
553 if (ret)
554 return ret;
555
556 if (IS_VALLEYVIEW(dev)) {
557 seq_printf(m, "Display IER:\t%08x\n",
558 I915_READ(VLV_IER));
559 seq_printf(m, "Display IIR:\t%08x\n",
560 I915_READ(VLV_IIR));
561 seq_printf(m, "Display IIR_RW:\t%08x\n",
562 I915_READ(VLV_IIR_RW));
563 seq_printf(m, "Display IMR:\t%08x\n",
564 I915_READ(VLV_IMR));
565 for_each_pipe(pipe)
566 seq_printf(m, "Pipe %c stat:\t%08x\n",
567 pipe_name(pipe),
568 I915_READ(PIPESTAT(pipe)));
569
570 seq_printf(m, "Master IER:\t%08x\n",
571 I915_READ(VLV_MASTER_IER));
572
573 seq_printf(m, "Render IER:\t%08x\n",
574 I915_READ(GTIER));
575 seq_printf(m, "Render IIR:\t%08x\n",
576 I915_READ(GTIIR));
577 seq_printf(m, "Render IMR:\t%08x\n",
578 I915_READ(GTIMR));
579
580 seq_printf(m, "PM IER:\t\t%08x\n",
581 I915_READ(GEN6_PMIER));
582 seq_printf(m, "PM IIR:\t\t%08x\n",
583 I915_READ(GEN6_PMIIR));
584 seq_printf(m, "PM IMR:\t\t%08x\n",
585 I915_READ(GEN6_PMIMR));
586
587 seq_printf(m, "Port hotplug:\t%08x\n",
588 I915_READ(PORT_HOTPLUG_EN));
589 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
590 I915_READ(VLV_DPFLIPSTAT));
591 seq_printf(m, "DPINVGTT:\t%08x\n",
592 I915_READ(DPINVGTT));
593
594 } else if (!HAS_PCH_SPLIT(dev)) {
595 seq_printf(m, "Interrupt enable: %08x\n",
596 I915_READ(IER));
597 seq_printf(m, "Interrupt identity: %08x\n",
598 I915_READ(IIR));
599 seq_printf(m, "Interrupt mask: %08x\n",
600 I915_READ(IMR));
601 for_each_pipe(pipe)
602 seq_printf(m, "Pipe %c stat: %08x\n",
603 pipe_name(pipe),
604 I915_READ(PIPESTAT(pipe)));
605 } else {
606 seq_printf(m, "North Display Interrupt enable: %08x\n",
607 I915_READ(DEIER));
608 seq_printf(m, "North Display Interrupt identity: %08x\n",
609 I915_READ(DEIIR));
610 seq_printf(m, "North Display Interrupt mask: %08x\n",
611 I915_READ(DEIMR));
612 seq_printf(m, "South Display Interrupt enable: %08x\n",
613 I915_READ(SDEIER));
614 seq_printf(m, "South Display Interrupt identity: %08x\n",
615 I915_READ(SDEIIR));
616 seq_printf(m, "South Display Interrupt mask: %08x\n",
617 I915_READ(SDEIMR));
618 seq_printf(m, "Graphics Interrupt enable: %08x\n",
619 I915_READ(GTIER));
620 seq_printf(m, "Graphics Interrupt identity: %08x\n",
621 I915_READ(GTIIR));
622 seq_printf(m, "Graphics Interrupt mask: %08x\n",
623 I915_READ(GTIMR));
624 }
625 seq_printf(m, "Interrupts received: %d\n",
626 atomic_read(&dev_priv->irq_received));
627 for_each_ring(ring, dev_priv, i) {
628 if (IS_GEN6(dev) || IS_GEN7(dev)) {
629 seq_printf(m,
630 "Graphics Interrupt mask (%s): %08x\n",
631 ring->name, I915_READ_IMR(ring));
632 }
633 i915_ring_seqno_info(m, ring);
634 }
635 mutex_unlock(&dev->struct_mutex);
636
637 return 0;
638 }
639
640 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
641 {
642 struct drm_info_node *node = (struct drm_info_node *) m->private;
643 struct drm_device *dev = node->minor->dev;
644 drm_i915_private_t *dev_priv = dev->dev_private;
645 int i, ret;
646
647 ret = mutex_lock_interruptible(&dev->struct_mutex);
648 if (ret)
649 return ret;
650
651 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
652 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
653 for (i = 0; i < dev_priv->num_fence_regs; i++) {
654 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
655
656 seq_printf(m, "Fence %d, pin count = %d, object = ",
657 i, dev_priv->fence_regs[i].pin_count);
658 if (obj == NULL)
659 seq_puts(m, "unused");
660 else
661 describe_obj(m, obj);
662 seq_putc(m, '\n');
663 }
664
665 mutex_unlock(&dev->struct_mutex);
666 return 0;
667 }
668
669 static int i915_hws_info(struct seq_file *m, void *data)
670 {
671 struct drm_info_node *node = (struct drm_info_node *) m->private;
672 struct drm_device *dev = node->minor->dev;
673 drm_i915_private_t *dev_priv = dev->dev_private;
674 struct intel_ring_buffer *ring;
675 const u32 *hws;
676 int i;
677
678 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
679 hws = ring->status_page.page_addr;
680 if (hws == NULL)
681 return 0;
682
683 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
684 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
685 i * 4,
686 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
687 }
688 return 0;
689 }
690
691 static ssize_t
692 i915_error_state_write(struct file *filp,
693 const char __user *ubuf,
694 size_t cnt,
695 loff_t *ppos)
696 {
697 struct i915_error_state_file_priv *error_priv = filp->private_data;
698 struct drm_device *dev = error_priv->dev;
699 int ret;
700
701 DRM_DEBUG_DRIVER("Resetting error state\n");
702
703 ret = mutex_lock_interruptible(&dev->struct_mutex);
704 if (ret)
705 return ret;
706
707 i915_destroy_error_state(dev);
708 mutex_unlock(&dev->struct_mutex);
709
710 return cnt;
711 }
712
713 static int i915_error_state_open(struct inode *inode, struct file *file)
714 {
715 struct drm_device *dev = inode->i_private;
716 struct i915_error_state_file_priv *error_priv;
717
718 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
719 if (!error_priv)
720 return -ENOMEM;
721
722 error_priv->dev = dev;
723
724 i915_error_state_get(dev, error_priv);
725
726 file->private_data = error_priv;
727
728 return 0;
729 }
730
731 static int i915_error_state_release(struct inode *inode, struct file *file)
732 {
733 struct i915_error_state_file_priv *error_priv = file->private_data;
734
735 i915_error_state_put(error_priv);
736 kfree(error_priv);
737
738 return 0;
739 }
740
741 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
742 size_t count, loff_t *pos)
743 {
744 struct i915_error_state_file_priv *error_priv = file->private_data;
745 struct drm_i915_error_state_buf error_str;
746 loff_t tmp_pos = 0;
747 ssize_t ret_count = 0;
748 int ret;
749
750 ret = i915_error_state_buf_init(&error_str, count, *pos);
751 if (ret)
752 return ret;
753
754 ret = i915_error_state_to_str(&error_str, error_priv);
755 if (ret)
756 goto out;
757
758 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
759 error_str.buf,
760 error_str.bytes);
761
762 if (ret_count < 0)
763 ret = ret_count;
764 else
765 *pos = error_str.start + ret_count;
766 out:
767 i915_error_state_buf_release(&error_str);
768 return ret ?: ret_count;
769 }
770
771 static const struct file_operations i915_error_state_fops = {
772 .owner = THIS_MODULE,
773 .open = i915_error_state_open,
774 .read = i915_error_state_read,
775 .write = i915_error_state_write,
776 .llseek = default_llseek,
777 .release = i915_error_state_release,
778 };
779
780 static int
781 i915_next_seqno_get(void *data, u64 *val)
782 {
783 struct drm_device *dev = data;
784 drm_i915_private_t *dev_priv = dev->dev_private;
785 int ret;
786
787 ret = mutex_lock_interruptible(&dev->struct_mutex);
788 if (ret)
789 return ret;
790
791 *val = dev_priv->next_seqno;
792 mutex_unlock(&dev->struct_mutex);
793
794 return 0;
795 }
796
797 static int
798 i915_next_seqno_set(void *data, u64 val)
799 {
800 struct drm_device *dev = data;
801 int ret;
802
803 ret = mutex_lock_interruptible(&dev->struct_mutex);
804 if (ret)
805 return ret;
806
807 ret = i915_gem_set_seqno(dev, val);
808 mutex_unlock(&dev->struct_mutex);
809
810 return ret;
811 }
812
813 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
814 i915_next_seqno_get, i915_next_seqno_set,
815 "0x%llx\n");
816
817 static int i915_rstdby_delays(struct seq_file *m, void *unused)
818 {
819 struct drm_info_node *node = (struct drm_info_node *) m->private;
820 struct drm_device *dev = node->minor->dev;
821 drm_i915_private_t *dev_priv = dev->dev_private;
822 u16 crstanddelay;
823 int ret;
824
825 ret = mutex_lock_interruptible(&dev->struct_mutex);
826 if (ret)
827 return ret;
828
829 crstanddelay = I915_READ16(CRSTANDVID);
830
831 mutex_unlock(&dev->struct_mutex);
832
833 seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
834
835 return 0;
836 }
837
838 static int i915_cur_delayinfo(struct seq_file *m, void *unused)
839 {
840 struct drm_info_node *node = (struct drm_info_node *) m->private;
841 struct drm_device *dev = node->minor->dev;
842 drm_i915_private_t *dev_priv = dev->dev_private;
843 int ret;
844
845 if (IS_GEN5(dev)) {
846 u16 rgvswctl = I915_READ16(MEMSWCTL);
847 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
848
849 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
850 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
851 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
852 MEMSTAT_VID_SHIFT);
853 seq_printf(m, "Current P-state: %d\n",
854 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
855 } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
856 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
857 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
858 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
859 u32 rpstat, cagf;
860 u32 rpupei, rpcurup, rpprevup;
861 u32 rpdownei, rpcurdown, rpprevdown;
862 int max_freq;
863
864 /* RPSTAT1 is in the GT power well */
865 ret = mutex_lock_interruptible(&dev->struct_mutex);
866 if (ret)
867 return ret;
868
869 gen6_gt_force_wake_get(dev_priv);
870
871 rpstat = I915_READ(GEN6_RPSTAT1);
872 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
873 rpcurup = I915_READ(GEN6_RP_CUR_UP);
874 rpprevup = I915_READ(GEN6_RP_PREV_UP);
875 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
876 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
877 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
878 if (IS_HASWELL(dev))
879 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
880 else
881 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
882 cagf *= GT_FREQUENCY_MULTIPLIER;
883
884 gen6_gt_force_wake_put(dev_priv);
885 mutex_unlock(&dev->struct_mutex);
886
887 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
888 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
889 seq_printf(m, "Render p-state ratio: %d\n",
890 (gt_perf_status & 0xff00) >> 8);
891 seq_printf(m, "Render p-state VID: %d\n",
892 gt_perf_status & 0xff);
893 seq_printf(m, "Render p-state limit: %d\n",
894 rp_state_limits & 0xff);
895 seq_printf(m, "CAGF: %dMHz\n", cagf);
896 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
897 GEN6_CURICONT_MASK);
898 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
899 GEN6_CURBSYTAVG_MASK);
900 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
901 GEN6_CURBSYTAVG_MASK);
902 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
903 GEN6_CURIAVG_MASK);
904 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
905 GEN6_CURBSYTAVG_MASK);
906 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
907 GEN6_CURBSYTAVG_MASK);
908
909 max_freq = (rp_state_cap & 0xff0000) >> 16;
910 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
911 max_freq * GT_FREQUENCY_MULTIPLIER);
912
913 max_freq = (rp_state_cap & 0xff00) >> 8;
914 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
915 max_freq * GT_FREQUENCY_MULTIPLIER);
916
917 max_freq = rp_state_cap & 0xff;
918 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
919 max_freq * GT_FREQUENCY_MULTIPLIER);
920
921 seq_printf(m, "Max overclocked frequency: %dMHz\n",
922 dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER);
923 } else if (IS_VALLEYVIEW(dev)) {
924 u32 freq_sts, val;
925
926 mutex_lock(&dev_priv->rps.hw_lock);
927 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
928 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
929 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
930
931 val = vlv_punit_read(dev_priv, PUNIT_FUSE_BUS1);
932 seq_printf(m, "max GPU freq: %d MHz\n",
933 vlv_gpu_freq(dev_priv->mem_freq, val));
934
935 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM);
936 seq_printf(m, "min GPU freq: %d MHz\n",
937 vlv_gpu_freq(dev_priv->mem_freq, val));
938
939 seq_printf(m, "current GPU freq: %d MHz\n",
940 vlv_gpu_freq(dev_priv->mem_freq,
941 (freq_sts >> 8) & 0xff));
942 mutex_unlock(&dev_priv->rps.hw_lock);
943 } else {
944 seq_puts(m, "no P-state info available\n");
945 }
946
947 return 0;
948 }
949
950 static int i915_delayfreq_table(struct seq_file *m, void *unused)
951 {
952 struct drm_info_node *node = (struct drm_info_node *) m->private;
953 struct drm_device *dev = node->minor->dev;
954 drm_i915_private_t *dev_priv = dev->dev_private;
955 u32 delayfreq;
956 int ret, i;
957
958 ret = mutex_lock_interruptible(&dev->struct_mutex);
959 if (ret)
960 return ret;
961
962 for (i = 0; i < 16; i++) {
963 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
964 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
965 (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
966 }
967
968 mutex_unlock(&dev->struct_mutex);
969
970 return 0;
971 }
972
973 static inline int MAP_TO_MV(int map)
974 {
975 return 1250 - (map * 25);
976 }
977
978 static int i915_inttoext_table(struct seq_file *m, void *unused)
979 {
980 struct drm_info_node *node = (struct drm_info_node *) m->private;
981 struct drm_device *dev = node->minor->dev;
982 drm_i915_private_t *dev_priv = dev->dev_private;
983 u32 inttoext;
984 int ret, i;
985
986 ret = mutex_lock_interruptible(&dev->struct_mutex);
987 if (ret)
988 return ret;
989
990 for (i = 1; i <= 32; i++) {
991 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
992 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
993 }
994
995 mutex_unlock(&dev->struct_mutex);
996
997 return 0;
998 }
999
1000 static int ironlake_drpc_info(struct seq_file *m)
1001 {
1002 struct drm_info_node *node = (struct drm_info_node *) m->private;
1003 struct drm_device *dev = node->minor->dev;
1004 drm_i915_private_t *dev_priv = dev->dev_private;
1005 u32 rgvmodectl, rstdbyctl;
1006 u16 crstandvid;
1007 int ret;
1008
1009 ret = mutex_lock_interruptible(&dev->struct_mutex);
1010 if (ret)
1011 return ret;
1012
1013 rgvmodectl = I915_READ(MEMMODECTL);
1014 rstdbyctl = I915_READ(RSTDBYCTL);
1015 crstandvid = I915_READ16(CRSTANDVID);
1016
1017 mutex_unlock(&dev->struct_mutex);
1018
1019 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1020 "yes" : "no");
1021 seq_printf(m, "Boost freq: %d\n",
1022 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1023 MEMMODE_BOOST_FREQ_SHIFT);
1024 seq_printf(m, "HW control enabled: %s\n",
1025 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1026 seq_printf(m, "SW control enabled: %s\n",
1027 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1028 seq_printf(m, "Gated voltage change: %s\n",
1029 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1030 seq_printf(m, "Starting frequency: P%d\n",
1031 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1032 seq_printf(m, "Max P-state: P%d\n",
1033 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1034 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1035 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1036 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1037 seq_printf(m, "Render standby enabled: %s\n",
1038 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1039 seq_puts(m, "Current RS state: ");
1040 switch (rstdbyctl & RSX_STATUS_MASK) {
1041 case RSX_STATUS_ON:
1042 seq_puts(m, "on\n");
1043 break;
1044 case RSX_STATUS_RC1:
1045 seq_puts(m, "RC1\n");
1046 break;
1047 case RSX_STATUS_RC1E:
1048 seq_puts(m, "RC1E\n");
1049 break;
1050 case RSX_STATUS_RS1:
1051 seq_puts(m, "RS1\n");
1052 break;
1053 case RSX_STATUS_RS2:
1054 seq_puts(m, "RS2 (RC6)\n");
1055 break;
1056 case RSX_STATUS_RS3:
1057 seq_puts(m, "RC3 (RC6+)\n");
1058 break;
1059 default:
1060 seq_puts(m, "unknown\n");
1061 break;
1062 }
1063
1064 return 0;
1065 }
1066
1067 static int gen6_drpc_info(struct seq_file *m)
1068 {
1069
1070 struct drm_info_node *node = (struct drm_info_node *) m->private;
1071 struct drm_device *dev = node->minor->dev;
1072 struct drm_i915_private *dev_priv = dev->dev_private;
1073 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1074 unsigned forcewake_count;
1075 int count = 0, ret;
1076
1077 ret = mutex_lock_interruptible(&dev->struct_mutex);
1078 if (ret)
1079 return ret;
1080
1081 spin_lock_irq(&dev_priv->uncore.lock);
1082 forcewake_count = dev_priv->uncore.forcewake_count;
1083 spin_unlock_irq(&dev_priv->uncore.lock);
1084
1085 if (forcewake_count) {
1086 seq_puts(m, "RC information inaccurate because somebody "
1087 "holds a forcewake reference \n");
1088 } else {
1089 /* NB: we cannot use forcewake, else we read the wrong values */
1090 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1091 udelay(10);
1092 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1093 }
1094
1095 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1096 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1097
1098 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1099 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1100 mutex_unlock(&dev->struct_mutex);
1101 mutex_lock(&dev_priv->rps.hw_lock);
1102 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1103 mutex_unlock(&dev_priv->rps.hw_lock);
1104
1105 seq_printf(m, "Video Turbo Mode: %s\n",
1106 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1107 seq_printf(m, "HW control enabled: %s\n",
1108 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1109 seq_printf(m, "SW control enabled: %s\n",
1110 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1111 GEN6_RP_MEDIA_SW_MODE));
1112 seq_printf(m, "RC1e Enabled: %s\n",
1113 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1114 seq_printf(m, "RC6 Enabled: %s\n",
1115 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1116 seq_printf(m, "Deep RC6 Enabled: %s\n",
1117 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1118 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1119 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1120 seq_puts(m, "Current RC state: ");
1121 switch (gt_core_status & GEN6_RCn_MASK) {
1122 case GEN6_RC0:
1123 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1124 seq_puts(m, "Core Power Down\n");
1125 else
1126 seq_puts(m, "on\n");
1127 break;
1128 case GEN6_RC3:
1129 seq_puts(m, "RC3\n");
1130 break;
1131 case GEN6_RC6:
1132 seq_puts(m, "RC6\n");
1133 break;
1134 case GEN6_RC7:
1135 seq_puts(m, "RC7\n");
1136 break;
1137 default:
1138 seq_puts(m, "Unknown\n");
1139 break;
1140 }
1141
1142 seq_printf(m, "Core Power Down: %s\n",
1143 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1144
1145 /* Not exactly sure what this is */
1146 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1147 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1148 seq_printf(m, "RC6 residency since boot: %u\n",
1149 I915_READ(GEN6_GT_GFX_RC6));
1150 seq_printf(m, "RC6+ residency since boot: %u\n",
1151 I915_READ(GEN6_GT_GFX_RC6p));
1152 seq_printf(m, "RC6++ residency since boot: %u\n",
1153 I915_READ(GEN6_GT_GFX_RC6pp));
1154
1155 seq_printf(m, "RC6 voltage: %dmV\n",
1156 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1157 seq_printf(m, "RC6+ voltage: %dmV\n",
1158 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1159 seq_printf(m, "RC6++ voltage: %dmV\n",
1160 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1161 return 0;
1162 }
1163
1164 static int i915_drpc_info(struct seq_file *m, void *unused)
1165 {
1166 struct drm_info_node *node = (struct drm_info_node *) m->private;
1167 struct drm_device *dev = node->minor->dev;
1168
1169 if (IS_GEN6(dev) || IS_GEN7(dev))
1170 return gen6_drpc_info(m);
1171 else
1172 return ironlake_drpc_info(m);
1173 }
1174
1175 static int i915_fbc_status(struct seq_file *m, void *unused)
1176 {
1177 struct drm_info_node *node = (struct drm_info_node *) m->private;
1178 struct drm_device *dev = node->minor->dev;
1179 drm_i915_private_t *dev_priv = dev->dev_private;
1180
1181 if (!I915_HAS_FBC(dev)) {
1182 seq_puts(m, "FBC unsupported on this chipset\n");
1183 return 0;
1184 }
1185
1186 if (intel_fbc_enabled(dev)) {
1187 seq_puts(m, "FBC enabled\n");
1188 } else {
1189 seq_puts(m, "FBC disabled: ");
1190 switch (dev_priv->fbc.no_fbc_reason) {
1191 case FBC_OK:
1192 seq_puts(m, "FBC actived, but currently disabled in hardware");
1193 break;
1194 case FBC_UNSUPPORTED:
1195 seq_puts(m, "unsupported by this chipset");
1196 break;
1197 case FBC_NO_OUTPUT:
1198 seq_puts(m, "no outputs");
1199 break;
1200 case FBC_STOLEN_TOO_SMALL:
1201 seq_puts(m, "not enough stolen memory");
1202 break;
1203 case FBC_UNSUPPORTED_MODE:
1204 seq_puts(m, "mode not supported");
1205 break;
1206 case FBC_MODE_TOO_LARGE:
1207 seq_puts(m, "mode too large");
1208 break;
1209 case FBC_BAD_PLANE:
1210 seq_puts(m, "FBC unsupported on plane");
1211 break;
1212 case FBC_NOT_TILED:
1213 seq_puts(m, "scanout buffer not tiled");
1214 break;
1215 case FBC_MULTIPLE_PIPES:
1216 seq_puts(m, "multiple pipes are enabled");
1217 break;
1218 case FBC_MODULE_PARAM:
1219 seq_puts(m, "disabled per module param (default off)");
1220 break;
1221 case FBC_CHIP_DEFAULT:
1222 seq_puts(m, "disabled per chip default");
1223 break;
1224 default:
1225 seq_puts(m, "unknown reason");
1226 }
1227 seq_putc(m, '\n');
1228 }
1229 return 0;
1230 }
1231
1232 static int i915_ips_status(struct seq_file *m, void *unused)
1233 {
1234 struct drm_info_node *node = (struct drm_info_node *) m->private;
1235 struct drm_device *dev = node->minor->dev;
1236 struct drm_i915_private *dev_priv = dev->dev_private;
1237
1238 if (!HAS_IPS(dev)) {
1239 seq_puts(m, "not supported\n");
1240 return 0;
1241 }
1242
1243 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1244 seq_puts(m, "enabled\n");
1245 else
1246 seq_puts(m, "disabled\n");
1247
1248 return 0;
1249 }
1250
1251 static int i915_sr_status(struct seq_file *m, void *unused)
1252 {
1253 struct drm_info_node *node = (struct drm_info_node *) m->private;
1254 struct drm_device *dev = node->minor->dev;
1255 drm_i915_private_t *dev_priv = dev->dev_private;
1256 bool sr_enabled = false;
1257
1258 if (HAS_PCH_SPLIT(dev))
1259 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1260 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1261 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1262 else if (IS_I915GM(dev))
1263 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1264 else if (IS_PINEVIEW(dev))
1265 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1266
1267 seq_printf(m, "self-refresh: %s\n",
1268 sr_enabled ? "enabled" : "disabled");
1269
1270 return 0;
1271 }
1272
1273 static int i915_emon_status(struct seq_file *m, void *unused)
1274 {
1275 struct drm_info_node *node = (struct drm_info_node *) m->private;
1276 struct drm_device *dev = node->minor->dev;
1277 drm_i915_private_t *dev_priv = dev->dev_private;
1278 unsigned long temp, chipset, gfx;
1279 int ret;
1280
1281 if (!IS_GEN5(dev))
1282 return -ENODEV;
1283
1284 ret = mutex_lock_interruptible(&dev->struct_mutex);
1285 if (ret)
1286 return ret;
1287
1288 temp = i915_mch_val(dev_priv);
1289 chipset = i915_chipset_val(dev_priv);
1290 gfx = i915_gfx_val(dev_priv);
1291 mutex_unlock(&dev->struct_mutex);
1292
1293 seq_printf(m, "GMCH temp: %ld\n", temp);
1294 seq_printf(m, "Chipset power: %ld\n", chipset);
1295 seq_printf(m, "GFX power: %ld\n", gfx);
1296 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1297
1298 return 0;
1299 }
1300
1301 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1302 {
1303 struct drm_info_node *node = (struct drm_info_node *) m->private;
1304 struct drm_device *dev = node->minor->dev;
1305 drm_i915_private_t *dev_priv = dev->dev_private;
1306 int ret;
1307 int gpu_freq, ia_freq;
1308
1309 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1310 seq_puts(m, "unsupported on this chipset\n");
1311 return 0;
1312 }
1313
1314 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1315 if (ret)
1316 return ret;
1317
1318 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1319
1320 for (gpu_freq = dev_priv->rps.min_delay;
1321 gpu_freq <= dev_priv->rps.max_delay;
1322 gpu_freq++) {
1323 ia_freq = gpu_freq;
1324 sandybridge_pcode_read(dev_priv,
1325 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1326 &ia_freq);
1327 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1328 gpu_freq * GT_FREQUENCY_MULTIPLIER,
1329 ((ia_freq >> 0) & 0xff) * 100,
1330 ((ia_freq >> 8) & 0xff) * 100);
1331 }
1332
1333 mutex_unlock(&dev_priv->rps.hw_lock);
1334
1335 return 0;
1336 }
1337
1338 static int i915_gfxec(struct seq_file *m, void *unused)
1339 {
1340 struct drm_info_node *node = (struct drm_info_node *) m->private;
1341 struct drm_device *dev = node->minor->dev;
1342 drm_i915_private_t *dev_priv = dev->dev_private;
1343 int ret;
1344
1345 ret = mutex_lock_interruptible(&dev->struct_mutex);
1346 if (ret)
1347 return ret;
1348
1349 seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1350
1351 mutex_unlock(&dev->struct_mutex);
1352
1353 return 0;
1354 }
1355
1356 static int i915_opregion(struct seq_file *m, void *unused)
1357 {
1358 struct drm_info_node *node = (struct drm_info_node *) m->private;
1359 struct drm_device *dev = node->minor->dev;
1360 drm_i915_private_t *dev_priv = dev->dev_private;
1361 struct intel_opregion *opregion = &dev_priv->opregion;
1362 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1363 int ret;
1364
1365 if (data == NULL)
1366 return -ENOMEM;
1367
1368 ret = mutex_lock_interruptible(&dev->struct_mutex);
1369 if (ret)
1370 goto out;
1371
1372 if (opregion->header) {
1373 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1374 seq_write(m, data, OPREGION_SIZE);
1375 }
1376
1377 mutex_unlock(&dev->struct_mutex);
1378
1379 out:
1380 kfree(data);
1381 return 0;
1382 }
1383
1384 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1385 {
1386 struct drm_info_node *node = (struct drm_info_node *) m->private;
1387 struct drm_device *dev = node->minor->dev;
1388 drm_i915_private_t *dev_priv = dev->dev_private;
1389 struct intel_fbdev *ifbdev;
1390 struct intel_framebuffer *fb;
1391 int ret;
1392
1393 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1394 if (ret)
1395 return ret;
1396
1397 ifbdev = dev_priv->fbdev;
1398 fb = to_intel_framebuffer(ifbdev->helper.fb);
1399
1400 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1401 fb->base.width,
1402 fb->base.height,
1403 fb->base.depth,
1404 fb->base.bits_per_pixel,
1405 atomic_read(&fb->base.refcount.refcount));
1406 describe_obj(m, fb->obj);
1407 seq_putc(m, '\n');
1408 mutex_unlock(&dev->mode_config.mutex);
1409
1410 mutex_lock(&dev->mode_config.fb_lock);
1411 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1412 if (&fb->base == ifbdev->helper.fb)
1413 continue;
1414
1415 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1416 fb->base.width,
1417 fb->base.height,
1418 fb->base.depth,
1419 fb->base.bits_per_pixel,
1420 atomic_read(&fb->base.refcount.refcount));
1421 describe_obj(m, fb->obj);
1422 seq_putc(m, '\n');
1423 }
1424 mutex_unlock(&dev->mode_config.fb_lock);
1425
1426 return 0;
1427 }
1428
1429 static int i915_context_status(struct seq_file *m, void *unused)
1430 {
1431 struct drm_info_node *node = (struct drm_info_node *) m->private;
1432 struct drm_device *dev = node->minor->dev;
1433 drm_i915_private_t *dev_priv = dev->dev_private;
1434 struct intel_ring_buffer *ring;
1435 int ret, i;
1436
1437 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1438 if (ret)
1439 return ret;
1440
1441 if (dev_priv->ips.pwrctx) {
1442 seq_puts(m, "power context ");
1443 describe_obj(m, dev_priv->ips.pwrctx);
1444 seq_putc(m, '\n');
1445 }
1446
1447 if (dev_priv->ips.renderctx) {
1448 seq_puts(m, "render context ");
1449 describe_obj(m, dev_priv->ips.renderctx);
1450 seq_putc(m, '\n');
1451 }
1452
1453 for_each_ring(ring, dev_priv, i) {
1454 if (ring->default_context) {
1455 seq_printf(m, "HW default context %s ring ", ring->name);
1456 describe_obj(m, ring->default_context->obj);
1457 seq_putc(m, '\n');
1458 }
1459 }
1460
1461 mutex_unlock(&dev->mode_config.mutex);
1462
1463 return 0;
1464 }
1465
1466 static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1467 {
1468 struct drm_info_node *node = (struct drm_info_node *) m->private;
1469 struct drm_device *dev = node->minor->dev;
1470 struct drm_i915_private *dev_priv = dev->dev_private;
1471 unsigned forcewake_count;
1472
1473 spin_lock_irq(&dev_priv->uncore.lock);
1474 forcewake_count = dev_priv->uncore.forcewake_count;
1475 spin_unlock_irq(&dev_priv->uncore.lock);
1476
1477 seq_printf(m, "forcewake count = %u\n", forcewake_count);
1478
1479 return 0;
1480 }
1481
1482 static const char *swizzle_string(unsigned swizzle)
1483 {
1484 switch (swizzle) {
1485 case I915_BIT_6_SWIZZLE_NONE:
1486 return "none";
1487 case I915_BIT_6_SWIZZLE_9:
1488 return "bit9";
1489 case I915_BIT_6_SWIZZLE_9_10:
1490 return "bit9/bit10";
1491 case I915_BIT_6_SWIZZLE_9_11:
1492 return "bit9/bit11";
1493 case I915_BIT_6_SWIZZLE_9_10_11:
1494 return "bit9/bit10/bit11";
1495 case I915_BIT_6_SWIZZLE_9_17:
1496 return "bit9/bit17";
1497 case I915_BIT_6_SWIZZLE_9_10_17:
1498 return "bit9/bit10/bit17";
1499 case I915_BIT_6_SWIZZLE_UNKNOWN:
1500 return "unknown";
1501 }
1502
1503 return "bug";
1504 }
1505
1506 static int i915_swizzle_info(struct seq_file *m, void *data)
1507 {
1508 struct drm_info_node *node = (struct drm_info_node *) m->private;
1509 struct drm_device *dev = node->minor->dev;
1510 struct drm_i915_private *dev_priv = dev->dev_private;
1511 int ret;
1512
1513 ret = mutex_lock_interruptible(&dev->struct_mutex);
1514 if (ret)
1515 return ret;
1516
1517 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1518 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1519 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1520 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1521
1522 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1523 seq_printf(m, "DDC = 0x%08x\n",
1524 I915_READ(DCC));
1525 seq_printf(m, "C0DRB3 = 0x%04x\n",
1526 I915_READ16(C0DRB3));
1527 seq_printf(m, "C1DRB3 = 0x%04x\n",
1528 I915_READ16(C1DRB3));
1529 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1530 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1531 I915_READ(MAD_DIMM_C0));
1532 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1533 I915_READ(MAD_DIMM_C1));
1534 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1535 I915_READ(MAD_DIMM_C2));
1536 seq_printf(m, "TILECTL = 0x%08x\n",
1537 I915_READ(TILECTL));
1538 seq_printf(m, "ARB_MODE = 0x%08x\n",
1539 I915_READ(ARB_MODE));
1540 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1541 I915_READ(DISP_ARB_CTL));
1542 }
1543 mutex_unlock(&dev->struct_mutex);
1544
1545 return 0;
1546 }
1547
1548 static int i915_ppgtt_info(struct seq_file *m, void *data)
1549 {
1550 struct drm_info_node *node = (struct drm_info_node *) m->private;
1551 struct drm_device *dev = node->minor->dev;
1552 struct drm_i915_private *dev_priv = dev->dev_private;
1553 struct intel_ring_buffer *ring;
1554 int i, ret;
1555
1556
1557 ret = mutex_lock_interruptible(&dev->struct_mutex);
1558 if (ret)
1559 return ret;
1560 if (INTEL_INFO(dev)->gen == 6)
1561 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1562
1563 for_each_ring(ring, dev_priv, i) {
1564 seq_printf(m, "%s\n", ring->name);
1565 if (INTEL_INFO(dev)->gen == 7)
1566 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1567 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1568 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1569 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1570 }
1571 if (dev_priv->mm.aliasing_ppgtt) {
1572 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1573
1574 seq_puts(m, "aliasing PPGTT:\n");
1575 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1576 }
1577 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
1578 mutex_unlock(&dev->struct_mutex);
1579
1580 return 0;
1581 }
1582
1583 static int i915_dpio_info(struct seq_file *m, void *data)
1584 {
1585 struct drm_info_node *node = (struct drm_info_node *) m->private;
1586 struct drm_device *dev = node->minor->dev;
1587 struct drm_i915_private *dev_priv = dev->dev_private;
1588 int ret;
1589
1590
1591 if (!IS_VALLEYVIEW(dev)) {
1592 seq_puts(m, "unsupported\n");
1593 return 0;
1594 }
1595
1596 ret = mutex_lock_interruptible(&dev_priv->dpio_lock);
1597 if (ret)
1598 return ret;
1599
1600 seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
1601
1602 seq_printf(m, "DPIO_DIV_A: 0x%08x\n",
1603 vlv_dpio_read(dev_priv, _DPIO_DIV_A));
1604 seq_printf(m, "DPIO_DIV_B: 0x%08x\n",
1605 vlv_dpio_read(dev_priv, _DPIO_DIV_B));
1606
1607 seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n",
1608 vlv_dpio_read(dev_priv, _DPIO_REFSFR_A));
1609 seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n",
1610 vlv_dpio_read(dev_priv, _DPIO_REFSFR_B));
1611
1612 seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n",
1613 vlv_dpio_read(dev_priv, _DPIO_CORE_CLK_A));
1614 seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n",
1615 vlv_dpio_read(dev_priv, _DPIO_CORE_CLK_B));
1616
1617 seq_printf(m, "DPIO_LPF_COEFF_A: 0x%08x\n",
1618 vlv_dpio_read(dev_priv, _DPIO_LPF_COEFF_A));
1619 seq_printf(m, "DPIO_LPF_COEFF_B: 0x%08x\n",
1620 vlv_dpio_read(dev_priv, _DPIO_LPF_COEFF_B));
1621
1622 seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
1623 vlv_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE));
1624
1625 mutex_unlock(&dev_priv->dpio_lock);
1626
1627 return 0;
1628 }
1629
1630 static int i915_llc(struct seq_file *m, void *data)
1631 {
1632 struct drm_info_node *node = (struct drm_info_node *) m->private;
1633 struct drm_device *dev = node->minor->dev;
1634 struct drm_i915_private *dev_priv = dev->dev_private;
1635
1636 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
1637 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
1638 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
1639
1640 return 0;
1641 }
1642
1643 static int i915_edp_psr_status(struct seq_file *m, void *data)
1644 {
1645 struct drm_info_node *node = m->private;
1646 struct drm_device *dev = node->minor->dev;
1647 struct drm_i915_private *dev_priv = dev->dev_private;
1648 u32 psrstat, psrperf;
1649
1650 if (!IS_HASWELL(dev)) {
1651 seq_puts(m, "PSR not supported on this platform\n");
1652 } else if (IS_HASWELL(dev) && I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE) {
1653 seq_puts(m, "PSR enabled\n");
1654 } else {
1655 seq_puts(m, "PSR disabled: ");
1656 switch (dev_priv->no_psr_reason) {
1657 case PSR_NO_SOURCE:
1658 seq_puts(m, "not supported on this platform");
1659 break;
1660 case PSR_NO_SINK:
1661 seq_puts(m, "not supported by panel");
1662 break;
1663 case PSR_MODULE_PARAM:
1664 seq_puts(m, "disabled by flag");
1665 break;
1666 case PSR_CRTC_NOT_ACTIVE:
1667 seq_puts(m, "crtc not active");
1668 break;
1669 case PSR_PWR_WELL_ENABLED:
1670 seq_puts(m, "power well enabled");
1671 break;
1672 case PSR_NOT_TILED:
1673 seq_puts(m, "not tiled");
1674 break;
1675 case PSR_SPRITE_ENABLED:
1676 seq_puts(m, "sprite enabled");
1677 break;
1678 case PSR_S3D_ENABLED:
1679 seq_puts(m, "stereo 3d enabled");
1680 break;
1681 case PSR_INTERLACED_ENABLED:
1682 seq_puts(m, "interlaced enabled");
1683 break;
1684 case PSR_HSW_NOT_DDIA:
1685 seq_puts(m, "HSW ties PSR to DDI A (eDP)");
1686 break;
1687 default:
1688 seq_puts(m, "unknown reason");
1689 }
1690 seq_puts(m, "\n");
1691 return 0;
1692 }
1693
1694 psrstat = I915_READ(EDP_PSR_STATUS_CTL);
1695
1696 seq_puts(m, "PSR Current State: ");
1697 switch (psrstat & EDP_PSR_STATUS_STATE_MASK) {
1698 case EDP_PSR_STATUS_STATE_IDLE:
1699 seq_puts(m, "Reset state\n");
1700 break;
1701 case EDP_PSR_STATUS_STATE_SRDONACK:
1702 seq_puts(m, "Wait for TG/Stream to send on frame of data after SRD conditions are met\n");
1703 break;
1704 case EDP_PSR_STATUS_STATE_SRDENT:
1705 seq_puts(m, "SRD entry\n");
1706 break;
1707 case EDP_PSR_STATUS_STATE_BUFOFF:
1708 seq_puts(m, "Wait for buffer turn off\n");
1709 break;
1710 case EDP_PSR_STATUS_STATE_BUFON:
1711 seq_puts(m, "Wait for buffer turn on\n");
1712 break;
1713 case EDP_PSR_STATUS_STATE_AUXACK:
1714 seq_puts(m, "Wait for AUX to acknowledge on SRD exit\n");
1715 break;
1716 case EDP_PSR_STATUS_STATE_SRDOFFACK:
1717 seq_puts(m, "Wait for TG/Stream to acknowledge the SRD VDM exit\n");
1718 break;
1719 default:
1720 seq_puts(m, "Unknown\n");
1721 break;
1722 }
1723
1724 seq_puts(m, "Link Status: ");
1725 switch (psrstat & EDP_PSR_STATUS_LINK_MASK) {
1726 case EDP_PSR_STATUS_LINK_FULL_OFF:
1727 seq_puts(m, "Link is fully off\n");
1728 break;
1729 case EDP_PSR_STATUS_LINK_FULL_ON:
1730 seq_puts(m, "Link is fully on\n");
1731 break;
1732 case EDP_PSR_STATUS_LINK_STANDBY:
1733 seq_puts(m, "Link is in standby\n");
1734 break;
1735 default:
1736 seq_puts(m, "Unknown\n");
1737 break;
1738 }
1739
1740 seq_printf(m, "PSR Entry Count: %u\n",
1741 psrstat >> EDP_PSR_STATUS_COUNT_SHIFT &
1742 EDP_PSR_STATUS_COUNT_MASK);
1743
1744 seq_printf(m, "Max Sleep Timer Counter: %u\n",
1745 psrstat >> EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT &
1746 EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK);
1747
1748 seq_printf(m, "Had AUX error: %s\n",
1749 yesno(psrstat & EDP_PSR_STATUS_AUX_ERROR));
1750
1751 seq_printf(m, "Sending AUX: %s\n",
1752 yesno(psrstat & EDP_PSR_STATUS_AUX_SENDING));
1753
1754 seq_printf(m, "Sending Idle: %s\n",
1755 yesno(psrstat & EDP_PSR_STATUS_SENDING_IDLE));
1756
1757 seq_printf(m, "Sending TP2 TP3: %s\n",
1758 yesno(psrstat & EDP_PSR_STATUS_SENDING_TP2_TP3));
1759
1760 seq_printf(m, "Sending TP1: %s\n",
1761 yesno(psrstat & EDP_PSR_STATUS_SENDING_TP1));
1762
1763 seq_printf(m, "Idle Count: %u\n",
1764 psrstat & EDP_PSR_STATUS_IDLE_MASK);
1765
1766 psrperf = (I915_READ(EDP_PSR_PERF_CNT)) & EDP_PSR_PERF_CNT_MASK;
1767 seq_printf(m, "Performance Counter: %u\n", psrperf);
1768
1769 return 0;
1770 }
1771
1772 static int
1773 i915_wedged_get(void *data, u64 *val)
1774 {
1775 struct drm_device *dev = data;
1776 drm_i915_private_t *dev_priv = dev->dev_private;
1777
1778 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
1779
1780 return 0;
1781 }
1782
1783 static int
1784 i915_wedged_set(void *data, u64 val)
1785 {
1786 struct drm_device *dev = data;
1787
1788 DRM_INFO("Manually setting wedged to %llu\n", val);
1789 i915_handle_error(dev, val);
1790
1791 return 0;
1792 }
1793
1794 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
1795 i915_wedged_get, i915_wedged_set,
1796 "%llu\n");
1797
1798 static int
1799 i915_ring_stop_get(void *data, u64 *val)
1800 {
1801 struct drm_device *dev = data;
1802 drm_i915_private_t *dev_priv = dev->dev_private;
1803
1804 *val = dev_priv->gpu_error.stop_rings;
1805
1806 return 0;
1807 }
1808
1809 static int
1810 i915_ring_stop_set(void *data, u64 val)
1811 {
1812 struct drm_device *dev = data;
1813 struct drm_i915_private *dev_priv = dev->dev_private;
1814 int ret;
1815
1816 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
1817
1818 ret = mutex_lock_interruptible(&dev->struct_mutex);
1819 if (ret)
1820 return ret;
1821
1822 dev_priv->gpu_error.stop_rings = val;
1823 mutex_unlock(&dev->struct_mutex);
1824
1825 return 0;
1826 }
1827
1828 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
1829 i915_ring_stop_get, i915_ring_stop_set,
1830 "0x%08llx\n");
1831
1832 #define DROP_UNBOUND 0x1
1833 #define DROP_BOUND 0x2
1834 #define DROP_RETIRE 0x4
1835 #define DROP_ACTIVE 0x8
1836 #define DROP_ALL (DROP_UNBOUND | \
1837 DROP_BOUND | \
1838 DROP_RETIRE | \
1839 DROP_ACTIVE)
1840 static int
1841 i915_drop_caches_get(void *data, u64 *val)
1842 {
1843 *val = DROP_ALL;
1844
1845 return 0;
1846 }
1847
1848 static int
1849 i915_drop_caches_set(void *data, u64 val)
1850 {
1851 struct drm_device *dev = data;
1852 struct drm_i915_private *dev_priv = dev->dev_private;
1853 struct drm_i915_gem_object *obj, *next;
1854 struct i915_address_space *vm;
1855 struct i915_vma *vma, *x;
1856 int ret;
1857
1858 DRM_DEBUG_DRIVER("Dropping caches: 0x%08llx\n", val);
1859
1860 /* No need to check and wait for gpu resets, only libdrm auto-restarts
1861 * on ioctls on -EAGAIN. */
1862 ret = mutex_lock_interruptible(&dev->struct_mutex);
1863 if (ret)
1864 return ret;
1865
1866 if (val & DROP_ACTIVE) {
1867 ret = i915_gpu_idle(dev);
1868 if (ret)
1869 goto unlock;
1870 }
1871
1872 if (val & (DROP_RETIRE | DROP_ACTIVE))
1873 i915_gem_retire_requests(dev);
1874
1875 if (val & DROP_BOUND) {
1876 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
1877 list_for_each_entry_safe(vma, x, &vm->inactive_list,
1878 mm_list) {
1879 if (vma->obj->pin_count)
1880 continue;
1881
1882 ret = i915_vma_unbind(vma);
1883 if (ret)
1884 goto unlock;
1885 }
1886 }
1887 }
1888
1889 if (val & DROP_UNBOUND) {
1890 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
1891 global_list)
1892 if (obj->pages_pin_count == 0) {
1893 ret = i915_gem_object_put_pages(obj);
1894 if (ret)
1895 goto unlock;
1896 }
1897 }
1898
1899 unlock:
1900 mutex_unlock(&dev->struct_mutex);
1901
1902 return ret;
1903 }
1904
1905 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
1906 i915_drop_caches_get, i915_drop_caches_set,
1907 "0x%08llx\n");
1908
1909 static int
1910 i915_max_freq_get(void *data, u64 *val)
1911 {
1912 struct drm_device *dev = data;
1913 drm_i915_private_t *dev_priv = dev->dev_private;
1914 int ret;
1915
1916 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1917 return -ENODEV;
1918
1919 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1920 if (ret)
1921 return ret;
1922
1923 if (IS_VALLEYVIEW(dev))
1924 *val = vlv_gpu_freq(dev_priv->mem_freq,
1925 dev_priv->rps.max_delay);
1926 else
1927 *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
1928 mutex_unlock(&dev_priv->rps.hw_lock);
1929
1930 return 0;
1931 }
1932
1933 static int
1934 i915_max_freq_set(void *data, u64 val)
1935 {
1936 struct drm_device *dev = data;
1937 struct drm_i915_private *dev_priv = dev->dev_private;
1938 int ret;
1939
1940 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1941 return -ENODEV;
1942
1943 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
1944
1945 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1946 if (ret)
1947 return ret;
1948
1949 /*
1950 * Turbo will still be enabled, but won't go above the set value.
1951 */
1952 if (IS_VALLEYVIEW(dev)) {
1953 val = vlv_freq_opcode(dev_priv->mem_freq, val);
1954 dev_priv->rps.max_delay = val;
1955 gen6_set_rps(dev, val);
1956 } else {
1957 do_div(val, GT_FREQUENCY_MULTIPLIER);
1958 dev_priv->rps.max_delay = val;
1959 gen6_set_rps(dev, val);
1960 }
1961
1962 mutex_unlock(&dev_priv->rps.hw_lock);
1963
1964 return 0;
1965 }
1966
1967 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
1968 i915_max_freq_get, i915_max_freq_set,
1969 "%llu\n");
1970
1971 static int
1972 i915_min_freq_get(void *data, u64 *val)
1973 {
1974 struct drm_device *dev = data;
1975 drm_i915_private_t *dev_priv = dev->dev_private;
1976 int ret;
1977
1978 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1979 return -ENODEV;
1980
1981 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1982 if (ret)
1983 return ret;
1984
1985 if (IS_VALLEYVIEW(dev))
1986 *val = vlv_gpu_freq(dev_priv->mem_freq,
1987 dev_priv->rps.min_delay);
1988 else
1989 *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
1990 mutex_unlock(&dev_priv->rps.hw_lock);
1991
1992 return 0;
1993 }
1994
1995 static int
1996 i915_min_freq_set(void *data, u64 val)
1997 {
1998 struct drm_device *dev = data;
1999 struct drm_i915_private *dev_priv = dev->dev_private;
2000 int ret;
2001
2002 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2003 return -ENODEV;
2004
2005 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
2006
2007 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2008 if (ret)
2009 return ret;
2010
2011 /*
2012 * Turbo will still be enabled, but won't go below the set value.
2013 */
2014 if (IS_VALLEYVIEW(dev)) {
2015 val = vlv_freq_opcode(dev_priv->mem_freq, val);
2016 dev_priv->rps.min_delay = val;
2017 valleyview_set_rps(dev, val);
2018 } else {
2019 do_div(val, GT_FREQUENCY_MULTIPLIER);
2020 dev_priv->rps.min_delay = val;
2021 gen6_set_rps(dev, val);
2022 }
2023 mutex_unlock(&dev_priv->rps.hw_lock);
2024
2025 return 0;
2026 }
2027
2028 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
2029 i915_min_freq_get, i915_min_freq_set,
2030 "%llu\n");
2031
2032 static int
2033 i915_cache_sharing_get(void *data, u64 *val)
2034 {
2035 struct drm_device *dev = data;
2036 drm_i915_private_t *dev_priv = dev->dev_private;
2037 u32 snpcr;
2038 int ret;
2039
2040 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2041 return -ENODEV;
2042
2043 ret = mutex_lock_interruptible(&dev->struct_mutex);
2044 if (ret)
2045 return ret;
2046
2047 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
2048 mutex_unlock(&dev_priv->dev->struct_mutex);
2049
2050 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
2051
2052 return 0;
2053 }
2054
2055 static int
2056 i915_cache_sharing_set(void *data, u64 val)
2057 {
2058 struct drm_device *dev = data;
2059 struct drm_i915_private *dev_priv = dev->dev_private;
2060 u32 snpcr;
2061
2062 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2063 return -ENODEV;
2064
2065 if (val > 3)
2066 return -EINVAL;
2067
2068 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
2069
2070 /* Update the cache sharing policy here as well */
2071 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
2072 snpcr &= ~GEN6_MBC_SNPCR_MASK;
2073 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
2074 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
2075
2076 return 0;
2077 }
2078
2079 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
2080 i915_cache_sharing_get, i915_cache_sharing_set,
2081 "%llu\n");
2082
2083 /* As the drm_debugfs_init() routines are called before dev->dev_private is
2084 * allocated we need to hook into the minor for release. */
2085 static int
2086 drm_add_fake_info_node(struct drm_minor *minor,
2087 struct dentry *ent,
2088 const void *key)
2089 {
2090 struct drm_info_node *node;
2091
2092 node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL);
2093 if (node == NULL) {
2094 debugfs_remove(ent);
2095 return -ENOMEM;
2096 }
2097
2098 node->minor = minor;
2099 node->dent = ent;
2100 node->info_ent = (void *) key;
2101
2102 mutex_lock(&minor->debugfs_lock);
2103 list_add(&node->list, &minor->debugfs_list);
2104 mutex_unlock(&minor->debugfs_lock);
2105
2106 return 0;
2107 }
2108
2109 static int i915_forcewake_open(struct inode *inode, struct file *file)
2110 {
2111 struct drm_device *dev = inode->i_private;
2112 struct drm_i915_private *dev_priv = dev->dev_private;
2113
2114 if (INTEL_INFO(dev)->gen < 6)
2115 return 0;
2116
2117 gen6_gt_force_wake_get(dev_priv);
2118
2119 return 0;
2120 }
2121
2122 static int i915_forcewake_release(struct inode *inode, struct file *file)
2123 {
2124 struct drm_device *dev = inode->i_private;
2125 struct drm_i915_private *dev_priv = dev->dev_private;
2126
2127 if (INTEL_INFO(dev)->gen < 6)
2128 return 0;
2129
2130 gen6_gt_force_wake_put(dev_priv);
2131
2132 return 0;
2133 }
2134
2135 static const struct file_operations i915_forcewake_fops = {
2136 .owner = THIS_MODULE,
2137 .open = i915_forcewake_open,
2138 .release = i915_forcewake_release,
2139 };
2140
2141 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
2142 {
2143 struct drm_device *dev = minor->dev;
2144 struct dentry *ent;
2145
2146 ent = debugfs_create_file("i915_forcewake_user",
2147 S_IRUSR,
2148 root, dev,
2149 &i915_forcewake_fops);
2150 if (IS_ERR(ent))
2151 return PTR_ERR(ent);
2152
2153 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
2154 }
2155
2156 static int i915_debugfs_create(struct dentry *root,
2157 struct drm_minor *minor,
2158 const char *name,
2159 const struct file_operations *fops)
2160 {
2161 struct drm_device *dev = minor->dev;
2162 struct dentry *ent;
2163
2164 ent = debugfs_create_file(name,
2165 S_IRUGO | S_IWUSR,
2166 root, dev,
2167 fops);
2168 if (IS_ERR(ent))
2169 return PTR_ERR(ent);
2170
2171 return drm_add_fake_info_node(minor, ent, fops);
2172 }
2173
2174 static struct drm_info_list i915_debugfs_list[] = {
2175 {"i915_capabilities", i915_capabilities, 0},
2176 {"i915_gem_objects", i915_gem_object_info, 0},
2177 {"i915_gem_gtt", i915_gem_gtt_info, 0},
2178 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
2179 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
2180 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
2181 {"i915_gem_stolen", i915_gem_stolen_list_info },
2182 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2183 {"i915_gem_request", i915_gem_request_info, 0},
2184 {"i915_gem_seqno", i915_gem_seqno_info, 0},
2185 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2186 {"i915_gem_interrupt", i915_interrupt_info, 0},
2187 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
2188 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
2189 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
2190 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
2191 {"i915_rstdby_delays", i915_rstdby_delays, 0},
2192 {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
2193 {"i915_delayfreq_table", i915_delayfreq_table, 0},
2194 {"i915_inttoext_table", i915_inttoext_table, 0},
2195 {"i915_drpc_info", i915_drpc_info, 0},
2196 {"i915_emon_status", i915_emon_status, 0},
2197 {"i915_ring_freq_table", i915_ring_freq_table, 0},
2198 {"i915_gfxec", i915_gfxec, 0},
2199 {"i915_fbc_status", i915_fbc_status, 0},
2200 {"i915_ips_status", i915_ips_status, 0},
2201 {"i915_sr_status", i915_sr_status, 0},
2202 {"i915_opregion", i915_opregion, 0},
2203 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
2204 {"i915_context_status", i915_context_status, 0},
2205 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
2206 {"i915_swizzle_info", i915_swizzle_info, 0},
2207 {"i915_ppgtt_info", i915_ppgtt_info, 0},
2208 {"i915_dpio", i915_dpio_info, 0},
2209 {"i915_llc", i915_llc, 0},
2210 {"i915_edp_psr_status", i915_edp_psr_status, 0},
2211 };
2212 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2213
2214 static struct i915_debugfs_files {
2215 const char *name;
2216 const struct file_operations *fops;
2217 } i915_debugfs_files[] = {
2218 {"i915_wedged", &i915_wedged_fops},
2219 {"i915_max_freq", &i915_max_freq_fops},
2220 {"i915_min_freq", &i915_min_freq_fops},
2221 {"i915_cache_sharing", &i915_cache_sharing_fops},
2222 {"i915_ring_stop", &i915_ring_stop_fops},
2223 {"i915_gem_drop_caches", &i915_drop_caches_fops},
2224 {"i915_error_state", &i915_error_state_fops},
2225 {"i915_next_seqno", &i915_next_seqno_fops},
2226 };
2227
2228 int i915_debugfs_init(struct drm_minor *minor)
2229 {
2230 int ret, i;
2231
2232 ret = i915_forcewake_create(minor->debugfs_root, minor);
2233 if (ret)
2234 return ret;
2235
2236 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
2237 ret = i915_debugfs_create(minor->debugfs_root, minor,
2238 i915_debugfs_files[i].name,
2239 i915_debugfs_files[i].fops);
2240 if (ret)
2241 return ret;
2242 }
2243
2244 return drm_debugfs_create_files(i915_debugfs_list,
2245 I915_DEBUGFS_ENTRIES,
2246 minor->debugfs_root, minor);
2247 }
2248
2249 void i915_debugfs_cleanup(struct drm_minor *minor)
2250 {
2251 int i;
2252
2253 drm_debugfs_remove_files(i915_debugfs_list,
2254 I915_DEBUGFS_ENTRIES, minor);
2255 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
2256 1, minor);
2257 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
2258 struct drm_info_list *info_list =
2259 (struct drm_info_list *) i915_debugfs_files[i].fops;
2260
2261 drm_debugfs_remove_files(info_list, 1, minor);
2262 }
2263 }
2264
2265 #endif /* CONFIG_DEBUG_FS */
Linux kernel - Deliverables
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