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drm/i915: add gen6+ registers to i915_swizzle_info
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29 #include <linux/seq_file.h>
30 #include <linux/debugfs.h>
31 #include <linux/slab.h>
32 #include <linux/export.h>
33 #include "drmP.h"
34 #include "drm.h"
35 #include "intel_drv.h"
36 #include "intel_ringbuffer.h"
37 #include "i915_drm.h"
38 #include "i915_drv.h"
39
40 #define DRM_I915_RING_DEBUG 1
41
42
43 #if defined(CONFIG_DEBUG_FS)
44
45 enum {
46 ACTIVE_LIST,
47 FLUSHING_LIST,
48 INACTIVE_LIST,
49 PINNED_LIST,
50 DEFERRED_FREE_LIST,
51 };
52
53 static const char *yesno(int v)
54 {
55 return v ? "yes" : "no";
56 }
57
58 static int i915_capabilities(struct seq_file *m, void *data)
59 {
60 struct drm_info_node *node = (struct drm_info_node *) m->private;
61 struct drm_device *dev = node->minor->dev;
62 const struct intel_device_info *info = INTEL_INFO(dev);
63
64 seq_printf(m, "gen: %d\n", info->gen);
65 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
66 #define B(x) seq_printf(m, #x ": %s\n", yesno(info->x))
67 B(is_mobile);
68 B(is_i85x);
69 B(is_i915g);
70 B(is_i945gm);
71 B(is_g33);
72 B(need_gfx_hws);
73 B(is_g4x);
74 B(is_pineview);
75 B(is_broadwater);
76 B(is_crestline);
77 B(has_fbc);
78 B(has_pipe_cxsr);
79 B(has_hotplug);
80 B(cursor_needs_physical);
81 B(has_overlay);
82 B(overlay_needs_physical);
83 B(supports_tv);
84 B(has_bsd_ring);
85 B(has_blt_ring);
86 B(has_llc);
87 #undef B
88
89 return 0;
90 }
91
92 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
93 {
94 if (obj->user_pin_count > 0)
95 return "P";
96 else if (obj->pin_count > 0)
97 return "p";
98 else
99 return " ";
100 }
101
102 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
103 {
104 switch (obj->tiling_mode) {
105 default:
106 case I915_TILING_NONE: return " ";
107 case I915_TILING_X: return "X";
108 case I915_TILING_Y: return "Y";
109 }
110 }
111
112 static const char *cache_level_str(int type)
113 {
114 switch (type) {
115 case I915_CACHE_NONE: return " uncached";
116 case I915_CACHE_LLC: return " snooped (LLC)";
117 case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)";
118 default: return "";
119 }
120 }
121
122 static void
123 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
124 {
125 seq_printf(m, "%p: %s%s %8zd %04x %04x %d %d%s%s%s",
126 &obj->base,
127 get_pin_flag(obj),
128 get_tiling_flag(obj),
129 obj->base.size,
130 obj->base.read_domains,
131 obj->base.write_domain,
132 obj->last_rendering_seqno,
133 obj->last_fenced_seqno,
134 cache_level_str(obj->cache_level),
135 obj->dirty ? " dirty" : "",
136 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
137 if (obj->base.name)
138 seq_printf(m, " (name: %d)", obj->base.name);
139 if (obj->fence_reg != I915_FENCE_REG_NONE)
140 seq_printf(m, " (fence: %d)", obj->fence_reg);
141 if (obj->gtt_space != NULL)
142 seq_printf(m, " (gtt offset: %08x, size: %08x)",
143 obj->gtt_offset, (unsigned int)obj->gtt_space->size);
144 if (obj->pin_mappable || obj->fault_mappable) {
145 char s[3], *t = s;
146 if (obj->pin_mappable)
147 *t++ = 'p';
148 if (obj->fault_mappable)
149 *t++ = 'f';
150 *t = '\0';
151 seq_printf(m, " (%s mappable)", s);
152 }
153 if (obj->ring != NULL)
154 seq_printf(m, " (%s)", obj->ring->name);
155 }
156
157 static int i915_gem_object_list_info(struct seq_file *m, void *data)
158 {
159 struct drm_info_node *node = (struct drm_info_node *) m->private;
160 uintptr_t list = (uintptr_t) node->info_ent->data;
161 struct list_head *head;
162 struct drm_device *dev = node->minor->dev;
163 drm_i915_private_t *dev_priv = dev->dev_private;
164 struct drm_i915_gem_object *obj;
165 size_t total_obj_size, total_gtt_size;
166 int count, ret;
167
168 ret = mutex_lock_interruptible(&dev->struct_mutex);
169 if (ret)
170 return ret;
171
172 switch (list) {
173 case ACTIVE_LIST:
174 seq_printf(m, "Active:\n");
175 head = &dev_priv->mm.active_list;
176 break;
177 case INACTIVE_LIST:
178 seq_printf(m, "Inactive:\n");
179 head = &dev_priv->mm.inactive_list;
180 break;
181 case PINNED_LIST:
182 seq_printf(m, "Pinned:\n");
183 head = &dev_priv->mm.pinned_list;
184 break;
185 case FLUSHING_LIST:
186 seq_printf(m, "Flushing:\n");
187 head = &dev_priv->mm.flushing_list;
188 break;
189 case DEFERRED_FREE_LIST:
190 seq_printf(m, "Deferred free:\n");
191 head = &dev_priv->mm.deferred_free_list;
192 break;
193 default:
194 mutex_unlock(&dev->struct_mutex);
195 return -EINVAL;
196 }
197
198 total_obj_size = total_gtt_size = count = 0;
199 list_for_each_entry(obj, head, mm_list) {
200 seq_printf(m, " ");
201 describe_obj(m, obj);
202 seq_printf(m, "\n");
203 total_obj_size += obj->base.size;
204 total_gtt_size += obj->gtt_space->size;
205 count++;
206 }
207 mutex_unlock(&dev->struct_mutex);
208
209 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
210 count, total_obj_size, total_gtt_size);
211 return 0;
212 }
213
214 #define count_objects(list, member) do { \
215 list_for_each_entry(obj, list, member) { \
216 size += obj->gtt_space->size; \
217 ++count; \
218 if (obj->map_and_fenceable) { \
219 mappable_size += obj->gtt_space->size; \
220 ++mappable_count; \
221 } \
222 } \
223 } while (0)
224
225 static int i915_gem_object_info(struct seq_file *m, void* data)
226 {
227 struct drm_info_node *node = (struct drm_info_node *) m->private;
228 struct drm_device *dev = node->minor->dev;
229 struct drm_i915_private *dev_priv = dev->dev_private;
230 u32 count, mappable_count;
231 size_t size, mappable_size;
232 struct drm_i915_gem_object *obj;
233 int ret;
234
235 ret = mutex_lock_interruptible(&dev->struct_mutex);
236 if (ret)
237 return ret;
238
239 seq_printf(m, "%u objects, %zu bytes\n",
240 dev_priv->mm.object_count,
241 dev_priv->mm.object_memory);
242
243 size = count = mappable_size = mappable_count = 0;
244 count_objects(&dev_priv->mm.gtt_list, gtt_list);
245 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
246 count, mappable_count, size, mappable_size);
247
248 size = count = mappable_size = mappable_count = 0;
249 count_objects(&dev_priv->mm.active_list, mm_list);
250 count_objects(&dev_priv->mm.flushing_list, mm_list);
251 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
252 count, mappable_count, size, mappable_size);
253
254 size = count = mappable_size = mappable_count = 0;
255 count_objects(&dev_priv->mm.pinned_list, mm_list);
256 seq_printf(m, " %u [%u] pinned objects, %zu [%zu] bytes\n",
257 count, mappable_count, size, mappable_size);
258
259 size = count = mappable_size = mappable_count = 0;
260 count_objects(&dev_priv->mm.inactive_list, mm_list);
261 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
262 count, mappable_count, size, mappable_size);
263
264 size = count = mappable_size = mappable_count = 0;
265 count_objects(&dev_priv->mm.deferred_free_list, mm_list);
266 seq_printf(m, " %u [%u] freed objects, %zu [%zu] bytes\n",
267 count, mappable_count, size, mappable_size);
268
269 size = count = mappable_size = mappable_count = 0;
270 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
271 if (obj->fault_mappable) {
272 size += obj->gtt_space->size;
273 ++count;
274 }
275 if (obj->pin_mappable) {
276 mappable_size += obj->gtt_space->size;
277 ++mappable_count;
278 }
279 }
280 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
281 mappable_count, mappable_size);
282 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
283 count, size);
284
285 seq_printf(m, "%zu [%zu] gtt total\n",
286 dev_priv->mm.gtt_total, dev_priv->mm.mappable_gtt_total);
287
288 mutex_unlock(&dev->struct_mutex);
289
290 return 0;
291 }
292
293 static int i915_gem_gtt_info(struct seq_file *m, void* data)
294 {
295 struct drm_info_node *node = (struct drm_info_node *) m->private;
296 struct drm_device *dev = node->minor->dev;
297 struct drm_i915_private *dev_priv = dev->dev_private;
298 struct drm_i915_gem_object *obj;
299 size_t total_obj_size, total_gtt_size;
300 int count, ret;
301
302 ret = mutex_lock_interruptible(&dev->struct_mutex);
303 if (ret)
304 return ret;
305
306 total_obj_size = total_gtt_size = count = 0;
307 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
308 seq_printf(m, " ");
309 describe_obj(m, obj);
310 seq_printf(m, "\n");
311 total_obj_size += obj->base.size;
312 total_gtt_size += obj->gtt_space->size;
313 count++;
314 }
315
316 mutex_unlock(&dev->struct_mutex);
317
318 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
319 count, total_obj_size, total_gtt_size);
320
321 return 0;
322 }
323
324
325 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
326 {
327 struct drm_info_node *node = (struct drm_info_node *) m->private;
328 struct drm_device *dev = node->minor->dev;
329 unsigned long flags;
330 struct intel_crtc *crtc;
331
332 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
333 const char pipe = pipe_name(crtc->pipe);
334 const char plane = plane_name(crtc->plane);
335 struct intel_unpin_work *work;
336
337 spin_lock_irqsave(&dev->event_lock, flags);
338 work = crtc->unpin_work;
339 if (work == NULL) {
340 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
341 pipe, plane);
342 } else {
343 if (!work->pending) {
344 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
345 pipe, plane);
346 } else {
347 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
348 pipe, plane);
349 }
350 if (work->enable_stall_check)
351 seq_printf(m, "Stall check enabled, ");
352 else
353 seq_printf(m, "Stall check waiting for page flip ioctl, ");
354 seq_printf(m, "%d prepares\n", work->pending);
355
356 if (work->old_fb_obj) {
357 struct drm_i915_gem_object *obj = work->old_fb_obj;
358 if (obj)
359 seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
360 }
361 if (work->pending_flip_obj) {
362 struct drm_i915_gem_object *obj = work->pending_flip_obj;
363 if (obj)
364 seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
365 }
366 }
367 spin_unlock_irqrestore(&dev->event_lock, flags);
368 }
369
370 return 0;
371 }
372
373 static int i915_gem_request_info(struct seq_file *m, void *data)
374 {
375 struct drm_info_node *node = (struct drm_info_node *) m->private;
376 struct drm_device *dev = node->minor->dev;
377 drm_i915_private_t *dev_priv = dev->dev_private;
378 struct drm_i915_gem_request *gem_request;
379 int ret, count;
380
381 ret = mutex_lock_interruptible(&dev->struct_mutex);
382 if (ret)
383 return ret;
384
385 count = 0;
386 if (!list_empty(&dev_priv->ring[RCS].request_list)) {
387 seq_printf(m, "Render requests:\n");
388 list_for_each_entry(gem_request,
389 &dev_priv->ring[RCS].request_list,
390 list) {
391 seq_printf(m, " %d @ %d\n",
392 gem_request->seqno,
393 (int) (jiffies - gem_request->emitted_jiffies));
394 }
395 count++;
396 }
397 if (!list_empty(&dev_priv->ring[VCS].request_list)) {
398 seq_printf(m, "BSD requests:\n");
399 list_for_each_entry(gem_request,
400 &dev_priv->ring[VCS].request_list,
401 list) {
402 seq_printf(m, " %d @ %d\n",
403 gem_request->seqno,
404 (int) (jiffies - gem_request->emitted_jiffies));
405 }
406 count++;
407 }
408 if (!list_empty(&dev_priv->ring[BCS].request_list)) {
409 seq_printf(m, "BLT requests:\n");
410 list_for_each_entry(gem_request,
411 &dev_priv->ring[BCS].request_list,
412 list) {
413 seq_printf(m, " %d @ %d\n",
414 gem_request->seqno,
415 (int) (jiffies - gem_request->emitted_jiffies));
416 }
417 count++;
418 }
419 mutex_unlock(&dev->struct_mutex);
420
421 if (count == 0)
422 seq_printf(m, "No requests\n");
423
424 return 0;
425 }
426
427 static void i915_ring_seqno_info(struct seq_file *m,
428 struct intel_ring_buffer *ring)
429 {
430 if (ring->get_seqno) {
431 seq_printf(m, "Current sequence (%s): %d\n",
432 ring->name, ring->get_seqno(ring));
433 seq_printf(m, "Waiter sequence (%s): %d\n",
434 ring->name, ring->waiting_seqno);
435 seq_printf(m, "IRQ sequence (%s): %d\n",
436 ring->name, ring->irq_seqno);
437 }
438 }
439
440 static int i915_gem_seqno_info(struct seq_file *m, void *data)
441 {
442 struct drm_info_node *node = (struct drm_info_node *) m->private;
443 struct drm_device *dev = node->minor->dev;
444 drm_i915_private_t *dev_priv = dev->dev_private;
445 int ret, i;
446
447 ret = mutex_lock_interruptible(&dev->struct_mutex);
448 if (ret)
449 return ret;
450
451 for (i = 0; i < I915_NUM_RINGS; i++)
452 i915_ring_seqno_info(m, &dev_priv->ring[i]);
453
454 mutex_unlock(&dev->struct_mutex);
455
456 return 0;
457 }
458
459
460 static int i915_interrupt_info(struct seq_file *m, void *data)
461 {
462 struct drm_info_node *node = (struct drm_info_node *) m->private;
463 struct drm_device *dev = node->minor->dev;
464 drm_i915_private_t *dev_priv = dev->dev_private;
465 int ret, i, pipe;
466
467 ret = mutex_lock_interruptible(&dev->struct_mutex);
468 if (ret)
469 return ret;
470
471 if (!HAS_PCH_SPLIT(dev)) {
472 seq_printf(m, "Interrupt enable: %08x\n",
473 I915_READ(IER));
474 seq_printf(m, "Interrupt identity: %08x\n",
475 I915_READ(IIR));
476 seq_printf(m, "Interrupt mask: %08x\n",
477 I915_READ(IMR));
478 for_each_pipe(pipe)
479 seq_printf(m, "Pipe %c stat: %08x\n",
480 pipe_name(pipe),
481 I915_READ(PIPESTAT(pipe)));
482 } else {
483 seq_printf(m, "North Display Interrupt enable: %08x\n",
484 I915_READ(DEIER));
485 seq_printf(m, "North Display Interrupt identity: %08x\n",
486 I915_READ(DEIIR));
487 seq_printf(m, "North Display Interrupt mask: %08x\n",
488 I915_READ(DEIMR));
489 seq_printf(m, "South Display Interrupt enable: %08x\n",
490 I915_READ(SDEIER));
491 seq_printf(m, "South Display Interrupt identity: %08x\n",
492 I915_READ(SDEIIR));
493 seq_printf(m, "South Display Interrupt mask: %08x\n",
494 I915_READ(SDEIMR));
495 seq_printf(m, "Graphics Interrupt enable: %08x\n",
496 I915_READ(GTIER));
497 seq_printf(m, "Graphics Interrupt identity: %08x\n",
498 I915_READ(GTIIR));
499 seq_printf(m, "Graphics Interrupt mask: %08x\n",
500 I915_READ(GTIMR));
501 }
502 seq_printf(m, "Interrupts received: %d\n",
503 atomic_read(&dev_priv->irq_received));
504 for (i = 0; i < I915_NUM_RINGS; i++) {
505 if (IS_GEN6(dev) || IS_GEN7(dev)) {
506 seq_printf(m, "Graphics Interrupt mask (%s): %08x\n",
507 dev_priv->ring[i].name,
508 I915_READ_IMR(&dev_priv->ring[i]));
509 }
510 i915_ring_seqno_info(m, &dev_priv->ring[i]);
511 }
512 mutex_unlock(&dev->struct_mutex);
513
514 return 0;
515 }
516
517 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
518 {
519 struct drm_info_node *node = (struct drm_info_node *) m->private;
520 struct drm_device *dev = node->minor->dev;
521 drm_i915_private_t *dev_priv = dev->dev_private;
522 int i, ret;
523
524 ret = mutex_lock_interruptible(&dev->struct_mutex);
525 if (ret)
526 return ret;
527
528 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
529 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
530 for (i = 0; i < dev_priv->num_fence_regs; i++) {
531 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
532
533 seq_printf(m, "Fenced object[%2d] = ", i);
534 if (obj == NULL)
535 seq_printf(m, "unused");
536 else
537 describe_obj(m, obj);
538 seq_printf(m, "\n");
539 }
540
541 mutex_unlock(&dev->struct_mutex);
542 return 0;
543 }
544
545 static int i915_hws_info(struct seq_file *m, void *data)
546 {
547 struct drm_info_node *node = (struct drm_info_node *) m->private;
548 struct drm_device *dev = node->minor->dev;
549 drm_i915_private_t *dev_priv = dev->dev_private;
550 struct intel_ring_buffer *ring;
551 const volatile u32 __iomem *hws;
552 int i;
553
554 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
555 hws = (volatile u32 __iomem *)ring->status_page.page_addr;
556 if (hws == NULL)
557 return 0;
558
559 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
560 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
561 i * 4,
562 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
563 }
564 return 0;
565 }
566
567 static int i915_ringbuffer_data(struct seq_file *m, void *data)
568 {
569 struct drm_info_node *node = (struct drm_info_node *) m->private;
570 struct drm_device *dev = node->minor->dev;
571 drm_i915_private_t *dev_priv = dev->dev_private;
572 struct intel_ring_buffer *ring;
573 int ret;
574
575 ret = mutex_lock_interruptible(&dev->struct_mutex);
576 if (ret)
577 return ret;
578
579 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
580 if (!ring->obj) {
581 seq_printf(m, "No ringbuffer setup\n");
582 } else {
583 const u8 __iomem *virt = ring->virtual_start;
584 uint32_t off;
585
586 for (off = 0; off < ring->size; off += 4) {
587 uint32_t *ptr = (uint32_t *)(virt + off);
588 seq_printf(m, "%08x : %08x\n", off, *ptr);
589 }
590 }
591 mutex_unlock(&dev->struct_mutex);
592
593 return 0;
594 }
595
596 static int i915_ringbuffer_info(struct seq_file *m, void *data)
597 {
598 struct drm_info_node *node = (struct drm_info_node *) m->private;
599 struct drm_device *dev = node->minor->dev;
600 drm_i915_private_t *dev_priv = dev->dev_private;
601 struct intel_ring_buffer *ring;
602 int ret;
603
604 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
605 if (ring->size == 0)
606 return 0;
607
608 ret = mutex_lock_interruptible(&dev->struct_mutex);
609 if (ret)
610 return ret;
611
612 seq_printf(m, "Ring %s:\n", ring->name);
613 seq_printf(m, " Head : %08x\n", I915_READ_HEAD(ring) & HEAD_ADDR);
614 seq_printf(m, " Tail : %08x\n", I915_READ_TAIL(ring) & TAIL_ADDR);
615 seq_printf(m, " Size : %08x\n", ring->size);
616 seq_printf(m, " Active : %08x\n", intel_ring_get_active_head(ring));
617 seq_printf(m, " NOPID : %08x\n", I915_READ_NOPID(ring));
618 if (IS_GEN6(dev)) {
619 seq_printf(m, " Sync 0 : %08x\n", I915_READ_SYNC_0(ring));
620 seq_printf(m, " Sync 1 : %08x\n", I915_READ_SYNC_1(ring));
621 }
622 seq_printf(m, " Control : %08x\n", I915_READ_CTL(ring));
623 seq_printf(m, " Start : %08x\n", I915_READ_START(ring));
624
625 mutex_unlock(&dev->struct_mutex);
626
627 return 0;
628 }
629
630 static const char *ring_str(int ring)
631 {
632 switch (ring) {
633 case RCS: return "render";
634 case VCS: return "bsd";
635 case BCS: return "blt";
636 default: return "";
637 }
638 }
639
640 static const char *pin_flag(int pinned)
641 {
642 if (pinned > 0)
643 return " P";
644 else if (pinned < 0)
645 return " p";
646 else
647 return "";
648 }
649
650 static const char *tiling_flag(int tiling)
651 {
652 switch (tiling) {
653 default:
654 case I915_TILING_NONE: return "";
655 case I915_TILING_X: return " X";
656 case I915_TILING_Y: return " Y";
657 }
658 }
659
660 static const char *dirty_flag(int dirty)
661 {
662 return dirty ? " dirty" : "";
663 }
664
665 static const char *purgeable_flag(int purgeable)
666 {
667 return purgeable ? " purgeable" : "";
668 }
669
670 static void print_error_buffers(struct seq_file *m,
671 const char *name,
672 struct drm_i915_error_buffer *err,
673 int count)
674 {
675 seq_printf(m, "%s [%d]:\n", name, count);
676
677 while (count--) {
678 seq_printf(m, " %08x %8u %04x %04x %08x%s%s%s%s%s%s%s",
679 err->gtt_offset,
680 err->size,
681 err->read_domains,
682 err->write_domain,
683 err->seqno,
684 pin_flag(err->pinned),
685 tiling_flag(err->tiling),
686 dirty_flag(err->dirty),
687 purgeable_flag(err->purgeable),
688 err->ring != -1 ? " " : "",
689 ring_str(err->ring),
690 cache_level_str(err->cache_level));
691
692 if (err->name)
693 seq_printf(m, " (name: %d)", err->name);
694 if (err->fence_reg != I915_FENCE_REG_NONE)
695 seq_printf(m, " (fence: %d)", err->fence_reg);
696
697 seq_printf(m, "\n");
698 err++;
699 }
700 }
701
702 static void i915_ring_error_state(struct seq_file *m,
703 struct drm_device *dev,
704 struct drm_i915_error_state *error,
705 unsigned ring)
706 {
707 seq_printf(m, "%s command stream:\n", ring_str(ring));
708 seq_printf(m, " HEAD: 0x%08x\n", error->head[ring]);
709 seq_printf(m, " TAIL: 0x%08x\n", error->tail[ring]);
710 seq_printf(m, " ACTHD: 0x%08x\n", error->acthd[ring]);
711 seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]);
712 seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]);
713 seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone[ring]);
714 if (ring == RCS && INTEL_INFO(dev)->gen >= 4) {
715 seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1);
716 seq_printf(m, " BBADDR: 0x%08llx\n", error->bbaddr);
717 }
718 if (INTEL_INFO(dev)->gen >= 4)
719 seq_printf(m, " INSTPS: 0x%08x\n", error->instps[ring]);
720 seq_printf(m, " INSTPM: 0x%08x\n", error->instpm[ring]);
721 if (INTEL_INFO(dev)->gen >= 6) {
722 seq_printf(m, " FADDR: 0x%08x\n", error->faddr[ring]);
723 seq_printf(m, " FAULT_REG: 0x%08x\n", error->fault_reg[ring]);
724 }
725 seq_printf(m, " seqno: 0x%08x\n", error->seqno[ring]);
726 }
727
728 static int i915_error_state(struct seq_file *m, void *unused)
729 {
730 struct drm_info_node *node = (struct drm_info_node *) m->private;
731 struct drm_device *dev = node->minor->dev;
732 drm_i915_private_t *dev_priv = dev->dev_private;
733 struct drm_i915_error_state *error;
734 unsigned long flags;
735 int i, page, offset, elt;
736
737 spin_lock_irqsave(&dev_priv->error_lock, flags);
738 if (!dev_priv->first_error) {
739 seq_printf(m, "no error state collected\n");
740 goto out;
741 }
742
743 error = dev_priv->first_error;
744
745 seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
746 error->time.tv_usec);
747 seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
748 seq_printf(m, "EIR: 0x%08x\n", error->eir);
749 seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
750
751 for (i = 0; i < dev_priv->num_fence_regs; i++)
752 seq_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
753
754 if (INTEL_INFO(dev)->gen >= 6) {
755 seq_printf(m, "ERROR: 0x%08x\n", error->error);
756 seq_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
757 }
758
759 i915_ring_error_state(m, dev, error, RCS);
760 if (HAS_BLT(dev))
761 i915_ring_error_state(m, dev, error, BCS);
762 if (HAS_BSD(dev))
763 i915_ring_error_state(m, dev, error, VCS);
764
765 if (error->active_bo)
766 print_error_buffers(m, "Active",
767 error->active_bo,
768 error->active_bo_count);
769
770 if (error->pinned_bo)
771 print_error_buffers(m, "Pinned",
772 error->pinned_bo,
773 error->pinned_bo_count);
774
775 for (i = 0; i < ARRAY_SIZE(error->batchbuffer); i++) {
776 if (error->batchbuffer[i]) {
777 struct drm_i915_error_object *obj = error->batchbuffer[i];
778
779 seq_printf(m, "%s --- gtt_offset = 0x%08x\n",
780 dev_priv->ring[i].name,
781 obj->gtt_offset);
782 offset = 0;
783 for (page = 0; page < obj->page_count; page++) {
784 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
785 seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]);
786 offset += 4;
787 }
788 }
789 }
790 }
791
792 for (i = 0; i < ARRAY_SIZE(error->ringbuffer); i++) {
793 if (error->ringbuffer[i]) {
794 struct drm_i915_error_object *obj = error->ringbuffer[i];
795 seq_printf(m, "%s --- ringbuffer = 0x%08x\n",
796 dev_priv->ring[i].name,
797 obj->gtt_offset);
798 offset = 0;
799 for (page = 0; page < obj->page_count; page++) {
800 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
801 seq_printf(m, "%08x : %08x\n",
802 offset,
803 obj->pages[page][elt]);
804 offset += 4;
805 }
806 }
807 }
808 }
809
810 if (error->overlay)
811 intel_overlay_print_error_state(m, error->overlay);
812
813 if (error->display)
814 intel_display_print_error_state(m, dev, error->display);
815
816 out:
817 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
818
819 return 0;
820 }
821
822 static int i915_rstdby_delays(struct seq_file *m, void *unused)
823 {
824 struct drm_info_node *node = (struct drm_info_node *) m->private;
825 struct drm_device *dev = node->minor->dev;
826 drm_i915_private_t *dev_priv = dev->dev_private;
827 u16 crstanddelay;
828 int ret;
829
830 ret = mutex_lock_interruptible(&dev->struct_mutex);
831 if (ret)
832 return ret;
833
834 crstanddelay = I915_READ16(CRSTANDVID);
835
836 mutex_unlock(&dev->struct_mutex);
837
838 seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
839
840 return 0;
841 }
842
843 static int i915_cur_delayinfo(struct seq_file *m, void *unused)
844 {
845 struct drm_info_node *node = (struct drm_info_node *) m->private;
846 struct drm_device *dev = node->minor->dev;
847 drm_i915_private_t *dev_priv = dev->dev_private;
848 int ret;
849
850 if (IS_GEN5(dev)) {
851 u16 rgvswctl = I915_READ16(MEMSWCTL);
852 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
853
854 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
855 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
856 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
857 MEMSTAT_VID_SHIFT);
858 seq_printf(m, "Current P-state: %d\n",
859 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
860 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
861 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
862 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
863 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
864 u32 rpstat;
865 u32 rpupei, rpcurup, rpprevup;
866 u32 rpdownei, rpcurdown, rpprevdown;
867 int max_freq;
868
869 /* RPSTAT1 is in the GT power well */
870 ret = mutex_lock_interruptible(&dev->struct_mutex);
871 if (ret)
872 return ret;
873
874 gen6_gt_force_wake_get(dev_priv);
875
876 rpstat = I915_READ(GEN6_RPSTAT1);
877 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
878 rpcurup = I915_READ(GEN6_RP_CUR_UP);
879 rpprevup = I915_READ(GEN6_RP_PREV_UP);
880 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
881 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
882 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
883
884 gen6_gt_force_wake_put(dev_priv);
885 mutex_unlock(&dev->struct_mutex);
886
887 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
888 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
889 seq_printf(m, "Render p-state ratio: %d\n",
890 (gt_perf_status & 0xff00) >> 8);
891 seq_printf(m, "Render p-state VID: %d\n",
892 gt_perf_status & 0xff);
893 seq_printf(m, "Render p-state limit: %d\n",
894 rp_state_limits & 0xff);
895 seq_printf(m, "CAGF: %dMHz\n", ((rpstat & GEN6_CAGF_MASK) >>
896 GEN6_CAGF_SHIFT) * 50);
897 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
898 GEN6_CURICONT_MASK);
899 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
900 GEN6_CURBSYTAVG_MASK);
901 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
902 GEN6_CURBSYTAVG_MASK);
903 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
904 GEN6_CURIAVG_MASK);
905 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
906 GEN6_CURBSYTAVG_MASK);
907 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
908 GEN6_CURBSYTAVG_MASK);
909
910 max_freq = (rp_state_cap & 0xff0000) >> 16;
911 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
912 max_freq * 50);
913
914 max_freq = (rp_state_cap & 0xff00) >> 8;
915 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
916 max_freq * 50);
917
918 max_freq = rp_state_cap & 0xff;
919 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
920 max_freq * 50);
921 } else {
922 seq_printf(m, "no P-state info available\n");
923 }
924
925 return 0;
926 }
927
928 static int i915_delayfreq_table(struct seq_file *m, void *unused)
929 {
930 struct drm_info_node *node = (struct drm_info_node *) m->private;
931 struct drm_device *dev = node->minor->dev;
932 drm_i915_private_t *dev_priv = dev->dev_private;
933 u32 delayfreq;
934 int ret, i;
935
936 ret = mutex_lock_interruptible(&dev->struct_mutex);
937 if (ret)
938 return ret;
939
940 for (i = 0; i < 16; i++) {
941 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
942 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
943 (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
944 }
945
946 mutex_unlock(&dev->struct_mutex);
947
948 return 0;
949 }
950
951 static inline int MAP_TO_MV(int map)
952 {
953 return 1250 - (map * 25);
954 }
955
956 static int i915_inttoext_table(struct seq_file *m, void *unused)
957 {
958 struct drm_info_node *node = (struct drm_info_node *) m->private;
959 struct drm_device *dev = node->minor->dev;
960 drm_i915_private_t *dev_priv = dev->dev_private;
961 u32 inttoext;
962 int ret, i;
963
964 ret = mutex_lock_interruptible(&dev->struct_mutex);
965 if (ret)
966 return ret;
967
968 for (i = 1; i <= 32; i++) {
969 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
970 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
971 }
972
973 mutex_unlock(&dev->struct_mutex);
974
975 return 0;
976 }
977
978 static int ironlake_drpc_info(struct seq_file *m)
979 {
980 struct drm_info_node *node = (struct drm_info_node *) m->private;
981 struct drm_device *dev = node->minor->dev;
982 drm_i915_private_t *dev_priv = dev->dev_private;
983 u32 rgvmodectl, rstdbyctl;
984 u16 crstandvid;
985 int ret;
986
987 ret = mutex_lock_interruptible(&dev->struct_mutex);
988 if (ret)
989 return ret;
990
991 rgvmodectl = I915_READ(MEMMODECTL);
992 rstdbyctl = I915_READ(RSTDBYCTL);
993 crstandvid = I915_READ16(CRSTANDVID);
994
995 mutex_unlock(&dev->struct_mutex);
996
997 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
998 "yes" : "no");
999 seq_printf(m, "Boost freq: %d\n",
1000 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1001 MEMMODE_BOOST_FREQ_SHIFT);
1002 seq_printf(m, "HW control enabled: %s\n",
1003 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1004 seq_printf(m, "SW control enabled: %s\n",
1005 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1006 seq_printf(m, "Gated voltage change: %s\n",
1007 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1008 seq_printf(m, "Starting frequency: P%d\n",
1009 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1010 seq_printf(m, "Max P-state: P%d\n",
1011 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1012 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1013 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1014 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1015 seq_printf(m, "Render standby enabled: %s\n",
1016 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1017 seq_printf(m, "Current RS state: ");
1018 switch (rstdbyctl & RSX_STATUS_MASK) {
1019 case RSX_STATUS_ON:
1020 seq_printf(m, "on\n");
1021 break;
1022 case RSX_STATUS_RC1:
1023 seq_printf(m, "RC1\n");
1024 break;
1025 case RSX_STATUS_RC1E:
1026 seq_printf(m, "RC1E\n");
1027 break;
1028 case RSX_STATUS_RS1:
1029 seq_printf(m, "RS1\n");
1030 break;
1031 case RSX_STATUS_RS2:
1032 seq_printf(m, "RS2 (RC6)\n");
1033 break;
1034 case RSX_STATUS_RS3:
1035 seq_printf(m, "RC3 (RC6+)\n");
1036 break;
1037 default:
1038 seq_printf(m, "unknown\n");
1039 break;
1040 }
1041
1042 return 0;
1043 }
1044
1045 static int gen6_drpc_info(struct seq_file *m)
1046 {
1047
1048 struct drm_info_node *node = (struct drm_info_node *) m->private;
1049 struct drm_device *dev = node->minor->dev;
1050 struct drm_i915_private *dev_priv = dev->dev_private;
1051 u32 rpmodectl1, gt_core_status, rcctl1;
1052 int count=0, ret;
1053
1054
1055 ret = mutex_lock_interruptible(&dev->struct_mutex);
1056 if (ret)
1057 return ret;
1058
1059 if (atomic_read(&dev_priv->forcewake_count)) {
1060 seq_printf(m, "RC information inaccurate because userspace "
1061 "holds a reference \n");
1062 } else {
1063 /* NB: we cannot use forcewake, else we read the wrong values */
1064 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1065 udelay(10);
1066 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1067 }
1068
1069 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1070 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4);
1071
1072 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1073 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1074 mutex_unlock(&dev->struct_mutex);
1075
1076 seq_printf(m, "Video Turbo Mode: %s\n",
1077 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1078 seq_printf(m, "HW control enabled: %s\n",
1079 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1080 seq_printf(m, "SW control enabled: %s\n",
1081 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1082 GEN6_RP_MEDIA_SW_MODE));
1083 seq_printf(m, "RC6 Enabled: %s\n",
1084 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1085 seq_printf(m, "RC6 Enabled: %s\n",
1086 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1087 seq_printf(m, "Deep RC6 Enabled: %s\n",
1088 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1089 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1090 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1091 seq_printf(m, "Current RC state: ");
1092 switch (gt_core_status & GEN6_RCn_MASK) {
1093 case GEN6_RC0:
1094 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1095 seq_printf(m, "Core Power Down\n");
1096 else
1097 seq_printf(m, "on\n");
1098 break;
1099 case GEN6_RC3:
1100 seq_printf(m, "RC3\n");
1101 break;
1102 case GEN6_RC6:
1103 seq_printf(m, "RC6\n");
1104 break;
1105 case GEN6_RC7:
1106 seq_printf(m, "RC7\n");
1107 break;
1108 default:
1109 seq_printf(m, "Unknown\n");
1110 break;
1111 }
1112
1113 seq_printf(m, "Core Power Down: %s\n",
1114 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1115 return 0;
1116 }
1117
1118 static int i915_drpc_info(struct seq_file *m, void *unused)
1119 {
1120 struct drm_info_node *node = (struct drm_info_node *) m->private;
1121 struct drm_device *dev = node->minor->dev;
1122
1123 if (IS_GEN6(dev) || IS_GEN7(dev))
1124 return gen6_drpc_info(m);
1125 else
1126 return ironlake_drpc_info(m);
1127 }
1128
1129 static int i915_fbc_status(struct seq_file *m, void *unused)
1130 {
1131 struct drm_info_node *node = (struct drm_info_node *) m->private;
1132 struct drm_device *dev = node->minor->dev;
1133 drm_i915_private_t *dev_priv = dev->dev_private;
1134
1135 if (!I915_HAS_FBC(dev)) {
1136 seq_printf(m, "FBC unsupported on this chipset\n");
1137 return 0;
1138 }
1139
1140 if (intel_fbc_enabled(dev)) {
1141 seq_printf(m, "FBC enabled\n");
1142 } else {
1143 seq_printf(m, "FBC disabled: ");
1144 switch (dev_priv->no_fbc_reason) {
1145 case FBC_NO_OUTPUT:
1146 seq_printf(m, "no outputs");
1147 break;
1148 case FBC_STOLEN_TOO_SMALL:
1149 seq_printf(m, "not enough stolen memory");
1150 break;
1151 case FBC_UNSUPPORTED_MODE:
1152 seq_printf(m, "mode not supported");
1153 break;
1154 case FBC_MODE_TOO_LARGE:
1155 seq_printf(m, "mode too large");
1156 break;
1157 case FBC_BAD_PLANE:
1158 seq_printf(m, "FBC unsupported on plane");
1159 break;
1160 case FBC_NOT_TILED:
1161 seq_printf(m, "scanout buffer not tiled");
1162 break;
1163 case FBC_MULTIPLE_PIPES:
1164 seq_printf(m, "multiple pipes are enabled");
1165 break;
1166 case FBC_MODULE_PARAM:
1167 seq_printf(m, "disabled per module param (default off)");
1168 break;
1169 default:
1170 seq_printf(m, "unknown reason");
1171 }
1172 seq_printf(m, "\n");
1173 }
1174 return 0;
1175 }
1176
1177 static int i915_sr_status(struct seq_file *m, void *unused)
1178 {
1179 struct drm_info_node *node = (struct drm_info_node *) m->private;
1180 struct drm_device *dev = node->minor->dev;
1181 drm_i915_private_t *dev_priv = dev->dev_private;
1182 bool sr_enabled = false;
1183
1184 if (HAS_PCH_SPLIT(dev))
1185 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1186 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1187 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1188 else if (IS_I915GM(dev))
1189 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1190 else if (IS_PINEVIEW(dev))
1191 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1192
1193 seq_printf(m, "self-refresh: %s\n",
1194 sr_enabled ? "enabled" : "disabled");
1195
1196 return 0;
1197 }
1198
1199 static int i915_emon_status(struct seq_file *m, void *unused)
1200 {
1201 struct drm_info_node *node = (struct drm_info_node *) m->private;
1202 struct drm_device *dev = node->minor->dev;
1203 drm_i915_private_t *dev_priv = dev->dev_private;
1204 unsigned long temp, chipset, gfx;
1205 int ret;
1206
1207 ret = mutex_lock_interruptible(&dev->struct_mutex);
1208 if (ret)
1209 return ret;
1210
1211 temp = i915_mch_val(dev_priv);
1212 chipset = i915_chipset_val(dev_priv);
1213 gfx = i915_gfx_val(dev_priv);
1214 mutex_unlock(&dev->struct_mutex);
1215
1216 seq_printf(m, "GMCH temp: %ld\n", temp);
1217 seq_printf(m, "Chipset power: %ld\n", chipset);
1218 seq_printf(m, "GFX power: %ld\n", gfx);
1219 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1220
1221 return 0;
1222 }
1223
1224 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1225 {
1226 struct drm_info_node *node = (struct drm_info_node *) m->private;
1227 struct drm_device *dev = node->minor->dev;
1228 drm_i915_private_t *dev_priv = dev->dev_private;
1229 int ret;
1230 int gpu_freq, ia_freq;
1231
1232 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1233 seq_printf(m, "unsupported on this chipset\n");
1234 return 0;
1235 }
1236
1237 ret = mutex_lock_interruptible(&dev->struct_mutex);
1238 if (ret)
1239 return ret;
1240
1241 seq_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\n");
1242
1243 for (gpu_freq = dev_priv->min_delay; gpu_freq <= dev_priv->max_delay;
1244 gpu_freq++) {
1245 I915_WRITE(GEN6_PCODE_DATA, gpu_freq);
1246 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
1247 GEN6_PCODE_READ_MIN_FREQ_TABLE);
1248 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
1249 GEN6_PCODE_READY) == 0, 10)) {
1250 DRM_ERROR("pcode read of freq table timed out\n");
1251 continue;
1252 }
1253 ia_freq = I915_READ(GEN6_PCODE_DATA);
1254 seq_printf(m, "%d\t\t%d\n", gpu_freq * 50, ia_freq * 100);
1255 }
1256
1257 mutex_unlock(&dev->struct_mutex);
1258
1259 return 0;
1260 }
1261
1262 static int i915_gfxec(struct seq_file *m, void *unused)
1263 {
1264 struct drm_info_node *node = (struct drm_info_node *) m->private;
1265 struct drm_device *dev = node->minor->dev;
1266 drm_i915_private_t *dev_priv = dev->dev_private;
1267 int ret;
1268
1269 ret = mutex_lock_interruptible(&dev->struct_mutex);
1270 if (ret)
1271 return ret;
1272
1273 seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1274
1275 mutex_unlock(&dev->struct_mutex);
1276
1277 return 0;
1278 }
1279
1280 static int i915_opregion(struct seq_file *m, void *unused)
1281 {
1282 struct drm_info_node *node = (struct drm_info_node *) m->private;
1283 struct drm_device *dev = node->minor->dev;
1284 drm_i915_private_t *dev_priv = dev->dev_private;
1285 struct intel_opregion *opregion = &dev_priv->opregion;
1286 int ret;
1287
1288 ret = mutex_lock_interruptible(&dev->struct_mutex);
1289 if (ret)
1290 return ret;
1291
1292 if (opregion->header)
1293 seq_write(m, opregion->header, OPREGION_SIZE);
1294
1295 mutex_unlock(&dev->struct_mutex);
1296
1297 return 0;
1298 }
1299
1300 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1301 {
1302 struct drm_info_node *node = (struct drm_info_node *) m->private;
1303 struct drm_device *dev = node->minor->dev;
1304 drm_i915_private_t *dev_priv = dev->dev_private;
1305 struct intel_fbdev *ifbdev;
1306 struct intel_framebuffer *fb;
1307 int ret;
1308
1309 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1310 if (ret)
1311 return ret;
1312
1313 ifbdev = dev_priv->fbdev;
1314 fb = to_intel_framebuffer(ifbdev->helper.fb);
1315
1316 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ",
1317 fb->base.width,
1318 fb->base.height,
1319 fb->base.depth,
1320 fb->base.bits_per_pixel);
1321 describe_obj(m, fb->obj);
1322 seq_printf(m, "\n");
1323
1324 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1325 if (&fb->base == ifbdev->helper.fb)
1326 continue;
1327
1328 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ",
1329 fb->base.width,
1330 fb->base.height,
1331 fb->base.depth,
1332 fb->base.bits_per_pixel);
1333 describe_obj(m, fb->obj);
1334 seq_printf(m, "\n");
1335 }
1336
1337 mutex_unlock(&dev->mode_config.mutex);
1338
1339 return 0;
1340 }
1341
1342 static int i915_context_status(struct seq_file *m, void *unused)
1343 {
1344 struct drm_info_node *node = (struct drm_info_node *) m->private;
1345 struct drm_device *dev = node->minor->dev;
1346 drm_i915_private_t *dev_priv = dev->dev_private;
1347 int ret;
1348
1349 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1350 if (ret)
1351 return ret;
1352
1353 if (dev_priv->pwrctx) {
1354 seq_printf(m, "power context ");
1355 describe_obj(m, dev_priv->pwrctx);
1356 seq_printf(m, "\n");
1357 }
1358
1359 if (dev_priv->renderctx) {
1360 seq_printf(m, "render context ");
1361 describe_obj(m, dev_priv->renderctx);
1362 seq_printf(m, "\n");
1363 }
1364
1365 mutex_unlock(&dev->mode_config.mutex);
1366
1367 return 0;
1368 }
1369
1370 static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1371 {
1372 struct drm_info_node *node = (struct drm_info_node *) m->private;
1373 struct drm_device *dev = node->minor->dev;
1374 struct drm_i915_private *dev_priv = dev->dev_private;
1375
1376 seq_printf(m, "forcewake count = %d\n",
1377 atomic_read(&dev_priv->forcewake_count));
1378
1379 return 0;
1380 }
1381
1382 static const char *swizzle_string(unsigned swizzle)
1383 {
1384 switch(swizzle) {
1385 case I915_BIT_6_SWIZZLE_NONE:
1386 return "none";
1387 case I915_BIT_6_SWIZZLE_9:
1388 return "bit9";
1389 case I915_BIT_6_SWIZZLE_9_10:
1390 return "bit9/bit10";
1391 case I915_BIT_6_SWIZZLE_9_11:
1392 return "bit9/bit11";
1393 case I915_BIT_6_SWIZZLE_9_10_11:
1394 return "bit9/bit10/bit11";
1395 case I915_BIT_6_SWIZZLE_9_17:
1396 return "bit9/bit17";
1397 case I915_BIT_6_SWIZZLE_9_10_17:
1398 return "bit9/bit10/bit17";
1399 case I915_BIT_6_SWIZZLE_UNKNOWN:
1400 return "unkown";
1401 }
1402
1403 return "bug";
1404 }
1405
1406 static int i915_swizzle_info(struct seq_file *m, void *data)
1407 {
1408 struct drm_info_node *node = (struct drm_info_node *) m->private;
1409 struct drm_device *dev = node->minor->dev;
1410 struct drm_i915_private *dev_priv = dev->dev_private;
1411
1412 mutex_lock(&dev->struct_mutex);
1413 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1414 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1415 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1416 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1417
1418 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1419 seq_printf(m, "DDC = 0x%08x\n",
1420 I915_READ(DCC));
1421 seq_printf(m, "C0DRB3 = 0x%04x\n",
1422 I915_READ16(C0DRB3));
1423 seq_printf(m, "C1DRB3 = 0x%04x\n",
1424 I915_READ16(C1DRB3));
1425 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1426 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1427 I915_READ(MAD_DIMM_C0));
1428 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1429 I915_READ(MAD_DIMM_C1));
1430 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1431 I915_READ(MAD_DIMM_C2));
1432 seq_printf(m, "TILECTL = 0x%08x\n",
1433 I915_READ(TILECTL));
1434 seq_printf(m, "ARB_MODE = 0x%08x\n",
1435 I915_READ(ARB_MODE));
1436 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1437 I915_READ(DISP_ARB_CTL));
1438 }
1439 mutex_unlock(&dev->struct_mutex);
1440
1441 return 0;
1442 }
1443
1444 static int
1445 i915_debugfs_common_open(struct inode *inode,
1446 struct file *filp)
1447 {
1448 filp->private_data = inode->i_private;
1449 return 0;
1450 }
1451
1452 static ssize_t
1453 i915_wedged_read(struct file *filp,
1454 char __user *ubuf,
1455 size_t max,
1456 loff_t *ppos)
1457 {
1458 struct drm_device *dev = filp->private_data;
1459 drm_i915_private_t *dev_priv = dev->dev_private;
1460 char buf[80];
1461 int len;
1462
1463 len = snprintf(buf, sizeof(buf),
1464 "wedged : %d\n",
1465 atomic_read(&dev_priv->mm.wedged));
1466
1467 if (len > sizeof(buf))
1468 len = sizeof(buf);
1469
1470 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1471 }
1472
1473 static ssize_t
1474 i915_wedged_write(struct file *filp,
1475 const char __user *ubuf,
1476 size_t cnt,
1477 loff_t *ppos)
1478 {
1479 struct drm_device *dev = filp->private_data;
1480 char buf[20];
1481 int val = 1;
1482
1483 if (cnt > 0) {
1484 if (cnt > sizeof(buf) - 1)
1485 return -EINVAL;
1486
1487 if (copy_from_user(buf, ubuf, cnt))
1488 return -EFAULT;
1489 buf[cnt] = 0;
1490
1491 val = simple_strtoul(buf, NULL, 0);
1492 }
1493
1494 DRM_INFO("Manually setting wedged to %d\n", val);
1495 i915_handle_error(dev, val);
1496
1497 return cnt;
1498 }
1499
1500 static const struct file_operations i915_wedged_fops = {
1501 .owner = THIS_MODULE,
1502 .open = i915_debugfs_common_open,
1503 .read = i915_wedged_read,
1504 .write = i915_wedged_write,
1505 .llseek = default_llseek,
1506 };
1507
1508 static ssize_t
1509 i915_max_freq_read(struct file *filp,
1510 char __user *ubuf,
1511 size_t max,
1512 loff_t *ppos)
1513 {
1514 struct drm_device *dev = filp->private_data;
1515 drm_i915_private_t *dev_priv = dev->dev_private;
1516 char buf[80];
1517 int len;
1518
1519 len = snprintf(buf, sizeof(buf),
1520 "max freq: %d\n", dev_priv->max_delay * 50);
1521
1522 if (len > sizeof(buf))
1523 len = sizeof(buf);
1524
1525 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1526 }
1527
1528 static ssize_t
1529 i915_max_freq_write(struct file *filp,
1530 const char __user *ubuf,
1531 size_t cnt,
1532 loff_t *ppos)
1533 {
1534 struct drm_device *dev = filp->private_data;
1535 struct drm_i915_private *dev_priv = dev->dev_private;
1536 char buf[20];
1537 int val = 1;
1538
1539 if (cnt > 0) {
1540 if (cnt > sizeof(buf) - 1)
1541 return -EINVAL;
1542
1543 if (copy_from_user(buf, ubuf, cnt))
1544 return -EFAULT;
1545 buf[cnt] = 0;
1546
1547 val = simple_strtoul(buf, NULL, 0);
1548 }
1549
1550 DRM_DEBUG_DRIVER("Manually setting max freq to %d\n", val);
1551
1552 /*
1553 * Turbo will still be enabled, but won't go above the set value.
1554 */
1555 dev_priv->max_delay = val / 50;
1556
1557 gen6_set_rps(dev, val / 50);
1558
1559 return cnt;
1560 }
1561
1562 static const struct file_operations i915_max_freq_fops = {
1563 .owner = THIS_MODULE,
1564 .open = i915_debugfs_common_open,
1565 .read = i915_max_freq_read,
1566 .write = i915_max_freq_write,
1567 .llseek = default_llseek,
1568 };
1569
1570 static ssize_t
1571 i915_cache_sharing_read(struct file *filp,
1572 char __user *ubuf,
1573 size_t max,
1574 loff_t *ppos)
1575 {
1576 struct drm_device *dev = filp->private_data;
1577 drm_i915_private_t *dev_priv = dev->dev_private;
1578 char buf[80];
1579 u32 snpcr;
1580 int len;
1581
1582 mutex_lock(&dev_priv->dev->struct_mutex);
1583 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
1584 mutex_unlock(&dev_priv->dev->struct_mutex);
1585
1586 len = snprintf(buf, sizeof(buf),
1587 "%d\n", (snpcr & GEN6_MBC_SNPCR_MASK) >>
1588 GEN6_MBC_SNPCR_SHIFT);
1589
1590 if (len > sizeof(buf))
1591 len = sizeof(buf);
1592
1593 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1594 }
1595
1596 static ssize_t
1597 i915_cache_sharing_write(struct file *filp,
1598 const char __user *ubuf,
1599 size_t cnt,
1600 loff_t *ppos)
1601 {
1602 struct drm_device *dev = filp->private_data;
1603 struct drm_i915_private *dev_priv = dev->dev_private;
1604 char buf[20];
1605 u32 snpcr;
1606 int val = 1;
1607
1608 if (cnt > 0) {
1609 if (cnt > sizeof(buf) - 1)
1610 return -EINVAL;
1611
1612 if (copy_from_user(buf, ubuf, cnt))
1613 return -EFAULT;
1614 buf[cnt] = 0;
1615
1616 val = simple_strtoul(buf, NULL, 0);
1617 }
1618
1619 if (val < 0 || val > 3)
1620 return -EINVAL;
1621
1622 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %d\n", val);
1623
1624 /* Update the cache sharing policy here as well */
1625 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
1626 snpcr &= ~GEN6_MBC_SNPCR_MASK;
1627 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
1628 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
1629
1630 return cnt;
1631 }
1632
1633 static const struct file_operations i915_cache_sharing_fops = {
1634 .owner = THIS_MODULE,
1635 .open = i915_debugfs_common_open,
1636 .read = i915_cache_sharing_read,
1637 .write = i915_cache_sharing_write,
1638 .llseek = default_llseek,
1639 };
1640
1641 /* As the drm_debugfs_init() routines are called before dev->dev_private is
1642 * allocated we need to hook into the minor for release. */
1643 static int
1644 drm_add_fake_info_node(struct drm_minor *minor,
1645 struct dentry *ent,
1646 const void *key)
1647 {
1648 struct drm_info_node *node;
1649
1650 node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL);
1651 if (node == NULL) {
1652 debugfs_remove(ent);
1653 return -ENOMEM;
1654 }
1655
1656 node->minor = minor;
1657 node->dent = ent;
1658 node->info_ent = (void *) key;
1659
1660 mutex_lock(&minor->debugfs_lock);
1661 list_add(&node->list, &minor->debugfs_list);
1662 mutex_unlock(&minor->debugfs_lock);
1663
1664 return 0;
1665 }
1666
1667 static int i915_forcewake_open(struct inode *inode, struct file *file)
1668 {
1669 struct drm_device *dev = inode->i_private;
1670 struct drm_i915_private *dev_priv = dev->dev_private;
1671 int ret;
1672
1673 if (!IS_GEN6(dev))
1674 return 0;
1675
1676 ret = mutex_lock_interruptible(&dev->struct_mutex);
1677 if (ret)
1678 return ret;
1679 gen6_gt_force_wake_get(dev_priv);
1680 mutex_unlock(&dev->struct_mutex);
1681
1682 return 0;
1683 }
1684
1685 int i915_forcewake_release(struct inode *inode, struct file *file)
1686 {
1687 struct drm_device *dev = inode->i_private;
1688 struct drm_i915_private *dev_priv = dev->dev_private;
1689
1690 if (!IS_GEN6(dev))
1691 return 0;
1692
1693 /*
1694 * It's bad that we can potentially hang userspace if struct_mutex gets
1695 * forever stuck. However, if we cannot acquire this lock it means that
1696 * almost certainly the driver has hung, is not unload-able. Therefore
1697 * hanging here is probably a minor inconvenience not to be seen my
1698 * almost every user.
1699 */
1700 mutex_lock(&dev->struct_mutex);
1701 gen6_gt_force_wake_put(dev_priv);
1702 mutex_unlock(&dev->struct_mutex);
1703
1704 return 0;
1705 }
1706
1707 static const struct file_operations i915_forcewake_fops = {
1708 .owner = THIS_MODULE,
1709 .open = i915_forcewake_open,
1710 .release = i915_forcewake_release,
1711 };
1712
1713 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
1714 {
1715 struct drm_device *dev = minor->dev;
1716 struct dentry *ent;
1717
1718 ent = debugfs_create_file("i915_forcewake_user",
1719 S_IRUSR,
1720 root, dev,
1721 &i915_forcewake_fops);
1722 if (IS_ERR(ent))
1723 return PTR_ERR(ent);
1724
1725 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
1726 }
1727
1728 static int i915_debugfs_create(struct dentry *root,
1729 struct drm_minor *minor,
1730 const char *name,
1731 const struct file_operations *fops)
1732 {
1733 struct drm_device *dev = minor->dev;
1734 struct dentry *ent;
1735
1736 ent = debugfs_create_file(name,
1737 S_IRUGO | S_IWUSR,
1738 root, dev,
1739 fops);
1740 if (IS_ERR(ent))
1741 return PTR_ERR(ent);
1742
1743 return drm_add_fake_info_node(minor, ent, fops);
1744 }
1745
1746 static struct drm_info_list i915_debugfs_list[] = {
1747 {"i915_capabilities", i915_capabilities, 0},
1748 {"i915_gem_objects", i915_gem_object_info, 0},
1749 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1750 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
1751 {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST},
1752 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
1753 {"i915_gem_pinned", i915_gem_object_list_info, 0, (void *) PINNED_LIST},
1754 {"i915_gem_deferred_free", i915_gem_object_list_info, 0, (void *) DEFERRED_FREE_LIST},
1755 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
1756 {"i915_gem_request", i915_gem_request_info, 0},
1757 {"i915_gem_seqno", i915_gem_seqno_info, 0},
1758 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
1759 {"i915_gem_interrupt", i915_interrupt_info, 0},
1760 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
1761 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
1762 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
1763 {"i915_ringbuffer_data", i915_ringbuffer_data, 0, (void *)RCS},
1764 {"i915_ringbuffer_info", i915_ringbuffer_info, 0, (void *)RCS},
1765 {"i915_bsd_ringbuffer_data", i915_ringbuffer_data, 0, (void *)VCS},
1766 {"i915_bsd_ringbuffer_info", i915_ringbuffer_info, 0, (void *)VCS},
1767 {"i915_blt_ringbuffer_data", i915_ringbuffer_data, 0, (void *)BCS},
1768 {"i915_blt_ringbuffer_info", i915_ringbuffer_info, 0, (void *)BCS},
1769 {"i915_error_state", i915_error_state, 0},
1770 {"i915_rstdby_delays", i915_rstdby_delays, 0},
1771 {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
1772 {"i915_delayfreq_table", i915_delayfreq_table, 0},
1773 {"i915_inttoext_table", i915_inttoext_table, 0},
1774 {"i915_drpc_info", i915_drpc_info, 0},
1775 {"i915_emon_status", i915_emon_status, 0},
1776 {"i915_ring_freq_table", i915_ring_freq_table, 0},
1777 {"i915_gfxec", i915_gfxec, 0},
1778 {"i915_fbc_status", i915_fbc_status, 0},
1779 {"i915_sr_status", i915_sr_status, 0},
1780 {"i915_opregion", i915_opregion, 0},
1781 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
1782 {"i915_context_status", i915_context_status, 0},
1783 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
1784 {"i915_swizzle_info", i915_swizzle_info, 0},
1785 };
1786 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
1787
1788 int i915_debugfs_init(struct drm_minor *minor)
1789 {
1790 int ret;
1791
1792 ret = i915_debugfs_create(minor->debugfs_root, minor,
1793 "i915_wedged",
1794 &i915_wedged_fops);
1795 if (ret)
1796 return ret;
1797
1798 ret = i915_forcewake_create(minor->debugfs_root, minor);
1799 if (ret)
1800 return ret;
1801
1802 ret = i915_debugfs_create(minor->debugfs_root, minor,
1803 "i915_max_freq",
1804 &i915_max_freq_fops);
1805 if (ret)
1806 return ret;
1807
1808 ret = i915_debugfs_create(minor->debugfs_root, minor,
1809 "i915_cache_sharing",
1810 &i915_cache_sharing_fops);
1811 if (ret)
1812 return ret;
1813
1814 return drm_debugfs_create_files(i915_debugfs_list,
1815 I915_DEBUGFS_ENTRIES,
1816 minor->debugfs_root, minor);
1817 }
1818
1819 void i915_debugfs_cleanup(struct drm_minor *minor)
1820 {
1821 drm_debugfs_remove_files(i915_debugfs_list,
1822 I915_DEBUGFS_ENTRIES, minor);
1823 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
1824 1, minor);
1825 drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops,
1826 1, minor);
1827 drm_debugfs_remove_files((struct drm_info_list *) &i915_max_freq_fops,
1828 1, minor);
1829 drm_debugfs_remove_files((struct drm_info_list *) &i915_cache_sharing_fops,
1830 1, minor);
1831 }
1832
1833 #endif /* CONFIG_DEBUG_FS */
Linux kernel - Deliverables
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