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drm/i915: Reject opening of pipe crc files for invalid pipes
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
37 #include <drm/drmP.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
41 #include "i915_drv.h"
42
43 #if defined(CONFIG_DEBUG_FS)
44
45 enum {
46 ACTIVE_LIST,
47 INACTIVE_LIST,
48 PINNED_LIST,
49 };
50
51 static const char *yesno(int v)
52 {
53 return v ? "yes" : "no";
54 }
55
56 /* As the drm_debugfs_init() routines are called before dev->dev_private is
57 * allocated we need to hook into the minor for release. */
58 static int
59 drm_add_fake_info_node(struct drm_minor *minor,
60 struct dentry *ent,
61 const void *key)
62 {
63 struct drm_info_node *node;
64
65 node = kmalloc(sizeof(*node), GFP_KERNEL);
66 if (node == NULL) {
67 debugfs_remove(ent);
68 return -ENOMEM;
69 }
70
71 node->minor = minor;
72 node->dent = ent;
73 node->info_ent = (void *) key;
74
75 mutex_lock(&minor->debugfs_lock);
76 list_add(&node->list, &minor->debugfs_list);
77 mutex_unlock(&minor->debugfs_lock);
78
79 return 0;
80 }
81
82 static int i915_capabilities(struct seq_file *m, void *data)
83 {
84 struct drm_info_node *node = (struct drm_info_node *) m->private;
85 struct drm_device *dev = node->minor->dev;
86 const struct intel_device_info *info = INTEL_INFO(dev);
87
88 seq_printf(m, "gen: %d\n", info->gen);
89 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
90 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
91 #define SEP_SEMICOLON ;
92 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
93 #undef PRINT_FLAG
94 #undef SEP_SEMICOLON
95
96 return 0;
97 }
98
99 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
100 {
101 if (obj->user_pin_count > 0)
102 return "P";
103 else if (obj->pin_count > 0)
104 return "p";
105 else
106 return " ";
107 }
108
109 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
110 {
111 switch (obj->tiling_mode) {
112 default:
113 case I915_TILING_NONE: return " ";
114 case I915_TILING_X: return "X";
115 case I915_TILING_Y: return "Y";
116 }
117 }
118
119 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
120 {
121 return obj->has_global_gtt_mapping ? "g" : " ";
122 }
123
124 static void
125 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
126 {
127 struct i915_vma *vma;
128 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
129 &obj->base,
130 get_pin_flag(obj),
131 get_tiling_flag(obj),
132 get_global_flag(obj),
133 obj->base.size / 1024,
134 obj->base.read_domains,
135 obj->base.write_domain,
136 obj->last_read_seqno,
137 obj->last_write_seqno,
138 obj->last_fenced_seqno,
139 i915_cache_level_str(obj->cache_level),
140 obj->dirty ? " dirty" : "",
141 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
142 if (obj->base.name)
143 seq_printf(m, " (name: %d)", obj->base.name);
144 if (obj->pin_count)
145 seq_printf(m, " (pinned x %d)", obj->pin_count);
146 if (obj->pin_display)
147 seq_printf(m, " (display)");
148 if (obj->fence_reg != I915_FENCE_REG_NONE)
149 seq_printf(m, " (fence: %d)", obj->fence_reg);
150 list_for_each_entry(vma, &obj->vma_list, vma_link) {
151 if (!i915_is_ggtt(vma->vm))
152 seq_puts(m, " (pp");
153 else
154 seq_puts(m, " (g");
155 seq_printf(m, "gtt offset: %08lx, size: %08lx)",
156 vma->node.start, vma->node.size);
157 }
158 if (obj->stolen)
159 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
160 if (obj->pin_mappable || obj->fault_mappable) {
161 char s[3], *t = s;
162 if (obj->pin_mappable)
163 *t++ = 'p';
164 if (obj->fault_mappable)
165 *t++ = 'f';
166 *t = '\0';
167 seq_printf(m, " (%s mappable)", s);
168 }
169 if (obj->ring != NULL)
170 seq_printf(m, " (%s)", obj->ring->name);
171 }
172
173 static void describe_ctx(struct seq_file *m, struct i915_hw_context *ctx)
174 {
175 seq_putc(m, ctx->is_initialized ? 'I' : 'i');
176 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
177 seq_putc(m, ' ');
178 }
179
180 static int i915_gem_object_list_info(struct seq_file *m, void *data)
181 {
182 struct drm_info_node *node = (struct drm_info_node *) m->private;
183 uintptr_t list = (uintptr_t) node->info_ent->data;
184 struct list_head *head;
185 struct drm_device *dev = node->minor->dev;
186 struct drm_i915_private *dev_priv = dev->dev_private;
187 struct i915_address_space *vm = &dev_priv->gtt.base;
188 struct i915_vma *vma;
189 size_t total_obj_size, total_gtt_size;
190 int count, ret;
191
192 ret = mutex_lock_interruptible(&dev->struct_mutex);
193 if (ret)
194 return ret;
195
196 /* FIXME: the user of this interface might want more than just GGTT */
197 switch (list) {
198 case ACTIVE_LIST:
199 seq_puts(m, "Active:\n");
200 head = &vm->active_list;
201 break;
202 case INACTIVE_LIST:
203 seq_puts(m, "Inactive:\n");
204 head = &vm->inactive_list;
205 break;
206 default:
207 mutex_unlock(&dev->struct_mutex);
208 return -EINVAL;
209 }
210
211 total_obj_size = total_gtt_size = count = 0;
212 list_for_each_entry(vma, head, mm_list) {
213 seq_printf(m, " ");
214 describe_obj(m, vma->obj);
215 seq_printf(m, "\n");
216 total_obj_size += vma->obj->base.size;
217 total_gtt_size += vma->node.size;
218 count++;
219 }
220 mutex_unlock(&dev->struct_mutex);
221
222 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
223 count, total_obj_size, total_gtt_size);
224 return 0;
225 }
226
227 static int obj_rank_by_stolen(void *priv,
228 struct list_head *A, struct list_head *B)
229 {
230 struct drm_i915_gem_object *a =
231 container_of(A, struct drm_i915_gem_object, obj_exec_link);
232 struct drm_i915_gem_object *b =
233 container_of(B, struct drm_i915_gem_object, obj_exec_link);
234
235 return a->stolen->start - b->stolen->start;
236 }
237
238 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
239 {
240 struct drm_info_node *node = (struct drm_info_node *) m->private;
241 struct drm_device *dev = node->minor->dev;
242 struct drm_i915_private *dev_priv = dev->dev_private;
243 struct drm_i915_gem_object *obj;
244 size_t total_obj_size, total_gtt_size;
245 LIST_HEAD(stolen);
246 int count, ret;
247
248 ret = mutex_lock_interruptible(&dev->struct_mutex);
249 if (ret)
250 return ret;
251
252 total_obj_size = total_gtt_size = count = 0;
253 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
254 if (obj->stolen == NULL)
255 continue;
256
257 list_add(&obj->obj_exec_link, &stolen);
258
259 total_obj_size += obj->base.size;
260 total_gtt_size += i915_gem_obj_ggtt_size(obj);
261 count++;
262 }
263 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
264 if (obj->stolen == NULL)
265 continue;
266
267 list_add(&obj->obj_exec_link, &stolen);
268
269 total_obj_size += obj->base.size;
270 count++;
271 }
272 list_sort(NULL, &stolen, obj_rank_by_stolen);
273 seq_puts(m, "Stolen:\n");
274 while (!list_empty(&stolen)) {
275 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
276 seq_puts(m, " ");
277 describe_obj(m, obj);
278 seq_putc(m, '\n');
279 list_del_init(&obj->obj_exec_link);
280 }
281 mutex_unlock(&dev->struct_mutex);
282
283 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
284 count, total_obj_size, total_gtt_size);
285 return 0;
286 }
287
288 #define count_objects(list, member) do { \
289 list_for_each_entry(obj, list, member) { \
290 size += i915_gem_obj_ggtt_size(obj); \
291 ++count; \
292 if (obj->map_and_fenceable) { \
293 mappable_size += i915_gem_obj_ggtt_size(obj); \
294 ++mappable_count; \
295 } \
296 } \
297 } while (0)
298
299 struct file_stats {
300 int count;
301 size_t total, active, inactive, unbound;
302 };
303
304 static int per_file_stats(int id, void *ptr, void *data)
305 {
306 struct drm_i915_gem_object *obj = ptr;
307 struct file_stats *stats = data;
308
309 stats->count++;
310 stats->total += obj->base.size;
311
312 if (i915_gem_obj_ggtt_bound(obj)) {
313 if (!list_empty(&obj->ring_list))
314 stats->active += obj->base.size;
315 else
316 stats->inactive += obj->base.size;
317 } else {
318 if (!list_empty(&obj->global_list))
319 stats->unbound += obj->base.size;
320 }
321
322 return 0;
323 }
324
325 #define count_vmas(list, member) do { \
326 list_for_each_entry(vma, list, member) { \
327 size += i915_gem_obj_ggtt_size(vma->obj); \
328 ++count; \
329 if (vma->obj->map_and_fenceable) { \
330 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
331 ++mappable_count; \
332 } \
333 } \
334 } while (0)
335
336 static int i915_gem_object_info(struct seq_file *m, void* data)
337 {
338 struct drm_info_node *node = (struct drm_info_node *) m->private;
339 struct drm_device *dev = node->minor->dev;
340 struct drm_i915_private *dev_priv = dev->dev_private;
341 u32 count, mappable_count, purgeable_count;
342 size_t size, mappable_size, purgeable_size;
343 struct drm_i915_gem_object *obj;
344 struct i915_address_space *vm = &dev_priv->gtt.base;
345 struct drm_file *file;
346 struct i915_vma *vma;
347 int ret;
348
349 ret = mutex_lock_interruptible(&dev->struct_mutex);
350 if (ret)
351 return ret;
352
353 seq_printf(m, "%u objects, %zu bytes\n",
354 dev_priv->mm.object_count,
355 dev_priv->mm.object_memory);
356
357 size = count = mappable_size = mappable_count = 0;
358 count_objects(&dev_priv->mm.bound_list, global_list);
359 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
360 count, mappable_count, size, mappable_size);
361
362 size = count = mappable_size = mappable_count = 0;
363 count_vmas(&vm->active_list, mm_list);
364 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
365 count, mappable_count, size, mappable_size);
366
367 size = count = mappable_size = mappable_count = 0;
368 count_vmas(&vm->inactive_list, mm_list);
369 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
370 count, mappable_count, size, mappable_size);
371
372 size = count = purgeable_size = purgeable_count = 0;
373 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
374 size += obj->base.size, ++count;
375 if (obj->madv == I915_MADV_DONTNEED)
376 purgeable_size += obj->base.size, ++purgeable_count;
377 }
378 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
379
380 size = count = mappable_size = mappable_count = 0;
381 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
382 if (obj->fault_mappable) {
383 size += i915_gem_obj_ggtt_size(obj);
384 ++count;
385 }
386 if (obj->pin_mappable) {
387 mappable_size += i915_gem_obj_ggtt_size(obj);
388 ++mappable_count;
389 }
390 if (obj->madv == I915_MADV_DONTNEED) {
391 purgeable_size += obj->base.size;
392 ++purgeable_count;
393 }
394 }
395 seq_printf(m, "%u purgeable objects, %zu bytes\n",
396 purgeable_count, purgeable_size);
397 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
398 mappable_count, mappable_size);
399 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
400 count, size);
401
402 seq_printf(m, "%zu [%lu] gtt total\n",
403 dev_priv->gtt.base.total,
404 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
405
406 seq_putc(m, '\n');
407 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
408 struct file_stats stats;
409
410 memset(&stats, 0, sizeof(stats));
411 idr_for_each(&file->object_idr, per_file_stats, &stats);
412 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n",
413 get_pid_task(file->pid, PIDTYPE_PID)->comm,
414 stats.count,
415 stats.total,
416 stats.active,
417 stats.inactive,
418 stats.unbound);
419 }
420
421 mutex_unlock(&dev->struct_mutex);
422
423 return 0;
424 }
425
426 static int i915_gem_gtt_info(struct seq_file *m, void *data)
427 {
428 struct drm_info_node *node = (struct drm_info_node *) m->private;
429 struct drm_device *dev = node->minor->dev;
430 uintptr_t list = (uintptr_t) node->info_ent->data;
431 struct drm_i915_private *dev_priv = dev->dev_private;
432 struct drm_i915_gem_object *obj;
433 size_t total_obj_size, total_gtt_size;
434 int count, ret;
435
436 ret = mutex_lock_interruptible(&dev->struct_mutex);
437 if (ret)
438 return ret;
439
440 total_obj_size = total_gtt_size = count = 0;
441 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
442 if (list == PINNED_LIST && obj->pin_count == 0)
443 continue;
444
445 seq_puts(m, " ");
446 describe_obj(m, obj);
447 seq_putc(m, '\n');
448 total_obj_size += obj->base.size;
449 total_gtt_size += i915_gem_obj_ggtt_size(obj);
450 count++;
451 }
452
453 mutex_unlock(&dev->struct_mutex);
454
455 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
456 count, total_obj_size, total_gtt_size);
457
458 return 0;
459 }
460
461 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
462 {
463 struct drm_info_node *node = (struct drm_info_node *) m->private;
464 struct drm_device *dev = node->minor->dev;
465 unsigned long flags;
466 struct intel_crtc *crtc;
467
468 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
469 const char pipe = pipe_name(crtc->pipe);
470 const char plane = plane_name(crtc->plane);
471 struct intel_unpin_work *work;
472
473 spin_lock_irqsave(&dev->event_lock, flags);
474 work = crtc->unpin_work;
475 if (work == NULL) {
476 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
477 pipe, plane);
478 } else {
479 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
480 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
481 pipe, plane);
482 } else {
483 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
484 pipe, plane);
485 }
486 if (work->enable_stall_check)
487 seq_puts(m, "Stall check enabled, ");
488 else
489 seq_puts(m, "Stall check waiting for page flip ioctl, ");
490 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
491
492 if (work->old_fb_obj) {
493 struct drm_i915_gem_object *obj = work->old_fb_obj;
494 if (obj)
495 seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n",
496 i915_gem_obj_ggtt_offset(obj));
497 }
498 if (work->pending_flip_obj) {
499 struct drm_i915_gem_object *obj = work->pending_flip_obj;
500 if (obj)
501 seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n",
502 i915_gem_obj_ggtt_offset(obj));
503 }
504 }
505 spin_unlock_irqrestore(&dev->event_lock, flags);
506 }
507
508 return 0;
509 }
510
511 static int i915_gem_request_info(struct seq_file *m, void *data)
512 {
513 struct drm_info_node *node = (struct drm_info_node *) m->private;
514 struct drm_device *dev = node->minor->dev;
515 drm_i915_private_t *dev_priv = dev->dev_private;
516 struct intel_ring_buffer *ring;
517 struct drm_i915_gem_request *gem_request;
518 int ret, count, i;
519
520 ret = mutex_lock_interruptible(&dev->struct_mutex);
521 if (ret)
522 return ret;
523
524 count = 0;
525 for_each_ring(ring, dev_priv, i) {
526 if (list_empty(&ring->request_list))
527 continue;
528
529 seq_printf(m, "%s requests:\n", ring->name);
530 list_for_each_entry(gem_request,
531 &ring->request_list,
532 list) {
533 seq_printf(m, " %d @ %d\n",
534 gem_request->seqno,
535 (int) (jiffies - gem_request->emitted_jiffies));
536 }
537 count++;
538 }
539 mutex_unlock(&dev->struct_mutex);
540
541 if (count == 0)
542 seq_puts(m, "No requests\n");
543
544 return 0;
545 }
546
547 static void i915_ring_seqno_info(struct seq_file *m,
548 struct intel_ring_buffer *ring)
549 {
550 if (ring->get_seqno) {
551 seq_printf(m, "Current sequence (%s): %u\n",
552 ring->name, ring->get_seqno(ring, false));
553 }
554 }
555
556 static int i915_gem_seqno_info(struct seq_file *m, void *data)
557 {
558 struct drm_info_node *node = (struct drm_info_node *) m->private;
559 struct drm_device *dev = node->minor->dev;
560 drm_i915_private_t *dev_priv = dev->dev_private;
561 struct intel_ring_buffer *ring;
562 int ret, i;
563
564 ret = mutex_lock_interruptible(&dev->struct_mutex);
565 if (ret)
566 return ret;
567
568 for_each_ring(ring, dev_priv, i)
569 i915_ring_seqno_info(m, ring);
570
571 mutex_unlock(&dev->struct_mutex);
572
573 return 0;
574 }
575
576
577 static int i915_interrupt_info(struct seq_file *m, void *data)
578 {
579 struct drm_info_node *node = (struct drm_info_node *) m->private;
580 struct drm_device *dev = node->minor->dev;
581 drm_i915_private_t *dev_priv = dev->dev_private;
582 struct intel_ring_buffer *ring;
583 int ret, i, pipe;
584
585 ret = mutex_lock_interruptible(&dev->struct_mutex);
586 if (ret)
587 return ret;
588
589 if (IS_VALLEYVIEW(dev)) {
590 seq_printf(m, "Display IER:\t%08x\n",
591 I915_READ(VLV_IER));
592 seq_printf(m, "Display IIR:\t%08x\n",
593 I915_READ(VLV_IIR));
594 seq_printf(m, "Display IIR_RW:\t%08x\n",
595 I915_READ(VLV_IIR_RW));
596 seq_printf(m, "Display IMR:\t%08x\n",
597 I915_READ(VLV_IMR));
598 for_each_pipe(pipe)
599 seq_printf(m, "Pipe %c stat:\t%08x\n",
600 pipe_name(pipe),
601 I915_READ(PIPESTAT(pipe)));
602
603 seq_printf(m, "Master IER:\t%08x\n",
604 I915_READ(VLV_MASTER_IER));
605
606 seq_printf(m, "Render IER:\t%08x\n",
607 I915_READ(GTIER));
608 seq_printf(m, "Render IIR:\t%08x\n",
609 I915_READ(GTIIR));
610 seq_printf(m, "Render IMR:\t%08x\n",
611 I915_READ(GTIMR));
612
613 seq_printf(m, "PM IER:\t\t%08x\n",
614 I915_READ(GEN6_PMIER));
615 seq_printf(m, "PM IIR:\t\t%08x\n",
616 I915_READ(GEN6_PMIIR));
617 seq_printf(m, "PM IMR:\t\t%08x\n",
618 I915_READ(GEN6_PMIMR));
619
620 seq_printf(m, "Port hotplug:\t%08x\n",
621 I915_READ(PORT_HOTPLUG_EN));
622 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
623 I915_READ(VLV_DPFLIPSTAT));
624 seq_printf(m, "DPINVGTT:\t%08x\n",
625 I915_READ(DPINVGTT));
626
627 } else if (!HAS_PCH_SPLIT(dev)) {
628 seq_printf(m, "Interrupt enable: %08x\n",
629 I915_READ(IER));
630 seq_printf(m, "Interrupt identity: %08x\n",
631 I915_READ(IIR));
632 seq_printf(m, "Interrupt mask: %08x\n",
633 I915_READ(IMR));
634 for_each_pipe(pipe)
635 seq_printf(m, "Pipe %c stat: %08x\n",
636 pipe_name(pipe),
637 I915_READ(PIPESTAT(pipe)));
638 } else {
639 seq_printf(m, "North Display Interrupt enable: %08x\n",
640 I915_READ(DEIER));
641 seq_printf(m, "North Display Interrupt identity: %08x\n",
642 I915_READ(DEIIR));
643 seq_printf(m, "North Display Interrupt mask: %08x\n",
644 I915_READ(DEIMR));
645 seq_printf(m, "South Display Interrupt enable: %08x\n",
646 I915_READ(SDEIER));
647 seq_printf(m, "South Display Interrupt identity: %08x\n",
648 I915_READ(SDEIIR));
649 seq_printf(m, "South Display Interrupt mask: %08x\n",
650 I915_READ(SDEIMR));
651 seq_printf(m, "Graphics Interrupt enable: %08x\n",
652 I915_READ(GTIER));
653 seq_printf(m, "Graphics Interrupt identity: %08x\n",
654 I915_READ(GTIIR));
655 seq_printf(m, "Graphics Interrupt mask: %08x\n",
656 I915_READ(GTIMR));
657 }
658 seq_printf(m, "Interrupts received: %d\n",
659 atomic_read(&dev_priv->irq_received));
660 for_each_ring(ring, dev_priv, i) {
661 if (IS_GEN6(dev) || IS_GEN7(dev)) {
662 seq_printf(m,
663 "Graphics Interrupt mask (%s): %08x\n",
664 ring->name, I915_READ_IMR(ring));
665 }
666 i915_ring_seqno_info(m, ring);
667 }
668 mutex_unlock(&dev->struct_mutex);
669
670 return 0;
671 }
672
673 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
674 {
675 struct drm_info_node *node = (struct drm_info_node *) m->private;
676 struct drm_device *dev = node->minor->dev;
677 drm_i915_private_t *dev_priv = dev->dev_private;
678 int i, ret;
679
680 ret = mutex_lock_interruptible(&dev->struct_mutex);
681 if (ret)
682 return ret;
683
684 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
685 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
686 for (i = 0; i < dev_priv->num_fence_regs; i++) {
687 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
688
689 seq_printf(m, "Fence %d, pin count = %d, object = ",
690 i, dev_priv->fence_regs[i].pin_count);
691 if (obj == NULL)
692 seq_puts(m, "unused");
693 else
694 describe_obj(m, obj);
695 seq_putc(m, '\n');
696 }
697
698 mutex_unlock(&dev->struct_mutex);
699 return 0;
700 }
701
702 static int i915_hws_info(struct seq_file *m, void *data)
703 {
704 struct drm_info_node *node = (struct drm_info_node *) m->private;
705 struct drm_device *dev = node->minor->dev;
706 drm_i915_private_t *dev_priv = dev->dev_private;
707 struct intel_ring_buffer *ring;
708 const u32 *hws;
709 int i;
710
711 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
712 hws = ring->status_page.page_addr;
713 if (hws == NULL)
714 return 0;
715
716 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
717 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
718 i * 4,
719 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
720 }
721 return 0;
722 }
723
724 static ssize_t
725 i915_error_state_write(struct file *filp,
726 const char __user *ubuf,
727 size_t cnt,
728 loff_t *ppos)
729 {
730 struct i915_error_state_file_priv *error_priv = filp->private_data;
731 struct drm_device *dev = error_priv->dev;
732 int ret;
733
734 DRM_DEBUG_DRIVER("Resetting error state\n");
735
736 ret = mutex_lock_interruptible(&dev->struct_mutex);
737 if (ret)
738 return ret;
739
740 i915_destroy_error_state(dev);
741 mutex_unlock(&dev->struct_mutex);
742
743 return cnt;
744 }
745
746 static int i915_error_state_open(struct inode *inode, struct file *file)
747 {
748 struct drm_device *dev = inode->i_private;
749 struct i915_error_state_file_priv *error_priv;
750
751 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
752 if (!error_priv)
753 return -ENOMEM;
754
755 error_priv->dev = dev;
756
757 i915_error_state_get(dev, error_priv);
758
759 file->private_data = error_priv;
760
761 return 0;
762 }
763
764 static int i915_error_state_release(struct inode *inode, struct file *file)
765 {
766 struct i915_error_state_file_priv *error_priv = file->private_data;
767
768 i915_error_state_put(error_priv);
769 kfree(error_priv);
770
771 return 0;
772 }
773
774 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
775 size_t count, loff_t *pos)
776 {
777 struct i915_error_state_file_priv *error_priv = file->private_data;
778 struct drm_i915_error_state_buf error_str;
779 loff_t tmp_pos = 0;
780 ssize_t ret_count = 0;
781 int ret;
782
783 ret = i915_error_state_buf_init(&error_str, count, *pos);
784 if (ret)
785 return ret;
786
787 ret = i915_error_state_to_str(&error_str, error_priv);
788 if (ret)
789 goto out;
790
791 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
792 error_str.buf,
793 error_str.bytes);
794
795 if (ret_count < 0)
796 ret = ret_count;
797 else
798 *pos = error_str.start + ret_count;
799 out:
800 i915_error_state_buf_release(&error_str);
801 return ret ?: ret_count;
802 }
803
804 static const struct file_operations i915_error_state_fops = {
805 .owner = THIS_MODULE,
806 .open = i915_error_state_open,
807 .read = i915_error_state_read,
808 .write = i915_error_state_write,
809 .llseek = default_llseek,
810 .release = i915_error_state_release,
811 };
812
813 static int
814 i915_next_seqno_get(void *data, u64 *val)
815 {
816 struct drm_device *dev = data;
817 drm_i915_private_t *dev_priv = dev->dev_private;
818 int ret;
819
820 ret = mutex_lock_interruptible(&dev->struct_mutex);
821 if (ret)
822 return ret;
823
824 *val = dev_priv->next_seqno;
825 mutex_unlock(&dev->struct_mutex);
826
827 return 0;
828 }
829
830 static int
831 i915_next_seqno_set(void *data, u64 val)
832 {
833 struct drm_device *dev = data;
834 int ret;
835
836 ret = mutex_lock_interruptible(&dev->struct_mutex);
837 if (ret)
838 return ret;
839
840 ret = i915_gem_set_seqno(dev, val);
841 mutex_unlock(&dev->struct_mutex);
842
843 return ret;
844 }
845
846 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
847 i915_next_seqno_get, i915_next_seqno_set,
848 "0x%llx\n");
849
850 static int i915_rstdby_delays(struct seq_file *m, void *unused)
851 {
852 struct drm_info_node *node = (struct drm_info_node *) m->private;
853 struct drm_device *dev = node->minor->dev;
854 drm_i915_private_t *dev_priv = dev->dev_private;
855 u16 crstanddelay;
856 int ret;
857
858 ret = mutex_lock_interruptible(&dev->struct_mutex);
859 if (ret)
860 return ret;
861
862 crstanddelay = I915_READ16(CRSTANDVID);
863
864 mutex_unlock(&dev->struct_mutex);
865
866 seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
867
868 return 0;
869 }
870
871 static int i915_cur_delayinfo(struct seq_file *m, void *unused)
872 {
873 struct drm_info_node *node = (struct drm_info_node *) m->private;
874 struct drm_device *dev = node->minor->dev;
875 drm_i915_private_t *dev_priv = dev->dev_private;
876 int ret;
877
878 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
879
880 if (IS_GEN5(dev)) {
881 u16 rgvswctl = I915_READ16(MEMSWCTL);
882 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
883
884 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
885 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
886 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
887 MEMSTAT_VID_SHIFT);
888 seq_printf(m, "Current P-state: %d\n",
889 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
890 } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
891 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
892 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
893 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
894 u32 rpstat, cagf, reqf;
895 u32 rpupei, rpcurup, rpprevup;
896 u32 rpdownei, rpcurdown, rpprevdown;
897 int max_freq;
898
899 /* RPSTAT1 is in the GT power well */
900 ret = mutex_lock_interruptible(&dev->struct_mutex);
901 if (ret)
902 return ret;
903
904 gen6_gt_force_wake_get(dev_priv);
905
906 reqf = I915_READ(GEN6_RPNSWREQ);
907 reqf &= ~GEN6_TURBO_DISABLE;
908 if (IS_HASWELL(dev))
909 reqf >>= 24;
910 else
911 reqf >>= 25;
912 reqf *= GT_FREQUENCY_MULTIPLIER;
913
914 rpstat = I915_READ(GEN6_RPSTAT1);
915 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
916 rpcurup = I915_READ(GEN6_RP_CUR_UP);
917 rpprevup = I915_READ(GEN6_RP_PREV_UP);
918 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
919 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
920 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
921 if (IS_HASWELL(dev))
922 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
923 else
924 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
925 cagf *= GT_FREQUENCY_MULTIPLIER;
926
927 gen6_gt_force_wake_put(dev_priv);
928 mutex_unlock(&dev->struct_mutex);
929
930 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
931 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
932 seq_printf(m, "Render p-state ratio: %d\n",
933 (gt_perf_status & 0xff00) >> 8);
934 seq_printf(m, "Render p-state VID: %d\n",
935 gt_perf_status & 0xff);
936 seq_printf(m, "Render p-state limit: %d\n",
937 rp_state_limits & 0xff);
938 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
939 seq_printf(m, "CAGF: %dMHz\n", cagf);
940 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
941 GEN6_CURICONT_MASK);
942 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
943 GEN6_CURBSYTAVG_MASK);
944 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
945 GEN6_CURBSYTAVG_MASK);
946 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
947 GEN6_CURIAVG_MASK);
948 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
949 GEN6_CURBSYTAVG_MASK);
950 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
951 GEN6_CURBSYTAVG_MASK);
952
953 max_freq = (rp_state_cap & 0xff0000) >> 16;
954 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
955 max_freq * GT_FREQUENCY_MULTIPLIER);
956
957 max_freq = (rp_state_cap & 0xff00) >> 8;
958 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
959 max_freq * GT_FREQUENCY_MULTIPLIER);
960
961 max_freq = rp_state_cap & 0xff;
962 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
963 max_freq * GT_FREQUENCY_MULTIPLIER);
964
965 seq_printf(m, "Max overclocked frequency: %dMHz\n",
966 dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER);
967 } else if (IS_VALLEYVIEW(dev)) {
968 u32 freq_sts, val;
969
970 mutex_lock(&dev_priv->rps.hw_lock);
971 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
972 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
973 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
974
975 val = valleyview_rps_max_freq(dev_priv);
976 seq_printf(m, "max GPU freq: %d MHz\n",
977 vlv_gpu_freq(dev_priv, val));
978
979 val = valleyview_rps_min_freq(dev_priv);
980 seq_printf(m, "min GPU freq: %d MHz\n",
981 vlv_gpu_freq(dev_priv, val));
982
983 seq_printf(m, "current GPU freq: %d MHz\n",
984 vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
985 mutex_unlock(&dev_priv->rps.hw_lock);
986 } else {
987 seq_puts(m, "no P-state info available\n");
988 }
989
990 return 0;
991 }
992
993 static int i915_delayfreq_table(struct seq_file *m, void *unused)
994 {
995 struct drm_info_node *node = (struct drm_info_node *) m->private;
996 struct drm_device *dev = node->minor->dev;
997 drm_i915_private_t *dev_priv = dev->dev_private;
998 u32 delayfreq;
999 int ret, i;
1000
1001 ret = mutex_lock_interruptible(&dev->struct_mutex);
1002 if (ret)
1003 return ret;
1004
1005 for (i = 0; i < 16; i++) {
1006 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
1007 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
1008 (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
1009 }
1010
1011 mutex_unlock(&dev->struct_mutex);
1012
1013 return 0;
1014 }
1015
1016 static inline int MAP_TO_MV(int map)
1017 {
1018 return 1250 - (map * 25);
1019 }
1020
1021 static int i915_inttoext_table(struct seq_file *m, void *unused)
1022 {
1023 struct drm_info_node *node = (struct drm_info_node *) m->private;
1024 struct drm_device *dev = node->minor->dev;
1025 drm_i915_private_t *dev_priv = dev->dev_private;
1026 u32 inttoext;
1027 int ret, i;
1028
1029 ret = mutex_lock_interruptible(&dev->struct_mutex);
1030 if (ret)
1031 return ret;
1032
1033 for (i = 1; i <= 32; i++) {
1034 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
1035 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
1036 }
1037
1038 mutex_unlock(&dev->struct_mutex);
1039
1040 return 0;
1041 }
1042
1043 static int ironlake_drpc_info(struct seq_file *m)
1044 {
1045 struct drm_info_node *node = (struct drm_info_node *) m->private;
1046 struct drm_device *dev = node->minor->dev;
1047 drm_i915_private_t *dev_priv = dev->dev_private;
1048 u32 rgvmodectl, rstdbyctl;
1049 u16 crstandvid;
1050 int ret;
1051
1052 ret = mutex_lock_interruptible(&dev->struct_mutex);
1053 if (ret)
1054 return ret;
1055
1056 rgvmodectl = I915_READ(MEMMODECTL);
1057 rstdbyctl = I915_READ(RSTDBYCTL);
1058 crstandvid = I915_READ16(CRSTANDVID);
1059
1060 mutex_unlock(&dev->struct_mutex);
1061
1062 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1063 "yes" : "no");
1064 seq_printf(m, "Boost freq: %d\n",
1065 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1066 MEMMODE_BOOST_FREQ_SHIFT);
1067 seq_printf(m, "HW control enabled: %s\n",
1068 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1069 seq_printf(m, "SW control enabled: %s\n",
1070 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1071 seq_printf(m, "Gated voltage change: %s\n",
1072 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1073 seq_printf(m, "Starting frequency: P%d\n",
1074 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1075 seq_printf(m, "Max P-state: P%d\n",
1076 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1077 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1078 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1079 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1080 seq_printf(m, "Render standby enabled: %s\n",
1081 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1082 seq_puts(m, "Current RS state: ");
1083 switch (rstdbyctl & RSX_STATUS_MASK) {
1084 case RSX_STATUS_ON:
1085 seq_puts(m, "on\n");
1086 break;
1087 case RSX_STATUS_RC1:
1088 seq_puts(m, "RC1\n");
1089 break;
1090 case RSX_STATUS_RC1E:
1091 seq_puts(m, "RC1E\n");
1092 break;
1093 case RSX_STATUS_RS1:
1094 seq_puts(m, "RS1\n");
1095 break;
1096 case RSX_STATUS_RS2:
1097 seq_puts(m, "RS2 (RC6)\n");
1098 break;
1099 case RSX_STATUS_RS3:
1100 seq_puts(m, "RC3 (RC6+)\n");
1101 break;
1102 default:
1103 seq_puts(m, "unknown\n");
1104 break;
1105 }
1106
1107 return 0;
1108 }
1109
1110 static int gen6_drpc_info(struct seq_file *m)
1111 {
1112
1113 struct drm_info_node *node = (struct drm_info_node *) m->private;
1114 struct drm_device *dev = node->minor->dev;
1115 struct drm_i915_private *dev_priv = dev->dev_private;
1116 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1117 unsigned forcewake_count;
1118 int count = 0, ret;
1119
1120 ret = mutex_lock_interruptible(&dev->struct_mutex);
1121 if (ret)
1122 return ret;
1123
1124 spin_lock_irq(&dev_priv->uncore.lock);
1125 forcewake_count = dev_priv->uncore.forcewake_count;
1126 spin_unlock_irq(&dev_priv->uncore.lock);
1127
1128 if (forcewake_count) {
1129 seq_puts(m, "RC information inaccurate because somebody "
1130 "holds a forcewake reference \n");
1131 } else {
1132 /* NB: we cannot use forcewake, else we read the wrong values */
1133 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1134 udelay(10);
1135 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1136 }
1137
1138 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1139 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1140
1141 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1142 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1143 mutex_unlock(&dev->struct_mutex);
1144 mutex_lock(&dev_priv->rps.hw_lock);
1145 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1146 mutex_unlock(&dev_priv->rps.hw_lock);
1147
1148 seq_printf(m, "Video Turbo Mode: %s\n",
1149 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1150 seq_printf(m, "HW control enabled: %s\n",
1151 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1152 seq_printf(m, "SW control enabled: %s\n",
1153 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1154 GEN6_RP_MEDIA_SW_MODE));
1155 seq_printf(m, "RC1e Enabled: %s\n",
1156 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1157 seq_printf(m, "RC6 Enabled: %s\n",
1158 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1159 seq_printf(m, "Deep RC6 Enabled: %s\n",
1160 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1161 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1162 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1163 seq_puts(m, "Current RC state: ");
1164 switch (gt_core_status & GEN6_RCn_MASK) {
1165 case GEN6_RC0:
1166 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1167 seq_puts(m, "Core Power Down\n");
1168 else
1169 seq_puts(m, "on\n");
1170 break;
1171 case GEN6_RC3:
1172 seq_puts(m, "RC3\n");
1173 break;
1174 case GEN6_RC6:
1175 seq_puts(m, "RC6\n");
1176 break;
1177 case GEN6_RC7:
1178 seq_puts(m, "RC7\n");
1179 break;
1180 default:
1181 seq_puts(m, "Unknown\n");
1182 break;
1183 }
1184
1185 seq_printf(m, "Core Power Down: %s\n",
1186 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1187
1188 /* Not exactly sure what this is */
1189 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1190 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1191 seq_printf(m, "RC6 residency since boot: %u\n",
1192 I915_READ(GEN6_GT_GFX_RC6));
1193 seq_printf(m, "RC6+ residency since boot: %u\n",
1194 I915_READ(GEN6_GT_GFX_RC6p));
1195 seq_printf(m, "RC6++ residency since boot: %u\n",
1196 I915_READ(GEN6_GT_GFX_RC6pp));
1197
1198 seq_printf(m, "RC6 voltage: %dmV\n",
1199 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1200 seq_printf(m, "RC6+ voltage: %dmV\n",
1201 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1202 seq_printf(m, "RC6++ voltage: %dmV\n",
1203 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1204 return 0;
1205 }
1206
1207 static int i915_drpc_info(struct seq_file *m, void *unused)
1208 {
1209 struct drm_info_node *node = (struct drm_info_node *) m->private;
1210 struct drm_device *dev = node->minor->dev;
1211
1212 if (IS_GEN6(dev) || IS_GEN7(dev))
1213 return gen6_drpc_info(m);
1214 else
1215 return ironlake_drpc_info(m);
1216 }
1217
1218 static int i915_fbc_status(struct seq_file *m, void *unused)
1219 {
1220 struct drm_info_node *node = (struct drm_info_node *) m->private;
1221 struct drm_device *dev = node->minor->dev;
1222 drm_i915_private_t *dev_priv = dev->dev_private;
1223
1224 if (!I915_HAS_FBC(dev)) {
1225 seq_puts(m, "FBC unsupported on this chipset\n");
1226 return 0;
1227 }
1228
1229 if (intel_fbc_enabled(dev)) {
1230 seq_puts(m, "FBC enabled\n");
1231 } else {
1232 seq_puts(m, "FBC disabled: ");
1233 switch (dev_priv->fbc.no_fbc_reason) {
1234 case FBC_OK:
1235 seq_puts(m, "FBC actived, but currently disabled in hardware");
1236 break;
1237 case FBC_UNSUPPORTED:
1238 seq_puts(m, "unsupported by this chipset");
1239 break;
1240 case FBC_NO_OUTPUT:
1241 seq_puts(m, "no outputs");
1242 break;
1243 case FBC_STOLEN_TOO_SMALL:
1244 seq_puts(m, "not enough stolen memory");
1245 break;
1246 case FBC_UNSUPPORTED_MODE:
1247 seq_puts(m, "mode not supported");
1248 break;
1249 case FBC_MODE_TOO_LARGE:
1250 seq_puts(m, "mode too large");
1251 break;
1252 case FBC_BAD_PLANE:
1253 seq_puts(m, "FBC unsupported on plane");
1254 break;
1255 case FBC_NOT_TILED:
1256 seq_puts(m, "scanout buffer not tiled");
1257 break;
1258 case FBC_MULTIPLE_PIPES:
1259 seq_puts(m, "multiple pipes are enabled");
1260 break;
1261 case FBC_MODULE_PARAM:
1262 seq_puts(m, "disabled per module param (default off)");
1263 break;
1264 case FBC_CHIP_DEFAULT:
1265 seq_puts(m, "disabled per chip default");
1266 break;
1267 default:
1268 seq_puts(m, "unknown reason");
1269 }
1270 seq_putc(m, '\n');
1271 }
1272 return 0;
1273 }
1274
1275 static int i915_ips_status(struct seq_file *m, void *unused)
1276 {
1277 struct drm_info_node *node = (struct drm_info_node *) m->private;
1278 struct drm_device *dev = node->minor->dev;
1279 struct drm_i915_private *dev_priv = dev->dev_private;
1280
1281 if (!HAS_IPS(dev)) {
1282 seq_puts(m, "not supported\n");
1283 return 0;
1284 }
1285
1286 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1287 seq_puts(m, "enabled\n");
1288 else
1289 seq_puts(m, "disabled\n");
1290
1291 return 0;
1292 }
1293
1294 static int i915_sr_status(struct seq_file *m, void *unused)
1295 {
1296 struct drm_info_node *node = (struct drm_info_node *) m->private;
1297 struct drm_device *dev = node->minor->dev;
1298 drm_i915_private_t *dev_priv = dev->dev_private;
1299 bool sr_enabled = false;
1300
1301 if (HAS_PCH_SPLIT(dev))
1302 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1303 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1304 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1305 else if (IS_I915GM(dev))
1306 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1307 else if (IS_PINEVIEW(dev))
1308 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1309
1310 seq_printf(m, "self-refresh: %s\n",
1311 sr_enabled ? "enabled" : "disabled");
1312
1313 return 0;
1314 }
1315
1316 static int i915_emon_status(struct seq_file *m, void *unused)
1317 {
1318 struct drm_info_node *node = (struct drm_info_node *) m->private;
1319 struct drm_device *dev = node->minor->dev;
1320 drm_i915_private_t *dev_priv = dev->dev_private;
1321 unsigned long temp, chipset, gfx;
1322 int ret;
1323
1324 if (!IS_GEN5(dev))
1325 return -ENODEV;
1326
1327 ret = mutex_lock_interruptible(&dev->struct_mutex);
1328 if (ret)
1329 return ret;
1330
1331 temp = i915_mch_val(dev_priv);
1332 chipset = i915_chipset_val(dev_priv);
1333 gfx = i915_gfx_val(dev_priv);
1334 mutex_unlock(&dev->struct_mutex);
1335
1336 seq_printf(m, "GMCH temp: %ld\n", temp);
1337 seq_printf(m, "Chipset power: %ld\n", chipset);
1338 seq_printf(m, "GFX power: %ld\n", gfx);
1339 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1340
1341 return 0;
1342 }
1343
1344 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1345 {
1346 struct drm_info_node *node = (struct drm_info_node *) m->private;
1347 struct drm_device *dev = node->minor->dev;
1348 drm_i915_private_t *dev_priv = dev->dev_private;
1349 int ret;
1350 int gpu_freq, ia_freq;
1351
1352 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1353 seq_puts(m, "unsupported on this chipset\n");
1354 return 0;
1355 }
1356
1357 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1358
1359 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1360 if (ret)
1361 return ret;
1362
1363 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1364
1365 for (gpu_freq = dev_priv->rps.min_delay;
1366 gpu_freq <= dev_priv->rps.max_delay;
1367 gpu_freq++) {
1368 ia_freq = gpu_freq;
1369 sandybridge_pcode_read(dev_priv,
1370 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1371 &ia_freq);
1372 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1373 gpu_freq * GT_FREQUENCY_MULTIPLIER,
1374 ((ia_freq >> 0) & 0xff) * 100,
1375 ((ia_freq >> 8) & 0xff) * 100);
1376 }
1377
1378 mutex_unlock(&dev_priv->rps.hw_lock);
1379
1380 return 0;
1381 }
1382
1383 static int i915_gfxec(struct seq_file *m, void *unused)
1384 {
1385 struct drm_info_node *node = (struct drm_info_node *) m->private;
1386 struct drm_device *dev = node->minor->dev;
1387 drm_i915_private_t *dev_priv = dev->dev_private;
1388 int ret;
1389
1390 ret = mutex_lock_interruptible(&dev->struct_mutex);
1391 if (ret)
1392 return ret;
1393
1394 seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1395
1396 mutex_unlock(&dev->struct_mutex);
1397
1398 return 0;
1399 }
1400
1401 static int i915_opregion(struct seq_file *m, void *unused)
1402 {
1403 struct drm_info_node *node = (struct drm_info_node *) m->private;
1404 struct drm_device *dev = node->minor->dev;
1405 drm_i915_private_t *dev_priv = dev->dev_private;
1406 struct intel_opregion *opregion = &dev_priv->opregion;
1407 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1408 int ret;
1409
1410 if (data == NULL)
1411 return -ENOMEM;
1412
1413 ret = mutex_lock_interruptible(&dev->struct_mutex);
1414 if (ret)
1415 goto out;
1416
1417 if (opregion->header) {
1418 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1419 seq_write(m, data, OPREGION_SIZE);
1420 }
1421
1422 mutex_unlock(&dev->struct_mutex);
1423
1424 out:
1425 kfree(data);
1426 return 0;
1427 }
1428
1429 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1430 {
1431 struct drm_info_node *node = (struct drm_info_node *) m->private;
1432 struct drm_device *dev = node->minor->dev;
1433 struct intel_fbdev *ifbdev = NULL;
1434 struct intel_framebuffer *fb;
1435
1436 #ifdef CONFIG_DRM_I915_FBDEV
1437 struct drm_i915_private *dev_priv = dev->dev_private;
1438 int ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1439 if (ret)
1440 return ret;
1441
1442 ifbdev = dev_priv->fbdev;
1443 fb = to_intel_framebuffer(ifbdev->helper.fb);
1444
1445 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1446 fb->base.width,
1447 fb->base.height,
1448 fb->base.depth,
1449 fb->base.bits_per_pixel,
1450 atomic_read(&fb->base.refcount.refcount));
1451 describe_obj(m, fb->obj);
1452 seq_putc(m, '\n');
1453 mutex_unlock(&dev->mode_config.mutex);
1454 #endif
1455
1456 mutex_lock(&dev->mode_config.fb_lock);
1457 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1458 if (ifbdev && &fb->base == ifbdev->helper.fb)
1459 continue;
1460
1461 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1462 fb->base.width,
1463 fb->base.height,
1464 fb->base.depth,
1465 fb->base.bits_per_pixel,
1466 atomic_read(&fb->base.refcount.refcount));
1467 describe_obj(m, fb->obj);
1468 seq_putc(m, '\n');
1469 }
1470 mutex_unlock(&dev->mode_config.fb_lock);
1471
1472 return 0;
1473 }
1474
1475 static int i915_context_status(struct seq_file *m, void *unused)
1476 {
1477 struct drm_info_node *node = (struct drm_info_node *) m->private;
1478 struct drm_device *dev = node->minor->dev;
1479 drm_i915_private_t *dev_priv = dev->dev_private;
1480 struct intel_ring_buffer *ring;
1481 struct i915_hw_context *ctx;
1482 int ret, i;
1483
1484 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1485 if (ret)
1486 return ret;
1487
1488 if (dev_priv->ips.pwrctx) {
1489 seq_puts(m, "power context ");
1490 describe_obj(m, dev_priv->ips.pwrctx);
1491 seq_putc(m, '\n');
1492 }
1493
1494 if (dev_priv->ips.renderctx) {
1495 seq_puts(m, "render context ");
1496 describe_obj(m, dev_priv->ips.renderctx);
1497 seq_putc(m, '\n');
1498 }
1499
1500 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1501 seq_puts(m, "HW context ");
1502 describe_ctx(m, ctx);
1503 for_each_ring(ring, dev_priv, i)
1504 if (ring->default_context == ctx)
1505 seq_printf(m, "(default context %s) ", ring->name);
1506
1507 describe_obj(m, ctx->obj);
1508 seq_putc(m, '\n');
1509 }
1510
1511 mutex_unlock(&dev->mode_config.mutex);
1512
1513 return 0;
1514 }
1515
1516 static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1517 {
1518 struct drm_info_node *node = (struct drm_info_node *) m->private;
1519 struct drm_device *dev = node->minor->dev;
1520 struct drm_i915_private *dev_priv = dev->dev_private;
1521 unsigned forcewake_count;
1522
1523 spin_lock_irq(&dev_priv->uncore.lock);
1524 forcewake_count = dev_priv->uncore.forcewake_count;
1525 spin_unlock_irq(&dev_priv->uncore.lock);
1526
1527 seq_printf(m, "forcewake count = %u\n", forcewake_count);
1528
1529 return 0;
1530 }
1531
1532 static const char *swizzle_string(unsigned swizzle)
1533 {
1534 switch (swizzle) {
1535 case I915_BIT_6_SWIZZLE_NONE:
1536 return "none";
1537 case I915_BIT_6_SWIZZLE_9:
1538 return "bit9";
1539 case I915_BIT_6_SWIZZLE_9_10:
1540 return "bit9/bit10";
1541 case I915_BIT_6_SWIZZLE_9_11:
1542 return "bit9/bit11";
1543 case I915_BIT_6_SWIZZLE_9_10_11:
1544 return "bit9/bit10/bit11";
1545 case I915_BIT_6_SWIZZLE_9_17:
1546 return "bit9/bit17";
1547 case I915_BIT_6_SWIZZLE_9_10_17:
1548 return "bit9/bit10/bit17";
1549 case I915_BIT_6_SWIZZLE_UNKNOWN:
1550 return "unknown";
1551 }
1552
1553 return "bug";
1554 }
1555
1556 static int i915_swizzle_info(struct seq_file *m, void *data)
1557 {
1558 struct drm_info_node *node = (struct drm_info_node *) m->private;
1559 struct drm_device *dev = node->minor->dev;
1560 struct drm_i915_private *dev_priv = dev->dev_private;
1561 int ret;
1562
1563 ret = mutex_lock_interruptible(&dev->struct_mutex);
1564 if (ret)
1565 return ret;
1566
1567 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1568 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1569 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1570 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1571
1572 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1573 seq_printf(m, "DDC = 0x%08x\n",
1574 I915_READ(DCC));
1575 seq_printf(m, "C0DRB3 = 0x%04x\n",
1576 I915_READ16(C0DRB3));
1577 seq_printf(m, "C1DRB3 = 0x%04x\n",
1578 I915_READ16(C1DRB3));
1579 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1580 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1581 I915_READ(MAD_DIMM_C0));
1582 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1583 I915_READ(MAD_DIMM_C1));
1584 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1585 I915_READ(MAD_DIMM_C2));
1586 seq_printf(m, "TILECTL = 0x%08x\n",
1587 I915_READ(TILECTL));
1588 seq_printf(m, "ARB_MODE = 0x%08x\n",
1589 I915_READ(ARB_MODE));
1590 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1591 I915_READ(DISP_ARB_CTL));
1592 }
1593 mutex_unlock(&dev->struct_mutex);
1594
1595 return 0;
1596 }
1597
1598 static int i915_ppgtt_info(struct seq_file *m, void *data)
1599 {
1600 struct drm_info_node *node = (struct drm_info_node *) m->private;
1601 struct drm_device *dev = node->minor->dev;
1602 struct drm_i915_private *dev_priv = dev->dev_private;
1603 struct intel_ring_buffer *ring;
1604 int i, ret;
1605
1606
1607 ret = mutex_lock_interruptible(&dev->struct_mutex);
1608 if (ret)
1609 return ret;
1610 if (INTEL_INFO(dev)->gen == 6)
1611 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1612
1613 for_each_ring(ring, dev_priv, i) {
1614 seq_printf(m, "%s\n", ring->name);
1615 if (INTEL_INFO(dev)->gen == 7)
1616 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1617 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1618 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1619 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1620 }
1621 if (dev_priv->mm.aliasing_ppgtt) {
1622 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1623
1624 seq_puts(m, "aliasing PPGTT:\n");
1625 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1626 }
1627 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
1628 mutex_unlock(&dev->struct_mutex);
1629
1630 return 0;
1631 }
1632
1633 static int i915_dpio_info(struct seq_file *m, void *data)
1634 {
1635 struct drm_info_node *node = (struct drm_info_node *) m->private;
1636 struct drm_device *dev = node->minor->dev;
1637 struct drm_i915_private *dev_priv = dev->dev_private;
1638 int ret;
1639
1640
1641 if (!IS_VALLEYVIEW(dev)) {
1642 seq_puts(m, "unsupported\n");
1643 return 0;
1644 }
1645
1646 ret = mutex_lock_interruptible(&dev_priv->dpio_lock);
1647 if (ret)
1648 return ret;
1649
1650 seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
1651
1652 seq_printf(m, "DPIO PLL DW3 CH0 : 0x%08x\n",
1653 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(0)));
1654 seq_printf(m, "DPIO PLL DW3 CH1: 0x%08x\n",
1655 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(1)));
1656
1657 seq_printf(m, "DPIO PLL DW5 CH0: 0x%08x\n",
1658 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(0)));
1659 seq_printf(m, "DPIO PLL DW5 CH1: 0x%08x\n",
1660 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(1)));
1661
1662 seq_printf(m, "DPIO PLL DW7 CH0: 0x%08x\n",
1663 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(0)));
1664 seq_printf(m, "DPIO PLL DW7 CH1: 0x%08x\n",
1665 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(1)));
1666
1667 seq_printf(m, "DPIO PLL DW10 CH0: 0x%08x\n",
1668 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW10(0)));
1669 seq_printf(m, "DPIO PLL DW10 CH1: 0x%08x\n",
1670 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW10(1)));
1671
1672 seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
1673 vlv_dpio_read(dev_priv, PIPE_A, VLV_CMN_DW0));
1674
1675 mutex_unlock(&dev_priv->dpio_lock);
1676
1677 return 0;
1678 }
1679
1680 static int i915_llc(struct seq_file *m, void *data)
1681 {
1682 struct drm_info_node *node = (struct drm_info_node *) m->private;
1683 struct drm_device *dev = node->minor->dev;
1684 struct drm_i915_private *dev_priv = dev->dev_private;
1685
1686 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
1687 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
1688 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
1689
1690 return 0;
1691 }
1692
1693 static int i915_edp_psr_status(struct seq_file *m, void *data)
1694 {
1695 struct drm_info_node *node = m->private;
1696 struct drm_device *dev = node->minor->dev;
1697 struct drm_i915_private *dev_priv = dev->dev_private;
1698 u32 psrperf = 0;
1699 bool enabled = false;
1700
1701 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
1702 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
1703
1704 enabled = HAS_PSR(dev) &&
1705 I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1706 seq_printf(m, "Enabled: %s\n", yesno(enabled));
1707
1708 if (HAS_PSR(dev))
1709 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
1710 EDP_PSR_PERF_CNT_MASK;
1711 seq_printf(m, "Performance_Counter: %u\n", psrperf);
1712
1713 return 0;
1714 }
1715
1716 static int i915_energy_uJ(struct seq_file *m, void *data)
1717 {
1718 struct drm_info_node *node = m->private;
1719 struct drm_device *dev = node->minor->dev;
1720 struct drm_i915_private *dev_priv = dev->dev_private;
1721 u64 power;
1722 u32 units;
1723
1724 if (INTEL_INFO(dev)->gen < 6)
1725 return -ENODEV;
1726
1727 rdmsrl(MSR_RAPL_POWER_UNIT, power);
1728 power = (power & 0x1f00) >> 8;
1729 units = 1000000 / (1 << power); /* convert to uJ */
1730 power = I915_READ(MCH_SECP_NRG_STTS);
1731 power *= units;
1732
1733 seq_printf(m, "%llu", (long long unsigned)power);
1734
1735 return 0;
1736 }
1737
1738 static int i915_pc8_status(struct seq_file *m, void *unused)
1739 {
1740 struct drm_info_node *node = (struct drm_info_node *) m->private;
1741 struct drm_device *dev = node->minor->dev;
1742 struct drm_i915_private *dev_priv = dev->dev_private;
1743
1744 if (!IS_HASWELL(dev)) {
1745 seq_puts(m, "not supported\n");
1746 return 0;
1747 }
1748
1749 mutex_lock(&dev_priv->pc8.lock);
1750 seq_printf(m, "Requirements met: %s\n",
1751 yesno(dev_priv->pc8.requirements_met));
1752 seq_printf(m, "GPU idle: %s\n", yesno(dev_priv->pc8.gpu_idle));
1753 seq_printf(m, "Disable count: %d\n", dev_priv->pc8.disable_count);
1754 seq_printf(m, "IRQs disabled: %s\n",
1755 yesno(dev_priv->pc8.irqs_disabled));
1756 seq_printf(m, "Enabled: %s\n", yesno(dev_priv->pc8.enabled));
1757 mutex_unlock(&dev_priv->pc8.lock);
1758
1759 return 0;
1760 }
1761
1762 struct pipe_crc_info {
1763 const char *name;
1764 struct drm_device *dev;
1765 enum pipe pipe;
1766 };
1767
1768 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
1769 {
1770 struct pipe_crc_info *info = inode->i_private;
1771 struct drm_i915_private *dev_priv = info->dev->dev_private;
1772 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
1773
1774 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
1775 return -ENODEV;
1776
1777 spin_lock_irq(&pipe_crc->lock);
1778
1779 if (pipe_crc->opened) {
1780 spin_unlock_irq(&pipe_crc->lock);
1781 return -EBUSY; /* already open */
1782 }
1783
1784 pipe_crc->opened = true;
1785 filep->private_data = inode->i_private;
1786
1787 spin_unlock_irq(&pipe_crc->lock);
1788
1789 return 0;
1790 }
1791
1792 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
1793 {
1794 struct pipe_crc_info *info = inode->i_private;
1795 struct drm_i915_private *dev_priv = info->dev->dev_private;
1796 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
1797
1798 spin_lock_irq(&pipe_crc->lock);
1799 pipe_crc->opened = false;
1800 spin_unlock_irq(&pipe_crc->lock);
1801
1802 return 0;
1803 }
1804
1805 /* (6 fields, 8 chars each, space separated (5) + '\n') */
1806 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
1807 /* account for \'0' */
1808 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
1809
1810 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
1811 {
1812 assert_spin_locked(&pipe_crc->lock);
1813 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
1814 INTEL_PIPE_CRC_ENTRIES_NR);
1815 }
1816
1817 static ssize_t
1818 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
1819 loff_t *pos)
1820 {
1821 struct pipe_crc_info *info = filep->private_data;
1822 struct drm_device *dev = info->dev;
1823 struct drm_i915_private *dev_priv = dev->dev_private;
1824 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
1825 char buf[PIPE_CRC_BUFFER_LEN];
1826 int head, tail, n_entries, n;
1827 ssize_t bytes_read;
1828
1829 /*
1830 * Don't allow user space to provide buffers not big enough to hold
1831 * a line of data.
1832 */
1833 if (count < PIPE_CRC_LINE_LEN)
1834 return -EINVAL;
1835
1836 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
1837 return 0;
1838
1839 /* nothing to read */
1840 spin_lock_irq(&pipe_crc->lock);
1841 while (pipe_crc_data_count(pipe_crc) == 0) {
1842 int ret;
1843
1844 if (filep->f_flags & O_NONBLOCK) {
1845 spin_unlock_irq(&pipe_crc->lock);
1846 return -EAGAIN;
1847 }
1848
1849 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
1850 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
1851 if (ret) {
1852 spin_unlock_irq(&pipe_crc->lock);
1853 return ret;
1854 }
1855 }
1856
1857 /* We now have one or more entries to read */
1858 head = pipe_crc->head;
1859 tail = pipe_crc->tail;
1860 n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR),
1861 count / PIPE_CRC_LINE_LEN);
1862 spin_unlock_irq(&pipe_crc->lock);
1863
1864 bytes_read = 0;
1865 n = 0;
1866 do {
1867 struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail];
1868 int ret;
1869
1870 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
1871 "%8u %8x %8x %8x %8x %8x\n",
1872 entry->frame, entry->crc[0],
1873 entry->crc[1], entry->crc[2],
1874 entry->crc[3], entry->crc[4]);
1875
1876 ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN,
1877 buf, PIPE_CRC_LINE_LEN);
1878 if (ret == PIPE_CRC_LINE_LEN)
1879 return -EFAULT;
1880
1881 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
1882 tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1883 n++;
1884 } while (--n_entries);
1885
1886 spin_lock_irq(&pipe_crc->lock);
1887 pipe_crc->tail = tail;
1888 spin_unlock_irq(&pipe_crc->lock);
1889
1890 return bytes_read;
1891 }
1892
1893 static const struct file_operations i915_pipe_crc_fops = {
1894 .owner = THIS_MODULE,
1895 .open = i915_pipe_crc_open,
1896 .read = i915_pipe_crc_read,
1897 .release = i915_pipe_crc_release,
1898 };
1899
1900 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
1901 {
1902 .name = "i915_pipe_A_crc",
1903 .pipe = PIPE_A,
1904 },
1905 {
1906 .name = "i915_pipe_B_crc",
1907 .pipe = PIPE_B,
1908 },
1909 {
1910 .name = "i915_pipe_C_crc",
1911 .pipe = PIPE_C,
1912 },
1913 };
1914
1915 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
1916 enum pipe pipe)
1917 {
1918 struct drm_device *dev = minor->dev;
1919 struct dentry *ent;
1920 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
1921
1922 info->dev = dev;
1923 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
1924 &i915_pipe_crc_fops);
1925 if (IS_ERR(ent))
1926 return PTR_ERR(ent);
1927
1928 return drm_add_fake_info_node(minor, ent, info);
1929 }
1930
1931 static const char * const pipe_crc_sources[] = {
1932 "none",
1933 "plane1",
1934 "plane2",
1935 "pf",
1936 "pipe",
1937 "TV",
1938 "DP-B",
1939 "DP-C",
1940 "DP-D",
1941 "auto",
1942 };
1943
1944 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
1945 {
1946 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
1947 return pipe_crc_sources[source];
1948 }
1949
1950 static int display_crc_ctl_show(struct seq_file *m, void *data)
1951 {
1952 struct drm_device *dev = m->private;
1953 struct drm_i915_private *dev_priv = dev->dev_private;
1954 int i;
1955
1956 for (i = 0; i < I915_MAX_PIPES; i++)
1957 seq_printf(m, "%c %s\n", pipe_name(i),
1958 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
1959
1960 return 0;
1961 }
1962
1963 static int display_crc_ctl_open(struct inode *inode, struct file *file)
1964 {
1965 struct drm_device *dev = inode->i_private;
1966
1967 return single_open(file, display_crc_ctl_show, dev);
1968 }
1969
1970 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
1971 uint32_t *val)
1972 {
1973 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
1974 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
1975
1976 switch (*source) {
1977 case INTEL_PIPE_CRC_SOURCE_PIPE:
1978 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
1979 break;
1980 case INTEL_PIPE_CRC_SOURCE_NONE:
1981 *val = 0;
1982 break;
1983 default:
1984 return -EINVAL;
1985 }
1986
1987 return 0;
1988 }
1989
1990 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
1991 enum intel_pipe_crc_source *source)
1992 {
1993 struct intel_encoder *encoder;
1994 struct intel_crtc *crtc;
1995 struct intel_digital_port *dig_port;
1996 int ret = 0;
1997
1998 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
1999
2000 mutex_lock(&dev->mode_config.mutex);
2001 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2002 base.head) {
2003 if (!encoder->base.crtc)
2004 continue;
2005
2006 crtc = to_intel_crtc(encoder->base.crtc);
2007
2008 if (crtc->pipe != pipe)
2009 continue;
2010
2011 switch (encoder->type) {
2012 case INTEL_OUTPUT_TVOUT:
2013 *source = INTEL_PIPE_CRC_SOURCE_TV;
2014 break;
2015 case INTEL_OUTPUT_DISPLAYPORT:
2016 case INTEL_OUTPUT_EDP:
2017 dig_port = enc_to_dig_port(&encoder->base);
2018 switch (dig_port->port) {
2019 case PORT_B:
2020 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
2021 break;
2022 case PORT_C:
2023 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
2024 break;
2025 case PORT_D:
2026 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
2027 break;
2028 default:
2029 WARN(1, "nonexisting DP port %c\n",
2030 port_name(dig_port->port));
2031 break;
2032 }
2033 break;
2034 }
2035 }
2036 mutex_unlock(&dev->mode_config.mutex);
2037
2038 return ret;
2039 }
2040
2041 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
2042 enum pipe pipe,
2043 enum intel_pipe_crc_source *source,
2044 uint32_t *val)
2045 {
2046 struct drm_i915_private *dev_priv = dev->dev_private;
2047 bool need_stable_symbols = false;
2048
2049 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2050 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2051 if (ret)
2052 return ret;
2053 }
2054
2055 switch (*source) {
2056 case INTEL_PIPE_CRC_SOURCE_PIPE:
2057 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
2058 break;
2059 case INTEL_PIPE_CRC_SOURCE_DP_B:
2060 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
2061 need_stable_symbols = true;
2062 break;
2063 case INTEL_PIPE_CRC_SOURCE_DP_C:
2064 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
2065 need_stable_symbols = true;
2066 break;
2067 case INTEL_PIPE_CRC_SOURCE_NONE:
2068 *val = 0;
2069 break;
2070 default:
2071 return -EINVAL;
2072 }
2073
2074 /*
2075 * When the pipe CRC tap point is after the transcoders we need
2076 * to tweak symbol-level features to produce a deterministic series of
2077 * symbols for a given frame. We need to reset those features only once
2078 * a frame (instead of every nth symbol):
2079 * - DC-balance: used to ensure a better clock recovery from the data
2080 * link (SDVO)
2081 * - DisplayPort scrambling: used for EMI reduction
2082 */
2083 if (need_stable_symbols) {
2084 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2085
2086 WARN_ON(!IS_G4X(dev));
2087
2088 tmp |= DC_BALANCE_RESET_VLV;
2089 if (pipe == PIPE_A)
2090 tmp |= PIPE_A_SCRAMBLE_RESET;
2091 else
2092 tmp |= PIPE_B_SCRAMBLE_RESET;
2093
2094 I915_WRITE(PORT_DFT2_G4X, tmp);
2095 }
2096
2097 return 0;
2098 }
2099
2100 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
2101 enum pipe pipe,
2102 enum intel_pipe_crc_source *source,
2103 uint32_t *val)
2104 {
2105 struct drm_i915_private *dev_priv = dev->dev_private;
2106 bool need_stable_symbols = false;
2107
2108 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2109 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2110 if (ret)
2111 return ret;
2112 }
2113
2114 switch (*source) {
2115 case INTEL_PIPE_CRC_SOURCE_PIPE:
2116 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
2117 break;
2118 case INTEL_PIPE_CRC_SOURCE_TV:
2119 if (!SUPPORTS_TV(dev))
2120 return -EINVAL;
2121 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
2122 break;
2123 case INTEL_PIPE_CRC_SOURCE_DP_B:
2124 if (!IS_G4X(dev))
2125 return -EINVAL;
2126 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
2127 need_stable_symbols = true;
2128 break;
2129 case INTEL_PIPE_CRC_SOURCE_DP_C:
2130 if (!IS_G4X(dev))
2131 return -EINVAL;
2132 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
2133 need_stable_symbols = true;
2134 break;
2135 case INTEL_PIPE_CRC_SOURCE_DP_D:
2136 if (!IS_G4X(dev))
2137 return -EINVAL;
2138 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
2139 need_stable_symbols = true;
2140 break;
2141 case INTEL_PIPE_CRC_SOURCE_NONE:
2142 *val = 0;
2143 break;
2144 default:
2145 return -EINVAL;
2146 }
2147
2148 /*
2149 * When the pipe CRC tap point is after the transcoders we need
2150 * to tweak symbol-level features to produce a deterministic series of
2151 * symbols for a given frame. We need to reset those features only once
2152 * a frame (instead of every nth symbol):
2153 * - DC-balance: used to ensure a better clock recovery from the data
2154 * link (SDVO)
2155 * - DisplayPort scrambling: used for EMI reduction
2156 */
2157 if (need_stable_symbols) {
2158 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2159
2160 WARN_ON(!IS_G4X(dev));
2161
2162 I915_WRITE(PORT_DFT_I9XX,
2163 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
2164
2165 if (pipe == PIPE_A)
2166 tmp |= PIPE_A_SCRAMBLE_RESET;
2167 else
2168 tmp |= PIPE_B_SCRAMBLE_RESET;
2169
2170 I915_WRITE(PORT_DFT2_G4X, tmp);
2171 }
2172
2173 return 0;
2174 }
2175
2176 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
2177 enum pipe pipe)
2178 {
2179 struct drm_i915_private *dev_priv = dev->dev_private;
2180 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2181
2182 if (pipe == PIPE_A)
2183 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2184 else
2185 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2186 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
2187 tmp &= ~DC_BALANCE_RESET_VLV;
2188 I915_WRITE(PORT_DFT2_G4X, tmp);
2189
2190 }
2191
2192 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
2193 enum pipe pipe)
2194 {
2195 struct drm_i915_private *dev_priv = dev->dev_private;
2196 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2197
2198 if (pipe == PIPE_A)
2199 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2200 else
2201 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2202 I915_WRITE(PORT_DFT2_G4X, tmp);
2203
2204 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
2205 I915_WRITE(PORT_DFT_I9XX,
2206 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
2207 }
2208 }
2209
2210 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
2211 uint32_t *val)
2212 {
2213 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2214 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2215
2216 switch (*source) {
2217 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2218 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
2219 break;
2220 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2221 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
2222 break;
2223 case INTEL_PIPE_CRC_SOURCE_PIPE:
2224 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
2225 break;
2226 case INTEL_PIPE_CRC_SOURCE_NONE:
2227 *val = 0;
2228 break;
2229 default:
2230 return -EINVAL;
2231 }
2232
2233 return 0;
2234 }
2235
2236 static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
2237 uint32_t *val)
2238 {
2239 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2240 *source = INTEL_PIPE_CRC_SOURCE_PF;
2241
2242 switch (*source) {
2243 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2244 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
2245 break;
2246 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2247 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
2248 break;
2249 case INTEL_PIPE_CRC_SOURCE_PF:
2250 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
2251 break;
2252 case INTEL_PIPE_CRC_SOURCE_NONE:
2253 *val = 0;
2254 break;
2255 default:
2256 return -EINVAL;
2257 }
2258
2259 return 0;
2260 }
2261
2262 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
2263 enum intel_pipe_crc_source source)
2264 {
2265 struct drm_i915_private *dev_priv = dev->dev_private;
2266 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
2267 u32 val;
2268 int ret;
2269
2270 if (pipe_crc->source == source)
2271 return 0;
2272
2273 /* forbid changing the source without going back to 'none' */
2274 if (pipe_crc->source && source)
2275 return -EINVAL;
2276
2277 if (IS_GEN2(dev))
2278 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
2279 else if (INTEL_INFO(dev)->gen < 5)
2280 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
2281 else if (IS_VALLEYVIEW(dev))
2282 ret = vlv_pipe_crc_ctl_reg(dev,pipe, &source, &val);
2283 else if (IS_GEN5(dev) || IS_GEN6(dev))
2284 ret = ilk_pipe_crc_ctl_reg(&source, &val);
2285 else
2286 ret = ivb_pipe_crc_ctl_reg(&source, &val);
2287
2288 if (ret != 0)
2289 return ret;
2290
2291 /* none -> real source transition */
2292 if (source) {
2293 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
2294 pipe_name(pipe), pipe_crc_source_name(source));
2295
2296 pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) *
2297 INTEL_PIPE_CRC_ENTRIES_NR,
2298 GFP_KERNEL);
2299 if (!pipe_crc->entries)
2300 return -ENOMEM;
2301
2302 spin_lock_irq(&pipe_crc->lock);
2303 pipe_crc->head = 0;
2304 pipe_crc->tail = 0;
2305 spin_unlock_irq(&pipe_crc->lock);
2306 }
2307
2308 pipe_crc->source = source;
2309
2310 I915_WRITE(PIPE_CRC_CTL(pipe), val);
2311 POSTING_READ(PIPE_CRC_CTL(pipe));
2312
2313 /* real source -> none transition */
2314 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
2315 struct intel_pipe_crc_entry *entries;
2316
2317 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
2318 pipe_name(pipe));
2319
2320 intel_wait_for_vblank(dev, pipe);
2321
2322 spin_lock_irq(&pipe_crc->lock);
2323 entries = pipe_crc->entries;
2324 pipe_crc->entries = NULL;
2325 spin_unlock_irq(&pipe_crc->lock);
2326
2327 kfree(entries);
2328
2329 if (IS_G4X(dev))
2330 g4x_undo_pipe_scramble_reset(dev, pipe);
2331 else if (IS_VALLEYVIEW(dev))
2332 vlv_undo_pipe_scramble_reset(dev, pipe);
2333 }
2334
2335 return 0;
2336 }
2337
2338 /*
2339 * Parse pipe CRC command strings:
2340 * command: wsp* object wsp+ name wsp+ source wsp*
2341 * object: 'pipe'
2342 * name: (A | B | C)
2343 * source: (none | plane1 | plane2 | pf)
2344 * wsp: (#0x20 | #0x9 | #0xA)+
2345 *
2346 * eg.:
2347 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
2348 * "pipe A none" -> Stop CRC
2349 */
2350 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
2351 {
2352 int n_words = 0;
2353
2354 while (*buf) {
2355 char *end;
2356
2357 /* skip leading white space */
2358 buf = skip_spaces(buf);
2359 if (!*buf)
2360 break; /* end of buffer */
2361
2362 /* find end of word */
2363 for (end = buf; *end && !isspace(*end); end++)
2364 ;
2365
2366 if (n_words == max_words) {
2367 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
2368 max_words);
2369 return -EINVAL; /* ran out of words[] before bytes */
2370 }
2371
2372 if (*end)
2373 *end++ = '\0';
2374 words[n_words++] = buf;
2375 buf = end;
2376 }
2377
2378 return n_words;
2379 }
2380
2381 enum intel_pipe_crc_object {
2382 PIPE_CRC_OBJECT_PIPE,
2383 };
2384
2385 static const char * const pipe_crc_objects[] = {
2386 "pipe",
2387 };
2388
2389 static int
2390 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
2391 {
2392 int i;
2393
2394 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
2395 if (!strcmp(buf, pipe_crc_objects[i])) {
2396 *o = i;
2397 return 0;
2398 }
2399
2400 return -EINVAL;
2401 }
2402
2403 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
2404 {
2405 const char name = buf[0];
2406
2407 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
2408 return -EINVAL;
2409
2410 *pipe = name - 'A';
2411
2412 return 0;
2413 }
2414
2415 static int
2416 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
2417 {
2418 int i;
2419
2420 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
2421 if (!strcmp(buf, pipe_crc_sources[i])) {
2422 *s = i;
2423 return 0;
2424 }
2425
2426 return -EINVAL;
2427 }
2428
2429 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
2430 {
2431 #define N_WORDS 3
2432 int n_words;
2433 char *words[N_WORDS];
2434 enum pipe pipe;
2435 enum intel_pipe_crc_object object;
2436 enum intel_pipe_crc_source source;
2437
2438 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
2439 if (n_words != N_WORDS) {
2440 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
2441 N_WORDS);
2442 return -EINVAL;
2443 }
2444
2445 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
2446 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
2447 return -EINVAL;
2448 }
2449
2450 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
2451 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
2452 return -EINVAL;
2453 }
2454
2455 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
2456 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
2457 return -EINVAL;
2458 }
2459
2460 return pipe_crc_set_source(dev, pipe, source);
2461 }
2462
2463 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
2464 size_t len, loff_t *offp)
2465 {
2466 struct seq_file *m = file->private_data;
2467 struct drm_device *dev = m->private;
2468 char *tmpbuf;
2469 int ret;
2470
2471 if (len == 0)
2472 return 0;
2473
2474 if (len > PAGE_SIZE - 1) {
2475 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
2476 PAGE_SIZE);
2477 return -E2BIG;
2478 }
2479
2480 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
2481 if (!tmpbuf)
2482 return -ENOMEM;
2483
2484 if (copy_from_user(tmpbuf, ubuf, len)) {
2485 ret = -EFAULT;
2486 goto out;
2487 }
2488 tmpbuf[len] = '\0';
2489
2490 ret = display_crc_ctl_parse(dev, tmpbuf, len);
2491
2492 out:
2493 kfree(tmpbuf);
2494 if (ret < 0)
2495 return ret;
2496
2497 *offp += len;
2498 return len;
2499 }
2500
2501 static const struct file_operations i915_display_crc_ctl_fops = {
2502 .owner = THIS_MODULE,
2503 .open = display_crc_ctl_open,
2504 .read = seq_read,
2505 .llseek = seq_lseek,
2506 .release = single_release,
2507 .write = display_crc_ctl_write
2508 };
2509
2510 static int
2511 i915_wedged_get(void *data, u64 *val)
2512 {
2513 struct drm_device *dev = data;
2514 drm_i915_private_t *dev_priv = dev->dev_private;
2515
2516 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
2517
2518 return 0;
2519 }
2520
2521 static int
2522 i915_wedged_set(void *data, u64 val)
2523 {
2524 struct drm_device *dev = data;
2525
2526 DRM_INFO("Manually setting wedged to %llu\n", val);
2527 i915_handle_error(dev, val);
2528
2529 return 0;
2530 }
2531
2532 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
2533 i915_wedged_get, i915_wedged_set,
2534 "%llu\n");
2535
2536 static int
2537 i915_ring_stop_get(void *data, u64 *val)
2538 {
2539 struct drm_device *dev = data;
2540 drm_i915_private_t *dev_priv = dev->dev_private;
2541
2542 *val = dev_priv->gpu_error.stop_rings;
2543
2544 return 0;
2545 }
2546
2547 static int
2548 i915_ring_stop_set(void *data, u64 val)
2549 {
2550 struct drm_device *dev = data;
2551 struct drm_i915_private *dev_priv = dev->dev_private;
2552 int ret;
2553
2554 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
2555
2556 ret = mutex_lock_interruptible(&dev->struct_mutex);
2557 if (ret)
2558 return ret;
2559
2560 dev_priv->gpu_error.stop_rings = val;
2561 mutex_unlock(&dev->struct_mutex);
2562
2563 return 0;
2564 }
2565
2566 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
2567 i915_ring_stop_get, i915_ring_stop_set,
2568 "0x%08llx\n");
2569
2570 static int
2571 i915_ring_missed_irq_get(void *data, u64 *val)
2572 {
2573 struct drm_device *dev = data;
2574 struct drm_i915_private *dev_priv = dev->dev_private;
2575
2576 *val = dev_priv->gpu_error.missed_irq_rings;
2577 return 0;
2578 }
2579
2580 static int
2581 i915_ring_missed_irq_set(void *data, u64 val)
2582 {
2583 struct drm_device *dev = data;
2584 struct drm_i915_private *dev_priv = dev->dev_private;
2585 int ret;
2586
2587 /* Lock against concurrent debugfs callers */
2588 ret = mutex_lock_interruptible(&dev->struct_mutex);
2589 if (ret)
2590 return ret;
2591 dev_priv->gpu_error.missed_irq_rings = val;
2592 mutex_unlock(&dev->struct_mutex);
2593
2594 return 0;
2595 }
2596
2597 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
2598 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
2599 "0x%08llx\n");
2600
2601 static int
2602 i915_ring_test_irq_get(void *data, u64 *val)
2603 {
2604 struct drm_device *dev = data;
2605 struct drm_i915_private *dev_priv = dev->dev_private;
2606
2607 *val = dev_priv->gpu_error.test_irq_rings;
2608
2609 return 0;
2610 }
2611
2612 static int
2613 i915_ring_test_irq_set(void *data, u64 val)
2614 {
2615 struct drm_device *dev = data;
2616 struct drm_i915_private *dev_priv = dev->dev_private;
2617 int ret;
2618
2619 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
2620
2621 /* Lock against concurrent debugfs callers */
2622 ret = mutex_lock_interruptible(&dev->struct_mutex);
2623 if (ret)
2624 return ret;
2625
2626 dev_priv->gpu_error.test_irq_rings = val;
2627 mutex_unlock(&dev->struct_mutex);
2628
2629 return 0;
2630 }
2631
2632 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
2633 i915_ring_test_irq_get, i915_ring_test_irq_set,
2634 "0x%08llx\n");
2635
2636 #define DROP_UNBOUND 0x1
2637 #define DROP_BOUND 0x2
2638 #define DROP_RETIRE 0x4
2639 #define DROP_ACTIVE 0x8
2640 #define DROP_ALL (DROP_UNBOUND | \
2641 DROP_BOUND | \
2642 DROP_RETIRE | \
2643 DROP_ACTIVE)
2644 static int
2645 i915_drop_caches_get(void *data, u64 *val)
2646 {
2647 *val = DROP_ALL;
2648
2649 return 0;
2650 }
2651
2652 static int
2653 i915_drop_caches_set(void *data, u64 val)
2654 {
2655 struct drm_device *dev = data;
2656 struct drm_i915_private *dev_priv = dev->dev_private;
2657 struct drm_i915_gem_object *obj, *next;
2658 struct i915_address_space *vm;
2659 struct i915_vma *vma, *x;
2660 int ret;
2661
2662 DRM_DEBUG_DRIVER("Dropping caches: 0x%08llx\n", val);
2663
2664 /* No need to check and wait for gpu resets, only libdrm auto-restarts
2665 * on ioctls on -EAGAIN. */
2666 ret = mutex_lock_interruptible(&dev->struct_mutex);
2667 if (ret)
2668 return ret;
2669
2670 if (val & DROP_ACTIVE) {
2671 ret = i915_gpu_idle(dev);
2672 if (ret)
2673 goto unlock;
2674 }
2675
2676 if (val & (DROP_RETIRE | DROP_ACTIVE))
2677 i915_gem_retire_requests(dev);
2678
2679 if (val & DROP_BOUND) {
2680 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2681 list_for_each_entry_safe(vma, x, &vm->inactive_list,
2682 mm_list) {
2683 if (vma->obj->pin_count)
2684 continue;
2685
2686 ret = i915_vma_unbind(vma);
2687 if (ret)
2688 goto unlock;
2689 }
2690 }
2691 }
2692
2693 if (val & DROP_UNBOUND) {
2694 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
2695 global_list)
2696 if (obj->pages_pin_count == 0) {
2697 ret = i915_gem_object_put_pages(obj);
2698 if (ret)
2699 goto unlock;
2700 }
2701 }
2702
2703 unlock:
2704 mutex_unlock(&dev->struct_mutex);
2705
2706 return ret;
2707 }
2708
2709 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
2710 i915_drop_caches_get, i915_drop_caches_set,
2711 "0x%08llx\n");
2712
2713 static int
2714 i915_max_freq_get(void *data, u64 *val)
2715 {
2716 struct drm_device *dev = data;
2717 drm_i915_private_t *dev_priv = dev->dev_private;
2718 int ret;
2719
2720 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2721 return -ENODEV;
2722
2723 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
2724
2725 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2726 if (ret)
2727 return ret;
2728
2729 if (IS_VALLEYVIEW(dev))
2730 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay);
2731 else
2732 *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
2733 mutex_unlock(&dev_priv->rps.hw_lock);
2734
2735 return 0;
2736 }
2737
2738 static int
2739 i915_max_freq_set(void *data, u64 val)
2740 {
2741 struct drm_device *dev = data;
2742 struct drm_i915_private *dev_priv = dev->dev_private;
2743 int ret;
2744
2745 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2746 return -ENODEV;
2747
2748 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
2749
2750 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
2751
2752 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2753 if (ret)
2754 return ret;
2755
2756 /*
2757 * Turbo will still be enabled, but won't go above the set value.
2758 */
2759 if (IS_VALLEYVIEW(dev)) {
2760 val = vlv_freq_opcode(dev_priv, val);
2761 dev_priv->rps.max_delay = val;
2762 valleyview_set_rps(dev, val);
2763 } else {
2764 do_div(val, GT_FREQUENCY_MULTIPLIER);
2765 dev_priv->rps.max_delay = val;
2766 gen6_set_rps(dev, val);
2767 }
2768
2769 mutex_unlock(&dev_priv->rps.hw_lock);
2770
2771 return 0;
2772 }
2773
2774 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
2775 i915_max_freq_get, i915_max_freq_set,
2776 "%llu\n");
2777
2778 static int
2779 i915_min_freq_get(void *data, u64 *val)
2780 {
2781 struct drm_device *dev = data;
2782 drm_i915_private_t *dev_priv = dev->dev_private;
2783 int ret;
2784
2785 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2786 return -ENODEV;
2787
2788 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
2789
2790 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2791 if (ret)
2792 return ret;
2793
2794 if (IS_VALLEYVIEW(dev))
2795 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay);
2796 else
2797 *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
2798 mutex_unlock(&dev_priv->rps.hw_lock);
2799
2800 return 0;
2801 }
2802
2803 static int
2804 i915_min_freq_set(void *data, u64 val)
2805 {
2806 struct drm_device *dev = data;
2807 struct drm_i915_private *dev_priv = dev->dev_private;
2808 int ret;
2809
2810 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2811 return -ENODEV;
2812
2813 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
2814
2815 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
2816
2817 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2818 if (ret)
2819 return ret;
2820
2821 /*
2822 * Turbo will still be enabled, but won't go below the set value.
2823 */
2824 if (IS_VALLEYVIEW(dev)) {
2825 val = vlv_freq_opcode(dev_priv, val);
2826 dev_priv->rps.min_delay = val;
2827 valleyview_set_rps(dev, val);
2828 } else {
2829 do_div(val, GT_FREQUENCY_MULTIPLIER);
2830 dev_priv->rps.min_delay = val;
2831 gen6_set_rps(dev, val);
2832 }
2833 mutex_unlock(&dev_priv->rps.hw_lock);
2834
2835 return 0;
2836 }
2837
2838 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
2839 i915_min_freq_get, i915_min_freq_set,
2840 "%llu\n");
2841
2842 static int
2843 i915_cache_sharing_get(void *data, u64 *val)
2844 {
2845 struct drm_device *dev = data;
2846 drm_i915_private_t *dev_priv = dev->dev_private;
2847 u32 snpcr;
2848 int ret;
2849
2850 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2851 return -ENODEV;
2852
2853 ret = mutex_lock_interruptible(&dev->struct_mutex);
2854 if (ret)
2855 return ret;
2856
2857 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
2858 mutex_unlock(&dev_priv->dev->struct_mutex);
2859
2860 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
2861
2862 return 0;
2863 }
2864
2865 static int
2866 i915_cache_sharing_set(void *data, u64 val)
2867 {
2868 struct drm_device *dev = data;
2869 struct drm_i915_private *dev_priv = dev->dev_private;
2870 u32 snpcr;
2871
2872 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2873 return -ENODEV;
2874
2875 if (val > 3)
2876 return -EINVAL;
2877
2878 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
2879
2880 /* Update the cache sharing policy here as well */
2881 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
2882 snpcr &= ~GEN6_MBC_SNPCR_MASK;
2883 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
2884 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
2885
2886 return 0;
2887 }
2888
2889 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
2890 i915_cache_sharing_get, i915_cache_sharing_set,
2891 "%llu\n");
2892
2893 static int i915_forcewake_open(struct inode *inode, struct file *file)
2894 {
2895 struct drm_device *dev = inode->i_private;
2896 struct drm_i915_private *dev_priv = dev->dev_private;
2897
2898 if (INTEL_INFO(dev)->gen < 6)
2899 return 0;
2900
2901 gen6_gt_force_wake_get(dev_priv);
2902
2903 return 0;
2904 }
2905
2906 static int i915_forcewake_release(struct inode *inode, struct file *file)
2907 {
2908 struct drm_device *dev = inode->i_private;
2909 struct drm_i915_private *dev_priv = dev->dev_private;
2910
2911 if (INTEL_INFO(dev)->gen < 6)
2912 return 0;
2913
2914 gen6_gt_force_wake_put(dev_priv);
2915
2916 return 0;
2917 }
2918
2919 static const struct file_operations i915_forcewake_fops = {
2920 .owner = THIS_MODULE,
2921 .open = i915_forcewake_open,
2922 .release = i915_forcewake_release,
2923 };
2924
2925 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
2926 {
2927 struct drm_device *dev = minor->dev;
2928 struct dentry *ent;
2929
2930 ent = debugfs_create_file("i915_forcewake_user",
2931 S_IRUSR,
2932 root, dev,
2933 &i915_forcewake_fops);
2934 if (IS_ERR(ent))
2935 return PTR_ERR(ent);
2936
2937 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
2938 }
2939
2940 static int i915_debugfs_create(struct dentry *root,
2941 struct drm_minor *minor,
2942 const char *name,
2943 const struct file_operations *fops)
2944 {
2945 struct drm_device *dev = minor->dev;
2946 struct dentry *ent;
2947
2948 ent = debugfs_create_file(name,
2949 S_IRUGO | S_IWUSR,
2950 root, dev,
2951 fops);
2952 if (IS_ERR(ent))
2953 return PTR_ERR(ent);
2954
2955 return drm_add_fake_info_node(minor, ent, fops);
2956 }
2957
2958 static struct drm_info_list i915_debugfs_list[] = {
2959 {"i915_capabilities", i915_capabilities, 0},
2960 {"i915_gem_objects", i915_gem_object_info, 0},
2961 {"i915_gem_gtt", i915_gem_gtt_info, 0},
2962 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
2963 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
2964 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
2965 {"i915_gem_stolen", i915_gem_stolen_list_info },
2966 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2967 {"i915_gem_request", i915_gem_request_info, 0},
2968 {"i915_gem_seqno", i915_gem_seqno_info, 0},
2969 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2970 {"i915_gem_interrupt", i915_interrupt_info, 0},
2971 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
2972 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
2973 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
2974 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
2975 {"i915_rstdby_delays", i915_rstdby_delays, 0},
2976 {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
2977 {"i915_delayfreq_table", i915_delayfreq_table, 0},
2978 {"i915_inttoext_table", i915_inttoext_table, 0},
2979 {"i915_drpc_info", i915_drpc_info, 0},
2980 {"i915_emon_status", i915_emon_status, 0},
2981 {"i915_ring_freq_table", i915_ring_freq_table, 0},
2982 {"i915_gfxec", i915_gfxec, 0},
2983 {"i915_fbc_status", i915_fbc_status, 0},
2984 {"i915_ips_status", i915_ips_status, 0},
2985 {"i915_sr_status", i915_sr_status, 0},
2986 {"i915_opregion", i915_opregion, 0},
2987 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
2988 {"i915_context_status", i915_context_status, 0},
2989 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
2990 {"i915_swizzle_info", i915_swizzle_info, 0},
2991 {"i915_ppgtt_info", i915_ppgtt_info, 0},
2992 {"i915_dpio", i915_dpio_info, 0},
2993 {"i915_llc", i915_llc, 0},
2994 {"i915_edp_psr_status", i915_edp_psr_status, 0},
2995 {"i915_energy_uJ", i915_energy_uJ, 0},
2996 {"i915_pc8_status", i915_pc8_status, 0},
2997 };
2998 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2999
3000 static struct i915_debugfs_files {
3001 const char *name;
3002 const struct file_operations *fops;
3003 } i915_debugfs_files[] = {
3004 {"i915_wedged", &i915_wedged_fops},
3005 {"i915_max_freq", &i915_max_freq_fops},
3006 {"i915_min_freq", &i915_min_freq_fops},
3007 {"i915_cache_sharing", &i915_cache_sharing_fops},
3008 {"i915_ring_stop", &i915_ring_stop_fops},
3009 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
3010 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
3011 {"i915_gem_drop_caches", &i915_drop_caches_fops},
3012 {"i915_error_state", &i915_error_state_fops},
3013 {"i915_next_seqno", &i915_next_seqno_fops},
3014 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
3015 };
3016
3017 void intel_display_crc_init(struct drm_device *dev)
3018 {
3019 struct drm_i915_private *dev_priv = dev->dev_private;
3020 enum pipe pipe;
3021
3022 for_each_pipe(pipe) {
3023 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3024
3025 pipe_crc->opened = false;
3026 spin_lock_init(&pipe_crc->lock);
3027 init_waitqueue_head(&pipe_crc->wq);
3028 }
3029 }
3030
3031 int i915_debugfs_init(struct drm_minor *minor)
3032 {
3033 int ret, i;
3034
3035 ret = i915_forcewake_create(minor->debugfs_root, minor);
3036 if (ret)
3037 return ret;
3038
3039 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
3040 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
3041 if (ret)
3042 return ret;
3043 }
3044
3045 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3046 ret = i915_debugfs_create(minor->debugfs_root, minor,
3047 i915_debugfs_files[i].name,
3048 i915_debugfs_files[i].fops);
3049 if (ret)
3050 return ret;
3051 }
3052
3053 return drm_debugfs_create_files(i915_debugfs_list,
3054 I915_DEBUGFS_ENTRIES,
3055 minor->debugfs_root, minor);
3056 }
3057
3058 void i915_debugfs_cleanup(struct drm_minor *minor)
3059 {
3060 int i;
3061
3062 drm_debugfs_remove_files(i915_debugfs_list,
3063 I915_DEBUGFS_ENTRIES, minor);
3064
3065 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
3066 1, minor);
3067
3068 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
3069 struct drm_info_list *info_list =
3070 (struct drm_info_list *)&i915_pipe_crc_data[i];
3071
3072 drm_debugfs_remove_files(info_list, 1, minor);
3073 }
3074
3075 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3076 struct drm_info_list *info_list =
3077 (struct drm_info_list *) i915_debugfs_files[i].fops;
3078
3079 drm_debugfs_remove_files(info_list, 1, minor);
3080 }
3081 }
3082
3083 #endif /* CONFIG_DEBUG_FS */
Linux kernel - Deliverables
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