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drm/i915: Grab dev->struct_mutex in i915_gem_pageflip_info
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
37 #include <drm/drmP.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
41 #include "i915_drv.h"
42
43 enum {
44 ACTIVE_LIST,
45 INACTIVE_LIST,
46 PINNED_LIST,
47 };
48
49 static const char *yesno(int v)
50 {
51 return v ? "yes" : "no";
52 }
53
54 /* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
56 static int
57 drm_add_fake_info_node(struct drm_minor *minor,
58 struct dentry *ent,
59 const void *key)
60 {
61 struct drm_info_node *node;
62
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
64 if (node == NULL) {
65 debugfs_remove(ent);
66 return -ENOMEM;
67 }
68
69 node->minor = minor;
70 node->dent = ent;
71 node->info_ent = (void *) key;
72
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
76
77 return 0;
78 }
79
80 static int i915_capabilities(struct seq_file *m, void *data)
81 {
82 struct drm_info_node *node = m->private;
83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
85
86 seq_printf(m, "gen: %d\n", info->gen);
87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
88 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89 #define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
91 #undef PRINT_FLAG
92 #undef SEP_SEMICOLON
93
94 return 0;
95 }
96
97 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
98 {
99 if (obj->user_pin_count > 0)
100 return "P";
101 else if (i915_gem_obj_is_pinned(obj))
102 return "p";
103 else
104 return " ";
105 }
106
107 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
108 {
109 switch (obj->tiling_mode) {
110 default:
111 case I915_TILING_NONE: return " ";
112 case I915_TILING_X: return "X";
113 case I915_TILING_Y: return "Y";
114 }
115 }
116
117 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
118 {
119 return obj->has_global_gtt_mapping ? "g" : " ";
120 }
121
122 static void
123 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
124 {
125 struct i915_vma *vma;
126 int pin_count = 0;
127
128 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
129 &obj->base,
130 get_pin_flag(obj),
131 get_tiling_flag(obj),
132 get_global_flag(obj),
133 obj->base.size / 1024,
134 obj->base.read_domains,
135 obj->base.write_domain,
136 obj->last_read_seqno,
137 obj->last_write_seqno,
138 obj->last_fenced_seqno,
139 i915_cache_level_str(obj->cache_level),
140 obj->dirty ? " dirty" : "",
141 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
142 if (obj->base.name)
143 seq_printf(m, " (name: %d)", obj->base.name);
144 list_for_each_entry(vma, &obj->vma_list, vma_link)
145 if (vma->pin_count > 0)
146 pin_count++;
147 seq_printf(m, " (pinned x %d)", pin_count);
148 if (obj->pin_display)
149 seq_printf(m, " (display)");
150 if (obj->fence_reg != I915_FENCE_REG_NONE)
151 seq_printf(m, " (fence: %d)", obj->fence_reg);
152 list_for_each_entry(vma, &obj->vma_list, vma_link) {
153 if (!i915_is_ggtt(vma->vm))
154 seq_puts(m, " (pp");
155 else
156 seq_puts(m, " (g");
157 seq_printf(m, "gtt offset: %08lx, size: %08lx)",
158 vma->node.start, vma->node.size);
159 }
160 if (obj->stolen)
161 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
162 if (obj->pin_mappable || obj->fault_mappable) {
163 char s[3], *t = s;
164 if (obj->pin_mappable)
165 *t++ = 'p';
166 if (obj->fault_mappable)
167 *t++ = 'f';
168 *t = '\0';
169 seq_printf(m, " (%s mappable)", s);
170 }
171 if (obj->ring != NULL)
172 seq_printf(m, " (%s)", obj->ring->name);
173 }
174
175 static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
176 {
177 seq_putc(m, ctx->is_initialized ? 'I' : 'i');
178 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
179 seq_putc(m, ' ');
180 }
181
182 static int i915_gem_object_list_info(struct seq_file *m, void *data)
183 {
184 struct drm_info_node *node = m->private;
185 uintptr_t list = (uintptr_t) node->info_ent->data;
186 struct list_head *head;
187 struct drm_device *dev = node->minor->dev;
188 struct drm_i915_private *dev_priv = dev->dev_private;
189 struct i915_address_space *vm = &dev_priv->gtt.base;
190 struct i915_vma *vma;
191 size_t total_obj_size, total_gtt_size;
192 int count, ret;
193
194 ret = mutex_lock_interruptible(&dev->struct_mutex);
195 if (ret)
196 return ret;
197
198 /* FIXME: the user of this interface might want more than just GGTT */
199 switch (list) {
200 case ACTIVE_LIST:
201 seq_puts(m, "Active:\n");
202 head = &vm->active_list;
203 break;
204 case INACTIVE_LIST:
205 seq_puts(m, "Inactive:\n");
206 head = &vm->inactive_list;
207 break;
208 default:
209 mutex_unlock(&dev->struct_mutex);
210 return -EINVAL;
211 }
212
213 total_obj_size = total_gtt_size = count = 0;
214 list_for_each_entry(vma, head, mm_list) {
215 seq_printf(m, " ");
216 describe_obj(m, vma->obj);
217 seq_printf(m, "\n");
218 total_obj_size += vma->obj->base.size;
219 total_gtt_size += vma->node.size;
220 count++;
221 }
222 mutex_unlock(&dev->struct_mutex);
223
224 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
225 count, total_obj_size, total_gtt_size);
226 return 0;
227 }
228
229 static int obj_rank_by_stolen(void *priv,
230 struct list_head *A, struct list_head *B)
231 {
232 struct drm_i915_gem_object *a =
233 container_of(A, struct drm_i915_gem_object, obj_exec_link);
234 struct drm_i915_gem_object *b =
235 container_of(B, struct drm_i915_gem_object, obj_exec_link);
236
237 return a->stolen->start - b->stolen->start;
238 }
239
240 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
241 {
242 struct drm_info_node *node = m->private;
243 struct drm_device *dev = node->minor->dev;
244 struct drm_i915_private *dev_priv = dev->dev_private;
245 struct drm_i915_gem_object *obj;
246 size_t total_obj_size, total_gtt_size;
247 LIST_HEAD(stolen);
248 int count, ret;
249
250 ret = mutex_lock_interruptible(&dev->struct_mutex);
251 if (ret)
252 return ret;
253
254 total_obj_size = total_gtt_size = count = 0;
255 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
256 if (obj->stolen == NULL)
257 continue;
258
259 list_add(&obj->obj_exec_link, &stolen);
260
261 total_obj_size += obj->base.size;
262 total_gtt_size += i915_gem_obj_ggtt_size(obj);
263 count++;
264 }
265 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
266 if (obj->stolen == NULL)
267 continue;
268
269 list_add(&obj->obj_exec_link, &stolen);
270
271 total_obj_size += obj->base.size;
272 count++;
273 }
274 list_sort(NULL, &stolen, obj_rank_by_stolen);
275 seq_puts(m, "Stolen:\n");
276 while (!list_empty(&stolen)) {
277 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
278 seq_puts(m, " ");
279 describe_obj(m, obj);
280 seq_putc(m, '\n');
281 list_del_init(&obj->obj_exec_link);
282 }
283 mutex_unlock(&dev->struct_mutex);
284
285 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
286 count, total_obj_size, total_gtt_size);
287 return 0;
288 }
289
290 #define count_objects(list, member) do { \
291 list_for_each_entry(obj, list, member) { \
292 size += i915_gem_obj_ggtt_size(obj); \
293 ++count; \
294 if (obj->map_and_fenceable) { \
295 mappable_size += i915_gem_obj_ggtt_size(obj); \
296 ++mappable_count; \
297 } \
298 } \
299 } while (0)
300
301 struct file_stats {
302 struct drm_i915_file_private *file_priv;
303 int count;
304 size_t total, unbound;
305 size_t global, shared;
306 size_t active, inactive;
307 };
308
309 static int per_file_stats(int id, void *ptr, void *data)
310 {
311 struct drm_i915_gem_object *obj = ptr;
312 struct file_stats *stats = data;
313 struct i915_vma *vma;
314
315 stats->count++;
316 stats->total += obj->base.size;
317
318 if (obj->base.name || obj->base.dma_buf)
319 stats->shared += obj->base.size;
320
321 if (USES_FULL_PPGTT(obj->base.dev)) {
322 list_for_each_entry(vma, &obj->vma_list, vma_link) {
323 struct i915_hw_ppgtt *ppgtt;
324
325 if (!drm_mm_node_allocated(&vma->node))
326 continue;
327
328 if (i915_is_ggtt(vma->vm)) {
329 stats->global += obj->base.size;
330 continue;
331 }
332
333 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
334 if (ppgtt->ctx && ppgtt->ctx->file_priv != stats->file_priv)
335 continue;
336
337 if (obj->ring) /* XXX per-vma statistic */
338 stats->active += obj->base.size;
339 else
340 stats->inactive += obj->base.size;
341
342 return 0;
343 }
344 } else {
345 if (i915_gem_obj_ggtt_bound(obj)) {
346 stats->global += obj->base.size;
347 if (obj->ring)
348 stats->active += obj->base.size;
349 else
350 stats->inactive += obj->base.size;
351 return 0;
352 }
353 }
354
355 if (!list_empty(&obj->global_list))
356 stats->unbound += obj->base.size;
357
358 return 0;
359 }
360
361 #define count_vmas(list, member) do { \
362 list_for_each_entry(vma, list, member) { \
363 size += i915_gem_obj_ggtt_size(vma->obj); \
364 ++count; \
365 if (vma->obj->map_and_fenceable) { \
366 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
367 ++mappable_count; \
368 } \
369 } \
370 } while (0)
371
372 static int i915_gem_object_info(struct seq_file *m, void* data)
373 {
374 struct drm_info_node *node = m->private;
375 struct drm_device *dev = node->minor->dev;
376 struct drm_i915_private *dev_priv = dev->dev_private;
377 u32 count, mappable_count, purgeable_count;
378 size_t size, mappable_size, purgeable_size;
379 struct drm_i915_gem_object *obj;
380 struct i915_address_space *vm = &dev_priv->gtt.base;
381 struct drm_file *file;
382 struct i915_vma *vma;
383 int ret;
384
385 ret = mutex_lock_interruptible(&dev->struct_mutex);
386 if (ret)
387 return ret;
388
389 seq_printf(m, "%u objects, %zu bytes\n",
390 dev_priv->mm.object_count,
391 dev_priv->mm.object_memory);
392
393 size = count = mappable_size = mappable_count = 0;
394 count_objects(&dev_priv->mm.bound_list, global_list);
395 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
396 count, mappable_count, size, mappable_size);
397
398 size = count = mappable_size = mappable_count = 0;
399 count_vmas(&vm->active_list, mm_list);
400 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
401 count, mappable_count, size, mappable_size);
402
403 size = count = mappable_size = mappable_count = 0;
404 count_vmas(&vm->inactive_list, mm_list);
405 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
406 count, mappable_count, size, mappable_size);
407
408 size = count = purgeable_size = purgeable_count = 0;
409 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
410 size += obj->base.size, ++count;
411 if (obj->madv == I915_MADV_DONTNEED)
412 purgeable_size += obj->base.size, ++purgeable_count;
413 }
414 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
415
416 size = count = mappable_size = mappable_count = 0;
417 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
418 if (obj->fault_mappable) {
419 size += i915_gem_obj_ggtt_size(obj);
420 ++count;
421 }
422 if (obj->pin_mappable) {
423 mappable_size += i915_gem_obj_ggtt_size(obj);
424 ++mappable_count;
425 }
426 if (obj->madv == I915_MADV_DONTNEED) {
427 purgeable_size += obj->base.size;
428 ++purgeable_count;
429 }
430 }
431 seq_printf(m, "%u purgeable objects, %zu bytes\n",
432 purgeable_count, purgeable_size);
433 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
434 mappable_count, mappable_size);
435 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
436 count, size);
437
438 seq_printf(m, "%zu [%lu] gtt total\n",
439 dev_priv->gtt.base.total,
440 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
441
442 seq_putc(m, '\n');
443 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
444 struct file_stats stats;
445 struct task_struct *task;
446
447 memset(&stats, 0, sizeof(stats));
448 stats.file_priv = file->driver_priv;
449 idr_for_each(&file->object_idr, per_file_stats, &stats);
450 /*
451 * Although we have a valid reference on file->pid, that does
452 * not guarantee that the task_struct who called get_pid() is
453 * still alive (e.g. get_pid(current) => fork() => exit()).
454 * Therefore, we need to protect this ->comm access using RCU.
455 */
456 rcu_read_lock();
457 task = pid_task(file->pid, PIDTYPE_PID);
458 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n",
459 task ? task->comm : "<unknown>",
460 stats.count,
461 stats.total,
462 stats.active,
463 stats.inactive,
464 stats.global,
465 stats.shared,
466 stats.unbound);
467 rcu_read_unlock();
468 }
469
470 mutex_unlock(&dev->struct_mutex);
471
472 return 0;
473 }
474
475 static int i915_gem_gtt_info(struct seq_file *m, void *data)
476 {
477 struct drm_info_node *node = m->private;
478 struct drm_device *dev = node->minor->dev;
479 uintptr_t list = (uintptr_t) node->info_ent->data;
480 struct drm_i915_private *dev_priv = dev->dev_private;
481 struct drm_i915_gem_object *obj;
482 size_t total_obj_size, total_gtt_size;
483 int count, ret;
484
485 ret = mutex_lock_interruptible(&dev->struct_mutex);
486 if (ret)
487 return ret;
488
489 total_obj_size = total_gtt_size = count = 0;
490 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
491 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
492 continue;
493
494 seq_puts(m, " ");
495 describe_obj(m, obj);
496 seq_putc(m, '\n');
497 total_obj_size += obj->base.size;
498 total_gtt_size += i915_gem_obj_ggtt_size(obj);
499 count++;
500 }
501
502 mutex_unlock(&dev->struct_mutex);
503
504 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
505 count, total_obj_size, total_gtt_size);
506
507 return 0;
508 }
509
510 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
511 {
512 struct drm_info_node *node = m->private;
513 struct drm_device *dev = node->minor->dev;
514 unsigned long flags;
515 struct intel_crtc *crtc;
516 int ret;
517
518 ret = mutex_lock_interruptible(&dev->struct_mutex);
519 if (ret)
520 return ret;
521
522 for_each_intel_crtc(dev, crtc) {
523 const char pipe = pipe_name(crtc->pipe);
524 const char plane = plane_name(crtc->plane);
525 struct intel_unpin_work *work;
526
527 spin_lock_irqsave(&dev->event_lock, flags);
528 work = crtc->unpin_work;
529 if (work == NULL) {
530 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
531 pipe, plane);
532 } else {
533 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
534 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
535 pipe, plane);
536 } else {
537 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
538 pipe, plane);
539 }
540 if (work->enable_stall_check)
541 seq_puts(m, "Stall check enabled, ");
542 else
543 seq_puts(m, "Stall check waiting for page flip ioctl, ");
544 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
545
546 if (work->old_fb_obj) {
547 struct drm_i915_gem_object *obj = work->old_fb_obj;
548 if (obj)
549 seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n",
550 i915_gem_obj_ggtt_offset(obj));
551 }
552 if (work->pending_flip_obj) {
553 struct drm_i915_gem_object *obj = work->pending_flip_obj;
554 if (obj)
555 seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n",
556 i915_gem_obj_ggtt_offset(obj));
557 }
558 }
559 spin_unlock_irqrestore(&dev->event_lock, flags);
560 }
561
562 mutex_unlock(&dev->struct_mutex);
563
564 return 0;
565 }
566
567 static int i915_gem_request_info(struct seq_file *m, void *data)
568 {
569 struct drm_info_node *node = m->private;
570 struct drm_device *dev = node->minor->dev;
571 struct drm_i915_private *dev_priv = dev->dev_private;
572 struct intel_engine_cs *ring;
573 struct drm_i915_gem_request *gem_request;
574 int ret, count, i;
575
576 ret = mutex_lock_interruptible(&dev->struct_mutex);
577 if (ret)
578 return ret;
579
580 count = 0;
581 for_each_ring(ring, dev_priv, i) {
582 if (list_empty(&ring->request_list))
583 continue;
584
585 seq_printf(m, "%s requests:\n", ring->name);
586 list_for_each_entry(gem_request,
587 &ring->request_list,
588 list) {
589 seq_printf(m, " %d @ %d\n",
590 gem_request->seqno,
591 (int) (jiffies - gem_request->emitted_jiffies));
592 }
593 count++;
594 }
595 mutex_unlock(&dev->struct_mutex);
596
597 if (count == 0)
598 seq_puts(m, "No requests\n");
599
600 return 0;
601 }
602
603 static void i915_ring_seqno_info(struct seq_file *m,
604 struct intel_engine_cs *ring)
605 {
606 if (ring->get_seqno) {
607 seq_printf(m, "Current sequence (%s): %u\n",
608 ring->name, ring->get_seqno(ring, false));
609 }
610 }
611
612 static int i915_gem_seqno_info(struct seq_file *m, void *data)
613 {
614 struct drm_info_node *node = m->private;
615 struct drm_device *dev = node->minor->dev;
616 struct drm_i915_private *dev_priv = dev->dev_private;
617 struct intel_engine_cs *ring;
618 int ret, i;
619
620 ret = mutex_lock_interruptible(&dev->struct_mutex);
621 if (ret)
622 return ret;
623 intel_runtime_pm_get(dev_priv);
624
625 for_each_ring(ring, dev_priv, i)
626 i915_ring_seqno_info(m, ring);
627
628 intel_runtime_pm_put(dev_priv);
629 mutex_unlock(&dev->struct_mutex);
630
631 return 0;
632 }
633
634
635 static int i915_interrupt_info(struct seq_file *m, void *data)
636 {
637 struct drm_info_node *node = m->private;
638 struct drm_device *dev = node->minor->dev;
639 struct drm_i915_private *dev_priv = dev->dev_private;
640 struct intel_engine_cs *ring;
641 int ret, i, pipe;
642
643 ret = mutex_lock_interruptible(&dev->struct_mutex);
644 if (ret)
645 return ret;
646 intel_runtime_pm_get(dev_priv);
647
648 if (IS_CHERRYVIEW(dev)) {
649 int i;
650 seq_printf(m, "Master Interrupt Control:\t%08x\n",
651 I915_READ(GEN8_MASTER_IRQ));
652
653 seq_printf(m, "Display IER:\t%08x\n",
654 I915_READ(VLV_IER));
655 seq_printf(m, "Display IIR:\t%08x\n",
656 I915_READ(VLV_IIR));
657 seq_printf(m, "Display IIR_RW:\t%08x\n",
658 I915_READ(VLV_IIR_RW));
659 seq_printf(m, "Display IMR:\t%08x\n",
660 I915_READ(VLV_IMR));
661 for_each_pipe(pipe)
662 seq_printf(m, "Pipe %c stat:\t%08x\n",
663 pipe_name(pipe),
664 I915_READ(PIPESTAT(pipe)));
665
666 seq_printf(m, "Port hotplug:\t%08x\n",
667 I915_READ(PORT_HOTPLUG_EN));
668 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
669 I915_READ(VLV_DPFLIPSTAT));
670 seq_printf(m, "DPINVGTT:\t%08x\n",
671 I915_READ(DPINVGTT));
672
673 for (i = 0; i < 4; i++) {
674 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
675 i, I915_READ(GEN8_GT_IMR(i)));
676 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
677 i, I915_READ(GEN8_GT_IIR(i)));
678 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
679 i, I915_READ(GEN8_GT_IER(i)));
680 }
681
682 seq_printf(m, "PCU interrupt mask:\t%08x\n",
683 I915_READ(GEN8_PCU_IMR));
684 seq_printf(m, "PCU interrupt identity:\t%08x\n",
685 I915_READ(GEN8_PCU_IIR));
686 seq_printf(m, "PCU interrupt enable:\t%08x\n",
687 I915_READ(GEN8_PCU_IER));
688 } else if (INTEL_INFO(dev)->gen >= 8) {
689 seq_printf(m, "Master Interrupt Control:\t%08x\n",
690 I915_READ(GEN8_MASTER_IRQ));
691
692 for (i = 0; i < 4; i++) {
693 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
694 i, I915_READ(GEN8_GT_IMR(i)));
695 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
696 i, I915_READ(GEN8_GT_IIR(i)));
697 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
698 i, I915_READ(GEN8_GT_IER(i)));
699 }
700
701 for_each_pipe(pipe) {
702 seq_printf(m, "Pipe %c IMR:\t%08x\n",
703 pipe_name(pipe),
704 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
705 seq_printf(m, "Pipe %c IIR:\t%08x\n",
706 pipe_name(pipe),
707 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
708 seq_printf(m, "Pipe %c IER:\t%08x\n",
709 pipe_name(pipe),
710 I915_READ(GEN8_DE_PIPE_IER(pipe)));
711 }
712
713 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
714 I915_READ(GEN8_DE_PORT_IMR));
715 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
716 I915_READ(GEN8_DE_PORT_IIR));
717 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
718 I915_READ(GEN8_DE_PORT_IER));
719
720 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
721 I915_READ(GEN8_DE_MISC_IMR));
722 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
723 I915_READ(GEN8_DE_MISC_IIR));
724 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
725 I915_READ(GEN8_DE_MISC_IER));
726
727 seq_printf(m, "PCU interrupt mask:\t%08x\n",
728 I915_READ(GEN8_PCU_IMR));
729 seq_printf(m, "PCU interrupt identity:\t%08x\n",
730 I915_READ(GEN8_PCU_IIR));
731 seq_printf(m, "PCU interrupt enable:\t%08x\n",
732 I915_READ(GEN8_PCU_IER));
733 } else if (IS_VALLEYVIEW(dev)) {
734 seq_printf(m, "Display IER:\t%08x\n",
735 I915_READ(VLV_IER));
736 seq_printf(m, "Display IIR:\t%08x\n",
737 I915_READ(VLV_IIR));
738 seq_printf(m, "Display IIR_RW:\t%08x\n",
739 I915_READ(VLV_IIR_RW));
740 seq_printf(m, "Display IMR:\t%08x\n",
741 I915_READ(VLV_IMR));
742 for_each_pipe(pipe)
743 seq_printf(m, "Pipe %c stat:\t%08x\n",
744 pipe_name(pipe),
745 I915_READ(PIPESTAT(pipe)));
746
747 seq_printf(m, "Master IER:\t%08x\n",
748 I915_READ(VLV_MASTER_IER));
749
750 seq_printf(m, "Render IER:\t%08x\n",
751 I915_READ(GTIER));
752 seq_printf(m, "Render IIR:\t%08x\n",
753 I915_READ(GTIIR));
754 seq_printf(m, "Render IMR:\t%08x\n",
755 I915_READ(GTIMR));
756
757 seq_printf(m, "PM IER:\t\t%08x\n",
758 I915_READ(GEN6_PMIER));
759 seq_printf(m, "PM IIR:\t\t%08x\n",
760 I915_READ(GEN6_PMIIR));
761 seq_printf(m, "PM IMR:\t\t%08x\n",
762 I915_READ(GEN6_PMIMR));
763
764 seq_printf(m, "Port hotplug:\t%08x\n",
765 I915_READ(PORT_HOTPLUG_EN));
766 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
767 I915_READ(VLV_DPFLIPSTAT));
768 seq_printf(m, "DPINVGTT:\t%08x\n",
769 I915_READ(DPINVGTT));
770
771 } else if (!HAS_PCH_SPLIT(dev)) {
772 seq_printf(m, "Interrupt enable: %08x\n",
773 I915_READ(IER));
774 seq_printf(m, "Interrupt identity: %08x\n",
775 I915_READ(IIR));
776 seq_printf(m, "Interrupt mask: %08x\n",
777 I915_READ(IMR));
778 for_each_pipe(pipe)
779 seq_printf(m, "Pipe %c stat: %08x\n",
780 pipe_name(pipe),
781 I915_READ(PIPESTAT(pipe)));
782 } else {
783 seq_printf(m, "North Display Interrupt enable: %08x\n",
784 I915_READ(DEIER));
785 seq_printf(m, "North Display Interrupt identity: %08x\n",
786 I915_READ(DEIIR));
787 seq_printf(m, "North Display Interrupt mask: %08x\n",
788 I915_READ(DEIMR));
789 seq_printf(m, "South Display Interrupt enable: %08x\n",
790 I915_READ(SDEIER));
791 seq_printf(m, "South Display Interrupt identity: %08x\n",
792 I915_READ(SDEIIR));
793 seq_printf(m, "South Display Interrupt mask: %08x\n",
794 I915_READ(SDEIMR));
795 seq_printf(m, "Graphics Interrupt enable: %08x\n",
796 I915_READ(GTIER));
797 seq_printf(m, "Graphics Interrupt identity: %08x\n",
798 I915_READ(GTIIR));
799 seq_printf(m, "Graphics Interrupt mask: %08x\n",
800 I915_READ(GTIMR));
801 }
802 for_each_ring(ring, dev_priv, i) {
803 if (INTEL_INFO(dev)->gen >= 6) {
804 seq_printf(m,
805 "Graphics Interrupt mask (%s): %08x\n",
806 ring->name, I915_READ_IMR(ring));
807 }
808 i915_ring_seqno_info(m, ring);
809 }
810 intel_runtime_pm_put(dev_priv);
811 mutex_unlock(&dev->struct_mutex);
812
813 return 0;
814 }
815
816 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
817 {
818 struct drm_info_node *node = m->private;
819 struct drm_device *dev = node->minor->dev;
820 struct drm_i915_private *dev_priv = dev->dev_private;
821 int i, ret;
822
823 ret = mutex_lock_interruptible(&dev->struct_mutex);
824 if (ret)
825 return ret;
826
827 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
828 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
829 for (i = 0; i < dev_priv->num_fence_regs; i++) {
830 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
831
832 seq_printf(m, "Fence %d, pin count = %d, object = ",
833 i, dev_priv->fence_regs[i].pin_count);
834 if (obj == NULL)
835 seq_puts(m, "unused");
836 else
837 describe_obj(m, obj);
838 seq_putc(m, '\n');
839 }
840
841 mutex_unlock(&dev->struct_mutex);
842 return 0;
843 }
844
845 static int i915_hws_info(struct seq_file *m, void *data)
846 {
847 struct drm_info_node *node = m->private;
848 struct drm_device *dev = node->minor->dev;
849 struct drm_i915_private *dev_priv = dev->dev_private;
850 struct intel_engine_cs *ring;
851 const u32 *hws;
852 int i;
853
854 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
855 hws = ring->status_page.page_addr;
856 if (hws == NULL)
857 return 0;
858
859 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
860 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
861 i * 4,
862 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
863 }
864 return 0;
865 }
866
867 static ssize_t
868 i915_error_state_write(struct file *filp,
869 const char __user *ubuf,
870 size_t cnt,
871 loff_t *ppos)
872 {
873 struct i915_error_state_file_priv *error_priv = filp->private_data;
874 struct drm_device *dev = error_priv->dev;
875 int ret;
876
877 DRM_DEBUG_DRIVER("Resetting error state\n");
878
879 ret = mutex_lock_interruptible(&dev->struct_mutex);
880 if (ret)
881 return ret;
882
883 i915_destroy_error_state(dev);
884 mutex_unlock(&dev->struct_mutex);
885
886 return cnt;
887 }
888
889 static int i915_error_state_open(struct inode *inode, struct file *file)
890 {
891 struct drm_device *dev = inode->i_private;
892 struct i915_error_state_file_priv *error_priv;
893
894 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
895 if (!error_priv)
896 return -ENOMEM;
897
898 error_priv->dev = dev;
899
900 i915_error_state_get(dev, error_priv);
901
902 file->private_data = error_priv;
903
904 return 0;
905 }
906
907 static int i915_error_state_release(struct inode *inode, struct file *file)
908 {
909 struct i915_error_state_file_priv *error_priv = file->private_data;
910
911 i915_error_state_put(error_priv);
912 kfree(error_priv);
913
914 return 0;
915 }
916
917 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
918 size_t count, loff_t *pos)
919 {
920 struct i915_error_state_file_priv *error_priv = file->private_data;
921 struct drm_i915_error_state_buf error_str;
922 loff_t tmp_pos = 0;
923 ssize_t ret_count = 0;
924 int ret;
925
926 ret = i915_error_state_buf_init(&error_str, count, *pos);
927 if (ret)
928 return ret;
929
930 ret = i915_error_state_to_str(&error_str, error_priv);
931 if (ret)
932 goto out;
933
934 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
935 error_str.buf,
936 error_str.bytes);
937
938 if (ret_count < 0)
939 ret = ret_count;
940 else
941 *pos = error_str.start + ret_count;
942 out:
943 i915_error_state_buf_release(&error_str);
944 return ret ?: ret_count;
945 }
946
947 static const struct file_operations i915_error_state_fops = {
948 .owner = THIS_MODULE,
949 .open = i915_error_state_open,
950 .read = i915_error_state_read,
951 .write = i915_error_state_write,
952 .llseek = default_llseek,
953 .release = i915_error_state_release,
954 };
955
956 static int
957 i915_next_seqno_get(void *data, u64 *val)
958 {
959 struct drm_device *dev = data;
960 struct drm_i915_private *dev_priv = dev->dev_private;
961 int ret;
962
963 ret = mutex_lock_interruptible(&dev->struct_mutex);
964 if (ret)
965 return ret;
966
967 *val = dev_priv->next_seqno;
968 mutex_unlock(&dev->struct_mutex);
969
970 return 0;
971 }
972
973 static int
974 i915_next_seqno_set(void *data, u64 val)
975 {
976 struct drm_device *dev = data;
977 int ret;
978
979 ret = mutex_lock_interruptible(&dev->struct_mutex);
980 if (ret)
981 return ret;
982
983 ret = i915_gem_set_seqno(dev, val);
984 mutex_unlock(&dev->struct_mutex);
985
986 return ret;
987 }
988
989 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
990 i915_next_seqno_get, i915_next_seqno_set,
991 "0x%llx\n");
992
993 static int i915_rstdby_delays(struct seq_file *m, void *unused)
994 {
995 struct drm_info_node *node = m->private;
996 struct drm_device *dev = node->minor->dev;
997 struct drm_i915_private *dev_priv = dev->dev_private;
998 u16 crstanddelay;
999 int ret;
1000
1001 ret = mutex_lock_interruptible(&dev->struct_mutex);
1002 if (ret)
1003 return ret;
1004 intel_runtime_pm_get(dev_priv);
1005
1006 crstanddelay = I915_READ16(CRSTANDVID);
1007
1008 intel_runtime_pm_put(dev_priv);
1009 mutex_unlock(&dev->struct_mutex);
1010
1011 seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
1012
1013 return 0;
1014 }
1015
1016 static int i915_frequency_info(struct seq_file *m, void *unused)
1017 {
1018 struct drm_info_node *node = m->private;
1019 struct drm_device *dev = node->minor->dev;
1020 struct drm_i915_private *dev_priv = dev->dev_private;
1021 int ret = 0;
1022
1023 intel_runtime_pm_get(dev_priv);
1024
1025 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1026
1027 if (IS_GEN5(dev)) {
1028 u16 rgvswctl = I915_READ16(MEMSWCTL);
1029 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1030
1031 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1032 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1033 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1034 MEMSTAT_VID_SHIFT);
1035 seq_printf(m, "Current P-state: %d\n",
1036 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1037 } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1038 IS_BROADWELL(dev)) {
1039 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1040 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1041 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1042 u32 rpmodectl, rpinclimit, rpdeclimit;
1043 u32 rpstat, cagf, reqf;
1044 u32 rpupei, rpcurup, rpprevup;
1045 u32 rpdownei, rpcurdown, rpprevdown;
1046 int max_freq;
1047
1048 /* RPSTAT1 is in the GT power well */
1049 ret = mutex_lock_interruptible(&dev->struct_mutex);
1050 if (ret)
1051 goto out;
1052
1053 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
1054
1055 reqf = I915_READ(GEN6_RPNSWREQ);
1056 reqf &= ~GEN6_TURBO_DISABLE;
1057 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1058 reqf >>= 24;
1059 else
1060 reqf >>= 25;
1061 reqf *= GT_FREQUENCY_MULTIPLIER;
1062
1063 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1064 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1065 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1066
1067 rpstat = I915_READ(GEN6_RPSTAT1);
1068 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1069 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1070 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1071 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1072 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1073 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1074 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1075 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1076 else
1077 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1078 cagf *= GT_FREQUENCY_MULTIPLIER;
1079
1080 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
1081 mutex_unlock(&dev->struct_mutex);
1082
1083 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1084 I915_READ(GEN6_PMIER),
1085 I915_READ(GEN6_PMIMR),
1086 I915_READ(GEN6_PMISR),
1087 I915_READ(GEN6_PMIIR),
1088 I915_READ(GEN6_PMINTRMSK));
1089 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1090 seq_printf(m, "Render p-state ratio: %d\n",
1091 (gt_perf_status & 0xff00) >> 8);
1092 seq_printf(m, "Render p-state VID: %d\n",
1093 gt_perf_status & 0xff);
1094 seq_printf(m, "Render p-state limit: %d\n",
1095 rp_state_limits & 0xff);
1096 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1097 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1098 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1099 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1100 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1101 seq_printf(m, "CAGF: %dMHz\n", cagf);
1102 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1103 GEN6_CURICONT_MASK);
1104 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1105 GEN6_CURBSYTAVG_MASK);
1106 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1107 GEN6_CURBSYTAVG_MASK);
1108 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1109 GEN6_CURIAVG_MASK);
1110 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1111 GEN6_CURBSYTAVG_MASK);
1112 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1113 GEN6_CURBSYTAVG_MASK);
1114
1115 max_freq = (rp_state_cap & 0xff0000) >> 16;
1116 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1117 max_freq * GT_FREQUENCY_MULTIPLIER);
1118
1119 max_freq = (rp_state_cap & 0xff00) >> 8;
1120 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1121 max_freq * GT_FREQUENCY_MULTIPLIER);
1122
1123 max_freq = rp_state_cap & 0xff;
1124 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1125 max_freq * GT_FREQUENCY_MULTIPLIER);
1126
1127 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1128 dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER);
1129 } else if (IS_VALLEYVIEW(dev)) {
1130 u32 freq_sts, val;
1131
1132 mutex_lock(&dev_priv->rps.hw_lock);
1133 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1134 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1135 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1136
1137 val = valleyview_rps_max_freq(dev_priv);
1138 seq_printf(m, "max GPU freq: %d MHz\n",
1139 vlv_gpu_freq(dev_priv, val));
1140
1141 val = valleyview_rps_min_freq(dev_priv);
1142 seq_printf(m, "min GPU freq: %d MHz\n",
1143 vlv_gpu_freq(dev_priv, val));
1144
1145 seq_printf(m, "current GPU freq: %d MHz\n",
1146 vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1147 mutex_unlock(&dev_priv->rps.hw_lock);
1148 } else {
1149 seq_puts(m, "no P-state info available\n");
1150 }
1151
1152 out:
1153 intel_runtime_pm_put(dev_priv);
1154 return ret;
1155 }
1156
1157 static int i915_delayfreq_table(struct seq_file *m, void *unused)
1158 {
1159 struct drm_info_node *node = m->private;
1160 struct drm_device *dev = node->minor->dev;
1161 struct drm_i915_private *dev_priv = dev->dev_private;
1162 u32 delayfreq;
1163 int ret, i;
1164
1165 ret = mutex_lock_interruptible(&dev->struct_mutex);
1166 if (ret)
1167 return ret;
1168 intel_runtime_pm_get(dev_priv);
1169
1170 for (i = 0; i < 16; i++) {
1171 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
1172 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
1173 (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
1174 }
1175
1176 intel_runtime_pm_put(dev_priv);
1177
1178 mutex_unlock(&dev->struct_mutex);
1179
1180 return 0;
1181 }
1182
1183 static inline int MAP_TO_MV(int map)
1184 {
1185 return 1250 - (map * 25);
1186 }
1187
1188 static int i915_inttoext_table(struct seq_file *m, void *unused)
1189 {
1190 struct drm_info_node *node = m->private;
1191 struct drm_device *dev = node->minor->dev;
1192 struct drm_i915_private *dev_priv = dev->dev_private;
1193 u32 inttoext;
1194 int ret, i;
1195
1196 ret = mutex_lock_interruptible(&dev->struct_mutex);
1197 if (ret)
1198 return ret;
1199 intel_runtime_pm_get(dev_priv);
1200
1201 for (i = 1; i <= 32; i++) {
1202 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
1203 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
1204 }
1205
1206 intel_runtime_pm_put(dev_priv);
1207 mutex_unlock(&dev->struct_mutex);
1208
1209 return 0;
1210 }
1211
1212 static int ironlake_drpc_info(struct seq_file *m)
1213 {
1214 struct drm_info_node *node = m->private;
1215 struct drm_device *dev = node->minor->dev;
1216 struct drm_i915_private *dev_priv = dev->dev_private;
1217 u32 rgvmodectl, rstdbyctl;
1218 u16 crstandvid;
1219 int ret;
1220
1221 ret = mutex_lock_interruptible(&dev->struct_mutex);
1222 if (ret)
1223 return ret;
1224 intel_runtime_pm_get(dev_priv);
1225
1226 rgvmodectl = I915_READ(MEMMODECTL);
1227 rstdbyctl = I915_READ(RSTDBYCTL);
1228 crstandvid = I915_READ16(CRSTANDVID);
1229
1230 intel_runtime_pm_put(dev_priv);
1231 mutex_unlock(&dev->struct_mutex);
1232
1233 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1234 "yes" : "no");
1235 seq_printf(m, "Boost freq: %d\n",
1236 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1237 MEMMODE_BOOST_FREQ_SHIFT);
1238 seq_printf(m, "HW control enabled: %s\n",
1239 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1240 seq_printf(m, "SW control enabled: %s\n",
1241 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1242 seq_printf(m, "Gated voltage change: %s\n",
1243 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1244 seq_printf(m, "Starting frequency: P%d\n",
1245 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1246 seq_printf(m, "Max P-state: P%d\n",
1247 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1248 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1249 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1250 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1251 seq_printf(m, "Render standby enabled: %s\n",
1252 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1253 seq_puts(m, "Current RS state: ");
1254 switch (rstdbyctl & RSX_STATUS_MASK) {
1255 case RSX_STATUS_ON:
1256 seq_puts(m, "on\n");
1257 break;
1258 case RSX_STATUS_RC1:
1259 seq_puts(m, "RC1\n");
1260 break;
1261 case RSX_STATUS_RC1E:
1262 seq_puts(m, "RC1E\n");
1263 break;
1264 case RSX_STATUS_RS1:
1265 seq_puts(m, "RS1\n");
1266 break;
1267 case RSX_STATUS_RS2:
1268 seq_puts(m, "RS2 (RC6)\n");
1269 break;
1270 case RSX_STATUS_RS3:
1271 seq_puts(m, "RC3 (RC6+)\n");
1272 break;
1273 default:
1274 seq_puts(m, "unknown\n");
1275 break;
1276 }
1277
1278 return 0;
1279 }
1280
1281 static int vlv_drpc_info(struct seq_file *m)
1282 {
1283
1284 struct drm_info_node *node = m->private;
1285 struct drm_device *dev = node->minor->dev;
1286 struct drm_i915_private *dev_priv = dev->dev_private;
1287 u32 rpmodectl1, rcctl1;
1288 unsigned fw_rendercount = 0, fw_mediacount = 0;
1289
1290 intel_runtime_pm_get(dev_priv);
1291
1292 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1293 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1294
1295 intel_runtime_pm_put(dev_priv);
1296
1297 seq_printf(m, "Video Turbo Mode: %s\n",
1298 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1299 seq_printf(m, "Turbo enabled: %s\n",
1300 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1301 seq_printf(m, "HW control enabled: %s\n",
1302 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1303 seq_printf(m, "SW control enabled: %s\n",
1304 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1305 GEN6_RP_MEDIA_SW_MODE));
1306 seq_printf(m, "RC6 Enabled: %s\n",
1307 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1308 GEN6_RC_CTL_EI_MODE(1))));
1309 seq_printf(m, "Render Power Well: %s\n",
1310 (I915_READ(VLV_GTLC_PW_STATUS) &
1311 VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1312 seq_printf(m, "Media Power Well: %s\n",
1313 (I915_READ(VLV_GTLC_PW_STATUS) &
1314 VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1315
1316 seq_printf(m, "Render RC6 residency since boot: %u\n",
1317 I915_READ(VLV_GT_RENDER_RC6));
1318 seq_printf(m, "Media RC6 residency since boot: %u\n",
1319 I915_READ(VLV_GT_MEDIA_RC6));
1320
1321 spin_lock_irq(&dev_priv->uncore.lock);
1322 fw_rendercount = dev_priv->uncore.fw_rendercount;
1323 fw_mediacount = dev_priv->uncore.fw_mediacount;
1324 spin_unlock_irq(&dev_priv->uncore.lock);
1325
1326 seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount);
1327 seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount);
1328
1329
1330 return 0;
1331 }
1332
1333
1334 static int gen6_drpc_info(struct seq_file *m)
1335 {
1336
1337 struct drm_info_node *node = m->private;
1338 struct drm_device *dev = node->minor->dev;
1339 struct drm_i915_private *dev_priv = dev->dev_private;
1340 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1341 unsigned forcewake_count;
1342 int count = 0, ret;
1343
1344 ret = mutex_lock_interruptible(&dev->struct_mutex);
1345 if (ret)
1346 return ret;
1347 intel_runtime_pm_get(dev_priv);
1348
1349 spin_lock_irq(&dev_priv->uncore.lock);
1350 forcewake_count = dev_priv->uncore.forcewake_count;
1351 spin_unlock_irq(&dev_priv->uncore.lock);
1352
1353 if (forcewake_count) {
1354 seq_puts(m, "RC information inaccurate because somebody "
1355 "holds a forcewake reference \n");
1356 } else {
1357 /* NB: we cannot use forcewake, else we read the wrong values */
1358 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1359 udelay(10);
1360 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1361 }
1362
1363 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1364 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1365
1366 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1367 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1368 mutex_unlock(&dev->struct_mutex);
1369 mutex_lock(&dev_priv->rps.hw_lock);
1370 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1371 mutex_unlock(&dev_priv->rps.hw_lock);
1372
1373 intel_runtime_pm_put(dev_priv);
1374
1375 seq_printf(m, "Video Turbo Mode: %s\n",
1376 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1377 seq_printf(m, "HW control enabled: %s\n",
1378 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1379 seq_printf(m, "SW control enabled: %s\n",
1380 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1381 GEN6_RP_MEDIA_SW_MODE));
1382 seq_printf(m, "RC1e Enabled: %s\n",
1383 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1384 seq_printf(m, "RC6 Enabled: %s\n",
1385 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1386 seq_printf(m, "Deep RC6 Enabled: %s\n",
1387 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1388 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1389 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1390 seq_puts(m, "Current RC state: ");
1391 switch (gt_core_status & GEN6_RCn_MASK) {
1392 case GEN6_RC0:
1393 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1394 seq_puts(m, "Core Power Down\n");
1395 else
1396 seq_puts(m, "on\n");
1397 break;
1398 case GEN6_RC3:
1399 seq_puts(m, "RC3\n");
1400 break;
1401 case GEN6_RC6:
1402 seq_puts(m, "RC6\n");
1403 break;
1404 case GEN6_RC7:
1405 seq_puts(m, "RC7\n");
1406 break;
1407 default:
1408 seq_puts(m, "Unknown\n");
1409 break;
1410 }
1411
1412 seq_printf(m, "Core Power Down: %s\n",
1413 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1414
1415 /* Not exactly sure what this is */
1416 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1417 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1418 seq_printf(m, "RC6 residency since boot: %u\n",
1419 I915_READ(GEN6_GT_GFX_RC6));
1420 seq_printf(m, "RC6+ residency since boot: %u\n",
1421 I915_READ(GEN6_GT_GFX_RC6p));
1422 seq_printf(m, "RC6++ residency since boot: %u\n",
1423 I915_READ(GEN6_GT_GFX_RC6pp));
1424
1425 seq_printf(m, "RC6 voltage: %dmV\n",
1426 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1427 seq_printf(m, "RC6+ voltage: %dmV\n",
1428 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1429 seq_printf(m, "RC6++ voltage: %dmV\n",
1430 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1431 return 0;
1432 }
1433
1434 static int i915_drpc_info(struct seq_file *m, void *unused)
1435 {
1436 struct drm_info_node *node = m->private;
1437 struct drm_device *dev = node->minor->dev;
1438
1439 if (IS_VALLEYVIEW(dev))
1440 return vlv_drpc_info(m);
1441 else if (IS_GEN6(dev) || IS_GEN7(dev))
1442 return gen6_drpc_info(m);
1443 else
1444 return ironlake_drpc_info(m);
1445 }
1446
1447 static int i915_fbc_status(struct seq_file *m, void *unused)
1448 {
1449 struct drm_info_node *node = m->private;
1450 struct drm_device *dev = node->minor->dev;
1451 struct drm_i915_private *dev_priv = dev->dev_private;
1452
1453 if (!HAS_FBC(dev)) {
1454 seq_puts(m, "FBC unsupported on this chipset\n");
1455 return 0;
1456 }
1457
1458 intel_runtime_pm_get(dev_priv);
1459
1460 if (intel_fbc_enabled(dev)) {
1461 seq_puts(m, "FBC enabled\n");
1462 } else {
1463 seq_puts(m, "FBC disabled: ");
1464 switch (dev_priv->fbc.no_fbc_reason) {
1465 case FBC_OK:
1466 seq_puts(m, "FBC actived, but currently disabled in hardware");
1467 break;
1468 case FBC_UNSUPPORTED:
1469 seq_puts(m, "unsupported by this chipset");
1470 break;
1471 case FBC_NO_OUTPUT:
1472 seq_puts(m, "no outputs");
1473 break;
1474 case FBC_STOLEN_TOO_SMALL:
1475 seq_puts(m, "not enough stolen memory");
1476 break;
1477 case FBC_UNSUPPORTED_MODE:
1478 seq_puts(m, "mode not supported");
1479 break;
1480 case FBC_MODE_TOO_LARGE:
1481 seq_puts(m, "mode too large");
1482 break;
1483 case FBC_BAD_PLANE:
1484 seq_puts(m, "FBC unsupported on plane");
1485 break;
1486 case FBC_NOT_TILED:
1487 seq_puts(m, "scanout buffer not tiled");
1488 break;
1489 case FBC_MULTIPLE_PIPES:
1490 seq_puts(m, "multiple pipes are enabled");
1491 break;
1492 case FBC_MODULE_PARAM:
1493 seq_puts(m, "disabled per module param (default off)");
1494 break;
1495 case FBC_CHIP_DEFAULT:
1496 seq_puts(m, "disabled per chip default");
1497 break;
1498 default:
1499 seq_puts(m, "unknown reason");
1500 }
1501 seq_putc(m, '\n');
1502 }
1503
1504 intel_runtime_pm_put(dev_priv);
1505
1506 return 0;
1507 }
1508
1509 static int i915_ips_status(struct seq_file *m, void *unused)
1510 {
1511 struct drm_info_node *node = m->private;
1512 struct drm_device *dev = node->minor->dev;
1513 struct drm_i915_private *dev_priv = dev->dev_private;
1514
1515 if (!HAS_IPS(dev)) {
1516 seq_puts(m, "not supported\n");
1517 return 0;
1518 }
1519
1520 intel_runtime_pm_get(dev_priv);
1521
1522 if (IS_BROADWELL(dev) || I915_READ(IPS_CTL) & IPS_ENABLE)
1523 seq_puts(m, "enabled\n");
1524 else
1525 seq_puts(m, "disabled\n");
1526
1527 intel_runtime_pm_put(dev_priv);
1528
1529 return 0;
1530 }
1531
1532 static int i915_sr_status(struct seq_file *m, void *unused)
1533 {
1534 struct drm_info_node *node = m->private;
1535 struct drm_device *dev = node->minor->dev;
1536 struct drm_i915_private *dev_priv = dev->dev_private;
1537 bool sr_enabled = false;
1538
1539 intel_runtime_pm_get(dev_priv);
1540
1541 if (HAS_PCH_SPLIT(dev))
1542 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1543 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1544 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1545 else if (IS_I915GM(dev))
1546 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1547 else if (IS_PINEVIEW(dev))
1548 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1549
1550 intel_runtime_pm_put(dev_priv);
1551
1552 seq_printf(m, "self-refresh: %s\n",
1553 sr_enabled ? "enabled" : "disabled");
1554
1555 return 0;
1556 }
1557
1558 static int i915_emon_status(struct seq_file *m, void *unused)
1559 {
1560 struct drm_info_node *node = m->private;
1561 struct drm_device *dev = node->minor->dev;
1562 struct drm_i915_private *dev_priv = dev->dev_private;
1563 unsigned long temp, chipset, gfx;
1564 int ret;
1565
1566 if (!IS_GEN5(dev))
1567 return -ENODEV;
1568
1569 ret = mutex_lock_interruptible(&dev->struct_mutex);
1570 if (ret)
1571 return ret;
1572
1573 temp = i915_mch_val(dev_priv);
1574 chipset = i915_chipset_val(dev_priv);
1575 gfx = i915_gfx_val(dev_priv);
1576 mutex_unlock(&dev->struct_mutex);
1577
1578 seq_printf(m, "GMCH temp: %ld\n", temp);
1579 seq_printf(m, "Chipset power: %ld\n", chipset);
1580 seq_printf(m, "GFX power: %ld\n", gfx);
1581 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1582
1583 return 0;
1584 }
1585
1586 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1587 {
1588 struct drm_info_node *node = m->private;
1589 struct drm_device *dev = node->minor->dev;
1590 struct drm_i915_private *dev_priv = dev->dev_private;
1591 int ret = 0;
1592 int gpu_freq, ia_freq;
1593
1594 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1595 seq_puts(m, "unsupported on this chipset\n");
1596 return 0;
1597 }
1598
1599 intel_runtime_pm_get(dev_priv);
1600
1601 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1602
1603 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1604 if (ret)
1605 goto out;
1606
1607 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1608
1609 for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1610 gpu_freq <= dev_priv->rps.max_freq_softlimit;
1611 gpu_freq++) {
1612 ia_freq = gpu_freq;
1613 sandybridge_pcode_read(dev_priv,
1614 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1615 &ia_freq);
1616 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1617 gpu_freq * GT_FREQUENCY_MULTIPLIER,
1618 ((ia_freq >> 0) & 0xff) * 100,
1619 ((ia_freq >> 8) & 0xff) * 100);
1620 }
1621
1622 mutex_unlock(&dev_priv->rps.hw_lock);
1623
1624 out:
1625 intel_runtime_pm_put(dev_priv);
1626 return ret;
1627 }
1628
1629 static int i915_gfxec(struct seq_file *m, void *unused)
1630 {
1631 struct drm_info_node *node = m->private;
1632 struct drm_device *dev = node->minor->dev;
1633 struct drm_i915_private *dev_priv = dev->dev_private;
1634 int ret;
1635
1636 ret = mutex_lock_interruptible(&dev->struct_mutex);
1637 if (ret)
1638 return ret;
1639 intel_runtime_pm_get(dev_priv);
1640
1641 seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1642 intel_runtime_pm_put(dev_priv);
1643
1644 mutex_unlock(&dev->struct_mutex);
1645
1646 return 0;
1647 }
1648
1649 static int i915_opregion(struct seq_file *m, void *unused)
1650 {
1651 struct drm_info_node *node = m->private;
1652 struct drm_device *dev = node->minor->dev;
1653 struct drm_i915_private *dev_priv = dev->dev_private;
1654 struct intel_opregion *opregion = &dev_priv->opregion;
1655 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1656 int ret;
1657
1658 if (data == NULL)
1659 return -ENOMEM;
1660
1661 ret = mutex_lock_interruptible(&dev->struct_mutex);
1662 if (ret)
1663 goto out;
1664
1665 if (opregion->header) {
1666 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1667 seq_write(m, data, OPREGION_SIZE);
1668 }
1669
1670 mutex_unlock(&dev->struct_mutex);
1671
1672 out:
1673 kfree(data);
1674 return 0;
1675 }
1676
1677 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1678 {
1679 struct drm_info_node *node = m->private;
1680 struct drm_device *dev = node->minor->dev;
1681 struct intel_fbdev *ifbdev = NULL;
1682 struct intel_framebuffer *fb;
1683
1684 #ifdef CONFIG_DRM_I915_FBDEV
1685 struct drm_i915_private *dev_priv = dev->dev_private;
1686
1687 ifbdev = dev_priv->fbdev;
1688 fb = to_intel_framebuffer(ifbdev->helper.fb);
1689
1690 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1691 fb->base.width,
1692 fb->base.height,
1693 fb->base.depth,
1694 fb->base.bits_per_pixel,
1695 atomic_read(&fb->base.refcount.refcount));
1696 describe_obj(m, fb->obj);
1697 seq_putc(m, '\n');
1698 #endif
1699
1700 mutex_lock(&dev->mode_config.fb_lock);
1701 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1702 if (ifbdev && &fb->base == ifbdev->helper.fb)
1703 continue;
1704
1705 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1706 fb->base.width,
1707 fb->base.height,
1708 fb->base.depth,
1709 fb->base.bits_per_pixel,
1710 atomic_read(&fb->base.refcount.refcount));
1711 describe_obj(m, fb->obj);
1712 seq_putc(m, '\n');
1713 }
1714 mutex_unlock(&dev->mode_config.fb_lock);
1715
1716 return 0;
1717 }
1718
1719 static int i915_context_status(struct seq_file *m, void *unused)
1720 {
1721 struct drm_info_node *node = m->private;
1722 struct drm_device *dev = node->minor->dev;
1723 struct drm_i915_private *dev_priv = dev->dev_private;
1724 struct intel_engine_cs *ring;
1725 struct intel_context *ctx;
1726 int ret, i;
1727
1728 ret = mutex_lock_interruptible(&dev->struct_mutex);
1729 if (ret)
1730 return ret;
1731
1732 if (dev_priv->ips.pwrctx) {
1733 seq_puts(m, "power context ");
1734 describe_obj(m, dev_priv->ips.pwrctx);
1735 seq_putc(m, '\n');
1736 }
1737
1738 if (dev_priv->ips.renderctx) {
1739 seq_puts(m, "render context ");
1740 describe_obj(m, dev_priv->ips.renderctx);
1741 seq_putc(m, '\n');
1742 }
1743
1744 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1745 if (ctx->obj == NULL)
1746 continue;
1747
1748 seq_puts(m, "HW context ");
1749 describe_ctx(m, ctx);
1750 for_each_ring(ring, dev_priv, i)
1751 if (ring->default_context == ctx)
1752 seq_printf(m, "(default context %s) ", ring->name);
1753
1754 describe_obj(m, ctx->obj);
1755 seq_putc(m, '\n');
1756 }
1757
1758 mutex_unlock(&dev->struct_mutex);
1759
1760 return 0;
1761 }
1762
1763 static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1764 {
1765 struct drm_info_node *node = m->private;
1766 struct drm_device *dev = node->minor->dev;
1767 struct drm_i915_private *dev_priv = dev->dev_private;
1768 unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0;
1769
1770 spin_lock_irq(&dev_priv->uncore.lock);
1771 if (IS_VALLEYVIEW(dev)) {
1772 fw_rendercount = dev_priv->uncore.fw_rendercount;
1773 fw_mediacount = dev_priv->uncore.fw_mediacount;
1774 } else
1775 forcewake_count = dev_priv->uncore.forcewake_count;
1776 spin_unlock_irq(&dev_priv->uncore.lock);
1777
1778 if (IS_VALLEYVIEW(dev)) {
1779 seq_printf(m, "fw_rendercount = %u\n", fw_rendercount);
1780 seq_printf(m, "fw_mediacount = %u\n", fw_mediacount);
1781 } else
1782 seq_printf(m, "forcewake count = %u\n", forcewake_count);
1783
1784 return 0;
1785 }
1786
1787 static const char *swizzle_string(unsigned swizzle)
1788 {
1789 switch (swizzle) {
1790 case I915_BIT_6_SWIZZLE_NONE:
1791 return "none";
1792 case I915_BIT_6_SWIZZLE_9:
1793 return "bit9";
1794 case I915_BIT_6_SWIZZLE_9_10:
1795 return "bit9/bit10";
1796 case I915_BIT_6_SWIZZLE_9_11:
1797 return "bit9/bit11";
1798 case I915_BIT_6_SWIZZLE_9_10_11:
1799 return "bit9/bit10/bit11";
1800 case I915_BIT_6_SWIZZLE_9_17:
1801 return "bit9/bit17";
1802 case I915_BIT_6_SWIZZLE_9_10_17:
1803 return "bit9/bit10/bit17";
1804 case I915_BIT_6_SWIZZLE_UNKNOWN:
1805 return "unknown";
1806 }
1807
1808 return "bug";
1809 }
1810
1811 static int i915_swizzle_info(struct seq_file *m, void *data)
1812 {
1813 struct drm_info_node *node = m->private;
1814 struct drm_device *dev = node->minor->dev;
1815 struct drm_i915_private *dev_priv = dev->dev_private;
1816 int ret;
1817
1818 ret = mutex_lock_interruptible(&dev->struct_mutex);
1819 if (ret)
1820 return ret;
1821 intel_runtime_pm_get(dev_priv);
1822
1823 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1824 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1825 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1826 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1827
1828 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1829 seq_printf(m, "DDC = 0x%08x\n",
1830 I915_READ(DCC));
1831 seq_printf(m, "C0DRB3 = 0x%04x\n",
1832 I915_READ16(C0DRB3));
1833 seq_printf(m, "C1DRB3 = 0x%04x\n",
1834 I915_READ16(C1DRB3));
1835 } else if (INTEL_INFO(dev)->gen >= 6) {
1836 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1837 I915_READ(MAD_DIMM_C0));
1838 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1839 I915_READ(MAD_DIMM_C1));
1840 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1841 I915_READ(MAD_DIMM_C2));
1842 seq_printf(m, "TILECTL = 0x%08x\n",
1843 I915_READ(TILECTL));
1844 if (IS_GEN8(dev))
1845 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
1846 I915_READ(GAMTARBMODE));
1847 else
1848 seq_printf(m, "ARB_MODE = 0x%08x\n",
1849 I915_READ(ARB_MODE));
1850 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1851 I915_READ(DISP_ARB_CTL));
1852 }
1853 intel_runtime_pm_put(dev_priv);
1854 mutex_unlock(&dev->struct_mutex);
1855
1856 return 0;
1857 }
1858
1859 static int per_file_ctx(int id, void *ptr, void *data)
1860 {
1861 struct intel_context *ctx = ptr;
1862 struct seq_file *m = data;
1863 struct i915_hw_ppgtt *ppgtt = ctx_to_ppgtt(ctx);
1864
1865 if (i915_gem_context_is_default(ctx))
1866 seq_puts(m, " default context:\n");
1867 else
1868 seq_printf(m, " context %d:\n", ctx->id);
1869 ppgtt->debug_dump(ppgtt, m);
1870
1871 return 0;
1872 }
1873
1874 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
1875 {
1876 struct drm_i915_private *dev_priv = dev->dev_private;
1877 struct intel_engine_cs *ring;
1878 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1879 int unused, i;
1880
1881 if (!ppgtt)
1882 return;
1883
1884 seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
1885 seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
1886 for_each_ring(ring, dev_priv, unused) {
1887 seq_printf(m, "%s\n", ring->name);
1888 for (i = 0; i < 4; i++) {
1889 u32 offset = 0x270 + i * 8;
1890 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
1891 pdp <<= 32;
1892 pdp |= I915_READ(ring->mmio_base + offset);
1893 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
1894 }
1895 }
1896 }
1897
1898 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
1899 {
1900 struct drm_i915_private *dev_priv = dev->dev_private;
1901 struct intel_engine_cs *ring;
1902 struct drm_file *file;
1903 int i;
1904
1905 if (INTEL_INFO(dev)->gen == 6)
1906 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1907
1908 for_each_ring(ring, dev_priv, i) {
1909 seq_printf(m, "%s\n", ring->name);
1910 if (INTEL_INFO(dev)->gen == 7)
1911 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1912 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1913 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1914 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1915 }
1916 if (dev_priv->mm.aliasing_ppgtt) {
1917 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1918
1919 seq_puts(m, "aliasing PPGTT:\n");
1920 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1921
1922 ppgtt->debug_dump(ppgtt, m);
1923 } else
1924 return;
1925
1926 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
1927 struct drm_i915_file_private *file_priv = file->driver_priv;
1928
1929 seq_printf(m, "proc: %s\n",
1930 get_pid_task(file->pid, PIDTYPE_PID)->comm);
1931 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
1932 }
1933 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
1934 }
1935
1936 static int i915_ppgtt_info(struct seq_file *m, void *data)
1937 {
1938 struct drm_info_node *node = m->private;
1939 struct drm_device *dev = node->minor->dev;
1940 struct drm_i915_private *dev_priv = dev->dev_private;
1941
1942 int ret = mutex_lock_interruptible(&dev->struct_mutex);
1943 if (ret)
1944 return ret;
1945 intel_runtime_pm_get(dev_priv);
1946
1947 if (INTEL_INFO(dev)->gen >= 8)
1948 gen8_ppgtt_info(m, dev);
1949 else if (INTEL_INFO(dev)->gen >= 6)
1950 gen6_ppgtt_info(m, dev);
1951
1952 intel_runtime_pm_put(dev_priv);
1953 mutex_unlock(&dev->struct_mutex);
1954
1955 return 0;
1956 }
1957
1958 static int i915_llc(struct seq_file *m, void *data)
1959 {
1960 struct drm_info_node *node = m->private;
1961 struct drm_device *dev = node->minor->dev;
1962 struct drm_i915_private *dev_priv = dev->dev_private;
1963
1964 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
1965 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
1966 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
1967
1968 return 0;
1969 }
1970
1971 static int i915_edp_psr_status(struct seq_file *m, void *data)
1972 {
1973 struct drm_info_node *node = m->private;
1974 struct drm_device *dev = node->minor->dev;
1975 struct drm_i915_private *dev_priv = dev->dev_private;
1976 u32 psrperf = 0;
1977 bool enabled = false;
1978
1979 intel_runtime_pm_get(dev_priv);
1980
1981 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
1982 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
1983 seq_printf(m, "Enabled: %s\n", yesno(dev_priv->psr.enabled));
1984 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
1985
1986 enabled = HAS_PSR(dev) &&
1987 I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1988 seq_printf(m, "HW Enabled & Active bit: %s\n", yesno(enabled));
1989
1990 if (HAS_PSR(dev))
1991 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
1992 EDP_PSR_PERF_CNT_MASK;
1993 seq_printf(m, "Performance_Counter: %u\n", psrperf);
1994
1995 intel_runtime_pm_put(dev_priv);
1996 return 0;
1997 }
1998
1999 static int i915_sink_crc(struct seq_file *m, void *data)
2000 {
2001 struct drm_info_node *node = m->private;
2002 struct drm_device *dev = node->minor->dev;
2003 struct intel_encoder *encoder;
2004 struct intel_connector *connector;
2005 struct intel_dp *intel_dp = NULL;
2006 int ret;
2007 u8 crc[6];
2008
2009 drm_modeset_lock_all(dev);
2010 list_for_each_entry(connector, &dev->mode_config.connector_list,
2011 base.head) {
2012
2013 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2014 continue;
2015
2016 if (!connector->base.encoder)
2017 continue;
2018
2019 encoder = to_intel_encoder(connector->base.encoder);
2020 if (encoder->type != INTEL_OUTPUT_EDP)
2021 continue;
2022
2023 intel_dp = enc_to_intel_dp(&encoder->base);
2024
2025 ret = intel_dp_sink_crc(intel_dp, crc);
2026 if (ret)
2027 goto out;
2028
2029 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2030 crc[0], crc[1], crc[2],
2031 crc[3], crc[4], crc[5]);
2032 goto out;
2033 }
2034 ret = -ENODEV;
2035 out:
2036 drm_modeset_unlock_all(dev);
2037 return ret;
2038 }
2039
2040 static int i915_energy_uJ(struct seq_file *m, void *data)
2041 {
2042 struct drm_info_node *node = m->private;
2043 struct drm_device *dev = node->minor->dev;
2044 struct drm_i915_private *dev_priv = dev->dev_private;
2045 u64 power;
2046 u32 units;
2047
2048 if (INTEL_INFO(dev)->gen < 6)
2049 return -ENODEV;
2050
2051 intel_runtime_pm_get(dev_priv);
2052
2053 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2054 power = (power & 0x1f00) >> 8;
2055 units = 1000000 / (1 << power); /* convert to uJ */
2056 power = I915_READ(MCH_SECP_NRG_STTS);
2057 power *= units;
2058
2059 intel_runtime_pm_put(dev_priv);
2060
2061 seq_printf(m, "%llu", (long long unsigned)power);
2062
2063 return 0;
2064 }
2065
2066 static int i915_pc8_status(struct seq_file *m, void *unused)
2067 {
2068 struct drm_info_node *node = m->private;
2069 struct drm_device *dev = node->minor->dev;
2070 struct drm_i915_private *dev_priv = dev->dev_private;
2071
2072 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2073 seq_puts(m, "not supported\n");
2074 return 0;
2075 }
2076
2077 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2078 seq_printf(m, "IRQs disabled: %s\n",
2079 yesno(dev_priv->pm.irqs_disabled));
2080
2081 return 0;
2082 }
2083
2084 static const char *power_domain_str(enum intel_display_power_domain domain)
2085 {
2086 switch (domain) {
2087 case POWER_DOMAIN_PIPE_A:
2088 return "PIPE_A";
2089 case POWER_DOMAIN_PIPE_B:
2090 return "PIPE_B";
2091 case POWER_DOMAIN_PIPE_C:
2092 return "PIPE_C";
2093 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2094 return "PIPE_A_PANEL_FITTER";
2095 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2096 return "PIPE_B_PANEL_FITTER";
2097 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2098 return "PIPE_C_PANEL_FITTER";
2099 case POWER_DOMAIN_TRANSCODER_A:
2100 return "TRANSCODER_A";
2101 case POWER_DOMAIN_TRANSCODER_B:
2102 return "TRANSCODER_B";
2103 case POWER_DOMAIN_TRANSCODER_C:
2104 return "TRANSCODER_C";
2105 case POWER_DOMAIN_TRANSCODER_EDP:
2106 return "TRANSCODER_EDP";
2107 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2108 return "PORT_DDI_A_2_LANES";
2109 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2110 return "PORT_DDI_A_4_LANES";
2111 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2112 return "PORT_DDI_B_2_LANES";
2113 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2114 return "PORT_DDI_B_4_LANES";
2115 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2116 return "PORT_DDI_C_2_LANES";
2117 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2118 return "PORT_DDI_C_4_LANES";
2119 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2120 return "PORT_DDI_D_2_LANES";
2121 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2122 return "PORT_DDI_D_4_LANES";
2123 case POWER_DOMAIN_PORT_DSI:
2124 return "PORT_DSI";
2125 case POWER_DOMAIN_PORT_CRT:
2126 return "PORT_CRT";
2127 case POWER_DOMAIN_PORT_OTHER:
2128 return "PORT_OTHER";
2129 case POWER_DOMAIN_VGA:
2130 return "VGA";
2131 case POWER_DOMAIN_AUDIO:
2132 return "AUDIO";
2133 case POWER_DOMAIN_INIT:
2134 return "INIT";
2135 default:
2136 WARN_ON(1);
2137 return "?";
2138 }
2139 }
2140
2141 static int i915_power_domain_info(struct seq_file *m, void *unused)
2142 {
2143 struct drm_info_node *node = m->private;
2144 struct drm_device *dev = node->minor->dev;
2145 struct drm_i915_private *dev_priv = dev->dev_private;
2146 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2147 int i;
2148
2149 mutex_lock(&power_domains->lock);
2150
2151 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2152 for (i = 0; i < power_domains->power_well_count; i++) {
2153 struct i915_power_well *power_well;
2154 enum intel_display_power_domain power_domain;
2155
2156 power_well = &power_domains->power_wells[i];
2157 seq_printf(m, "%-25s %d\n", power_well->name,
2158 power_well->count);
2159
2160 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2161 power_domain++) {
2162 if (!(BIT(power_domain) & power_well->domains))
2163 continue;
2164
2165 seq_printf(m, " %-23s %d\n",
2166 power_domain_str(power_domain),
2167 power_domains->domain_use_count[power_domain]);
2168 }
2169 }
2170
2171 mutex_unlock(&power_domains->lock);
2172
2173 return 0;
2174 }
2175
2176 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2177 struct drm_display_mode *mode)
2178 {
2179 int i;
2180
2181 for (i = 0; i < tabs; i++)
2182 seq_putc(m, '\t');
2183
2184 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2185 mode->base.id, mode->name,
2186 mode->vrefresh, mode->clock,
2187 mode->hdisplay, mode->hsync_start,
2188 mode->hsync_end, mode->htotal,
2189 mode->vdisplay, mode->vsync_start,
2190 mode->vsync_end, mode->vtotal,
2191 mode->type, mode->flags);
2192 }
2193
2194 static void intel_encoder_info(struct seq_file *m,
2195 struct intel_crtc *intel_crtc,
2196 struct intel_encoder *intel_encoder)
2197 {
2198 struct drm_info_node *node = m->private;
2199 struct drm_device *dev = node->minor->dev;
2200 struct drm_crtc *crtc = &intel_crtc->base;
2201 struct intel_connector *intel_connector;
2202 struct drm_encoder *encoder;
2203
2204 encoder = &intel_encoder->base;
2205 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2206 encoder->base.id, encoder->name);
2207 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2208 struct drm_connector *connector = &intel_connector->base;
2209 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2210 connector->base.id,
2211 connector->name,
2212 drm_get_connector_status_name(connector->status));
2213 if (connector->status == connector_status_connected) {
2214 struct drm_display_mode *mode = &crtc->mode;
2215 seq_printf(m, ", mode:\n");
2216 intel_seq_print_mode(m, 2, mode);
2217 } else {
2218 seq_putc(m, '\n');
2219 }
2220 }
2221 }
2222
2223 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2224 {
2225 struct drm_info_node *node = m->private;
2226 struct drm_device *dev = node->minor->dev;
2227 struct drm_crtc *crtc = &intel_crtc->base;
2228 struct intel_encoder *intel_encoder;
2229
2230 if (crtc->primary->fb)
2231 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2232 crtc->primary->fb->base.id, crtc->x, crtc->y,
2233 crtc->primary->fb->width, crtc->primary->fb->height);
2234 else
2235 seq_puts(m, "\tprimary plane disabled\n");
2236 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2237 intel_encoder_info(m, intel_crtc, intel_encoder);
2238 }
2239
2240 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2241 {
2242 struct drm_display_mode *mode = panel->fixed_mode;
2243
2244 seq_printf(m, "\tfixed mode:\n");
2245 intel_seq_print_mode(m, 2, mode);
2246 }
2247
2248 static void intel_dp_info(struct seq_file *m,
2249 struct intel_connector *intel_connector)
2250 {
2251 struct intel_encoder *intel_encoder = intel_connector->encoder;
2252 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2253
2254 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2255 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2256 "no");
2257 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2258 intel_panel_info(m, &intel_connector->panel);
2259 }
2260
2261 static void intel_hdmi_info(struct seq_file *m,
2262 struct intel_connector *intel_connector)
2263 {
2264 struct intel_encoder *intel_encoder = intel_connector->encoder;
2265 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2266
2267 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2268 "no");
2269 }
2270
2271 static void intel_lvds_info(struct seq_file *m,
2272 struct intel_connector *intel_connector)
2273 {
2274 intel_panel_info(m, &intel_connector->panel);
2275 }
2276
2277 static void intel_connector_info(struct seq_file *m,
2278 struct drm_connector *connector)
2279 {
2280 struct intel_connector *intel_connector = to_intel_connector(connector);
2281 struct intel_encoder *intel_encoder = intel_connector->encoder;
2282 struct drm_display_mode *mode;
2283
2284 seq_printf(m, "connector %d: type %s, status: %s\n",
2285 connector->base.id, connector->name,
2286 drm_get_connector_status_name(connector->status));
2287 if (connector->status == connector_status_connected) {
2288 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2289 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2290 connector->display_info.width_mm,
2291 connector->display_info.height_mm);
2292 seq_printf(m, "\tsubpixel order: %s\n",
2293 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2294 seq_printf(m, "\tCEA rev: %d\n",
2295 connector->display_info.cea_rev);
2296 }
2297 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2298 intel_encoder->type == INTEL_OUTPUT_EDP)
2299 intel_dp_info(m, intel_connector);
2300 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2301 intel_hdmi_info(m, intel_connector);
2302 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2303 intel_lvds_info(m, intel_connector);
2304
2305 seq_printf(m, "\tmodes:\n");
2306 list_for_each_entry(mode, &connector->modes, head)
2307 intel_seq_print_mode(m, 2, mode);
2308 }
2309
2310 static bool cursor_active(struct drm_device *dev, int pipe)
2311 {
2312 struct drm_i915_private *dev_priv = dev->dev_private;
2313 u32 state;
2314
2315 if (IS_845G(dev) || IS_I865G(dev))
2316 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
2317 else
2318 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2319
2320 return state;
2321 }
2322
2323 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2324 {
2325 struct drm_i915_private *dev_priv = dev->dev_private;
2326 u32 pos;
2327
2328 pos = I915_READ(CURPOS(pipe));
2329
2330 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2331 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2332 *x = -*x;
2333
2334 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2335 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2336 *y = -*y;
2337
2338 return cursor_active(dev, pipe);
2339 }
2340
2341 static int i915_display_info(struct seq_file *m, void *unused)
2342 {
2343 struct drm_info_node *node = m->private;
2344 struct drm_device *dev = node->minor->dev;
2345 struct drm_i915_private *dev_priv = dev->dev_private;
2346 struct intel_crtc *crtc;
2347 struct drm_connector *connector;
2348
2349 intel_runtime_pm_get(dev_priv);
2350 drm_modeset_lock_all(dev);
2351 seq_printf(m, "CRTC info\n");
2352 seq_printf(m, "---------\n");
2353 for_each_intel_crtc(dev, crtc) {
2354 bool active;
2355 int x, y;
2356
2357 seq_printf(m, "CRTC %d: pipe: %c, active: %s\n",
2358 crtc->base.base.id, pipe_name(crtc->pipe),
2359 yesno(crtc->active));
2360 if (crtc->active) {
2361 intel_crtc_info(m, crtc);
2362
2363 active = cursor_position(dev, crtc->pipe, &x, &y);
2364 seq_printf(m, "\tcursor visible? %s, position (%d, %d), addr 0x%08x, active? %s\n",
2365 yesno(crtc->cursor_base),
2366 x, y, crtc->cursor_addr,
2367 yesno(active));
2368 }
2369
2370 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2371 yesno(!crtc->cpu_fifo_underrun_disabled),
2372 yesno(!crtc->pch_fifo_underrun_disabled));
2373 }
2374
2375 seq_printf(m, "\n");
2376 seq_printf(m, "Connector info\n");
2377 seq_printf(m, "--------------\n");
2378 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2379 intel_connector_info(m, connector);
2380 }
2381 drm_modeset_unlock_all(dev);
2382 intel_runtime_pm_put(dev_priv);
2383
2384 return 0;
2385 }
2386
2387 struct pipe_crc_info {
2388 const char *name;
2389 struct drm_device *dev;
2390 enum pipe pipe;
2391 };
2392
2393 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
2394 {
2395 struct pipe_crc_info *info = inode->i_private;
2396 struct drm_i915_private *dev_priv = info->dev->dev_private;
2397 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2398
2399 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
2400 return -ENODEV;
2401
2402 spin_lock_irq(&pipe_crc->lock);
2403
2404 if (pipe_crc->opened) {
2405 spin_unlock_irq(&pipe_crc->lock);
2406 return -EBUSY; /* already open */
2407 }
2408
2409 pipe_crc->opened = true;
2410 filep->private_data = inode->i_private;
2411
2412 spin_unlock_irq(&pipe_crc->lock);
2413
2414 return 0;
2415 }
2416
2417 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
2418 {
2419 struct pipe_crc_info *info = inode->i_private;
2420 struct drm_i915_private *dev_priv = info->dev->dev_private;
2421 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2422
2423 spin_lock_irq(&pipe_crc->lock);
2424 pipe_crc->opened = false;
2425 spin_unlock_irq(&pipe_crc->lock);
2426
2427 return 0;
2428 }
2429
2430 /* (6 fields, 8 chars each, space separated (5) + '\n') */
2431 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
2432 /* account for \'0' */
2433 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
2434
2435 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
2436 {
2437 assert_spin_locked(&pipe_crc->lock);
2438 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2439 INTEL_PIPE_CRC_ENTRIES_NR);
2440 }
2441
2442 static ssize_t
2443 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
2444 loff_t *pos)
2445 {
2446 struct pipe_crc_info *info = filep->private_data;
2447 struct drm_device *dev = info->dev;
2448 struct drm_i915_private *dev_priv = dev->dev_private;
2449 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2450 char buf[PIPE_CRC_BUFFER_LEN];
2451 int head, tail, n_entries, n;
2452 ssize_t bytes_read;
2453
2454 /*
2455 * Don't allow user space to provide buffers not big enough to hold
2456 * a line of data.
2457 */
2458 if (count < PIPE_CRC_LINE_LEN)
2459 return -EINVAL;
2460
2461 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
2462 return 0;
2463
2464 /* nothing to read */
2465 spin_lock_irq(&pipe_crc->lock);
2466 while (pipe_crc_data_count(pipe_crc) == 0) {
2467 int ret;
2468
2469 if (filep->f_flags & O_NONBLOCK) {
2470 spin_unlock_irq(&pipe_crc->lock);
2471 return -EAGAIN;
2472 }
2473
2474 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2475 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2476 if (ret) {
2477 spin_unlock_irq(&pipe_crc->lock);
2478 return ret;
2479 }
2480 }
2481
2482 /* We now have one or more entries to read */
2483 head = pipe_crc->head;
2484 tail = pipe_crc->tail;
2485 n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR),
2486 count / PIPE_CRC_LINE_LEN);
2487 spin_unlock_irq(&pipe_crc->lock);
2488
2489 bytes_read = 0;
2490 n = 0;
2491 do {
2492 struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail];
2493 int ret;
2494
2495 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
2496 "%8u %8x %8x %8x %8x %8x\n",
2497 entry->frame, entry->crc[0],
2498 entry->crc[1], entry->crc[2],
2499 entry->crc[3], entry->crc[4]);
2500
2501 ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN,
2502 buf, PIPE_CRC_LINE_LEN);
2503 if (ret == PIPE_CRC_LINE_LEN)
2504 return -EFAULT;
2505
2506 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
2507 tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
2508 n++;
2509 } while (--n_entries);
2510
2511 spin_lock_irq(&pipe_crc->lock);
2512 pipe_crc->tail = tail;
2513 spin_unlock_irq(&pipe_crc->lock);
2514
2515 return bytes_read;
2516 }
2517
2518 static const struct file_operations i915_pipe_crc_fops = {
2519 .owner = THIS_MODULE,
2520 .open = i915_pipe_crc_open,
2521 .read = i915_pipe_crc_read,
2522 .release = i915_pipe_crc_release,
2523 };
2524
2525 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
2526 {
2527 .name = "i915_pipe_A_crc",
2528 .pipe = PIPE_A,
2529 },
2530 {
2531 .name = "i915_pipe_B_crc",
2532 .pipe = PIPE_B,
2533 },
2534 {
2535 .name = "i915_pipe_C_crc",
2536 .pipe = PIPE_C,
2537 },
2538 };
2539
2540 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
2541 enum pipe pipe)
2542 {
2543 struct drm_device *dev = minor->dev;
2544 struct dentry *ent;
2545 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
2546
2547 info->dev = dev;
2548 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
2549 &i915_pipe_crc_fops);
2550 if (!ent)
2551 return -ENOMEM;
2552
2553 return drm_add_fake_info_node(minor, ent, info);
2554 }
2555
2556 static const char * const pipe_crc_sources[] = {
2557 "none",
2558 "plane1",
2559 "plane2",
2560 "pf",
2561 "pipe",
2562 "TV",
2563 "DP-B",
2564 "DP-C",
2565 "DP-D",
2566 "auto",
2567 };
2568
2569 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
2570 {
2571 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
2572 return pipe_crc_sources[source];
2573 }
2574
2575 static int display_crc_ctl_show(struct seq_file *m, void *data)
2576 {
2577 struct drm_device *dev = m->private;
2578 struct drm_i915_private *dev_priv = dev->dev_private;
2579 int i;
2580
2581 for (i = 0; i < I915_MAX_PIPES; i++)
2582 seq_printf(m, "%c %s\n", pipe_name(i),
2583 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
2584
2585 return 0;
2586 }
2587
2588 static int display_crc_ctl_open(struct inode *inode, struct file *file)
2589 {
2590 struct drm_device *dev = inode->i_private;
2591
2592 return single_open(file, display_crc_ctl_show, dev);
2593 }
2594
2595 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
2596 uint32_t *val)
2597 {
2598 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2599 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2600
2601 switch (*source) {
2602 case INTEL_PIPE_CRC_SOURCE_PIPE:
2603 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
2604 break;
2605 case INTEL_PIPE_CRC_SOURCE_NONE:
2606 *val = 0;
2607 break;
2608 default:
2609 return -EINVAL;
2610 }
2611
2612 return 0;
2613 }
2614
2615 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
2616 enum intel_pipe_crc_source *source)
2617 {
2618 struct intel_encoder *encoder;
2619 struct intel_crtc *crtc;
2620 struct intel_digital_port *dig_port;
2621 int ret = 0;
2622
2623 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2624
2625 drm_modeset_lock_all(dev);
2626 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2627 base.head) {
2628 if (!encoder->base.crtc)
2629 continue;
2630
2631 crtc = to_intel_crtc(encoder->base.crtc);
2632
2633 if (crtc->pipe != pipe)
2634 continue;
2635
2636 switch (encoder->type) {
2637 case INTEL_OUTPUT_TVOUT:
2638 *source = INTEL_PIPE_CRC_SOURCE_TV;
2639 break;
2640 case INTEL_OUTPUT_DISPLAYPORT:
2641 case INTEL_OUTPUT_EDP:
2642 dig_port = enc_to_dig_port(&encoder->base);
2643 switch (dig_port->port) {
2644 case PORT_B:
2645 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
2646 break;
2647 case PORT_C:
2648 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
2649 break;
2650 case PORT_D:
2651 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
2652 break;
2653 default:
2654 WARN(1, "nonexisting DP port %c\n",
2655 port_name(dig_port->port));
2656 break;
2657 }
2658 break;
2659 }
2660 }
2661 drm_modeset_unlock_all(dev);
2662
2663 return ret;
2664 }
2665
2666 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
2667 enum pipe pipe,
2668 enum intel_pipe_crc_source *source,
2669 uint32_t *val)
2670 {
2671 struct drm_i915_private *dev_priv = dev->dev_private;
2672 bool need_stable_symbols = false;
2673
2674 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2675 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2676 if (ret)
2677 return ret;
2678 }
2679
2680 switch (*source) {
2681 case INTEL_PIPE_CRC_SOURCE_PIPE:
2682 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
2683 break;
2684 case INTEL_PIPE_CRC_SOURCE_DP_B:
2685 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
2686 need_stable_symbols = true;
2687 break;
2688 case INTEL_PIPE_CRC_SOURCE_DP_C:
2689 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
2690 need_stable_symbols = true;
2691 break;
2692 case INTEL_PIPE_CRC_SOURCE_NONE:
2693 *val = 0;
2694 break;
2695 default:
2696 return -EINVAL;
2697 }
2698
2699 /*
2700 * When the pipe CRC tap point is after the transcoders we need
2701 * to tweak symbol-level features to produce a deterministic series of
2702 * symbols for a given frame. We need to reset those features only once
2703 * a frame (instead of every nth symbol):
2704 * - DC-balance: used to ensure a better clock recovery from the data
2705 * link (SDVO)
2706 * - DisplayPort scrambling: used for EMI reduction
2707 */
2708 if (need_stable_symbols) {
2709 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2710
2711 tmp |= DC_BALANCE_RESET_VLV;
2712 if (pipe == PIPE_A)
2713 tmp |= PIPE_A_SCRAMBLE_RESET;
2714 else
2715 tmp |= PIPE_B_SCRAMBLE_RESET;
2716
2717 I915_WRITE(PORT_DFT2_G4X, tmp);
2718 }
2719
2720 return 0;
2721 }
2722
2723 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
2724 enum pipe pipe,
2725 enum intel_pipe_crc_source *source,
2726 uint32_t *val)
2727 {
2728 struct drm_i915_private *dev_priv = dev->dev_private;
2729 bool need_stable_symbols = false;
2730
2731 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2732 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2733 if (ret)
2734 return ret;
2735 }
2736
2737 switch (*source) {
2738 case INTEL_PIPE_CRC_SOURCE_PIPE:
2739 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
2740 break;
2741 case INTEL_PIPE_CRC_SOURCE_TV:
2742 if (!SUPPORTS_TV(dev))
2743 return -EINVAL;
2744 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
2745 break;
2746 case INTEL_PIPE_CRC_SOURCE_DP_B:
2747 if (!IS_G4X(dev))
2748 return -EINVAL;
2749 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
2750 need_stable_symbols = true;
2751 break;
2752 case INTEL_PIPE_CRC_SOURCE_DP_C:
2753 if (!IS_G4X(dev))
2754 return -EINVAL;
2755 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
2756 need_stable_symbols = true;
2757 break;
2758 case INTEL_PIPE_CRC_SOURCE_DP_D:
2759 if (!IS_G4X(dev))
2760 return -EINVAL;
2761 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
2762 need_stable_symbols = true;
2763 break;
2764 case INTEL_PIPE_CRC_SOURCE_NONE:
2765 *val = 0;
2766 break;
2767 default:
2768 return -EINVAL;
2769 }
2770
2771 /*
2772 * When the pipe CRC tap point is after the transcoders we need
2773 * to tweak symbol-level features to produce a deterministic series of
2774 * symbols for a given frame. We need to reset those features only once
2775 * a frame (instead of every nth symbol):
2776 * - DC-balance: used to ensure a better clock recovery from the data
2777 * link (SDVO)
2778 * - DisplayPort scrambling: used for EMI reduction
2779 */
2780 if (need_stable_symbols) {
2781 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2782
2783 WARN_ON(!IS_G4X(dev));
2784
2785 I915_WRITE(PORT_DFT_I9XX,
2786 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
2787
2788 if (pipe == PIPE_A)
2789 tmp |= PIPE_A_SCRAMBLE_RESET;
2790 else
2791 tmp |= PIPE_B_SCRAMBLE_RESET;
2792
2793 I915_WRITE(PORT_DFT2_G4X, tmp);
2794 }
2795
2796 return 0;
2797 }
2798
2799 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
2800 enum pipe pipe)
2801 {
2802 struct drm_i915_private *dev_priv = dev->dev_private;
2803 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2804
2805 if (pipe == PIPE_A)
2806 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2807 else
2808 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2809 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
2810 tmp &= ~DC_BALANCE_RESET_VLV;
2811 I915_WRITE(PORT_DFT2_G4X, tmp);
2812
2813 }
2814
2815 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
2816 enum pipe pipe)
2817 {
2818 struct drm_i915_private *dev_priv = dev->dev_private;
2819 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2820
2821 if (pipe == PIPE_A)
2822 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2823 else
2824 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2825 I915_WRITE(PORT_DFT2_G4X, tmp);
2826
2827 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
2828 I915_WRITE(PORT_DFT_I9XX,
2829 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
2830 }
2831 }
2832
2833 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
2834 uint32_t *val)
2835 {
2836 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2837 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2838
2839 switch (*source) {
2840 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2841 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
2842 break;
2843 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2844 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
2845 break;
2846 case INTEL_PIPE_CRC_SOURCE_PIPE:
2847 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
2848 break;
2849 case INTEL_PIPE_CRC_SOURCE_NONE:
2850 *val = 0;
2851 break;
2852 default:
2853 return -EINVAL;
2854 }
2855
2856 return 0;
2857 }
2858
2859 static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
2860 uint32_t *val)
2861 {
2862 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2863 *source = INTEL_PIPE_CRC_SOURCE_PF;
2864
2865 switch (*source) {
2866 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2867 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
2868 break;
2869 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2870 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
2871 break;
2872 case INTEL_PIPE_CRC_SOURCE_PF:
2873 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
2874 break;
2875 case INTEL_PIPE_CRC_SOURCE_NONE:
2876 *val = 0;
2877 break;
2878 default:
2879 return -EINVAL;
2880 }
2881
2882 return 0;
2883 }
2884
2885 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
2886 enum intel_pipe_crc_source source)
2887 {
2888 struct drm_i915_private *dev_priv = dev->dev_private;
2889 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
2890 u32 val = 0; /* shut up gcc */
2891 int ret;
2892
2893 if (pipe_crc->source == source)
2894 return 0;
2895
2896 /* forbid changing the source without going back to 'none' */
2897 if (pipe_crc->source && source)
2898 return -EINVAL;
2899
2900 if (IS_GEN2(dev))
2901 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
2902 else if (INTEL_INFO(dev)->gen < 5)
2903 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
2904 else if (IS_VALLEYVIEW(dev))
2905 ret = vlv_pipe_crc_ctl_reg(dev,pipe, &source, &val);
2906 else if (IS_GEN5(dev) || IS_GEN6(dev))
2907 ret = ilk_pipe_crc_ctl_reg(&source, &val);
2908 else
2909 ret = ivb_pipe_crc_ctl_reg(&source, &val);
2910
2911 if (ret != 0)
2912 return ret;
2913
2914 /* none -> real source transition */
2915 if (source) {
2916 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
2917 pipe_name(pipe), pipe_crc_source_name(source));
2918
2919 pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) *
2920 INTEL_PIPE_CRC_ENTRIES_NR,
2921 GFP_KERNEL);
2922 if (!pipe_crc->entries)
2923 return -ENOMEM;
2924
2925 spin_lock_irq(&pipe_crc->lock);
2926 pipe_crc->head = 0;
2927 pipe_crc->tail = 0;
2928 spin_unlock_irq(&pipe_crc->lock);
2929 }
2930
2931 pipe_crc->source = source;
2932
2933 I915_WRITE(PIPE_CRC_CTL(pipe), val);
2934 POSTING_READ(PIPE_CRC_CTL(pipe));
2935
2936 /* real source -> none transition */
2937 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
2938 struct intel_pipe_crc_entry *entries;
2939 struct intel_crtc *crtc =
2940 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2941
2942 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
2943 pipe_name(pipe));
2944
2945 drm_modeset_lock(&crtc->base.mutex, NULL);
2946 if (crtc->active)
2947 intel_wait_for_vblank(dev, pipe);
2948 drm_modeset_unlock(&crtc->base.mutex);
2949
2950 spin_lock_irq(&pipe_crc->lock);
2951 entries = pipe_crc->entries;
2952 pipe_crc->entries = NULL;
2953 spin_unlock_irq(&pipe_crc->lock);
2954
2955 kfree(entries);
2956
2957 if (IS_G4X(dev))
2958 g4x_undo_pipe_scramble_reset(dev, pipe);
2959 else if (IS_VALLEYVIEW(dev))
2960 vlv_undo_pipe_scramble_reset(dev, pipe);
2961 }
2962
2963 return 0;
2964 }
2965
2966 /*
2967 * Parse pipe CRC command strings:
2968 * command: wsp* object wsp+ name wsp+ source wsp*
2969 * object: 'pipe'
2970 * name: (A | B | C)
2971 * source: (none | plane1 | plane2 | pf)
2972 * wsp: (#0x20 | #0x9 | #0xA)+
2973 *
2974 * eg.:
2975 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
2976 * "pipe A none" -> Stop CRC
2977 */
2978 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
2979 {
2980 int n_words = 0;
2981
2982 while (*buf) {
2983 char *end;
2984
2985 /* skip leading white space */
2986 buf = skip_spaces(buf);
2987 if (!*buf)
2988 break; /* end of buffer */
2989
2990 /* find end of word */
2991 for (end = buf; *end && !isspace(*end); end++)
2992 ;
2993
2994 if (n_words == max_words) {
2995 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
2996 max_words);
2997 return -EINVAL; /* ran out of words[] before bytes */
2998 }
2999
3000 if (*end)
3001 *end++ = '\0';
3002 words[n_words++] = buf;
3003 buf = end;
3004 }
3005
3006 return n_words;
3007 }
3008
3009 enum intel_pipe_crc_object {
3010 PIPE_CRC_OBJECT_PIPE,
3011 };
3012
3013 static const char * const pipe_crc_objects[] = {
3014 "pipe",
3015 };
3016
3017 static int
3018 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
3019 {
3020 int i;
3021
3022 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3023 if (!strcmp(buf, pipe_crc_objects[i])) {
3024 *o = i;
3025 return 0;
3026 }
3027
3028 return -EINVAL;
3029 }
3030
3031 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
3032 {
3033 const char name = buf[0];
3034
3035 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3036 return -EINVAL;
3037
3038 *pipe = name - 'A';
3039
3040 return 0;
3041 }
3042
3043 static int
3044 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
3045 {
3046 int i;
3047
3048 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3049 if (!strcmp(buf, pipe_crc_sources[i])) {
3050 *s = i;
3051 return 0;
3052 }
3053
3054 return -EINVAL;
3055 }
3056
3057 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
3058 {
3059 #define N_WORDS 3
3060 int n_words;
3061 char *words[N_WORDS];
3062 enum pipe pipe;
3063 enum intel_pipe_crc_object object;
3064 enum intel_pipe_crc_source source;
3065
3066 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
3067 if (n_words != N_WORDS) {
3068 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3069 N_WORDS);
3070 return -EINVAL;
3071 }
3072
3073 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
3074 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
3075 return -EINVAL;
3076 }
3077
3078 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
3079 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
3080 return -EINVAL;
3081 }
3082
3083 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
3084 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
3085 return -EINVAL;
3086 }
3087
3088 return pipe_crc_set_source(dev, pipe, source);
3089 }
3090
3091 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3092 size_t len, loff_t *offp)
3093 {
3094 struct seq_file *m = file->private_data;
3095 struct drm_device *dev = m->private;
3096 char *tmpbuf;
3097 int ret;
3098
3099 if (len == 0)
3100 return 0;
3101
3102 if (len > PAGE_SIZE - 1) {
3103 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3104 PAGE_SIZE);
3105 return -E2BIG;
3106 }
3107
3108 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3109 if (!tmpbuf)
3110 return -ENOMEM;
3111
3112 if (copy_from_user(tmpbuf, ubuf, len)) {
3113 ret = -EFAULT;
3114 goto out;
3115 }
3116 tmpbuf[len] = '\0';
3117
3118 ret = display_crc_ctl_parse(dev, tmpbuf, len);
3119
3120 out:
3121 kfree(tmpbuf);
3122 if (ret < 0)
3123 return ret;
3124
3125 *offp += len;
3126 return len;
3127 }
3128
3129 static const struct file_operations i915_display_crc_ctl_fops = {
3130 .owner = THIS_MODULE,
3131 .open = display_crc_ctl_open,
3132 .read = seq_read,
3133 .llseek = seq_lseek,
3134 .release = single_release,
3135 .write = display_crc_ctl_write
3136 };
3137
3138 static void wm_latency_show(struct seq_file *m, const uint16_t wm[5])
3139 {
3140 struct drm_device *dev = m->private;
3141 int num_levels = ilk_wm_max_level(dev) + 1;
3142 int level;
3143
3144 drm_modeset_lock_all(dev);
3145
3146 for (level = 0; level < num_levels; level++) {
3147 unsigned int latency = wm[level];
3148
3149 /* WM1+ latency values in 0.5us units */
3150 if (level > 0)
3151 latency *= 5;
3152
3153 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3154 level, wm[level],
3155 latency / 10, latency % 10);
3156 }
3157
3158 drm_modeset_unlock_all(dev);
3159 }
3160
3161 static int pri_wm_latency_show(struct seq_file *m, void *data)
3162 {
3163 struct drm_device *dev = m->private;
3164
3165 wm_latency_show(m, to_i915(dev)->wm.pri_latency);
3166
3167 return 0;
3168 }
3169
3170 static int spr_wm_latency_show(struct seq_file *m, void *data)
3171 {
3172 struct drm_device *dev = m->private;
3173
3174 wm_latency_show(m, to_i915(dev)->wm.spr_latency);
3175
3176 return 0;
3177 }
3178
3179 static int cur_wm_latency_show(struct seq_file *m, void *data)
3180 {
3181 struct drm_device *dev = m->private;
3182
3183 wm_latency_show(m, to_i915(dev)->wm.cur_latency);
3184
3185 return 0;
3186 }
3187
3188 static int pri_wm_latency_open(struct inode *inode, struct file *file)
3189 {
3190 struct drm_device *dev = inode->i_private;
3191
3192 if (!HAS_PCH_SPLIT(dev))
3193 return -ENODEV;
3194
3195 return single_open(file, pri_wm_latency_show, dev);
3196 }
3197
3198 static int spr_wm_latency_open(struct inode *inode, struct file *file)
3199 {
3200 struct drm_device *dev = inode->i_private;
3201
3202 if (!HAS_PCH_SPLIT(dev))
3203 return -ENODEV;
3204
3205 return single_open(file, spr_wm_latency_show, dev);
3206 }
3207
3208 static int cur_wm_latency_open(struct inode *inode, struct file *file)
3209 {
3210 struct drm_device *dev = inode->i_private;
3211
3212 if (!HAS_PCH_SPLIT(dev))
3213 return -ENODEV;
3214
3215 return single_open(file, cur_wm_latency_show, dev);
3216 }
3217
3218 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3219 size_t len, loff_t *offp, uint16_t wm[5])
3220 {
3221 struct seq_file *m = file->private_data;
3222 struct drm_device *dev = m->private;
3223 uint16_t new[5] = { 0 };
3224 int num_levels = ilk_wm_max_level(dev) + 1;
3225 int level;
3226 int ret;
3227 char tmp[32];
3228
3229 if (len >= sizeof(tmp))
3230 return -EINVAL;
3231
3232 if (copy_from_user(tmp, ubuf, len))
3233 return -EFAULT;
3234
3235 tmp[len] = '\0';
3236
3237 ret = sscanf(tmp, "%hu %hu %hu %hu %hu", &new[0], &new[1], &new[2], &new[3], &new[4]);
3238 if (ret != num_levels)
3239 return -EINVAL;
3240
3241 drm_modeset_lock_all(dev);
3242
3243 for (level = 0; level < num_levels; level++)
3244 wm[level] = new[level];
3245
3246 drm_modeset_unlock_all(dev);
3247
3248 return len;
3249 }
3250
3251
3252 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3253 size_t len, loff_t *offp)
3254 {
3255 struct seq_file *m = file->private_data;
3256 struct drm_device *dev = m->private;
3257
3258 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.pri_latency);
3259 }
3260
3261 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3262 size_t len, loff_t *offp)
3263 {
3264 struct seq_file *m = file->private_data;
3265 struct drm_device *dev = m->private;
3266
3267 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.spr_latency);
3268 }
3269
3270 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3271 size_t len, loff_t *offp)
3272 {
3273 struct seq_file *m = file->private_data;
3274 struct drm_device *dev = m->private;
3275
3276 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.cur_latency);
3277 }
3278
3279 static const struct file_operations i915_pri_wm_latency_fops = {
3280 .owner = THIS_MODULE,
3281 .open = pri_wm_latency_open,
3282 .read = seq_read,
3283 .llseek = seq_lseek,
3284 .release = single_release,
3285 .write = pri_wm_latency_write
3286 };
3287
3288 static const struct file_operations i915_spr_wm_latency_fops = {
3289 .owner = THIS_MODULE,
3290 .open = spr_wm_latency_open,
3291 .read = seq_read,
3292 .llseek = seq_lseek,
3293 .release = single_release,
3294 .write = spr_wm_latency_write
3295 };
3296
3297 static const struct file_operations i915_cur_wm_latency_fops = {
3298 .owner = THIS_MODULE,
3299 .open = cur_wm_latency_open,
3300 .read = seq_read,
3301 .llseek = seq_lseek,
3302 .release = single_release,
3303 .write = cur_wm_latency_write
3304 };
3305
3306 static int
3307 i915_wedged_get(void *data, u64 *val)
3308 {
3309 struct drm_device *dev = data;
3310 struct drm_i915_private *dev_priv = dev->dev_private;
3311
3312 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
3313
3314 return 0;
3315 }
3316
3317 static int
3318 i915_wedged_set(void *data, u64 val)
3319 {
3320 struct drm_device *dev = data;
3321 struct drm_i915_private *dev_priv = dev->dev_private;
3322
3323 intel_runtime_pm_get(dev_priv);
3324
3325 i915_handle_error(dev, val,
3326 "Manually setting wedged to %llu", val);
3327
3328 intel_runtime_pm_put(dev_priv);
3329
3330 return 0;
3331 }
3332
3333 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
3334 i915_wedged_get, i915_wedged_set,
3335 "%llu\n");
3336
3337 static int
3338 i915_ring_stop_get(void *data, u64 *val)
3339 {
3340 struct drm_device *dev = data;
3341 struct drm_i915_private *dev_priv = dev->dev_private;
3342
3343 *val = dev_priv->gpu_error.stop_rings;
3344
3345 return 0;
3346 }
3347
3348 static int
3349 i915_ring_stop_set(void *data, u64 val)
3350 {
3351 struct drm_device *dev = data;
3352 struct drm_i915_private *dev_priv = dev->dev_private;
3353 int ret;
3354
3355 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
3356
3357 ret = mutex_lock_interruptible(&dev->struct_mutex);
3358 if (ret)
3359 return ret;
3360
3361 dev_priv->gpu_error.stop_rings = val;
3362 mutex_unlock(&dev->struct_mutex);
3363
3364 return 0;
3365 }
3366
3367 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
3368 i915_ring_stop_get, i915_ring_stop_set,
3369 "0x%08llx\n");
3370
3371 static int
3372 i915_ring_missed_irq_get(void *data, u64 *val)
3373 {
3374 struct drm_device *dev = data;
3375 struct drm_i915_private *dev_priv = dev->dev_private;
3376
3377 *val = dev_priv->gpu_error.missed_irq_rings;
3378 return 0;
3379 }
3380
3381 static int
3382 i915_ring_missed_irq_set(void *data, u64 val)
3383 {
3384 struct drm_device *dev = data;
3385 struct drm_i915_private *dev_priv = dev->dev_private;
3386 int ret;
3387
3388 /* Lock against concurrent debugfs callers */
3389 ret = mutex_lock_interruptible(&dev->struct_mutex);
3390 if (ret)
3391 return ret;
3392 dev_priv->gpu_error.missed_irq_rings = val;
3393 mutex_unlock(&dev->struct_mutex);
3394
3395 return 0;
3396 }
3397
3398 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
3399 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
3400 "0x%08llx\n");
3401
3402 static int
3403 i915_ring_test_irq_get(void *data, u64 *val)
3404 {
3405 struct drm_device *dev = data;
3406 struct drm_i915_private *dev_priv = dev->dev_private;
3407
3408 *val = dev_priv->gpu_error.test_irq_rings;
3409
3410 return 0;
3411 }
3412
3413 static int
3414 i915_ring_test_irq_set(void *data, u64 val)
3415 {
3416 struct drm_device *dev = data;
3417 struct drm_i915_private *dev_priv = dev->dev_private;
3418 int ret;
3419
3420 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
3421
3422 /* Lock against concurrent debugfs callers */
3423 ret = mutex_lock_interruptible(&dev->struct_mutex);
3424 if (ret)
3425 return ret;
3426
3427 dev_priv->gpu_error.test_irq_rings = val;
3428 mutex_unlock(&dev->struct_mutex);
3429
3430 return 0;
3431 }
3432
3433 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
3434 i915_ring_test_irq_get, i915_ring_test_irq_set,
3435 "0x%08llx\n");
3436
3437 #define DROP_UNBOUND 0x1
3438 #define DROP_BOUND 0x2
3439 #define DROP_RETIRE 0x4
3440 #define DROP_ACTIVE 0x8
3441 #define DROP_ALL (DROP_UNBOUND | \
3442 DROP_BOUND | \
3443 DROP_RETIRE | \
3444 DROP_ACTIVE)
3445 static int
3446 i915_drop_caches_get(void *data, u64 *val)
3447 {
3448 *val = DROP_ALL;
3449
3450 return 0;
3451 }
3452
3453 static int
3454 i915_drop_caches_set(void *data, u64 val)
3455 {
3456 struct drm_device *dev = data;
3457 struct drm_i915_private *dev_priv = dev->dev_private;
3458 struct drm_i915_gem_object *obj, *next;
3459 struct i915_address_space *vm;
3460 struct i915_vma *vma, *x;
3461 int ret;
3462
3463 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
3464
3465 /* No need to check and wait for gpu resets, only libdrm auto-restarts
3466 * on ioctls on -EAGAIN. */
3467 ret = mutex_lock_interruptible(&dev->struct_mutex);
3468 if (ret)
3469 return ret;
3470
3471 if (val & DROP_ACTIVE) {
3472 ret = i915_gpu_idle(dev);
3473 if (ret)
3474 goto unlock;
3475 }
3476
3477 if (val & (DROP_RETIRE | DROP_ACTIVE))
3478 i915_gem_retire_requests(dev);
3479
3480 if (val & DROP_BOUND) {
3481 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
3482 list_for_each_entry_safe(vma, x, &vm->inactive_list,
3483 mm_list) {
3484 if (vma->pin_count)
3485 continue;
3486
3487 ret = i915_vma_unbind(vma);
3488 if (ret)
3489 goto unlock;
3490 }
3491 }
3492 }
3493
3494 if (val & DROP_UNBOUND) {
3495 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
3496 global_list)
3497 if (obj->pages_pin_count == 0) {
3498 ret = i915_gem_object_put_pages(obj);
3499 if (ret)
3500 goto unlock;
3501 }
3502 }
3503
3504 unlock:
3505 mutex_unlock(&dev->struct_mutex);
3506
3507 return ret;
3508 }
3509
3510 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
3511 i915_drop_caches_get, i915_drop_caches_set,
3512 "0x%08llx\n");
3513
3514 static int
3515 i915_max_freq_get(void *data, u64 *val)
3516 {
3517 struct drm_device *dev = data;
3518 struct drm_i915_private *dev_priv = dev->dev_private;
3519 int ret;
3520
3521 if (INTEL_INFO(dev)->gen < 6)
3522 return -ENODEV;
3523
3524 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3525
3526 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3527 if (ret)
3528 return ret;
3529
3530 if (IS_VALLEYVIEW(dev))
3531 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
3532 else
3533 *val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
3534 mutex_unlock(&dev_priv->rps.hw_lock);
3535
3536 return 0;
3537 }
3538
3539 static int
3540 i915_max_freq_set(void *data, u64 val)
3541 {
3542 struct drm_device *dev = data;
3543 struct drm_i915_private *dev_priv = dev->dev_private;
3544 u32 rp_state_cap, hw_max, hw_min;
3545 int ret;
3546
3547 if (INTEL_INFO(dev)->gen < 6)
3548 return -ENODEV;
3549
3550 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3551
3552 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
3553
3554 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3555 if (ret)
3556 return ret;
3557
3558 /*
3559 * Turbo will still be enabled, but won't go above the set value.
3560 */
3561 if (IS_VALLEYVIEW(dev)) {
3562 val = vlv_freq_opcode(dev_priv, val);
3563
3564 hw_max = valleyview_rps_max_freq(dev_priv);
3565 hw_min = valleyview_rps_min_freq(dev_priv);
3566 } else {
3567 do_div(val, GT_FREQUENCY_MULTIPLIER);
3568
3569 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3570 hw_max = dev_priv->rps.max_freq;
3571 hw_min = (rp_state_cap >> 16) & 0xff;
3572 }
3573
3574 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
3575 mutex_unlock(&dev_priv->rps.hw_lock);
3576 return -EINVAL;
3577 }
3578
3579 dev_priv->rps.max_freq_softlimit = val;
3580
3581 if (IS_VALLEYVIEW(dev))
3582 valleyview_set_rps(dev, val);
3583 else
3584 gen6_set_rps(dev, val);
3585
3586 mutex_unlock(&dev_priv->rps.hw_lock);
3587
3588 return 0;
3589 }
3590
3591 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
3592 i915_max_freq_get, i915_max_freq_set,
3593 "%llu\n");
3594
3595 static int
3596 i915_min_freq_get(void *data, u64 *val)
3597 {
3598 struct drm_device *dev = data;
3599 struct drm_i915_private *dev_priv = dev->dev_private;
3600 int ret;
3601
3602 if (INTEL_INFO(dev)->gen < 6)
3603 return -ENODEV;
3604
3605 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3606
3607 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3608 if (ret)
3609 return ret;
3610
3611 if (IS_VALLEYVIEW(dev))
3612 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
3613 else
3614 *val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
3615 mutex_unlock(&dev_priv->rps.hw_lock);
3616
3617 return 0;
3618 }
3619
3620 static int
3621 i915_min_freq_set(void *data, u64 val)
3622 {
3623 struct drm_device *dev = data;
3624 struct drm_i915_private *dev_priv = dev->dev_private;
3625 u32 rp_state_cap, hw_max, hw_min;
3626 int ret;
3627
3628 if (INTEL_INFO(dev)->gen < 6)
3629 return -ENODEV;
3630
3631 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3632
3633 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
3634
3635 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3636 if (ret)
3637 return ret;
3638
3639 /*
3640 * Turbo will still be enabled, but won't go below the set value.
3641 */
3642 if (IS_VALLEYVIEW(dev)) {
3643 val = vlv_freq_opcode(dev_priv, val);
3644
3645 hw_max = valleyview_rps_max_freq(dev_priv);
3646 hw_min = valleyview_rps_min_freq(dev_priv);
3647 } else {
3648 do_div(val, GT_FREQUENCY_MULTIPLIER);
3649
3650 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3651 hw_max = dev_priv->rps.max_freq;
3652 hw_min = (rp_state_cap >> 16) & 0xff;
3653 }
3654
3655 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
3656 mutex_unlock(&dev_priv->rps.hw_lock);
3657 return -EINVAL;
3658 }
3659
3660 dev_priv->rps.min_freq_softlimit = val;
3661
3662 if (IS_VALLEYVIEW(dev))
3663 valleyview_set_rps(dev, val);
3664 else
3665 gen6_set_rps(dev, val);
3666
3667 mutex_unlock(&dev_priv->rps.hw_lock);
3668
3669 return 0;
3670 }
3671
3672 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
3673 i915_min_freq_get, i915_min_freq_set,
3674 "%llu\n");
3675
3676 static int
3677 i915_cache_sharing_get(void *data, u64 *val)
3678 {
3679 struct drm_device *dev = data;
3680 struct drm_i915_private *dev_priv = dev->dev_private;
3681 u32 snpcr;
3682 int ret;
3683
3684 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3685 return -ENODEV;
3686
3687 ret = mutex_lock_interruptible(&dev->struct_mutex);
3688 if (ret)
3689 return ret;
3690 intel_runtime_pm_get(dev_priv);
3691
3692 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3693
3694 intel_runtime_pm_put(dev_priv);
3695 mutex_unlock(&dev_priv->dev->struct_mutex);
3696
3697 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
3698
3699 return 0;
3700 }
3701
3702 static int
3703 i915_cache_sharing_set(void *data, u64 val)
3704 {
3705 struct drm_device *dev = data;
3706 struct drm_i915_private *dev_priv = dev->dev_private;
3707 u32 snpcr;
3708
3709 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3710 return -ENODEV;
3711
3712 if (val > 3)
3713 return -EINVAL;
3714
3715 intel_runtime_pm_get(dev_priv);
3716 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
3717
3718 /* Update the cache sharing policy here as well */
3719 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3720 snpcr &= ~GEN6_MBC_SNPCR_MASK;
3721 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
3722 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3723
3724 intel_runtime_pm_put(dev_priv);
3725 return 0;
3726 }
3727
3728 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
3729 i915_cache_sharing_get, i915_cache_sharing_set,
3730 "%llu\n");
3731
3732 static int i915_forcewake_open(struct inode *inode, struct file *file)
3733 {
3734 struct drm_device *dev = inode->i_private;
3735 struct drm_i915_private *dev_priv = dev->dev_private;
3736
3737 if (INTEL_INFO(dev)->gen < 6)
3738 return 0;
3739
3740 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3741
3742 return 0;
3743 }
3744
3745 static int i915_forcewake_release(struct inode *inode, struct file *file)
3746 {
3747 struct drm_device *dev = inode->i_private;
3748 struct drm_i915_private *dev_priv = dev->dev_private;
3749
3750 if (INTEL_INFO(dev)->gen < 6)
3751 return 0;
3752
3753 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3754
3755 return 0;
3756 }
3757
3758 static const struct file_operations i915_forcewake_fops = {
3759 .owner = THIS_MODULE,
3760 .open = i915_forcewake_open,
3761 .release = i915_forcewake_release,
3762 };
3763
3764 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
3765 {
3766 struct drm_device *dev = minor->dev;
3767 struct dentry *ent;
3768
3769 ent = debugfs_create_file("i915_forcewake_user",
3770 S_IRUSR,
3771 root, dev,
3772 &i915_forcewake_fops);
3773 if (!ent)
3774 return -ENOMEM;
3775
3776 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
3777 }
3778
3779 static int i915_debugfs_create(struct dentry *root,
3780 struct drm_minor *minor,
3781 const char *name,
3782 const struct file_operations *fops)
3783 {
3784 struct drm_device *dev = minor->dev;
3785 struct dentry *ent;
3786
3787 ent = debugfs_create_file(name,
3788 S_IRUGO | S_IWUSR,
3789 root, dev,
3790 fops);
3791 if (!ent)
3792 return -ENOMEM;
3793
3794 return drm_add_fake_info_node(minor, ent, fops);
3795 }
3796
3797 static const struct drm_info_list i915_debugfs_list[] = {
3798 {"i915_capabilities", i915_capabilities, 0},
3799 {"i915_gem_objects", i915_gem_object_info, 0},
3800 {"i915_gem_gtt", i915_gem_gtt_info, 0},
3801 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
3802 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
3803 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
3804 {"i915_gem_stolen", i915_gem_stolen_list_info },
3805 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
3806 {"i915_gem_request", i915_gem_request_info, 0},
3807 {"i915_gem_seqno", i915_gem_seqno_info, 0},
3808 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
3809 {"i915_gem_interrupt", i915_interrupt_info, 0},
3810 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
3811 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
3812 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
3813 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
3814 {"i915_rstdby_delays", i915_rstdby_delays, 0},
3815 {"i915_frequency_info", i915_frequency_info, 0},
3816 {"i915_delayfreq_table", i915_delayfreq_table, 0},
3817 {"i915_inttoext_table", i915_inttoext_table, 0},
3818 {"i915_drpc_info", i915_drpc_info, 0},
3819 {"i915_emon_status", i915_emon_status, 0},
3820 {"i915_ring_freq_table", i915_ring_freq_table, 0},
3821 {"i915_gfxec", i915_gfxec, 0},
3822 {"i915_fbc_status", i915_fbc_status, 0},
3823 {"i915_ips_status", i915_ips_status, 0},
3824 {"i915_sr_status", i915_sr_status, 0},
3825 {"i915_opregion", i915_opregion, 0},
3826 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
3827 {"i915_context_status", i915_context_status, 0},
3828 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
3829 {"i915_swizzle_info", i915_swizzle_info, 0},
3830 {"i915_ppgtt_info", i915_ppgtt_info, 0},
3831 {"i915_llc", i915_llc, 0},
3832 {"i915_edp_psr_status", i915_edp_psr_status, 0},
3833 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
3834 {"i915_energy_uJ", i915_energy_uJ, 0},
3835 {"i915_pc8_status", i915_pc8_status, 0},
3836 {"i915_power_domain_info", i915_power_domain_info, 0},
3837 {"i915_display_info", i915_display_info, 0},
3838 };
3839 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
3840
3841 static const struct i915_debugfs_files {
3842 const char *name;
3843 const struct file_operations *fops;
3844 } i915_debugfs_files[] = {
3845 {"i915_wedged", &i915_wedged_fops},
3846 {"i915_max_freq", &i915_max_freq_fops},
3847 {"i915_min_freq", &i915_min_freq_fops},
3848 {"i915_cache_sharing", &i915_cache_sharing_fops},
3849 {"i915_ring_stop", &i915_ring_stop_fops},
3850 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
3851 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
3852 {"i915_gem_drop_caches", &i915_drop_caches_fops},
3853 {"i915_error_state", &i915_error_state_fops},
3854 {"i915_next_seqno", &i915_next_seqno_fops},
3855 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
3856 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
3857 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
3858 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
3859 };
3860
3861 void intel_display_crc_init(struct drm_device *dev)
3862 {
3863 struct drm_i915_private *dev_priv = dev->dev_private;
3864 enum pipe pipe;
3865
3866 for_each_pipe(pipe) {
3867 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3868
3869 pipe_crc->opened = false;
3870 spin_lock_init(&pipe_crc->lock);
3871 init_waitqueue_head(&pipe_crc->wq);
3872 }
3873 }
3874
3875 int i915_debugfs_init(struct drm_minor *minor)
3876 {
3877 int ret, i;
3878
3879 ret = i915_forcewake_create(minor->debugfs_root, minor);
3880 if (ret)
3881 return ret;
3882
3883 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
3884 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
3885 if (ret)
3886 return ret;
3887 }
3888
3889 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3890 ret = i915_debugfs_create(minor->debugfs_root, minor,
3891 i915_debugfs_files[i].name,
3892 i915_debugfs_files[i].fops);
3893 if (ret)
3894 return ret;
3895 }
3896
3897 return drm_debugfs_create_files(i915_debugfs_list,
3898 I915_DEBUGFS_ENTRIES,
3899 minor->debugfs_root, minor);
3900 }
3901
3902 void i915_debugfs_cleanup(struct drm_minor *minor)
3903 {
3904 int i;
3905
3906 drm_debugfs_remove_files(i915_debugfs_list,
3907 I915_DEBUGFS_ENTRIES, minor);
3908
3909 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
3910 1, minor);
3911
3912 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
3913 struct drm_info_list *info_list =
3914 (struct drm_info_list *)&i915_pipe_crc_data[i];
3915
3916 drm_debugfs_remove_files(info_list, 1, minor);
3917 }
3918
3919 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3920 struct drm_info_list *info_list =
3921 (struct drm_info_list *) i915_debugfs_files[i].fops;
3922
3923 drm_debugfs_remove_files(info_list, 1, minor);
3924 }
3925 }
Linux kernel - Deliverables
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