2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
49 /* As the drm_debugfs_init() routines are called before dev->dev_private is
50 * allocated we need to hook into the minor for release. */
52 drm_add_fake_info_node(struct drm_minor
*minor
,
56 struct drm_info_node
*node
;
58 node
= kmalloc(sizeof(*node
), GFP_KERNEL
);
66 node
->info_ent
= (void *) key
;
68 mutex_lock(&minor
->debugfs_lock
);
69 list_add(&node
->list
, &minor
->debugfs_list
);
70 mutex_unlock(&minor
->debugfs_lock
);
75 static int i915_capabilities(struct seq_file
*m
, void *data
)
77 struct drm_info_node
*node
= m
->private;
78 struct drm_device
*dev
= node
->minor
->dev
;
79 const struct intel_device_info
*info
= INTEL_INFO(dev
);
81 seq_printf(m
, "gen: %d\n", info
->gen
);
82 seq_printf(m
, "pch: %d\n", INTEL_PCH_TYPE(dev
));
83 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
84 #define SEP_SEMICOLON ;
85 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG
, SEP_SEMICOLON
);
92 static const char get_active_flag(struct drm_i915_gem_object
*obj
)
94 return obj
->active
? '*' : ' ';
97 static const char get_pin_flag(struct drm_i915_gem_object
*obj
)
99 return obj
->pin_display
? 'p' : ' ';
102 static const char get_tiling_flag(struct drm_i915_gem_object
*obj
)
104 switch (obj
->tiling_mode
) {
106 case I915_TILING_NONE
: return ' ';
107 case I915_TILING_X
: return 'X';
108 case I915_TILING_Y
: return 'Y';
112 static inline const char get_global_flag(struct drm_i915_gem_object
*obj
)
114 return i915_gem_obj_to_ggtt(obj
) ? 'g' : ' ';
117 static inline const char get_pin_mapped_flag(struct drm_i915_gem_object
*obj
)
119 return obj
->mapping
? 'M' : ' ';
122 static u64
i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object
*obj
)
125 struct i915_vma
*vma
;
127 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
128 if (vma
->is_ggtt
&& drm_mm_node_allocated(&vma
->node
))
129 size
+= vma
->node
.size
;
136 describe_obj(struct seq_file
*m
, struct drm_i915_gem_object
*obj
)
138 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
139 struct intel_engine_cs
*engine
;
140 struct i915_vma
*vma
;
142 enum intel_engine_id id
;
144 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
146 seq_printf(m
, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ",
148 get_active_flag(obj
),
150 get_tiling_flag(obj
),
151 get_global_flag(obj
),
152 get_pin_mapped_flag(obj
),
153 obj
->base
.size
/ 1024,
154 obj
->base
.read_domains
,
155 obj
->base
.write_domain
);
156 for_each_engine_id(engine
, dev_priv
, id
)
158 i915_gem_request_get_seqno(obj
->last_read_req
[id
]));
159 seq_printf(m
, "] %x %x%s%s%s",
160 i915_gem_request_get_seqno(obj
->last_write_req
),
161 i915_gem_request_get_seqno(obj
->last_fenced_req
),
162 i915_cache_level_str(to_i915(obj
->base
.dev
), obj
->cache_level
),
163 obj
->dirty
? " dirty" : "",
164 obj
->madv
== I915_MADV_DONTNEED
? " purgeable" : "");
166 seq_printf(m
, " (name: %d)", obj
->base
.name
);
167 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
168 if (vma
->pin_count
> 0)
171 seq_printf(m
, " (pinned x %d)", pin_count
);
172 if (obj
->pin_display
)
173 seq_printf(m
, " (display)");
174 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
)
175 seq_printf(m
, " (fence: %d)", obj
->fence_reg
);
176 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
177 seq_printf(m
, " (%sgtt offset: %08llx, size: %08llx",
178 vma
->is_ggtt
? "g" : "pp",
179 vma
->node
.start
, vma
->node
.size
);
181 seq_printf(m
, ", type: %u", vma
->ggtt_view
.type
);
185 seq_printf(m
, " (stolen: %08llx)", obj
->stolen
->start
);
186 if (obj
->pin_display
|| obj
->fault_mappable
) {
188 if (obj
->pin_display
)
190 if (obj
->fault_mappable
)
193 seq_printf(m
, " (%s mappable)", s
);
195 if (obj
->last_write_req
!= NULL
)
196 seq_printf(m
, " (%s)",
197 i915_gem_request_get_engine(obj
->last_write_req
)->name
);
198 if (obj
->frontbuffer_bits
)
199 seq_printf(m
, " (frontbuffer: 0x%03x)", obj
->frontbuffer_bits
);
202 static void describe_ctx(struct seq_file
*m
, struct intel_context
*ctx
)
204 seq_putc(m
, ctx
->legacy_hw_ctx
.initialized
? 'I' : 'i');
205 seq_putc(m
, ctx
->remap_slice
? 'R' : 'r');
209 static int i915_gem_object_list_info(struct seq_file
*m
, void *data
)
211 struct drm_info_node
*node
= m
->private;
212 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
213 struct list_head
*head
;
214 struct drm_device
*dev
= node
->minor
->dev
;
215 struct drm_i915_private
*dev_priv
= to_i915(dev
);
216 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
217 struct i915_vma
*vma
;
218 u64 total_obj_size
, total_gtt_size
;
221 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
225 /* FIXME: the user of this interface might want more than just GGTT */
228 seq_puts(m
, "Active:\n");
229 head
= &ggtt
->base
.active_list
;
232 seq_puts(m
, "Inactive:\n");
233 head
= &ggtt
->base
.inactive_list
;
236 mutex_unlock(&dev
->struct_mutex
);
240 total_obj_size
= total_gtt_size
= count
= 0;
241 list_for_each_entry(vma
, head
, vm_link
) {
243 describe_obj(m
, vma
->obj
);
245 total_obj_size
+= vma
->obj
->base
.size
;
246 total_gtt_size
+= vma
->node
.size
;
249 mutex_unlock(&dev
->struct_mutex
);
251 seq_printf(m
, "Total %d objects, %llu bytes, %llu GTT size\n",
252 count
, total_obj_size
, total_gtt_size
);
256 static int obj_rank_by_stolen(void *priv
,
257 struct list_head
*A
, struct list_head
*B
)
259 struct drm_i915_gem_object
*a
=
260 container_of(A
, struct drm_i915_gem_object
, obj_exec_link
);
261 struct drm_i915_gem_object
*b
=
262 container_of(B
, struct drm_i915_gem_object
, obj_exec_link
);
264 if (a
->stolen
->start
< b
->stolen
->start
)
266 if (a
->stolen
->start
> b
->stolen
->start
)
271 static int i915_gem_stolen_list_info(struct seq_file
*m
, void *data
)
273 struct drm_info_node
*node
= m
->private;
274 struct drm_device
*dev
= node
->minor
->dev
;
275 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
276 struct drm_i915_gem_object
*obj
;
277 u64 total_obj_size
, total_gtt_size
;
281 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
285 total_obj_size
= total_gtt_size
= count
= 0;
286 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
287 if (obj
->stolen
== NULL
)
290 list_add(&obj
->obj_exec_link
, &stolen
);
292 total_obj_size
+= obj
->base
.size
;
293 total_gtt_size
+= i915_gem_obj_total_ggtt_size(obj
);
296 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
297 if (obj
->stolen
== NULL
)
300 list_add(&obj
->obj_exec_link
, &stolen
);
302 total_obj_size
+= obj
->base
.size
;
305 list_sort(NULL
, &stolen
, obj_rank_by_stolen
);
306 seq_puts(m
, "Stolen:\n");
307 while (!list_empty(&stolen
)) {
308 obj
= list_first_entry(&stolen
, typeof(*obj
), obj_exec_link
);
310 describe_obj(m
, obj
);
312 list_del_init(&obj
->obj_exec_link
);
314 mutex_unlock(&dev
->struct_mutex
);
316 seq_printf(m
, "Total %d objects, %llu bytes, %llu GTT size\n",
317 count
, total_obj_size
, total_gtt_size
);
321 #define count_objects(list, member) do { \
322 list_for_each_entry(obj, list, member) { \
323 size += i915_gem_obj_total_ggtt_size(obj); \
325 if (obj->map_and_fenceable) { \
326 mappable_size += i915_gem_obj_ggtt_size(obj); \
333 struct drm_i915_file_private
*file_priv
;
337 u64 active
, inactive
;
340 static int per_file_stats(int id
, void *ptr
, void *data
)
342 struct drm_i915_gem_object
*obj
= ptr
;
343 struct file_stats
*stats
= data
;
344 struct i915_vma
*vma
;
347 stats
->total
+= obj
->base
.size
;
349 if (obj
->base
.name
|| obj
->base
.dma_buf
)
350 stats
->shared
+= obj
->base
.size
;
352 if (USES_FULL_PPGTT(obj
->base
.dev
)) {
353 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
354 struct i915_hw_ppgtt
*ppgtt
;
356 if (!drm_mm_node_allocated(&vma
->node
))
360 stats
->global
+= obj
->base
.size
;
364 ppgtt
= container_of(vma
->vm
, struct i915_hw_ppgtt
, base
);
365 if (ppgtt
->file_priv
!= stats
->file_priv
)
368 if (obj
->active
) /* XXX per-vma statistic */
369 stats
->active
+= obj
->base
.size
;
371 stats
->inactive
+= obj
->base
.size
;
376 if (i915_gem_obj_ggtt_bound(obj
)) {
377 stats
->global
+= obj
->base
.size
;
379 stats
->active
+= obj
->base
.size
;
381 stats
->inactive
+= obj
->base
.size
;
386 if (!list_empty(&obj
->global_list
))
387 stats
->unbound
+= obj
->base
.size
;
392 #define print_file_stats(m, name, stats) do { \
394 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
405 static void print_batch_pool_stats(struct seq_file
*m
,
406 struct drm_i915_private
*dev_priv
)
408 struct drm_i915_gem_object
*obj
;
409 struct file_stats stats
;
410 struct intel_engine_cs
*engine
;
413 memset(&stats
, 0, sizeof(stats
));
415 for_each_engine(engine
, dev_priv
) {
416 for (j
= 0; j
< ARRAY_SIZE(engine
->batch_pool
.cache_list
); j
++) {
417 list_for_each_entry(obj
,
418 &engine
->batch_pool
.cache_list
[j
],
420 per_file_stats(0, obj
, &stats
);
424 print_file_stats(m
, "[k]batch pool", stats
);
427 #define count_vmas(list, member) do { \
428 list_for_each_entry(vma, list, member) { \
429 size += i915_gem_obj_total_ggtt_size(vma->obj); \
431 if (vma->obj->map_and_fenceable) { \
432 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
438 static int i915_gem_object_info(struct seq_file
*m
, void* data
)
440 struct drm_info_node
*node
= m
->private;
441 struct drm_device
*dev
= node
->minor
->dev
;
442 struct drm_i915_private
*dev_priv
= to_i915(dev
);
443 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
444 u32 count
, mappable_count
, purgeable_count
;
445 u64 size
, mappable_size
, purgeable_size
;
446 struct drm_i915_gem_object
*obj
;
447 struct drm_file
*file
;
448 struct i915_vma
*vma
;
451 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
455 seq_printf(m
, "%u objects, %zu bytes\n",
456 dev_priv
->mm
.object_count
,
457 dev_priv
->mm
.object_memory
);
459 size
= count
= mappable_size
= mappable_count
= 0;
460 count_objects(&dev_priv
->mm
.bound_list
, global_list
);
461 seq_printf(m
, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
462 count
, mappable_count
, size
, mappable_size
);
464 size
= count
= mappable_size
= mappable_count
= 0;
465 count_vmas(&ggtt
->base
.active_list
, vm_link
);
466 seq_printf(m
, " %u [%u] active objects, %llu [%llu] bytes\n",
467 count
, mappable_count
, size
, mappable_size
);
469 size
= count
= mappable_size
= mappable_count
= 0;
470 count_vmas(&ggtt
->base
.inactive_list
, vm_link
);
471 seq_printf(m
, " %u [%u] inactive objects, %llu [%llu] bytes\n",
472 count
, mappable_count
, size
, mappable_size
);
474 size
= count
= purgeable_size
= purgeable_count
= 0;
475 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
476 size
+= obj
->base
.size
, ++count
;
477 if (obj
->madv
== I915_MADV_DONTNEED
)
478 purgeable_size
+= obj
->base
.size
, ++purgeable_count
;
480 seq_printf(m
, "%u unbound objects, %llu bytes\n", count
, size
);
482 size
= count
= mappable_size
= mappable_count
= 0;
483 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
484 if (obj
->fault_mappable
) {
485 size
+= i915_gem_obj_ggtt_size(obj
);
488 if (obj
->pin_display
) {
489 mappable_size
+= i915_gem_obj_ggtt_size(obj
);
492 if (obj
->madv
== I915_MADV_DONTNEED
) {
493 purgeable_size
+= obj
->base
.size
;
497 seq_printf(m
, "%u purgeable objects, %llu bytes\n",
498 purgeable_count
, purgeable_size
);
499 seq_printf(m
, "%u pinned mappable objects, %llu bytes\n",
500 mappable_count
, mappable_size
);
501 seq_printf(m
, "%u fault mappable objects, %llu bytes\n",
504 seq_printf(m
, "%llu [%llu] gtt total\n",
505 ggtt
->base
.total
, ggtt
->mappable_end
- ggtt
->base
.start
);
508 print_batch_pool_stats(m
, dev_priv
);
509 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
510 struct file_stats stats
;
511 struct task_struct
*task
;
513 memset(&stats
, 0, sizeof(stats
));
514 stats
.file_priv
= file
->driver_priv
;
515 spin_lock(&file
->table_lock
);
516 idr_for_each(&file
->object_idr
, per_file_stats
, &stats
);
517 spin_unlock(&file
->table_lock
);
519 * Although we have a valid reference on file->pid, that does
520 * not guarantee that the task_struct who called get_pid() is
521 * still alive (e.g. get_pid(current) => fork() => exit()).
522 * Therefore, we need to protect this ->comm access using RCU.
525 task
= pid_task(file
->pid
, PIDTYPE_PID
);
526 print_file_stats(m
, task
? task
->comm
: "<unknown>", stats
);
530 mutex_unlock(&dev
->struct_mutex
);
535 static int i915_gem_gtt_info(struct seq_file
*m
, void *data
)
537 struct drm_info_node
*node
= m
->private;
538 struct drm_device
*dev
= node
->minor
->dev
;
539 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
540 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
541 struct drm_i915_gem_object
*obj
;
542 u64 total_obj_size
, total_gtt_size
;
545 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
549 total_obj_size
= total_gtt_size
= count
= 0;
550 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
551 if (list
== PINNED_LIST
&& !i915_gem_obj_is_pinned(obj
))
555 describe_obj(m
, obj
);
557 total_obj_size
+= obj
->base
.size
;
558 total_gtt_size
+= i915_gem_obj_total_ggtt_size(obj
);
562 mutex_unlock(&dev
->struct_mutex
);
564 seq_printf(m
, "Total %d objects, %llu bytes, %llu GTT size\n",
565 count
, total_obj_size
, total_gtt_size
);
570 static int i915_gem_pageflip_info(struct seq_file
*m
, void *data
)
572 struct drm_info_node
*node
= m
->private;
573 struct drm_device
*dev
= node
->minor
->dev
;
574 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
575 struct intel_crtc
*crtc
;
578 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
582 for_each_intel_crtc(dev
, crtc
) {
583 const char pipe
= pipe_name(crtc
->pipe
);
584 const char plane
= plane_name(crtc
->plane
);
585 struct intel_unpin_work
*work
;
587 spin_lock_irq(&dev
->event_lock
);
588 work
= crtc
->unpin_work
;
590 seq_printf(m
, "No flip due on pipe %c (plane %c)\n",
595 if (atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
596 seq_printf(m
, "Flip queued on pipe %c (plane %c)\n",
599 seq_printf(m
, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
602 if (work
->flip_queued_req
) {
603 struct intel_engine_cs
*engine
= i915_gem_request_get_engine(work
->flip_queued_req
);
605 seq_printf(m
, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
607 i915_gem_request_get_seqno(work
->flip_queued_req
),
608 dev_priv
->next_seqno
,
609 engine
->get_seqno(engine
),
610 i915_gem_request_completed(work
->flip_queued_req
, true));
612 seq_printf(m
, "Flip not associated with any ring\n");
613 seq_printf(m
, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
614 work
->flip_queued_vblank
,
615 work
->flip_ready_vblank
,
616 drm_crtc_vblank_count(&crtc
->base
));
617 if (work
->enable_stall_check
)
618 seq_puts(m
, "Stall check enabled, ");
620 seq_puts(m
, "Stall check waiting for page flip ioctl, ");
621 seq_printf(m
, "%d prepares\n", atomic_read(&work
->pending
));
623 if (INTEL_INFO(dev
)->gen
>= 4)
624 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(crtc
->plane
)));
626 addr
= I915_READ(DSPADDR(crtc
->plane
));
627 seq_printf(m
, "Current scanout address 0x%08x\n", addr
);
629 if (work
->pending_flip_obj
) {
630 seq_printf(m
, "New framebuffer address 0x%08lx\n", (long)work
->gtt_offset
);
631 seq_printf(m
, "MMIO update completed? %d\n", addr
== work
->gtt_offset
);
634 spin_unlock_irq(&dev
->event_lock
);
637 mutex_unlock(&dev
->struct_mutex
);
642 static int i915_gem_batch_pool_info(struct seq_file
*m
, void *data
)
644 struct drm_info_node
*node
= m
->private;
645 struct drm_device
*dev
= node
->minor
->dev
;
646 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
647 struct drm_i915_gem_object
*obj
;
648 struct intel_engine_cs
*engine
;
652 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
656 for_each_engine(engine
, dev_priv
) {
657 for (j
= 0; j
< ARRAY_SIZE(engine
->batch_pool
.cache_list
); j
++) {
661 list_for_each_entry(obj
,
662 &engine
->batch_pool
.cache_list
[j
],
665 seq_printf(m
, "%s cache[%d]: %d objects\n",
666 engine
->name
, j
, count
);
668 list_for_each_entry(obj
,
669 &engine
->batch_pool
.cache_list
[j
],
672 describe_obj(m
, obj
);
680 seq_printf(m
, "total: %d\n", total
);
682 mutex_unlock(&dev
->struct_mutex
);
687 static int i915_gem_request_info(struct seq_file
*m
, void *data
)
689 struct drm_info_node
*node
= m
->private;
690 struct drm_device
*dev
= node
->minor
->dev
;
691 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
692 struct intel_engine_cs
*engine
;
693 struct drm_i915_gem_request
*req
;
696 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
701 for_each_engine(engine
, dev_priv
) {
705 list_for_each_entry(req
, &engine
->request_list
, list
)
710 seq_printf(m
, "%s requests: %d\n", engine
->name
, count
);
711 list_for_each_entry(req
, &engine
->request_list
, list
) {
712 struct task_struct
*task
;
717 task
= pid_task(req
->pid
, PIDTYPE_PID
);
718 seq_printf(m
, " %x @ %d: %s [%d]\n",
720 (int) (jiffies
- req
->emitted_jiffies
),
721 task
? task
->comm
: "<unknown>",
722 task
? task
->pid
: -1);
728 mutex_unlock(&dev
->struct_mutex
);
731 seq_puts(m
, "No requests\n");
736 static void i915_ring_seqno_info(struct seq_file
*m
,
737 struct intel_engine_cs
*engine
)
739 seq_printf(m
, "Current sequence (%s): %x\n",
740 engine
->name
, engine
->get_seqno(engine
));
741 seq_printf(m
, "Current user interrupts (%s): %x\n",
742 engine
->name
, READ_ONCE(engine
->user_interrupts
));
745 static int i915_gem_seqno_info(struct seq_file
*m
, void *data
)
747 struct drm_info_node
*node
= m
->private;
748 struct drm_device
*dev
= node
->minor
->dev
;
749 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
750 struct intel_engine_cs
*engine
;
753 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
756 intel_runtime_pm_get(dev_priv
);
758 for_each_engine(engine
, dev_priv
)
759 i915_ring_seqno_info(m
, engine
);
761 intel_runtime_pm_put(dev_priv
);
762 mutex_unlock(&dev
->struct_mutex
);
768 static int i915_interrupt_info(struct seq_file
*m
, void *data
)
770 struct drm_info_node
*node
= m
->private;
771 struct drm_device
*dev
= node
->minor
->dev
;
772 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
773 struct intel_engine_cs
*engine
;
776 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
779 intel_runtime_pm_get(dev_priv
);
781 if (IS_CHERRYVIEW(dev
)) {
782 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
783 I915_READ(GEN8_MASTER_IRQ
));
785 seq_printf(m
, "Display IER:\t%08x\n",
787 seq_printf(m
, "Display IIR:\t%08x\n",
789 seq_printf(m
, "Display IIR_RW:\t%08x\n",
790 I915_READ(VLV_IIR_RW
));
791 seq_printf(m
, "Display IMR:\t%08x\n",
793 for_each_pipe(dev_priv
, pipe
)
794 seq_printf(m
, "Pipe %c stat:\t%08x\n",
796 I915_READ(PIPESTAT(pipe
)));
798 seq_printf(m
, "Port hotplug:\t%08x\n",
799 I915_READ(PORT_HOTPLUG_EN
));
800 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
801 I915_READ(VLV_DPFLIPSTAT
));
802 seq_printf(m
, "DPINVGTT:\t%08x\n",
803 I915_READ(DPINVGTT
));
805 for (i
= 0; i
< 4; i
++) {
806 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
807 i
, I915_READ(GEN8_GT_IMR(i
)));
808 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
809 i
, I915_READ(GEN8_GT_IIR(i
)));
810 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
811 i
, I915_READ(GEN8_GT_IER(i
)));
814 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
815 I915_READ(GEN8_PCU_IMR
));
816 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
817 I915_READ(GEN8_PCU_IIR
));
818 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
819 I915_READ(GEN8_PCU_IER
));
820 } else if (INTEL_INFO(dev
)->gen
>= 8) {
821 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
822 I915_READ(GEN8_MASTER_IRQ
));
824 for (i
= 0; i
< 4; i
++) {
825 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
826 i
, I915_READ(GEN8_GT_IMR(i
)));
827 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
828 i
, I915_READ(GEN8_GT_IIR(i
)));
829 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
830 i
, I915_READ(GEN8_GT_IER(i
)));
833 for_each_pipe(dev_priv
, pipe
) {
834 enum intel_display_power_domain power_domain
;
836 power_domain
= POWER_DOMAIN_PIPE(pipe
);
837 if (!intel_display_power_get_if_enabled(dev_priv
,
839 seq_printf(m
, "Pipe %c power disabled\n",
843 seq_printf(m
, "Pipe %c IMR:\t%08x\n",
845 I915_READ(GEN8_DE_PIPE_IMR(pipe
)));
846 seq_printf(m
, "Pipe %c IIR:\t%08x\n",
848 I915_READ(GEN8_DE_PIPE_IIR(pipe
)));
849 seq_printf(m
, "Pipe %c IER:\t%08x\n",
851 I915_READ(GEN8_DE_PIPE_IER(pipe
)));
853 intel_display_power_put(dev_priv
, power_domain
);
856 seq_printf(m
, "Display Engine port interrupt mask:\t%08x\n",
857 I915_READ(GEN8_DE_PORT_IMR
));
858 seq_printf(m
, "Display Engine port interrupt identity:\t%08x\n",
859 I915_READ(GEN8_DE_PORT_IIR
));
860 seq_printf(m
, "Display Engine port interrupt enable:\t%08x\n",
861 I915_READ(GEN8_DE_PORT_IER
));
863 seq_printf(m
, "Display Engine misc interrupt mask:\t%08x\n",
864 I915_READ(GEN8_DE_MISC_IMR
));
865 seq_printf(m
, "Display Engine misc interrupt identity:\t%08x\n",
866 I915_READ(GEN8_DE_MISC_IIR
));
867 seq_printf(m
, "Display Engine misc interrupt enable:\t%08x\n",
868 I915_READ(GEN8_DE_MISC_IER
));
870 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
871 I915_READ(GEN8_PCU_IMR
));
872 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
873 I915_READ(GEN8_PCU_IIR
));
874 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
875 I915_READ(GEN8_PCU_IER
));
876 } else if (IS_VALLEYVIEW(dev
)) {
877 seq_printf(m
, "Display IER:\t%08x\n",
879 seq_printf(m
, "Display IIR:\t%08x\n",
881 seq_printf(m
, "Display IIR_RW:\t%08x\n",
882 I915_READ(VLV_IIR_RW
));
883 seq_printf(m
, "Display IMR:\t%08x\n",
885 for_each_pipe(dev_priv
, pipe
)
886 seq_printf(m
, "Pipe %c stat:\t%08x\n",
888 I915_READ(PIPESTAT(pipe
)));
890 seq_printf(m
, "Master IER:\t%08x\n",
891 I915_READ(VLV_MASTER_IER
));
893 seq_printf(m
, "Render IER:\t%08x\n",
895 seq_printf(m
, "Render IIR:\t%08x\n",
897 seq_printf(m
, "Render IMR:\t%08x\n",
900 seq_printf(m
, "PM IER:\t\t%08x\n",
901 I915_READ(GEN6_PMIER
));
902 seq_printf(m
, "PM IIR:\t\t%08x\n",
903 I915_READ(GEN6_PMIIR
));
904 seq_printf(m
, "PM IMR:\t\t%08x\n",
905 I915_READ(GEN6_PMIMR
));
907 seq_printf(m
, "Port hotplug:\t%08x\n",
908 I915_READ(PORT_HOTPLUG_EN
));
909 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
910 I915_READ(VLV_DPFLIPSTAT
));
911 seq_printf(m
, "DPINVGTT:\t%08x\n",
912 I915_READ(DPINVGTT
));
914 } else if (!HAS_PCH_SPLIT(dev
)) {
915 seq_printf(m
, "Interrupt enable: %08x\n",
917 seq_printf(m
, "Interrupt identity: %08x\n",
919 seq_printf(m
, "Interrupt mask: %08x\n",
921 for_each_pipe(dev_priv
, pipe
)
922 seq_printf(m
, "Pipe %c stat: %08x\n",
924 I915_READ(PIPESTAT(pipe
)));
926 seq_printf(m
, "North Display Interrupt enable: %08x\n",
928 seq_printf(m
, "North Display Interrupt identity: %08x\n",
930 seq_printf(m
, "North Display Interrupt mask: %08x\n",
932 seq_printf(m
, "South Display Interrupt enable: %08x\n",
934 seq_printf(m
, "South Display Interrupt identity: %08x\n",
936 seq_printf(m
, "South Display Interrupt mask: %08x\n",
938 seq_printf(m
, "Graphics Interrupt enable: %08x\n",
940 seq_printf(m
, "Graphics Interrupt identity: %08x\n",
942 seq_printf(m
, "Graphics Interrupt mask: %08x\n",
945 for_each_engine(engine
, dev_priv
) {
946 if (INTEL_INFO(dev
)->gen
>= 6) {
948 "Graphics Interrupt mask (%s): %08x\n",
949 engine
->name
, I915_READ_IMR(engine
));
951 i915_ring_seqno_info(m
, engine
);
953 intel_runtime_pm_put(dev_priv
);
954 mutex_unlock(&dev
->struct_mutex
);
959 static int i915_gem_fence_regs_info(struct seq_file
*m
, void *data
)
961 struct drm_info_node
*node
= m
->private;
962 struct drm_device
*dev
= node
->minor
->dev
;
963 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
966 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
970 seq_printf(m
, "Total fences = %d\n", dev_priv
->num_fence_regs
);
971 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
972 struct drm_i915_gem_object
*obj
= dev_priv
->fence_regs
[i
].obj
;
974 seq_printf(m
, "Fence %d, pin count = %d, object = ",
975 i
, dev_priv
->fence_regs
[i
].pin_count
);
977 seq_puts(m
, "unused");
979 describe_obj(m
, obj
);
983 mutex_unlock(&dev
->struct_mutex
);
987 static int i915_hws_info(struct seq_file
*m
, void *data
)
989 struct drm_info_node
*node
= m
->private;
990 struct drm_device
*dev
= node
->minor
->dev
;
991 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
992 struct intel_engine_cs
*engine
;
996 engine
= &dev_priv
->engine
[(uintptr_t)node
->info_ent
->data
];
997 hws
= engine
->status_page
.page_addr
;
1001 for (i
= 0; i
< 4096 / sizeof(u32
) / 4; i
+= 4) {
1002 seq_printf(m
, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1004 hws
[i
], hws
[i
+ 1], hws
[i
+ 2], hws
[i
+ 3]);
1010 i915_error_state_write(struct file
*filp
,
1011 const char __user
*ubuf
,
1015 struct i915_error_state_file_priv
*error_priv
= filp
->private_data
;
1016 struct drm_device
*dev
= error_priv
->dev
;
1019 DRM_DEBUG_DRIVER("Resetting error state\n");
1021 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1025 i915_destroy_error_state(dev
);
1026 mutex_unlock(&dev
->struct_mutex
);
1031 static int i915_error_state_open(struct inode
*inode
, struct file
*file
)
1033 struct drm_device
*dev
= inode
->i_private
;
1034 struct i915_error_state_file_priv
*error_priv
;
1036 error_priv
= kzalloc(sizeof(*error_priv
), GFP_KERNEL
);
1040 error_priv
->dev
= dev
;
1042 i915_error_state_get(dev
, error_priv
);
1044 file
->private_data
= error_priv
;
1049 static int i915_error_state_release(struct inode
*inode
, struct file
*file
)
1051 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
1053 i915_error_state_put(error_priv
);
1059 static ssize_t
i915_error_state_read(struct file
*file
, char __user
*userbuf
,
1060 size_t count
, loff_t
*pos
)
1062 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
1063 struct drm_i915_error_state_buf error_str
;
1065 ssize_t ret_count
= 0;
1068 ret
= i915_error_state_buf_init(&error_str
, to_i915(error_priv
->dev
), count
, *pos
);
1072 ret
= i915_error_state_to_str(&error_str
, error_priv
);
1076 ret_count
= simple_read_from_buffer(userbuf
, count
, &tmp_pos
,
1083 *pos
= error_str
.start
+ ret_count
;
1085 i915_error_state_buf_release(&error_str
);
1086 return ret
?: ret_count
;
1089 static const struct file_operations i915_error_state_fops
= {
1090 .owner
= THIS_MODULE
,
1091 .open
= i915_error_state_open
,
1092 .read
= i915_error_state_read
,
1093 .write
= i915_error_state_write
,
1094 .llseek
= default_llseek
,
1095 .release
= i915_error_state_release
,
1099 i915_next_seqno_get(void *data
, u64
*val
)
1101 struct drm_device
*dev
= data
;
1102 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1105 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1109 *val
= dev_priv
->next_seqno
;
1110 mutex_unlock(&dev
->struct_mutex
);
1116 i915_next_seqno_set(void *data
, u64 val
)
1118 struct drm_device
*dev
= data
;
1121 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1125 ret
= i915_gem_set_seqno(dev
, val
);
1126 mutex_unlock(&dev
->struct_mutex
);
1131 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops
,
1132 i915_next_seqno_get
, i915_next_seqno_set
,
1135 static int i915_frequency_info(struct seq_file
*m
, void *unused
)
1137 struct drm_info_node
*node
= m
->private;
1138 struct drm_device
*dev
= node
->minor
->dev
;
1139 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1142 intel_runtime_pm_get(dev_priv
);
1144 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
1147 u16 rgvswctl
= I915_READ16(MEMSWCTL
);
1148 u16 rgvstat
= I915_READ16(MEMSTAT_ILK
);
1150 seq_printf(m
, "Requested P-state: %d\n", (rgvswctl
>> 8) & 0xf);
1151 seq_printf(m
, "Requested VID: %d\n", rgvswctl
& 0x3f);
1152 seq_printf(m
, "Current VID: %d\n", (rgvstat
& MEMSTAT_VID_MASK
) >>
1154 seq_printf(m
, "Current P-state: %d\n",
1155 (rgvstat
& MEMSTAT_PSTATE_MASK
) >> MEMSTAT_PSTATE_SHIFT
);
1156 } else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
1159 mutex_lock(&dev_priv
->rps
.hw_lock
);
1160 freq_sts
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
1161 seq_printf(m
, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts
);
1162 seq_printf(m
, "DDR freq: %d MHz\n", dev_priv
->mem_freq
);
1164 seq_printf(m
, "actual GPU freq: %d MHz\n",
1165 intel_gpu_freq(dev_priv
, (freq_sts
>> 8) & 0xff));
1167 seq_printf(m
, "current GPU freq: %d MHz\n",
1168 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
));
1170 seq_printf(m
, "max GPU freq: %d MHz\n",
1171 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1173 seq_printf(m
, "min GPU freq: %d MHz\n",
1174 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
));
1176 seq_printf(m
, "idle GPU freq: %d MHz\n",
1177 intel_gpu_freq(dev_priv
, dev_priv
->rps
.idle_freq
));
1180 "efficient (RPe) frequency: %d MHz\n",
1181 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
));
1182 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1183 } else if (INTEL_INFO(dev
)->gen
>= 6) {
1184 u32 rp_state_limits
;
1187 u32 rpmodectl
, rpinclimit
, rpdeclimit
;
1188 u32 rpstat
, cagf
, reqf
;
1189 u32 rpupei
, rpcurup
, rpprevup
;
1190 u32 rpdownei
, rpcurdown
, rpprevdown
;
1191 u32 pm_ier
, pm_imr
, pm_isr
, pm_iir
, pm_mask
;
1194 rp_state_limits
= I915_READ(GEN6_RP_STATE_LIMITS
);
1195 if (IS_BROXTON(dev
)) {
1196 rp_state_cap
= I915_READ(BXT_RP_STATE_CAP
);
1197 gt_perf_status
= I915_READ(BXT_GT_PERF_STATUS
);
1199 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
1200 gt_perf_status
= I915_READ(GEN6_GT_PERF_STATUS
);
1203 /* RPSTAT1 is in the GT power well */
1204 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1208 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
1210 reqf
= I915_READ(GEN6_RPNSWREQ
);
1214 reqf
&= ~GEN6_TURBO_DISABLE
;
1215 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1220 reqf
= intel_gpu_freq(dev_priv
, reqf
);
1222 rpmodectl
= I915_READ(GEN6_RP_CONTROL
);
1223 rpinclimit
= I915_READ(GEN6_RP_UP_THRESHOLD
);
1224 rpdeclimit
= I915_READ(GEN6_RP_DOWN_THRESHOLD
);
1226 rpstat
= I915_READ(GEN6_RPSTAT1
);
1227 rpupei
= I915_READ(GEN6_RP_CUR_UP_EI
);
1228 rpcurup
= I915_READ(GEN6_RP_CUR_UP
);
1229 rpprevup
= I915_READ(GEN6_RP_PREV_UP
);
1230 rpdownei
= I915_READ(GEN6_RP_CUR_DOWN_EI
);
1231 rpcurdown
= I915_READ(GEN6_RP_CUR_DOWN
);
1232 rpprevdown
= I915_READ(GEN6_RP_PREV_DOWN
);
1234 cagf
= (rpstat
& GEN9_CAGF_MASK
) >> GEN9_CAGF_SHIFT
;
1235 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1236 cagf
= (rpstat
& HSW_CAGF_MASK
) >> HSW_CAGF_SHIFT
;
1238 cagf
= (rpstat
& GEN6_CAGF_MASK
) >> GEN6_CAGF_SHIFT
;
1239 cagf
= intel_gpu_freq(dev_priv
, cagf
);
1241 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
1242 mutex_unlock(&dev
->struct_mutex
);
1244 if (IS_GEN6(dev
) || IS_GEN7(dev
)) {
1245 pm_ier
= I915_READ(GEN6_PMIER
);
1246 pm_imr
= I915_READ(GEN6_PMIMR
);
1247 pm_isr
= I915_READ(GEN6_PMISR
);
1248 pm_iir
= I915_READ(GEN6_PMIIR
);
1249 pm_mask
= I915_READ(GEN6_PMINTRMSK
);
1251 pm_ier
= I915_READ(GEN8_GT_IER(2));
1252 pm_imr
= I915_READ(GEN8_GT_IMR(2));
1253 pm_isr
= I915_READ(GEN8_GT_ISR(2));
1254 pm_iir
= I915_READ(GEN8_GT_IIR(2));
1255 pm_mask
= I915_READ(GEN6_PMINTRMSK
);
1257 seq_printf(m
, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1258 pm_ier
, pm_imr
, pm_isr
, pm_iir
, pm_mask
);
1259 seq_printf(m
, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status
);
1260 seq_printf(m
, "Render p-state ratio: %d\n",
1261 (gt_perf_status
& (IS_GEN9(dev
) ? 0x1ff00 : 0xff00)) >> 8);
1262 seq_printf(m
, "Render p-state VID: %d\n",
1263 gt_perf_status
& 0xff);
1264 seq_printf(m
, "Render p-state limit: %d\n",
1265 rp_state_limits
& 0xff);
1266 seq_printf(m
, "RPSTAT1: 0x%08x\n", rpstat
);
1267 seq_printf(m
, "RPMODECTL: 0x%08x\n", rpmodectl
);
1268 seq_printf(m
, "RPINCLIMIT: 0x%08x\n", rpinclimit
);
1269 seq_printf(m
, "RPDECLIMIT: 0x%08x\n", rpdeclimit
);
1270 seq_printf(m
, "RPNSWREQ: %dMHz\n", reqf
);
1271 seq_printf(m
, "CAGF: %dMHz\n", cagf
);
1272 seq_printf(m
, "RP CUR UP EI: %dus\n", rpupei
&
1273 GEN6_CURICONT_MASK
);
1274 seq_printf(m
, "RP CUR UP: %dus\n", rpcurup
&
1275 GEN6_CURBSYTAVG_MASK
);
1276 seq_printf(m
, "RP PREV UP: %dus\n", rpprevup
&
1277 GEN6_CURBSYTAVG_MASK
);
1278 seq_printf(m
, "Up threshold: %d%%\n",
1279 dev_priv
->rps
.up_threshold
);
1281 seq_printf(m
, "RP CUR DOWN EI: %dus\n", rpdownei
&
1283 seq_printf(m
, "RP CUR DOWN: %dus\n", rpcurdown
&
1284 GEN6_CURBSYTAVG_MASK
);
1285 seq_printf(m
, "RP PREV DOWN: %dus\n", rpprevdown
&
1286 GEN6_CURBSYTAVG_MASK
);
1287 seq_printf(m
, "Down threshold: %d%%\n",
1288 dev_priv
->rps
.down_threshold
);
1290 max_freq
= (IS_BROXTON(dev
) ? rp_state_cap
>> 0 :
1291 rp_state_cap
>> 16) & 0xff;
1292 max_freq
*= (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
) ?
1293 GEN9_FREQ_SCALER
: 1);
1294 seq_printf(m
, "Lowest (RPN) frequency: %dMHz\n",
1295 intel_gpu_freq(dev_priv
, max_freq
));
1297 max_freq
= (rp_state_cap
& 0xff00) >> 8;
1298 max_freq
*= (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
) ?
1299 GEN9_FREQ_SCALER
: 1);
1300 seq_printf(m
, "Nominal (RP1) frequency: %dMHz\n",
1301 intel_gpu_freq(dev_priv
, max_freq
));
1303 max_freq
= (IS_BROXTON(dev
) ? rp_state_cap
>> 16 :
1304 rp_state_cap
>> 0) & 0xff;
1305 max_freq
*= (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
) ?
1306 GEN9_FREQ_SCALER
: 1);
1307 seq_printf(m
, "Max non-overclocked (RP0) frequency: %dMHz\n",
1308 intel_gpu_freq(dev_priv
, max_freq
));
1309 seq_printf(m
, "Max overclocked frequency: %dMHz\n",
1310 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1312 seq_printf(m
, "Current freq: %d MHz\n",
1313 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
));
1314 seq_printf(m
, "Actual freq: %d MHz\n", cagf
);
1315 seq_printf(m
, "Idle freq: %d MHz\n",
1316 intel_gpu_freq(dev_priv
, dev_priv
->rps
.idle_freq
));
1317 seq_printf(m
, "Min freq: %d MHz\n",
1318 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
));
1319 seq_printf(m
, "Max freq: %d MHz\n",
1320 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1322 "efficient (RPe) frequency: %d MHz\n",
1323 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
));
1325 seq_puts(m
, "no P-state info available\n");
1328 seq_printf(m
, "Current CD clock frequency: %d kHz\n", dev_priv
->cdclk_freq
);
1329 seq_printf(m
, "Max CD clock frequency: %d kHz\n", dev_priv
->max_cdclk_freq
);
1330 seq_printf(m
, "Max pixel clock frequency: %d kHz\n", dev_priv
->max_dotclk_freq
);
1333 intel_runtime_pm_put(dev_priv
);
1337 static int i915_hangcheck_info(struct seq_file
*m
, void *unused
)
1339 struct drm_info_node
*node
= m
->private;
1340 struct drm_device
*dev
= node
->minor
->dev
;
1341 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1342 struct intel_engine_cs
*engine
;
1343 u64 acthd
[I915_NUM_ENGINES
];
1344 u32 seqno
[I915_NUM_ENGINES
];
1345 u32 instdone
[I915_NUM_INSTDONE_REG
];
1346 enum intel_engine_id id
;
1349 if (!i915
.enable_hangcheck
) {
1350 seq_printf(m
, "Hangcheck disabled\n");
1354 intel_runtime_pm_get(dev_priv
);
1356 for_each_engine_id(engine
, dev_priv
, id
) {
1357 acthd
[id
] = intel_ring_get_active_head(engine
);
1358 seqno
[id
] = engine
->get_seqno(engine
);
1361 i915_get_extra_instdone(dev
, instdone
);
1363 intel_runtime_pm_put(dev_priv
);
1365 if (delayed_work_pending(&dev_priv
->gpu_error
.hangcheck_work
)) {
1366 seq_printf(m
, "Hangcheck active, fires in %dms\n",
1367 jiffies_to_msecs(dev_priv
->gpu_error
.hangcheck_work
.timer
.expires
-
1370 seq_printf(m
, "Hangcheck inactive\n");
1372 for_each_engine_id(engine
, dev_priv
, id
) {
1373 seq_printf(m
, "%s:\n", engine
->name
);
1374 seq_printf(m
, "\tseqno = %x [current %x, last %x]\n",
1375 engine
->hangcheck
.seqno
,
1377 engine
->last_submitted_seqno
);
1378 seq_printf(m
, "\tuser interrupts = %x [current %x]\n",
1379 engine
->hangcheck
.user_interrupts
,
1380 READ_ONCE(engine
->user_interrupts
));
1381 seq_printf(m
, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1382 (long long)engine
->hangcheck
.acthd
,
1383 (long long)acthd
[id
]);
1384 seq_printf(m
, "\tscore = %d\n", engine
->hangcheck
.score
);
1385 seq_printf(m
, "\taction = %d\n", engine
->hangcheck
.action
);
1387 if (engine
->id
== RCS
) {
1388 seq_puts(m
, "\tinstdone read =");
1390 for (j
= 0; j
< I915_NUM_INSTDONE_REG
; j
++)
1391 seq_printf(m
, " 0x%08x", instdone
[j
]);
1393 seq_puts(m
, "\n\tinstdone accu =");
1395 for (j
= 0; j
< I915_NUM_INSTDONE_REG
; j
++)
1396 seq_printf(m
, " 0x%08x",
1397 engine
->hangcheck
.instdone
[j
]);
1406 static int ironlake_drpc_info(struct seq_file
*m
)
1408 struct drm_info_node
*node
= m
->private;
1409 struct drm_device
*dev
= node
->minor
->dev
;
1410 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1411 u32 rgvmodectl
, rstdbyctl
;
1415 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1418 intel_runtime_pm_get(dev_priv
);
1420 rgvmodectl
= I915_READ(MEMMODECTL
);
1421 rstdbyctl
= I915_READ(RSTDBYCTL
);
1422 crstandvid
= I915_READ16(CRSTANDVID
);
1424 intel_runtime_pm_put(dev_priv
);
1425 mutex_unlock(&dev
->struct_mutex
);
1427 seq_printf(m
, "HD boost: %s\n", yesno(rgvmodectl
& MEMMODE_BOOST_EN
));
1428 seq_printf(m
, "Boost freq: %d\n",
1429 (rgvmodectl
& MEMMODE_BOOST_FREQ_MASK
) >>
1430 MEMMODE_BOOST_FREQ_SHIFT
);
1431 seq_printf(m
, "HW control enabled: %s\n",
1432 yesno(rgvmodectl
& MEMMODE_HWIDLE_EN
));
1433 seq_printf(m
, "SW control enabled: %s\n",
1434 yesno(rgvmodectl
& MEMMODE_SWMODE_EN
));
1435 seq_printf(m
, "Gated voltage change: %s\n",
1436 yesno(rgvmodectl
& MEMMODE_RCLK_GATE
));
1437 seq_printf(m
, "Starting frequency: P%d\n",
1438 (rgvmodectl
& MEMMODE_FSTART_MASK
) >> MEMMODE_FSTART_SHIFT
);
1439 seq_printf(m
, "Max P-state: P%d\n",
1440 (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
);
1441 seq_printf(m
, "Min P-state: P%d\n", (rgvmodectl
& MEMMODE_FMIN_MASK
));
1442 seq_printf(m
, "RS1 VID: %d\n", (crstandvid
& 0x3f));
1443 seq_printf(m
, "RS2 VID: %d\n", ((crstandvid
>> 8) & 0x3f));
1444 seq_printf(m
, "Render standby enabled: %s\n",
1445 yesno(!(rstdbyctl
& RCX_SW_EXIT
)));
1446 seq_puts(m
, "Current RS state: ");
1447 switch (rstdbyctl
& RSX_STATUS_MASK
) {
1449 seq_puts(m
, "on\n");
1451 case RSX_STATUS_RC1
:
1452 seq_puts(m
, "RC1\n");
1454 case RSX_STATUS_RC1E
:
1455 seq_puts(m
, "RC1E\n");
1457 case RSX_STATUS_RS1
:
1458 seq_puts(m
, "RS1\n");
1460 case RSX_STATUS_RS2
:
1461 seq_puts(m
, "RS2 (RC6)\n");
1463 case RSX_STATUS_RS3
:
1464 seq_puts(m
, "RC3 (RC6+)\n");
1467 seq_puts(m
, "unknown\n");
1474 static int i915_forcewake_domains(struct seq_file
*m
, void *data
)
1476 struct drm_info_node
*node
= m
->private;
1477 struct drm_device
*dev
= node
->minor
->dev
;
1478 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1479 struct intel_uncore_forcewake_domain
*fw_domain
;
1481 spin_lock_irq(&dev_priv
->uncore
.lock
);
1482 for_each_fw_domain(fw_domain
, dev_priv
) {
1483 seq_printf(m
, "%s.wake_count = %u\n",
1484 intel_uncore_forcewake_domain_to_str(fw_domain
->id
),
1485 fw_domain
->wake_count
);
1487 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1492 static int vlv_drpc_info(struct seq_file
*m
)
1494 struct drm_info_node
*node
= m
->private;
1495 struct drm_device
*dev
= node
->minor
->dev
;
1496 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1497 u32 rpmodectl1
, rcctl1
, pw_status
;
1499 intel_runtime_pm_get(dev_priv
);
1501 pw_status
= I915_READ(VLV_GTLC_PW_STATUS
);
1502 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1503 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1505 intel_runtime_pm_put(dev_priv
);
1507 seq_printf(m
, "Video Turbo Mode: %s\n",
1508 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1509 seq_printf(m
, "Turbo enabled: %s\n",
1510 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1511 seq_printf(m
, "HW control enabled: %s\n",
1512 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1513 seq_printf(m
, "SW control enabled: %s\n",
1514 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1515 GEN6_RP_MEDIA_SW_MODE
));
1516 seq_printf(m
, "RC6 Enabled: %s\n",
1517 yesno(rcctl1
& (GEN7_RC_CTL_TO_MODE
|
1518 GEN6_RC_CTL_EI_MODE(1))));
1519 seq_printf(m
, "Render Power Well: %s\n",
1520 (pw_status
& VLV_GTLC_PW_RENDER_STATUS_MASK
) ? "Up" : "Down");
1521 seq_printf(m
, "Media Power Well: %s\n",
1522 (pw_status
& VLV_GTLC_PW_MEDIA_STATUS_MASK
) ? "Up" : "Down");
1524 seq_printf(m
, "Render RC6 residency since boot: %u\n",
1525 I915_READ(VLV_GT_RENDER_RC6
));
1526 seq_printf(m
, "Media RC6 residency since boot: %u\n",
1527 I915_READ(VLV_GT_MEDIA_RC6
));
1529 return i915_forcewake_domains(m
, NULL
);
1532 static int gen6_drpc_info(struct seq_file
*m
)
1534 struct drm_info_node
*node
= m
->private;
1535 struct drm_device
*dev
= node
->minor
->dev
;
1536 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1537 u32 rpmodectl1
, gt_core_status
, rcctl1
, rc6vids
= 0;
1538 unsigned forcewake_count
;
1541 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1544 intel_runtime_pm_get(dev_priv
);
1546 spin_lock_irq(&dev_priv
->uncore
.lock
);
1547 forcewake_count
= dev_priv
->uncore
.fw_domain
[FW_DOMAIN_ID_RENDER
].wake_count
;
1548 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1550 if (forcewake_count
) {
1551 seq_puts(m
, "RC information inaccurate because somebody "
1552 "holds a forcewake reference \n");
1554 /* NB: we cannot use forcewake, else we read the wrong values */
1555 while (count
++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK
) & 1))
1557 seq_printf(m
, "RC information accurate: %s\n", yesno(count
< 51));
1560 gt_core_status
= I915_READ_FW(GEN6_GT_CORE_STATUS
);
1561 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS
, gt_core_status
, 4, true);
1563 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1564 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1565 mutex_unlock(&dev
->struct_mutex
);
1566 mutex_lock(&dev_priv
->rps
.hw_lock
);
1567 sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
1568 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1570 intel_runtime_pm_put(dev_priv
);
1572 seq_printf(m
, "Video Turbo Mode: %s\n",
1573 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1574 seq_printf(m
, "HW control enabled: %s\n",
1575 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1576 seq_printf(m
, "SW control enabled: %s\n",
1577 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1578 GEN6_RP_MEDIA_SW_MODE
));
1579 seq_printf(m
, "RC1e Enabled: %s\n",
1580 yesno(rcctl1
& GEN6_RC_CTL_RC1e_ENABLE
));
1581 seq_printf(m
, "RC6 Enabled: %s\n",
1582 yesno(rcctl1
& GEN6_RC_CTL_RC6_ENABLE
));
1583 seq_printf(m
, "Deep RC6 Enabled: %s\n",
1584 yesno(rcctl1
& GEN6_RC_CTL_RC6p_ENABLE
));
1585 seq_printf(m
, "Deepest RC6 Enabled: %s\n",
1586 yesno(rcctl1
& GEN6_RC_CTL_RC6pp_ENABLE
));
1587 seq_puts(m
, "Current RC state: ");
1588 switch (gt_core_status
& GEN6_RCn_MASK
) {
1590 if (gt_core_status
& GEN6_CORE_CPD_STATE_MASK
)
1591 seq_puts(m
, "Core Power Down\n");
1593 seq_puts(m
, "on\n");
1596 seq_puts(m
, "RC3\n");
1599 seq_puts(m
, "RC6\n");
1602 seq_puts(m
, "RC7\n");
1605 seq_puts(m
, "Unknown\n");
1609 seq_printf(m
, "Core Power Down: %s\n",
1610 yesno(gt_core_status
& GEN6_CORE_CPD_STATE_MASK
));
1612 /* Not exactly sure what this is */
1613 seq_printf(m
, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1614 I915_READ(GEN6_GT_GFX_RC6_LOCKED
));
1615 seq_printf(m
, "RC6 residency since boot: %u\n",
1616 I915_READ(GEN6_GT_GFX_RC6
));
1617 seq_printf(m
, "RC6+ residency since boot: %u\n",
1618 I915_READ(GEN6_GT_GFX_RC6p
));
1619 seq_printf(m
, "RC6++ residency since boot: %u\n",
1620 I915_READ(GEN6_GT_GFX_RC6pp
));
1622 seq_printf(m
, "RC6 voltage: %dmV\n",
1623 GEN6_DECODE_RC6_VID(((rc6vids
>> 0) & 0xff)));
1624 seq_printf(m
, "RC6+ voltage: %dmV\n",
1625 GEN6_DECODE_RC6_VID(((rc6vids
>> 8) & 0xff)));
1626 seq_printf(m
, "RC6++ voltage: %dmV\n",
1627 GEN6_DECODE_RC6_VID(((rc6vids
>> 16) & 0xff)));
1631 static int i915_drpc_info(struct seq_file
*m
, void *unused
)
1633 struct drm_info_node
*node
= m
->private;
1634 struct drm_device
*dev
= node
->minor
->dev
;
1636 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
1637 return vlv_drpc_info(m
);
1638 else if (INTEL_INFO(dev
)->gen
>= 6)
1639 return gen6_drpc_info(m
);
1641 return ironlake_drpc_info(m
);
1644 static int i915_frontbuffer_tracking(struct seq_file
*m
, void *unused
)
1646 struct drm_info_node
*node
= m
->private;
1647 struct drm_device
*dev
= node
->minor
->dev
;
1648 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1650 seq_printf(m
, "FB tracking busy bits: 0x%08x\n",
1651 dev_priv
->fb_tracking
.busy_bits
);
1653 seq_printf(m
, "FB tracking flip bits: 0x%08x\n",
1654 dev_priv
->fb_tracking
.flip_bits
);
1659 static int i915_fbc_status(struct seq_file
*m
, void *unused
)
1661 struct drm_info_node
*node
= m
->private;
1662 struct drm_device
*dev
= node
->minor
->dev
;
1663 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1665 if (!HAS_FBC(dev
)) {
1666 seq_puts(m
, "FBC unsupported on this chipset\n");
1670 intel_runtime_pm_get(dev_priv
);
1671 mutex_lock(&dev_priv
->fbc
.lock
);
1673 if (intel_fbc_is_active(dev_priv
))
1674 seq_puts(m
, "FBC enabled\n");
1676 seq_printf(m
, "FBC disabled: %s\n",
1677 dev_priv
->fbc
.no_fbc_reason
);
1679 if (INTEL_INFO(dev_priv
)->gen
>= 7)
1680 seq_printf(m
, "Compressing: %s\n",
1681 yesno(I915_READ(FBC_STATUS2
) &
1682 FBC_COMPRESSION_MASK
));
1684 mutex_unlock(&dev_priv
->fbc
.lock
);
1685 intel_runtime_pm_put(dev_priv
);
1690 static int i915_fbc_fc_get(void *data
, u64
*val
)
1692 struct drm_device
*dev
= data
;
1693 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1695 if (INTEL_INFO(dev
)->gen
< 7 || !HAS_FBC(dev
))
1698 *val
= dev_priv
->fbc
.false_color
;
1703 static int i915_fbc_fc_set(void *data
, u64 val
)
1705 struct drm_device
*dev
= data
;
1706 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1709 if (INTEL_INFO(dev
)->gen
< 7 || !HAS_FBC(dev
))
1712 mutex_lock(&dev_priv
->fbc
.lock
);
1714 reg
= I915_READ(ILK_DPFC_CONTROL
);
1715 dev_priv
->fbc
.false_color
= val
;
1717 I915_WRITE(ILK_DPFC_CONTROL
, val
?
1718 (reg
| FBC_CTL_FALSE_COLOR
) :
1719 (reg
& ~FBC_CTL_FALSE_COLOR
));
1721 mutex_unlock(&dev_priv
->fbc
.lock
);
1725 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops
,
1726 i915_fbc_fc_get
, i915_fbc_fc_set
,
1729 static int i915_ips_status(struct seq_file
*m
, void *unused
)
1731 struct drm_info_node
*node
= m
->private;
1732 struct drm_device
*dev
= node
->minor
->dev
;
1733 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1735 if (!HAS_IPS(dev
)) {
1736 seq_puts(m
, "not supported\n");
1740 intel_runtime_pm_get(dev_priv
);
1742 seq_printf(m
, "Enabled by kernel parameter: %s\n",
1743 yesno(i915
.enable_ips
));
1745 if (INTEL_INFO(dev
)->gen
>= 8) {
1746 seq_puts(m
, "Currently: unknown\n");
1748 if (I915_READ(IPS_CTL
) & IPS_ENABLE
)
1749 seq_puts(m
, "Currently: enabled\n");
1751 seq_puts(m
, "Currently: disabled\n");
1754 intel_runtime_pm_put(dev_priv
);
1759 static int i915_sr_status(struct seq_file
*m
, void *unused
)
1761 struct drm_info_node
*node
= m
->private;
1762 struct drm_device
*dev
= node
->minor
->dev
;
1763 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1764 bool sr_enabled
= false;
1766 intel_runtime_pm_get(dev_priv
);
1768 if (HAS_PCH_SPLIT(dev
))
1769 sr_enabled
= I915_READ(WM1_LP_ILK
) & WM1_LP_SR_EN
;
1770 else if (IS_CRESTLINE(dev
) || IS_G4X(dev
) ||
1771 IS_I945G(dev
) || IS_I945GM(dev
))
1772 sr_enabled
= I915_READ(FW_BLC_SELF
) & FW_BLC_SELF_EN
;
1773 else if (IS_I915GM(dev
))
1774 sr_enabled
= I915_READ(INSTPM
) & INSTPM_SELF_EN
;
1775 else if (IS_PINEVIEW(dev
))
1776 sr_enabled
= I915_READ(DSPFW3
) & PINEVIEW_SELF_REFRESH_EN
;
1777 else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
1778 sr_enabled
= I915_READ(FW_BLC_SELF_VLV
) & FW_CSPWRDWNEN
;
1780 intel_runtime_pm_put(dev_priv
);
1782 seq_printf(m
, "self-refresh: %s\n",
1783 sr_enabled
? "enabled" : "disabled");
1788 static int i915_emon_status(struct seq_file
*m
, void *unused
)
1790 struct drm_info_node
*node
= m
->private;
1791 struct drm_device
*dev
= node
->minor
->dev
;
1792 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1793 unsigned long temp
, chipset
, gfx
;
1799 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1803 temp
= i915_mch_val(dev_priv
);
1804 chipset
= i915_chipset_val(dev_priv
);
1805 gfx
= i915_gfx_val(dev_priv
);
1806 mutex_unlock(&dev
->struct_mutex
);
1808 seq_printf(m
, "GMCH temp: %ld\n", temp
);
1809 seq_printf(m
, "Chipset power: %ld\n", chipset
);
1810 seq_printf(m
, "GFX power: %ld\n", gfx
);
1811 seq_printf(m
, "Total power: %ld\n", chipset
+ gfx
);
1816 static int i915_ring_freq_table(struct seq_file
*m
, void *unused
)
1818 struct drm_info_node
*node
= m
->private;
1819 struct drm_device
*dev
= node
->minor
->dev
;
1820 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1822 int gpu_freq
, ia_freq
;
1823 unsigned int max_gpu_freq
, min_gpu_freq
;
1825 if (!HAS_CORE_RING_FREQ(dev
)) {
1826 seq_puts(m
, "unsupported on this chipset\n");
1830 intel_runtime_pm_get(dev_priv
);
1832 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
1834 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
1838 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
1839 /* Convert GT frequency to 50 HZ units */
1841 dev_priv
->rps
.min_freq_softlimit
/ GEN9_FREQ_SCALER
;
1843 dev_priv
->rps
.max_freq_softlimit
/ GEN9_FREQ_SCALER
;
1845 min_gpu_freq
= dev_priv
->rps
.min_freq_softlimit
;
1846 max_gpu_freq
= dev_priv
->rps
.max_freq_softlimit
;
1849 seq_puts(m
, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1851 for (gpu_freq
= min_gpu_freq
; gpu_freq
<= max_gpu_freq
; gpu_freq
++) {
1853 sandybridge_pcode_read(dev_priv
,
1854 GEN6_PCODE_READ_MIN_FREQ_TABLE
,
1856 seq_printf(m
, "%d\t\t%d\t\t\t\t%d\n",
1857 intel_gpu_freq(dev_priv
, (gpu_freq
*
1858 (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
) ?
1859 GEN9_FREQ_SCALER
: 1))),
1860 ((ia_freq
>> 0) & 0xff) * 100,
1861 ((ia_freq
>> 8) & 0xff) * 100);
1864 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1867 intel_runtime_pm_put(dev_priv
);
1871 static int i915_opregion(struct seq_file
*m
, void *unused
)
1873 struct drm_info_node
*node
= m
->private;
1874 struct drm_device
*dev
= node
->minor
->dev
;
1875 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1876 struct intel_opregion
*opregion
= &dev_priv
->opregion
;
1879 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1883 if (opregion
->header
)
1884 seq_write(m
, opregion
->header
, OPREGION_SIZE
);
1886 mutex_unlock(&dev
->struct_mutex
);
1892 static int i915_vbt(struct seq_file
*m
, void *unused
)
1894 struct drm_info_node
*node
= m
->private;
1895 struct drm_device
*dev
= node
->minor
->dev
;
1896 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1897 struct intel_opregion
*opregion
= &dev_priv
->opregion
;
1900 seq_write(m
, opregion
->vbt
, opregion
->vbt_size
);
1905 static int i915_gem_framebuffer_info(struct seq_file
*m
, void *data
)
1907 struct drm_info_node
*node
= m
->private;
1908 struct drm_device
*dev
= node
->minor
->dev
;
1909 struct intel_framebuffer
*fbdev_fb
= NULL
;
1910 struct drm_framebuffer
*drm_fb
;
1913 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1917 #ifdef CONFIG_DRM_FBDEV_EMULATION
1918 if (to_i915(dev
)->fbdev
) {
1919 fbdev_fb
= to_intel_framebuffer(to_i915(dev
)->fbdev
->helper
.fb
);
1921 seq_printf(m
, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1922 fbdev_fb
->base
.width
,
1923 fbdev_fb
->base
.height
,
1924 fbdev_fb
->base
.depth
,
1925 fbdev_fb
->base
.bits_per_pixel
,
1926 fbdev_fb
->base
.modifier
[0],
1927 atomic_read(&fbdev_fb
->base
.refcount
.refcount
));
1928 describe_obj(m
, fbdev_fb
->obj
);
1933 mutex_lock(&dev
->mode_config
.fb_lock
);
1934 drm_for_each_fb(drm_fb
, dev
) {
1935 struct intel_framebuffer
*fb
= to_intel_framebuffer(drm_fb
);
1939 seq_printf(m
, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1943 fb
->base
.bits_per_pixel
,
1944 fb
->base
.modifier
[0],
1945 atomic_read(&fb
->base
.refcount
.refcount
));
1946 describe_obj(m
, fb
->obj
);
1949 mutex_unlock(&dev
->mode_config
.fb_lock
);
1950 mutex_unlock(&dev
->struct_mutex
);
1955 static void describe_ctx_ringbuf(struct seq_file
*m
,
1956 struct intel_ringbuffer
*ringbuf
)
1958 seq_printf(m
, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1959 ringbuf
->space
, ringbuf
->head
, ringbuf
->tail
,
1960 ringbuf
->last_retired_head
);
1963 static int i915_context_status(struct seq_file
*m
, void *unused
)
1965 struct drm_info_node
*node
= m
->private;
1966 struct drm_device
*dev
= node
->minor
->dev
;
1967 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1968 struct intel_engine_cs
*engine
;
1969 struct intel_context
*ctx
;
1970 enum intel_engine_id id
;
1973 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1977 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
1978 if (!i915
.enable_execlists
&&
1979 ctx
->legacy_hw_ctx
.rcs_state
== NULL
)
1982 seq_puts(m
, "HW context ");
1983 describe_ctx(m
, ctx
);
1984 if (ctx
== dev_priv
->kernel_context
)
1985 seq_printf(m
, "(kernel context) ");
1987 if (i915
.enable_execlists
) {
1989 for_each_engine_id(engine
, dev_priv
, id
) {
1990 struct drm_i915_gem_object
*ctx_obj
=
1991 ctx
->engine
[id
].state
;
1992 struct intel_ringbuffer
*ringbuf
=
1993 ctx
->engine
[id
].ringbuf
;
1995 seq_printf(m
, "%s: ", engine
->name
);
1997 describe_obj(m
, ctx_obj
);
1999 describe_ctx_ringbuf(m
, ringbuf
);
2003 describe_obj(m
, ctx
->legacy_hw_ctx
.rcs_state
);
2009 mutex_unlock(&dev
->struct_mutex
);
2014 static void i915_dump_lrc_obj(struct seq_file
*m
,
2015 struct intel_context
*ctx
,
2016 struct intel_engine_cs
*engine
)
2019 uint32_t *reg_state
;
2021 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[engine
->id
].state
;
2022 unsigned long ggtt_offset
= 0;
2024 if (ctx_obj
== NULL
) {
2025 seq_printf(m
, "Context on %s with no gem object\n",
2030 seq_printf(m
, "CONTEXT: %s %u\n", engine
->name
,
2031 intel_execlists_ctx_id(ctx
, engine
));
2033 if (!i915_gem_obj_ggtt_bound(ctx_obj
))
2034 seq_puts(m
, "\tNot bound in GGTT\n");
2036 ggtt_offset
= i915_gem_obj_ggtt_offset(ctx_obj
);
2038 if (i915_gem_object_get_pages(ctx_obj
)) {
2039 seq_puts(m
, "\tFailed to get pages for context object\n");
2043 page
= i915_gem_object_get_page(ctx_obj
, LRC_STATE_PN
);
2044 if (!WARN_ON(page
== NULL
)) {
2045 reg_state
= kmap_atomic(page
);
2047 for (j
= 0; j
< 0x600 / sizeof(u32
) / 4; j
+= 4) {
2048 seq_printf(m
, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2049 ggtt_offset
+ 4096 + (j
* 4),
2050 reg_state
[j
], reg_state
[j
+ 1],
2051 reg_state
[j
+ 2], reg_state
[j
+ 3]);
2053 kunmap_atomic(reg_state
);
2059 static int i915_dump_lrc(struct seq_file
*m
, void *unused
)
2061 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2062 struct drm_device
*dev
= node
->minor
->dev
;
2063 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2064 struct intel_engine_cs
*engine
;
2065 struct intel_context
*ctx
;
2068 if (!i915
.enable_execlists
) {
2069 seq_printf(m
, "Logical Ring Contexts are disabled\n");
2073 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2077 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
)
2078 if (ctx
!= dev_priv
->kernel_context
)
2079 for_each_engine(engine
, dev_priv
)
2080 i915_dump_lrc_obj(m
, ctx
, engine
);
2082 mutex_unlock(&dev
->struct_mutex
);
2087 static int i915_execlists(struct seq_file
*m
, void *data
)
2089 struct drm_info_node
*node
= (struct drm_info_node
*)m
->private;
2090 struct drm_device
*dev
= node
->minor
->dev
;
2091 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2092 struct intel_engine_cs
*engine
;
2098 struct list_head
*cursor
;
2101 if (!i915
.enable_execlists
) {
2102 seq_puts(m
, "Logical Ring Contexts are disabled\n");
2106 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2110 intel_runtime_pm_get(dev_priv
);
2112 for_each_engine(engine
, dev_priv
) {
2113 struct drm_i915_gem_request
*head_req
= NULL
;
2116 seq_printf(m
, "%s\n", engine
->name
);
2118 status
= I915_READ(RING_EXECLIST_STATUS_LO(engine
));
2119 ctx_id
= I915_READ(RING_EXECLIST_STATUS_HI(engine
));
2120 seq_printf(m
, "\tExeclist status: 0x%08X, context: %u\n",
2123 status_pointer
= I915_READ(RING_CONTEXT_STATUS_PTR(engine
));
2124 seq_printf(m
, "\tStatus pointer: 0x%08X\n", status_pointer
);
2126 read_pointer
= engine
->next_context_status_buffer
;
2127 write_pointer
= GEN8_CSB_WRITE_PTR(status_pointer
);
2128 if (read_pointer
> write_pointer
)
2129 write_pointer
+= GEN8_CSB_ENTRIES
;
2130 seq_printf(m
, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2131 read_pointer
, write_pointer
);
2133 for (i
= 0; i
< GEN8_CSB_ENTRIES
; i
++) {
2134 status
= I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine
, i
));
2135 ctx_id
= I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine
, i
));
2137 seq_printf(m
, "\tStatus buffer %d: 0x%08X, context: %u\n",
2141 spin_lock_bh(&engine
->execlist_lock
);
2142 list_for_each(cursor
, &engine
->execlist_queue
)
2144 head_req
= list_first_entry_or_null(&engine
->execlist_queue
,
2145 struct drm_i915_gem_request
,
2147 spin_unlock_bh(&engine
->execlist_lock
);
2149 seq_printf(m
, "\t%d requests in queue\n", count
);
2151 seq_printf(m
, "\tHead request id: %u\n",
2152 intel_execlists_ctx_id(head_req
->ctx
, engine
));
2153 seq_printf(m
, "\tHead request tail: %u\n",
2160 intel_runtime_pm_put(dev_priv
);
2161 mutex_unlock(&dev
->struct_mutex
);
2166 static const char *swizzle_string(unsigned swizzle
)
2169 case I915_BIT_6_SWIZZLE_NONE
:
2171 case I915_BIT_6_SWIZZLE_9
:
2173 case I915_BIT_6_SWIZZLE_9_10
:
2174 return "bit9/bit10";
2175 case I915_BIT_6_SWIZZLE_9_11
:
2176 return "bit9/bit11";
2177 case I915_BIT_6_SWIZZLE_9_10_11
:
2178 return "bit9/bit10/bit11";
2179 case I915_BIT_6_SWIZZLE_9_17
:
2180 return "bit9/bit17";
2181 case I915_BIT_6_SWIZZLE_9_10_17
:
2182 return "bit9/bit10/bit17";
2183 case I915_BIT_6_SWIZZLE_UNKNOWN
:
2190 static int i915_swizzle_info(struct seq_file
*m
, void *data
)
2192 struct drm_info_node
*node
= m
->private;
2193 struct drm_device
*dev
= node
->minor
->dev
;
2194 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2197 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2200 intel_runtime_pm_get(dev_priv
);
2202 seq_printf(m
, "bit6 swizzle for X-tiling = %s\n",
2203 swizzle_string(dev_priv
->mm
.bit_6_swizzle_x
));
2204 seq_printf(m
, "bit6 swizzle for Y-tiling = %s\n",
2205 swizzle_string(dev_priv
->mm
.bit_6_swizzle_y
));
2207 if (IS_GEN3(dev
) || IS_GEN4(dev
)) {
2208 seq_printf(m
, "DDC = 0x%08x\n",
2210 seq_printf(m
, "DDC2 = 0x%08x\n",
2212 seq_printf(m
, "C0DRB3 = 0x%04x\n",
2213 I915_READ16(C0DRB3
));
2214 seq_printf(m
, "C1DRB3 = 0x%04x\n",
2215 I915_READ16(C1DRB3
));
2216 } else if (INTEL_INFO(dev
)->gen
>= 6) {
2217 seq_printf(m
, "MAD_DIMM_C0 = 0x%08x\n",
2218 I915_READ(MAD_DIMM_C0
));
2219 seq_printf(m
, "MAD_DIMM_C1 = 0x%08x\n",
2220 I915_READ(MAD_DIMM_C1
));
2221 seq_printf(m
, "MAD_DIMM_C2 = 0x%08x\n",
2222 I915_READ(MAD_DIMM_C2
));
2223 seq_printf(m
, "TILECTL = 0x%08x\n",
2224 I915_READ(TILECTL
));
2225 if (INTEL_INFO(dev
)->gen
>= 8)
2226 seq_printf(m
, "GAMTARBMODE = 0x%08x\n",
2227 I915_READ(GAMTARBMODE
));
2229 seq_printf(m
, "ARB_MODE = 0x%08x\n",
2230 I915_READ(ARB_MODE
));
2231 seq_printf(m
, "DISP_ARB_CTL = 0x%08x\n",
2232 I915_READ(DISP_ARB_CTL
));
2235 if (dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
)
2236 seq_puts(m
, "L-shaped memory detected\n");
2238 intel_runtime_pm_put(dev_priv
);
2239 mutex_unlock(&dev
->struct_mutex
);
2244 static int per_file_ctx(int id
, void *ptr
, void *data
)
2246 struct intel_context
*ctx
= ptr
;
2247 struct seq_file
*m
= data
;
2248 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
2251 seq_printf(m
, " no ppgtt for context %d\n",
2256 if (i915_gem_context_is_default(ctx
))
2257 seq_puts(m
, " default context:\n");
2259 seq_printf(m
, " context %d:\n", ctx
->user_handle
);
2260 ppgtt
->debug_dump(ppgtt
, m
);
2265 static void gen8_ppgtt_info(struct seq_file
*m
, struct drm_device
*dev
)
2267 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2268 struct intel_engine_cs
*engine
;
2269 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2275 for_each_engine(engine
, dev_priv
) {
2276 seq_printf(m
, "%s\n", engine
->name
);
2277 for (i
= 0; i
< 4; i
++) {
2278 u64 pdp
= I915_READ(GEN8_RING_PDP_UDW(engine
, i
));
2280 pdp
|= I915_READ(GEN8_RING_PDP_LDW(engine
, i
));
2281 seq_printf(m
, "\tPDP%d 0x%016llx\n", i
, pdp
);
2286 static void gen6_ppgtt_info(struct seq_file
*m
, struct drm_device
*dev
)
2288 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2289 struct intel_engine_cs
*engine
;
2291 if (INTEL_INFO(dev
)->gen
== 6)
2292 seq_printf(m
, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE
));
2294 for_each_engine(engine
, dev_priv
) {
2295 seq_printf(m
, "%s\n", engine
->name
);
2296 if (INTEL_INFO(dev
)->gen
== 7)
2297 seq_printf(m
, "GFX_MODE: 0x%08x\n",
2298 I915_READ(RING_MODE_GEN7(engine
)));
2299 seq_printf(m
, "PP_DIR_BASE: 0x%08x\n",
2300 I915_READ(RING_PP_DIR_BASE(engine
)));
2301 seq_printf(m
, "PP_DIR_BASE_READ: 0x%08x\n",
2302 I915_READ(RING_PP_DIR_BASE_READ(engine
)));
2303 seq_printf(m
, "PP_DIR_DCLV: 0x%08x\n",
2304 I915_READ(RING_PP_DIR_DCLV(engine
)));
2306 if (dev_priv
->mm
.aliasing_ppgtt
) {
2307 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2309 seq_puts(m
, "aliasing PPGTT:\n");
2310 seq_printf(m
, "pd gtt offset: 0x%08x\n", ppgtt
->pd
.base
.ggtt_offset
);
2312 ppgtt
->debug_dump(ppgtt
, m
);
2315 seq_printf(m
, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK
));
2318 static int i915_ppgtt_info(struct seq_file
*m
, void *data
)
2320 struct drm_info_node
*node
= m
->private;
2321 struct drm_device
*dev
= node
->minor
->dev
;
2322 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2323 struct drm_file
*file
;
2325 int ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2328 intel_runtime_pm_get(dev_priv
);
2330 if (INTEL_INFO(dev
)->gen
>= 8)
2331 gen8_ppgtt_info(m
, dev
);
2332 else if (INTEL_INFO(dev
)->gen
>= 6)
2333 gen6_ppgtt_info(m
, dev
);
2335 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
2336 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2337 struct task_struct
*task
;
2339 task
= get_pid_task(file
->pid
, PIDTYPE_PID
);
2344 seq_printf(m
, "\nproc: %s\n", task
->comm
);
2345 put_task_struct(task
);
2346 idr_for_each(&file_priv
->context_idr
, per_file_ctx
,
2347 (void *)(unsigned long)m
);
2351 intel_runtime_pm_put(dev_priv
);
2352 mutex_unlock(&dev
->struct_mutex
);
2357 static int count_irq_waiters(struct drm_i915_private
*i915
)
2359 struct intel_engine_cs
*engine
;
2362 for_each_engine(engine
, i915
)
2363 count
+= engine
->irq_refcount
;
2368 static int i915_rps_boost_info(struct seq_file
*m
, void *data
)
2370 struct drm_info_node
*node
= m
->private;
2371 struct drm_device
*dev
= node
->minor
->dev
;
2372 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2373 struct drm_file
*file
;
2375 seq_printf(m
, "RPS enabled? %d\n", dev_priv
->rps
.enabled
);
2376 seq_printf(m
, "GPU busy? %d\n", dev_priv
->mm
.busy
);
2377 seq_printf(m
, "CPU waiting? %d\n", count_irq_waiters(dev_priv
));
2378 seq_printf(m
, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2379 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
),
2380 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
2381 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq_softlimit
),
2382 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq_softlimit
),
2383 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
2384 spin_lock(&dev_priv
->rps
.client_lock
);
2385 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
2386 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2387 struct task_struct
*task
;
2390 task
= pid_task(file
->pid
, PIDTYPE_PID
);
2391 seq_printf(m
, "%s [%d]: %d boosts%s\n",
2392 task
? task
->comm
: "<unknown>",
2393 task
? task
->pid
: -1,
2394 file_priv
->rps
.boosts
,
2395 list_empty(&file_priv
->rps
.link
) ? "" : ", active");
2398 seq_printf(m
, "Semaphore boosts: %d%s\n",
2399 dev_priv
->rps
.semaphores
.boosts
,
2400 list_empty(&dev_priv
->rps
.semaphores
.link
) ? "" : ", active");
2401 seq_printf(m
, "MMIO flip boosts: %d%s\n",
2402 dev_priv
->rps
.mmioflips
.boosts
,
2403 list_empty(&dev_priv
->rps
.mmioflips
.link
) ? "" : ", active");
2404 seq_printf(m
, "Kernel boosts: %d\n", dev_priv
->rps
.boosts
);
2405 spin_unlock(&dev_priv
->rps
.client_lock
);
2410 static int i915_llc(struct seq_file
*m
, void *data
)
2412 struct drm_info_node
*node
= m
->private;
2413 struct drm_device
*dev
= node
->minor
->dev
;
2414 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2415 const bool edram
= INTEL_GEN(dev_priv
) > 8;
2417 seq_printf(m
, "LLC: %s\n", yesno(HAS_LLC(dev
)));
2418 seq_printf(m
, "%s: %lluMB\n", edram
? "eDRAM" : "eLLC",
2419 intel_uncore_edram_size(dev_priv
)/1024/1024);
2424 static int i915_guc_load_status_info(struct seq_file
*m
, void *data
)
2426 struct drm_info_node
*node
= m
->private;
2427 struct drm_i915_private
*dev_priv
= node
->minor
->dev
->dev_private
;
2428 struct intel_guc_fw
*guc_fw
= &dev_priv
->guc
.guc_fw
;
2431 if (!HAS_GUC_UCODE(dev_priv
))
2434 seq_printf(m
, "GuC firmware status:\n");
2435 seq_printf(m
, "\tpath: %s\n",
2436 guc_fw
->guc_fw_path
);
2437 seq_printf(m
, "\tfetch: %s\n",
2438 intel_guc_fw_status_repr(guc_fw
->guc_fw_fetch_status
));
2439 seq_printf(m
, "\tload: %s\n",
2440 intel_guc_fw_status_repr(guc_fw
->guc_fw_load_status
));
2441 seq_printf(m
, "\tversion wanted: %d.%d\n",
2442 guc_fw
->guc_fw_major_wanted
, guc_fw
->guc_fw_minor_wanted
);
2443 seq_printf(m
, "\tversion found: %d.%d\n",
2444 guc_fw
->guc_fw_major_found
, guc_fw
->guc_fw_minor_found
);
2445 seq_printf(m
, "\theader: offset is %d; size = %d\n",
2446 guc_fw
->header_offset
, guc_fw
->header_size
);
2447 seq_printf(m
, "\tuCode: offset is %d; size = %d\n",
2448 guc_fw
->ucode_offset
, guc_fw
->ucode_size
);
2449 seq_printf(m
, "\tRSA: offset is %d; size = %d\n",
2450 guc_fw
->rsa_offset
, guc_fw
->rsa_size
);
2452 tmp
= I915_READ(GUC_STATUS
);
2454 seq_printf(m
, "\nGuC status 0x%08x:\n", tmp
);
2455 seq_printf(m
, "\tBootrom status = 0x%x\n",
2456 (tmp
& GS_BOOTROM_MASK
) >> GS_BOOTROM_SHIFT
);
2457 seq_printf(m
, "\tuKernel status = 0x%x\n",
2458 (tmp
& GS_UKERNEL_MASK
) >> GS_UKERNEL_SHIFT
);
2459 seq_printf(m
, "\tMIA Core status = 0x%x\n",
2460 (tmp
& GS_MIA_MASK
) >> GS_MIA_SHIFT
);
2461 seq_puts(m
, "\nScratch registers:\n");
2462 for (i
= 0; i
< 16; i
++)
2463 seq_printf(m
, "\t%2d: \t0x%x\n", i
, I915_READ(SOFT_SCRATCH(i
)));
2468 static void i915_guc_client_info(struct seq_file
*m
,
2469 struct drm_i915_private
*dev_priv
,
2470 struct i915_guc_client
*client
)
2472 struct intel_engine_cs
*engine
;
2475 seq_printf(m
, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2476 client
->priority
, client
->ctx_index
, client
->proc_desc_offset
);
2477 seq_printf(m
, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2478 client
->doorbell_id
, client
->doorbell_offset
, client
->cookie
);
2479 seq_printf(m
, "\tWQ size %d, offset: 0x%x, tail %d\n",
2480 client
->wq_size
, client
->wq_offset
, client
->wq_tail
);
2482 seq_printf(m
, "\tFailed to queue: %u\n", client
->q_fail
);
2483 seq_printf(m
, "\tFailed doorbell: %u\n", client
->b_fail
);
2484 seq_printf(m
, "\tLast submission result: %d\n", client
->retcode
);
2486 for_each_engine(engine
, dev_priv
) {
2487 seq_printf(m
, "\tSubmissions: %llu %s\n",
2488 client
->submissions
[engine
->guc_id
],
2490 tot
+= client
->submissions
[engine
->guc_id
];
2492 seq_printf(m
, "\tTotal: %llu\n", tot
);
2495 static int i915_guc_info(struct seq_file
*m
, void *data
)
2497 struct drm_info_node
*node
= m
->private;
2498 struct drm_device
*dev
= node
->minor
->dev
;
2499 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2500 struct intel_guc guc
;
2501 struct i915_guc_client client
= {};
2502 struct intel_engine_cs
*engine
;
2505 if (!HAS_GUC_SCHED(dev_priv
))
2508 if (mutex_lock_interruptible(&dev
->struct_mutex
))
2511 /* Take a local copy of the GuC data, so we can dump it at leisure */
2512 guc
= dev_priv
->guc
;
2513 if (guc
.execbuf_client
)
2514 client
= *guc
.execbuf_client
;
2516 mutex_unlock(&dev
->struct_mutex
);
2518 seq_printf(m
, "GuC total action count: %llu\n", guc
.action_count
);
2519 seq_printf(m
, "GuC action failure count: %u\n", guc
.action_fail
);
2520 seq_printf(m
, "GuC last action command: 0x%x\n", guc
.action_cmd
);
2521 seq_printf(m
, "GuC last action status: 0x%x\n", guc
.action_status
);
2522 seq_printf(m
, "GuC last action error code: %d\n", guc
.action_err
);
2524 seq_printf(m
, "\nGuC submissions:\n");
2525 for_each_engine(engine
, dev_priv
) {
2526 seq_printf(m
, "\t%-24s: %10llu, last seqno 0x%08x\n",
2527 engine
->name
, guc
.submissions
[engine
->guc_id
],
2528 guc
.last_seqno
[engine
->guc_id
]);
2529 total
+= guc
.submissions
[engine
->guc_id
];
2531 seq_printf(m
, "\t%s: %llu\n", "Total", total
);
2533 seq_printf(m
, "\nGuC execbuf client @ %p:\n", guc
.execbuf_client
);
2534 i915_guc_client_info(m
, dev_priv
, &client
);
2536 /* Add more as required ... */
2541 static int i915_guc_log_dump(struct seq_file
*m
, void *data
)
2543 struct drm_info_node
*node
= m
->private;
2544 struct drm_device
*dev
= node
->minor
->dev
;
2545 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2546 struct drm_i915_gem_object
*log_obj
= dev_priv
->guc
.log_obj
;
2553 for (pg
= 0; pg
< log_obj
->base
.size
/ PAGE_SIZE
; pg
++) {
2554 log
= kmap_atomic(i915_gem_object_get_page(log_obj
, pg
));
2556 for (i
= 0; i
< PAGE_SIZE
/ sizeof(u32
); i
+= 4)
2557 seq_printf(m
, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2558 *(log
+ i
), *(log
+ i
+ 1),
2559 *(log
+ i
+ 2), *(log
+ i
+ 3));
2569 static int i915_edp_psr_status(struct seq_file
*m
, void *data
)
2571 struct drm_info_node
*node
= m
->private;
2572 struct drm_device
*dev
= node
->minor
->dev
;
2573 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2577 bool enabled
= false;
2579 if (!HAS_PSR(dev
)) {
2580 seq_puts(m
, "PSR not supported\n");
2584 intel_runtime_pm_get(dev_priv
);
2586 mutex_lock(&dev_priv
->psr
.lock
);
2587 seq_printf(m
, "Sink_Support: %s\n", yesno(dev_priv
->psr
.sink_support
));
2588 seq_printf(m
, "Source_OK: %s\n", yesno(dev_priv
->psr
.source_ok
));
2589 seq_printf(m
, "Enabled: %s\n", yesno((bool)dev_priv
->psr
.enabled
));
2590 seq_printf(m
, "Active: %s\n", yesno(dev_priv
->psr
.active
));
2591 seq_printf(m
, "Busy frontbuffer bits: 0x%03x\n",
2592 dev_priv
->psr
.busy_frontbuffer_bits
);
2593 seq_printf(m
, "Re-enable work scheduled: %s\n",
2594 yesno(work_busy(&dev_priv
->psr
.work
.work
)));
2597 enabled
= I915_READ(EDP_PSR_CTL
) & EDP_PSR_ENABLE
;
2599 for_each_pipe(dev_priv
, pipe
) {
2600 stat
[pipe
] = I915_READ(VLV_PSRSTAT(pipe
)) &
2601 VLV_EDP_PSR_CURR_STATE_MASK
;
2602 if ((stat
[pipe
] == VLV_EDP_PSR_ACTIVE_NORFB_UP
) ||
2603 (stat
[pipe
] == VLV_EDP_PSR_ACTIVE_SF_UPDATE
))
2608 seq_printf(m
, "Main link in standby mode: %s\n",
2609 yesno(dev_priv
->psr
.link_standby
));
2611 seq_printf(m
, "HW Enabled & Active bit: %s", yesno(enabled
));
2614 for_each_pipe(dev_priv
, pipe
) {
2615 if ((stat
[pipe
] == VLV_EDP_PSR_ACTIVE_NORFB_UP
) ||
2616 (stat
[pipe
] == VLV_EDP_PSR_ACTIVE_SF_UPDATE
))
2617 seq_printf(m
, " pipe %c", pipe_name(pipe
));
2622 * VLV/CHV PSR has no kind of performance counter
2623 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2625 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2626 psrperf
= I915_READ(EDP_PSR_PERF_CNT
) &
2627 EDP_PSR_PERF_CNT_MASK
;
2629 seq_printf(m
, "Performance_Counter: %u\n", psrperf
);
2631 mutex_unlock(&dev_priv
->psr
.lock
);
2633 intel_runtime_pm_put(dev_priv
);
2637 static int i915_sink_crc(struct seq_file
*m
, void *data
)
2639 struct drm_info_node
*node
= m
->private;
2640 struct drm_device
*dev
= node
->minor
->dev
;
2641 struct intel_encoder
*encoder
;
2642 struct intel_connector
*connector
;
2643 struct intel_dp
*intel_dp
= NULL
;
2647 drm_modeset_lock_all(dev
);
2648 for_each_intel_connector(dev
, connector
) {
2650 if (connector
->base
.dpms
!= DRM_MODE_DPMS_ON
)
2653 if (!connector
->base
.encoder
)
2656 encoder
= to_intel_encoder(connector
->base
.encoder
);
2657 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2660 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2662 ret
= intel_dp_sink_crc(intel_dp
, crc
);
2666 seq_printf(m
, "%02x%02x%02x%02x%02x%02x\n",
2667 crc
[0], crc
[1], crc
[2],
2668 crc
[3], crc
[4], crc
[5]);
2673 drm_modeset_unlock_all(dev
);
2677 static int i915_energy_uJ(struct seq_file
*m
, void *data
)
2679 struct drm_info_node
*node
= m
->private;
2680 struct drm_device
*dev
= node
->minor
->dev
;
2681 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2685 if (INTEL_INFO(dev
)->gen
< 6)
2688 intel_runtime_pm_get(dev_priv
);
2690 rdmsrl(MSR_RAPL_POWER_UNIT
, power
);
2691 power
= (power
& 0x1f00) >> 8;
2692 units
= 1000000 / (1 << power
); /* convert to uJ */
2693 power
= I915_READ(MCH_SECP_NRG_STTS
);
2696 intel_runtime_pm_put(dev_priv
);
2698 seq_printf(m
, "%llu", (long long unsigned)power
);
2703 static int i915_runtime_pm_status(struct seq_file
*m
, void *unused
)
2705 struct drm_info_node
*node
= m
->private;
2706 struct drm_device
*dev
= node
->minor
->dev
;
2707 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2709 if (!HAS_RUNTIME_PM(dev_priv
))
2710 seq_puts(m
, "Runtime power management not supported\n");
2712 seq_printf(m
, "GPU idle: %s\n", yesno(!dev_priv
->mm
.busy
));
2713 seq_printf(m
, "IRQs disabled: %s\n",
2714 yesno(!intel_irqs_enabled(dev_priv
)));
2716 seq_printf(m
, "Usage count: %d\n",
2717 atomic_read(&dev
->dev
->power
.usage_count
));
2719 seq_printf(m
, "Device Power Management (CONFIG_PM) disabled\n");
2721 seq_printf(m
, "PCI device power state: %s [%d]\n",
2722 pci_power_name(dev_priv
->dev
->pdev
->current_state
),
2723 dev_priv
->dev
->pdev
->current_state
);
2728 static int i915_power_domain_info(struct seq_file
*m
, void *unused
)
2730 struct drm_info_node
*node
= m
->private;
2731 struct drm_device
*dev
= node
->minor
->dev
;
2732 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2733 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
2736 mutex_lock(&power_domains
->lock
);
2738 seq_printf(m
, "%-25s %s\n", "Power well/domain", "Use count");
2739 for (i
= 0; i
< power_domains
->power_well_count
; i
++) {
2740 struct i915_power_well
*power_well
;
2741 enum intel_display_power_domain power_domain
;
2743 power_well
= &power_domains
->power_wells
[i
];
2744 seq_printf(m
, "%-25s %d\n", power_well
->name
,
2747 for (power_domain
= 0; power_domain
< POWER_DOMAIN_NUM
;
2749 if (!(BIT(power_domain
) & power_well
->domains
))
2752 seq_printf(m
, " %-23s %d\n",
2753 intel_display_power_domain_str(power_domain
),
2754 power_domains
->domain_use_count
[power_domain
]);
2758 mutex_unlock(&power_domains
->lock
);
2763 static int i915_dmc_info(struct seq_file
*m
, void *unused
)
2765 struct drm_info_node
*node
= m
->private;
2766 struct drm_device
*dev
= node
->minor
->dev
;
2767 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2768 struct intel_csr
*csr
;
2770 if (!HAS_CSR(dev
)) {
2771 seq_puts(m
, "not supported\n");
2775 csr
= &dev_priv
->csr
;
2777 intel_runtime_pm_get(dev_priv
);
2779 seq_printf(m
, "fw loaded: %s\n", yesno(csr
->dmc_payload
!= NULL
));
2780 seq_printf(m
, "path: %s\n", csr
->fw_path
);
2782 if (!csr
->dmc_payload
)
2785 seq_printf(m
, "version: %d.%d\n", CSR_VERSION_MAJOR(csr
->version
),
2786 CSR_VERSION_MINOR(csr
->version
));
2788 if (IS_SKYLAKE(dev
) && csr
->version
>= CSR_VERSION(1, 6)) {
2789 seq_printf(m
, "DC3 -> DC5 count: %d\n",
2790 I915_READ(SKL_CSR_DC3_DC5_COUNT
));
2791 seq_printf(m
, "DC5 -> DC6 count: %d\n",
2792 I915_READ(SKL_CSR_DC5_DC6_COUNT
));
2793 } else if (IS_BROXTON(dev
) && csr
->version
>= CSR_VERSION(1, 4)) {
2794 seq_printf(m
, "DC3 -> DC5 count: %d\n",
2795 I915_READ(BXT_CSR_DC3_DC5_COUNT
));
2799 seq_printf(m
, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2800 seq_printf(m
, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE
));
2801 seq_printf(m
, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL
));
2803 intel_runtime_pm_put(dev_priv
);
2808 static void intel_seq_print_mode(struct seq_file
*m
, int tabs
,
2809 struct drm_display_mode
*mode
)
2813 for (i
= 0; i
< tabs
; i
++)
2816 seq_printf(m
, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2817 mode
->base
.id
, mode
->name
,
2818 mode
->vrefresh
, mode
->clock
,
2819 mode
->hdisplay
, mode
->hsync_start
,
2820 mode
->hsync_end
, mode
->htotal
,
2821 mode
->vdisplay
, mode
->vsync_start
,
2822 mode
->vsync_end
, mode
->vtotal
,
2823 mode
->type
, mode
->flags
);
2826 static void intel_encoder_info(struct seq_file
*m
,
2827 struct intel_crtc
*intel_crtc
,
2828 struct intel_encoder
*intel_encoder
)
2830 struct drm_info_node
*node
= m
->private;
2831 struct drm_device
*dev
= node
->minor
->dev
;
2832 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2833 struct intel_connector
*intel_connector
;
2834 struct drm_encoder
*encoder
;
2836 encoder
= &intel_encoder
->base
;
2837 seq_printf(m
, "\tencoder %d: type: %s, connectors:\n",
2838 encoder
->base
.id
, encoder
->name
);
2839 for_each_connector_on_encoder(dev
, encoder
, intel_connector
) {
2840 struct drm_connector
*connector
= &intel_connector
->base
;
2841 seq_printf(m
, "\t\tconnector %d: type: %s, status: %s",
2844 drm_get_connector_status_name(connector
->status
));
2845 if (connector
->status
== connector_status_connected
) {
2846 struct drm_display_mode
*mode
= &crtc
->mode
;
2847 seq_printf(m
, ", mode:\n");
2848 intel_seq_print_mode(m
, 2, mode
);
2855 static void intel_crtc_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
2857 struct drm_info_node
*node
= m
->private;
2858 struct drm_device
*dev
= node
->minor
->dev
;
2859 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2860 struct intel_encoder
*intel_encoder
;
2861 struct drm_plane_state
*plane_state
= crtc
->primary
->state
;
2862 struct drm_framebuffer
*fb
= plane_state
->fb
;
2865 seq_printf(m
, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2866 fb
->base
.id
, plane_state
->src_x
>> 16,
2867 plane_state
->src_y
>> 16, fb
->width
, fb
->height
);
2869 seq_puts(m
, "\tprimary plane disabled\n");
2870 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
2871 intel_encoder_info(m
, intel_crtc
, intel_encoder
);
2874 static void intel_panel_info(struct seq_file
*m
, struct intel_panel
*panel
)
2876 struct drm_display_mode
*mode
= panel
->fixed_mode
;
2878 seq_printf(m
, "\tfixed mode:\n");
2879 intel_seq_print_mode(m
, 2, mode
);
2882 static void intel_dp_info(struct seq_file
*m
,
2883 struct intel_connector
*intel_connector
)
2885 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2886 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
2888 seq_printf(m
, "\tDPCD rev: %x\n", intel_dp
->dpcd
[DP_DPCD_REV
]);
2889 seq_printf(m
, "\taudio support: %s\n", yesno(intel_dp
->has_audio
));
2890 if (intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2891 intel_panel_info(m
, &intel_connector
->panel
);
2894 static void intel_dp_mst_info(struct seq_file
*m
,
2895 struct intel_connector
*intel_connector
)
2897 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2898 struct intel_dp_mst_encoder
*intel_mst
=
2899 enc_to_mst(&intel_encoder
->base
);
2900 struct intel_digital_port
*intel_dig_port
= intel_mst
->primary
;
2901 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
2902 bool has_audio
= drm_dp_mst_port_has_audio(&intel_dp
->mst_mgr
,
2903 intel_connector
->port
);
2905 seq_printf(m
, "\taudio support: %s\n", yesno(has_audio
));
2908 static void intel_hdmi_info(struct seq_file
*m
,
2909 struct intel_connector
*intel_connector
)
2911 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2912 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&intel_encoder
->base
);
2914 seq_printf(m
, "\taudio support: %s\n", yesno(intel_hdmi
->has_audio
));
2917 static void intel_lvds_info(struct seq_file
*m
,
2918 struct intel_connector
*intel_connector
)
2920 intel_panel_info(m
, &intel_connector
->panel
);
2923 static void intel_connector_info(struct seq_file
*m
,
2924 struct drm_connector
*connector
)
2926 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2927 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2928 struct drm_display_mode
*mode
;
2930 seq_printf(m
, "connector %d: type %s, status: %s\n",
2931 connector
->base
.id
, connector
->name
,
2932 drm_get_connector_status_name(connector
->status
));
2933 if (connector
->status
== connector_status_connected
) {
2934 seq_printf(m
, "\tname: %s\n", connector
->display_info
.name
);
2935 seq_printf(m
, "\tphysical dimensions: %dx%dmm\n",
2936 connector
->display_info
.width_mm
,
2937 connector
->display_info
.height_mm
);
2938 seq_printf(m
, "\tsubpixel order: %s\n",
2939 drm_get_subpixel_order_name(connector
->display_info
.subpixel_order
));
2940 seq_printf(m
, "\tCEA rev: %d\n",
2941 connector
->display_info
.cea_rev
);
2943 if (intel_encoder
) {
2944 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
2945 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2946 intel_dp_info(m
, intel_connector
);
2947 else if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
)
2948 intel_hdmi_info(m
, intel_connector
);
2949 else if (intel_encoder
->type
== INTEL_OUTPUT_LVDS
)
2950 intel_lvds_info(m
, intel_connector
);
2951 else if (intel_encoder
->type
== INTEL_OUTPUT_DP_MST
)
2952 intel_dp_mst_info(m
, intel_connector
);
2955 seq_printf(m
, "\tmodes:\n");
2956 list_for_each_entry(mode
, &connector
->modes
, head
)
2957 intel_seq_print_mode(m
, 2, mode
);
2960 static bool cursor_active(struct drm_device
*dev
, int pipe
)
2962 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2965 if (IS_845G(dev
) || IS_I865G(dev
))
2966 state
= I915_READ(CURCNTR(PIPE_A
)) & CURSOR_ENABLE
;
2968 state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
2973 static bool cursor_position(struct drm_device
*dev
, int pipe
, int *x
, int *y
)
2975 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2978 pos
= I915_READ(CURPOS(pipe
));
2980 *x
= (pos
>> CURSOR_X_SHIFT
) & CURSOR_POS_MASK
;
2981 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
))
2984 *y
= (pos
>> CURSOR_Y_SHIFT
) & CURSOR_POS_MASK
;
2985 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
))
2988 return cursor_active(dev
, pipe
);
2991 static const char *plane_type(enum drm_plane_type type
)
2994 case DRM_PLANE_TYPE_OVERLAY
:
2996 case DRM_PLANE_TYPE_PRIMARY
:
2998 case DRM_PLANE_TYPE_CURSOR
:
3001 * Deliberately omitting default: to generate compiler warnings
3002 * when a new drm_plane_type gets added.
3009 static const char *plane_rotation(unsigned int rotation
)
3011 static char buf
[48];
3013 * According to doc only one DRM_ROTATE_ is allowed but this
3014 * will print them all to visualize if the values are misused
3016 snprintf(buf
, sizeof(buf
),
3017 "%s%s%s%s%s%s(0x%08x)",
3018 (rotation
& BIT(DRM_ROTATE_0
)) ? "0 " : "",
3019 (rotation
& BIT(DRM_ROTATE_90
)) ? "90 " : "",
3020 (rotation
& BIT(DRM_ROTATE_180
)) ? "180 " : "",
3021 (rotation
& BIT(DRM_ROTATE_270
)) ? "270 " : "",
3022 (rotation
& BIT(DRM_REFLECT_X
)) ? "FLIPX " : "",
3023 (rotation
& BIT(DRM_REFLECT_Y
)) ? "FLIPY " : "",
3029 static void intel_plane_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
3031 struct drm_info_node
*node
= m
->private;
3032 struct drm_device
*dev
= node
->minor
->dev
;
3033 struct intel_plane
*intel_plane
;
3035 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
3036 struct drm_plane_state
*state
;
3037 struct drm_plane
*plane
= &intel_plane
->base
;
3039 if (!plane
->state
) {
3040 seq_puts(m
, "plane->state is NULL!\n");
3044 state
= plane
->state
;
3046 seq_printf(m
, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3048 plane_type(intel_plane
->base
.type
),
3049 state
->crtc_x
, state
->crtc_y
,
3050 state
->crtc_w
, state
->crtc_h
,
3051 (state
->src_x
>> 16),
3052 ((state
->src_x
& 0xffff) * 15625) >> 10,
3053 (state
->src_y
>> 16),
3054 ((state
->src_y
& 0xffff) * 15625) >> 10,
3055 (state
->src_w
>> 16),
3056 ((state
->src_w
& 0xffff) * 15625) >> 10,
3057 (state
->src_h
>> 16),
3058 ((state
->src_h
& 0xffff) * 15625) >> 10,
3059 state
->fb
? drm_get_format_name(state
->fb
->pixel_format
) : "N/A",
3060 plane_rotation(state
->rotation
));
3064 static void intel_scaler_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
3066 struct intel_crtc_state
*pipe_config
;
3067 int num_scalers
= intel_crtc
->num_scalers
;
3070 pipe_config
= to_intel_crtc_state(intel_crtc
->base
.state
);
3072 /* Not all platformas have a scaler */
3074 seq_printf(m
, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3076 pipe_config
->scaler_state
.scaler_users
,
3077 pipe_config
->scaler_state
.scaler_id
);
3079 for (i
= 0; i
< SKL_NUM_SCALERS
; i
++) {
3080 struct intel_scaler
*sc
=
3081 &pipe_config
->scaler_state
.scalers
[i
];
3083 seq_printf(m
, ", scalers[%d]: use=%s, mode=%x",
3084 i
, yesno(sc
->in_use
), sc
->mode
);
3088 seq_puts(m
, "\tNo scalers available on this platform\n");
3092 static int i915_display_info(struct seq_file
*m
, void *unused
)
3094 struct drm_info_node
*node
= m
->private;
3095 struct drm_device
*dev
= node
->minor
->dev
;
3096 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3097 struct intel_crtc
*crtc
;
3098 struct drm_connector
*connector
;
3100 intel_runtime_pm_get(dev_priv
);
3101 drm_modeset_lock_all(dev
);
3102 seq_printf(m
, "CRTC info\n");
3103 seq_printf(m
, "---------\n");
3104 for_each_intel_crtc(dev
, crtc
) {
3106 struct intel_crtc_state
*pipe_config
;
3109 pipe_config
= to_intel_crtc_state(crtc
->base
.state
);
3111 seq_printf(m
, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3112 crtc
->base
.base
.id
, pipe_name(crtc
->pipe
),
3113 yesno(pipe_config
->base
.active
),
3114 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
,
3115 yesno(pipe_config
->dither
), pipe_config
->pipe_bpp
);
3117 if (pipe_config
->base
.active
) {
3118 intel_crtc_info(m
, crtc
);
3120 active
= cursor_position(dev
, crtc
->pipe
, &x
, &y
);
3121 seq_printf(m
, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3122 yesno(crtc
->cursor_base
),
3123 x
, y
, crtc
->base
.cursor
->state
->crtc_w
,
3124 crtc
->base
.cursor
->state
->crtc_h
,
3125 crtc
->cursor_addr
, yesno(active
));
3126 intel_scaler_info(m
, crtc
);
3127 intel_plane_info(m
, crtc
);
3130 seq_printf(m
, "\tunderrun reporting: cpu=%s pch=%s \n",
3131 yesno(!crtc
->cpu_fifo_underrun_disabled
),
3132 yesno(!crtc
->pch_fifo_underrun_disabled
));
3135 seq_printf(m
, "\n");
3136 seq_printf(m
, "Connector info\n");
3137 seq_printf(m
, "--------------\n");
3138 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
3139 intel_connector_info(m
, connector
);
3141 drm_modeset_unlock_all(dev
);
3142 intel_runtime_pm_put(dev_priv
);
3147 static int i915_semaphore_status(struct seq_file
*m
, void *unused
)
3149 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3150 struct drm_device
*dev
= node
->minor
->dev
;
3151 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3152 struct intel_engine_cs
*engine
;
3153 int num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
3154 enum intel_engine_id id
;
3157 if (!i915_semaphore_is_enabled(dev
)) {
3158 seq_puts(m
, "Semaphores are disabled\n");
3162 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3165 intel_runtime_pm_get(dev_priv
);
3167 if (IS_BROADWELL(dev
)) {
3171 page
= i915_gem_object_get_page(dev_priv
->semaphore_obj
, 0);
3173 seqno
= (uint64_t *)kmap_atomic(page
);
3174 for_each_engine_id(engine
, dev_priv
, id
) {
3177 seq_printf(m
, "%s\n", engine
->name
);
3179 seq_puts(m
, " Last signal:");
3180 for (j
= 0; j
< num_rings
; j
++) {
3181 offset
= id
* I915_NUM_ENGINES
+ j
;
3182 seq_printf(m
, "0x%08llx (0x%02llx) ",
3183 seqno
[offset
], offset
* 8);
3187 seq_puts(m
, " Last wait: ");
3188 for (j
= 0; j
< num_rings
; j
++) {
3189 offset
= id
+ (j
* I915_NUM_ENGINES
);
3190 seq_printf(m
, "0x%08llx (0x%02llx) ",
3191 seqno
[offset
], offset
* 8);
3196 kunmap_atomic(seqno
);
3198 seq_puts(m
, " Last signal:");
3199 for_each_engine(engine
, dev_priv
)
3200 for (j
= 0; j
< num_rings
; j
++)
3201 seq_printf(m
, "0x%08x\n",
3202 I915_READ(engine
->semaphore
.mbox
.signal
[j
]));
3206 seq_puts(m
, "\nSync seqno:\n");
3207 for_each_engine(engine
, dev_priv
) {
3208 for (j
= 0; j
< num_rings
; j
++)
3209 seq_printf(m
, " 0x%08x ",
3210 engine
->semaphore
.sync_seqno
[j
]);
3215 intel_runtime_pm_put(dev_priv
);
3216 mutex_unlock(&dev
->struct_mutex
);
3220 static int i915_shared_dplls_info(struct seq_file
*m
, void *unused
)
3222 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3223 struct drm_device
*dev
= node
->minor
->dev
;
3224 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3227 drm_modeset_lock_all(dev
);
3228 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3229 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
3231 seq_printf(m
, "DPLL%i: %s, id: %i\n", i
, pll
->name
, pll
->id
);
3232 seq_printf(m
, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3233 pll
->config
.crtc_mask
, pll
->active_mask
, yesno(pll
->on
));
3234 seq_printf(m
, " tracked hardware state:\n");
3235 seq_printf(m
, " dpll: 0x%08x\n", pll
->config
.hw_state
.dpll
);
3236 seq_printf(m
, " dpll_md: 0x%08x\n",
3237 pll
->config
.hw_state
.dpll_md
);
3238 seq_printf(m
, " fp0: 0x%08x\n", pll
->config
.hw_state
.fp0
);
3239 seq_printf(m
, " fp1: 0x%08x\n", pll
->config
.hw_state
.fp1
);
3240 seq_printf(m
, " wrpll: 0x%08x\n", pll
->config
.hw_state
.wrpll
);
3242 drm_modeset_unlock_all(dev
);
3247 static int i915_wa_registers(struct seq_file
*m
, void *unused
)
3251 struct intel_engine_cs
*engine
;
3252 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3253 struct drm_device
*dev
= node
->minor
->dev
;
3254 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3255 struct i915_workarounds
*workarounds
= &dev_priv
->workarounds
;
3256 enum intel_engine_id id
;
3258 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3262 intel_runtime_pm_get(dev_priv
);
3264 seq_printf(m
, "Workarounds applied: %d\n", workarounds
->count
);
3265 for_each_engine_id(engine
, dev_priv
, id
)
3266 seq_printf(m
, "HW whitelist count for %s: %d\n",
3267 engine
->name
, workarounds
->hw_whitelist_count
[id
]);
3268 for (i
= 0; i
< workarounds
->count
; ++i
) {
3270 u32 mask
, value
, read
;
3273 addr
= workarounds
->reg
[i
].addr
;
3274 mask
= workarounds
->reg
[i
].mask
;
3275 value
= workarounds
->reg
[i
].value
;
3276 read
= I915_READ(addr
);
3277 ok
= (value
& mask
) == (read
& mask
);
3278 seq_printf(m
, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3279 i915_mmio_reg_offset(addr
), value
, mask
, read
, ok
? "OK" : "FAIL");
3282 intel_runtime_pm_put(dev_priv
);
3283 mutex_unlock(&dev
->struct_mutex
);
3288 static int i915_ddb_info(struct seq_file
*m
, void *unused
)
3290 struct drm_info_node
*node
= m
->private;
3291 struct drm_device
*dev
= node
->minor
->dev
;
3292 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3293 struct skl_ddb_allocation
*ddb
;
3294 struct skl_ddb_entry
*entry
;
3298 if (INTEL_INFO(dev
)->gen
< 9)
3301 drm_modeset_lock_all(dev
);
3303 ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
3305 seq_printf(m
, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3307 for_each_pipe(dev_priv
, pipe
) {
3308 seq_printf(m
, "Pipe %c\n", pipe_name(pipe
));
3310 for_each_plane(dev_priv
, pipe
, plane
) {
3311 entry
= &ddb
->plane
[pipe
][plane
];
3312 seq_printf(m
, " Plane%-8d%8u%8u%8u\n", plane
+ 1,
3313 entry
->start
, entry
->end
,
3314 skl_ddb_entry_size(entry
));
3317 entry
= &ddb
->plane
[pipe
][PLANE_CURSOR
];
3318 seq_printf(m
, " %-13s%8u%8u%8u\n", "Cursor", entry
->start
,
3319 entry
->end
, skl_ddb_entry_size(entry
));
3322 drm_modeset_unlock_all(dev
);
3327 static void drrs_status_per_crtc(struct seq_file
*m
,
3328 struct drm_device
*dev
, struct intel_crtc
*intel_crtc
)
3330 struct intel_encoder
*intel_encoder
;
3331 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3332 struct i915_drrs
*drrs
= &dev_priv
->drrs
;
3335 for_each_encoder_on_crtc(dev
, &intel_crtc
->base
, intel_encoder
) {
3336 /* Encoder connected on this CRTC */
3337 switch (intel_encoder
->type
) {
3338 case INTEL_OUTPUT_EDP
:
3339 seq_puts(m
, "eDP:\n");
3341 case INTEL_OUTPUT_DSI
:
3342 seq_puts(m
, "DSI:\n");
3344 case INTEL_OUTPUT_HDMI
:
3345 seq_puts(m
, "HDMI:\n");
3347 case INTEL_OUTPUT_DISPLAYPORT
:
3348 seq_puts(m
, "DP:\n");
3351 seq_printf(m
, "Other encoder (id=%d).\n",
3352 intel_encoder
->type
);
3357 if (dev_priv
->vbt
.drrs_type
== STATIC_DRRS_SUPPORT
)
3358 seq_puts(m
, "\tVBT: DRRS_type: Static");
3359 else if (dev_priv
->vbt
.drrs_type
== SEAMLESS_DRRS_SUPPORT
)
3360 seq_puts(m
, "\tVBT: DRRS_type: Seamless");
3361 else if (dev_priv
->vbt
.drrs_type
== DRRS_NOT_SUPPORTED
)
3362 seq_puts(m
, "\tVBT: DRRS_type: None");
3364 seq_puts(m
, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3366 seq_puts(m
, "\n\n");
3368 if (to_intel_crtc_state(intel_crtc
->base
.state
)->has_drrs
) {
3369 struct intel_panel
*panel
;
3371 mutex_lock(&drrs
->mutex
);
3372 /* DRRS Supported */
3373 seq_puts(m
, "\tDRRS Supported: Yes\n");
3375 /* disable_drrs() will make drrs->dp NULL */
3377 seq_puts(m
, "Idleness DRRS: Disabled");
3378 mutex_unlock(&drrs
->mutex
);
3382 panel
= &drrs
->dp
->attached_connector
->panel
;
3383 seq_printf(m
, "\t\tBusy_frontbuffer_bits: 0x%X",
3384 drrs
->busy_frontbuffer_bits
);
3386 seq_puts(m
, "\n\t\t");
3387 if (drrs
->refresh_rate_type
== DRRS_HIGH_RR
) {
3388 seq_puts(m
, "DRRS_State: DRRS_HIGH_RR\n");
3389 vrefresh
= panel
->fixed_mode
->vrefresh
;
3390 } else if (drrs
->refresh_rate_type
== DRRS_LOW_RR
) {
3391 seq_puts(m
, "DRRS_State: DRRS_LOW_RR\n");
3392 vrefresh
= panel
->downclock_mode
->vrefresh
;
3394 seq_printf(m
, "DRRS_State: Unknown(%d)\n",
3395 drrs
->refresh_rate_type
);
3396 mutex_unlock(&drrs
->mutex
);
3399 seq_printf(m
, "\t\tVrefresh: %d", vrefresh
);
3401 seq_puts(m
, "\n\t\t");
3402 mutex_unlock(&drrs
->mutex
);
3404 /* DRRS not supported. Print the VBT parameter*/
3405 seq_puts(m
, "\tDRRS Supported : No");
3410 static int i915_drrs_status(struct seq_file
*m
, void *unused
)
3412 struct drm_info_node
*node
= m
->private;
3413 struct drm_device
*dev
= node
->minor
->dev
;
3414 struct intel_crtc
*intel_crtc
;
3415 int active_crtc_cnt
= 0;
3417 for_each_intel_crtc(dev
, intel_crtc
) {
3418 drm_modeset_lock(&intel_crtc
->base
.mutex
, NULL
);
3420 if (intel_crtc
->base
.state
->active
) {
3422 seq_printf(m
, "\nCRTC %d: ", active_crtc_cnt
);
3424 drrs_status_per_crtc(m
, dev
, intel_crtc
);
3427 drm_modeset_unlock(&intel_crtc
->base
.mutex
);
3430 if (!active_crtc_cnt
)
3431 seq_puts(m
, "No active crtc found\n");
3436 struct pipe_crc_info
{
3438 struct drm_device
*dev
;
3442 static int i915_dp_mst_info(struct seq_file
*m
, void *unused
)
3444 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3445 struct drm_device
*dev
= node
->minor
->dev
;
3446 struct drm_encoder
*encoder
;
3447 struct intel_encoder
*intel_encoder
;
3448 struct intel_digital_port
*intel_dig_port
;
3449 drm_modeset_lock_all(dev
);
3450 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
3451 intel_encoder
= to_intel_encoder(encoder
);
3452 if (intel_encoder
->type
!= INTEL_OUTPUT_DISPLAYPORT
)
3454 intel_dig_port
= enc_to_dig_port(encoder
);
3455 if (!intel_dig_port
->dp
.can_mst
)
3458 drm_dp_mst_dump_topology(m
, &intel_dig_port
->dp
.mst_mgr
);
3460 drm_modeset_unlock_all(dev
);
3464 static int i915_pipe_crc_open(struct inode
*inode
, struct file
*filep
)
3466 struct pipe_crc_info
*info
= inode
->i_private
;
3467 struct drm_i915_private
*dev_priv
= info
->dev
->dev_private
;
3468 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
3470 if (info
->pipe
>= INTEL_INFO(info
->dev
)->num_pipes
)
3473 spin_lock_irq(&pipe_crc
->lock
);
3475 if (pipe_crc
->opened
) {
3476 spin_unlock_irq(&pipe_crc
->lock
);
3477 return -EBUSY
; /* already open */
3480 pipe_crc
->opened
= true;
3481 filep
->private_data
= inode
->i_private
;
3483 spin_unlock_irq(&pipe_crc
->lock
);
3488 static int i915_pipe_crc_release(struct inode
*inode
, struct file
*filep
)
3490 struct pipe_crc_info
*info
= inode
->i_private
;
3491 struct drm_i915_private
*dev_priv
= info
->dev
->dev_private
;
3492 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
3494 spin_lock_irq(&pipe_crc
->lock
);
3495 pipe_crc
->opened
= false;
3496 spin_unlock_irq(&pipe_crc
->lock
);
3501 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3502 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3503 /* account for \'0' */
3504 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3506 static int pipe_crc_data_count(struct intel_pipe_crc
*pipe_crc
)
3508 assert_spin_locked(&pipe_crc
->lock
);
3509 return CIRC_CNT(pipe_crc
->head
, pipe_crc
->tail
,
3510 INTEL_PIPE_CRC_ENTRIES_NR
);
3514 i915_pipe_crc_read(struct file
*filep
, char __user
*user_buf
, size_t count
,
3517 struct pipe_crc_info
*info
= filep
->private_data
;
3518 struct drm_device
*dev
= info
->dev
;
3519 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3520 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
3521 char buf
[PIPE_CRC_BUFFER_LEN
];
3526 * Don't allow user space to provide buffers not big enough to hold
3529 if (count
< PIPE_CRC_LINE_LEN
)
3532 if (pipe_crc
->source
== INTEL_PIPE_CRC_SOURCE_NONE
)
3535 /* nothing to read */
3536 spin_lock_irq(&pipe_crc
->lock
);
3537 while (pipe_crc_data_count(pipe_crc
) == 0) {
3540 if (filep
->f_flags
& O_NONBLOCK
) {
3541 spin_unlock_irq(&pipe_crc
->lock
);
3545 ret
= wait_event_interruptible_lock_irq(pipe_crc
->wq
,
3546 pipe_crc_data_count(pipe_crc
), pipe_crc
->lock
);
3548 spin_unlock_irq(&pipe_crc
->lock
);
3553 /* We now have one or more entries to read */
3554 n_entries
= count
/ PIPE_CRC_LINE_LEN
;
3557 while (n_entries
> 0) {
3558 struct intel_pipe_crc_entry
*entry
=
3559 &pipe_crc
->entries
[pipe_crc
->tail
];
3562 if (CIRC_CNT(pipe_crc
->head
, pipe_crc
->tail
,
3563 INTEL_PIPE_CRC_ENTRIES_NR
) < 1)
3566 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR
);
3567 pipe_crc
->tail
= (pipe_crc
->tail
+ 1) & (INTEL_PIPE_CRC_ENTRIES_NR
- 1);
3569 bytes_read
+= snprintf(buf
, PIPE_CRC_BUFFER_LEN
,
3570 "%8u %8x %8x %8x %8x %8x\n",
3571 entry
->frame
, entry
->crc
[0],
3572 entry
->crc
[1], entry
->crc
[2],
3573 entry
->crc
[3], entry
->crc
[4]);
3575 spin_unlock_irq(&pipe_crc
->lock
);
3577 ret
= copy_to_user(user_buf
, buf
, PIPE_CRC_LINE_LEN
);
3578 if (ret
== PIPE_CRC_LINE_LEN
)
3581 user_buf
+= PIPE_CRC_LINE_LEN
;
3584 spin_lock_irq(&pipe_crc
->lock
);
3587 spin_unlock_irq(&pipe_crc
->lock
);
3592 static const struct file_operations i915_pipe_crc_fops
= {
3593 .owner
= THIS_MODULE
,
3594 .open
= i915_pipe_crc_open
,
3595 .read
= i915_pipe_crc_read
,
3596 .release
= i915_pipe_crc_release
,
3599 static struct pipe_crc_info i915_pipe_crc_data
[I915_MAX_PIPES
] = {
3601 .name
= "i915_pipe_A_crc",
3605 .name
= "i915_pipe_B_crc",
3609 .name
= "i915_pipe_C_crc",
3614 static int i915_pipe_crc_create(struct dentry
*root
, struct drm_minor
*minor
,
3617 struct drm_device
*dev
= minor
->dev
;
3619 struct pipe_crc_info
*info
= &i915_pipe_crc_data
[pipe
];
3622 ent
= debugfs_create_file(info
->name
, S_IRUGO
, root
, info
,
3623 &i915_pipe_crc_fops
);
3627 return drm_add_fake_info_node(minor
, ent
, info
);
3630 static const char * const pipe_crc_sources
[] = {
3643 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source
)
3645 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources
) != INTEL_PIPE_CRC_SOURCE_MAX
);
3646 return pipe_crc_sources
[source
];
3649 static int display_crc_ctl_show(struct seq_file
*m
, void *data
)
3651 struct drm_device
*dev
= m
->private;
3652 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3655 for (i
= 0; i
< I915_MAX_PIPES
; i
++)
3656 seq_printf(m
, "%c %s\n", pipe_name(i
),
3657 pipe_crc_source_name(dev_priv
->pipe_crc
[i
].source
));
3662 static int display_crc_ctl_open(struct inode
*inode
, struct file
*file
)
3664 struct drm_device
*dev
= inode
->i_private
;
3666 return single_open(file
, display_crc_ctl_show
, dev
);
3669 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
3672 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3673 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3676 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3677 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_INCLUDE_BORDER_I8XX
;
3679 case INTEL_PIPE_CRC_SOURCE_NONE
:
3689 static int i9xx_pipe_crc_auto_source(struct drm_device
*dev
, enum pipe pipe
,
3690 enum intel_pipe_crc_source
*source
)
3692 struct intel_encoder
*encoder
;
3693 struct intel_crtc
*crtc
;
3694 struct intel_digital_port
*dig_port
;
3697 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3699 drm_modeset_lock_all(dev
);
3700 for_each_intel_encoder(dev
, encoder
) {
3701 if (!encoder
->base
.crtc
)
3704 crtc
= to_intel_crtc(encoder
->base
.crtc
);
3706 if (crtc
->pipe
!= pipe
)
3709 switch (encoder
->type
) {
3710 case INTEL_OUTPUT_TVOUT
:
3711 *source
= INTEL_PIPE_CRC_SOURCE_TV
;
3713 case INTEL_OUTPUT_DISPLAYPORT
:
3714 case INTEL_OUTPUT_EDP
:
3715 dig_port
= enc_to_dig_port(&encoder
->base
);
3716 switch (dig_port
->port
) {
3718 *source
= INTEL_PIPE_CRC_SOURCE_DP_B
;
3721 *source
= INTEL_PIPE_CRC_SOURCE_DP_C
;
3724 *source
= INTEL_PIPE_CRC_SOURCE_DP_D
;
3727 WARN(1, "nonexisting DP port %c\n",
3728 port_name(dig_port
->port
));
3736 drm_modeset_unlock_all(dev
);
3741 static int vlv_pipe_crc_ctl_reg(struct drm_device
*dev
,
3743 enum intel_pipe_crc_source
*source
,
3746 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3747 bool need_stable_symbols
= false;
3749 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
3750 int ret
= i9xx_pipe_crc_auto_source(dev
, pipe
, source
);
3756 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3757 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_VLV
;
3759 case INTEL_PIPE_CRC_SOURCE_DP_B
:
3760 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_VLV
;
3761 need_stable_symbols
= true;
3763 case INTEL_PIPE_CRC_SOURCE_DP_C
:
3764 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_VLV
;
3765 need_stable_symbols
= true;
3767 case INTEL_PIPE_CRC_SOURCE_DP_D
:
3768 if (!IS_CHERRYVIEW(dev
))
3770 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_D_VLV
;
3771 need_stable_symbols
= true;
3773 case INTEL_PIPE_CRC_SOURCE_NONE
:
3781 * When the pipe CRC tap point is after the transcoders we need
3782 * to tweak symbol-level features to produce a deterministic series of
3783 * symbols for a given frame. We need to reset those features only once
3784 * a frame (instead of every nth symbol):
3785 * - DC-balance: used to ensure a better clock recovery from the data
3787 * - DisplayPort scrambling: used for EMI reduction
3789 if (need_stable_symbols
) {
3790 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3792 tmp
|= DC_BALANCE_RESET_VLV
;
3795 tmp
|= PIPE_A_SCRAMBLE_RESET
;
3798 tmp
|= PIPE_B_SCRAMBLE_RESET
;
3801 tmp
|= PIPE_C_SCRAMBLE_RESET
;
3806 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3812 static int i9xx_pipe_crc_ctl_reg(struct drm_device
*dev
,
3814 enum intel_pipe_crc_source
*source
,
3817 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3818 bool need_stable_symbols
= false;
3820 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
3821 int ret
= i9xx_pipe_crc_auto_source(dev
, pipe
, source
);
3827 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3828 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_I9XX
;
3830 case INTEL_PIPE_CRC_SOURCE_TV
:
3831 if (!SUPPORTS_TV(dev
))
3833 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_TV_PRE
;
3835 case INTEL_PIPE_CRC_SOURCE_DP_B
:
3838 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_G4X
;
3839 need_stable_symbols
= true;
3841 case INTEL_PIPE_CRC_SOURCE_DP_C
:
3844 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_G4X
;
3845 need_stable_symbols
= true;
3847 case INTEL_PIPE_CRC_SOURCE_DP_D
:
3850 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_D_G4X
;
3851 need_stable_symbols
= true;
3853 case INTEL_PIPE_CRC_SOURCE_NONE
:
3861 * When the pipe CRC tap point is after the transcoders we need
3862 * to tweak symbol-level features to produce a deterministic series of
3863 * symbols for a given frame. We need to reset those features only once
3864 * a frame (instead of every nth symbol):
3865 * - DC-balance: used to ensure a better clock recovery from the data
3867 * - DisplayPort scrambling: used for EMI reduction
3869 if (need_stable_symbols
) {
3870 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3872 WARN_ON(!IS_G4X(dev
));
3874 I915_WRITE(PORT_DFT_I9XX
,
3875 I915_READ(PORT_DFT_I9XX
) | DC_BALANCE_RESET
);
3878 tmp
|= PIPE_A_SCRAMBLE_RESET
;
3880 tmp
|= PIPE_B_SCRAMBLE_RESET
;
3882 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3888 static void vlv_undo_pipe_scramble_reset(struct drm_device
*dev
,
3891 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3892 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3896 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
3899 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
3902 tmp
&= ~PIPE_C_SCRAMBLE_RESET
;
3907 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
))
3908 tmp
&= ~DC_BALANCE_RESET_VLV
;
3909 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3913 static void g4x_undo_pipe_scramble_reset(struct drm_device
*dev
,
3916 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3917 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3920 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
3922 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
3923 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3925 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
)) {
3926 I915_WRITE(PORT_DFT_I9XX
,
3927 I915_READ(PORT_DFT_I9XX
) & ~DC_BALANCE_RESET
);
3931 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
3934 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3935 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3938 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
3939 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_ILK
;
3941 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
3942 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_ILK
;
3944 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3945 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_ILK
;
3947 case INTEL_PIPE_CRC_SOURCE_NONE
:
3957 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device
*dev
, bool enable
)
3959 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3960 struct intel_crtc
*crtc
=
3961 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_A
]);
3962 struct intel_crtc_state
*pipe_config
;
3963 struct drm_atomic_state
*state
;
3966 drm_modeset_lock_all(dev
);
3967 state
= drm_atomic_state_alloc(dev
);
3973 state
->acquire_ctx
= drm_modeset_legacy_acquire_ctx(&crtc
->base
);
3974 pipe_config
= intel_atomic_get_crtc_state(state
, crtc
);
3975 if (IS_ERR(pipe_config
)) {
3976 ret
= PTR_ERR(pipe_config
);
3980 pipe_config
->pch_pfit
.force_thru
= enable
;
3981 if (pipe_config
->cpu_transcoder
== TRANSCODER_EDP
&&
3982 pipe_config
->pch_pfit
.enabled
!= enable
)
3983 pipe_config
->base
.connectors_changed
= true;
3985 ret
= drm_atomic_commit(state
);
3987 drm_modeset_unlock_all(dev
);
3988 WARN(ret
, "Toggling workaround to %i returns %i\n", enable
, ret
);
3990 drm_atomic_state_free(state
);
3993 static int ivb_pipe_crc_ctl_reg(struct drm_device
*dev
,
3995 enum intel_pipe_crc_source
*source
,
3998 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3999 *source
= INTEL_PIPE_CRC_SOURCE_PF
;
4002 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
4003 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_IVB
;
4005 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
4006 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_IVB
;
4008 case INTEL_PIPE_CRC_SOURCE_PF
:
4009 if (IS_HASWELL(dev
) && pipe
== PIPE_A
)
4010 hsw_trans_edp_pipe_A_crc_wa(dev
, true);
4012 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PF_IVB
;
4014 case INTEL_PIPE_CRC_SOURCE_NONE
:
4024 static int pipe_crc_set_source(struct drm_device
*dev
, enum pipe pipe
,
4025 enum intel_pipe_crc_source source
)
4027 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4028 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
4029 struct intel_crtc
*crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
,
4031 enum intel_display_power_domain power_domain
;
4032 u32 val
= 0; /* shut up gcc */
4035 if (pipe_crc
->source
== source
)
4038 /* forbid changing the source without going back to 'none' */
4039 if (pipe_crc
->source
&& source
)
4042 power_domain
= POWER_DOMAIN_PIPE(pipe
);
4043 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
)) {
4044 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4049 ret
= i8xx_pipe_crc_ctl_reg(&source
, &val
);
4050 else if (INTEL_INFO(dev
)->gen
< 5)
4051 ret
= i9xx_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
4052 else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
4053 ret
= vlv_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
4054 else if (IS_GEN5(dev
) || IS_GEN6(dev
))
4055 ret
= ilk_pipe_crc_ctl_reg(&source
, &val
);
4057 ret
= ivb_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
4062 /* none -> real source transition */
4064 struct intel_pipe_crc_entry
*entries
;
4066 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4067 pipe_name(pipe
), pipe_crc_source_name(source
));
4069 entries
= kcalloc(INTEL_PIPE_CRC_ENTRIES_NR
,
4070 sizeof(pipe_crc
->entries
[0]),
4078 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4079 * enabled and disabled dynamically based on package C states,
4080 * user space can't make reliable use of the CRCs, so let's just
4081 * completely disable it.
4083 hsw_disable_ips(crtc
);
4085 spin_lock_irq(&pipe_crc
->lock
);
4086 kfree(pipe_crc
->entries
);
4087 pipe_crc
->entries
= entries
;
4090 spin_unlock_irq(&pipe_crc
->lock
);
4093 pipe_crc
->source
= source
;
4095 I915_WRITE(PIPE_CRC_CTL(pipe
), val
);
4096 POSTING_READ(PIPE_CRC_CTL(pipe
));
4098 /* real source -> none transition */
4099 if (source
== INTEL_PIPE_CRC_SOURCE_NONE
) {
4100 struct intel_pipe_crc_entry
*entries
;
4101 struct intel_crtc
*crtc
=
4102 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
4104 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4107 drm_modeset_lock(&crtc
->base
.mutex
, NULL
);
4108 if (crtc
->base
.state
->active
)
4109 intel_wait_for_vblank(dev
, pipe
);
4110 drm_modeset_unlock(&crtc
->base
.mutex
);
4112 spin_lock_irq(&pipe_crc
->lock
);
4113 entries
= pipe_crc
->entries
;
4114 pipe_crc
->entries
= NULL
;
4117 spin_unlock_irq(&pipe_crc
->lock
);
4122 g4x_undo_pipe_scramble_reset(dev
, pipe
);
4123 else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
4124 vlv_undo_pipe_scramble_reset(dev
, pipe
);
4125 else if (IS_HASWELL(dev
) && pipe
== PIPE_A
)
4126 hsw_trans_edp_pipe_A_crc_wa(dev
, false);
4128 hsw_enable_ips(crtc
);
4134 intel_display_power_put(dev_priv
, power_domain
);
4140 * Parse pipe CRC command strings:
4141 * command: wsp* object wsp+ name wsp+ source wsp*
4144 * source: (none | plane1 | plane2 | pf)
4145 * wsp: (#0x20 | #0x9 | #0xA)+
4148 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
4149 * "pipe A none" -> Stop CRC
4151 static int display_crc_ctl_tokenize(char *buf
, char *words
[], int max_words
)
4158 /* skip leading white space */
4159 buf
= skip_spaces(buf
);
4161 break; /* end of buffer */
4163 /* find end of word */
4164 for (end
= buf
; *end
&& !isspace(*end
); end
++)
4167 if (n_words
== max_words
) {
4168 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4170 return -EINVAL
; /* ran out of words[] before bytes */
4175 words
[n_words
++] = buf
;
4182 enum intel_pipe_crc_object
{
4183 PIPE_CRC_OBJECT_PIPE
,
4186 static const char * const pipe_crc_objects
[] = {
4191 display_crc_ctl_parse_object(const char *buf
, enum intel_pipe_crc_object
*o
)
4195 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_objects
); i
++)
4196 if (!strcmp(buf
, pipe_crc_objects
[i
])) {
4204 static int display_crc_ctl_parse_pipe(const char *buf
, enum pipe
*pipe
)
4206 const char name
= buf
[0];
4208 if (name
< 'A' || name
>= pipe_name(I915_MAX_PIPES
))
4217 display_crc_ctl_parse_source(const char *buf
, enum intel_pipe_crc_source
*s
)
4221 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_sources
); i
++)
4222 if (!strcmp(buf
, pipe_crc_sources
[i
])) {
4230 static int display_crc_ctl_parse(struct drm_device
*dev
, char *buf
, size_t len
)
4234 char *words
[N_WORDS
];
4236 enum intel_pipe_crc_object object
;
4237 enum intel_pipe_crc_source source
;
4239 n_words
= display_crc_ctl_tokenize(buf
, words
, N_WORDS
);
4240 if (n_words
!= N_WORDS
) {
4241 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4246 if (display_crc_ctl_parse_object(words
[0], &object
) < 0) {
4247 DRM_DEBUG_DRIVER("unknown object %s\n", words
[0]);
4251 if (display_crc_ctl_parse_pipe(words
[1], &pipe
) < 0) {
4252 DRM_DEBUG_DRIVER("unknown pipe %s\n", words
[1]);
4256 if (display_crc_ctl_parse_source(words
[2], &source
) < 0) {
4257 DRM_DEBUG_DRIVER("unknown source %s\n", words
[2]);
4261 return pipe_crc_set_source(dev
, pipe
, source
);
4264 static ssize_t
display_crc_ctl_write(struct file
*file
, const char __user
*ubuf
,
4265 size_t len
, loff_t
*offp
)
4267 struct seq_file
*m
= file
->private_data
;
4268 struct drm_device
*dev
= m
->private;
4275 if (len
> PAGE_SIZE
- 1) {
4276 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4281 tmpbuf
= kmalloc(len
+ 1, GFP_KERNEL
);
4285 if (copy_from_user(tmpbuf
, ubuf
, len
)) {
4291 ret
= display_crc_ctl_parse(dev
, tmpbuf
, len
);
4302 static const struct file_operations i915_display_crc_ctl_fops
= {
4303 .owner
= THIS_MODULE
,
4304 .open
= display_crc_ctl_open
,
4306 .llseek
= seq_lseek
,
4307 .release
= single_release
,
4308 .write
= display_crc_ctl_write
4311 static ssize_t
i915_displayport_test_active_write(struct file
*file
,
4312 const char __user
*ubuf
,
4313 size_t len
, loff_t
*offp
)
4317 struct drm_device
*dev
;
4318 struct drm_connector
*connector
;
4319 struct list_head
*connector_list
;
4320 struct intel_dp
*intel_dp
;
4323 dev
= ((struct seq_file
*)file
->private_data
)->private;
4325 connector_list
= &dev
->mode_config
.connector_list
;
4330 input_buffer
= kmalloc(len
+ 1, GFP_KERNEL
);
4334 if (copy_from_user(input_buffer
, ubuf
, len
)) {
4339 input_buffer
[len
] = '\0';
4340 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len
);
4342 list_for_each_entry(connector
, connector_list
, head
) {
4344 if (connector
->connector_type
!=
4345 DRM_MODE_CONNECTOR_DisplayPort
)
4348 if (connector
->status
== connector_status_connected
&&
4349 connector
->encoder
!= NULL
) {
4350 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4351 status
= kstrtoint(input_buffer
, 10, &val
);
4354 DRM_DEBUG_DRIVER("Got %d for test active\n", val
);
4355 /* To prevent erroneous activation of the compliance
4356 * testing code, only accept an actual value of 1 here
4359 intel_dp
->compliance_test_active
= 1;
4361 intel_dp
->compliance_test_active
= 0;
4365 kfree(input_buffer
);
4373 static int i915_displayport_test_active_show(struct seq_file
*m
, void *data
)
4375 struct drm_device
*dev
= m
->private;
4376 struct drm_connector
*connector
;
4377 struct list_head
*connector_list
= &dev
->mode_config
.connector_list
;
4378 struct intel_dp
*intel_dp
;
4380 list_for_each_entry(connector
, connector_list
, head
) {
4382 if (connector
->connector_type
!=
4383 DRM_MODE_CONNECTOR_DisplayPort
)
4386 if (connector
->status
== connector_status_connected
&&
4387 connector
->encoder
!= NULL
) {
4388 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4389 if (intel_dp
->compliance_test_active
)
4400 static int i915_displayport_test_active_open(struct inode
*inode
,
4403 struct drm_device
*dev
= inode
->i_private
;
4405 return single_open(file
, i915_displayport_test_active_show
, dev
);
4408 static const struct file_operations i915_displayport_test_active_fops
= {
4409 .owner
= THIS_MODULE
,
4410 .open
= i915_displayport_test_active_open
,
4412 .llseek
= seq_lseek
,
4413 .release
= single_release
,
4414 .write
= i915_displayport_test_active_write
4417 static int i915_displayport_test_data_show(struct seq_file
*m
, void *data
)
4419 struct drm_device
*dev
= m
->private;
4420 struct drm_connector
*connector
;
4421 struct list_head
*connector_list
= &dev
->mode_config
.connector_list
;
4422 struct intel_dp
*intel_dp
;
4424 list_for_each_entry(connector
, connector_list
, head
) {
4426 if (connector
->connector_type
!=
4427 DRM_MODE_CONNECTOR_DisplayPort
)
4430 if (connector
->status
== connector_status_connected
&&
4431 connector
->encoder
!= NULL
) {
4432 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4433 seq_printf(m
, "%lx", intel_dp
->compliance_test_data
);
4440 static int i915_displayport_test_data_open(struct inode
*inode
,
4443 struct drm_device
*dev
= inode
->i_private
;
4445 return single_open(file
, i915_displayport_test_data_show
, dev
);
4448 static const struct file_operations i915_displayport_test_data_fops
= {
4449 .owner
= THIS_MODULE
,
4450 .open
= i915_displayport_test_data_open
,
4452 .llseek
= seq_lseek
,
4453 .release
= single_release
4456 static int i915_displayport_test_type_show(struct seq_file
*m
, void *data
)
4458 struct drm_device
*dev
= m
->private;
4459 struct drm_connector
*connector
;
4460 struct list_head
*connector_list
= &dev
->mode_config
.connector_list
;
4461 struct intel_dp
*intel_dp
;
4463 list_for_each_entry(connector
, connector_list
, head
) {
4465 if (connector
->connector_type
!=
4466 DRM_MODE_CONNECTOR_DisplayPort
)
4469 if (connector
->status
== connector_status_connected
&&
4470 connector
->encoder
!= NULL
) {
4471 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4472 seq_printf(m
, "%02lx", intel_dp
->compliance_test_type
);
4480 static int i915_displayport_test_type_open(struct inode
*inode
,
4483 struct drm_device
*dev
= inode
->i_private
;
4485 return single_open(file
, i915_displayport_test_type_show
, dev
);
4488 static const struct file_operations i915_displayport_test_type_fops
= {
4489 .owner
= THIS_MODULE
,
4490 .open
= i915_displayport_test_type_open
,
4492 .llseek
= seq_lseek
,
4493 .release
= single_release
4496 static void wm_latency_show(struct seq_file
*m
, const uint16_t wm
[8])
4498 struct drm_device
*dev
= m
->private;
4502 if (IS_CHERRYVIEW(dev
))
4504 else if (IS_VALLEYVIEW(dev
))
4507 num_levels
= ilk_wm_max_level(dev
) + 1;
4509 drm_modeset_lock_all(dev
);
4511 for (level
= 0; level
< num_levels
; level
++) {
4512 unsigned int latency
= wm
[level
];
4515 * - WM1+ latency values in 0.5us units
4516 * - latencies are in us on gen9/vlv/chv
4518 if (INTEL_INFO(dev
)->gen
>= 9 || IS_VALLEYVIEW(dev
) ||
4524 seq_printf(m
, "WM%d %u (%u.%u usec)\n",
4525 level
, wm
[level
], latency
/ 10, latency
% 10);
4528 drm_modeset_unlock_all(dev
);
4531 static int pri_wm_latency_show(struct seq_file
*m
, void *data
)
4533 struct drm_device
*dev
= m
->private;
4534 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4535 const uint16_t *latencies
;
4537 if (INTEL_INFO(dev
)->gen
>= 9)
4538 latencies
= dev_priv
->wm
.skl_latency
;
4540 latencies
= to_i915(dev
)->wm
.pri_latency
;
4542 wm_latency_show(m
, latencies
);
4547 static int spr_wm_latency_show(struct seq_file
*m
, void *data
)
4549 struct drm_device
*dev
= m
->private;
4550 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4551 const uint16_t *latencies
;
4553 if (INTEL_INFO(dev
)->gen
>= 9)
4554 latencies
= dev_priv
->wm
.skl_latency
;
4556 latencies
= to_i915(dev
)->wm
.spr_latency
;
4558 wm_latency_show(m
, latencies
);
4563 static int cur_wm_latency_show(struct seq_file
*m
, void *data
)
4565 struct drm_device
*dev
= m
->private;
4566 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4567 const uint16_t *latencies
;
4569 if (INTEL_INFO(dev
)->gen
>= 9)
4570 latencies
= dev_priv
->wm
.skl_latency
;
4572 latencies
= to_i915(dev
)->wm
.cur_latency
;
4574 wm_latency_show(m
, latencies
);
4579 static int pri_wm_latency_open(struct inode
*inode
, struct file
*file
)
4581 struct drm_device
*dev
= inode
->i_private
;
4583 if (INTEL_INFO(dev
)->gen
< 5)
4586 return single_open(file
, pri_wm_latency_show
, dev
);
4589 static int spr_wm_latency_open(struct inode
*inode
, struct file
*file
)
4591 struct drm_device
*dev
= inode
->i_private
;
4593 if (HAS_GMCH_DISPLAY(dev
))
4596 return single_open(file
, spr_wm_latency_show
, dev
);
4599 static int cur_wm_latency_open(struct inode
*inode
, struct file
*file
)
4601 struct drm_device
*dev
= inode
->i_private
;
4603 if (HAS_GMCH_DISPLAY(dev
))
4606 return single_open(file
, cur_wm_latency_show
, dev
);
4609 static ssize_t
wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4610 size_t len
, loff_t
*offp
, uint16_t wm
[8])
4612 struct seq_file
*m
= file
->private_data
;
4613 struct drm_device
*dev
= m
->private;
4614 uint16_t new[8] = { 0 };
4620 if (IS_CHERRYVIEW(dev
))
4622 else if (IS_VALLEYVIEW(dev
))
4625 num_levels
= ilk_wm_max_level(dev
) + 1;
4627 if (len
>= sizeof(tmp
))
4630 if (copy_from_user(tmp
, ubuf
, len
))
4635 ret
= sscanf(tmp
, "%hu %hu %hu %hu %hu %hu %hu %hu",
4636 &new[0], &new[1], &new[2], &new[3],
4637 &new[4], &new[5], &new[6], &new[7]);
4638 if (ret
!= num_levels
)
4641 drm_modeset_lock_all(dev
);
4643 for (level
= 0; level
< num_levels
; level
++)
4644 wm
[level
] = new[level
];
4646 drm_modeset_unlock_all(dev
);
4652 static ssize_t
pri_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4653 size_t len
, loff_t
*offp
)
4655 struct seq_file
*m
= file
->private_data
;
4656 struct drm_device
*dev
= m
->private;
4657 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4658 uint16_t *latencies
;
4660 if (INTEL_INFO(dev
)->gen
>= 9)
4661 latencies
= dev_priv
->wm
.skl_latency
;
4663 latencies
= to_i915(dev
)->wm
.pri_latency
;
4665 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
4668 static ssize_t
spr_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4669 size_t len
, loff_t
*offp
)
4671 struct seq_file
*m
= file
->private_data
;
4672 struct drm_device
*dev
= m
->private;
4673 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4674 uint16_t *latencies
;
4676 if (INTEL_INFO(dev
)->gen
>= 9)
4677 latencies
= dev_priv
->wm
.skl_latency
;
4679 latencies
= to_i915(dev
)->wm
.spr_latency
;
4681 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
4684 static ssize_t
cur_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4685 size_t len
, loff_t
*offp
)
4687 struct seq_file
*m
= file
->private_data
;
4688 struct drm_device
*dev
= m
->private;
4689 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4690 uint16_t *latencies
;
4692 if (INTEL_INFO(dev
)->gen
>= 9)
4693 latencies
= dev_priv
->wm
.skl_latency
;
4695 latencies
= to_i915(dev
)->wm
.cur_latency
;
4697 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
4700 static const struct file_operations i915_pri_wm_latency_fops
= {
4701 .owner
= THIS_MODULE
,
4702 .open
= pri_wm_latency_open
,
4704 .llseek
= seq_lseek
,
4705 .release
= single_release
,
4706 .write
= pri_wm_latency_write
4709 static const struct file_operations i915_spr_wm_latency_fops
= {
4710 .owner
= THIS_MODULE
,
4711 .open
= spr_wm_latency_open
,
4713 .llseek
= seq_lseek
,
4714 .release
= single_release
,
4715 .write
= spr_wm_latency_write
4718 static const struct file_operations i915_cur_wm_latency_fops
= {
4719 .owner
= THIS_MODULE
,
4720 .open
= cur_wm_latency_open
,
4722 .llseek
= seq_lseek
,
4723 .release
= single_release
,
4724 .write
= cur_wm_latency_write
4728 i915_wedged_get(void *data
, u64
*val
)
4730 struct drm_device
*dev
= data
;
4731 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4733 *val
= i915_terminally_wedged(&dev_priv
->gpu_error
);
4739 i915_wedged_set(void *data
, u64 val
)
4741 struct drm_device
*dev
= data
;
4742 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4745 * There is no safeguard against this debugfs entry colliding
4746 * with the hangcheck calling same i915_handle_error() in
4747 * parallel, causing an explosion. For now we assume that the
4748 * test harness is responsible enough not to inject gpu hangs
4749 * while it is writing to 'i915_wedged'
4752 if (i915_reset_in_progress(&dev_priv
->gpu_error
))
4755 intel_runtime_pm_get(dev_priv
);
4757 i915_handle_error(dev
, val
,
4758 "Manually setting wedged to %llu", val
);
4760 intel_runtime_pm_put(dev_priv
);
4765 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops
,
4766 i915_wedged_get
, i915_wedged_set
,
4770 i915_ring_stop_get(void *data
, u64
*val
)
4772 struct drm_device
*dev
= data
;
4773 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4775 *val
= dev_priv
->gpu_error
.stop_rings
;
4781 i915_ring_stop_set(void *data
, u64 val
)
4783 struct drm_device
*dev
= data
;
4784 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4787 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val
);
4789 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4793 dev_priv
->gpu_error
.stop_rings
= val
;
4794 mutex_unlock(&dev
->struct_mutex
);
4799 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops
,
4800 i915_ring_stop_get
, i915_ring_stop_set
,
4804 i915_ring_missed_irq_get(void *data
, u64
*val
)
4806 struct drm_device
*dev
= data
;
4807 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4809 *val
= dev_priv
->gpu_error
.missed_irq_rings
;
4814 i915_ring_missed_irq_set(void *data
, u64 val
)
4816 struct drm_device
*dev
= data
;
4817 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4820 /* Lock against concurrent debugfs callers */
4821 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4824 dev_priv
->gpu_error
.missed_irq_rings
= val
;
4825 mutex_unlock(&dev
->struct_mutex
);
4830 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops
,
4831 i915_ring_missed_irq_get
, i915_ring_missed_irq_set
,
4835 i915_ring_test_irq_get(void *data
, u64
*val
)
4837 struct drm_device
*dev
= data
;
4838 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4840 *val
= dev_priv
->gpu_error
.test_irq_rings
;
4846 i915_ring_test_irq_set(void *data
, u64 val
)
4848 struct drm_device
*dev
= data
;
4849 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4852 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val
);
4854 /* Lock against concurrent debugfs callers */
4855 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4859 dev_priv
->gpu_error
.test_irq_rings
= val
;
4860 mutex_unlock(&dev
->struct_mutex
);
4865 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops
,
4866 i915_ring_test_irq_get
, i915_ring_test_irq_set
,
4869 #define DROP_UNBOUND 0x1
4870 #define DROP_BOUND 0x2
4871 #define DROP_RETIRE 0x4
4872 #define DROP_ACTIVE 0x8
4873 #define DROP_ALL (DROP_UNBOUND | \
4878 i915_drop_caches_get(void *data
, u64
*val
)
4886 i915_drop_caches_set(void *data
, u64 val
)
4888 struct drm_device
*dev
= data
;
4889 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4892 DRM_DEBUG("Dropping caches: 0x%08llx\n", val
);
4894 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4895 * on ioctls on -EAGAIN. */
4896 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4900 if (val
& DROP_ACTIVE
) {
4901 ret
= i915_gpu_idle(dev
);
4906 if (val
& (DROP_RETIRE
| DROP_ACTIVE
))
4907 i915_gem_retire_requests(dev
);
4909 if (val
& DROP_BOUND
)
4910 i915_gem_shrink(dev_priv
, LONG_MAX
, I915_SHRINK_BOUND
);
4912 if (val
& DROP_UNBOUND
)
4913 i915_gem_shrink(dev_priv
, LONG_MAX
, I915_SHRINK_UNBOUND
);
4916 mutex_unlock(&dev
->struct_mutex
);
4921 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops
,
4922 i915_drop_caches_get
, i915_drop_caches_set
,
4926 i915_max_freq_get(void *data
, u64
*val
)
4928 struct drm_device
*dev
= data
;
4929 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4932 if (INTEL_INFO(dev
)->gen
< 6)
4935 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4937 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4941 *val
= intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq_softlimit
);
4942 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4948 i915_max_freq_set(void *data
, u64 val
)
4950 struct drm_device
*dev
= data
;
4951 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4955 if (INTEL_INFO(dev
)->gen
< 6)
4958 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4960 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val
);
4962 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4967 * Turbo will still be enabled, but won't go above the set value.
4969 val
= intel_freq_opcode(dev_priv
, val
);
4971 hw_max
= dev_priv
->rps
.max_freq
;
4972 hw_min
= dev_priv
->rps
.min_freq
;
4974 if (val
< hw_min
|| val
> hw_max
|| val
< dev_priv
->rps
.min_freq_softlimit
) {
4975 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4979 dev_priv
->rps
.max_freq_softlimit
= val
;
4981 intel_set_rps(dev
, val
);
4983 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4988 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops
,
4989 i915_max_freq_get
, i915_max_freq_set
,
4993 i915_min_freq_get(void *data
, u64
*val
)
4995 struct drm_device
*dev
= data
;
4996 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4999 if (INTEL_INFO(dev
)->gen
< 6)
5002 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
5004 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
5008 *val
= intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq_softlimit
);
5009 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5015 i915_min_freq_set(void *data
, u64 val
)
5017 struct drm_device
*dev
= data
;
5018 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5022 if (INTEL_INFO(dev
)->gen
< 6)
5025 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
5027 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val
);
5029 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
5034 * Turbo will still be enabled, but won't go below the set value.
5036 val
= intel_freq_opcode(dev_priv
, val
);
5038 hw_max
= dev_priv
->rps
.max_freq
;
5039 hw_min
= dev_priv
->rps
.min_freq
;
5041 if (val
< hw_min
|| val
> hw_max
|| val
> dev_priv
->rps
.max_freq_softlimit
) {
5042 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5046 dev_priv
->rps
.min_freq_softlimit
= val
;
5048 intel_set_rps(dev
, val
);
5050 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5055 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops
,
5056 i915_min_freq_get
, i915_min_freq_set
,
5060 i915_cache_sharing_get(void *data
, u64
*val
)
5062 struct drm_device
*dev
= data
;
5063 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5067 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
5070 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
5073 intel_runtime_pm_get(dev_priv
);
5075 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
5077 intel_runtime_pm_put(dev_priv
);
5078 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
5080 *val
= (snpcr
& GEN6_MBC_SNPCR_MASK
) >> GEN6_MBC_SNPCR_SHIFT
;
5086 i915_cache_sharing_set(void *data
, u64 val
)
5088 struct drm_device
*dev
= data
;
5089 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5092 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
5098 intel_runtime_pm_get(dev_priv
);
5099 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val
);
5101 /* Update the cache sharing policy here as well */
5102 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
5103 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
5104 snpcr
|= (val
<< GEN6_MBC_SNPCR_SHIFT
);
5105 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
5107 intel_runtime_pm_put(dev_priv
);
5111 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops
,
5112 i915_cache_sharing_get
, i915_cache_sharing_set
,
5115 struct sseu_dev_status
{
5116 unsigned int slice_total
;
5117 unsigned int subslice_total
;
5118 unsigned int subslice_per_slice
;
5119 unsigned int eu_total
;
5120 unsigned int eu_per_subslice
;
5123 static void cherryview_sseu_device_status(struct drm_device
*dev
,
5124 struct sseu_dev_status
*stat
)
5126 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5129 u32 sig1
[ss_max
], sig2
[ss_max
];
5131 sig1
[0] = I915_READ(CHV_POWER_SS0_SIG1
);
5132 sig1
[1] = I915_READ(CHV_POWER_SS1_SIG1
);
5133 sig2
[0] = I915_READ(CHV_POWER_SS0_SIG2
);
5134 sig2
[1] = I915_READ(CHV_POWER_SS1_SIG2
);
5136 for (ss
= 0; ss
< ss_max
; ss
++) {
5137 unsigned int eu_cnt
;
5139 if (sig1
[ss
] & CHV_SS_PG_ENABLE
)
5140 /* skip disabled subslice */
5143 stat
->slice_total
= 1;
5144 stat
->subslice_per_slice
++;
5145 eu_cnt
= ((sig1
[ss
] & CHV_EU08_PG_ENABLE
) ? 0 : 2) +
5146 ((sig1
[ss
] & CHV_EU19_PG_ENABLE
) ? 0 : 2) +
5147 ((sig1
[ss
] & CHV_EU210_PG_ENABLE
) ? 0 : 2) +
5148 ((sig2
[ss
] & CHV_EU311_PG_ENABLE
) ? 0 : 2);
5149 stat
->eu_total
+= eu_cnt
;
5150 stat
->eu_per_subslice
= max(stat
->eu_per_subslice
, eu_cnt
);
5152 stat
->subslice_total
= stat
->subslice_per_slice
;
5155 static void gen9_sseu_device_status(struct drm_device
*dev
,
5156 struct sseu_dev_status
*stat
)
5158 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5159 int s_max
= 3, ss_max
= 4;
5161 u32 s_reg
[s_max
], eu_reg
[2*s_max
], eu_mask
[2];
5163 /* BXT has a single slice and at most 3 subslices. */
5164 if (IS_BROXTON(dev
)) {
5169 for (s
= 0; s
< s_max
; s
++) {
5170 s_reg
[s
] = I915_READ(GEN9_SLICE_PGCTL_ACK(s
));
5171 eu_reg
[2*s
] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s
));
5172 eu_reg
[2*s
+ 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s
));
5175 eu_mask
[0] = GEN9_PGCTL_SSA_EU08_ACK
|
5176 GEN9_PGCTL_SSA_EU19_ACK
|
5177 GEN9_PGCTL_SSA_EU210_ACK
|
5178 GEN9_PGCTL_SSA_EU311_ACK
;
5179 eu_mask
[1] = GEN9_PGCTL_SSB_EU08_ACK
|
5180 GEN9_PGCTL_SSB_EU19_ACK
|
5181 GEN9_PGCTL_SSB_EU210_ACK
|
5182 GEN9_PGCTL_SSB_EU311_ACK
;
5184 for (s
= 0; s
< s_max
; s
++) {
5185 unsigned int ss_cnt
= 0;
5187 if ((s_reg
[s
] & GEN9_PGCTL_SLICE_ACK
) == 0)
5188 /* skip disabled slice */
5191 stat
->slice_total
++;
5193 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
))
5194 ss_cnt
= INTEL_INFO(dev
)->subslice_per_slice
;
5196 for (ss
= 0; ss
< ss_max
; ss
++) {
5197 unsigned int eu_cnt
;
5199 if (IS_BROXTON(dev
) &&
5200 !(s_reg
[s
] & (GEN9_PGCTL_SS_ACK(ss
))))
5201 /* skip disabled subslice */
5204 if (IS_BROXTON(dev
))
5207 eu_cnt
= 2 * hweight32(eu_reg
[2*s
+ ss
/2] &
5209 stat
->eu_total
+= eu_cnt
;
5210 stat
->eu_per_subslice
= max(stat
->eu_per_subslice
,
5214 stat
->subslice_total
+= ss_cnt
;
5215 stat
->subslice_per_slice
= max(stat
->subslice_per_slice
,
5220 static void broadwell_sseu_device_status(struct drm_device
*dev
,
5221 struct sseu_dev_status
*stat
)
5223 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5225 u32 slice_info
= I915_READ(GEN8_GT_SLICE_INFO
);
5227 stat
->slice_total
= hweight32(slice_info
& GEN8_LSLICESTAT_MASK
);
5229 if (stat
->slice_total
) {
5230 stat
->subslice_per_slice
= INTEL_INFO(dev
)->subslice_per_slice
;
5231 stat
->subslice_total
= stat
->slice_total
*
5232 stat
->subslice_per_slice
;
5233 stat
->eu_per_subslice
= INTEL_INFO(dev
)->eu_per_subslice
;
5234 stat
->eu_total
= stat
->eu_per_subslice
* stat
->subslice_total
;
5236 /* subtract fused off EU(s) from enabled slice(s) */
5237 for (s
= 0; s
< stat
->slice_total
; s
++) {
5238 u8 subslice_7eu
= INTEL_INFO(dev
)->subslice_7eu
[s
];
5240 stat
->eu_total
-= hweight8(subslice_7eu
);
5245 static int i915_sseu_status(struct seq_file
*m
, void *unused
)
5247 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
5248 struct drm_device
*dev
= node
->minor
->dev
;
5249 struct sseu_dev_status stat
;
5251 if (INTEL_INFO(dev
)->gen
< 8)
5254 seq_puts(m
, "SSEU Device Info\n");
5255 seq_printf(m
, " Available Slice Total: %u\n",
5256 INTEL_INFO(dev
)->slice_total
);
5257 seq_printf(m
, " Available Subslice Total: %u\n",
5258 INTEL_INFO(dev
)->subslice_total
);
5259 seq_printf(m
, " Available Subslice Per Slice: %u\n",
5260 INTEL_INFO(dev
)->subslice_per_slice
);
5261 seq_printf(m
, " Available EU Total: %u\n",
5262 INTEL_INFO(dev
)->eu_total
);
5263 seq_printf(m
, " Available EU Per Subslice: %u\n",
5264 INTEL_INFO(dev
)->eu_per_subslice
);
5265 seq_printf(m
, " Has Slice Power Gating: %s\n",
5266 yesno(INTEL_INFO(dev
)->has_slice_pg
));
5267 seq_printf(m
, " Has Subslice Power Gating: %s\n",
5268 yesno(INTEL_INFO(dev
)->has_subslice_pg
));
5269 seq_printf(m
, " Has EU Power Gating: %s\n",
5270 yesno(INTEL_INFO(dev
)->has_eu_pg
));
5272 seq_puts(m
, "SSEU Device Status\n");
5273 memset(&stat
, 0, sizeof(stat
));
5274 if (IS_CHERRYVIEW(dev
)) {
5275 cherryview_sseu_device_status(dev
, &stat
);
5276 } else if (IS_BROADWELL(dev
)) {
5277 broadwell_sseu_device_status(dev
, &stat
);
5278 } else if (INTEL_INFO(dev
)->gen
>= 9) {
5279 gen9_sseu_device_status(dev
, &stat
);
5281 seq_printf(m
, " Enabled Slice Total: %u\n",
5283 seq_printf(m
, " Enabled Subslice Total: %u\n",
5284 stat
.subslice_total
);
5285 seq_printf(m
, " Enabled Subslice Per Slice: %u\n",
5286 stat
.subslice_per_slice
);
5287 seq_printf(m
, " Enabled EU Total: %u\n",
5289 seq_printf(m
, " Enabled EU Per Subslice: %u\n",
5290 stat
.eu_per_subslice
);
5295 static int i915_forcewake_open(struct inode
*inode
, struct file
*file
)
5297 struct drm_device
*dev
= inode
->i_private
;
5298 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5300 if (INTEL_INFO(dev
)->gen
< 6)
5303 intel_runtime_pm_get(dev_priv
);
5304 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5309 static int i915_forcewake_release(struct inode
*inode
, struct file
*file
)
5311 struct drm_device
*dev
= inode
->i_private
;
5312 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5314 if (INTEL_INFO(dev
)->gen
< 6)
5317 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5318 intel_runtime_pm_put(dev_priv
);
5323 static const struct file_operations i915_forcewake_fops
= {
5324 .owner
= THIS_MODULE
,
5325 .open
= i915_forcewake_open
,
5326 .release
= i915_forcewake_release
,
5329 static int i915_forcewake_create(struct dentry
*root
, struct drm_minor
*minor
)
5331 struct drm_device
*dev
= minor
->dev
;
5334 ent
= debugfs_create_file("i915_forcewake_user",
5337 &i915_forcewake_fops
);
5341 return drm_add_fake_info_node(minor
, ent
, &i915_forcewake_fops
);
5344 static int i915_debugfs_create(struct dentry
*root
,
5345 struct drm_minor
*minor
,
5347 const struct file_operations
*fops
)
5349 struct drm_device
*dev
= minor
->dev
;
5352 ent
= debugfs_create_file(name
,
5359 return drm_add_fake_info_node(minor
, ent
, fops
);
5362 static const struct drm_info_list i915_debugfs_list
[] = {
5363 {"i915_capabilities", i915_capabilities
, 0},
5364 {"i915_gem_objects", i915_gem_object_info
, 0},
5365 {"i915_gem_gtt", i915_gem_gtt_info
, 0},
5366 {"i915_gem_pinned", i915_gem_gtt_info
, 0, (void *) PINNED_LIST
},
5367 {"i915_gem_active", i915_gem_object_list_info
, 0, (void *) ACTIVE_LIST
},
5368 {"i915_gem_inactive", i915_gem_object_list_info
, 0, (void *) INACTIVE_LIST
},
5369 {"i915_gem_stolen", i915_gem_stolen_list_info
},
5370 {"i915_gem_pageflip", i915_gem_pageflip_info
, 0},
5371 {"i915_gem_request", i915_gem_request_info
, 0},
5372 {"i915_gem_seqno", i915_gem_seqno_info
, 0},
5373 {"i915_gem_fence_regs", i915_gem_fence_regs_info
, 0},
5374 {"i915_gem_interrupt", i915_interrupt_info
, 0},
5375 {"i915_gem_hws", i915_hws_info
, 0, (void *)RCS
},
5376 {"i915_gem_hws_blt", i915_hws_info
, 0, (void *)BCS
},
5377 {"i915_gem_hws_bsd", i915_hws_info
, 0, (void *)VCS
},
5378 {"i915_gem_hws_vebox", i915_hws_info
, 0, (void *)VECS
},
5379 {"i915_gem_batch_pool", i915_gem_batch_pool_info
, 0},
5380 {"i915_guc_info", i915_guc_info
, 0},
5381 {"i915_guc_load_status", i915_guc_load_status_info
, 0},
5382 {"i915_guc_log_dump", i915_guc_log_dump
, 0},
5383 {"i915_frequency_info", i915_frequency_info
, 0},
5384 {"i915_hangcheck_info", i915_hangcheck_info
, 0},
5385 {"i915_drpc_info", i915_drpc_info
, 0},
5386 {"i915_emon_status", i915_emon_status
, 0},
5387 {"i915_ring_freq_table", i915_ring_freq_table
, 0},
5388 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking
, 0},
5389 {"i915_fbc_status", i915_fbc_status
, 0},
5390 {"i915_ips_status", i915_ips_status
, 0},
5391 {"i915_sr_status", i915_sr_status
, 0},
5392 {"i915_opregion", i915_opregion
, 0},
5393 {"i915_vbt", i915_vbt
, 0},
5394 {"i915_gem_framebuffer", i915_gem_framebuffer_info
, 0},
5395 {"i915_context_status", i915_context_status
, 0},
5396 {"i915_dump_lrc", i915_dump_lrc
, 0},
5397 {"i915_execlists", i915_execlists
, 0},
5398 {"i915_forcewake_domains", i915_forcewake_domains
, 0},
5399 {"i915_swizzle_info", i915_swizzle_info
, 0},
5400 {"i915_ppgtt_info", i915_ppgtt_info
, 0},
5401 {"i915_llc", i915_llc
, 0},
5402 {"i915_edp_psr_status", i915_edp_psr_status
, 0},
5403 {"i915_sink_crc_eDP1", i915_sink_crc
, 0},
5404 {"i915_energy_uJ", i915_energy_uJ
, 0},
5405 {"i915_runtime_pm_status", i915_runtime_pm_status
, 0},
5406 {"i915_power_domain_info", i915_power_domain_info
, 0},
5407 {"i915_dmc_info", i915_dmc_info
, 0},
5408 {"i915_display_info", i915_display_info
, 0},
5409 {"i915_semaphore_status", i915_semaphore_status
, 0},
5410 {"i915_shared_dplls_info", i915_shared_dplls_info
, 0},
5411 {"i915_dp_mst_info", i915_dp_mst_info
, 0},
5412 {"i915_wa_registers", i915_wa_registers
, 0},
5413 {"i915_ddb_info", i915_ddb_info
, 0},
5414 {"i915_sseu_status", i915_sseu_status
, 0},
5415 {"i915_drrs_status", i915_drrs_status
, 0},
5416 {"i915_rps_boost_info", i915_rps_boost_info
, 0},
5418 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5420 static const struct i915_debugfs_files
{
5422 const struct file_operations
*fops
;
5423 } i915_debugfs_files
[] = {
5424 {"i915_wedged", &i915_wedged_fops
},
5425 {"i915_max_freq", &i915_max_freq_fops
},
5426 {"i915_min_freq", &i915_min_freq_fops
},
5427 {"i915_cache_sharing", &i915_cache_sharing_fops
},
5428 {"i915_ring_stop", &i915_ring_stop_fops
},
5429 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops
},
5430 {"i915_ring_test_irq", &i915_ring_test_irq_fops
},
5431 {"i915_gem_drop_caches", &i915_drop_caches_fops
},
5432 {"i915_error_state", &i915_error_state_fops
},
5433 {"i915_next_seqno", &i915_next_seqno_fops
},
5434 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops
},
5435 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops
},
5436 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops
},
5437 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops
},
5438 {"i915_fbc_false_color", &i915_fbc_fc_fops
},
5439 {"i915_dp_test_data", &i915_displayport_test_data_fops
},
5440 {"i915_dp_test_type", &i915_displayport_test_type_fops
},
5441 {"i915_dp_test_active", &i915_displayport_test_active_fops
}
5444 void intel_display_crc_init(struct drm_device
*dev
)
5446 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5449 for_each_pipe(dev_priv
, pipe
) {
5450 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
5452 pipe_crc
->opened
= false;
5453 spin_lock_init(&pipe_crc
->lock
);
5454 init_waitqueue_head(&pipe_crc
->wq
);
5458 int i915_debugfs_init(struct drm_minor
*minor
)
5462 ret
= i915_forcewake_create(minor
->debugfs_root
, minor
);
5466 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
5467 ret
= i915_pipe_crc_create(minor
->debugfs_root
, minor
, i
);
5472 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
5473 ret
= i915_debugfs_create(minor
->debugfs_root
, minor
,
5474 i915_debugfs_files
[i
].name
,
5475 i915_debugfs_files
[i
].fops
);
5480 return drm_debugfs_create_files(i915_debugfs_list
,
5481 I915_DEBUGFS_ENTRIES
,
5482 minor
->debugfs_root
, minor
);
5485 void i915_debugfs_cleanup(struct drm_minor
*minor
)
5489 drm_debugfs_remove_files(i915_debugfs_list
,
5490 I915_DEBUGFS_ENTRIES
, minor
);
5492 drm_debugfs_remove_files((struct drm_info_list
*) &i915_forcewake_fops
,
5495 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
5496 struct drm_info_list
*info_list
=
5497 (struct drm_info_list
*)&i915_pipe_crc_data
[i
];
5499 drm_debugfs_remove_files(info_list
, 1, minor
);
5502 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
5503 struct drm_info_list
*info_list
=
5504 (struct drm_info_list
*) i915_debugfs_files
[i
].fops
;
5506 drm_debugfs_remove_files(info_list
, 1, minor
);
5511 /* DPCD dump start address. */
5512 unsigned int offset
;
5513 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5515 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5517 /* Only valid for eDP. */
5521 static const struct dpcd_block i915_dpcd_debug
[] = {
5522 { .offset
= DP_DPCD_REV
, .size
= DP_RECEIVER_CAP_SIZE
},
5523 { .offset
= DP_PSR_SUPPORT
, .end
= DP_PSR_CAPS
},
5524 { .offset
= DP_DOWNSTREAM_PORT_0
, .size
= 16 },
5525 { .offset
= DP_LINK_BW_SET
, .end
= DP_EDP_CONFIGURATION_SET
},
5526 { .offset
= DP_SINK_COUNT
, .end
= DP_ADJUST_REQUEST_LANE2_3
},
5527 { .offset
= DP_SET_POWER
},
5528 { .offset
= DP_EDP_DPCD_REV
},
5529 { .offset
= DP_EDP_GENERAL_CAP_1
, .end
= DP_EDP_GENERAL_CAP_3
},
5530 { .offset
= DP_EDP_DISPLAY_CONTROL_REGISTER
, .end
= DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB
},
5531 { .offset
= DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET
, .end
= DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET
},
5534 static int i915_dpcd_show(struct seq_file
*m
, void *data
)
5536 struct drm_connector
*connector
= m
->private;
5537 struct intel_dp
*intel_dp
=
5538 enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
5543 if (connector
->status
!= connector_status_connected
)
5546 for (i
= 0; i
< ARRAY_SIZE(i915_dpcd_debug
); i
++) {
5547 const struct dpcd_block
*b
= &i915_dpcd_debug
[i
];
5548 size_t size
= b
->end
? b
->end
- b
->offset
+ 1 : (b
->size
?: 1);
5551 connector
->connector_type
!= DRM_MODE_CONNECTOR_eDP
)
5554 /* low tech for now */
5555 if (WARN_ON(size
> sizeof(buf
)))
5558 err
= drm_dp_dpcd_read(&intel_dp
->aux
, b
->offset
, buf
, size
);
5560 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5561 size
, b
->offset
, err
);
5565 seq_printf(m
, "%04x: %*ph\n", b
->offset
, (int) size
, buf
);
5571 static int i915_dpcd_open(struct inode
*inode
, struct file
*file
)
5573 return single_open(file
, i915_dpcd_show
, inode
->i_private
);
5576 static const struct file_operations i915_dpcd_fops
= {
5577 .owner
= THIS_MODULE
,
5578 .open
= i915_dpcd_open
,
5580 .llseek
= seq_lseek
,
5581 .release
= single_release
,
5585 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5586 * @connector: pointer to a registered drm_connector
5588 * Cleanup will be done by drm_connector_unregister() through a call to
5589 * drm_debugfs_connector_remove().
5591 * Returns 0 on success, negative error codes on error.
5593 int i915_debugfs_connector_add(struct drm_connector
*connector
)
5595 struct dentry
*root
= connector
->debugfs_entry
;
5597 /* The connector must have been registered beforehands. */
5601 if (connector
->connector_type
== DRM_MODE_CONNECTOR_DisplayPort
||
5602 connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
5603 debugfs_create_file("i915_dpcd", S_IRUGO
, root
, connector
,