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drm/i915: get/put runtime PM at i915_semaphore_status
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
37 #include <drm/drmP.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
41 #include "i915_drv.h"
42
43 enum {
44 ACTIVE_LIST,
45 INACTIVE_LIST,
46 PINNED_LIST,
47 };
48
49 static const char *yesno(int v)
50 {
51 return v ? "yes" : "no";
52 }
53
54 /* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
56 static int
57 drm_add_fake_info_node(struct drm_minor *minor,
58 struct dentry *ent,
59 const void *key)
60 {
61 struct drm_info_node *node;
62
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
64 if (node == NULL) {
65 debugfs_remove(ent);
66 return -ENOMEM;
67 }
68
69 node->minor = minor;
70 node->dent = ent;
71 node->info_ent = (void *) key;
72
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
76
77 return 0;
78 }
79
80 static int i915_capabilities(struct seq_file *m, void *data)
81 {
82 struct drm_info_node *node = m->private;
83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
85
86 seq_printf(m, "gen: %d\n", info->gen);
87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
88 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89 #define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
91 #undef PRINT_FLAG
92 #undef SEP_SEMICOLON
93
94 return 0;
95 }
96
97 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
98 {
99 if (obj->user_pin_count > 0)
100 return "P";
101 else if (i915_gem_obj_is_pinned(obj))
102 return "p";
103 else
104 return " ";
105 }
106
107 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
108 {
109 switch (obj->tiling_mode) {
110 default:
111 case I915_TILING_NONE: return " ";
112 case I915_TILING_X: return "X";
113 case I915_TILING_Y: return "Y";
114 }
115 }
116
117 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
118 {
119 return obj->has_global_gtt_mapping ? "g" : " ";
120 }
121
122 static void
123 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
124 {
125 struct i915_vma *vma;
126 int pin_count = 0;
127
128 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
129 &obj->base,
130 get_pin_flag(obj),
131 get_tiling_flag(obj),
132 get_global_flag(obj),
133 obj->base.size / 1024,
134 obj->base.read_domains,
135 obj->base.write_domain,
136 obj->last_read_seqno,
137 obj->last_write_seqno,
138 obj->last_fenced_seqno,
139 i915_cache_level_str(obj->cache_level),
140 obj->dirty ? " dirty" : "",
141 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
142 if (obj->base.name)
143 seq_printf(m, " (name: %d)", obj->base.name);
144 list_for_each_entry(vma, &obj->vma_list, vma_link)
145 if (vma->pin_count > 0)
146 pin_count++;
147 seq_printf(m, " (pinned x %d)", pin_count);
148 if (obj->pin_display)
149 seq_printf(m, " (display)");
150 if (obj->fence_reg != I915_FENCE_REG_NONE)
151 seq_printf(m, " (fence: %d)", obj->fence_reg);
152 list_for_each_entry(vma, &obj->vma_list, vma_link) {
153 if (!i915_is_ggtt(vma->vm))
154 seq_puts(m, " (pp");
155 else
156 seq_puts(m, " (g");
157 seq_printf(m, "gtt offset: %08lx, size: %08lx)",
158 vma->node.start, vma->node.size);
159 }
160 if (obj->stolen)
161 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
162 if (obj->pin_mappable || obj->fault_mappable) {
163 char s[3], *t = s;
164 if (obj->pin_mappable)
165 *t++ = 'p';
166 if (obj->fault_mappable)
167 *t++ = 'f';
168 *t = '\0';
169 seq_printf(m, " (%s mappable)", s);
170 }
171 if (obj->ring != NULL)
172 seq_printf(m, " (%s)", obj->ring->name);
173 if (obj->frontbuffer_bits)
174 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
175 }
176
177 static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
178 {
179 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
180 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
181 seq_putc(m, ' ');
182 }
183
184 static int i915_gem_object_list_info(struct seq_file *m, void *data)
185 {
186 struct drm_info_node *node = m->private;
187 uintptr_t list = (uintptr_t) node->info_ent->data;
188 struct list_head *head;
189 struct drm_device *dev = node->minor->dev;
190 struct drm_i915_private *dev_priv = dev->dev_private;
191 struct i915_address_space *vm = &dev_priv->gtt.base;
192 struct i915_vma *vma;
193 size_t total_obj_size, total_gtt_size;
194 int count, ret;
195
196 ret = mutex_lock_interruptible(&dev->struct_mutex);
197 if (ret)
198 return ret;
199
200 /* FIXME: the user of this interface might want more than just GGTT */
201 switch (list) {
202 case ACTIVE_LIST:
203 seq_puts(m, "Active:\n");
204 head = &vm->active_list;
205 break;
206 case INACTIVE_LIST:
207 seq_puts(m, "Inactive:\n");
208 head = &vm->inactive_list;
209 break;
210 default:
211 mutex_unlock(&dev->struct_mutex);
212 return -EINVAL;
213 }
214
215 total_obj_size = total_gtt_size = count = 0;
216 list_for_each_entry(vma, head, mm_list) {
217 seq_printf(m, " ");
218 describe_obj(m, vma->obj);
219 seq_printf(m, "\n");
220 total_obj_size += vma->obj->base.size;
221 total_gtt_size += vma->node.size;
222 count++;
223 }
224 mutex_unlock(&dev->struct_mutex);
225
226 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
227 count, total_obj_size, total_gtt_size);
228 return 0;
229 }
230
231 static int obj_rank_by_stolen(void *priv,
232 struct list_head *A, struct list_head *B)
233 {
234 struct drm_i915_gem_object *a =
235 container_of(A, struct drm_i915_gem_object, obj_exec_link);
236 struct drm_i915_gem_object *b =
237 container_of(B, struct drm_i915_gem_object, obj_exec_link);
238
239 return a->stolen->start - b->stolen->start;
240 }
241
242 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
243 {
244 struct drm_info_node *node = m->private;
245 struct drm_device *dev = node->minor->dev;
246 struct drm_i915_private *dev_priv = dev->dev_private;
247 struct drm_i915_gem_object *obj;
248 size_t total_obj_size, total_gtt_size;
249 LIST_HEAD(stolen);
250 int count, ret;
251
252 ret = mutex_lock_interruptible(&dev->struct_mutex);
253 if (ret)
254 return ret;
255
256 total_obj_size = total_gtt_size = count = 0;
257 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
258 if (obj->stolen == NULL)
259 continue;
260
261 list_add(&obj->obj_exec_link, &stolen);
262
263 total_obj_size += obj->base.size;
264 total_gtt_size += i915_gem_obj_ggtt_size(obj);
265 count++;
266 }
267 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
268 if (obj->stolen == NULL)
269 continue;
270
271 list_add(&obj->obj_exec_link, &stolen);
272
273 total_obj_size += obj->base.size;
274 count++;
275 }
276 list_sort(NULL, &stolen, obj_rank_by_stolen);
277 seq_puts(m, "Stolen:\n");
278 while (!list_empty(&stolen)) {
279 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
280 seq_puts(m, " ");
281 describe_obj(m, obj);
282 seq_putc(m, '\n');
283 list_del_init(&obj->obj_exec_link);
284 }
285 mutex_unlock(&dev->struct_mutex);
286
287 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
288 count, total_obj_size, total_gtt_size);
289 return 0;
290 }
291
292 #define count_objects(list, member) do { \
293 list_for_each_entry(obj, list, member) { \
294 size += i915_gem_obj_ggtt_size(obj); \
295 ++count; \
296 if (obj->map_and_fenceable) { \
297 mappable_size += i915_gem_obj_ggtt_size(obj); \
298 ++mappable_count; \
299 } \
300 } \
301 } while (0)
302
303 struct file_stats {
304 struct drm_i915_file_private *file_priv;
305 int count;
306 size_t total, unbound;
307 size_t global, shared;
308 size_t active, inactive;
309 };
310
311 static int per_file_stats(int id, void *ptr, void *data)
312 {
313 struct drm_i915_gem_object *obj = ptr;
314 struct file_stats *stats = data;
315 struct i915_vma *vma;
316
317 stats->count++;
318 stats->total += obj->base.size;
319
320 if (obj->base.name || obj->base.dma_buf)
321 stats->shared += obj->base.size;
322
323 if (USES_FULL_PPGTT(obj->base.dev)) {
324 list_for_each_entry(vma, &obj->vma_list, vma_link) {
325 struct i915_hw_ppgtt *ppgtt;
326
327 if (!drm_mm_node_allocated(&vma->node))
328 continue;
329
330 if (i915_is_ggtt(vma->vm)) {
331 stats->global += obj->base.size;
332 continue;
333 }
334
335 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
336 if (ppgtt->ctx && ppgtt->ctx->file_priv != stats->file_priv)
337 continue;
338
339 if (obj->ring) /* XXX per-vma statistic */
340 stats->active += obj->base.size;
341 else
342 stats->inactive += obj->base.size;
343
344 return 0;
345 }
346 } else {
347 if (i915_gem_obj_ggtt_bound(obj)) {
348 stats->global += obj->base.size;
349 if (obj->ring)
350 stats->active += obj->base.size;
351 else
352 stats->inactive += obj->base.size;
353 return 0;
354 }
355 }
356
357 if (!list_empty(&obj->global_list))
358 stats->unbound += obj->base.size;
359
360 return 0;
361 }
362
363 #define count_vmas(list, member) do { \
364 list_for_each_entry(vma, list, member) { \
365 size += i915_gem_obj_ggtt_size(vma->obj); \
366 ++count; \
367 if (vma->obj->map_and_fenceable) { \
368 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
369 ++mappable_count; \
370 } \
371 } \
372 } while (0)
373
374 static int i915_gem_object_info(struct seq_file *m, void* data)
375 {
376 struct drm_info_node *node = m->private;
377 struct drm_device *dev = node->minor->dev;
378 struct drm_i915_private *dev_priv = dev->dev_private;
379 u32 count, mappable_count, purgeable_count;
380 size_t size, mappable_size, purgeable_size;
381 struct drm_i915_gem_object *obj;
382 struct i915_address_space *vm = &dev_priv->gtt.base;
383 struct drm_file *file;
384 struct i915_vma *vma;
385 int ret;
386
387 ret = mutex_lock_interruptible(&dev->struct_mutex);
388 if (ret)
389 return ret;
390
391 seq_printf(m, "%u objects, %zu bytes\n",
392 dev_priv->mm.object_count,
393 dev_priv->mm.object_memory);
394
395 size = count = mappable_size = mappable_count = 0;
396 count_objects(&dev_priv->mm.bound_list, global_list);
397 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
398 count, mappable_count, size, mappable_size);
399
400 size = count = mappable_size = mappable_count = 0;
401 count_vmas(&vm->active_list, mm_list);
402 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
403 count, mappable_count, size, mappable_size);
404
405 size = count = mappable_size = mappable_count = 0;
406 count_vmas(&vm->inactive_list, mm_list);
407 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
408 count, mappable_count, size, mappable_size);
409
410 size = count = purgeable_size = purgeable_count = 0;
411 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
412 size += obj->base.size, ++count;
413 if (obj->madv == I915_MADV_DONTNEED)
414 purgeable_size += obj->base.size, ++purgeable_count;
415 }
416 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
417
418 size = count = mappable_size = mappable_count = 0;
419 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
420 if (obj->fault_mappable) {
421 size += i915_gem_obj_ggtt_size(obj);
422 ++count;
423 }
424 if (obj->pin_mappable) {
425 mappable_size += i915_gem_obj_ggtt_size(obj);
426 ++mappable_count;
427 }
428 if (obj->madv == I915_MADV_DONTNEED) {
429 purgeable_size += obj->base.size;
430 ++purgeable_count;
431 }
432 }
433 seq_printf(m, "%u purgeable objects, %zu bytes\n",
434 purgeable_count, purgeable_size);
435 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
436 mappable_count, mappable_size);
437 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
438 count, size);
439
440 seq_printf(m, "%zu [%lu] gtt total\n",
441 dev_priv->gtt.base.total,
442 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
443
444 seq_putc(m, '\n');
445 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
446 struct file_stats stats;
447 struct task_struct *task;
448
449 memset(&stats, 0, sizeof(stats));
450 stats.file_priv = file->driver_priv;
451 spin_lock(&file->table_lock);
452 idr_for_each(&file->object_idr, per_file_stats, &stats);
453 spin_unlock(&file->table_lock);
454 /*
455 * Although we have a valid reference on file->pid, that does
456 * not guarantee that the task_struct who called get_pid() is
457 * still alive (e.g. get_pid(current) => fork() => exit()).
458 * Therefore, we need to protect this ->comm access using RCU.
459 */
460 rcu_read_lock();
461 task = pid_task(file->pid, PIDTYPE_PID);
462 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n",
463 task ? task->comm : "<unknown>",
464 stats.count,
465 stats.total,
466 stats.active,
467 stats.inactive,
468 stats.global,
469 stats.shared,
470 stats.unbound);
471 rcu_read_unlock();
472 }
473
474 mutex_unlock(&dev->struct_mutex);
475
476 return 0;
477 }
478
479 static int i915_gem_gtt_info(struct seq_file *m, void *data)
480 {
481 struct drm_info_node *node = m->private;
482 struct drm_device *dev = node->minor->dev;
483 uintptr_t list = (uintptr_t) node->info_ent->data;
484 struct drm_i915_private *dev_priv = dev->dev_private;
485 struct drm_i915_gem_object *obj;
486 size_t total_obj_size, total_gtt_size;
487 int count, ret;
488
489 ret = mutex_lock_interruptible(&dev->struct_mutex);
490 if (ret)
491 return ret;
492
493 total_obj_size = total_gtt_size = count = 0;
494 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
495 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
496 continue;
497
498 seq_puts(m, " ");
499 describe_obj(m, obj);
500 seq_putc(m, '\n');
501 total_obj_size += obj->base.size;
502 total_gtt_size += i915_gem_obj_ggtt_size(obj);
503 count++;
504 }
505
506 mutex_unlock(&dev->struct_mutex);
507
508 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
509 count, total_obj_size, total_gtt_size);
510
511 return 0;
512 }
513
514 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
515 {
516 struct drm_info_node *node = m->private;
517 struct drm_device *dev = node->minor->dev;
518 unsigned long flags;
519 struct intel_crtc *crtc;
520 int ret;
521
522 ret = mutex_lock_interruptible(&dev->struct_mutex);
523 if (ret)
524 return ret;
525
526 for_each_intel_crtc(dev, crtc) {
527 const char pipe = pipe_name(crtc->pipe);
528 const char plane = plane_name(crtc->plane);
529 struct intel_unpin_work *work;
530
531 spin_lock_irqsave(&dev->event_lock, flags);
532 work = crtc->unpin_work;
533 if (work == NULL) {
534 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
535 pipe, plane);
536 } else {
537 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
538 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
539 pipe, plane);
540 } else {
541 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
542 pipe, plane);
543 }
544 if (work->enable_stall_check)
545 seq_puts(m, "Stall check enabled, ");
546 else
547 seq_puts(m, "Stall check waiting for page flip ioctl, ");
548 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
549
550 if (work->old_fb_obj) {
551 struct drm_i915_gem_object *obj = work->old_fb_obj;
552 if (obj)
553 seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n",
554 i915_gem_obj_ggtt_offset(obj));
555 }
556 if (work->pending_flip_obj) {
557 struct drm_i915_gem_object *obj = work->pending_flip_obj;
558 if (obj)
559 seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n",
560 i915_gem_obj_ggtt_offset(obj));
561 }
562 }
563 spin_unlock_irqrestore(&dev->event_lock, flags);
564 }
565
566 mutex_unlock(&dev->struct_mutex);
567
568 return 0;
569 }
570
571 static int i915_gem_request_info(struct seq_file *m, void *data)
572 {
573 struct drm_info_node *node = m->private;
574 struct drm_device *dev = node->minor->dev;
575 struct drm_i915_private *dev_priv = dev->dev_private;
576 struct intel_engine_cs *ring;
577 struct drm_i915_gem_request *gem_request;
578 int ret, count, i;
579
580 ret = mutex_lock_interruptible(&dev->struct_mutex);
581 if (ret)
582 return ret;
583
584 count = 0;
585 for_each_ring(ring, dev_priv, i) {
586 if (list_empty(&ring->request_list))
587 continue;
588
589 seq_printf(m, "%s requests:\n", ring->name);
590 list_for_each_entry(gem_request,
591 &ring->request_list,
592 list) {
593 seq_printf(m, " %d @ %d\n",
594 gem_request->seqno,
595 (int) (jiffies - gem_request->emitted_jiffies));
596 }
597 count++;
598 }
599 mutex_unlock(&dev->struct_mutex);
600
601 if (count == 0)
602 seq_puts(m, "No requests\n");
603
604 return 0;
605 }
606
607 static void i915_ring_seqno_info(struct seq_file *m,
608 struct intel_engine_cs *ring)
609 {
610 if (ring->get_seqno) {
611 seq_printf(m, "Current sequence (%s): %u\n",
612 ring->name, ring->get_seqno(ring, false));
613 }
614 }
615
616 static int i915_gem_seqno_info(struct seq_file *m, void *data)
617 {
618 struct drm_info_node *node = m->private;
619 struct drm_device *dev = node->minor->dev;
620 struct drm_i915_private *dev_priv = dev->dev_private;
621 struct intel_engine_cs *ring;
622 int ret, i;
623
624 ret = mutex_lock_interruptible(&dev->struct_mutex);
625 if (ret)
626 return ret;
627 intel_runtime_pm_get(dev_priv);
628
629 for_each_ring(ring, dev_priv, i)
630 i915_ring_seqno_info(m, ring);
631
632 intel_runtime_pm_put(dev_priv);
633 mutex_unlock(&dev->struct_mutex);
634
635 return 0;
636 }
637
638
639 static int i915_interrupt_info(struct seq_file *m, void *data)
640 {
641 struct drm_info_node *node = m->private;
642 struct drm_device *dev = node->minor->dev;
643 struct drm_i915_private *dev_priv = dev->dev_private;
644 struct intel_engine_cs *ring;
645 int ret, i, pipe;
646
647 ret = mutex_lock_interruptible(&dev->struct_mutex);
648 if (ret)
649 return ret;
650 intel_runtime_pm_get(dev_priv);
651
652 if (IS_CHERRYVIEW(dev)) {
653 int i;
654 seq_printf(m, "Master Interrupt Control:\t%08x\n",
655 I915_READ(GEN8_MASTER_IRQ));
656
657 seq_printf(m, "Display IER:\t%08x\n",
658 I915_READ(VLV_IER));
659 seq_printf(m, "Display IIR:\t%08x\n",
660 I915_READ(VLV_IIR));
661 seq_printf(m, "Display IIR_RW:\t%08x\n",
662 I915_READ(VLV_IIR_RW));
663 seq_printf(m, "Display IMR:\t%08x\n",
664 I915_READ(VLV_IMR));
665 for_each_pipe(pipe)
666 seq_printf(m, "Pipe %c stat:\t%08x\n",
667 pipe_name(pipe),
668 I915_READ(PIPESTAT(pipe)));
669
670 seq_printf(m, "Port hotplug:\t%08x\n",
671 I915_READ(PORT_HOTPLUG_EN));
672 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
673 I915_READ(VLV_DPFLIPSTAT));
674 seq_printf(m, "DPINVGTT:\t%08x\n",
675 I915_READ(DPINVGTT));
676
677 for (i = 0; i < 4; i++) {
678 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
679 i, I915_READ(GEN8_GT_IMR(i)));
680 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
681 i, I915_READ(GEN8_GT_IIR(i)));
682 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
683 i, I915_READ(GEN8_GT_IER(i)));
684 }
685
686 seq_printf(m, "PCU interrupt mask:\t%08x\n",
687 I915_READ(GEN8_PCU_IMR));
688 seq_printf(m, "PCU interrupt identity:\t%08x\n",
689 I915_READ(GEN8_PCU_IIR));
690 seq_printf(m, "PCU interrupt enable:\t%08x\n",
691 I915_READ(GEN8_PCU_IER));
692 } else if (INTEL_INFO(dev)->gen >= 8) {
693 seq_printf(m, "Master Interrupt Control:\t%08x\n",
694 I915_READ(GEN8_MASTER_IRQ));
695
696 for (i = 0; i < 4; i++) {
697 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
698 i, I915_READ(GEN8_GT_IMR(i)));
699 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
700 i, I915_READ(GEN8_GT_IIR(i)));
701 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
702 i, I915_READ(GEN8_GT_IER(i)));
703 }
704
705 for_each_pipe(pipe) {
706 seq_printf(m, "Pipe %c IMR:\t%08x\n",
707 pipe_name(pipe),
708 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
709 seq_printf(m, "Pipe %c IIR:\t%08x\n",
710 pipe_name(pipe),
711 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
712 seq_printf(m, "Pipe %c IER:\t%08x\n",
713 pipe_name(pipe),
714 I915_READ(GEN8_DE_PIPE_IER(pipe)));
715 }
716
717 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
718 I915_READ(GEN8_DE_PORT_IMR));
719 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
720 I915_READ(GEN8_DE_PORT_IIR));
721 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
722 I915_READ(GEN8_DE_PORT_IER));
723
724 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
725 I915_READ(GEN8_DE_MISC_IMR));
726 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
727 I915_READ(GEN8_DE_MISC_IIR));
728 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
729 I915_READ(GEN8_DE_MISC_IER));
730
731 seq_printf(m, "PCU interrupt mask:\t%08x\n",
732 I915_READ(GEN8_PCU_IMR));
733 seq_printf(m, "PCU interrupt identity:\t%08x\n",
734 I915_READ(GEN8_PCU_IIR));
735 seq_printf(m, "PCU interrupt enable:\t%08x\n",
736 I915_READ(GEN8_PCU_IER));
737 } else if (IS_VALLEYVIEW(dev)) {
738 seq_printf(m, "Display IER:\t%08x\n",
739 I915_READ(VLV_IER));
740 seq_printf(m, "Display IIR:\t%08x\n",
741 I915_READ(VLV_IIR));
742 seq_printf(m, "Display IIR_RW:\t%08x\n",
743 I915_READ(VLV_IIR_RW));
744 seq_printf(m, "Display IMR:\t%08x\n",
745 I915_READ(VLV_IMR));
746 for_each_pipe(pipe)
747 seq_printf(m, "Pipe %c stat:\t%08x\n",
748 pipe_name(pipe),
749 I915_READ(PIPESTAT(pipe)));
750
751 seq_printf(m, "Master IER:\t%08x\n",
752 I915_READ(VLV_MASTER_IER));
753
754 seq_printf(m, "Render IER:\t%08x\n",
755 I915_READ(GTIER));
756 seq_printf(m, "Render IIR:\t%08x\n",
757 I915_READ(GTIIR));
758 seq_printf(m, "Render IMR:\t%08x\n",
759 I915_READ(GTIMR));
760
761 seq_printf(m, "PM IER:\t\t%08x\n",
762 I915_READ(GEN6_PMIER));
763 seq_printf(m, "PM IIR:\t\t%08x\n",
764 I915_READ(GEN6_PMIIR));
765 seq_printf(m, "PM IMR:\t\t%08x\n",
766 I915_READ(GEN6_PMIMR));
767
768 seq_printf(m, "Port hotplug:\t%08x\n",
769 I915_READ(PORT_HOTPLUG_EN));
770 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
771 I915_READ(VLV_DPFLIPSTAT));
772 seq_printf(m, "DPINVGTT:\t%08x\n",
773 I915_READ(DPINVGTT));
774
775 } else if (!HAS_PCH_SPLIT(dev)) {
776 seq_printf(m, "Interrupt enable: %08x\n",
777 I915_READ(IER));
778 seq_printf(m, "Interrupt identity: %08x\n",
779 I915_READ(IIR));
780 seq_printf(m, "Interrupt mask: %08x\n",
781 I915_READ(IMR));
782 for_each_pipe(pipe)
783 seq_printf(m, "Pipe %c stat: %08x\n",
784 pipe_name(pipe),
785 I915_READ(PIPESTAT(pipe)));
786 } else {
787 seq_printf(m, "North Display Interrupt enable: %08x\n",
788 I915_READ(DEIER));
789 seq_printf(m, "North Display Interrupt identity: %08x\n",
790 I915_READ(DEIIR));
791 seq_printf(m, "North Display Interrupt mask: %08x\n",
792 I915_READ(DEIMR));
793 seq_printf(m, "South Display Interrupt enable: %08x\n",
794 I915_READ(SDEIER));
795 seq_printf(m, "South Display Interrupt identity: %08x\n",
796 I915_READ(SDEIIR));
797 seq_printf(m, "South Display Interrupt mask: %08x\n",
798 I915_READ(SDEIMR));
799 seq_printf(m, "Graphics Interrupt enable: %08x\n",
800 I915_READ(GTIER));
801 seq_printf(m, "Graphics Interrupt identity: %08x\n",
802 I915_READ(GTIIR));
803 seq_printf(m, "Graphics Interrupt mask: %08x\n",
804 I915_READ(GTIMR));
805 }
806 for_each_ring(ring, dev_priv, i) {
807 if (INTEL_INFO(dev)->gen >= 6) {
808 seq_printf(m,
809 "Graphics Interrupt mask (%s): %08x\n",
810 ring->name, I915_READ_IMR(ring));
811 }
812 i915_ring_seqno_info(m, ring);
813 }
814 intel_runtime_pm_put(dev_priv);
815 mutex_unlock(&dev->struct_mutex);
816
817 return 0;
818 }
819
820 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
821 {
822 struct drm_info_node *node = m->private;
823 struct drm_device *dev = node->minor->dev;
824 struct drm_i915_private *dev_priv = dev->dev_private;
825 int i, ret;
826
827 ret = mutex_lock_interruptible(&dev->struct_mutex);
828 if (ret)
829 return ret;
830
831 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
832 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
833 for (i = 0; i < dev_priv->num_fence_regs; i++) {
834 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
835
836 seq_printf(m, "Fence %d, pin count = %d, object = ",
837 i, dev_priv->fence_regs[i].pin_count);
838 if (obj == NULL)
839 seq_puts(m, "unused");
840 else
841 describe_obj(m, obj);
842 seq_putc(m, '\n');
843 }
844
845 mutex_unlock(&dev->struct_mutex);
846 return 0;
847 }
848
849 static int i915_hws_info(struct seq_file *m, void *data)
850 {
851 struct drm_info_node *node = m->private;
852 struct drm_device *dev = node->minor->dev;
853 struct drm_i915_private *dev_priv = dev->dev_private;
854 struct intel_engine_cs *ring;
855 const u32 *hws;
856 int i;
857
858 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
859 hws = ring->status_page.page_addr;
860 if (hws == NULL)
861 return 0;
862
863 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
864 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
865 i * 4,
866 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
867 }
868 return 0;
869 }
870
871 static ssize_t
872 i915_error_state_write(struct file *filp,
873 const char __user *ubuf,
874 size_t cnt,
875 loff_t *ppos)
876 {
877 struct i915_error_state_file_priv *error_priv = filp->private_data;
878 struct drm_device *dev = error_priv->dev;
879 int ret;
880
881 DRM_DEBUG_DRIVER("Resetting error state\n");
882
883 ret = mutex_lock_interruptible(&dev->struct_mutex);
884 if (ret)
885 return ret;
886
887 i915_destroy_error_state(dev);
888 mutex_unlock(&dev->struct_mutex);
889
890 return cnt;
891 }
892
893 static int i915_error_state_open(struct inode *inode, struct file *file)
894 {
895 struct drm_device *dev = inode->i_private;
896 struct i915_error_state_file_priv *error_priv;
897
898 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
899 if (!error_priv)
900 return -ENOMEM;
901
902 error_priv->dev = dev;
903
904 i915_error_state_get(dev, error_priv);
905
906 file->private_data = error_priv;
907
908 return 0;
909 }
910
911 static int i915_error_state_release(struct inode *inode, struct file *file)
912 {
913 struct i915_error_state_file_priv *error_priv = file->private_data;
914
915 i915_error_state_put(error_priv);
916 kfree(error_priv);
917
918 return 0;
919 }
920
921 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
922 size_t count, loff_t *pos)
923 {
924 struct i915_error_state_file_priv *error_priv = file->private_data;
925 struct drm_i915_error_state_buf error_str;
926 loff_t tmp_pos = 0;
927 ssize_t ret_count = 0;
928 int ret;
929
930 ret = i915_error_state_buf_init(&error_str, count, *pos);
931 if (ret)
932 return ret;
933
934 ret = i915_error_state_to_str(&error_str, error_priv);
935 if (ret)
936 goto out;
937
938 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
939 error_str.buf,
940 error_str.bytes);
941
942 if (ret_count < 0)
943 ret = ret_count;
944 else
945 *pos = error_str.start + ret_count;
946 out:
947 i915_error_state_buf_release(&error_str);
948 return ret ?: ret_count;
949 }
950
951 static const struct file_operations i915_error_state_fops = {
952 .owner = THIS_MODULE,
953 .open = i915_error_state_open,
954 .read = i915_error_state_read,
955 .write = i915_error_state_write,
956 .llseek = default_llseek,
957 .release = i915_error_state_release,
958 };
959
960 static int
961 i915_next_seqno_get(void *data, u64 *val)
962 {
963 struct drm_device *dev = data;
964 struct drm_i915_private *dev_priv = dev->dev_private;
965 int ret;
966
967 ret = mutex_lock_interruptible(&dev->struct_mutex);
968 if (ret)
969 return ret;
970
971 *val = dev_priv->next_seqno;
972 mutex_unlock(&dev->struct_mutex);
973
974 return 0;
975 }
976
977 static int
978 i915_next_seqno_set(void *data, u64 val)
979 {
980 struct drm_device *dev = data;
981 int ret;
982
983 ret = mutex_lock_interruptible(&dev->struct_mutex);
984 if (ret)
985 return ret;
986
987 ret = i915_gem_set_seqno(dev, val);
988 mutex_unlock(&dev->struct_mutex);
989
990 return ret;
991 }
992
993 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
994 i915_next_seqno_get, i915_next_seqno_set,
995 "0x%llx\n");
996
997 static int i915_frequency_info(struct seq_file *m, void *unused)
998 {
999 struct drm_info_node *node = m->private;
1000 struct drm_device *dev = node->minor->dev;
1001 struct drm_i915_private *dev_priv = dev->dev_private;
1002 int ret = 0;
1003
1004 intel_runtime_pm_get(dev_priv);
1005
1006 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1007
1008 if (IS_GEN5(dev)) {
1009 u16 rgvswctl = I915_READ16(MEMSWCTL);
1010 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1011
1012 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1013 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1014 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1015 MEMSTAT_VID_SHIFT);
1016 seq_printf(m, "Current P-state: %d\n",
1017 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1018 } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1019 IS_BROADWELL(dev)) {
1020 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1021 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1022 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1023 u32 rpmodectl, rpinclimit, rpdeclimit;
1024 u32 rpstat, cagf, reqf;
1025 u32 rpupei, rpcurup, rpprevup;
1026 u32 rpdownei, rpcurdown, rpprevdown;
1027 int max_freq;
1028
1029 /* RPSTAT1 is in the GT power well */
1030 ret = mutex_lock_interruptible(&dev->struct_mutex);
1031 if (ret)
1032 goto out;
1033
1034 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
1035
1036 reqf = I915_READ(GEN6_RPNSWREQ);
1037 reqf &= ~GEN6_TURBO_DISABLE;
1038 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1039 reqf >>= 24;
1040 else
1041 reqf >>= 25;
1042 reqf *= GT_FREQUENCY_MULTIPLIER;
1043
1044 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1045 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1046 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1047
1048 rpstat = I915_READ(GEN6_RPSTAT1);
1049 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1050 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1051 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1052 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1053 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1054 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1055 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1056 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1057 else
1058 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1059 cagf *= GT_FREQUENCY_MULTIPLIER;
1060
1061 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
1062 mutex_unlock(&dev->struct_mutex);
1063
1064 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1065 I915_READ(GEN6_PMIER),
1066 I915_READ(GEN6_PMIMR),
1067 I915_READ(GEN6_PMISR),
1068 I915_READ(GEN6_PMIIR),
1069 I915_READ(GEN6_PMINTRMSK));
1070 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1071 seq_printf(m, "Render p-state ratio: %d\n",
1072 (gt_perf_status & 0xff00) >> 8);
1073 seq_printf(m, "Render p-state VID: %d\n",
1074 gt_perf_status & 0xff);
1075 seq_printf(m, "Render p-state limit: %d\n",
1076 rp_state_limits & 0xff);
1077 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1078 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1079 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1080 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1081 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1082 seq_printf(m, "CAGF: %dMHz\n", cagf);
1083 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1084 GEN6_CURICONT_MASK);
1085 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1086 GEN6_CURBSYTAVG_MASK);
1087 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1088 GEN6_CURBSYTAVG_MASK);
1089 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1090 GEN6_CURIAVG_MASK);
1091 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1092 GEN6_CURBSYTAVG_MASK);
1093 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1094 GEN6_CURBSYTAVG_MASK);
1095
1096 max_freq = (rp_state_cap & 0xff0000) >> 16;
1097 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1098 max_freq * GT_FREQUENCY_MULTIPLIER);
1099
1100 max_freq = (rp_state_cap & 0xff00) >> 8;
1101 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1102 max_freq * GT_FREQUENCY_MULTIPLIER);
1103
1104 max_freq = rp_state_cap & 0xff;
1105 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1106 max_freq * GT_FREQUENCY_MULTIPLIER);
1107
1108 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1109 dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER);
1110 } else if (IS_VALLEYVIEW(dev)) {
1111 u32 freq_sts, val;
1112
1113 mutex_lock(&dev_priv->rps.hw_lock);
1114 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1115 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1116 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1117
1118 val = valleyview_rps_max_freq(dev_priv);
1119 seq_printf(m, "max GPU freq: %d MHz\n",
1120 vlv_gpu_freq(dev_priv, val));
1121
1122 val = valleyview_rps_min_freq(dev_priv);
1123 seq_printf(m, "min GPU freq: %d MHz\n",
1124 vlv_gpu_freq(dev_priv, val));
1125
1126 seq_printf(m, "current GPU freq: %d MHz\n",
1127 vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1128 mutex_unlock(&dev_priv->rps.hw_lock);
1129 } else {
1130 seq_puts(m, "no P-state info available\n");
1131 }
1132
1133 out:
1134 intel_runtime_pm_put(dev_priv);
1135 return ret;
1136 }
1137
1138 static int ironlake_drpc_info(struct seq_file *m)
1139 {
1140 struct drm_info_node *node = m->private;
1141 struct drm_device *dev = node->minor->dev;
1142 struct drm_i915_private *dev_priv = dev->dev_private;
1143 u32 rgvmodectl, rstdbyctl;
1144 u16 crstandvid;
1145 int ret;
1146
1147 ret = mutex_lock_interruptible(&dev->struct_mutex);
1148 if (ret)
1149 return ret;
1150 intel_runtime_pm_get(dev_priv);
1151
1152 rgvmodectl = I915_READ(MEMMODECTL);
1153 rstdbyctl = I915_READ(RSTDBYCTL);
1154 crstandvid = I915_READ16(CRSTANDVID);
1155
1156 intel_runtime_pm_put(dev_priv);
1157 mutex_unlock(&dev->struct_mutex);
1158
1159 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1160 "yes" : "no");
1161 seq_printf(m, "Boost freq: %d\n",
1162 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1163 MEMMODE_BOOST_FREQ_SHIFT);
1164 seq_printf(m, "HW control enabled: %s\n",
1165 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1166 seq_printf(m, "SW control enabled: %s\n",
1167 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1168 seq_printf(m, "Gated voltage change: %s\n",
1169 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1170 seq_printf(m, "Starting frequency: P%d\n",
1171 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1172 seq_printf(m, "Max P-state: P%d\n",
1173 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1174 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1175 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1176 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1177 seq_printf(m, "Render standby enabled: %s\n",
1178 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1179 seq_puts(m, "Current RS state: ");
1180 switch (rstdbyctl & RSX_STATUS_MASK) {
1181 case RSX_STATUS_ON:
1182 seq_puts(m, "on\n");
1183 break;
1184 case RSX_STATUS_RC1:
1185 seq_puts(m, "RC1\n");
1186 break;
1187 case RSX_STATUS_RC1E:
1188 seq_puts(m, "RC1E\n");
1189 break;
1190 case RSX_STATUS_RS1:
1191 seq_puts(m, "RS1\n");
1192 break;
1193 case RSX_STATUS_RS2:
1194 seq_puts(m, "RS2 (RC6)\n");
1195 break;
1196 case RSX_STATUS_RS3:
1197 seq_puts(m, "RC3 (RC6+)\n");
1198 break;
1199 default:
1200 seq_puts(m, "unknown\n");
1201 break;
1202 }
1203
1204 return 0;
1205 }
1206
1207 static int vlv_drpc_info(struct seq_file *m)
1208 {
1209
1210 struct drm_info_node *node = m->private;
1211 struct drm_device *dev = node->minor->dev;
1212 struct drm_i915_private *dev_priv = dev->dev_private;
1213 u32 rpmodectl1, rcctl1;
1214 unsigned fw_rendercount = 0, fw_mediacount = 0;
1215
1216 intel_runtime_pm_get(dev_priv);
1217
1218 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1219 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1220
1221 intel_runtime_pm_put(dev_priv);
1222
1223 seq_printf(m, "Video Turbo Mode: %s\n",
1224 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1225 seq_printf(m, "Turbo enabled: %s\n",
1226 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1227 seq_printf(m, "HW control enabled: %s\n",
1228 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1229 seq_printf(m, "SW control enabled: %s\n",
1230 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1231 GEN6_RP_MEDIA_SW_MODE));
1232 seq_printf(m, "RC6 Enabled: %s\n",
1233 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1234 GEN6_RC_CTL_EI_MODE(1))));
1235 seq_printf(m, "Render Power Well: %s\n",
1236 (I915_READ(VLV_GTLC_PW_STATUS) &
1237 VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1238 seq_printf(m, "Media Power Well: %s\n",
1239 (I915_READ(VLV_GTLC_PW_STATUS) &
1240 VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1241
1242 seq_printf(m, "Render RC6 residency since boot: %u\n",
1243 I915_READ(VLV_GT_RENDER_RC6));
1244 seq_printf(m, "Media RC6 residency since boot: %u\n",
1245 I915_READ(VLV_GT_MEDIA_RC6));
1246
1247 spin_lock_irq(&dev_priv->uncore.lock);
1248 fw_rendercount = dev_priv->uncore.fw_rendercount;
1249 fw_mediacount = dev_priv->uncore.fw_mediacount;
1250 spin_unlock_irq(&dev_priv->uncore.lock);
1251
1252 seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount);
1253 seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount);
1254
1255
1256 return 0;
1257 }
1258
1259
1260 static int gen6_drpc_info(struct seq_file *m)
1261 {
1262
1263 struct drm_info_node *node = m->private;
1264 struct drm_device *dev = node->minor->dev;
1265 struct drm_i915_private *dev_priv = dev->dev_private;
1266 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1267 unsigned forcewake_count;
1268 int count = 0, ret;
1269
1270 ret = mutex_lock_interruptible(&dev->struct_mutex);
1271 if (ret)
1272 return ret;
1273 intel_runtime_pm_get(dev_priv);
1274
1275 spin_lock_irq(&dev_priv->uncore.lock);
1276 forcewake_count = dev_priv->uncore.forcewake_count;
1277 spin_unlock_irq(&dev_priv->uncore.lock);
1278
1279 if (forcewake_count) {
1280 seq_puts(m, "RC information inaccurate because somebody "
1281 "holds a forcewake reference \n");
1282 } else {
1283 /* NB: we cannot use forcewake, else we read the wrong values */
1284 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1285 udelay(10);
1286 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1287 }
1288
1289 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1290 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1291
1292 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1293 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1294 mutex_unlock(&dev->struct_mutex);
1295 mutex_lock(&dev_priv->rps.hw_lock);
1296 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1297 mutex_unlock(&dev_priv->rps.hw_lock);
1298
1299 intel_runtime_pm_put(dev_priv);
1300
1301 seq_printf(m, "Video Turbo Mode: %s\n",
1302 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1303 seq_printf(m, "HW control enabled: %s\n",
1304 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1305 seq_printf(m, "SW control enabled: %s\n",
1306 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1307 GEN6_RP_MEDIA_SW_MODE));
1308 seq_printf(m, "RC1e Enabled: %s\n",
1309 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1310 seq_printf(m, "RC6 Enabled: %s\n",
1311 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1312 seq_printf(m, "Deep RC6 Enabled: %s\n",
1313 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1314 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1315 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1316 seq_puts(m, "Current RC state: ");
1317 switch (gt_core_status & GEN6_RCn_MASK) {
1318 case GEN6_RC0:
1319 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1320 seq_puts(m, "Core Power Down\n");
1321 else
1322 seq_puts(m, "on\n");
1323 break;
1324 case GEN6_RC3:
1325 seq_puts(m, "RC3\n");
1326 break;
1327 case GEN6_RC6:
1328 seq_puts(m, "RC6\n");
1329 break;
1330 case GEN6_RC7:
1331 seq_puts(m, "RC7\n");
1332 break;
1333 default:
1334 seq_puts(m, "Unknown\n");
1335 break;
1336 }
1337
1338 seq_printf(m, "Core Power Down: %s\n",
1339 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1340
1341 /* Not exactly sure what this is */
1342 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1343 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1344 seq_printf(m, "RC6 residency since boot: %u\n",
1345 I915_READ(GEN6_GT_GFX_RC6));
1346 seq_printf(m, "RC6+ residency since boot: %u\n",
1347 I915_READ(GEN6_GT_GFX_RC6p));
1348 seq_printf(m, "RC6++ residency since boot: %u\n",
1349 I915_READ(GEN6_GT_GFX_RC6pp));
1350
1351 seq_printf(m, "RC6 voltage: %dmV\n",
1352 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1353 seq_printf(m, "RC6+ voltage: %dmV\n",
1354 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1355 seq_printf(m, "RC6++ voltage: %dmV\n",
1356 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1357 return 0;
1358 }
1359
1360 static int i915_drpc_info(struct seq_file *m, void *unused)
1361 {
1362 struct drm_info_node *node = m->private;
1363 struct drm_device *dev = node->minor->dev;
1364
1365 if (IS_VALLEYVIEW(dev))
1366 return vlv_drpc_info(m);
1367 else if (IS_GEN6(dev) || IS_GEN7(dev))
1368 return gen6_drpc_info(m);
1369 else
1370 return ironlake_drpc_info(m);
1371 }
1372
1373 static int i915_fbc_status(struct seq_file *m, void *unused)
1374 {
1375 struct drm_info_node *node = m->private;
1376 struct drm_device *dev = node->minor->dev;
1377 struct drm_i915_private *dev_priv = dev->dev_private;
1378
1379 if (!HAS_FBC(dev)) {
1380 seq_puts(m, "FBC unsupported on this chipset\n");
1381 return 0;
1382 }
1383
1384 intel_runtime_pm_get(dev_priv);
1385
1386 if (intel_fbc_enabled(dev)) {
1387 seq_puts(m, "FBC enabled\n");
1388 } else {
1389 seq_puts(m, "FBC disabled: ");
1390 switch (dev_priv->fbc.no_fbc_reason) {
1391 case FBC_OK:
1392 seq_puts(m, "FBC actived, but currently disabled in hardware");
1393 break;
1394 case FBC_UNSUPPORTED:
1395 seq_puts(m, "unsupported by this chipset");
1396 break;
1397 case FBC_NO_OUTPUT:
1398 seq_puts(m, "no outputs");
1399 break;
1400 case FBC_STOLEN_TOO_SMALL:
1401 seq_puts(m, "not enough stolen memory");
1402 break;
1403 case FBC_UNSUPPORTED_MODE:
1404 seq_puts(m, "mode not supported");
1405 break;
1406 case FBC_MODE_TOO_LARGE:
1407 seq_puts(m, "mode too large");
1408 break;
1409 case FBC_BAD_PLANE:
1410 seq_puts(m, "FBC unsupported on plane");
1411 break;
1412 case FBC_NOT_TILED:
1413 seq_puts(m, "scanout buffer not tiled");
1414 break;
1415 case FBC_MULTIPLE_PIPES:
1416 seq_puts(m, "multiple pipes are enabled");
1417 break;
1418 case FBC_MODULE_PARAM:
1419 seq_puts(m, "disabled per module param (default off)");
1420 break;
1421 case FBC_CHIP_DEFAULT:
1422 seq_puts(m, "disabled per chip default");
1423 break;
1424 default:
1425 seq_puts(m, "unknown reason");
1426 }
1427 seq_putc(m, '\n');
1428 }
1429
1430 intel_runtime_pm_put(dev_priv);
1431
1432 return 0;
1433 }
1434
1435 static int i915_ips_status(struct seq_file *m, void *unused)
1436 {
1437 struct drm_info_node *node = m->private;
1438 struct drm_device *dev = node->minor->dev;
1439 struct drm_i915_private *dev_priv = dev->dev_private;
1440
1441 if (!HAS_IPS(dev)) {
1442 seq_puts(m, "not supported\n");
1443 return 0;
1444 }
1445
1446 intel_runtime_pm_get(dev_priv);
1447
1448 seq_printf(m, "Enabled by kernel parameter: %s\n",
1449 yesno(i915.enable_ips));
1450
1451 if (INTEL_INFO(dev)->gen >= 8) {
1452 seq_puts(m, "Currently: unknown\n");
1453 } else {
1454 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1455 seq_puts(m, "Currently: enabled\n");
1456 else
1457 seq_puts(m, "Currently: disabled\n");
1458 }
1459
1460 intel_runtime_pm_put(dev_priv);
1461
1462 return 0;
1463 }
1464
1465 static int i915_sr_status(struct seq_file *m, void *unused)
1466 {
1467 struct drm_info_node *node = m->private;
1468 struct drm_device *dev = node->minor->dev;
1469 struct drm_i915_private *dev_priv = dev->dev_private;
1470 bool sr_enabled = false;
1471
1472 intel_runtime_pm_get(dev_priv);
1473
1474 if (HAS_PCH_SPLIT(dev))
1475 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1476 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1477 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1478 else if (IS_I915GM(dev))
1479 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1480 else if (IS_PINEVIEW(dev))
1481 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1482
1483 intel_runtime_pm_put(dev_priv);
1484
1485 seq_printf(m, "self-refresh: %s\n",
1486 sr_enabled ? "enabled" : "disabled");
1487
1488 return 0;
1489 }
1490
1491 static int i915_emon_status(struct seq_file *m, void *unused)
1492 {
1493 struct drm_info_node *node = m->private;
1494 struct drm_device *dev = node->minor->dev;
1495 struct drm_i915_private *dev_priv = dev->dev_private;
1496 unsigned long temp, chipset, gfx;
1497 int ret;
1498
1499 if (!IS_GEN5(dev))
1500 return -ENODEV;
1501
1502 ret = mutex_lock_interruptible(&dev->struct_mutex);
1503 if (ret)
1504 return ret;
1505
1506 temp = i915_mch_val(dev_priv);
1507 chipset = i915_chipset_val(dev_priv);
1508 gfx = i915_gfx_val(dev_priv);
1509 mutex_unlock(&dev->struct_mutex);
1510
1511 seq_printf(m, "GMCH temp: %ld\n", temp);
1512 seq_printf(m, "Chipset power: %ld\n", chipset);
1513 seq_printf(m, "GFX power: %ld\n", gfx);
1514 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1515
1516 return 0;
1517 }
1518
1519 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1520 {
1521 struct drm_info_node *node = m->private;
1522 struct drm_device *dev = node->minor->dev;
1523 struct drm_i915_private *dev_priv = dev->dev_private;
1524 int ret = 0;
1525 int gpu_freq, ia_freq;
1526
1527 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1528 seq_puts(m, "unsupported on this chipset\n");
1529 return 0;
1530 }
1531
1532 intel_runtime_pm_get(dev_priv);
1533
1534 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1535
1536 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1537 if (ret)
1538 goto out;
1539
1540 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1541
1542 for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1543 gpu_freq <= dev_priv->rps.max_freq_softlimit;
1544 gpu_freq++) {
1545 ia_freq = gpu_freq;
1546 sandybridge_pcode_read(dev_priv,
1547 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1548 &ia_freq);
1549 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1550 gpu_freq * GT_FREQUENCY_MULTIPLIER,
1551 ((ia_freq >> 0) & 0xff) * 100,
1552 ((ia_freq >> 8) & 0xff) * 100);
1553 }
1554
1555 mutex_unlock(&dev_priv->rps.hw_lock);
1556
1557 out:
1558 intel_runtime_pm_put(dev_priv);
1559 return ret;
1560 }
1561
1562 static int i915_opregion(struct seq_file *m, void *unused)
1563 {
1564 struct drm_info_node *node = m->private;
1565 struct drm_device *dev = node->minor->dev;
1566 struct drm_i915_private *dev_priv = dev->dev_private;
1567 struct intel_opregion *opregion = &dev_priv->opregion;
1568 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1569 int ret;
1570
1571 if (data == NULL)
1572 return -ENOMEM;
1573
1574 ret = mutex_lock_interruptible(&dev->struct_mutex);
1575 if (ret)
1576 goto out;
1577
1578 if (opregion->header) {
1579 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1580 seq_write(m, data, OPREGION_SIZE);
1581 }
1582
1583 mutex_unlock(&dev->struct_mutex);
1584
1585 out:
1586 kfree(data);
1587 return 0;
1588 }
1589
1590 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1591 {
1592 struct drm_info_node *node = m->private;
1593 struct drm_device *dev = node->minor->dev;
1594 struct intel_fbdev *ifbdev = NULL;
1595 struct intel_framebuffer *fb;
1596
1597 #ifdef CONFIG_DRM_I915_FBDEV
1598 struct drm_i915_private *dev_priv = dev->dev_private;
1599
1600 ifbdev = dev_priv->fbdev;
1601 fb = to_intel_framebuffer(ifbdev->helper.fb);
1602
1603 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1604 fb->base.width,
1605 fb->base.height,
1606 fb->base.depth,
1607 fb->base.bits_per_pixel,
1608 atomic_read(&fb->base.refcount.refcount));
1609 describe_obj(m, fb->obj);
1610 seq_putc(m, '\n');
1611 #endif
1612
1613 mutex_lock(&dev->mode_config.fb_lock);
1614 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1615 if (ifbdev && &fb->base == ifbdev->helper.fb)
1616 continue;
1617
1618 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1619 fb->base.width,
1620 fb->base.height,
1621 fb->base.depth,
1622 fb->base.bits_per_pixel,
1623 atomic_read(&fb->base.refcount.refcount));
1624 describe_obj(m, fb->obj);
1625 seq_putc(m, '\n');
1626 }
1627 mutex_unlock(&dev->mode_config.fb_lock);
1628
1629 return 0;
1630 }
1631
1632 static int i915_context_status(struct seq_file *m, void *unused)
1633 {
1634 struct drm_info_node *node = m->private;
1635 struct drm_device *dev = node->minor->dev;
1636 struct drm_i915_private *dev_priv = dev->dev_private;
1637 struct intel_engine_cs *ring;
1638 struct intel_context *ctx;
1639 int ret, i;
1640
1641 ret = mutex_lock_interruptible(&dev->struct_mutex);
1642 if (ret)
1643 return ret;
1644
1645 if (dev_priv->ips.pwrctx) {
1646 seq_puts(m, "power context ");
1647 describe_obj(m, dev_priv->ips.pwrctx);
1648 seq_putc(m, '\n');
1649 }
1650
1651 if (dev_priv->ips.renderctx) {
1652 seq_puts(m, "render context ");
1653 describe_obj(m, dev_priv->ips.renderctx);
1654 seq_putc(m, '\n');
1655 }
1656
1657 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1658 if (ctx->legacy_hw_ctx.rcs_state == NULL)
1659 continue;
1660
1661 seq_puts(m, "HW context ");
1662 describe_ctx(m, ctx);
1663 for_each_ring(ring, dev_priv, i)
1664 if (ring->default_context == ctx)
1665 seq_printf(m, "(default context %s) ", ring->name);
1666
1667 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1668 seq_putc(m, '\n');
1669 }
1670
1671 mutex_unlock(&dev->struct_mutex);
1672
1673 return 0;
1674 }
1675
1676 static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1677 {
1678 struct drm_info_node *node = m->private;
1679 struct drm_device *dev = node->minor->dev;
1680 struct drm_i915_private *dev_priv = dev->dev_private;
1681 unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0;
1682
1683 spin_lock_irq(&dev_priv->uncore.lock);
1684 if (IS_VALLEYVIEW(dev)) {
1685 fw_rendercount = dev_priv->uncore.fw_rendercount;
1686 fw_mediacount = dev_priv->uncore.fw_mediacount;
1687 } else
1688 forcewake_count = dev_priv->uncore.forcewake_count;
1689 spin_unlock_irq(&dev_priv->uncore.lock);
1690
1691 if (IS_VALLEYVIEW(dev)) {
1692 seq_printf(m, "fw_rendercount = %u\n", fw_rendercount);
1693 seq_printf(m, "fw_mediacount = %u\n", fw_mediacount);
1694 } else
1695 seq_printf(m, "forcewake count = %u\n", forcewake_count);
1696
1697 return 0;
1698 }
1699
1700 static const char *swizzle_string(unsigned swizzle)
1701 {
1702 switch (swizzle) {
1703 case I915_BIT_6_SWIZZLE_NONE:
1704 return "none";
1705 case I915_BIT_6_SWIZZLE_9:
1706 return "bit9";
1707 case I915_BIT_6_SWIZZLE_9_10:
1708 return "bit9/bit10";
1709 case I915_BIT_6_SWIZZLE_9_11:
1710 return "bit9/bit11";
1711 case I915_BIT_6_SWIZZLE_9_10_11:
1712 return "bit9/bit10/bit11";
1713 case I915_BIT_6_SWIZZLE_9_17:
1714 return "bit9/bit17";
1715 case I915_BIT_6_SWIZZLE_9_10_17:
1716 return "bit9/bit10/bit17";
1717 case I915_BIT_6_SWIZZLE_UNKNOWN:
1718 return "unknown";
1719 }
1720
1721 return "bug";
1722 }
1723
1724 static int i915_swizzle_info(struct seq_file *m, void *data)
1725 {
1726 struct drm_info_node *node = m->private;
1727 struct drm_device *dev = node->minor->dev;
1728 struct drm_i915_private *dev_priv = dev->dev_private;
1729 int ret;
1730
1731 ret = mutex_lock_interruptible(&dev->struct_mutex);
1732 if (ret)
1733 return ret;
1734 intel_runtime_pm_get(dev_priv);
1735
1736 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1737 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1738 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1739 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1740
1741 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1742 seq_printf(m, "DDC = 0x%08x\n",
1743 I915_READ(DCC));
1744 seq_printf(m, "C0DRB3 = 0x%04x\n",
1745 I915_READ16(C0DRB3));
1746 seq_printf(m, "C1DRB3 = 0x%04x\n",
1747 I915_READ16(C1DRB3));
1748 } else if (INTEL_INFO(dev)->gen >= 6) {
1749 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1750 I915_READ(MAD_DIMM_C0));
1751 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1752 I915_READ(MAD_DIMM_C1));
1753 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1754 I915_READ(MAD_DIMM_C2));
1755 seq_printf(m, "TILECTL = 0x%08x\n",
1756 I915_READ(TILECTL));
1757 if (IS_GEN8(dev))
1758 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
1759 I915_READ(GAMTARBMODE));
1760 else
1761 seq_printf(m, "ARB_MODE = 0x%08x\n",
1762 I915_READ(ARB_MODE));
1763 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1764 I915_READ(DISP_ARB_CTL));
1765 }
1766 intel_runtime_pm_put(dev_priv);
1767 mutex_unlock(&dev->struct_mutex);
1768
1769 return 0;
1770 }
1771
1772 static int per_file_ctx(int id, void *ptr, void *data)
1773 {
1774 struct intel_context *ctx = ptr;
1775 struct seq_file *m = data;
1776 struct i915_hw_ppgtt *ppgtt = ctx_to_ppgtt(ctx);
1777
1778 if (i915_gem_context_is_default(ctx))
1779 seq_puts(m, " default context:\n");
1780 else
1781 seq_printf(m, " context %d:\n", ctx->user_handle);
1782 ppgtt->debug_dump(ppgtt, m);
1783
1784 return 0;
1785 }
1786
1787 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
1788 {
1789 struct drm_i915_private *dev_priv = dev->dev_private;
1790 struct intel_engine_cs *ring;
1791 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1792 int unused, i;
1793
1794 if (!ppgtt)
1795 return;
1796
1797 seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
1798 seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
1799 for_each_ring(ring, dev_priv, unused) {
1800 seq_printf(m, "%s\n", ring->name);
1801 for (i = 0; i < 4; i++) {
1802 u32 offset = 0x270 + i * 8;
1803 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
1804 pdp <<= 32;
1805 pdp |= I915_READ(ring->mmio_base + offset);
1806 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
1807 }
1808 }
1809 }
1810
1811 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
1812 {
1813 struct drm_i915_private *dev_priv = dev->dev_private;
1814 struct intel_engine_cs *ring;
1815 struct drm_file *file;
1816 int i;
1817
1818 if (INTEL_INFO(dev)->gen == 6)
1819 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1820
1821 for_each_ring(ring, dev_priv, i) {
1822 seq_printf(m, "%s\n", ring->name);
1823 if (INTEL_INFO(dev)->gen == 7)
1824 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1825 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1826 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1827 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1828 }
1829 if (dev_priv->mm.aliasing_ppgtt) {
1830 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1831
1832 seq_puts(m, "aliasing PPGTT:\n");
1833 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1834
1835 ppgtt->debug_dump(ppgtt, m);
1836 } else
1837 return;
1838
1839 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
1840 struct drm_i915_file_private *file_priv = file->driver_priv;
1841
1842 seq_printf(m, "proc: %s\n",
1843 get_pid_task(file->pid, PIDTYPE_PID)->comm);
1844 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
1845 }
1846 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
1847 }
1848
1849 static int i915_ppgtt_info(struct seq_file *m, void *data)
1850 {
1851 struct drm_info_node *node = m->private;
1852 struct drm_device *dev = node->minor->dev;
1853 struct drm_i915_private *dev_priv = dev->dev_private;
1854
1855 int ret = mutex_lock_interruptible(&dev->struct_mutex);
1856 if (ret)
1857 return ret;
1858 intel_runtime_pm_get(dev_priv);
1859
1860 if (INTEL_INFO(dev)->gen >= 8)
1861 gen8_ppgtt_info(m, dev);
1862 else if (INTEL_INFO(dev)->gen >= 6)
1863 gen6_ppgtt_info(m, dev);
1864
1865 intel_runtime_pm_put(dev_priv);
1866 mutex_unlock(&dev->struct_mutex);
1867
1868 return 0;
1869 }
1870
1871 static int i915_llc(struct seq_file *m, void *data)
1872 {
1873 struct drm_info_node *node = m->private;
1874 struct drm_device *dev = node->minor->dev;
1875 struct drm_i915_private *dev_priv = dev->dev_private;
1876
1877 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
1878 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
1879 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
1880
1881 return 0;
1882 }
1883
1884 static int i915_edp_psr_status(struct seq_file *m, void *data)
1885 {
1886 struct drm_info_node *node = m->private;
1887 struct drm_device *dev = node->minor->dev;
1888 struct drm_i915_private *dev_priv = dev->dev_private;
1889 u32 psrperf = 0;
1890 bool enabled = false;
1891
1892 intel_runtime_pm_get(dev_priv);
1893
1894 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
1895 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
1896 seq_printf(m, "Enabled: %s\n", yesno(dev_priv->psr.enabled));
1897 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
1898
1899 enabled = HAS_PSR(dev) &&
1900 I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1901 seq_printf(m, "HW Enabled & Active bit: %s\n", yesno(enabled));
1902
1903 if (HAS_PSR(dev))
1904 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
1905 EDP_PSR_PERF_CNT_MASK;
1906 seq_printf(m, "Performance_Counter: %u\n", psrperf);
1907
1908 intel_runtime_pm_put(dev_priv);
1909 return 0;
1910 }
1911
1912 static int i915_sink_crc(struct seq_file *m, void *data)
1913 {
1914 struct drm_info_node *node = m->private;
1915 struct drm_device *dev = node->minor->dev;
1916 struct intel_encoder *encoder;
1917 struct intel_connector *connector;
1918 struct intel_dp *intel_dp = NULL;
1919 int ret;
1920 u8 crc[6];
1921
1922 drm_modeset_lock_all(dev);
1923 list_for_each_entry(connector, &dev->mode_config.connector_list,
1924 base.head) {
1925
1926 if (connector->base.dpms != DRM_MODE_DPMS_ON)
1927 continue;
1928
1929 if (!connector->base.encoder)
1930 continue;
1931
1932 encoder = to_intel_encoder(connector->base.encoder);
1933 if (encoder->type != INTEL_OUTPUT_EDP)
1934 continue;
1935
1936 intel_dp = enc_to_intel_dp(&encoder->base);
1937
1938 ret = intel_dp_sink_crc(intel_dp, crc);
1939 if (ret)
1940 goto out;
1941
1942 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
1943 crc[0], crc[1], crc[2],
1944 crc[3], crc[4], crc[5]);
1945 goto out;
1946 }
1947 ret = -ENODEV;
1948 out:
1949 drm_modeset_unlock_all(dev);
1950 return ret;
1951 }
1952
1953 static int i915_energy_uJ(struct seq_file *m, void *data)
1954 {
1955 struct drm_info_node *node = m->private;
1956 struct drm_device *dev = node->minor->dev;
1957 struct drm_i915_private *dev_priv = dev->dev_private;
1958 u64 power;
1959 u32 units;
1960
1961 if (INTEL_INFO(dev)->gen < 6)
1962 return -ENODEV;
1963
1964 intel_runtime_pm_get(dev_priv);
1965
1966 rdmsrl(MSR_RAPL_POWER_UNIT, power);
1967 power = (power & 0x1f00) >> 8;
1968 units = 1000000 / (1 << power); /* convert to uJ */
1969 power = I915_READ(MCH_SECP_NRG_STTS);
1970 power *= units;
1971
1972 intel_runtime_pm_put(dev_priv);
1973
1974 seq_printf(m, "%llu", (long long unsigned)power);
1975
1976 return 0;
1977 }
1978
1979 static int i915_pc8_status(struct seq_file *m, void *unused)
1980 {
1981 struct drm_info_node *node = m->private;
1982 struct drm_device *dev = node->minor->dev;
1983 struct drm_i915_private *dev_priv = dev->dev_private;
1984
1985 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
1986 seq_puts(m, "not supported\n");
1987 return 0;
1988 }
1989
1990 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
1991 seq_printf(m, "IRQs disabled: %s\n",
1992 yesno(dev_priv->pm.irqs_disabled));
1993
1994 return 0;
1995 }
1996
1997 static const char *power_domain_str(enum intel_display_power_domain domain)
1998 {
1999 switch (domain) {
2000 case POWER_DOMAIN_PIPE_A:
2001 return "PIPE_A";
2002 case POWER_DOMAIN_PIPE_B:
2003 return "PIPE_B";
2004 case POWER_DOMAIN_PIPE_C:
2005 return "PIPE_C";
2006 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2007 return "PIPE_A_PANEL_FITTER";
2008 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2009 return "PIPE_B_PANEL_FITTER";
2010 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2011 return "PIPE_C_PANEL_FITTER";
2012 case POWER_DOMAIN_TRANSCODER_A:
2013 return "TRANSCODER_A";
2014 case POWER_DOMAIN_TRANSCODER_B:
2015 return "TRANSCODER_B";
2016 case POWER_DOMAIN_TRANSCODER_C:
2017 return "TRANSCODER_C";
2018 case POWER_DOMAIN_TRANSCODER_EDP:
2019 return "TRANSCODER_EDP";
2020 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2021 return "PORT_DDI_A_2_LANES";
2022 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2023 return "PORT_DDI_A_4_LANES";
2024 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2025 return "PORT_DDI_B_2_LANES";
2026 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2027 return "PORT_DDI_B_4_LANES";
2028 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2029 return "PORT_DDI_C_2_LANES";
2030 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2031 return "PORT_DDI_C_4_LANES";
2032 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2033 return "PORT_DDI_D_2_LANES";
2034 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2035 return "PORT_DDI_D_4_LANES";
2036 case POWER_DOMAIN_PORT_DSI:
2037 return "PORT_DSI";
2038 case POWER_DOMAIN_PORT_CRT:
2039 return "PORT_CRT";
2040 case POWER_DOMAIN_PORT_OTHER:
2041 return "PORT_OTHER";
2042 case POWER_DOMAIN_VGA:
2043 return "VGA";
2044 case POWER_DOMAIN_AUDIO:
2045 return "AUDIO";
2046 case POWER_DOMAIN_INIT:
2047 return "INIT";
2048 default:
2049 WARN_ON(1);
2050 return "?";
2051 }
2052 }
2053
2054 static int i915_power_domain_info(struct seq_file *m, void *unused)
2055 {
2056 struct drm_info_node *node = m->private;
2057 struct drm_device *dev = node->minor->dev;
2058 struct drm_i915_private *dev_priv = dev->dev_private;
2059 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2060 int i;
2061
2062 mutex_lock(&power_domains->lock);
2063
2064 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2065 for (i = 0; i < power_domains->power_well_count; i++) {
2066 struct i915_power_well *power_well;
2067 enum intel_display_power_domain power_domain;
2068
2069 power_well = &power_domains->power_wells[i];
2070 seq_printf(m, "%-25s %d\n", power_well->name,
2071 power_well->count);
2072
2073 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2074 power_domain++) {
2075 if (!(BIT(power_domain) & power_well->domains))
2076 continue;
2077
2078 seq_printf(m, " %-23s %d\n",
2079 power_domain_str(power_domain),
2080 power_domains->domain_use_count[power_domain]);
2081 }
2082 }
2083
2084 mutex_unlock(&power_domains->lock);
2085
2086 return 0;
2087 }
2088
2089 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2090 struct drm_display_mode *mode)
2091 {
2092 int i;
2093
2094 for (i = 0; i < tabs; i++)
2095 seq_putc(m, '\t');
2096
2097 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2098 mode->base.id, mode->name,
2099 mode->vrefresh, mode->clock,
2100 mode->hdisplay, mode->hsync_start,
2101 mode->hsync_end, mode->htotal,
2102 mode->vdisplay, mode->vsync_start,
2103 mode->vsync_end, mode->vtotal,
2104 mode->type, mode->flags);
2105 }
2106
2107 static void intel_encoder_info(struct seq_file *m,
2108 struct intel_crtc *intel_crtc,
2109 struct intel_encoder *intel_encoder)
2110 {
2111 struct drm_info_node *node = m->private;
2112 struct drm_device *dev = node->minor->dev;
2113 struct drm_crtc *crtc = &intel_crtc->base;
2114 struct intel_connector *intel_connector;
2115 struct drm_encoder *encoder;
2116
2117 encoder = &intel_encoder->base;
2118 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2119 encoder->base.id, encoder->name);
2120 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2121 struct drm_connector *connector = &intel_connector->base;
2122 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2123 connector->base.id,
2124 connector->name,
2125 drm_get_connector_status_name(connector->status));
2126 if (connector->status == connector_status_connected) {
2127 struct drm_display_mode *mode = &crtc->mode;
2128 seq_printf(m, ", mode:\n");
2129 intel_seq_print_mode(m, 2, mode);
2130 } else {
2131 seq_putc(m, '\n');
2132 }
2133 }
2134 }
2135
2136 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2137 {
2138 struct drm_info_node *node = m->private;
2139 struct drm_device *dev = node->minor->dev;
2140 struct drm_crtc *crtc = &intel_crtc->base;
2141 struct intel_encoder *intel_encoder;
2142
2143 if (crtc->primary->fb)
2144 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2145 crtc->primary->fb->base.id, crtc->x, crtc->y,
2146 crtc->primary->fb->width, crtc->primary->fb->height);
2147 else
2148 seq_puts(m, "\tprimary plane disabled\n");
2149 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2150 intel_encoder_info(m, intel_crtc, intel_encoder);
2151 }
2152
2153 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2154 {
2155 struct drm_display_mode *mode = panel->fixed_mode;
2156
2157 seq_printf(m, "\tfixed mode:\n");
2158 intel_seq_print_mode(m, 2, mode);
2159 }
2160
2161 static void intel_dp_info(struct seq_file *m,
2162 struct intel_connector *intel_connector)
2163 {
2164 struct intel_encoder *intel_encoder = intel_connector->encoder;
2165 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2166
2167 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2168 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2169 "no");
2170 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2171 intel_panel_info(m, &intel_connector->panel);
2172 }
2173
2174 static void intel_hdmi_info(struct seq_file *m,
2175 struct intel_connector *intel_connector)
2176 {
2177 struct intel_encoder *intel_encoder = intel_connector->encoder;
2178 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2179
2180 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2181 "no");
2182 }
2183
2184 static void intel_lvds_info(struct seq_file *m,
2185 struct intel_connector *intel_connector)
2186 {
2187 intel_panel_info(m, &intel_connector->panel);
2188 }
2189
2190 static void intel_connector_info(struct seq_file *m,
2191 struct drm_connector *connector)
2192 {
2193 struct intel_connector *intel_connector = to_intel_connector(connector);
2194 struct intel_encoder *intel_encoder = intel_connector->encoder;
2195 struct drm_display_mode *mode;
2196
2197 seq_printf(m, "connector %d: type %s, status: %s\n",
2198 connector->base.id, connector->name,
2199 drm_get_connector_status_name(connector->status));
2200 if (connector->status == connector_status_connected) {
2201 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2202 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2203 connector->display_info.width_mm,
2204 connector->display_info.height_mm);
2205 seq_printf(m, "\tsubpixel order: %s\n",
2206 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2207 seq_printf(m, "\tCEA rev: %d\n",
2208 connector->display_info.cea_rev);
2209 }
2210 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2211 intel_encoder->type == INTEL_OUTPUT_EDP)
2212 intel_dp_info(m, intel_connector);
2213 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2214 intel_hdmi_info(m, intel_connector);
2215 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2216 intel_lvds_info(m, intel_connector);
2217
2218 seq_printf(m, "\tmodes:\n");
2219 list_for_each_entry(mode, &connector->modes, head)
2220 intel_seq_print_mode(m, 2, mode);
2221 }
2222
2223 static bool cursor_active(struct drm_device *dev, int pipe)
2224 {
2225 struct drm_i915_private *dev_priv = dev->dev_private;
2226 u32 state;
2227
2228 if (IS_845G(dev) || IS_I865G(dev))
2229 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
2230 else
2231 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2232
2233 return state;
2234 }
2235
2236 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2237 {
2238 struct drm_i915_private *dev_priv = dev->dev_private;
2239 u32 pos;
2240
2241 pos = I915_READ(CURPOS(pipe));
2242
2243 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2244 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2245 *x = -*x;
2246
2247 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2248 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2249 *y = -*y;
2250
2251 return cursor_active(dev, pipe);
2252 }
2253
2254 static int i915_display_info(struct seq_file *m, void *unused)
2255 {
2256 struct drm_info_node *node = m->private;
2257 struct drm_device *dev = node->minor->dev;
2258 struct drm_i915_private *dev_priv = dev->dev_private;
2259 struct intel_crtc *crtc;
2260 struct drm_connector *connector;
2261
2262 intel_runtime_pm_get(dev_priv);
2263 drm_modeset_lock_all(dev);
2264 seq_printf(m, "CRTC info\n");
2265 seq_printf(m, "---------\n");
2266 for_each_intel_crtc(dev, crtc) {
2267 bool active;
2268 int x, y;
2269
2270 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
2271 crtc->base.base.id, pipe_name(crtc->pipe),
2272 yesno(crtc->active), crtc->config.pipe_src_w, crtc->config.pipe_src_h);
2273 if (crtc->active) {
2274 intel_crtc_info(m, crtc);
2275
2276 active = cursor_position(dev, crtc->pipe, &x, &y);
2277 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
2278 yesno(crtc->cursor_base),
2279 x, y, crtc->cursor_width, crtc->cursor_height,
2280 crtc->cursor_addr, yesno(active));
2281 }
2282
2283 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2284 yesno(!crtc->cpu_fifo_underrun_disabled),
2285 yesno(!crtc->pch_fifo_underrun_disabled));
2286 }
2287
2288 seq_printf(m, "\n");
2289 seq_printf(m, "Connector info\n");
2290 seq_printf(m, "--------------\n");
2291 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2292 intel_connector_info(m, connector);
2293 }
2294 drm_modeset_unlock_all(dev);
2295 intel_runtime_pm_put(dev_priv);
2296
2297 return 0;
2298 }
2299
2300 static int i915_semaphore_status(struct seq_file *m, void *unused)
2301 {
2302 struct drm_info_node *node = (struct drm_info_node *) m->private;
2303 struct drm_device *dev = node->minor->dev;
2304 struct drm_i915_private *dev_priv = dev->dev_private;
2305 struct intel_engine_cs *ring;
2306 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2307 int i, j, ret;
2308
2309 if (!i915_semaphore_is_enabled(dev)) {
2310 seq_puts(m, "Semaphores are disabled\n");
2311 return 0;
2312 }
2313
2314 ret = mutex_lock_interruptible(&dev->struct_mutex);
2315 if (ret)
2316 return ret;
2317 intel_runtime_pm_get(dev_priv);
2318
2319 if (IS_BROADWELL(dev)) {
2320 struct page *page;
2321 uint64_t *seqno;
2322
2323 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
2324
2325 seqno = (uint64_t *)kmap_atomic(page);
2326 for_each_ring(ring, dev_priv, i) {
2327 uint64_t offset;
2328
2329 seq_printf(m, "%s\n", ring->name);
2330
2331 seq_puts(m, " Last signal:");
2332 for (j = 0; j < num_rings; j++) {
2333 offset = i * I915_NUM_RINGS + j;
2334 seq_printf(m, "0x%08llx (0x%02llx) ",
2335 seqno[offset], offset * 8);
2336 }
2337 seq_putc(m, '\n');
2338
2339 seq_puts(m, " Last wait: ");
2340 for (j = 0; j < num_rings; j++) {
2341 offset = i + (j * I915_NUM_RINGS);
2342 seq_printf(m, "0x%08llx (0x%02llx) ",
2343 seqno[offset], offset * 8);
2344 }
2345 seq_putc(m, '\n');
2346
2347 }
2348 kunmap_atomic(seqno);
2349 } else {
2350 seq_puts(m, " Last signal:");
2351 for_each_ring(ring, dev_priv, i)
2352 for (j = 0; j < num_rings; j++)
2353 seq_printf(m, "0x%08x\n",
2354 I915_READ(ring->semaphore.mbox.signal[j]));
2355 seq_putc(m, '\n');
2356 }
2357
2358 seq_puts(m, "\nSync seqno:\n");
2359 for_each_ring(ring, dev_priv, i) {
2360 for (j = 0; j < num_rings; j++) {
2361 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]);
2362 }
2363 seq_putc(m, '\n');
2364 }
2365 seq_putc(m, '\n');
2366
2367 intel_runtime_pm_put(dev_priv);
2368 mutex_unlock(&dev->struct_mutex);
2369 return 0;
2370 }
2371
2372 struct pipe_crc_info {
2373 const char *name;
2374 struct drm_device *dev;
2375 enum pipe pipe;
2376 };
2377
2378 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
2379 {
2380 struct pipe_crc_info *info = inode->i_private;
2381 struct drm_i915_private *dev_priv = info->dev->dev_private;
2382 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2383
2384 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
2385 return -ENODEV;
2386
2387 spin_lock_irq(&pipe_crc->lock);
2388
2389 if (pipe_crc->opened) {
2390 spin_unlock_irq(&pipe_crc->lock);
2391 return -EBUSY; /* already open */
2392 }
2393
2394 pipe_crc->opened = true;
2395 filep->private_data = inode->i_private;
2396
2397 spin_unlock_irq(&pipe_crc->lock);
2398
2399 return 0;
2400 }
2401
2402 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
2403 {
2404 struct pipe_crc_info *info = inode->i_private;
2405 struct drm_i915_private *dev_priv = info->dev->dev_private;
2406 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2407
2408 spin_lock_irq(&pipe_crc->lock);
2409 pipe_crc->opened = false;
2410 spin_unlock_irq(&pipe_crc->lock);
2411
2412 return 0;
2413 }
2414
2415 /* (6 fields, 8 chars each, space separated (5) + '\n') */
2416 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
2417 /* account for \'0' */
2418 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
2419
2420 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
2421 {
2422 assert_spin_locked(&pipe_crc->lock);
2423 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2424 INTEL_PIPE_CRC_ENTRIES_NR);
2425 }
2426
2427 static ssize_t
2428 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
2429 loff_t *pos)
2430 {
2431 struct pipe_crc_info *info = filep->private_data;
2432 struct drm_device *dev = info->dev;
2433 struct drm_i915_private *dev_priv = dev->dev_private;
2434 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2435 char buf[PIPE_CRC_BUFFER_LEN];
2436 int head, tail, n_entries, n;
2437 ssize_t bytes_read;
2438
2439 /*
2440 * Don't allow user space to provide buffers not big enough to hold
2441 * a line of data.
2442 */
2443 if (count < PIPE_CRC_LINE_LEN)
2444 return -EINVAL;
2445
2446 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
2447 return 0;
2448
2449 /* nothing to read */
2450 spin_lock_irq(&pipe_crc->lock);
2451 while (pipe_crc_data_count(pipe_crc) == 0) {
2452 int ret;
2453
2454 if (filep->f_flags & O_NONBLOCK) {
2455 spin_unlock_irq(&pipe_crc->lock);
2456 return -EAGAIN;
2457 }
2458
2459 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2460 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2461 if (ret) {
2462 spin_unlock_irq(&pipe_crc->lock);
2463 return ret;
2464 }
2465 }
2466
2467 /* We now have one or more entries to read */
2468 head = pipe_crc->head;
2469 tail = pipe_crc->tail;
2470 n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR),
2471 count / PIPE_CRC_LINE_LEN);
2472 spin_unlock_irq(&pipe_crc->lock);
2473
2474 bytes_read = 0;
2475 n = 0;
2476 do {
2477 struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail];
2478 int ret;
2479
2480 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
2481 "%8u %8x %8x %8x %8x %8x\n",
2482 entry->frame, entry->crc[0],
2483 entry->crc[1], entry->crc[2],
2484 entry->crc[3], entry->crc[4]);
2485
2486 ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN,
2487 buf, PIPE_CRC_LINE_LEN);
2488 if (ret == PIPE_CRC_LINE_LEN)
2489 return -EFAULT;
2490
2491 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
2492 tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
2493 n++;
2494 } while (--n_entries);
2495
2496 spin_lock_irq(&pipe_crc->lock);
2497 pipe_crc->tail = tail;
2498 spin_unlock_irq(&pipe_crc->lock);
2499
2500 return bytes_read;
2501 }
2502
2503 static const struct file_operations i915_pipe_crc_fops = {
2504 .owner = THIS_MODULE,
2505 .open = i915_pipe_crc_open,
2506 .read = i915_pipe_crc_read,
2507 .release = i915_pipe_crc_release,
2508 };
2509
2510 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
2511 {
2512 .name = "i915_pipe_A_crc",
2513 .pipe = PIPE_A,
2514 },
2515 {
2516 .name = "i915_pipe_B_crc",
2517 .pipe = PIPE_B,
2518 },
2519 {
2520 .name = "i915_pipe_C_crc",
2521 .pipe = PIPE_C,
2522 },
2523 };
2524
2525 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
2526 enum pipe pipe)
2527 {
2528 struct drm_device *dev = minor->dev;
2529 struct dentry *ent;
2530 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
2531
2532 info->dev = dev;
2533 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
2534 &i915_pipe_crc_fops);
2535 if (!ent)
2536 return -ENOMEM;
2537
2538 return drm_add_fake_info_node(minor, ent, info);
2539 }
2540
2541 static const char * const pipe_crc_sources[] = {
2542 "none",
2543 "plane1",
2544 "plane2",
2545 "pf",
2546 "pipe",
2547 "TV",
2548 "DP-B",
2549 "DP-C",
2550 "DP-D",
2551 "auto",
2552 };
2553
2554 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
2555 {
2556 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
2557 return pipe_crc_sources[source];
2558 }
2559
2560 static int display_crc_ctl_show(struct seq_file *m, void *data)
2561 {
2562 struct drm_device *dev = m->private;
2563 struct drm_i915_private *dev_priv = dev->dev_private;
2564 int i;
2565
2566 for (i = 0; i < I915_MAX_PIPES; i++)
2567 seq_printf(m, "%c %s\n", pipe_name(i),
2568 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
2569
2570 return 0;
2571 }
2572
2573 static int display_crc_ctl_open(struct inode *inode, struct file *file)
2574 {
2575 struct drm_device *dev = inode->i_private;
2576
2577 return single_open(file, display_crc_ctl_show, dev);
2578 }
2579
2580 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
2581 uint32_t *val)
2582 {
2583 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2584 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2585
2586 switch (*source) {
2587 case INTEL_PIPE_CRC_SOURCE_PIPE:
2588 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
2589 break;
2590 case INTEL_PIPE_CRC_SOURCE_NONE:
2591 *val = 0;
2592 break;
2593 default:
2594 return -EINVAL;
2595 }
2596
2597 return 0;
2598 }
2599
2600 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
2601 enum intel_pipe_crc_source *source)
2602 {
2603 struct intel_encoder *encoder;
2604 struct intel_crtc *crtc;
2605 struct intel_digital_port *dig_port;
2606 int ret = 0;
2607
2608 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2609
2610 drm_modeset_lock_all(dev);
2611 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2612 base.head) {
2613 if (!encoder->base.crtc)
2614 continue;
2615
2616 crtc = to_intel_crtc(encoder->base.crtc);
2617
2618 if (crtc->pipe != pipe)
2619 continue;
2620
2621 switch (encoder->type) {
2622 case INTEL_OUTPUT_TVOUT:
2623 *source = INTEL_PIPE_CRC_SOURCE_TV;
2624 break;
2625 case INTEL_OUTPUT_DISPLAYPORT:
2626 case INTEL_OUTPUT_EDP:
2627 dig_port = enc_to_dig_port(&encoder->base);
2628 switch (dig_port->port) {
2629 case PORT_B:
2630 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
2631 break;
2632 case PORT_C:
2633 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
2634 break;
2635 case PORT_D:
2636 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
2637 break;
2638 default:
2639 WARN(1, "nonexisting DP port %c\n",
2640 port_name(dig_port->port));
2641 break;
2642 }
2643 break;
2644 }
2645 }
2646 drm_modeset_unlock_all(dev);
2647
2648 return ret;
2649 }
2650
2651 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
2652 enum pipe pipe,
2653 enum intel_pipe_crc_source *source,
2654 uint32_t *val)
2655 {
2656 struct drm_i915_private *dev_priv = dev->dev_private;
2657 bool need_stable_symbols = false;
2658
2659 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2660 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2661 if (ret)
2662 return ret;
2663 }
2664
2665 switch (*source) {
2666 case INTEL_PIPE_CRC_SOURCE_PIPE:
2667 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
2668 break;
2669 case INTEL_PIPE_CRC_SOURCE_DP_B:
2670 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
2671 need_stable_symbols = true;
2672 break;
2673 case INTEL_PIPE_CRC_SOURCE_DP_C:
2674 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
2675 need_stable_symbols = true;
2676 break;
2677 case INTEL_PIPE_CRC_SOURCE_NONE:
2678 *val = 0;
2679 break;
2680 default:
2681 return -EINVAL;
2682 }
2683
2684 /*
2685 * When the pipe CRC tap point is after the transcoders we need
2686 * to tweak symbol-level features to produce a deterministic series of
2687 * symbols for a given frame. We need to reset those features only once
2688 * a frame (instead of every nth symbol):
2689 * - DC-balance: used to ensure a better clock recovery from the data
2690 * link (SDVO)
2691 * - DisplayPort scrambling: used for EMI reduction
2692 */
2693 if (need_stable_symbols) {
2694 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2695
2696 tmp |= DC_BALANCE_RESET_VLV;
2697 if (pipe == PIPE_A)
2698 tmp |= PIPE_A_SCRAMBLE_RESET;
2699 else
2700 tmp |= PIPE_B_SCRAMBLE_RESET;
2701
2702 I915_WRITE(PORT_DFT2_G4X, tmp);
2703 }
2704
2705 return 0;
2706 }
2707
2708 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
2709 enum pipe pipe,
2710 enum intel_pipe_crc_source *source,
2711 uint32_t *val)
2712 {
2713 struct drm_i915_private *dev_priv = dev->dev_private;
2714 bool need_stable_symbols = false;
2715
2716 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2717 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2718 if (ret)
2719 return ret;
2720 }
2721
2722 switch (*source) {
2723 case INTEL_PIPE_CRC_SOURCE_PIPE:
2724 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
2725 break;
2726 case INTEL_PIPE_CRC_SOURCE_TV:
2727 if (!SUPPORTS_TV(dev))
2728 return -EINVAL;
2729 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
2730 break;
2731 case INTEL_PIPE_CRC_SOURCE_DP_B:
2732 if (!IS_G4X(dev))
2733 return -EINVAL;
2734 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
2735 need_stable_symbols = true;
2736 break;
2737 case INTEL_PIPE_CRC_SOURCE_DP_C:
2738 if (!IS_G4X(dev))
2739 return -EINVAL;
2740 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
2741 need_stable_symbols = true;
2742 break;
2743 case INTEL_PIPE_CRC_SOURCE_DP_D:
2744 if (!IS_G4X(dev))
2745 return -EINVAL;
2746 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
2747 need_stable_symbols = true;
2748 break;
2749 case INTEL_PIPE_CRC_SOURCE_NONE:
2750 *val = 0;
2751 break;
2752 default:
2753 return -EINVAL;
2754 }
2755
2756 /*
2757 * When the pipe CRC tap point is after the transcoders we need
2758 * to tweak symbol-level features to produce a deterministic series of
2759 * symbols for a given frame. We need to reset those features only once
2760 * a frame (instead of every nth symbol):
2761 * - DC-balance: used to ensure a better clock recovery from the data
2762 * link (SDVO)
2763 * - DisplayPort scrambling: used for EMI reduction
2764 */
2765 if (need_stable_symbols) {
2766 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2767
2768 WARN_ON(!IS_G4X(dev));
2769
2770 I915_WRITE(PORT_DFT_I9XX,
2771 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
2772
2773 if (pipe == PIPE_A)
2774 tmp |= PIPE_A_SCRAMBLE_RESET;
2775 else
2776 tmp |= PIPE_B_SCRAMBLE_RESET;
2777
2778 I915_WRITE(PORT_DFT2_G4X, tmp);
2779 }
2780
2781 return 0;
2782 }
2783
2784 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
2785 enum pipe pipe)
2786 {
2787 struct drm_i915_private *dev_priv = dev->dev_private;
2788 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2789
2790 if (pipe == PIPE_A)
2791 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2792 else
2793 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2794 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
2795 tmp &= ~DC_BALANCE_RESET_VLV;
2796 I915_WRITE(PORT_DFT2_G4X, tmp);
2797
2798 }
2799
2800 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
2801 enum pipe pipe)
2802 {
2803 struct drm_i915_private *dev_priv = dev->dev_private;
2804 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2805
2806 if (pipe == PIPE_A)
2807 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2808 else
2809 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2810 I915_WRITE(PORT_DFT2_G4X, tmp);
2811
2812 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
2813 I915_WRITE(PORT_DFT_I9XX,
2814 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
2815 }
2816 }
2817
2818 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
2819 uint32_t *val)
2820 {
2821 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2822 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2823
2824 switch (*source) {
2825 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2826 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
2827 break;
2828 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2829 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
2830 break;
2831 case INTEL_PIPE_CRC_SOURCE_PIPE:
2832 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
2833 break;
2834 case INTEL_PIPE_CRC_SOURCE_NONE:
2835 *val = 0;
2836 break;
2837 default:
2838 return -EINVAL;
2839 }
2840
2841 return 0;
2842 }
2843
2844 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
2845 {
2846 struct drm_i915_private *dev_priv = dev->dev_private;
2847 struct intel_crtc *crtc =
2848 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
2849
2850 drm_modeset_lock_all(dev);
2851 /*
2852 * If we use the eDP transcoder we need to make sure that we don't
2853 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
2854 * relevant on hsw with pipe A when using the always-on power well
2855 * routing.
2856 */
2857 if (crtc->config.cpu_transcoder == TRANSCODER_EDP &&
2858 !crtc->config.pch_pfit.enabled) {
2859 crtc->config.pch_pfit.force_thru = true;
2860
2861 intel_display_power_get(dev_priv,
2862 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
2863
2864 dev_priv->display.crtc_disable(&crtc->base);
2865 dev_priv->display.crtc_enable(&crtc->base);
2866 }
2867 drm_modeset_unlock_all(dev);
2868 }
2869
2870 static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
2871 {
2872 struct drm_i915_private *dev_priv = dev->dev_private;
2873 struct intel_crtc *crtc =
2874 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
2875
2876 drm_modeset_lock_all(dev);
2877 /*
2878 * If we use the eDP transcoder we need to make sure that we don't
2879 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
2880 * relevant on hsw with pipe A when using the always-on power well
2881 * routing.
2882 */
2883 if (crtc->config.pch_pfit.force_thru) {
2884 crtc->config.pch_pfit.force_thru = false;
2885
2886 dev_priv->display.crtc_disable(&crtc->base);
2887 dev_priv->display.crtc_enable(&crtc->base);
2888
2889 intel_display_power_put(dev_priv,
2890 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
2891 }
2892 drm_modeset_unlock_all(dev);
2893 }
2894
2895 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
2896 enum pipe pipe,
2897 enum intel_pipe_crc_source *source,
2898 uint32_t *val)
2899 {
2900 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2901 *source = INTEL_PIPE_CRC_SOURCE_PF;
2902
2903 switch (*source) {
2904 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2905 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
2906 break;
2907 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2908 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
2909 break;
2910 case INTEL_PIPE_CRC_SOURCE_PF:
2911 if (IS_HASWELL(dev) && pipe == PIPE_A)
2912 hsw_trans_edp_pipe_A_crc_wa(dev);
2913
2914 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
2915 break;
2916 case INTEL_PIPE_CRC_SOURCE_NONE:
2917 *val = 0;
2918 break;
2919 default:
2920 return -EINVAL;
2921 }
2922
2923 return 0;
2924 }
2925
2926 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
2927 enum intel_pipe_crc_source source)
2928 {
2929 struct drm_i915_private *dev_priv = dev->dev_private;
2930 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
2931 u32 val = 0; /* shut up gcc */
2932 int ret;
2933
2934 if (pipe_crc->source == source)
2935 return 0;
2936
2937 /* forbid changing the source without going back to 'none' */
2938 if (pipe_crc->source && source)
2939 return -EINVAL;
2940
2941 if (IS_GEN2(dev))
2942 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
2943 else if (INTEL_INFO(dev)->gen < 5)
2944 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
2945 else if (IS_VALLEYVIEW(dev))
2946 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
2947 else if (IS_GEN5(dev) || IS_GEN6(dev))
2948 ret = ilk_pipe_crc_ctl_reg(&source, &val);
2949 else
2950 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
2951
2952 if (ret != 0)
2953 return ret;
2954
2955 /* none -> real source transition */
2956 if (source) {
2957 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
2958 pipe_name(pipe), pipe_crc_source_name(source));
2959
2960 pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) *
2961 INTEL_PIPE_CRC_ENTRIES_NR,
2962 GFP_KERNEL);
2963 if (!pipe_crc->entries)
2964 return -ENOMEM;
2965
2966 spin_lock_irq(&pipe_crc->lock);
2967 pipe_crc->head = 0;
2968 pipe_crc->tail = 0;
2969 spin_unlock_irq(&pipe_crc->lock);
2970 }
2971
2972 pipe_crc->source = source;
2973
2974 I915_WRITE(PIPE_CRC_CTL(pipe), val);
2975 POSTING_READ(PIPE_CRC_CTL(pipe));
2976
2977 /* real source -> none transition */
2978 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
2979 struct intel_pipe_crc_entry *entries;
2980 struct intel_crtc *crtc =
2981 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2982
2983 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
2984 pipe_name(pipe));
2985
2986 drm_modeset_lock(&crtc->base.mutex, NULL);
2987 if (crtc->active)
2988 intel_wait_for_vblank(dev, pipe);
2989 drm_modeset_unlock(&crtc->base.mutex);
2990
2991 spin_lock_irq(&pipe_crc->lock);
2992 entries = pipe_crc->entries;
2993 pipe_crc->entries = NULL;
2994 spin_unlock_irq(&pipe_crc->lock);
2995
2996 kfree(entries);
2997
2998 if (IS_G4X(dev))
2999 g4x_undo_pipe_scramble_reset(dev, pipe);
3000 else if (IS_VALLEYVIEW(dev))
3001 vlv_undo_pipe_scramble_reset(dev, pipe);
3002 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3003 hsw_undo_trans_edp_pipe_A_crc_wa(dev);
3004 }
3005
3006 return 0;
3007 }
3008
3009 /*
3010 * Parse pipe CRC command strings:
3011 * command: wsp* object wsp+ name wsp+ source wsp*
3012 * object: 'pipe'
3013 * name: (A | B | C)
3014 * source: (none | plane1 | plane2 | pf)
3015 * wsp: (#0x20 | #0x9 | #0xA)+
3016 *
3017 * eg.:
3018 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3019 * "pipe A none" -> Stop CRC
3020 */
3021 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
3022 {
3023 int n_words = 0;
3024
3025 while (*buf) {
3026 char *end;
3027
3028 /* skip leading white space */
3029 buf = skip_spaces(buf);
3030 if (!*buf)
3031 break; /* end of buffer */
3032
3033 /* find end of word */
3034 for (end = buf; *end && !isspace(*end); end++)
3035 ;
3036
3037 if (n_words == max_words) {
3038 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3039 max_words);
3040 return -EINVAL; /* ran out of words[] before bytes */
3041 }
3042
3043 if (*end)
3044 *end++ = '\0';
3045 words[n_words++] = buf;
3046 buf = end;
3047 }
3048
3049 return n_words;
3050 }
3051
3052 enum intel_pipe_crc_object {
3053 PIPE_CRC_OBJECT_PIPE,
3054 };
3055
3056 static const char * const pipe_crc_objects[] = {
3057 "pipe",
3058 };
3059
3060 static int
3061 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
3062 {
3063 int i;
3064
3065 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3066 if (!strcmp(buf, pipe_crc_objects[i])) {
3067 *o = i;
3068 return 0;
3069 }
3070
3071 return -EINVAL;
3072 }
3073
3074 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
3075 {
3076 const char name = buf[0];
3077
3078 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3079 return -EINVAL;
3080
3081 *pipe = name - 'A';
3082
3083 return 0;
3084 }
3085
3086 static int
3087 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
3088 {
3089 int i;
3090
3091 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3092 if (!strcmp(buf, pipe_crc_sources[i])) {
3093 *s = i;
3094 return 0;
3095 }
3096
3097 return -EINVAL;
3098 }
3099
3100 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
3101 {
3102 #define N_WORDS 3
3103 int n_words;
3104 char *words[N_WORDS];
3105 enum pipe pipe;
3106 enum intel_pipe_crc_object object;
3107 enum intel_pipe_crc_source source;
3108
3109 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
3110 if (n_words != N_WORDS) {
3111 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3112 N_WORDS);
3113 return -EINVAL;
3114 }
3115
3116 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
3117 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
3118 return -EINVAL;
3119 }
3120
3121 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
3122 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
3123 return -EINVAL;
3124 }
3125
3126 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
3127 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
3128 return -EINVAL;
3129 }
3130
3131 return pipe_crc_set_source(dev, pipe, source);
3132 }
3133
3134 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3135 size_t len, loff_t *offp)
3136 {
3137 struct seq_file *m = file->private_data;
3138 struct drm_device *dev = m->private;
3139 char *tmpbuf;
3140 int ret;
3141
3142 if (len == 0)
3143 return 0;
3144
3145 if (len > PAGE_SIZE - 1) {
3146 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3147 PAGE_SIZE);
3148 return -E2BIG;
3149 }
3150
3151 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3152 if (!tmpbuf)
3153 return -ENOMEM;
3154
3155 if (copy_from_user(tmpbuf, ubuf, len)) {
3156 ret = -EFAULT;
3157 goto out;
3158 }
3159 tmpbuf[len] = '\0';
3160
3161 ret = display_crc_ctl_parse(dev, tmpbuf, len);
3162
3163 out:
3164 kfree(tmpbuf);
3165 if (ret < 0)
3166 return ret;
3167
3168 *offp += len;
3169 return len;
3170 }
3171
3172 static const struct file_operations i915_display_crc_ctl_fops = {
3173 .owner = THIS_MODULE,
3174 .open = display_crc_ctl_open,
3175 .read = seq_read,
3176 .llseek = seq_lseek,
3177 .release = single_release,
3178 .write = display_crc_ctl_write
3179 };
3180
3181 static void wm_latency_show(struct seq_file *m, const uint16_t wm[5])
3182 {
3183 struct drm_device *dev = m->private;
3184 int num_levels = ilk_wm_max_level(dev) + 1;
3185 int level;
3186
3187 drm_modeset_lock_all(dev);
3188
3189 for (level = 0; level < num_levels; level++) {
3190 unsigned int latency = wm[level];
3191
3192 /* WM1+ latency values in 0.5us units */
3193 if (level > 0)
3194 latency *= 5;
3195
3196 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3197 level, wm[level],
3198 latency / 10, latency % 10);
3199 }
3200
3201 drm_modeset_unlock_all(dev);
3202 }
3203
3204 static int pri_wm_latency_show(struct seq_file *m, void *data)
3205 {
3206 struct drm_device *dev = m->private;
3207
3208 wm_latency_show(m, to_i915(dev)->wm.pri_latency);
3209
3210 return 0;
3211 }
3212
3213 static int spr_wm_latency_show(struct seq_file *m, void *data)
3214 {
3215 struct drm_device *dev = m->private;
3216
3217 wm_latency_show(m, to_i915(dev)->wm.spr_latency);
3218
3219 return 0;
3220 }
3221
3222 static int cur_wm_latency_show(struct seq_file *m, void *data)
3223 {
3224 struct drm_device *dev = m->private;
3225
3226 wm_latency_show(m, to_i915(dev)->wm.cur_latency);
3227
3228 return 0;
3229 }
3230
3231 static int pri_wm_latency_open(struct inode *inode, struct file *file)
3232 {
3233 struct drm_device *dev = inode->i_private;
3234
3235 if (!HAS_PCH_SPLIT(dev))
3236 return -ENODEV;
3237
3238 return single_open(file, pri_wm_latency_show, dev);
3239 }
3240
3241 static int spr_wm_latency_open(struct inode *inode, struct file *file)
3242 {
3243 struct drm_device *dev = inode->i_private;
3244
3245 if (!HAS_PCH_SPLIT(dev))
3246 return -ENODEV;
3247
3248 return single_open(file, spr_wm_latency_show, dev);
3249 }
3250
3251 static int cur_wm_latency_open(struct inode *inode, struct file *file)
3252 {
3253 struct drm_device *dev = inode->i_private;
3254
3255 if (!HAS_PCH_SPLIT(dev))
3256 return -ENODEV;
3257
3258 return single_open(file, cur_wm_latency_show, dev);
3259 }
3260
3261 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3262 size_t len, loff_t *offp, uint16_t wm[5])
3263 {
3264 struct seq_file *m = file->private_data;
3265 struct drm_device *dev = m->private;
3266 uint16_t new[5] = { 0 };
3267 int num_levels = ilk_wm_max_level(dev) + 1;
3268 int level;
3269 int ret;
3270 char tmp[32];
3271
3272 if (len >= sizeof(tmp))
3273 return -EINVAL;
3274
3275 if (copy_from_user(tmp, ubuf, len))
3276 return -EFAULT;
3277
3278 tmp[len] = '\0';
3279
3280 ret = sscanf(tmp, "%hu %hu %hu %hu %hu", &new[0], &new[1], &new[2], &new[3], &new[4]);
3281 if (ret != num_levels)
3282 return -EINVAL;
3283
3284 drm_modeset_lock_all(dev);
3285
3286 for (level = 0; level < num_levels; level++)
3287 wm[level] = new[level];
3288
3289 drm_modeset_unlock_all(dev);
3290
3291 return len;
3292 }
3293
3294
3295 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3296 size_t len, loff_t *offp)
3297 {
3298 struct seq_file *m = file->private_data;
3299 struct drm_device *dev = m->private;
3300
3301 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.pri_latency);
3302 }
3303
3304 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3305 size_t len, loff_t *offp)
3306 {
3307 struct seq_file *m = file->private_data;
3308 struct drm_device *dev = m->private;
3309
3310 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.spr_latency);
3311 }
3312
3313 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3314 size_t len, loff_t *offp)
3315 {
3316 struct seq_file *m = file->private_data;
3317 struct drm_device *dev = m->private;
3318
3319 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.cur_latency);
3320 }
3321
3322 static const struct file_operations i915_pri_wm_latency_fops = {
3323 .owner = THIS_MODULE,
3324 .open = pri_wm_latency_open,
3325 .read = seq_read,
3326 .llseek = seq_lseek,
3327 .release = single_release,
3328 .write = pri_wm_latency_write
3329 };
3330
3331 static const struct file_operations i915_spr_wm_latency_fops = {
3332 .owner = THIS_MODULE,
3333 .open = spr_wm_latency_open,
3334 .read = seq_read,
3335 .llseek = seq_lseek,
3336 .release = single_release,
3337 .write = spr_wm_latency_write
3338 };
3339
3340 static const struct file_operations i915_cur_wm_latency_fops = {
3341 .owner = THIS_MODULE,
3342 .open = cur_wm_latency_open,
3343 .read = seq_read,
3344 .llseek = seq_lseek,
3345 .release = single_release,
3346 .write = cur_wm_latency_write
3347 };
3348
3349 static int
3350 i915_wedged_get(void *data, u64 *val)
3351 {
3352 struct drm_device *dev = data;
3353 struct drm_i915_private *dev_priv = dev->dev_private;
3354
3355 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
3356
3357 return 0;
3358 }
3359
3360 static int
3361 i915_wedged_set(void *data, u64 val)
3362 {
3363 struct drm_device *dev = data;
3364 struct drm_i915_private *dev_priv = dev->dev_private;
3365
3366 intel_runtime_pm_get(dev_priv);
3367
3368 i915_handle_error(dev, val,
3369 "Manually setting wedged to %llu", val);
3370
3371 intel_runtime_pm_put(dev_priv);
3372
3373 return 0;
3374 }
3375
3376 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
3377 i915_wedged_get, i915_wedged_set,
3378 "%llu\n");
3379
3380 static int
3381 i915_ring_stop_get(void *data, u64 *val)
3382 {
3383 struct drm_device *dev = data;
3384 struct drm_i915_private *dev_priv = dev->dev_private;
3385
3386 *val = dev_priv->gpu_error.stop_rings;
3387
3388 return 0;
3389 }
3390
3391 static int
3392 i915_ring_stop_set(void *data, u64 val)
3393 {
3394 struct drm_device *dev = data;
3395 struct drm_i915_private *dev_priv = dev->dev_private;
3396 int ret;
3397
3398 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
3399
3400 ret = mutex_lock_interruptible(&dev->struct_mutex);
3401 if (ret)
3402 return ret;
3403
3404 dev_priv->gpu_error.stop_rings = val;
3405 mutex_unlock(&dev->struct_mutex);
3406
3407 return 0;
3408 }
3409
3410 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
3411 i915_ring_stop_get, i915_ring_stop_set,
3412 "0x%08llx\n");
3413
3414 static int
3415 i915_ring_missed_irq_get(void *data, u64 *val)
3416 {
3417 struct drm_device *dev = data;
3418 struct drm_i915_private *dev_priv = dev->dev_private;
3419
3420 *val = dev_priv->gpu_error.missed_irq_rings;
3421 return 0;
3422 }
3423
3424 static int
3425 i915_ring_missed_irq_set(void *data, u64 val)
3426 {
3427 struct drm_device *dev = data;
3428 struct drm_i915_private *dev_priv = dev->dev_private;
3429 int ret;
3430
3431 /* Lock against concurrent debugfs callers */
3432 ret = mutex_lock_interruptible(&dev->struct_mutex);
3433 if (ret)
3434 return ret;
3435 dev_priv->gpu_error.missed_irq_rings = val;
3436 mutex_unlock(&dev->struct_mutex);
3437
3438 return 0;
3439 }
3440
3441 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
3442 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
3443 "0x%08llx\n");
3444
3445 static int
3446 i915_ring_test_irq_get(void *data, u64 *val)
3447 {
3448 struct drm_device *dev = data;
3449 struct drm_i915_private *dev_priv = dev->dev_private;
3450
3451 *val = dev_priv->gpu_error.test_irq_rings;
3452
3453 return 0;
3454 }
3455
3456 static int
3457 i915_ring_test_irq_set(void *data, u64 val)
3458 {
3459 struct drm_device *dev = data;
3460 struct drm_i915_private *dev_priv = dev->dev_private;
3461 int ret;
3462
3463 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
3464
3465 /* Lock against concurrent debugfs callers */
3466 ret = mutex_lock_interruptible(&dev->struct_mutex);
3467 if (ret)
3468 return ret;
3469
3470 dev_priv->gpu_error.test_irq_rings = val;
3471 mutex_unlock(&dev->struct_mutex);
3472
3473 return 0;
3474 }
3475
3476 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
3477 i915_ring_test_irq_get, i915_ring_test_irq_set,
3478 "0x%08llx\n");
3479
3480 #define DROP_UNBOUND 0x1
3481 #define DROP_BOUND 0x2
3482 #define DROP_RETIRE 0x4
3483 #define DROP_ACTIVE 0x8
3484 #define DROP_ALL (DROP_UNBOUND | \
3485 DROP_BOUND | \
3486 DROP_RETIRE | \
3487 DROP_ACTIVE)
3488 static int
3489 i915_drop_caches_get(void *data, u64 *val)
3490 {
3491 *val = DROP_ALL;
3492
3493 return 0;
3494 }
3495
3496 static int
3497 i915_drop_caches_set(void *data, u64 val)
3498 {
3499 struct drm_device *dev = data;
3500 struct drm_i915_private *dev_priv = dev->dev_private;
3501 struct drm_i915_gem_object *obj, *next;
3502 struct i915_address_space *vm;
3503 struct i915_vma *vma, *x;
3504 int ret;
3505
3506 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
3507
3508 /* No need to check and wait for gpu resets, only libdrm auto-restarts
3509 * on ioctls on -EAGAIN. */
3510 ret = mutex_lock_interruptible(&dev->struct_mutex);
3511 if (ret)
3512 return ret;
3513
3514 if (val & DROP_ACTIVE) {
3515 ret = i915_gpu_idle(dev);
3516 if (ret)
3517 goto unlock;
3518 }
3519
3520 if (val & (DROP_RETIRE | DROP_ACTIVE))
3521 i915_gem_retire_requests(dev);
3522
3523 if (val & DROP_BOUND) {
3524 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
3525 list_for_each_entry_safe(vma, x, &vm->inactive_list,
3526 mm_list) {
3527 if (vma->pin_count)
3528 continue;
3529
3530 ret = i915_vma_unbind(vma);
3531 if (ret)
3532 goto unlock;
3533 }
3534 }
3535 }
3536
3537 if (val & DROP_UNBOUND) {
3538 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
3539 global_list)
3540 if (obj->pages_pin_count == 0) {
3541 ret = i915_gem_object_put_pages(obj);
3542 if (ret)
3543 goto unlock;
3544 }
3545 }
3546
3547 unlock:
3548 mutex_unlock(&dev->struct_mutex);
3549
3550 return ret;
3551 }
3552
3553 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
3554 i915_drop_caches_get, i915_drop_caches_set,
3555 "0x%08llx\n");
3556
3557 static int
3558 i915_max_freq_get(void *data, u64 *val)
3559 {
3560 struct drm_device *dev = data;
3561 struct drm_i915_private *dev_priv = dev->dev_private;
3562 int ret;
3563
3564 if (INTEL_INFO(dev)->gen < 6)
3565 return -ENODEV;
3566
3567 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3568
3569 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3570 if (ret)
3571 return ret;
3572
3573 if (IS_VALLEYVIEW(dev))
3574 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
3575 else
3576 *val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
3577 mutex_unlock(&dev_priv->rps.hw_lock);
3578
3579 return 0;
3580 }
3581
3582 static int
3583 i915_max_freq_set(void *data, u64 val)
3584 {
3585 struct drm_device *dev = data;
3586 struct drm_i915_private *dev_priv = dev->dev_private;
3587 u32 rp_state_cap, hw_max, hw_min;
3588 int ret;
3589
3590 if (INTEL_INFO(dev)->gen < 6)
3591 return -ENODEV;
3592
3593 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3594
3595 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
3596
3597 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3598 if (ret)
3599 return ret;
3600
3601 /*
3602 * Turbo will still be enabled, but won't go above the set value.
3603 */
3604 if (IS_VALLEYVIEW(dev)) {
3605 val = vlv_freq_opcode(dev_priv, val);
3606
3607 hw_max = valleyview_rps_max_freq(dev_priv);
3608 hw_min = valleyview_rps_min_freq(dev_priv);
3609 } else {
3610 do_div(val, GT_FREQUENCY_MULTIPLIER);
3611
3612 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3613 hw_max = dev_priv->rps.max_freq;
3614 hw_min = (rp_state_cap >> 16) & 0xff;
3615 }
3616
3617 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
3618 mutex_unlock(&dev_priv->rps.hw_lock);
3619 return -EINVAL;
3620 }
3621
3622 dev_priv->rps.max_freq_softlimit = val;
3623
3624 if (IS_VALLEYVIEW(dev))
3625 valleyview_set_rps(dev, val);
3626 else
3627 gen6_set_rps(dev, val);
3628
3629 mutex_unlock(&dev_priv->rps.hw_lock);
3630
3631 return 0;
3632 }
3633
3634 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
3635 i915_max_freq_get, i915_max_freq_set,
3636 "%llu\n");
3637
3638 static int
3639 i915_min_freq_get(void *data, u64 *val)
3640 {
3641 struct drm_device *dev = data;
3642 struct drm_i915_private *dev_priv = dev->dev_private;
3643 int ret;
3644
3645 if (INTEL_INFO(dev)->gen < 6)
3646 return -ENODEV;
3647
3648 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3649
3650 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3651 if (ret)
3652 return ret;
3653
3654 if (IS_VALLEYVIEW(dev))
3655 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
3656 else
3657 *val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
3658 mutex_unlock(&dev_priv->rps.hw_lock);
3659
3660 return 0;
3661 }
3662
3663 static int
3664 i915_min_freq_set(void *data, u64 val)
3665 {
3666 struct drm_device *dev = data;
3667 struct drm_i915_private *dev_priv = dev->dev_private;
3668 u32 rp_state_cap, hw_max, hw_min;
3669 int ret;
3670
3671 if (INTEL_INFO(dev)->gen < 6)
3672 return -ENODEV;
3673
3674 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3675
3676 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
3677
3678 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3679 if (ret)
3680 return ret;
3681
3682 /*
3683 * Turbo will still be enabled, but won't go below the set value.
3684 */
3685 if (IS_VALLEYVIEW(dev)) {
3686 val = vlv_freq_opcode(dev_priv, val);
3687
3688 hw_max = valleyview_rps_max_freq(dev_priv);
3689 hw_min = valleyview_rps_min_freq(dev_priv);
3690 } else {
3691 do_div(val, GT_FREQUENCY_MULTIPLIER);
3692
3693 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3694 hw_max = dev_priv->rps.max_freq;
3695 hw_min = (rp_state_cap >> 16) & 0xff;
3696 }
3697
3698 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
3699 mutex_unlock(&dev_priv->rps.hw_lock);
3700 return -EINVAL;
3701 }
3702
3703 dev_priv->rps.min_freq_softlimit = val;
3704
3705 if (IS_VALLEYVIEW(dev))
3706 valleyview_set_rps(dev, val);
3707 else
3708 gen6_set_rps(dev, val);
3709
3710 mutex_unlock(&dev_priv->rps.hw_lock);
3711
3712 return 0;
3713 }
3714
3715 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
3716 i915_min_freq_get, i915_min_freq_set,
3717 "%llu\n");
3718
3719 static int
3720 i915_cache_sharing_get(void *data, u64 *val)
3721 {
3722 struct drm_device *dev = data;
3723 struct drm_i915_private *dev_priv = dev->dev_private;
3724 u32 snpcr;
3725 int ret;
3726
3727 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3728 return -ENODEV;
3729
3730 ret = mutex_lock_interruptible(&dev->struct_mutex);
3731 if (ret)
3732 return ret;
3733 intel_runtime_pm_get(dev_priv);
3734
3735 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3736
3737 intel_runtime_pm_put(dev_priv);
3738 mutex_unlock(&dev_priv->dev->struct_mutex);
3739
3740 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
3741
3742 return 0;
3743 }
3744
3745 static int
3746 i915_cache_sharing_set(void *data, u64 val)
3747 {
3748 struct drm_device *dev = data;
3749 struct drm_i915_private *dev_priv = dev->dev_private;
3750 u32 snpcr;
3751
3752 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3753 return -ENODEV;
3754
3755 if (val > 3)
3756 return -EINVAL;
3757
3758 intel_runtime_pm_get(dev_priv);
3759 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
3760
3761 /* Update the cache sharing policy here as well */
3762 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3763 snpcr &= ~GEN6_MBC_SNPCR_MASK;
3764 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
3765 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3766
3767 intel_runtime_pm_put(dev_priv);
3768 return 0;
3769 }
3770
3771 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
3772 i915_cache_sharing_get, i915_cache_sharing_set,
3773 "%llu\n");
3774
3775 static int i915_forcewake_open(struct inode *inode, struct file *file)
3776 {
3777 struct drm_device *dev = inode->i_private;
3778 struct drm_i915_private *dev_priv = dev->dev_private;
3779
3780 if (INTEL_INFO(dev)->gen < 6)
3781 return 0;
3782
3783 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3784
3785 return 0;
3786 }
3787
3788 static int i915_forcewake_release(struct inode *inode, struct file *file)
3789 {
3790 struct drm_device *dev = inode->i_private;
3791 struct drm_i915_private *dev_priv = dev->dev_private;
3792
3793 if (INTEL_INFO(dev)->gen < 6)
3794 return 0;
3795
3796 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3797
3798 return 0;
3799 }
3800
3801 static const struct file_operations i915_forcewake_fops = {
3802 .owner = THIS_MODULE,
3803 .open = i915_forcewake_open,
3804 .release = i915_forcewake_release,
3805 };
3806
3807 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
3808 {
3809 struct drm_device *dev = minor->dev;
3810 struct dentry *ent;
3811
3812 ent = debugfs_create_file("i915_forcewake_user",
3813 S_IRUSR,
3814 root, dev,
3815 &i915_forcewake_fops);
3816 if (!ent)
3817 return -ENOMEM;
3818
3819 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
3820 }
3821
3822 static int i915_debugfs_create(struct dentry *root,
3823 struct drm_minor *minor,
3824 const char *name,
3825 const struct file_operations *fops)
3826 {
3827 struct drm_device *dev = minor->dev;
3828 struct dentry *ent;
3829
3830 ent = debugfs_create_file(name,
3831 S_IRUGO | S_IWUSR,
3832 root, dev,
3833 fops);
3834 if (!ent)
3835 return -ENOMEM;
3836
3837 return drm_add_fake_info_node(minor, ent, fops);
3838 }
3839
3840 static const struct drm_info_list i915_debugfs_list[] = {
3841 {"i915_capabilities", i915_capabilities, 0},
3842 {"i915_gem_objects", i915_gem_object_info, 0},
3843 {"i915_gem_gtt", i915_gem_gtt_info, 0},
3844 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
3845 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
3846 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
3847 {"i915_gem_stolen", i915_gem_stolen_list_info },
3848 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
3849 {"i915_gem_request", i915_gem_request_info, 0},
3850 {"i915_gem_seqno", i915_gem_seqno_info, 0},
3851 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
3852 {"i915_gem_interrupt", i915_interrupt_info, 0},
3853 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
3854 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
3855 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
3856 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
3857 {"i915_frequency_info", i915_frequency_info, 0},
3858 {"i915_drpc_info", i915_drpc_info, 0},
3859 {"i915_emon_status", i915_emon_status, 0},
3860 {"i915_ring_freq_table", i915_ring_freq_table, 0},
3861 {"i915_fbc_status", i915_fbc_status, 0},
3862 {"i915_ips_status", i915_ips_status, 0},
3863 {"i915_sr_status", i915_sr_status, 0},
3864 {"i915_opregion", i915_opregion, 0},
3865 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
3866 {"i915_context_status", i915_context_status, 0},
3867 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
3868 {"i915_swizzle_info", i915_swizzle_info, 0},
3869 {"i915_ppgtt_info", i915_ppgtt_info, 0},
3870 {"i915_llc", i915_llc, 0},
3871 {"i915_edp_psr_status", i915_edp_psr_status, 0},
3872 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
3873 {"i915_energy_uJ", i915_energy_uJ, 0},
3874 {"i915_pc8_status", i915_pc8_status, 0},
3875 {"i915_power_domain_info", i915_power_domain_info, 0},
3876 {"i915_display_info", i915_display_info, 0},
3877 {"i915_semaphore_status", i915_semaphore_status, 0},
3878 };
3879 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
3880
3881 static const struct i915_debugfs_files {
3882 const char *name;
3883 const struct file_operations *fops;
3884 } i915_debugfs_files[] = {
3885 {"i915_wedged", &i915_wedged_fops},
3886 {"i915_max_freq", &i915_max_freq_fops},
3887 {"i915_min_freq", &i915_min_freq_fops},
3888 {"i915_cache_sharing", &i915_cache_sharing_fops},
3889 {"i915_ring_stop", &i915_ring_stop_fops},
3890 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
3891 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
3892 {"i915_gem_drop_caches", &i915_drop_caches_fops},
3893 {"i915_error_state", &i915_error_state_fops},
3894 {"i915_next_seqno", &i915_next_seqno_fops},
3895 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
3896 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
3897 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
3898 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
3899 };
3900
3901 void intel_display_crc_init(struct drm_device *dev)
3902 {
3903 struct drm_i915_private *dev_priv = dev->dev_private;
3904 enum pipe pipe;
3905
3906 for_each_pipe(pipe) {
3907 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3908
3909 pipe_crc->opened = false;
3910 spin_lock_init(&pipe_crc->lock);
3911 init_waitqueue_head(&pipe_crc->wq);
3912 }
3913 }
3914
3915 int i915_debugfs_init(struct drm_minor *minor)
3916 {
3917 int ret, i;
3918
3919 ret = i915_forcewake_create(minor->debugfs_root, minor);
3920 if (ret)
3921 return ret;
3922
3923 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
3924 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
3925 if (ret)
3926 return ret;
3927 }
3928
3929 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3930 ret = i915_debugfs_create(minor->debugfs_root, minor,
3931 i915_debugfs_files[i].name,
3932 i915_debugfs_files[i].fops);
3933 if (ret)
3934 return ret;
3935 }
3936
3937 return drm_debugfs_create_files(i915_debugfs_list,
3938 I915_DEBUGFS_ENTRIES,
3939 minor->debugfs_root, minor);
3940 }
3941
3942 void i915_debugfs_cleanup(struct drm_minor *minor)
3943 {
3944 int i;
3945
3946 drm_debugfs_remove_files(i915_debugfs_list,
3947 I915_DEBUGFS_ENTRIES, minor);
3948
3949 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
3950 1, minor);
3951
3952 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
3953 struct drm_info_list *info_list =
3954 (struct drm_info_list *)&i915_pipe_crc_data[i];
3955
3956 drm_debugfs_remove_files(info_list, 1, minor);
3957 }
3958
3959 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3960 struct drm_info_list *info_list =
3961 (struct drm_info_list *) i915_debugfs_files[i].fops;
3962
3963 drm_debugfs_remove_files(info_list, 1, minor);
3964 }
3965 }
Linux kernel - Deliverables
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