2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
49 static const char *yesno(int v
)
51 return v
? "yes" : "no";
54 /* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
57 drm_add_fake_info_node(struct drm_minor
*minor
,
61 struct drm_info_node
*node
;
63 node
= kmalloc(sizeof(*node
), GFP_KERNEL
);
71 node
->info_ent
= (void *) key
;
73 mutex_lock(&minor
->debugfs_lock
);
74 list_add(&node
->list
, &minor
->debugfs_list
);
75 mutex_unlock(&minor
->debugfs_lock
);
80 static int i915_capabilities(struct seq_file
*m
, void *data
)
82 struct drm_info_node
*node
= m
->private;
83 struct drm_device
*dev
= node
->minor
->dev
;
84 const struct intel_device_info
*info
= INTEL_INFO(dev
);
86 seq_printf(m
, "gen: %d\n", info
->gen
);
87 seq_printf(m
, "pch: %d\n", INTEL_PCH_TYPE(dev
));
88 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89 #define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG
, SEP_SEMICOLON
);
97 static const char *get_pin_flag(struct drm_i915_gem_object
*obj
)
99 if (i915_gem_obj_is_pinned(obj
))
105 static const char *get_tiling_flag(struct drm_i915_gem_object
*obj
)
107 switch (obj
->tiling_mode
) {
109 case I915_TILING_NONE
: return " ";
110 case I915_TILING_X
: return "X";
111 case I915_TILING_Y
: return "Y";
115 static inline const char *get_global_flag(struct drm_i915_gem_object
*obj
)
117 return i915_gem_obj_to_ggtt(obj
) ? "g" : " ";
121 describe_obj(struct seq_file
*m
, struct drm_i915_gem_object
*obj
)
123 struct i915_vma
*vma
;
126 seq_printf(m
, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
129 get_tiling_flag(obj
),
130 get_global_flag(obj
),
131 obj
->base
.size
/ 1024,
132 obj
->base
.read_domains
,
133 obj
->base
.write_domain
,
134 i915_gem_request_get_seqno(obj
->last_read_req
),
135 i915_gem_request_get_seqno(obj
->last_write_req
),
136 i915_gem_request_get_seqno(obj
->last_fenced_req
),
137 i915_cache_level_str(to_i915(obj
->base
.dev
), obj
->cache_level
),
138 obj
->dirty
? " dirty" : "",
139 obj
->madv
== I915_MADV_DONTNEED
? " purgeable" : "");
141 seq_printf(m
, " (name: %d)", obj
->base
.name
);
142 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
143 if (vma
->pin_count
> 0)
145 seq_printf(m
, " (pinned x %d)", pin_count
);
146 if (obj
->pin_display
)
147 seq_printf(m
, " (display)");
148 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
)
149 seq_printf(m
, " (fence: %d)", obj
->fence_reg
);
150 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
151 if (!i915_is_ggtt(vma
->vm
))
155 seq_printf(m
, "gtt offset: %08lx, size: %08lx)",
156 vma
->node
.start
, vma
->node
.size
);
159 seq_printf(m
, " (stolen: %08lx)", obj
->stolen
->start
);
160 if (obj
->pin_mappable
|| obj
->fault_mappable
) {
162 if (obj
->pin_mappable
)
164 if (obj
->fault_mappable
)
167 seq_printf(m
, " (%s mappable)", s
);
169 if (obj
->last_read_req
!= NULL
)
170 seq_printf(m
, " (%s)",
171 i915_gem_request_get_ring(obj
->last_read_req
)->name
);
172 if (obj
->frontbuffer_bits
)
173 seq_printf(m
, " (frontbuffer: 0x%03x)", obj
->frontbuffer_bits
);
176 static void describe_ctx(struct seq_file
*m
, struct intel_context
*ctx
)
178 seq_putc(m
, ctx
->legacy_hw_ctx
.initialized
? 'I' : 'i');
179 seq_putc(m
, ctx
->remap_slice
? 'R' : 'r');
183 static int i915_gem_object_list_info(struct seq_file
*m
, void *data
)
185 struct drm_info_node
*node
= m
->private;
186 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
187 struct list_head
*head
;
188 struct drm_device
*dev
= node
->minor
->dev
;
189 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
190 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
191 struct i915_vma
*vma
;
192 size_t total_obj_size
, total_gtt_size
;
195 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
199 /* FIXME: the user of this interface might want more than just GGTT */
202 seq_puts(m
, "Active:\n");
203 head
= &vm
->active_list
;
206 seq_puts(m
, "Inactive:\n");
207 head
= &vm
->inactive_list
;
210 mutex_unlock(&dev
->struct_mutex
);
214 total_obj_size
= total_gtt_size
= count
= 0;
215 list_for_each_entry(vma
, head
, mm_list
) {
217 describe_obj(m
, vma
->obj
);
219 total_obj_size
+= vma
->obj
->base
.size
;
220 total_gtt_size
+= vma
->node
.size
;
223 mutex_unlock(&dev
->struct_mutex
);
225 seq_printf(m
, "Total %d objects, %zu bytes, %zu GTT size\n",
226 count
, total_obj_size
, total_gtt_size
);
230 static int obj_rank_by_stolen(void *priv
,
231 struct list_head
*A
, struct list_head
*B
)
233 struct drm_i915_gem_object
*a
=
234 container_of(A
, struct drm_i915_gem_object
, obj_exec_link
);
235 struct drm_i915_gem_object
*b
=
236 container_of(B
, struct drm_i915_gem_object
, obj_exec_link
);
238 return a
->stolen
->start
- b
->stolen
->start
;
241 static int i915_gem_stolen_list_info(struct seq_file
*m
, void *data
)
243 struct drm_info_node
*node
= m
->private;
244 struct drm_device
*dev
= node
->minor
->dev
;
245 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
246 struct drm_i915_gem_object
*obj
;
247 size_t total_obj_size
, total_gtt_size
;
251 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
255 total_obj_size
= total_gtt_size
= count
= 0;
256 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
257 if (obj
->stolen
== NULL
)
260 list_add(&obj
->obj_exec_link
, &stolen
);
262 total_obj_size
+= obj
->base
.size
;
263 total_gtt_size
+= i915_gem_obj_ggtt_size(obj
);
266 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
267 if (obj
->stolen
== NULL
)
270 list_add(&obj
->obj_exec_link
, &stolen
);
272 total_obj_size
+= obj
->base
.size
;
275 list_sort(NULL
, &stolen
, obj_rank_by_stolen
);
276 seq_puts(m
, "Stolen:\n");
277 while (!list_empty(&stolen
)) {
278 obj
= list_first_entry(&stolen
, typeof(*obj
), obj_exec_link
);
280 describe_obj(m
, obj
);
282 list_del_init(&obj
->obj_exec_link
);
284 mutex_unlock(&dev
->struct_mutex
);
286 seq_printf(m
, "Total %d objects, %zu bytes, %zu GTT size\n",
287 count
, total_obj_size
, total_gtt_size
);
291 #define count_objects(list, member) do { \
292 list_for_each_entry(obj, list, member) { \
293 size += i915_gem_obj_ggtt_size(obj); \
295 if (obj->map_and_fenceable) { \
296 mappable_size += i915_gem_obj_ggtt_size(obj); \
303 struct drm_i915_file_private
*file_priv
;
305 size_t total
, unbound
;
306 size_t global
, shared
;
307 size_t active
, inactive
;
310 static int per_file_stats(int id
, void *ptr
, void *data
)
312 struct drm_i915_gem_object
*obj
= ptr
;
313 struct file_stats
*stats
= data
;
314 struct i915_vma
*vma
;
317 stats
->total
+= obj
->base
.size
;
319 if (obj
->base
.name
|| obj
->base
.dma_buf
)
320 stats
->shared
+= obj
->base
.size
;
322 if (USES_FULL_PPGTT(obj
->base
.dev
)) {
323 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
324 struct i915_hw_ppgtt
*ppgtt
;
326 if (!drm_mm_node_allocated(&vma
->node
))
329 if (i915_is_ggtt(vma
->vm
)) {
330 stats
->global
+= obj
->base
.size
;
334 ppgtt
= container_of(vma
->vm
, struct i915_hw_ppgtt
, base
);
335 if (ppgtt
->file_priv
!= stats
->file_priv
)
338 if (obj
->active
) /* XXX per-vma statistic */
339 stats
->active
+= obj
->base
.size
;
341 stats
->inactive
+= obj
->base
.size
;
346 if (i915_gem_obj_ggtt_bound(obj
)) {
347 stats
->global
+= obj
->base
.size
;
349 stats
->active
+= obj
->base
.size
;
351 stats
->inactive
+= obj
->base
.size
;
356 if (!list_empty(&obj
->global_list
))
357 stats
->unbound
+= obj
->base
.size
;
362 #define count_vmas(list, member) do { \
363 list_for_each_entry(vma, list, member) { \
364 size += i915_gem_obj_ggtt_size(vma->obj); \
366 if (vma->obj->map_and_fenceable) { \
367 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
373 static int i915_gem_object_info(struct seq_file
*m
, void* data
)
375 struct drm_info_node
*node
= m
->private;
376 struct drm_device
*dev
= node
->minor
->dev
;
377 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
378 u32 count
, mappable_count
, purgeable_count
;
379 size_t size
, mappable_size
, purgeable_size
;
380 struct drm_i915_gem_object
*obj
;
381 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
382 struct drm_file
*file
;
383 struct i915_vma
*vma
;
386 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
390 seq_printf(m
, "%u objects, %zu bytes\n",
391 dev_priv
->mm
.object_count
,
392 dev_priv
->mm
.object_memory
);
394 size
= count
= mappable_size
= mappable_count
= 0;
395 count_objects(&dev_priv
->mm
.bound_list
, global_list
);
396 seq_printf(m
, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
397 count
, mappable_count
, size
, mappable_size
);
399 size
= count
= mappable_size
= mappable_count
= 0;
400 count_vmas(&vm
->active_list
, mm_list
);
401 seq_printf(m
, " %u [%u] active objects, %zu [%zu] bytes\n",
402 count
, mappable_count
, size
, mappable_size
);
404 size
= count
= mappable_size
= mappable_count
= 0;
405 count_vmas(&vm
->inactive_list
, mm_list
);
406 seq_printf(m
, " %u [%u] inactive objects, %zu [%zu] bytes\n",
407 count
, mappable_count
, size
, mappable_size
);
409 size
= count
= purgeable_size
= purgeable_count
= 0;
410 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
411 size
+= obj
->base
.size
, ++count
;
412 if (obj
->madv
== I915_MADV_DONTNEED
)
413 purgeable_size
+= obj
->base
.size
, ++purgeable_count
;
415 seq_printf(m
, "%u unbound objects, %zu bytes\n", count
, size
);
417 size
= count
= mappable_size
= mappable_count
= 0;
418 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
419 if (obj
->fault_mappable
) {
420 size
+= i915_gem_obj_ggtt_size(obj
);
423 if (obj
->pin_mappable
) {
424 mappable_size
+= i915_gem_obj_ggtt_size(obj
);
427 if (obj
->madv
== I915_MADV_DONTNEED
) {
428 purgeable_size
+= obj
->base
.size
;
432 seq_printf(m
, "%u purgeable objects, %zu bytes\n",
433 purgeable_count
, purgeable_size
);
434 seq_printf(m
, "%u pinned mappable objects, %zu bytes\n",
435 mappable_count
, mappable_size
);
436 seq_printf(m
, "%u fault mappable objects, %zu bytes\n",
439 seq_printf(m
, "%zu [%lu] gtt total\n",
440 dev_priv
->gtt
.base
.total
,
441 dev_priv
->gtt
.mappable_end
- dev_priv
->gtt
.base
.start
);
444 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
445 struct file_stats stats
;
446 struct task_struct
*task
;
448 memset(&stats
, 0, sizeof(stats
));
449 stats
.file_priv
= file
->driver_priv
;
450 spin_lock(&file
->table_lock
);
451 idr_for_each(&file
->object_idr
, per_file_stats
, &stats
);
452 spin_unlock(&file
->table_lock
);
454 * Although we have a valid reference on file->pid, that does
455 * not guarantee that the task_struct who called get_pid() is
456 * still alive (e.g. get_pid(current) => fork() => exit()).
457 * Therefore, we need to protect this ->comm access using RCU.
460 task
= pid_task(file
->pid
, PIDTYPE_PID
);
461 seq_printf(m
, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n",
462 task
? task
->comm
: "<unknown>",
473 mutex_unlock(&dev
->struct_mutex
);
478 static int i915_gem_gtt_info(struct seq_file
*m
, void *data
)
480 struct drm_info_node
*node
= m
->private;
481 struct drm_device
*dev
= node
->minor
->dev
;
482 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
483 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
484 struct drm_i915_gem_object
*obj
;
485 size_t total_obj_size
, total_gtt_size
;
488 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
492 total_obj_size
= total_gtt_size
= count
= 0;
493 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
494 if (list
== PINNED_LIST
&& !i915_gem_obj_is_pinned(obj
))
498 describe_obj(m
, obj
);
500 total_obj_size
+= obj
->base
.size
;
501 total_gtt_size
+= i915_gem_obj_ggtt_size(obj
);
505 mutex_unlock(&dev
->struct_mutex
);
507 seq_printf(m
, "Total %d objects, %zu bytes, %zu GTT size\n",
508 count
, total_obj_size
, total_gtt_size
);
513 static int i915_gem_pageflip_info(struct seq_file
*m
, void *data
)
515 struct drm_info_node
*node
= m
->private;
516 struct drm_device
*dev
= node
->minor
->dev
;
517 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
518 struct intel_crtc
*crtc
;
521 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
525 for_each_intel_crtc(dev
, crtc
) {
526 const char pipe
= pipe_name(crtc
->pipe
);
527 const char plane
= plane_name(crtc
->plane
);
528 struct intel_unpin_work
*work
;
530 spin_lock_irq(&dev
->event_lock
);
531 work
= crtc
->unpin_work
;
533 seq_printf(m
, "No flip due on pipe %c (plane %c)\n",
538 if (atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
539 seq_printf(m
, "Flip queued on pipe %c (plane %c)\n",
542 seq_printf(m
, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
545 if (work
->flip_queued_req
) {
546 struct intel_engine_cs
*ring
=
547 i915_gem_request_get_ring(work
->flip_queued_req
);
549 seq_printf(m
, "Flip queued on %s at seqno %u, next seqno %u [current breadcrumb %u], completed? %d\n",
551 i915_gem_request_get_seqno(work
->flip_queued_req
),
552 dev_priv
->next_seqno
,
553 ring
->get_seqno(ring
, true),
554 i915_gem_request_completed(work
->flip_queued_req
, true));
556 seq_printf(m
, "Flip not associated with any ring\n");
557 seq_printf(m
, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
558 work
->flip_queued_vblank
,
559 work
->flip_ready_vblank
,
560 drm_vblank_count(dev
, crtc
->pipe
));
561 if (work
->enable_stall_check
)
562 seq_puts(m
, "Stall check enabled, ");
564 seq_puts(m
, "Stall check waiting for page flip ioctl, ");
565 seq_printf(m
, "%d prepares\n", atomic_read(&work
->pending
));
567 if (INTEL_INFO(dev
)->gen
>= 4)
568 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(crtc
->plane
)));
570 addr
= I915_READ(DSPADDR(crtc
->plane
));
571 seq_printf(m
, "Current scanout address 0x%08x\n", addr
);
573 if (work
->pending_flip_obj
) {
574 seq_printf(m
, "New framebuffer address 0x%08lx\n", (long)work
->gtt_offset
);
575 seq_printf(m
, "MMIO update completed? %d\n", addr
== work
->gtt_offset
);
578 spin_unlock_irq(&dev
->event_lock
);
581 mutex_unlock(&dev
->struct_mutex
);
586 static int i915_gem_request_info(struct seq_file
*m
, void *data
)
588 struct drm_info_node
*node
= m
->private;
589 struct drm_device
*dev
= node
->minor
->dev
;
590 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
591 struct intel_engine_cs
*ring
;
592 struct drm_i915_gem_request
*gem_request
;
595 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
600 for_each_ring(ring
, dev_priv
, i
) {
601 if (list_empty(&ring
->request_list
))
604 seq_printf(m
, "%s requests:\n", ring
->name
);
605 list_for_each_entry(gem_request
,
608 seq_printf(m
, " %d @ %d\n",
610 (int) (jiffies
- gem_request
->emitted_jiffies
));
614 mutex_unlock(&dev
->struct_mutex
);
617 seq_puts(m
, "No requests\n");
622 static void i915_ring_seqno_info(struct seq_file
*m
,
623 struct intel_engine_cs
*ring
)
625 if (ring
->get_seqno
) {
626 seq_printf(m
, "Current sequence (%s): %u\n",
627 ring
->name
, ring
->get_seqno(ring
, false));
631 static int i915_gem_seqno_info(struct seq_file
*m
, void *data
)
633 struct drm_info_node
*node
= m
->private;
634 struct drm_device
*dev
= node
->minor
->dev
;
635 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
636 struct intel_engine_cs
*ring
;
639 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
642 intel_runtime_pm_get(dev_priv
);
644 for_each_ring(ring
, dev_priv
, i
)
645 i915_ring_seqno_info(m
, ring
);
647 intel_runtime_pm_put(dev_priv
);
648 mutex_unlock(&dev
->struct_mutex
);
654 static int i915_interrupt_info(struct seq_file
*m
, void *data
)
656 struct drm_info_node
*node
= m
->private;
657 struct drm_device
*dev
= node
->minor
->dev
;
658 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
659 struct intel_engine_cs
*ring
;
662 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
665 intel_runtime_pm_get(dev_priv
);
667 if (IS_CHERRYVIEW(dev
)) {
668 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
669 I915_READ(GEN8_MASTER_IRQ
));
671 seq_printf(m
, "Display IER:\t%08x\n",
673 seq_printf(m
, "Display IIR:\t%08x\n",
675 seq_printf(m
, "Display IIR_RW:\t%08x\n",
676 I915_READ(VLV_IIR_RW
));
677 seq_printf(m
, "Display IMR:\t%08x\n",
679 for_each_pipe(dev_priv
, pipe
)
680 seq_printf(m
, "Pipe %c stat:\t%08x\n",
682 I915_READ(PIPESTAT(pipe
)));
684 seq_printf(m
, "Port hotplug:\t%08x\n",
685 I915_READ(PORT_HOTPLUG_EN
));
686 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
687 I915_READ(VLV_DPFLIPSTAT
));
688 seq_printf(m
, "DPINVGTT:\t%08x\n",
689 I915_READ(DPINVGTT
));
691 for (i
= 0; i
< 4; i
++) {
692 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
693 i
, I915_READ(GEN8_GT_IMR(i
)));
694 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
695 i
, I915_READ(GEN8_GT_IIR(i
)));
696 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
697 i
, I915_READ(GEN8_GT_IER(i
)));
700 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
701 I915_READ(GEN8_PCU_IMR
));
702 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
703 I915_READ(GEN8_PCU_IIR
));
704 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
705 I915_READ(GEN8_PCU_IER
));
706 } else if (INTEL_INFO(dev
)->gen
>= 8) {
707 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
708 I915_READ(GEN8_MASTER_IRQ
));
710 for (i
= 0; i
< 4; i
++) {
711 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
712 i
, I915_READ(GEN8_GT_IMR(i
)));
713 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
714 i
, I915_READ(GEN8_GT_IIR(i
)));
715 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
716 i
, I915_READ(GEN8_GT_IER(i
)));
719 for_each_pipe(dev_priv
, pipe
) {
720 if (!intel_display_power_is_enabled(dev_priv
,
721 POWER_DOMAIN_PIPE(pipe
))) {
722 seq_printf(m
, "Pipe %c power disabled\n",
726 seq_printf(m
, "Pipe %c IMR:\t%08x\n",
728 I915_READ(GEN8_DE_PIPE_IMR(pipe
)));
729 seq_printf(m
, "Pipe %c IIR:\t%08x\n",
731 I915_READ(GEN8_DE_PIPE_IIR(pipe
)));
732 seq_printf(m
, "Pipe %c IER:\t%08x\n",
734 I915_READ(GEN8_DE_PIPE_IER(pipe
)));
737 seq_printf(m
, "Display Engine port interrupt mask:\t%08x\n",
738 I915_READ(GEN8_DE_PORT_IMR
));
739 seq_printf(m
, "Display Engine port interrupt identity:\t%08x\n",
740 I915_READ(GEN8_DE_PORT_IIR
));
741 seq_printf(m
, "Display Engine port interrupt enable:\t%08x\n",
742 I915_READ(GEN8_DE_PORT_IER
));
744 seq_printf(m
, "Display Engine misc interrupt mask:\t%08x\n",
745 I915_READ(GEN8_DE_MISC_IMR
));
746 seq_printf(m
, "Display Engine misc interrupt identity:\t%08x\n",
747 I915_READ(GEN8_DE_MISC_IIR
));
748 seq_printf(m
, "Display Engine misc interrupt enable:\t%08x\n",
749 I915_READ(GEN8_DE_MISC_IER
));
751 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
752 I915_READ(GEN8_PCU_IMR
));
753 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
754 I915_READ(GEN8_PCU_IIR
));
755 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
756 I915_READ(GEN8_PCU_IER
));
757 } else if (IS_VALLEYVIEW(dev
)) {
758 seq_printf(m
, "Display IER:\t%08x\n",
760 seq_printf(m
, "Display IIR:\t%08x\n",
762 seq_printf(m
, "Display IIR_RW:\t%08x\n",
763 I915_READ(VLV_IIR_RW
));
764 seq_printf(m
, "Display IMR:\t%08x\n",
766 for_each_pipe(dev_priv
, pipe
)
767 seq_printf(m
, "Pipe %c stat:\t%08x\n",
769 I915_READ(PIPESTAT(pipe
)));
771 seq_printf(m
, "Master IER:\t%08x\n",
772 I915_READ(VLV_MASTER_IER
));
774 seq_printf(m
, "Render IER:\t%08x\n",
776 seq_printf(m
, "Render IIR:\t%08x\n",
778 seq_printf(m
, "Render IMR:\t%08x\n",
781 seq_printf(m
, "PM IER:\t\t%08x\n",
782 I915_READ(GEN6_PMIER
));
783 seq_printf(m
, "PM IIR:\t\t%08x\n",
784 I915_READ(GEN6_PMIIR
));
785 seq_printf(m
, "PM IMR:\t\t%08x\n",
786 I915_READ(GEN6_PMIMR
));
788 seq_printf(m
, "Port hotplug:\t%08x\n",
789 I915_READ(PORT_HOTPLUG_EN
));
790 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
791 I915_READ(VLV_DPFLIPSTAT
));
792 seq_printf(m
, "DPINVGTT:\t%08x\n",
793 I915_READ(DPINVGTT
));
795 } else if (!HAS_PCH_SPLIT(dev
)) {
796 seq_printf(m
, "Interrupt enable: %08x\n",
798 seq_printf(m
, "Interrupt identity: %08x\n",
800 seq_printf(m
, "Interrupt mask: %08x\n",
802 for_each_pipe(dev_priv
, pipe
)
803 seq_printf(m
, "Pipe %c stat: %08x\n",
805 I915_READ(PIPESTAT(pipe
)));
807 seq_printf(m
, "North Display Interrupt enable: %08x\n",
809 seq_printf(m
, "North Display Interrupt identity: %08x\n",
811 seq_printf(m
, "North Display Interrupt mask: %08x\n",
813 seq_printf(m
, "South Display Interrupt enable: %08x\n",
815 seq_printf(m
, "South Display Interrupt identity: %08x\n",
817 seq_printf(m
, "South Display Interrupt mask: %08x\n",
819 seq_printf(m
, "Graphics Interrupt enable: %08x\n",
821 seq_printf(m
, "Graphics Interrupt identity: %08x\n",
823 seq_printf(m
, "Graphics Interrupt mask: %08x\n",
826 for_each_ring(ring
, dev_priv
, i
) {
827 if (INTEL_INFO(dev
)->gen
>= 6) {
829 "Graphics Interrupt mask (%s): %08x\n",
830 ring
->name
, I915_READ_IMR(ring
));
832 i915_ring_seqno_info(m
, ring
);
834 intel_runtime_pm_put(dev_priv
);
835 mutex_unlock(&dev
->struct_mutex
);
840 static int i915_gem_fence_regs_info(struct seq_file
*m
, void *data
)
842 struct drm_info_node
*node
= m
->private;
843 struct drm_device
*dev
= node
->minor
->dev
;
844 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
847 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
851 seq_printf(m
, "Reserved fences = %d\n", dev_priv
->fence_reg_start
);
852 seq_printf(m
, "Total fences = %d\n", dev_priv
->num_fence_regs
);
853 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
854 struct drm_i915_gem_object
*obj
= dev_priv
->fence_regs
[i
].obj
;
856 seq_printf(m
, "Fence %d, pin count = %d, object = ",
857 i
, dev_priv
->fence_regs
[i
].pin_count
);
859 seq_puts(m
, "unused");
861 describe_obj(m
, obj
);
865 mutex_unlock(&dev
->struct_mutex
);
869 static int i915_hws_info(struct seq_file
*m
, void *data
)
871 struct drm_info_node
*node
= m
->private;
872 struct drm_device
*dev
= node
->minor
->dev
;
873 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
874 struct intel_engine_cs
*ring
;
878 ring
= &dev_priv
->ring
[(uintptr_t)node
->info_ent
->data
];
879 hws
= ring
->status_page
.page_addr
;
883 for (i
= 0; i
< 4096 / sizeof(u32
) / 4; i
+= 4) {
884 seq_printf(m
, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
886 hws
[i
], hws
[i
+ 1], hws
[i
+ 2], hws
[i
+ 3]);
892 i915_error_state_write(struct file
*filp
,
893 const char __user
*ubuf
,
897 struct i915_error_state_file_priv
*error_priv
= filp
->private_data
;
898 struct drm_device
*dev
= error_priv
->dev
;
901 DRM_DEBUG_DRIVER("Resetting error state\n");
903 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
907 i915_destroy_error_state(dev
);
908 mutex_unlock(&dev
->struct_mutex
);
913 static int i915_error_state_open(struct inode
*inode
, struct file
*file
)
915 struct drm_device
*dev
= inode
->i_private
;
916 struct i915_error_state_file_priv
*error_priv
;
918 error_priv
= kzalloc(sizeof(*error_priv
), GFP_KERNEL
);
922 error_priv
->dev
= dev
;
924 i915_error_state_get(dev
, error_priv
);
926 file
->private_data
= error_priv
;
931 static int i915_error_state_release(struct inode
*inode
, struct file
*file
)
933 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
935 i915_error_state_put(error_priv
);
941 static ssize_t
i915_error_state_read(struct file
*file
, char __user
*userbuf
,
942 size_t count
, loff_t
*pos
)
944 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
945 struct drm_i915_error_state_buf error_str
;
947 ssize_t ret_count
= 0;
950 ret
= i915_error_state_buf_init(&error_str
, to_i915(error_priv
->dev
), count
, *pos
);
954 ret
= i915_error_state_to_str(&error_str
, error_priv
);
958 ret_count
= simple_read_from_buffer(userbuf
, count
, &tmp_pos
,
965 *pos
= error_str
.start
+ ret_count
;
967 i915_error_state_buf_release(&error_str
);
968 return ret
?: ret_count
;
971 static const struct file_operations i915_error_state_fops
= {
972 .owner
= THIS_MODULE
,
973 .open
= i915_error_state_open
,
974 .read
= i915_error_state_read
,
975 .write
= i915_error_state_write
,
976 .llseek
= default_llseek
,
977 .release
= i915_error_state_release
,
981 i915_next_seqno_get(void *data
, u64
*val
)
983 struct drm_device
*dev
= data
;
984 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
987 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
991 *val
= dev_priv
->next_seqno
;
992 mutex_unlock(&dev
->struct_mutex
);
998 i915_next_seqno_set(void *data
, u64 val
)
1000 struct drm_device
*dev
= data
;
1003 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1007 ret
= i915_gem_set_seqno(dev
, val
);
1008 mutex_unlock(&dev
->struct_mutex
);
1013 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops
,
1014 i915_next_seqno_get
, i915_next_seqno_set
,
1017 static int i915_frequency_info(struct seq_file
*m
, void *unused
)
1019 struct drm_info_node
*node
= m
->private;
1020 struct drm_device
*dev
= node
->minor
->dev
;
1021 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1024 intel_runtime_pm_get(dev_priv
);
1026 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
1029 u16 rgvswctl
= I915_READ16(MEMSWCTL
);
1030 u16 rgvstat
= I915_READ16(MEMSTAT_ILK
);
1032 seq_printf(m
, "Requested P-state: %d\n", (rgvswctl
>> 8) & 0xf);
1033 seq_printf(m
, "Requested VID: %d\n", rgvswctl
& 0x3f);
1034 seq_printf(m
, "Current VID: %d\n", (rgvstat
& MEMSTAT_VID_MASK
) >>
1036 seq_printf(m
, "Current P-state: %d\n",
1037 (rgvstat
& MEMSTAT_PSTATE_MASK
) >> MEMSTAT_PSTATE_SHIFT
);
1038 } else if (IS_GEN6(dev
) || (IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) ||
1039 IS_BROADWELL(dev
)) {
1040 u32 gt_perf_status
= I915_READ(GEN6_GT_PERF_STATUS
);
1041 u32 rp_state_limits
= I915_READ(GEN6_RP_STATE_LIMITS
);
1042 u32 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
1043 u32 rpmodectl
, rpinclimit
, rpdeclimit
;
1044 u32 rpstat
, cagf
, reqf
;
1045 u32 rpupei
, rpcurup
, rpprevup
;
1046 u32 rpdownei
, rpcurdown
, rpprevdown
;
1047 u32 pm_ier
, pm_imr
, pm_isr
, pm_iir
, pm_mask
;
1050 /* RPSTAT1 is in the GT power well */
1051 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1055 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
1057 reqf
= I915_READ(GEN6_RPNSWREQ
);
1058 reqf
&= ~GEN6_TURBO_DISABLE
;
1059 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1063 reqf
*= GT_FREQUENCY_MULTIPLIER
;
1065 rpmodectl
= I915_READ(GEN6_RP_CONTROL
);
1066 rpinclimit
= I915_READ(GEN6_RP_UP_THRESHOLD
);
1067 rpdeclimit
= I915_READ(GEN6_RP_DOWN_THRESHOLD
);
1069 rpstat
= I915_READ(GEN6_RPSTAT1
);
1070 rpupei
= I915_READ(GEN6_RP_CUR_UP_EI
);
1071 rpcurup
= I915_READ(GEN6_RP_CUR_UP
);
1072 rpprevup
= I915_READ(GEN6_RP_PREV_UP
);
1073 rpdownei
= I915_READ(GEN6_RP_CUR_DOWN_EI
);
1074 rpcurdown
= I915_READ(GEN6_RP_CUR_DOWN
);
1075 rpprevdown
= I915_READ(GEN6_RP_PREV_DOWN
);
1076 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1077 cagf
= (rpstat
& HSW_CAGF_MASK
) >> HSW_CAGF_SHIFT
;
1079 cagf
= (rpstat
& GEN6_CAGF_MASK
) >> GEN6_CAGF_SHIFT
;
1080 cagf
*= GT_FREQUENCY_MULTIPLIER
;
1082 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
1083 mutex_unlock(&dev
->struct_mutex
);
1085 if (IS_GEN6(dev
) || IS_GEN7(dev
)) {
1086 pm_ier
= I915_READ(GEN6_PMIER
);
1087 pm_imr
= I915_READ(GEN6_PMIMR
);
1088 pm_isr
= I915_READ(GEN6_PMISR
);
1089 pm_iir
= I915_READ(GEN6_PMIIR
);
1090 pm_mask
= I915_READ(GEN6_PMINTRMSK
);
1092 pm_ier
= I915_READ(GEN8_GT_IER(2));
1093 pm_imr
= I915_READ(GEN8_GT_IMR(2));
1094 pm_isr
= I915_READ(GEN8_GT_ISR(2));
1095 pm_iir
= I915_READ(GEN8_GT_IIR(2));
1096 pm_mask
= I915_READ(GEN6_PMINTRMSK
);
1098 seq_printf(m
, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1099 pm_ier
, pm_imr
, pm_isr
, pm_iir
, pm_mask
);
1100 seq_printf(m
, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status
);
1101 seq_printf(m
, "Render p-state ratio: %d\n",
1102 (gt_perf_status
& 0xff00) >> 8);
1103 seq_printf(m
, "Render p-state VID: %d\n",
1104 gt_perf_status
& 0xff);
1105 seq_printf(m
, "Render p-state limit: %d\n",
1106 rp_state_limits
& 0xff);
1107 seq_printf(m
, "RPSTAT1: 0x%08x\n", rpstat
);
1108 seq_printf(m
, "RPMODECTL: 0x%08x\n", rpmodectl
);
1109 seq_printf(m
, "RPINCLIMIT: 0x%08x\n", rpinclimit
);
1110 seq_printf(m
, "RPDECLIMIT: 0x%08x\n", rpdeclimit
);
1111 seq_printf(m
, "RPNSWREQ: %dMHz\n", reqf
);
1112 seq_printf(m
, "CAGF: %dMHz\n", cagf
);
1113 seq_printf(m
, "RP CUR UP EI: %dus\n", rpupei
&
1114 GEN6_CURICONT_MASK
);
1115 seq_printf(m
, "RP CUR UP: %dus\n", rpcurup
&
1116 GEN6_CURBSYTAVG_MASK
);
1117 seq_printf(m
, "RP PREV UP: %dus\n", rpprevup
&
1118 GEN6_CURBSYTAVG_MASK
);
1119 seq_printf(m
, "RP CUR DOWN EI: %dus\n", rpdownei
&
1121 seq_printf(m
, "RP CUR DOWN: %dus\n", rpcurdown
&
1122 GEN6_CURBSYTAVG_MASK
);
1123 seq_printf(m
, "RP PREV DOWN: %dus\n", rpprevdown
&
1124 GEN6_CURBSYTAVG_MASK
);
1126 max_freq
= (rp_state_cap
& 0xff0000) >> 16;
1127 seq_printf(m
, "Lowest (RPN) frequency: %dMHz\n",
1128 max_freq
* GT_FREQUENCY_MULTIPLIER
);
1130 max_freq
= (rp_state_cap
& 0xff00) >> 8;
1131 seq_printf(m
, "Nominal (RP1) frequency: %dMHz\n",
1132 max_freq
* GT_FREQUENCY_MULTIPLIER
);
1134 max_freq
= rp_state_cap
& 0xff;
1135 seq_printf(m
, "Max non-overclocked (RP0) frequency: %dMHz\n",
1136 max_freq
* GT_FREQUENCY_MULTIPLIER
);
1138 seq_printf(m
, "Max overclocked frequency: %dMHz\n",
1139 dev_priv
->rps
.max_freq
* GT_FREQUENCY_MULTIPLIER
);
1140 } else if (IS_VALLEYVIEW(dev
)) {
1143 mutex_lock(&dev_priv
->rps
.hw_lock
);
1144 freq_sts
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
1145 seq_printf(m
, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts
);
1146 seq_printf(m
, "DDR freq: %d MHz\n", dev_priv
->mem_freq
);
1148 seq_printf(m
, "max GPU freq: %d MHz\n",
1149 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1151 seq_printf(m
, "min GPU freq: %d MHz\n",
1152 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
));
1154 seq_printf(m
, "efficient (RPe) frequency: %d MHz\n",
1155 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
));
1157 seq_printf(m
, "current GPU freq: %d MHz\n",
1158 vlv_gpu_freq(dev_priv
, (freq_sts
>> 8) & 0xff));
1159 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1161 seq_puts(m
, "no P-state info available\n");
1165 intel_runtime_pm_put(dev_priv
);
1169 static int ironlake_drpc_info(struct seq_file
*m
)
1171 struct drm_info_node
*node
= m
->private;
1172 struct drm_device
*dev
= node
->minor
->dev
;
1173 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1174 u32 rgvmodectl
, rstdbyctl
;
1178 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1181 intel_runtime_pm_get(dev_priv
);
1183 rgvmodectl
= I915_READ(MEMMODECTL
);
1184 rstdbyctl
= I915_READ(RSTDBYCTL
);
1185 crstandvid
= I915_READ16(CRSTANDVID
);
1187 intel_runtime_pm_put(dev_priv
);
1188 mutex_unlock(&dev
->struct_mutex
);
1190 seq_printf(m
, "HD boost: %s\n", (rgvmodectl
& MEMMODE_BOOST_EN
) ?
1192 seq_printf(m
, "Boost freq: %d\n",
1193 (rgvmodectl
& MEMMODE_BOOST_FREQ_MASK
) >>
1194 MEMMODE_BOOST_FREQ_SHIFT
);
1195 seq_printf(m
, "HW control enabled: %s\n",
1196 rgvmodectl
& MEMMODE_HWIDLE_EN
? "yes" : "no");
1197 seq_printf(m
, "SW control enabled: %s\n",
1198 rgvmodectl
& MEMMODE_SWMODE_EN
? "yes" : "no");
1199 seq_printf(m
, "Gated voltage change: %s\n",
1200 rgvmodectl
& MEMMODE_RCLK_GATE
? "yes" : "no");
1201 seq_printf(m
, "Starting frequency: P%d\n",
1202 (rgvmodectl
& MEMMODE_FSTART_MASK
) >> MEMMODE_FSTART_SHIFT
);
1203 seq_printf(m
, "Max P-state: P%d\n",
1204 (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
);
1205 seq_printf(m
, "Min P-state: P%d\n", (rgvmodectl
& MEMMODE_FMIN_MASK
));
1206 seq_printf(m
, "RS1 VID: %d\n", (crstandvid
& 0x3f));
1207 seq_printf(m
, "RS2 VID: %d\n", ((crstandvid
>> 8) & 0x3f));
1208 seq_printf(m
, "Render standby enabled: %s\n",
1209 (rstdbyctl
& RCX_SW_EXIT
) ? "no" : "yes");
1210 seq_puts(m
, "Current RS state: ");
1211 switch (rstdbyctl
& RSX_STATUS_MASK
) {
1213 seq_puts(m
, "on\n");
1215 case RSX_STATUS_RC1
:
1216 seq_puts(m
, "RC1\n");
1218 case RSX_STATUS_RC1E
:
1219 seq_puts(m
, "RC1E\n");
1221 case RSX_STATUS_RS1
:
1222 seq_puts(m
, "RS1\n");
1224 case RSX_STATUS_RS2
:
1225 seq_puts(m
, "RS2 (RC6)\n");
1227 case RSX_STATUS_RS3
:
1228 seq_puts(m
, "RC3 (RC6+)\n");
1231 seq_puts(m
, "unknown\n");
1238 static int vlv_drpc_info(struct seq_file
*m
)
1241 struct drm_info_node
*node
= m
->private;
1242 struct drm_device
*dev
= node
->minor
->dev
;
1243 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1244 u32 rpmodectl1
, rcctl1
, pw_status
;
1245 unsigned fw_rendercount
= 0, fw_mediacount
= 0;
1247 intel_runtime_pm_get(dev_priv
);
1249 pw_status
= I915_READ(VLV_GTLC_PW_STATUS
);
1250 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1251 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1253 intel_runtime_pm_put(dev_priv
);
1255 seq_printf(m
, "Video Turbo Mode: %s\n",
1256 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1257 seq_printf(m
, "Turbo enabled: %s\n",
1258 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1259 seq_printf(m
, "HW control enabled: %s\n",
1260 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1261 seq_printf(m
, "SW control enabled: %s\n",
1262 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1263 GEN6_RP_MEDIA_SW_MODE
));
1264 seq_printf(m
, "RC6 Enabled: %s\n",
1265 yesno(rcctl1
& (GEN7_RC_CTL_TO_MODE
|
1266 GEN6_RC_CTL_EI_MODE(1))));
1267 seq_printf(m
, "Render Power Well: %s\n",
1268 (pw_status
& VLV_GTLC_PW_RENDER_STATUS_MASK
) ? "Up" : "Down");
1269 seq_printf(m
, "Media Power Well: %s\n",
1270 (pw_status
& VLV_GTLC_PW_MEDIA_STATUS_MASK
) ? "Up" : "Down");
1272 seq_printf(m
, "Render RC6 residency since boot: %u\n",
1273 I915_READ(VLV_GT_RENDER_RC6
));
1274 seq_printf(m
, "Media RC6 residency since boot: %u\n",
1275 I915_READ(VLV_GT_MEDIA_RC6
));
1277 spin_lock_irq(&dev_priv
->uncore
.lock
);
1278 fw_rendercount
= dev_priv
->uncore
.fw_rendercount
;
1279 fw_mediacount
= dev_priv
->uncore
.fw_mediacount
;
1280 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1282 seq_printf(m
, "Forcewake Render Count = %u\n", fw_rendercount
);
1283 seq_printf(m
, "Forcewake Media Count = %u\n", fw_mediacount
);
1290 static int gen6_drpc_info(struct seq_file
*m
)
1293 struct drm_info_node
*node
= m
->private;
1294 struct drm_device
*dev
= node
->minor
->dev
;
1295 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1296 u32 rpmodectl1
, gt_core_status
, rcctl1
, rc6vids
= 0;
1297 unsigned forcewake_count
;
1300 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1303 intel_runtime_pm_get(dev_priv
);
1305 spin_lock_irq(&dev_priv
->uncore
.lock
);
1306 forcewake_count
= dev_priv
->uncore
.forcewake_count
;
1307 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1309 if (forcewake_count
) {
1310 seq_puts(m
, "RC information inaccurate because somebody "
1311 "holds a forcewake reference \n");
1313 /* NB: we cannot use forcewake, else we read the wrong values */
1314 while (count
++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK
) & 1))
1316 seq_printf(m
, "RC information accurate: %s\n", yesno(count
< 51));
1319 gt_core_status
= readl(dev_priv
->regs
+ GEN6_GT_CORE_STATUS
);
1320 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS
, gt_core_status
, 4, true);
1322 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1323 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1324 mutex_unlock(&dev
->struct_mutex
);
1325 mutex_lock(&dev_priv
->rps
.hw_lock
);
1326 sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
1327 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1329 intel_runtime_pm_put(dev_priv
);
1331 seq_printf(m
, "Video Turbo Mode: %s\n",
1332 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1333 seq_printf(m
, "HW control enabled: %s\n",
1334 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1335 seq_printf(m
, "SW control enabled: %s\n",
1336 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1337 GEN6_RP_MEDIA_SW_MODE
));
1338 seq_printf(m
, "RC1e Enabled: %s\n",
1339 yesno(rcctl1
& GEN6_RC_CTL_RC1e_ENABLE
));
1340 seq_printf(m
, "RC6 Enabled: %s\n",
1341 yesno(rcctl1
& GEN6_RC_CTL_RC6_ENABLE
));
1342 seq_printf(m
, "Deep RC6 Enabled: %s\n",
1343 yesno(rcctl1
& GEN6_RC_CTL_RC6p_ENABLE
));
1344 seq_printf(m
, "Deepest RC6 Enabled: %s\n",
1345 yesno(rcctl1
& GEN6_RC_CTL_RC6pp_ENABLE
));
1346 seq_puts(m
, "Current RC state: ");
1347 switch (gt_core_status
& GEN6_RCn_MASK
) {
1349 if (gt_core_status
& GEN6_CORE_CPD_STATE_MASK
)
1350 seq_puts(m
, "Core Power Down\n");
1352 seq_puts(m
, "on\n");
1355 seq_puts(m
, "RC3\n");
1358 seq_puts(m
, "RC6\n");
1361 seq_puts(m
, "RC7\n");
1364 seq_puts(m
, "Unknown\n");
1368 seq_printf(m
, "Core Power Down: %s\n",
1369 yesno(gt_core_status
& GEN6_CORE_CPD_STATE_MASK
));
1371 /* Not exactly sure what this is */
1372 seq_printf(m
, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1373 I915_READ(GEN6_GT_GFX_RC6_LOCKED
));
1374 seq_printf(m
, "RC6 residency since boot: %u\n",
1375 I915_READ(GEN6_GT_GFX_RC6
));
1376 seq_printf(m
, "RC6+ residency since boot: %u\n",
1377 I915_READ(GEN6_GT_GFX_RC6p
));
1378 seq_printf(m
, "RC6++ residency since boot: %u\n",
1379 I915_READ(GEN6_GT_GFX_RC6pp
));
1381 seq_printf(m
, "RC6 voltage: %dmV\n",
1382 GEN6_DECODE_RC6_VID(((rc6vids
>> 0) & 0xff)));
1383 seq_printf(m
, "RC6+ voltage: %dmV\n",
1384 GEN6_DECODE_RC6_VID(((rc6vids
>> 8) & 0xff)));
1385 seq_printf(m
, "RC6++ voltage: %dmV\n",
1386 GEN6_DECODE_RC6_VID(((rc6vids
>> 16) & 0xff)));
1390 static int i915_drpc_info(struct seq_file
*m
, void *unused
)
1392 struct drm_info_node
*node
= m
->private;
1393 struct drm_device
*dev
= node
->minor
->dev
;
1395 if (IS_VALLEYVIEW(dev
))
1396 return vlv_drpc_info(m
);
1397 else if (INTEL_INFO(dev
)->gen
>= 6)
1398 return gen6_drpc_info(m
);
1400 return ironlake_drpc_info(m
);
1403 static int i915_fbc_status(struct seq_file
*m
, void *unused
)
1405 struct drm_info_node
*node
= m
->private;
1406 struct drm_device
*dev
= node
->minor
->dev
;
1407 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1409 if (!HAS_FBC(dev
)) {
1410 seq_puts(m
, "FBC unsupported on this chipset\n");
1414 intel_runtime_pm_get(dev_priv
);
1416 if (intel_fbc_enabled(dev
)) {
1417 seq_puts(m
, "FBC enabled\n");
1419 seq_puts(m
, "FBC disabled: ");
1420 switch (dev_priv
->fbc
.no_fbc_reason
) {
1422 seq_puts(m
, "FBC actived, but currently disabled in hardware");
1424 case FBC_UNSUPPORTED
:
1425 seq_puts(m
, "unsupported by this chipset");
1428 seq_puts(m
, "no outputs");
1430 case FBC_STOLEN_TOO_SMALL
:
1431 seq_puts(m
, "not enough stolen memory");
1433 case FBC_UNSUPPORTED_MODE
:
1434 seq_puts(m
, "mode not supported");
1436 case FBC_MODE_TOO_LARGE
:
1437 seq_puts(m
, "mode too large");
1440 seq_puts(m
, "FBC unsupported on plane");
1443 seq_puts(m
, "scanout buffer not tiled");
1445 case FBC_MULTIPLE_PIPES
:
1446 seq_puts(m
, "multiple pipes are enabled");
1448 case FBC_MODULE_PARAM
:
1449 seq_puts(m
, "disabled per module param (default off)");
1451 case FBC_CHIP_DEFAULT
:
1452 seq_puts(m
, "disabled per chip default");
1455 seq_puts(m
, "unknown reason");
1460 intel_runtime_pm_put(dev_priv
);
1465 static int i915_fbc_fc_get(void *data
, u64
*val
)
1467 struct drm_device
*dev
= data
;
1468 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1470 if (INTEL_INFO(dev
)->gen
< 7 || !HAS_FBC(dev
))
1473 drm_modeset_lock_all(dev
);
1474 *val
= dev_priv
->fbc
.false_color
;
1475 drm_modeset_unlock_all(dev
);
1480 static int i915_fbc_fc_set(void *data
, u64 val
)
1482 struct drm_device
*dev
= data
;
1483 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1486 if (INTEL_INFO(dev
)->gen
< 7 || !HAS_FBC(dev
))
1489 drm_modeset_lock_all(dev
);
1491 reg
= I915_READ(ILK_DPFC_CONTROL
);
1492 dev_priv
->fbc
.false_color
= val
;
1494 I915_WRITE(ILK_DPFC_CONTROL
, val
?
1495 (reg
| FBC_CTL_FALSE_COLOR
) :
1496 (reg
& ~FBC_CTL_FALSE_COLOR
));
1498 drm_modeset_unlock_all(dev
);
1502 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops
,
1503 i915_fbc_fc_get
, i915_fbc_fc_set
,
1506 static int i915_ips_status(struct seq_file
*m
, void *unused
)
1508 struct drm_info_node
*node
= m
->private;
1509 struct drm_device
*dev
= node
->minor
->dev
;
1510 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1512 if (!HAS_IPS(dev
)) {
1513 seq_puts(m
, "not supported\n");
1517 intel_runtime_pm_get(dev_priv
);
1519 seq_printf(m
, "Enabled by kernel parameter: %s\n",
1520 yesno(i915
.enable_ips
));
1522 if (INTEL_INFO(dev
)->gen
>= 8) {
1523 seq_puts(m
, "Currently: unknown\n");
1525 if (I915_READ(IPS_CTL
) & IPS_ENABLE
)
1526 seq_puts(m
, "Currently: enabled\n");
1528 seq_puts(m
, "Currently: disabled\n");
1531 intel_runtime_pm_put(dev_priv
);
1536 static int i915_sr_status(struct seq_file
*m
, void *unused
)
1538 struct drm_info_node
*node
= m
->private;
1539 struct drm_device
*dev
= node
->minor
->dev
;
1540 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1541 bool sr_enabled
= false;
1543 intel_runtime_pm_get(dev_priv
);
1545 if (HAS_PCH_SPLIT(dev
))
1546 sr_enabled
= I915_READ(WM1_LP_ILK
) & WM1_LP_SR_EN
;
1547 else if (IS_CRESTLINE(dev
) || IS_I945G(dev
) || IS_I945GM(dev
))
1548 sr_enabled
= I915_READ(FW_BLC_SELF
) & FW_BLC_SELF_EN
;
1549 else if (IS_I915GM(dev
))
1550 sr_enabled
= I915_READ(INSTPM
) & INSTPM_SELF_EN
;
1551 else if (IS_PINEVIEW(dev
))
1552 sr_enabled
= I915_READ(DSPFW3
) & PINEVIEW_SELF_REFRESH_EN
;
1554 intel_runtime_pm_put(dev_priv
);
1556 seq_printf(m
, "self-refresh: %s\n",
1557 sr_enabled
? "enabled" : "disabled");
1562 static int i915_emon_status(struct seq_file
*m
, void *unused
)
1564 struct drm_info_node
*node
= m
->private;
1565 struct drm_device
*dev
= node
->minor
->dev
;
1566 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1567 unsigned long temp
, chipset
, gfx
;
1573 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1577 temp
= i915_mch_val(dev_priv
);
1578 chipset
= i915_chipset_val(dev_priv
);
1579 gfx
= i915_gfx_val(dev_priv
);
1580 mutex_unlock(&dev
->struct_mutex
);
1582 seq_printf(m
, "GMCH temp: %ld\n", temp
);
1583 seq_printf(m
, "Chipset power: %ld\n", chipset
);
1584 seq_printf(m
, "GFX power: %ld\n", gfx
);
1585 seq_printf(m
, "Total power: %ld\n", chipset
+ gfx
);
1590 static int i915_ring_freq_table(struct seq_file
*m
, void *unused
)
1592 struct drm_info_node
*node
= m
->private;
1593 struct drm_device
*dev
= node
->minor
->dev
;
1594 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1596 int gpu_freq
, ia_freq
;
1598 if (!(IS_GEN6(dev
) || IS_GEN7(dev
))) {
1599 seq_puts(m
, "unsupported on this chipset\n");
1603 intel_runtime_pm_get(dev_priv
);
1605 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
1607 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
1611 seq_puts(m
, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1613 for (gpu_freq
= dev_priv
->rps
.min_freq_softlimit
;
1614 gpu_freq
<= dev_priv
->rps
.max_freq_softlimit
;
1617 sandybridge_pcode_read(dev_priv
,
1618 GEN6_PCODE_READ_MIN_FREQ_TABLE
,
1620 seq_printf(m
, "%d\t\t%d\t\t\t\t%d\n",
1621 gpu_freq
* GT_FREQUENCY_MULTIPLIER
,
1622 ((ia_freq
>> 0) & 0xff) * 100,
1623 ((ia_freq
>> 8) & 0xff) * 100);
1626 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1629 intel_runtime_pm_put(dev_priv
);
1633 static int i915_opregion(struct seq_file
*m
, void *unused
)
1635 struct drm_info_node
*node
= m
->private;
1636 struct drm_device
*dev
= node
->minor
->dev
;
1637 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1638 struct intel_opregion
*opregion
= &dev_priv
->opregion
;
1639 void *data
= kmalloc(OPREGION_SIZE
, GFP_KERNEL
);
1645 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1649 if (opregion
->header
) {
1650 memcpy_fromio(data
, opregion
->header
, OPREGION_SIZE
);
1651 seq_write(m
, data
, OPREGION_SIZE
);
1654 mutex_unlock(&dev
->struct_mutex
);
1661 static int i915_gem_framebuffer_info(struct seq_file
*m
, void *data
)
1663 struct drm_info_node
*node
= m
->private;
1664 struct drm_device
*dev
= node
->minor
->dev
;
1665 struct intel_fbdev
*ifbdev
= NULL
;
1666 struct intel_framebuffer
*fb
;
1668 #ifdef CONFIG_DRM_I915_FBDEV
1669 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1671 ifbdev
= dev_priv
->fbdev
;
1672 fb
= to_intel_framebuffer(ifbdev
->helper
.fb
);
1674 seq_printf(m
, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1678 fb
->base
.bits_per_pixel
,
1679 atomic_read(&fb
->base
.refcount
.refcount
));
1680 describe_obj(m
, fb
->obj
);
1684 mutex_lock(&dev
->mode_config
.fb_lock
);
1685 list_for_each_entry(fb
, &dev
->mode_config
.fb_list
, base
.head
) {
1686 if (ifbdev
&& &fb
->base
== ifbdev
->helper
.fb
)
1689 seq_printf(m
, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1693 fb
->base
.bits_per_pixel
,
1694 atomic_read(&fb
->base
.refcount
.refcount
));
1695 describe_obj(m
, fb
->obj
);
1698 mutex_unlock(&dev
->mode_config
.fb_lock
);
1703 static void describe_ctx_ringbuf(struct seq_file
*m
,
1704 struct intel_ringbuffer
*ringbuf
)
1706 seq_printf(m
, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1707 ringbuf
->space
, ringbuf
->head
, ringbuf
->tail
,
1708 ringbuf
->last_retired_head
);
1711 static int i915_context_status(struct seq_file
*m
, void *unused
)
1713 struct drm_info_node
*node
= m
->private;
1714 struct drm_device
*dev
= node
->minor
->dev
;
1715 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1716 struct intel_engine_cs
*ring
;
1717 struct intel_context
*ctx
;
1720 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1724 if (dev_priv
->ips
.pwrctx
) {
1725 seq_puts(m
, "power context ");
1726 describe_obj(m
, dev_priv
->ips
.pwrctx
);
1730 if (dev_priv
->ips
.renderctx
) {
1731 seq_puts(m
, "render context ");
1732 describe_obj(m
, dev_priv
->ips
.renderctx
);
1736 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
1737 if (!i915
.enable_execlists
&&
1738 ctx
->legacy_hw_ctx
.rcs_state
== NULL
)
1741 seq_puts(m
, "HW context ");
1742 describe_ctx(m
, ctx
);
1743 for_each_ring(ring
, dev_priv
, i
) {
1744 if (ring
->default_context
== ctx
)
1745 seq_printf(m
, "(default context %s) ",
1749 if (i915
.enable_execlists
) {
1751 for_each_ring(ring
, dev_priv
, i
) {
1752 struct drm_i915_gem_object
*ctx_obj
=
1753 ctx
->engine
[i
].state
;
1754 struct intel_ringbuffer
*ringbuf
=
1755 ctx
->engine
[i
].ringbuf
;
1757 seq_printf(m
, "%s: ", ring
->name
);
1759 describe_obj(m
, ctx_obj
);
1761 describe_ctx_ringbuf(m
, ringbuf
);
1765 describe_obj(m
, ctx
->legacy_hw_ctx
.rcs_state
);
1771 mutex_unlock(&dev
->struct_mutex
);
1776 static void i915_dump_lrc_obj(struct seq_file
*m
,
1777 struct intel_engine_cs
*ring
,
1778 struct drm_i915_gem_object
*ctx_obj
)
1781 uint32_t *reg_state
;
1783 unsigned long ggtt_offset
= 0;
1785 if (ctx_obj
== NULL
) {
1786 seq_printf(m
, "Context on %s with no gem object\n",
1791 seq_printf(m
, "CONTEXT: %s %u\n", ring
->name
,
1792 intel_execlists_ctx_id(ctx_obj
));
1794 if (!i915_gem_obj_ggtt_bound(ctx_obj
))
1795 seq_puts(m
, "\tNot bound in GGTT\n");
1797 ggtt_offset
= i915_gem_obj_ggtt_offset(ctx_obj
);
1799 if (i915_gem_object_get_pages(ctx_obj
)) {
1800 seq_puts(m
, "\tFailed to get pages for context object\n");
1804 page
= i915_gem_object_get_page(ctx_obj
, 1);
1805 if (!WARN_ON(page
== NULL
)) {
1806 reg_state
= kmap_atomic(page
);
1808 for (j
= 0; j
< 0x600 / sizeof(u32
) / 4; j
+= 4) {
1809 seq_printf(m
, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1810 ggtt_offset
+ 4096 + (j
* 4),
1811 reg_state
[j
], reg_state
[j
+ 1],
1812 reg_state
[j
+ 2], reg_state
[j
+ 3]);
1814 kunmap_atomic(reg_state
);
1820 static int i915_dump_lrc(struct seq_file
*m
, void *unused
)
1822 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1823 struct drm_device
*dev
= node
->minor
->dev
;
1824 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1825 struct intel_engine_cs
*ring
;
1826 struct intel_context
*ctx
;
1829 if (!i915
.enable_execlists
) {
1830 seq_printf(m
, "Logical Ring Contexts are disabled\n");
1834 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1838 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
1839 for_each_ring(ring
, dev_priv
, i
) {
1840 if (ring
->default_context
!= ctx
)
1841 i915_dump_lrc_obj(m
, ring
,
1842 ctx
->engine
[i
].state
);
1846 mutex_unlock(&dev
->struct_mutex
);
1851 static int i915_execlists(struct seq_file
*m
, void *data
)
1853 struct drm_info_node
*node
= (struct drm_info_node
*)m
->private;
1854 struct drm_device
*dev
= node
->minor
->dev
;
1855 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1856 struct intel_engine_cs
*ring
;
1862 struct list_head
*cursor
;
1866 if (!i915
.enable_execlists
) {
1867 seq_puts(m
, "Logical Ring Contexts are disabled\n");
1871 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1875 intel_runtime_pm_get(dev_priv
);
1877 for_each_ring(ring
, dev_priv
, ring_id
) {
1878 struct intel_ctx_submit_request
*head_req
= NULL
;
1880 unsigned long flags
;
1882 seq_printf(m
, "%s\n", ring
->name
);
1884 status
= I915_READ(RING_EXECLIST_STATUS(ring
));
1885 ctx_id
= I915_READ(RING_EXECLIST_STATUS(ring
) + 4);
1886 seq_printf(m
, "\tExeclist status: 0x%08X, context: %u\n",
1889 status_pointer
= I915_READ(RING_CONTEXT_STATUS_PTR(ring
));
1890 seq_printf(m
, "\tStatus pointer: 0x%08X\n", status_pointer
);
1892 read_pointer
= ring
->next_context_status_buffer
;
1893 write_pointer
= status_pointer
& 0x07;
1894 if (read_pointer
> write_pointer
)
1896 seq_printf(m
, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
1897 read_pointer
, write_pointer
);
1899 for (i
= 0; i
< 6; i
++) {
1900 status
= I915_READ(RING_CONTEXT_STATUS_BUF(ring
) + 8*i
);
1901 ctx_id
= I915_READ(RING_CONTEXT_STATUS_BUF(ring
) + 8*i
+ 4);
1903 seq_printf(m
, "\tStatus buffer %d: 0x%08X, context: %u\n",
1907 spin_lock_irqsave(&ring
->execlist_lock
, flags
);
1908 list_for_each(cursor
, &ring
->execlist_queue
)
1910 head_req
= list_first_entry_or_null(&ring
->execlist_queue
,
1911 struct intel_ctx_submit_request
, execlist_link
);
1912 spin_unlock_irqrestore(&ring
->execlist_lock
, flags
);
1914 seq_printf(m
, "\t%d requests in queue\n", count
);
1916 struct drm_i915_gem_object
*ctx_obj
;
1918 ctx_obj
= head_req
->ctx
->engine
[ring_id
].state
;
1919 seq_printf(m
, "\tHead request id: %u\n",
1920 intel_execlists_ctx_id(ctx_obj
));
1921 seq_printf(m
, "\tHead request tail: %u\n",
1928 intel_runtime_pm_put(dev_priv
);
1929 mutex_unlock(&dev
->struct_mutex
);
1934 static int i915_gen6_forcewake_count_info(struct seq_file
*m
, void *data
)
1936 struct drm_info_node
*node
= m
->private;
1937 struct drm_device
*dev
= node
->minor
->dev
;
1938 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1939 unsigned forcewake_count
= 0, fw_rendercount
= 0, fw_mediacount
= 0;
1941 spin_lock_irq(&dev_priv
->uncore
.lock
);
1942 if (IS_VALLEYVIEW(dev
)) {
1943 fw_rendercount
= dev_priv
->uncore
.fw_rendercount
;
1944 fw_mediacount
= dev_priv
->uncore
.fw_mediacount
;
1946 forcewake_count
= dev_priv
->uncore
.forcewake_count
;
1947 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1949 if (IS_VALLEYVIEW(dev
)) {
1950 seq_printf(m
, "fw_rendercount = %u\n", fw_rendercount
);
1951 seq_printf(m
, "fw_mediacount = %u\n", fw_mediacount
);
1953 seq_printf(m
, "forcewake count = %u\n", forcewake_count
);
1958 static const char *swizzle_string(unsigned swizzle
)
1961 case I915_BIT_6_SWIZZLE_NONE
:
1963 case I915_BIT_6_SWIZZLE_9
:
1965 case I915_BIT_6_SWIZZLE_9_10
:
1966 return "bit9/bit10";
1967 case I915_BIT_6_SWIZZLE_9_11
:
1968 return "bit9/bit11";
1969 case I915_BIT_6_SWIZZLE_9_10_11
:
1970 return "bit9/bit10/bit11";
1971 case I915_BIT_6_SWIZZLE_9_17
:
1972 return "bit9/bit17";
1973 case I915_BIT_6_SWIZZLE_9_10_17
:
1974 return "bit9/bit10/bit17";
1975 case I915_BIT_6_SWIZZLE_UNKNOWN
:
1982 static int i915_swizzle_info(struct seq_file
*m
, void *data
)
1984 struct drm_info_node
*node
= m
->private;
1985 struct drm_device
*dev
= node
->minor
->dev
;
1986 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1989 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1992 intel_runtime_pm_get(dev_priv
);
1994 seq_printf(m
, "bit6 swizzle for X-tiling = %s\n",
1995 swizzle_string(dev_priv
->mm
.bit_6_swizzle_x
));
1996 seq_printf(m
, "bit6 swizzle for Y-tiling = %s\n",
1997 swizzle_string(dev_priv
->mm
.bit_6_swizzle_y
));
1999 if (IS_GEN3(dev
) || IS_GEN4(dev
)) {
2000 seq_printf(m
, "DDC = 0x%08x\n",
2002 seq_printf(m
, "DDC2 = 0x%08x\n",
2004 seq_printf(m
, "C0DRB3 = 0x%04x\n",
2005 I915_READ16(C0DRB3
));
2006 seq_printf(m
, "C1DRB3 = 0x%04x\n",
2007 I915_READ16(C1DRB3
));
2008 } else if (INTEL_INFO(dev
)->gen
>= 6) {
2009 seq_printf(m
, "MAD_DIMM_C0 = 0x%08x\n",
2010 I915_READ(MAD_DIMM_C0
));
2011 seq_printf(m
, "MAD_DIMM_C1 = 0x%08x\n",
2012 I915_READ(MAD_DIMM_C1
));
2013 seq_printf(m
, "MAD_DIMM_C2 = 0x%08x\n",
2014 I915_READ(MAD_DIMM_C2
));
2015 seq_printf(m
, "TILECTL = 0x%08x\n",
2016 I915_READ(TILECTL
));
2017 if (INTEL_INFO(dev
)->gen
>= 8)
2018 seq_printf(m
, "GAMTARBMODE = 0x%08x\n",
2019 I915_READ(GAMTARBMODE
));
2021 seq_printf(m
, "ARB_MODE = 0x%08x\n",
2022 I915_READ(ARB_MODE
));
2023 seq_printf(m
, "DISP_ARB_CTL = 0x%08x\n",
2024 I915_READ(DISP_ARB_CTL
));
2027 if (dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
)
2028 seq_puts(m
, "L-shaped memory detected\n");
2030 intel_runtime_pm_put(dev_priv
);
2031 mutex_unlock(&dev
->struct_mutex
);
2036 static int per_file_ctx(int id
, void *ptr
, void *data
)
2038 struct intel_context
*ctx
= ptr
;
2039 struct seq_file
*m
= data
;
2040 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
2043 seq_printf(m
, " no ppgtt for context %d\n",
2048 if (i915_gem_context_is_default(ctx
))
2049 seq_puts(m
, " default context:\n");
2051 seq_printf(m
, " context %d:\n", ctx
->user_handle
);
2052 ppgtt
->debug_dump(ppgtt
, m
);
2057 static void gen8_ppgtt_info(struct seq_file
*m
, struct drm_device
*dev
)
2059 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2060 struct intel_engine_cs
*ring
;
2061 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2067 seq_printf(m
, "Page directories: %d\n", ppgtt
->num_pd_pages
);
2068 seq_printf(m
, "Page tables: %d\n", ppgtt
->num_pd_entries
);
2069 for_each_ring(ring
, dev_priv
, unused
) {
2070 seq_printf(m
, "%s\n", ring
->name
);
2071 for (i
= 0; i
< 4; i
++) {
2072 u32 offset
= 0x270 + i
* 8;
2073 u64 pdp
= I915_READ(ring
->mmio_base
+ offset
+ 4);
2075 pdp
|= I915_READ(ring
->mmio_base
+ offset
);
2076 seq_printf(m
, "\tPDP%d 0x%016llx\n", i
, pdp
);
2081 static void gen6_ppgtt_info(struct seq_file
*m
, struct drm_device
*dev
)
2083 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2084 struct intel_engine_cs
*ring
;
2085 struct drm_file
*file
;
2088 if (INTEL_INFO(dev
)->gen
== 6)
2089 seq_printf(m
, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE
));
2091 for_each_ring(ring
, dev_priv
, i
) {
2092 seq_printf(m
, "%s\n", ring
->name
);
2093 if (INTEL_INFO(dev
)->gen
== 7)
2094 seq_printf(m
, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring
)));
2095 seq_printf(m
, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring
)));
2096 seq_printf(m
, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring
)));
2097 seq_printf(m
, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring
)));
2099 if (dev_priv
->mm
.aliasing_ppgtt
) {
2100 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2102 seq_puts(m
, "aliasing PPGTT:\n");
2103 seq_printf(m
, "pd gtt offset: 0x%08x\n", ppgtt
->pd_offset
);
2105 ppgtt
->debug_dump(ppgtt
, m
);
2108 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
2109 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2111 seq_printf(m
, "proc: %s\n",
2112 get_pid_task(file
->pid
, PIDTYPE_PID
)->comm
);
2113 idr_for_each(&file_priv
->context_idr
, per_file_ctx
, m
);
2115 seq_printf(m
, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK
));
2118 static int i915_ppgtt_info(struct seq_file
*m
, void *data
)
2120 struct drm_info_node
*node
= m
->private;
2121 struct drm_device
*dev
= node
->minor
->dev
;
2122 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2124 int ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2127 intel_runtime_pm_get(dev_priv
);
2129 if (INTEL_INFO(dev
)->gen
>= 8)
2130 gen8_ppgtt_info(m
, dev
);
2131 else if (INTEL_INFO(dev
)->gen
>= 6)
2132 gen6_ppgtt_info(m
, dev
);
2134 intel_runtime_pm_put(dev_priv
);
2135 mutex_unlock(&dev
->struct_mutex
);
2140 static int i915_llc(struct seq_file
*m
, void *data
)
2142 struct drm_info_node
*node
= m
->private;
2143 struct drm_device
*dev
= node
->minor
->dev
;
2144 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2146 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2147 seq_printf(m
, "LLC: %s\n", yesno(HAS_LLC(dev
)));
2148 seq_printf(m
, "eLLC: %zuMB\n", dev_priv
->ellc_size
);
2153 static int i915_edp_psr_status(struct seq_file
*m
, void *data
)
2155 struct drm_info_node
*node
= m
->private;
2156 struct drm_device
*dev
= node
->minor
->dev
;
2157 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2161 bool enabled
= false;
2163 intel_runtime_pm_get(dev_priv
);
2165 mutex_lock(&dev_priv
->psr
.lock
);
2166 seq_printf(m
, "Sink_Support: %s\n", yesno(dev_priv
->psr
.sink_support
));
2167 seq_printf(m
, "Source_OK: %s\n", yesno(dev_priv
->psr
.source_ok
));
2168 seq_printf(m
, "Enabled: %s\n", yesno((bool)dev_priv
->psr
.enabled
));
2169 seq_printf(m
, "Active: %s\n", yesno(dev_priv
->psr
.active
));
2170 seq_printf(m
, "Busy frontbuffer bits: 0x%03x\n",
2171 dev_priv
->psr
.busy_frontbuffer_bits
);
2172 seq_printf(m
, "Re-enable work scheduled: %s\n",
2173 yesno(work_busy(&dev_priv
->psr
.work
.work
)));
2177 enabled
= I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
;
2179 for_each_pipe(dev_priv
, pipe
) {
2180 stat
[pipe
] = I915_READ(VLV_PSRSTAT(pipe
)) &
2181 VLV_EDP_PSR_CURR_STATE_MASK
;
2182 if ((stat
[pipe
] == VLV_EDP_PSR_ACTIVE_NORFB_UP
) ||
2183 (stat
[pipe
] == VLV_EDP_PSR_ACTIVE_SF_UPDATE
))
2188 seq_printf(m
, "HW Enabled & Active bit: %s", yesno(enabled
));
2191 for_each_pipe(dev_priv
, pipe
) {
2192 if ((stat
[pipe
] == VLV_EDP_PSR_ACTIVE_NORFB_UP
) ||
2193 (stat
[pipe
] == VLV_EDP_PSR_ACTIVE_SF_UPDATE
))
2194 seq_printf(m
, " pipe %c", pipe_name(pipe
));
2198 /* CHV PSR has no kind of performance counter */
2199 if (HAS_PSR(dev
) && HAS_DDI(dev
)) {
2200 psrperf
= I915_READ(EDP_PSR_PERF_CNT(dev
)) &
2201 EDP_PSR_PERF_CNT_MASK
;
2203 seq_printf(m
, "Performance_Counter: %u\n", psrperf
);
2205 mutex_unlock(&dev_priv
->psr
.lock
);
2207 intel_runtime_pm_put(dev_priv
);
2211 static int i915_sink_crc(struct seq_file
*m
, void *data
)
2213 struct drm_info_node
*node
= m
->private;
2214 struct drm_device
*dev
= node
->minor
->dev
;
2215 struct intel_encoder
*encoder
;
2216 struct intel_connector
*connector
;
2217 struct intel_dp
*intel_dp
= NULL
;
2221 drm_modeset_lock_all(dev
);
2222 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
2225 if (connector
->base
.dpms
!= DRM_MODE_DPMS_ON
)
2228 if (!connector
->base
.encoder
)
2231 encoder
= to_intel_encoder(connector
->base
.encoder
);
2232 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2235 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2237 ret
= intel_dp_sink_crc(intel_dp
, crc
);
2241 seq_printf(m
, "%02x%02x%02x%02x%02x%02x\n",
2242 crc
[0], crc
[1], crc
[2],
2243 crc
[3], crc
[4], crc
[5]);
2248 drm_modeset_unlock_all(dev
);
2252 static int i915_energy_uJ(struct seq_file
*m
, void *data
)
2254 struct drm_info_node
*node
= m
->private;
2255 struct drm_device
*dev
= node
->minor
->dev
;
2256 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2260 if (INTEL_INFO(dev
)->gen
< 6)
2263 intel_runtime_pm_get(dev_priv
);
2265 rdmsrl(MSR_RAPL_POWER_UNIT
, power
);
2266 power
= (power
& 0x1f00) >> 8;
2267 units
= 1000000 / (1 << power
); /* convert to uJ */
2268 power
= I915_READ(MCH_SECP_NRG_STTS
);
2271 intel_runtime_pm_put(dev_priv
);
2273 seq_printf(m
, "%llu", (long long unsigned)power
);
2278 static int i915_pc8_status(struct seq_file
*m
, void *unused
)
2280 struct drm_info_node
*node
= m
->private;
2281 struct drm_device
*dev
= node
->minor
->dev
;
2282 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2284 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
2285 seq_puts(m
, "not supported\n");
2289 seq_printf(m
, "GPU idle: %s\n", yesno(!dev_priv
->mm
.busy
));
2290 seq_printf(m
, "IRQs disabled: %s\n",
2291 yesno(!intel_irqs_enabled(dev_priv
)));
2296 static const char *power_domain_str(enum intel_display_power_domain domain
)
2299 case POWER_DOMAIN_PIPE_A
:
2301 case POWER_DOMAIN_PIPE_B
:
2303 case POWER_DOMAIN_PIPE_C
:
2305 case POWER_DOMAIN_PIPE_A_PANEL_FITTER
:
2306 return "PIPE_A_PANEL_FITTER";
2307 case POWER_DOMAIN_PIPE_B_PANEL_FITTER
:
2308 return "PIPE_B_PANEL_FITTER";
2309 case POWER_DOMAIN_PIPE_C_PANEL_FITTER
:
2310 return "PIPE_C_PANEL_FITTER";
2311 case POWER_DOMAIN_TRANSCODER_A
:
2312 return "TRANSCODER_A";
2313 case POWER_DOMAIN_TRANSCODER_B
:
2314 return "TRANSCODER_B";
2315 case POWER_DOMAIN_TRANSCODER_C
:
2316 return "TRANSCODER_C";
2317 case POWER_DOMAIN_TRANSCODER_EDP
:
2318 return "TRANSCODER_EDP";
2319 case POWER_DOMAIN_PORT_DDI_A_2_LANES
:
2320 return "PORT_DDI_A_2_LANES";
2321 case POWER_DOMAIN_PORT_DDI_A_4_LANES
:
2322 return "PORT_DDI_A_4_LANES";
2323 case POWER_DOMAIN_PORT_DDI_B_2_LANES
:
2324 return "PORT_DDI_B_2_LANES";
2325 case POWER_DOMAIN_PORT_DDI_B_4_LANES
:
2326 return "PORT_DDI_B_4_LANES";
2327 case POWER_DOMAIN_PORT_DDI_C_2_LANES
:
2328 return "PORT_DDI_C_2_LANES";
2329 case POWER_DOMAIN_PORT_DDI_C_4_LANES
:
2330 return "PORT_DDI_C_4_LANES";
2331 case POWER_DOMAIN_PORT_DDI_D_2_LANES
:
2332 return "PORT_DDI_D_2_LANES";
2333 case POWER_DOMAIN_PORT_DDI_D_4_LANES
:
2334 return "PORT_DDI_D_4_LANES";
2335 case POWER_DOMAIN_PORT_DSI
:
2337 case POWER_DOMAIN_PORT_CRT
:
2339 case POWER_DOMAIN_PORT_OTHER
:
2340 return "PORT_OTHER";
2341 case POWER_DOMAIN_VGA
:
2343 case POWER_DOMAIN_AUDIO
:
2345 case POWER_DOMAIN_PLLS
:
2347 case POWER_DOMAIN_INIT
:
2355 static int i915_power_domain_info(struct seq_file
*m
, void *unused
)
2357 struct drm_info_node
*node
= m
->private;
2358 struct drm_device
*dev
= node
->minor
->dev
;
2359 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2360 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
2363 mutex_lock(&power_domains
->lock
);
2365 seq_printf(m
, "%-25s %s\n", "Power well/domain", "Use count");
2366 for (i
= 0; i
< power_domains
->power_well_count
; i
++) {
2367 struct i915_power_well
*power_well
;
2368 enum intel_display_power_domain power_domain
;
2370 power_well
= &power_domains
->power_wells
[i
];
2371 seq_printf(m
, "%-25s %d\n", power_well
->name
,
2374 for (power_domain
= 0; power_domain
< POWER_DOMAIN_NUM
;
2376 if (!(BIT(power_domain
) & power_well
->domains
))
2379 seq_printf(m
, " %-23s %d\n",
2380 power_domain_str(power_domain
),
2381 power_domains
->domain_use_count
[power_domain
]);
2385 mutex_unlock(&power_domains
->lock
);
2390 static void intel_seq_print_mode(struct seq_file
*m
, int tabs
,
2391 struct drm_display_mode
*mode
)
2395 for (i
= 0; i
< tabs
; i
++)
2398 seq_printf(m
, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2399 mode
->base
.id
, mode
->name
,
2400 mode
->vrefresh
, mode
->clock
,
2401 mode
->hdisplay
, mode
->hsync_start
,
2402 mode
->hsync_end
, mode
->htotal
,
2403 mode
->vdisplay
, mode
->vsync_start
,
2404 mode
->vsync_end
, mode
->vtotal
,
2405 mode
->type
, mode
->flags
);
2408 static void intel_encoder_info(struct seq_file
*m
,
2409 struct intel_crtc
*intel_crtc
,
2410 struct intel_encoder
*intel_encoder
)
2412 struct drm_info_node
*node
= m
->private;
2413 struct drm_device
*dev
= node
->minor
->dev
;
2414 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2415 struct intel_connector
*intel_connector
;
2416 struct drm_encoder
*encoder
;
2418 encoder
= &intel_encoder
->base
;
2419 seq_printf(m
, "\tencoder %d: type: %s, connectors:\n",
2420 encoder
->base
.id
, encoder
->name
);
2421 for_each_connector_on_encoder(dev
, encoder
, intel_connector
) {
2422 struct drm_connector
*connector
= &intel_connector
->base
;
2423 seq_printf(m
, "\t\tconnector %d: type: %s, status: %s",
2426 drm_get_connector_status_name(connector
->status
));
2427 if (connector
->status
== connector_status_connected
) {
2428 struct drm_display_mode
*mode
= &crtc
->mode
;
2429 seq_printf(m
, ", mode:\n");
2430 intel_seq_print_mode(m
, 2, mode
);
2437 static void intel_crtc_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
2439 struct drm_info_node
*node
= m
->private;
2440 struct drm_device
*dev
= node
->minor
->dev
;
2441 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2442 struct intel_encoder
*intel_encoder
;
2444 if (crtc
->primary
->fb
)
2445 seq_printf(m
, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2446 crtc
->primary
->fb
->base
.id
, crtc
->x
, crtc
->y
,
2447 crtc
->primary
->fb
->width
, crtc
->primary
->fb
->height
);
2449 seq_puts(m
, "\tprimary plane disabled\n");
2450 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
2451 intel_encoder_info(m
, intel_crtc
, intel_encoder
);
2454 static void intel_panel_info(struct seq_file
*m
, struct intel_panel
*panel
)
2456 struct drm_display_mode
*mode
= panel
->fixed_mode
;
2458 seq_printf(m
, "\tfixed mode:\n");
2459 intel_seq_print_mode(m
, 2, mode
);
2462 static void intel_dp_info(struct seq_file
*m
,
2463 struct intel_connector
*intel_connector
)
2465 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2466 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
2468 seq_printf(m
, "\tDPCD rev: %x\n", intel_dp
->dpcd
[DP_DPCD_REV
]);
2469 seq_printf(m
, "\taudio support: %s\n", intel_dp
->has_audio
? "yes" :
2471 if (intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2472 intel_panel_info(m
, &intel_connector
->panel
);
2475 static void intel_hdmi_info(struct seq_file
*m
,
2476 struct intel_connector
*intel_connector
)
2478 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2479 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&intel_encoder
->base
);
2481 seq_printf(m
, "\taudio support: %s\n", intel_hdmi
->has_audio
? "yes" :
2485 static void intel_lvds_info(struct seq_file
*m
,
2486 struct intel_connector
*intel_connector
)
2488 intel_panel_info(m
, &intel_connector
->panel
);
2491 static void intel_connector_info(struct seq_file
*m
,
2492 struct drm_connector
*connector
)
2494 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2495 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2496 struct drm_display_mode
*mode
;
2498 seq_printf(m
, "connector %d: type %s, status: %s\n",
2499 connector
->base
.id
, connector
->name
,
2500 drm_get_connector_status_name(connector
->status
));
2501 if (connector
->status
== connector_status_connected
) {
2502 seq_printf(m
, "\tname: %s\n", connector
->display_info
.name
);
2503 seq_printf(m
, "\tphysical dimensions: %dx%dmm\n",
2504 connector
->display_info
.width_mm
,
2505 connector
->display_info
.height_mm
);
2506 seq_printf(m
, "\tsubpixel order: %s\n",
2507 drm_get_subpixel_order_name(connector
->display_info
.subpixel_order
));
2508 seq_printf(m
, "\tCEA rev: %d\n",
2509 connector
->display_info
.cea_rev
);
2511 if (intel_encoder
) {
2512 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
2513 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2514 intel_dp_info(m
, intel_connector
);
2515 else if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
)
2516 intel_hdmi_info(m
, intel_connector
);
2517 else if (intel_encoder
->type
== INTEL_OUTPUT_LVDS
)
2518 intel_lvds_info(m
, intel_connector
);
2521 seq_printf(m
, "\tmodes:\n");
2522 list_for_each_entry(mode
, &connector
->modes
, head
)
2523 intel_seq_print_mode(m
, 2, mode
);
2526 static bool cursor_active(struct drm_device
*dev
, int pipe
)
2528 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2531 if (IS_845G(dev
) || IS_I865G(dev
))
2532 state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
2534 state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
2539 static bool cursor_position(struct drm_device
*dev
, int pipe
, int *x
, int *y
)
2541 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2544 pos
= I915_READ(CURPOS(pipe
));
2546 *x
= (pos
>> CURSOR_X_SHIFT
) & CURSOR_POS_MASK
;
2547 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
))
2550 *y
= (pos
>> CURSOR_Y_SHIFT
) & CURSOR_POS_MASK
;
2551 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
))
2554 return cursor_active(dev
, pipe
);
2557 static int i915_display_info(struct seq_file
*m
, void *unused
)
2559 struct drm_info_node
*node
= m
->private;
2560 struct drm_device
*dev
= node
->minor
->dev
;
2561 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2562 struct intel_crtc
*crtc
;
2563 struct drm_connector
*connector
;
2565 intel_runtime_pm_get(dev_priv
);
2566 drm_modeset_lock_all(dev
);
2567 seq_printf(m
, "CRTC info\n");
2568 seq_printf(m
, "---------\n");
2569 for_each_intel_crtc(dev
, crtc
) {
2573 seq_printf(m
, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
2574 crtc
->base
.base
.id
, pipe_name(crtc
->pipe
),
2575 yesno(crtc
->active
), crtc
->config
.pipe_src_w
, crtc
->config
.pipe_src_h
);
2577 intel_crtc_info(m
, crtc
);
2579 active
= cursor_position(dev
, crtc
->pipe
, &x
, &y
);
2580 seq_printf(m
, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
2581 yesno(crtc
->cursor_base
),
2582 x
, y
, crtc
->cursor_width
, crtc
->cursor_height
,
2583 crtc
->cursor_addr
, yesno(active
));
2586 seq_printf(m
, "\tunderrun reporting: cpu=%s pch=%s \n",
2587 yesno(!crtc
->cpu_fifo_underrun_disabled
),
2588 yesno(!crtc
->pch_fifo_underrun_disabled
));
2591 seq_printf(m
, "\n");
2592 seq_printf(m
, "Connector info\n");
2593 seq_printf(m
, "--------------\n");
2594 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
2595 intel_connector_info(m
, connector
);
2597 drm_modeset_unlock_all(dev
);
2598 intel_runtime_pm_put(dev_priv
);
2603 static int i915_semaphore_status(struct seq_file
*m
, void *unused
)
2605 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2606 struct drm_device
*dev
= node
->minor
->dev
;
2607 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2608 struct intel_engine_cs
*ring
;
2609 int num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
2612 if (!i915_semaphore_is_enabled(dev
)) {
2613 seq_puts(m
, "Semaphores are disabled\n");
2617 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2620 intel_runtime_pm_get(dev_priv
);
2622 if (IS_BROADWELL(dev
)) {
2626 page
= i915_gem_object_get_page(dev_priv
->semaphore_obj
, 0);
2628 seqno
= (uint64_t *)kmap_atomic(page
);
2629 for_each_ring(ring
, dev_priv
, i
) {
2632 seq_printf(m
, "%s\n", ring
->name
);
2634 seq_puts(m
, " Last signal:");
2635 for (j
= 0; j
< num_rings
; j
++) {
2636 offset
= i
* I915_NUM_RINGS
+ j
;
2637 seq_printf(m
, "0x%08llx (0x%02llx) ",
2638 seqno
[offset
], offset
* 8);
2642 seq_puts(m
, " Last wait: ");
2643 for (j
= 0; j
< num_rings
; j
++) {
2644 offset
= i
+ (j
* I915_NUM_RINGS
);
2645 seq_printf(m
, "0x%08llx (0x%02llx) ",
2646 seqno
[offset
], offset
* 8);
2651 kunmap_atomic(seqno
);
2653 seq_puts(m
, " Last signal:");
2654 for_each_ring(ring
, dev_priv
, i
)
2655 for (j
= 0; j
< num_rings
; j
++)
2656 seq_printf(m
, "0x%08x\n",
2657 I915_READ(ring
->semaphore
.mbox
.signal
[j
]));
2661 seq_puts(m
, "\nSync seqno:\n");
2662 for_each_ring(ring
, dev_priv
, i
) {
2663 for (j
= 0; j
< num_rings
; j
++) {
2664 seq_printf(m
, " 0x%08x ", ring
->semaphore
.sync_seqno
[j
]);
2670 intel_runtime_pm_put(dev_priv
);
2671 mutex_unlock(&dev
->struct_mutex
);
2675 static int i915_shared_dplls_info(struct seq_file
*m
, void *unused
)
2677 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2678 struct drm_device
*dev
= node
->minor
->dev
;
2679 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2682 drm_modeset_lock_all(dev
);
2683 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
2684 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
2686 seq_printf(m
, "DPLL%i: %s, id: %i\n", i
, pll
->name
, pll
->id
);
2687 seq_printf(m
, " crtc_mask: 0x%08x, active: %d, on: %s\n",
2688 pll
->config
.crtc_mask
, pll
->active
, yesno(pll
->on
));
2689 seq_printf(m
, " tracked hardware state:\n");
2690 seq_printf(m
, " dpll: 0x%08x\n", pll
->config
.hw_state
.dpll
);
2691 seq_printf(m
, " dpll_md: 0x%08x\n",
2692 pll
->config
.hw_state
.dpll_md
);
2693 seq_printf(m
, " fp0: 0x%08x\n", pll
->config
.hw_state
.fp0
);
2694 seq_printf(m
, " fp1: 0x%08x\n", pll
->config
.hw_state
.fp1
);
2695 seq_printf(m
, " wrpll: 0x%08x\n", pll
->config
.hw_state
.wrpll
);
2697 drm_modeset_unlock_all(dev
);
2702 static int i915_wa_registers(struct seq_file
*m
, void *unused
)
2706 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2707 struct drm_device
*dev
= node
->minor
->dev
;
2708 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2710 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2714 intel_runtime_pm_get(dev_priv
);
2716 seq_printf(m
, "Workarounds applied: %d\n", dev_priv
->workarounds
.count
);
2717 for (i
= 0; i
< dev_priv
->workarounds
.count
; ++i
) {
2718 u32 addr
, mask
, value
, read
;
2721 addr
= dev_priv
->workarounds
.reg
[i
].addr
;
2722 mask
= dev_priv
->workarounds
.reg
[i
].mask
;
2723 value
= dev_priv
->workarounds
.reg
[i
].value
;
2724 read
= I915_READ(addr
);
2725 ok
= (value
& mask
) == (read
& mask
);
2726 seq_printf(m
, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2727 addr
, value
, mask
, read
, ok
? "OK" : "FAIL");
2730 intel_runtime_pm_put(dev_priv
);
2731 mutex_unlock(&dev
->struct_mutex
);
2736 static int i915_ddb_info(struct seq_file
*m
, void *unused
)
2738 struct drm_info_node
*node
= m
->private;
2739 struct drm_device
*dev
= node
->minor
->dev
;
2740 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2741 struct skl_ddb_allocation
*ddb
;
2742 struct skl_ddb_entry
*entry
;
2746 if (INTEL_INFO(dev
)->gen
< 9)
2749 drm_modeset_lock_all(dev
);
2751 ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
2753 seq_printf(m
, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
2755 for_each_pipe(dev_priv
, pipe
) {
2756 seq_printf(m
, "Pipe %c\n", pipe_name(pipe
));
2758 for_each_plane(pipe
, plane
) {
2759 entry
= &ddb
->plane
[pipe
][plane
];
2760 seq_printf(m
, " Plane%-8d%8u%8u%8u\n", plane
+ 1,
2761 entry
->start
, entry
->end
,
2762 skl_ddb_entry_size(entry
));
2765 entry
= &ddb
->cursor
[pipe
];
2766 seq_printf(m
, " %-13s%8u%8u%8u\n", "Cursor", entry
->start
,
2767 entry
->end
, skl_ddb_entry_size(entry
));
2770 drm_modeset_unlock_all(dev
);
2775 struct pipe_crc_info
{
2777 struct drm_device
*dev
;
2781 static int i915_dp_mst_info(struct seq_file
*m
, void *unused
)
2783 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2784 struct drm_device
*dev
= node
->minor
->dev
;
2785 struct drm_encoder
*encoder
;
2786 struct intel_encoder
*intel_encoder
;
2787 struct intel_digital_port
*intel_dig_port
;
2788 drm_modeset_lock_all(dev
);
2789 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
2790 intel_encoder
= to_intel_encoder(encoder
);
2791 if (intel_encoder
->type
!= INTEL_OUTPUT_DISPLAYPORT
)
2793 intel_dig_port
= enc_to_dig_port(encoder
);
2794 if (!intel_dig_port
->dp
.can_mst
)
2797 drm_dp_mst_dump_topology(m
, &intel_dig_port
->dp
.mst_mgr
);
2799 drm_modeset_unlock_all(dev
);
2803 static int i915_pipe_crc_open(struct inode
*inode
, struct file
*filep
)
2805 struct pipe_crc_info
*info
= inode
->i_private
;
2806 struct drm_i915_private
*dev_priv
= info
->dev
->dev_private
;
2807 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
2809 if (info
->pipe
>= INTEL_INFO(info
->dev
)->num_pipes
)
2812 spin_lock_irq(&pipe_crc
->lock
);
2814 if (pipe_crc
->opened
) {
2815 spin_unlock_irq(&pipe_crc
->lock
);
2816 return -EBUSY
; /* already open */
2819 pipe_crc
->opened
= true;
2820 filep
->private_data
= inode
->i_private
;
2822 spin_unlock_irq(&pipe_crc
->lock
);
2827 static int i915_pipe_crc_release(struct inode
*inode
, struct file
*filep
)
2829 struct pipe_crc_info
*info
= inode
->i_private
;
2830 struct drm_i915_private
*dev_priv
= info
->dev
->dev_private
;
2831 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
2833 spin_lock_irq(&pipe_crc
->lock
);
2834 pipe_crc
->opened
= false;
2835 spin_unlock_irq(&pipe_crc
->lock
);
2840 /* (6 fields, 8 chars each, space separated (5) + '\n') */
2841 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
2842 /* account for \'0' */
2843 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
2845 static int pipe_crc_data_count(struct intel_pipe_crc
*pipe_crc
)
2847 assert_spin_locked(&pipe_crc
->lock
);
2848 return CIRC_CNT(pipe_crc
->head
, pipe_crc
->tail
,
2849 INTEL_PIPE_CRC_ENTRIES_NR
);
2853 i915_pipe_crc_read(struct file
*filep
, char __user
*user_buf
, size_t count
,
2856 struct pipe_crc_info
*info
= filep
->private_data
;
2857 struct drm_device
*dev
= info
->dev
;
2858 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2859 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
2860 char buf
[PIPE_CRC_BUFFER_LEN
];
2861 int head
, tail
, n_entries
, n
;
2865 * Don't allow user space to provide buffers not big enough to hold
2868 if (count
< PIPE_CRC_LINE_LEN
)
2871 if (pipe_crc
->source
== INTEL_PIPE_CRC_SOURCE_NONE
)
2874 /* nothing to read */
2875 spin_lock_irq(&pipe_crc
->lock
);
2876 while (pipe_crc_data_count(pipe_crc
) == 0) {
2879 if (filep
->f_flags
& O_NONBLOCK
) {
2880 spin_unlock_irq(&pipe_crc
->lock
);
2884 ret
= wait_event_interruptible_lock_irq(pipe_crc
->wq
,
2885 pipe_crc_data_count(pipe_crc
), pipe_crc
->lock
);
2887 spin_unlock_irq(&pipe_crc
->lock
);
2892 /* We now have one or more entries to read */
2893 head
= pipe_crc
->head
;
2894 tail
= pipe_crc
->tail
;
2895 n_entries
= min((size_t)CIRC_CNT(head
, tail
, INTEL_PIPE_CRC_ENTRIES_NR
),
2896 count
/ PIPE_CRC_LINE_LEN
);
2897 spin_unlock_irq(&pipe_crc
->lock
);
2902 struct intel_pipe_crc_entry
*entry
= &pipe_crc
->entries
[tail
];
2905 bytes_read
+= snprintf(buf
, PIPE_CRC_BUFFER_LEN
,
2906 "%8u %8x %8x %8x %8x %8x\n",
2907 entry
->frame
, entry
->crc
[0],
2908 entry
->crc
[1], entry
->crc
[2],
2909 entry
->crc
[3], entry
->crc
[4]);
2911 ret
= copy_to_user(user_buf
+ n
* PIPE_CRC_LINE_LEN
,
2912 buf
, PIPE_CRC_LINE_LEN
);
2913 if (ret
== PIPE_CRC_LINE_LEN
)
2916 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR
);
2917 tail
= (tail
+ 1) & (INTEL_PIPE_CRC_ENTRIES_NR
- 1);
2919 } while (--n_entries
);
2921 spin_lock_irq(&pipe_crc
->lock
);
2922 pipe_crc
->tail
= tail
;
2923 spin_unlock_irq(&pipe_crc
->lock
);
2928 static const struct file_operations i915_pipe_crc_fops
= {
2929 .owner
= THIS_MODULE
,
2930 .open
= i915_pipe_crc_open
,
2931 .read
= i915_pipe_crc_read
,
2932 .release
= i915_pipe_crc_release
,
2935 static struct pipe_crc_info i915_pipe_crc_data
[I915_MAX_PIPES
] = {
2937 .name
= "i915_pipe_A_crc",
2941 .name
= "i915_pipe_B_crc",
2945 .name
= "i915_pipe_C_crc",
2950 static int i915_pipe_crc_create(struct dentry
*root
, struct drm_minor
*minor
,
2953 struct drm_device
*dev
= minor
->dev
;
2955 struct pipe_crc_info
*info
= &i915_pipe_crc_data
[pipe
];
2958 ent
= debugfs_create_file(info
->name
, S_IRUGO
, root
, info
,
2959 &i915_pipe_crc_fops
);
2963 return drm_add_fake_info_node(minor
, ent
, info
);
2966 static const char * const pipe_crc_sources
[] = {
2979 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source
)
2981 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources
) != INTEL_PIPE_CRC_SOURCE_MAX
);
2982 return pipe_crc_sources
[source
];
2985 static int display_crc_ctl_show(struct seq_file
*m
, void *data
)
2987 struct drm_device
*dev
= m
->private;
2988 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2991 for (i
= 0; i
< I915_MAX_PIPES
; i
++)
2992 seq_printf(m
, "%c %s\n", pipe_name(i
),
2993 pipe_crc_source_name(dev_priv
->pipe_crc
[i
].source
));
2998 static int display_crc_ctl_open(struct inode
*inode
, struct file
*file
)
3000 struct drm_device
*dev
= inode
->i_private
;
3002 return single_open(file
, display_crc_ctl_show
, dev
);
3005 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
3008 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3009 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3012 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3013 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_INCLUDE_BORDER_I8XX
;
3015 case INTEL_PIPE_CRC_SOURCE_NONE
:
3025 static int i9xx_pipe_crc_auto_source(struct drm_device
*dev
, enum pipe pipe
,
3026 enum intel_pipe_crc_source
*source
)
3028 struct intel_encoder
*encoder
;
3029 struct intel_crtc
*crtc
;
3030 struct intel_digital_port
*dig_port
;
3033 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3035 drm_modeset_lock_all(dev
);
3036 for_each_intel_encoder(dev
, encoder
) {
3037 if (!encoder
->base
.crtc
)
3040 crtc
= to_intel_crtc(encoder
->base
.crtc
);
3042 if (crtc
->pipe
!= pipe
)
3045 switch (encoder
->type
) {
3046 case INTEL_OUTPUT_TVOUT
:
3047 *source
= INTEL_PIPE_CRC_SOURCE_TV
;
3049 case INTEL_OUTPUT_DISPLAYPORT
:
3050 case INTEL_OUTPUT_EDP
:
3051 dig_port
= enc_to_dig_port(&encoder
->base
);
3052 switch (dig_port
->port
) {
3054 *source
= INTEL_PIPE_CRC_SOURCE_DP_B
;
3057 *source
= INTEL_PIPE_CRC_SOURCE_DP_C
;
3060 *source
= INTEL_PIPE_CRC_SOURCE_DP_D
;
3063 WARN(1, "nonexisting DP port %c\n",
3064 port_name(dig_port
->port
));
3072 drm_modeset_unlock_all(dev
);
3077 static int vlv_pipe_crc_ctl_reg(struct drm_device
*dev
,
3079 enum intel_pipe_crc_source
*source
,
3082 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3083 bool need_stable_symbols
= false;
3085 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
3086 int ret
= i9xx_pipe_crc_auto_source(dev
, pipe
, source
);
3092 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3093 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_VLV
;
3095 case INTEL_PIPE_CRC_SOURCE_DP_B
:
3096 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_VLV
;
3097 need_stable_symbols
= true;
3099 case INTEL_PIPE_CRC_SOURCE_DP_C
:
3100 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_VLV
;
3101 need_stable_symbols
= true;
3103 case INTEL_PIPE_CRC_SOURCE_DP_D
:
3104 if (!IS_CHERRYVIEW(dev
))
3106 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_D_VLV
;
3107 need_stable_symbols
= true;
3109 case INTEL_PIPE_CRC_SOURCE_NONE
:
3117 * When the pipe CRC tap point is after the transcoders we need
3118 * to tweak symbol-level features to produce a deterministic series of
3119 * symbols for a given frame. We need to reset those features only once
3120 * a frame (instead of every nth symbol):
3121 * - DC-balance: used to ensure a better clock recovery from the data
3123 * - DisplayPort scrambling: used for EMI reduction
3125 if (need_stable_symbols
) {
3126 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3128 tmp
|= DC_BALANCE_RESET_VLV
;
3131 tmp
|= PIPE_A_SCRAMBLE_RESET
;
3134 tmp
|= PIPE_B_SCRAMBLE_RESET
;
3137 tmp
|= PIPE_C_SCRAMBLE_RESET
;
3142 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3148 static int i9xx_pipe_crc_ctl_reg(struct drm_device
*dev
,
3150 enum intel_pipe_crc_source
*source
,
3153 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3154 bool need_stable_symbols
= false;
3156 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
3157 int ret
= i9xx_pipe_crc_auto_source(dev
, pipe
, source
);
3163 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3164 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_I9XX
;
3166 case INTEL_PIPE_CRC_SOURCE_TV
:
3167 if (!SUPPORTS_TV(dev
))
3169 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_TV_PRE
;
3171 case INTEL_PIPE_CRC_SOURCE_DP_B
:
3174 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_G4X
;
3175 need_stable_symbols
= true;
3177 case INTEL_PIPE_CRC_SOURCE_DP_C
:
3180 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_G4X
;
3181 need_stable_symbols
= true;
3183 case INTEL_PIPE_CRC_SOURCE_DP_D
:
3186 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_D_G4X
;
3187 need_stable_symbols
= true;
3189 case INTEL_PIPE_CRC_SOURCE_NONE
:
3197 * When the pipe CRC tap point is after the transcoders we need
3198 * to tweak symbol-level features to produce a deterministic series of
3199 * symbols for a given frame. We need to reset those features only once
3200 * a frame (instead of every nth symbol):
3201 * - DC-balance: used to ensure a better clock recovery from the data
3203 * - DisplayPort scrambling: used for EMI reduction
3205 if (need_stable_symbols
) {
3206 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3208 WARN_ON(!IS_G4X(dev
));
3210 I915_WRITE(PORT_DFT_I9XX
,
3211 I915_READ(PORT_DFT_I9XX
) | DC_BALANCE_RESET
);
3214 tmp
|= PIPE_A_SCRAMBLE_RESET
;
3216 tmp
|= PIPE_B_SCRAMBLE_RESET
;
3218 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3224 static void vlv_undo_pipe_scramble_reset(struct drm_device
*dev
,
3227 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3228 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3232 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
3235 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
3238 tmp
&= ~PIPE_C_SCRAMBLE_RESET
;
3243 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
))
3244 tmp
&= ~DC_BALANCE_RESET_VLV
;
3245 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3249 static void g4x_undo_pipe_scramble_reset(struct drm_device
*dev
,
3252 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3253 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3256 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
3258 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
3259 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3261 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
)) {
3262 I915_WRITE(PORT_DFT_I9XX
,
3263 I915_READ(PORT_DFT_I9XX
) & ~DC_BALANCE_RESET
);
3267 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
3270 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3271 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3274 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
3275 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_ILK
;
3277 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
3278 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_ILK
;
3280 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3281 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_ILK
;
3283 case INTEL_PIPE_CRC_SOURCE_NONE
:
3293 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device
*dev
)
3295 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3296 struct intel_crtc
*crtc
=
3297 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_A
]);
3299 drm_modeset_lock_all(dev
);
3301 * If we use the eDP transcoder we need to make sure that we don't
3302 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3303 * relevant on hsw with pipe A when using the always-on power well
3306 if (crtc
->config
.cpu_transcoder
== TRANSCODER_EDP
&&
3307 !crtc
->config
.pch_pfit
.enabled
) {
3308 crtc
->config
.pch_pfit
.force_thru
= true;
3310 intel_display_power_get(dev_priv
,
3311 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A
));
3313 dev_priv
->display
.crtc_disable(&crtc
->base
);
3314 dev_priv
->display
.crtc_enable(&crtc
->base
);
3316 drm_modeset_unlock_all(dev
);
3319 static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device
*dev
)
3321 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3322 struct intel_crtc
*crtc
=
3323 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_A
]);
3325 drm_modeset_lock_all(dev
);
3327 * If we use the eDP transcoder we need to make sure that we don't
3328 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3329 * relevant on hsw with pipe A when using the always-on power well
3332 if (crtc
->config
.pch_pfit
.force_thru
) {
3333 crtc
->config
.pch_pfit
.force_thru
= false;
3335 dev_priv
->display
.crtc_disable(&crtc
->base
);
3336 dev_priv
->display
.crtc_enable(&crtc
->base
);
3338 intel_display_power_put(dev_priv
,
3339 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A
));
3341 drm_modeset_unlock_all(dev
);
3344 static int ivb_pipe_crc_ctl_reg(struct drm_device
*dev
,
3346 enum intel_pipe_crc_source
*source
,
3349 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3350 *source
= INTEL_PIPE_CRC_SOURCE_PF
;
3353 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
3354 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_IVB
;
3356 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
3357 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_IVB
;
3359 case INTEL_PIPE_CRC_SOURCE_PF
:
3360 if (IS_HASWELL(dev
) && pipe
== PIPE_A
)
3361 hsw_trans_edp_pipe_A_crc_wa(dev
);
3363 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PF_IVB
;
3365 case INTEL_PIPE_CRC_SOURCE_NONE
:
3375 static int pipe_crc_set_source(struct drm_device
*dev
, enum pipe pipe
,
3376 enum intel_pipe_crc_source source
)
3378 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3379 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
3380 struct intel_crtc
*crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
,
3382 u32 val
= 0; /* shut up gcc */
3385 if (pipe_crc
->source
== source
)
3388 /* forbid changing the source without going back to 'none' */
3389 if (pipe_crc
->source
&& source
)
3392 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PIPE(pipe
))) {
3393 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3398 ret
= i8xx_pipe_crc_ctl_reg(&source
, &val
);
3399 else if (INTEL_INFO(dev
)->gen
< 5)
3400 ret
= i9xx_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
3401 else if (IS_VALLEYVIEW(dev
))
3402 ret
= vlv_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
3403 else if (IS_GEN5(dev
) || IS_GEN6(dev
))
3404 ret
= ilk_pipe_crc_ctl_reg(&source
, &val
);
3406 ret
= ivb_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
3411 /* none -> real source transition */
3413 struct intel_pipe_crc_entry
*entries
;
3415 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3416 pipe_name(pipe
), pipe_crc_source_name(source
));
3418 entries
= kcalloc(INTEL_PIPE_CRC_ENTRIES_NR
,
3419 sizeof(pipe_crc
->entries
[0]),
3425 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3426 * enabled and disabled dynamically based on package C states,
3427 * user space can't make reliable use of the CRCs, so let's just
3428 * completely disable it.
3430 hsw_disable_ips(crtc
);
3432 spin_lock_irq(&pipe_crc
->lock
);
3433 pipe_crc
->entries
= entries
;
3436 spin_unlock_irq(&pipe_crc
->lock
);
3439 pipe_crc
->source
= source
;
3441 I915_WRITE(PIPE_CRC_CTL(pipe
), val
);
3442 POSTING_READ(PIPE_CRC_CTL(pipe
));
3444 /* real source -> none transition */
3445 if (source
== INTEL_PIPE_CRC_SOURCE_NONE
) {
3446 struct intel_pipe_crc_entry
*entries
;
3447 struct intel_crtc
*crtc
=
3448 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
3450 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3453 drm_modeset_lock(&crtc
->base
.mutex
, NULL
);
3455 intel_wait_for_vblank(dev
, pipe
);
3456 drm_modeset_unlock(&crtc
->base
.mutex
);
3458 spin_lock_irq(&pipe_crc
->lock
);
3459 entries
= pipe_crc
->entries
;
3460 pipe_crc
->entries
= NULL
;
3461 spin_unlock_irq(&pipe_crc
->lock
);
3466 g4x_undo_pipe_scramble_reset(dev
, pipe
);
3467 else if (IS_VALLEYVIEW(dev
))
3468 vlv_undo_pipe_scramble_reset(dev
, pipe
);
3469 else if (IS_HASWELL(dev
) && pipe
== PIPE_A
)
3470 hsw_undo_trans_edp_pipe_A_crc_wa(dev
);
3472 hsw_enable_ips(crtc
);
3479 * Parse pipe CRC command strings:
3480 * command: wsp* object wsp+ name wsp+ source wsp*
3483 * source: (none | plane1 | plane2 | pf)
3484 * wsp: (#0x20 | #0x9 | #0xA)+
3487 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3488 * "pipe A none" -> Stop CRC
3490 static int display_crc_ctl_tokenize(char *buf
, char *words
[], int max_words
)
3497 /* skip leading white space */
3498 buf
= skip_spaces(buf
);
3500 break; /* end of buffer */
3502 /* find end of word */
3503 for (end
= buf
; *end
&& !isspace(*end
); end
++)
3506 if (n_words
== max_words
) {
3507 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3509 return -EINVAL
; /* ran out of words[] before bytes */
3514 words
[n_words
++] = buf
;
3521 enum intel_pipe_crc_object
{
3522 PIPE_CRC_OBJECT_PIPE
,
3525 static const char * const pipe_crc_objects
[] = {
3530 display_crc_ctl_parse_object(const char *buf
, enum intel_pipe_crc_object
*o
)
3534 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_objects
); i
++)
3535 if (!strcmp(buf
, pipe_crc_objects
[i
])) {
3543 static int display_crc_ctl_parse_pipe(const char *buf
, enum pipe
*pipe
)
3545 const char name
= buf
[0];
3547 if (name
< 'A' || name
>= pipe_name(I915_MAX_PIPES
))
3556 display_crc_ctl_parse_source(const char *buf
, enum intel_pipe_crc_source
*s
)
3560 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_sources
); i
++)
3561 if (!strcmp(buf
, pipe_crc_sources
[i
])) {
3569 static int display_crc_ctl_parse(struct drm_device
*dev
, char *buf
, size_t len
)
3573 char *words
[N_WORDS
];
3575 enum intel_pipe_crc_object object
;
3576 enum intel_pipe_crc_source source
;
3578 n_words
= display_crc_ctl_tokenize(buf
, words
, N_WORDS
);
3579 if (n_words
!= N_WORDS
) {
3580 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3585 if (display_crc_ctl_parse_object(words
[0], &object
) < 0) {
3586 DRM_DEBUG_DRIVER("unknown object %s\n", words
[0]);
3590 if (display_crc_ctl_parse_pipe(words
[1], &pipe
) < 0) {
3591 DRM_DEBUG_DRIVER("unknown pipe %s\n", words
[1]);
3595 if (display_crc_ctl_parse_source(words
[2], &source
) < 0) {
3596 DRM_DEBUG_DRIVER("unknown source %s\n", words
[2]);
3600 return pipe_crc_set_source(dev
, pipe
, source
);
3603 static ssize_t
display_crc_ctl_write(struct file
*file
, const char __user
*ubuf
,
3604 size_t len
, loff_t
*offp
)
3606 struct seq_file
*m
= file
->private_data
;
3607 struct drm_device
*dev
= m
->private;
3614 if (len
> PAGE_SIZE
- 1) {
3615 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3620 tmpbuf
= kmalloc(len
+ 1, GFP_KERNEL
);
3624 if (copy_from_user(tmpbuf
, ubuf
, len
)) {
3630 ret
= display_crc_ctl_parse(dev
, tmpbuf
, len
);
3641 static const struct file_operations i915_display_crc_ctl_fops
= {
3642 .owner
= THIS_MODULE
,
3643 .open
= display_crc_ctl_open
,
3645 .llseek
= seq_lseek
,
3646 .release
= single_release
,
3647 .write
= display_crc_ctl_write
3650 static void wm_latency_show(struct seq_file
*m
, const uint16_t wm
[8])
3652 struct drm_device
*dev
= m
->private;
3653 int num_levels
= ilk_wm_max_level(dev
) + 1;
3656 drm_modeset_lock_all(dev
);
3658 for (level
= 0; level
< num_levels
; level
++) {
3659 unsigned int latency
= wm
[level
];
3662 * - WM1+ latency values in 0.5us units
3663 * - latencies are in us on gen9
3665 if (INTEL_INFO(dev
)->gen
>= 9)
3670 seq_printf(m
, "WM%d %u (%u.%u usec)\n",
3671 level
, wm
[level
], latency
/ 10, latency
% 10);
3674 drm_modeset_unlock_all(dev
);
3677 static int pri_wm_latency_show(struct seq_file
*m
, void *data
)
3679 struct drm_device
*dev
= m
->private;
3680 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3681 const uint16_t *latencies
;
3683 if (INTEL_INFO(dev
)->gen
>= 9)
3684 latencies
= dev_priv
->wm
.skl_latency
;
3686 latencies
= to_i915(dev
)->wm
.pri_latency
;
3688 wm_latency_show(m
, latencies
);
3693 static int spr_wm_latency_show(struct seq_file
*m
, void *data
)
3695 struct drm_device
*dev
= m
->private;
3696 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3697 const uint16_t *latencies
;
3699 if (INTEL_INFO(dev
)->gen
>= 9)
3700 latencies
= dev_priv
->wm
.skl_latency
;
3702 latencies
= to_i915(dev
)->wm
.spr_latency
;
3704 wm_latency_show(m
, latencies
);
3709 static int cur_wm_latency_show(struct seq_file
*m
, void *data
)
3711 struct drm_device
*dev
= m
->private;
3712 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3713 const uint16_t *latencies
;
3715 if (INTEL_INFO(dev
)->gen
>= 9)
3716 latencies
= dev_priv
->wm
.skl_latency
;
3718 latencies
= to_i915(dev
)->wm
.cur_latency
;
3720 wm_latency_show(m
, latencies
);
3725 static int pri_wm_latency_open(struct inode
*inode
, struct file
*file
)
3727 struct drm_device
*dev
= inode
->i_private
;
3729 if (HAS_GMCH_DISPLAY(dev
))
3732 return single_open(file
, pri_wm_latency_show
, dev
);
3735 static int spr_wm_latency_open(struct inode
*inode
, struct file
*file
)
3737 struct drm_device
*dev
= inode
->i_private
;
3739 if (HAS_GMCH_DISPLAY(dev
))
3742 return single_open(file
, spr_wm_latency_show
, dev
);
3745 static int cur_wm_latency_open(struct inode
*inode
, struct file
*file
)
3747 struct drm_device
*dev
= inode
->i_private
;
3749 if (HAS_GMCH_DISPLAY(dev
))
3752 return single_open(file
, cur_wm_latency_show
, dev
);
3755 static ssize_t
wm_latency_write(struct file
*file
, const char __user
*ubuf
,
3756 size_t len
, loff_t
*offp
, uint16_t wm
[8])
3758 struct seq_file
*m
= file
->private_data
;
3759 struct drm_device
*dev
= m
->private;
3760 uint16_t new[8] = { 0 };
3761 int num_levels
= ilk_wm_max_level(dev
) + 1;
3766 if (len
>= sizeof(tmp
))
3769 if (copy_from_user(tmp
, ubuf
, len
))
3774 ret
= sscanf(tmp
, "%hu %hu %hu %hu %hu %hu %hu %hu",
3775 &new[0], &new[1], &new[2], &new[3],
3776 &new[4], &new[5], &new[6], &new[7]);
3777 if (ret
!= num_levels
)
3780 drm_modeset_lock_all(dev
);
3782 for (level
= 0; level
< num_levels
; level
++)
3783 wm
[level
] = new[level
];
3785 drm_modeset_unlock_all(dev
);
3791 static ssize_t
pri_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
3792 size_t len
, loff_t
*offp
)
3794 struct seq_file
*m
= file
->private_data
;
3795 struct drm_device
*dev
= m
->private;
3796 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3797 uint16_t *latencies
;
3799 if (INTEL_INFO(dev
)->gen
>= 9)
3800 latencies
= dev_priv
->wm
.skl_latency
;
3802 latencies
= to_i915(dev
)->wm
.pri_latency
;
3804 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
3807 static ssize_t
spr_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
3808 size_t len
, loff_t
*offp
)
3810 struct seq_file
*m
= file
->private_data
;
3811 struct drm_device
*dev
= m
->private;
3812 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3813 uint16_t *latencies
;
3815 if (INTEL_INFO(dev
)->gen
>= 9)
3816 latencies
= dev_priv
->wm
.skl_latency
;
3818 latencies
= to_i915(dev
)->wm
.spr_latency
;
3820 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
3823 static ssize_t
cur_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
3824 size_t len
, loff_t
*offp
)
3826 struct seq_file
*m
= file
->private_data
;
3827 struct drm_device
*dev
= m
->private;
3828 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3829 uint16_t *latencies
;
3831 if (INTEL_INFO(dev
)->gen
>= 9)
3832 latencies
= dev_priv
->wm
.skl_latency
;
3834 latencies
= to_i915(dev
)->wm
.cur_latency
;
3836 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
3839 static const struct file_operations i915_pri_wm_latency_fops
= {
3840 .owner
= THIS_MODULE
,
3841 .open
= pri_wm_latency_open
,
3843 .llseek
= seq_lseek
,
3844 .release
= single_release
,
3845 .write
= pri_wm_latency_write
3848 static const struct file_operations i915_spr_wm_latency_fops
= {
3849 .owner
= THIS_MODULE
,
3850 .open
= spr_wm_latency_open
,
3852 .llseek
= seq_lseek
,
3853 .release
= single_release
,
3854 .write
= spr_wm_latency_write
3857 static const struct file_operations i915_cur_wm_latency_fops
= {
3858 .owner
= THIS_MODULE
,
3859 .open
= cur_wm_latency_open
,
3861 .llseek
= seq_lseek
,
3862 .release
= single_release
,
3863 .write
= cur_wm_latency_write
3867 i915_wedged_get(void *data
, u64
*val
)
3869 struct drm_device
*dev
= data
;
3870 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3872 *val
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
3878 i915_wedged_set(void *data
, u64 val
)
3880 struct drm_device
*dev
= data
;
3881 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3883 intel_runtime_pm_get(dev_priv
);
3885 i915_handle_error(dev
, val
,
3886 "Manually setting wedged to %llu", val
);
3888 intel_runtime_pm_put(dev_priv
);
3893 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops
,
3894 i915_wedged_get
, i915_wedged_set
,
3898 i915_ring_stop_get(void *data
, u64
*val
)
3900 struct drm_device
*dev
= data
;
3901 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3903 *val
= dev_priv
->gpu_error
.stop_rings
;
3909 i915_ring_stop_set(void *data
, u64 val
)
3911 struct drm_device
*dev
= data
;
3912 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3915 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val
);
3917 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3921 dev_priv
->gpu_error
.stop_rings
= val
;
3922 mutex_unlock(&dev
->struct_mutex
);
3927 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops
,
3928 i915_ring_stop_get
, i915_ring_stop_set
,
3932 i915_ring_missed_irq_get(void *data
, u64
*val
)
3934 struct drm_device
*dev
= data
;
3935 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3937 *val
= dev_priv
->gpu_error
.missed_irq_rings
;
3942 i915_ring_missed_irq_set(void *data
, u64 val
)
3944 struct drm_device
*dev
= data
;
3945 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3948 /* Lock against concurrent debugfs callers */
3949 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3952 dev_priv
->gpu_error
.missed_irq_rings
= val
;
3953 mutex_unlock(&dev
->struct_mutex
);
3958 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops
,
3959 i915_ring_missed_irq_get
, i915_ring_missed_irq_set
,
3963 i915_ring_test_irq_get(void *data
, u64
*val
)
3965 struct drm_device
*dev
= data
;
3966 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3968 *val
= dev_priv
->gpu_error
.test_irq_rings
;
3974 i915_ring_test_irq_set(void *data
, u64 val
)
3976 struct drm_device
*dev
= data
;
3977 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3980 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val
);
3982 /* Lock against concurrent debugfs callers */
3983 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3987 dev_priv
->gpu_error
.test_irq_rings
= val
;
3988 mutex_unlock(&dev
->struct_mutex
);
3993 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops
,
3994 i915_ring_test_irq_get
, i915_ring_test_irq_set
,
3997 #define DROP_UNBOUND 0x1
3998 #define DROP_BOUND 0x2
3999 #define DROP_RETIRE 0x4
4000 #define DROP_ACTIVE 0x8
4001 #define DROP_ALL (DROP_UNBOUND | \
4006 i915_drop_caches_get(void *data
, u64
*val
)
4014 i915_drop_caches_set(void *data
, u64 val
)
4016 struct drm_device
*dev
= data
;
4017 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4020 DRM_DEBUG("Dropping caches: 0x%08llx\n", val
);
4022 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4023 * on ioctls on -EAGAIN. */
4024 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4028 if (val
& DROP_ACTIVE
) {
4029 ret
= i915_gpu_idle(dev
);
4034 if (val
& (DROP_RETIRE
| DROP_ACTIVE
))
4035 i915_gem_retire_requests(dev
);
4037 if (val
& DROP_BOUND
)
4038 i915_gem_shrink(dev_priv
, LONG_MAX
, I915_SHRINK_BOUND
);
4040 if (val
& DROP_UNBOUND
)
4041 i915_gem_shrink(dev_priv
, LONG_MAX
, I915_SHRINK_UNBOUND
);
4044 mutex_unlock(&dev
->struct_mutex
);
4049 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops
,
4050 i915_drop_caches_get
, i915_drop_caches_set
,
4054 i915_max_freq_get(void *data
, u64
*val
)
4056 struct drm_device
*dev
= data
;
4057 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4060 if (INTEL_INFO(dev
)->gen
< 6)
4063 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4065 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4069 if (IS_VALLEYVIEW(dev
))
4070 *val
= vlv_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq_softlimit
);
4072 *val
= dev_priv
->rps
.max_freq_softlimit
* GT_FREQUENCY_MULTIPLIER
;
4073 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4079 i915_max_freq_set(void *data
, u64 val
)
4081 struct drm_device
*dev
= data
;
4082 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4083 u32 rp_state_cap
, hw_max
, hw_min
;
4086 if (INTEL_INFO(dev
)->gen
< 6)
4089 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4091 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val
);
4093 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4098 * Turbo will still be enabled, but won't go above the set value.
4100 if (IS_VALLEYVIEW(dev
)) {
4101 val
= vlv_freq_opcode(dev_priv
, val
);
4103 hw_max
= dev_priv
->rps
.max_freq
;
4104 hw_min
= dev_priv
->rps
.min_freq
;
4106 do_div(val
, GT_FREQUENCY_MULTIPLIER
);
4108 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
4109 hw_max
= dev_priv
->rps
.max_freq
;
4110 hw_min
= (rp_state_cap
>> 16) & 0xff;
4113 if (val
< hw_min
|| val
> hw_max
|| val
< dev_priv
->rps
.min_freq_softlimit
) {
4114 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4118 dev_priv
->rps
.max_freq_softlimit
= val
;
4120 if (IS_VALLEYVIEW(dev
))
4121 valleyview_set_rps(dev
, val
);
4123 gen6_set_rps(dev
, val
);
4125 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4130 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops
,
4131 i915_max_freq_get
, i915_max_freq_set
,
4135 i915_min_freq_get(void *data
, u64
*val
)
4137 struct drm_device
*dev
= data
;
4138 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4141 if (INTEL_INFO(dev
)->gen
< 6)
4144 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4146 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4150 if (IS_VALLEYVIEW(dev
))
4151 *val
= vlv_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq_softlimit
);
4153 *val
= dev_priv
->rps
.min_freq_softlimit
* GT_FREQUENCY_MULTIPLIER
;
4154 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4160 i915_min_freq_set(void *data
, u64 val
)
4162 struct drm_device
*dev
= data
;
4163 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4164 u32 rp_state_cap
, hw_max
, hw_min
;
4167 if (INTEL_INFO(dev
)->gen
< 6)
4170 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4172 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val
);
4174 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4179 * Turbo will still be enabled, but won't go below the set value.
4181 if (IS_VALLEYVIEW(dev
)) {
4182 val
= vlv_freq_opcode(dev_priv
, val
);
4184 hw_max
= dev_priv
->rps
.max_freq
;
4185 hw_min
= dev_priv
->rps
.min_freq
;
4187 do_div(val
, GT_FREQUENCY_MULTIPLIER
);
4189 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
4190 hw_max
= dev_priv
->rps
.max_freq
;
4191 hw_min
= (rp_state_cap
>> 16) & 0xff;
4194 if (val
< hw_min
|| val
> hw_max
|| val
> dev_priv
->rps
.max_freq_softlimit
) {
4195 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4199 dev_priv
->rps
.min_freq_softlimit
= val
;
4201 if (IS_VALLEYVIEW(dev
))
4202 valleyview_set_rps(dev
, val
);
4204 gen6_set_rps(dev
, val
);
4206 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4211 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops
,
4212 i915_min_freq_get
, i915_min_freq_set
,
4216 i915_cache_sharing_get(void *data
, u64
*val
)
4218 struct drm_device
*dev
= data
;
4219 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4223 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
4226 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4229 intel_runtime_pm_get(dev_priv
);
4231 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
4233 intel_runtime_pm_put(dev_priv
);
4234 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
4236 *val
= (snpcr
& GEN6_MBC_SNPCR_MASK
) >> GEN6_MBC_SNPCR_SHIFT
;
4242 i915_cache_sharing_set(void *data
, u64 val
)
4244 struct drm_device
*dev
= data
;
4245 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4248 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
4254 intel_runtime_pm_get(dev_priv
);
4255 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val
);
4257 /* Update the cache sharing policy here as well */
4258 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
4259 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
4260 snpcr
|= (val
<< GEN6_MBC_SNPCR_SHIFT
);
4261 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
4263 intel_runtime_pm_put(dev_priv
);
4267 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops
,
4268 i915_cache_sharing_get
, i915_cache_sharing_set
,
4271 static int i915_forcewake_open(struct inode
*inode
, struct file
*file
)
4273 struct drm_device
*dev
= inode
->i_private
;
4274 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4276 if (INTEL_INFO(dev
)->gen
< 6)
4279 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
4284 static int i915_forcewake_release(struct inode
*inode
, struct file
*file
)
4286 struct drm_device
*dev
= inode
->i_private
;
4287 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4289 if (INTEL_INFO(dev
)->gen
< 6)
4292 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
4297 static const struct file_operations i915_forcewake_fops
= {
4298 .owner
= THIS_MODULE
,
4299 .open
= i915_forcewake_open
,
4300 .release
= i915_forcewake_release
,
4303 static int i915_forcewake_create(struct dentry
*root
, struct drm_minor
*minor
)
4305 struct drm_device
*dev
= minor
->dev
;
4308 ent
= debugfs_create_file("i915_forcewake_user",
4311 &i915_forcewake_fops
);
4315 return drm_add_fake_info_node(minor
, ent
, &i915_forcewake_fops
);
4318 static int i915_debugfs_create(struct dentry
*root
,
4319 struct drm_minor
*minor
,
4321 const struct file_operations
*fops
)
4323 struct drm_device
*dev
= minor
->dev
;
4326 ent
= debugfs_create_file(name
,
4333 return drm_add_fake_info_node(minor
, ent
, fops
);
4336 static const struct drm_info_list i915_debugfs_list
[] = {
4337 {"i915_capabilities", i915_capabilities
, 0},
4338 {"i915_gem_objects", i915_gem_object_info
, 0},
4339 {"i915_gem_gtt", i915_gem_gtt_info
, 0},
4340 {"i915_gem_pinned", i915_gem_gtt_info
, 0, (void *) PINNED_LIST
},
4341 {"i915_gem_active", i915_gem_object_list_info
, 0, (void *) ACTIVE_LIST
},
4342 {"i915_gem_inactive", i915_gem_object_list_info
, 0, (void *) INACTIVE_LIST
},
4343 {"i915_gem_stolen", i915_gem_stolen_list_info
},
4344 {"i915_gem_pageflip", i915_gem_pageflip_info
, 0},
4345 {"i915_gem_request", i915_gem_request_info
, 0},
4346 {"i915_gem_seqno", i915_gem_seqno_info
, 0},
4347 {"i915_gem_fence_regs", i915_gem_fence_regs_info
, 0},
4348 {"i915_gem_interrupt", i915_interrupt_info
, 0},
4349 {"i915_gem_hws", i915_hws_info
, 0, (void *)RCS
},
4350 {"i915_gem_hws_blt", i915_hws_info
, 0, (void *)BCS
},
4351 {"i915_gem_hws_bsd", i915_hws_info
, 0, (void *)VCS
},
4352 {"i915_gem_hws_vebox", i915_hws_info
, 0, (void *)VECS
},
4353 {"i915_frequency_info", i915_frequency_info
, 0},
4354 {"i915_drpc_info", i915_drpc_info
, 0},
4355 {"i915_emon_status", i915_emon_status
, 0},
4356 {"i915_ring_freq_table", i915_ring_freq_table
, 0},
4357 {"i915_fbc_status", i915_fbc_status
, 0},
4358 {"i915_ips_status", i915_ips_status
, 0},
4359 {"i915_sr_status", i915_sr_status
, 0},
4360 {"i915_opregion", i915_opregion
, 0},
4361 {"i915_gem_framebuffer", i915_gem_framebuffer_info
, 0},
4362 {"i915_context_status", i915_context_status
, 0},
4363 {"i915_dump_lrc", i915_dump_lrc
, 0},
4364 {"i915_execlists", i915_execlists
, 0},
4365 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info
, 0},
4366 {"i915_swizzle_info", i915_swizzle_info
, 0},
4367 {"i915_ppgtt_info", i915_ppgtt_info
, 0},
4368 {"i915_llc", i915_llc
, 0},
4369 {"i915_edp_psr_status", i915_edp_psr_status
, 0},
4370 {"i915_sink_crc_eDP1", i915_sink_crc
, 0},
4371 {"i915_energy_uJ", i915_energy_uJ
, 0},
4372 {"i915_pc8_status", i915_pc8_status
, 0},
4373 {"i915_power_domain_info", i915_power_domain_info
, 0},
4374 {"i915_display_info", i915_display_info
, 0},
4375 {"i915_semaphore_status", i915_semaphore_status
, 0},
4376 {"i915_shared_dplls_info", i915_shared_dplls_info
, 0},
4377 {"i915_dp_mst_info", i915_dp_mst_info
, 0},
4378 {"i915_wa_registers", i915_wa_registers
, 0},
4379 {"i915_ddb_info", i915_ddb_info
, 0},
4381 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
4383 static const struct i915_debugfs_files
{
4385 const struct file_operations
*fops
;
4386 } i915_debugfs_files
[] = {
4387 {"i915_wedged", &i915_wedged_fops
},
4388 {"i915_max_freq", &i915_max_freq_fops
},
4389 {"i915_min_freq", &i915_min_freq_fops
},
4390 {"i915_cache_sharing", &i915_cache_sharing_fops
},
4391 {"i915_ring_stop", &i915_ring_stop_fops
},
4392 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops
},
4393 {"i915_ring_test_irq", &i915_ring_test_irq_fops
},
4394 {"i915_gem_drop_caches", &i915_drop_caches_fops
},
4395 {"i915_error_state", &i915_error_state_fops
},
4396 {"i915_next_seqno", &i915_next_seqno_fops
},
4397 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops
},
4398 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops
},
4399 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops
},
4400 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops
},
4401 {"i915_fbc_false_color", &i915_fbc_fc_fops
},
4404 void intel_display_crc_init(struct drm_device
*dev
)
4406 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4409 for_each_pipe(dev_priv
, pipe
) {
4410 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
4412 pipe_crc
->opened
= false;
4413 spin_lock_init(&pipe_crc
->lock
);
4414 init_waitqueue_head(&pipe_crc
->wq
);
4418 int i915_debugfs_init(struct drm_minor
*minor
)
4422 ret
= i915_forcewake_create(minor
->debugfs_root
, minor
);
4426 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
4427 ret
= i915_pipe_crc_create(minor
->debugfs_root
, minor
, i
);
4432 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
4433 ret
= i915_debugfs_create(minor
->debugfs_root
, minor
,
4434 i915_debugfs_files
[i
].name
,
4435 i915_debugfs_files
[i
].fops
);
4440 return drm_debugfs_create_files(i915_debugfs_list
,
4441 I915_DEBUGFS_ENTRIES
,
4442 minor
->debugfs_root
, minor
);
4445 void i915_debugfs_cleanup(struct drm_minor
*minor
)
4449 drm_debugfs_remove_files(i915_debugfs_list
,
4450 I915_DEBUGFS_ENTRIES
, minor
);
4452 drm_debugfs_remove_files((struct drm_info_list
*) &i915_forcewake_fops
,
4455 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
4456 struct drm_info_list
*info_list
=
4457 (struct drm_info_list
*)&i915_pipe_crc_data
[i
];
4459 drm_debugfs_remove_files(info_list
, 1, minor
);
4462 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
4463 struct drm_info_list
*info_list
=
4464 (struct drm_info_list
*) i915_debugfs_files
[i
].fops
;
4466 drm_debugfs_remove_files(info_list
, 1, minor
);