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drm/i915: Integrate GuC-based command submission
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
37 #include <drm/drmP.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
41 #include "i915_drv.h"
42
43 enum {
44 ACTIVE_LIST,
45 INACTIVE_LIST,
46 PINNED_LIST,
47 };
48
49 static const char *yesno(int v)
50 {
51 return v ? "yes" : "no";
52 }
53
54 /* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
56 static int
57 drm_add_fake_info_node(struct drm_minor *minor,
58 struct dentry *ent,
59 const void *key)
60 {
61 struct drm_info_node *node;
62
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
64 if (node == NULL) {
65 debugfs_remove(ent);
66 return -ENOMEM;
67 }
68
69 node->minor = minor;
70 node->dent = ent;
71 node->info_ent = (void *) key;
72
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
76
77 return 0;
78 }
79
80 static int i915_capabilities(struct seq_file *m, void *data)
81 {
82 struct drm_info_node *node = m->private;
83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
85
86 seq_printf(m, "gen: %d\n", info->gen);
87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
88 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89 #define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
91 #undef PRINT_FLAG
92 #undef SEP_SEMICOLON
93
94 return 0;
95 }
96
97 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
98 {
99 if (obj->pin_display)
100 return "p";
101 else
102 return " ";
103 }
104
105 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
106 {
107 switch (obj->tiling_mode) {
108 default:
109 case I915_TILING_NONE: return " ";
110 case I915_TILING_X: return "X";
111 case I915_TILING_Y: return "Y";
112 }
113 }
114
115 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
116 {
117 return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
118 }
119
120 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
121 {
122 u64 size = 0;
123 struct i915_vma *vma;
124
125 list_for_each_entry(vma, &obj->vma_list, vma_link) {
126 if (i915_is_ggtt(vma->vm) &&
127 drm_mm_node_allocated(&vma->node))
128 size += vma->node.size;
129 }
130
131 return size;
132 }
133
134 static void
135 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
136 {
137 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
138 struct intel_engine_cs *ring;
139 struct i915_vma *vma;
140 int pin_count = 0;
141 int i;
142
143 seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ",
144 &obj->base,
145 obj->active ? "*" : " ",
146 get_pin_flag(obj),
147 get_tiling_flag(obj),
148 get_global_flag(obj),
149 obj->base.size / 1024,
150 obj->base.read_domains,
151 obj->base.write_domain);
152 for_each_ring(ring, dev_priv, i)
153 seq_printf(m, "%x ",
154 i915_gem_request_get_seqno(obj->last_read_req[i]));
155 seq_printf(m, "] %x %x%s%s%s",
156 i915_gem_request_get_seqno(obj->last_write_req),
157 i915_gem_request_get_seqno(obj->last_fenced_req),
158 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
159 obj->dirty ? " dirty" : "",
160 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
161 if (obj->base.name)
162 seq_printf(m, " (name: %d)", obj->base.name);
163 list_for_each_entry(vma, &obj->vma_list, vma_link) {
164 if (vma->pin_count > 0)
165 pin_count++;
166 }
167 seq_printf(m, " (pinned x %d)", pin_count);
168 if (obj->pin_display)
169 seq_printf(m, " (display)");
170 if (obj->fence_reg != I915_FENCE_REG_NONE)
171 seq_printf(m, " (fence: %d)", obj->fence_reg);
172 list_for_each_entry(vma, &obj->vma_list, vma_link) {
173 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
174 i915_is_ggtt(vma->vm) ? "g" : "pp",
175 vma->node.start, vma->node.size);
176 if (i915_is_ggtt(vma->vm))
177 seq_printf(m, ", type: %u)", vma->ggtt_view.type);
178 else
179 seq_puts(m, ")");
180 }
181 if (obj->stolen)
182 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
183 if (obj->pin_display || obj->fault_mappable) {
184 char s[3], *t = s;
185 if (obj->pin_display)
186 *t++ = 'p';
187 if (obj->fault_mappable)
188 *t++ = 'f';
189 *t = '\0';
190 seq_printf(m, " (%s mappable)", s);
191 }
192 if (obj->last_write_req != NULL)
193 seq_printf(m, " (%s)",
194 i915_gem_request_get_ring(obj->last_write_req)->name);
195 if (obj->frontbuffer_bits)
196 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
197 }
198
199 static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
200 {
201 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
202 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
203 seq_putc(m, ' ');
204 }
205
206 static int i915_gem_object_list_info(struct seq_file *m, void *data)
207 {
208 struct drm_info_node *node = m->private;
209 uintptr_t list = (uintptr_t) node->info_ent->data;
210 struct list_head *head;
211 struct drm_device *dev = node->minor->dev;
212 struct drm_i915_private *dev_priv = dev->dev_private;
213 struct i915_address_space *vm = &dev_priv->gtt.base;
214 struct i915_vma *vma;
215 u64 total_obj_size, total_gtt_size;
216 int count, ret;
217
218 ret = mutex_lock_interruptible(&dev->struct_mutex);
219 if (ret)
220 return ret;
221
222 /* FIXME: the user of this interface might want more than just GGTT */
223 switch (list) {
224 case ACTIVE_LIST:
225 seq_puts(m, "Active:\n");
226 head = &vm->active_list;
227 break;
228 case INACTIVE_LIST:
229 seq_puts(m, "Inactive:\n");
230 head = &vm->inactive_list;
231 break;
232 default:
233 mutex_unlock(&dev->struct_mutex);
234 return -EINVAL;
235 }
236
237 total_obj_size = total_gtt_size = count = 0;
238 list_for_each_entry(vma, head, mm_list) {
239 seq_printf(m, " ");
240 describe_obj(m, vma->obj);
241 seq_printf(m, "\n");
242 total_obj_size += vma->obj->base.size;
243 total_gtt_size += vma->node.size;
244 count++;
245 }
246 mutex_unlock(&dev->struct_mutex);
247
248 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
249 count, total_obj_size, total_gtt_size);
250 return 0;
251 }
252
253 static int obj_rank_by_stolen(void *priv,
254 struct list_head *A, struct list_head *B)
255 {
256 struct drm_i915_gem_object *a =
257 container_of(A, struct drm_i915_gem_object, obj_exec_link);
258 struct drm_i915_gem_object *b =
259 container_of(B, struct drm_i915_gem_object, obj_exec_link);
260
261 return a->stolen->start - b->stolen->start;
262 }
263
264 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
265 {
266 struct drm_info_node *node = m->private;
267 struct drm_device *dev = node->minor->dev;
268 struct drm_i915_private *dev_priv = dev->dev_private;
269 struct drm_i915_gem_object *obj;
270 u64 total_obj_size, total_gtt_size;
271 LIST_HEAD(stolen);
272 int count, ret;
273
274 ret = mutex_lock_interruptible(&dev->struct_mutex);
275 if (ret)
276 return ret;
277
278 total_obj_size = total_gtt_size = count = 0;
279 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
280 if (obj->stolen == NULL)
281 continue;
282
283 list_add(&obj->obj_exec_link, &stolen);
284
285 total_obj_size += obj->base.size;
286 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
287 count++;
288 }
289 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
290 if (obj->stolen == NULL)
291 continue;
292
293 list_add(&obj->obj_exec_link, &stolen);
294
295 total_obj_size += obj->base.size;
296 count++;
297 }
298 list_sort(NULL, &stolen, obj_rank_by_stolen);
299 seq_puts(m, "Stolen:\n");
300 while (!list_empty(&stolen)) {
301 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
302 seq_puts(m, " ");
303 describe_obj(m, obj);
304 seq_putc(m, '\n');
305 list_del_init(&obj->obj_exec_link);
306 }
307 mutex_unlock(&dev->struct_mutex);
308
309 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
310 count, total_obj_size, total_gtt_size);
311 return 0;
312 }
313
314 #define count_objects(list, member) do { \
315 list_for_each_entry(obj, list, member) { \
316 size += i915_gem_obj_total_ggtt_size(obj); \
317 ++count; \
318 if (obj->map_and_fenceable) { \
319 mappable_size += i915_gem_obj_ggtt_size(obj); \
320 ++mappable_count; \
321 } \
322 } \
323 } while (0)
324
325 struct file_stats {
326 struct drm_i915_file_private *file_priv;
327 unsigned long count;
328 u64 total, unbound;
329 u64 global, shared;
330 u64 active, inactive;
331 };
332
333 static int per_file_stats(int id, void *ptr, void *data)
334 {
335 struct drm_i915_gem_object *obj = ptr;
336 struct file_stats *stats = data;
337 struct i915_vma *vma;
338
339 stats->count++;
340 stats->total += obj->base.size;
341
342 if (obj->base.name || obj->base.dma_buf)
343 stats->shared += obj->base.size;
344
345 if (USES_FULL_PPGTT(obj->base.dev)) {
346 list_for_each_entry(vma, &obj->vma_list, vma_link) {
347 struct i915_hw_ppgtt *ppgtt;
348
349 if (!drm_mm_node_allocated(&vma->node))
350 continue;
351
352 if (i915_is_ggtt(vma->vm)) {
353 stats->global += obj->base.size;
354 continue;
355 }
356
357 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
358 if (ppgtt->file_priv != stats->file_priv)
359 continue;
360
361 if (obj->active) /* XXX per-vma statistic */
362 stats->active += obj->base.size;
363 else
364 stats->inactive += obj->base.size;
365
366 return 0;
367 }
368 } else {
369 if (i915_gem_obj_ggtt_bound(obj)) {
370 stats->global += obj->base.size;
371 if (obj->active)
372 stats->active += obj->base.size;
373 else
374 stats->inactive += obj->base.size;
375 return 0;
376 }
377 }
378
379 if (!list_empty(&obj->global_list))
380 stats->unbound += obj->base.size;
381
382 return 0;
383 }
384
385 #define print_file_stats(m, name, stats) do { \
386 if (stats.count) \
387 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
388 name, \
389 stats.count, \
390 stats.total, \
391 stats.active, \
392 stats.inactive, \
393 stats.global, \
394 stats.shared, \
395 stats.unbound); \
396 } while (0)
397
398 static void print_batch_pool_stats(struct seq_file *m,
399 struct drm_i915_private *dev_priv)
400 {
401 struct drm_i915_gem_object *obj;
402 struct file_stats stats;
403 struct intel_engine_cs *ring;
404 int i, j;
405
406 memset(&stats, 0, sizeof(stats));
407
408 for_each_ring(ring, dev_priv, i) {
409 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
410 list_for_each_entry(obj,
411 &ring->batch_pool.cache_list[j],
412 batch_pool_link)
413 per_file_stats(0, obj, &stats);
414 }
415 }
416
417 print_file_stats(m, "[k]batch pool", stats);
418 }
419
420 #define count_vmas(list, member) do { \
421 list_for_each_entry(vma, list, member) { \
422 size += i915_gem_obj_total_ggtt_size(vma->obj); \
423 ++count; \
424 if (vma->obj->map_and_fenceable) { \
425 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
426 ++mappable_count; \
427 } \
428 } \
429 } while (0)
430
431 static int i915_gem_object_info(struct seq_file *m, void* data)
432 {
433 struct drm_info_node *node = m->private;
434 struct drm_device *dev = node->minor->dev;
435 struct drm_i915_private *dev_priv = dev->dev_private;
436 u32 count, mappable_count, purgeable_count;
437 u64 size, mappable_size, purgeable_size;
438 struct drm_i915_gem_object *obj;
439 struct i915_address_space *vm = &dev_priv->gtt.base;
440 struct drm_file *file;
441 struct i915_vma *vma;
442 int ret;
443
444 ret = mutex_lock_interruptible(&dev->struct_mutex);
445 if (ret)
446 return ret;
447
448 seq_printf(m, "%u objects, %zu bytes\n",
449 dev_priv->mm.object_count,
450 dev_priv->mm.object_memory);
451
452 size = count = mappable_size = mappable_count = 0;
453 count_objects(&dev_priv->mm.bound_list, global_list);
454 seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
455 count, mappable_count, size, mappable_size);
456
457 size = count = mappable_size = mappable_count = 0;
458 count_vmas(&vm->active_list, mm_list);
459 seq_printf(m, " %u [%u] active objects, %llu [%llu] bytes\n",
460 count, mappable_count, size, mappable_size);
461
462 size = count = mappable_size = mappable_count = 0;
463 count_vmas(&vm->inactive_list, mm_list);
464 seq_printf(m, " %u [%u] inactive objects, %llu [%llu] bytes\n",
465 count, mappable_count, size, mappable_size);
466
467 size = count = purgeable_size = purgeable_count = 0;
468 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
469 size += obj->base.size, ++count;
470 if (obj->madv == I915_MADV_DONTNEED)
471 purgeable_size += obj->base.size, ++purgeable_count;
472 }
473 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
474
475 size = count = mappable_size = mappable_count = 0;
476 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
477 if (obj->fault_mappable) {
478 size += i915_gem_obj_ggtt_size(obj);
479 ++count;
480 }
481 if (obj->pin_display) {
482 mappable_size += i915_gem_obj_ggtt_size(obj);
483 ++mappable_count;
484 }
485 if (obj->madv == I915_MADV_DONTNEED) {
486 purgeable_size += obj->base.size;
487 ++purgeable_count;
488 }
489 }
490 seq_printf(m, "%u purgeable objects, %llu bytes\n",
491 purgeable_count, purgeable_size);
492 seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
493 mappable_count, mappable_size);
494 seq_printf(m, "%u fault mappable objects, %llu bytes\n",
495 count, size);
496
497 seq_printf(m, "%llu [%llu] gtt total\n",
498 dev_priv->gtt.base.total,
499 (u64)dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
500
501 seq_putc(m, '\n');
502 print_batch_pool_stats(m, dev_priv);
503 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
504 struct file_stats stats;
505 struct task_struct *task;
506
507 memset(&stats, 0, sizeof(stats));
508 stats.file_priv = file->driver_priv;
509 spin_lock(&file->table_lock);
510 idr_for_each(&file->object_idr, per_file_stats, &stats);
511 spin_unlock(&file->table_lock);
512 /*
513 * Although we have a valid reference on file->pid, that does
514 * not guarantee that the task_struct who called get_pid() is
515 * still alive (e.g. get_pid(current) => fork() => exit()).
516 * Therefore, we need to protect this ->comm access using RCU.
517 */
518 rcu_read_lock();
519 task = pid_task(file->pid, PIDTYPE_PID);
520 print_file_stats(m, task ? task->comm : "<unknown>", stats);
521 rcu_read_unlock();
522 }
523
524 mutex_unlock(&dev->struct_mutex);
525
526 return 0;
527 }
528
529 static int i915_gem_gtt_info(struct seq_file *m, void *data)
530 {
531 struct drm_info_node *node = m->private;
532 struct drm_device *dev = node->minor->dev;
533 uintptr_t list = (uintptr_t) node->info_ent->data;
534 struct drm_i915_private *dev_priv = dev->dev_private;
535 struct drm_i915_gem_object *obj;
536 u64 total_obj_size, total_gtt_size;
537 int count, ret;
538
539 ret = mutex_lock_interruptible(&dev->struct_mutex);
540 if (ret)
541 return ret;
542
543 total_obj_size = total_gtt_size = count = 0;
544 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
545 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
546 continue;
547
548 seq_puts(m, " ");
549 describe_obj(m, obj);
550 seq_putc(m, '\n');
551 total_obj_size += obj->base.size;
552 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
553 count++;
554 }
555
556 mutex_unlock(&dev->struct_mutex);
557
558 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
559 count, total_obj_size, total_gtt_size);
560
561 return 0;
562 }
563
564 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
565 {
566 struct drm_info_node *node = m->private;
567 struct drm_device *dev = node->minor->dev;
568 struct drm_i915_private *dev_priv = dev->dev_private;
569 struct intel_crtc *crtc;
570 int ret;
571
572 ret = mutex_lock_interruptible(&dev->struct_mutex);
573 if (ret)
574 return ret;
575
576 for_each_intel_crtc(dev, crtc) {
577 const char pipe = pipe_name(crtc->pipe);
578 const char plane = plane_name(crtc->plane);
579 struct intel_unpin_work *work;
580
581 spin_lock_irq(&dev->event_lock);
582 work = crtc->unpin_work;
583 if (work == NULL) {
584 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
585 pipe, plane);
586 } else {
587 u32 addr;
588
589 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
590 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
591 pipe, plane);
592 } else {
593 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
594 pipe, plane);
595 }
596 if (work->flip_queued_req) {
597 struct intel_engine_cs *ring =
598 i915_gem_request_get_ring(work->flip_queued_req);
599
600 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
601 ring->name,
602 i915_gem_request_get_seqno(work->flip_queued_req),
603 dev_priv->next_seqno,
604 ring->get_seqno(ring, true),
605 i915_gem_request_completed(work->flip_queued_req, true));
606 } else
607 seq_printf(m, "Flip not associated with any ring\n");
608 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
609 work->flip_queued_vblank,
610 work->flip_ready_vblank,
611 drm_crtc_vblank_count(&crtc->base));
612 if (work->enable_stall_check)
613 seq_puts(m, "Stall check enabled, ");
614 else
615 seq_puts(m, "Stall check waiting for page flip ioctl, ");
616 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
617
618 if (INTEL_INFO(dev)->gen >= 4)
619 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
620 else
621 addr = I915_READ(DSPADDR(crtc->plane));
622 seq_printf(m, "Current scanout address 0x%08x\n", addr);
623
624 if (work->pending_flip_obj) {
625 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
626 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
627 }
628 }
629 spin_unlock_irq(&dev->event_lock);
630 }
631
632 mutex_unlock(&dev->struct_mutex);
633
634 return 0;
635 }
636
637 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
638 {
639 struct drm_info_node *node = m->private;
640 struct drm_device *dev = node->minor->dev;
641 struct drm_i915_private *dev_priv = dev->dev_private;
642 struct drm_i915_gem_object *obj;
643 struct intel_engine_cs *ring;
644 int total = 0;
645 int ret, i, j;
646
647 ret = mutex_lock_interruptible(&dev->struct_mutex);
648 if (ret)
649 return ret;
650
651 for_each_ring(ring, dev_priv, i) {
652 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
653 int count;
654
655 count = 0;
656 list_for_each_entry(obj,
657 &ring->batch_pool.cache_list[j],
658 batch_pool_link)
659 count++;
660 seq_printf(m, "%s cache[%d]: %d objects\n",
661 ring->name, j, count);
662
663 list_for_each_entry(obj,
664 &ring->batch_pool.cache_list[j],
665 batch_pool_link) {
666 seq_puts(m, " ");
667 describe_obj(m, obj);
668 seq_putc(m, '\n');
669 }
670
671 total += count;
672 }
673 }
674
675 seq_printf(m, "total: %d\n", total);
676
677 mutex_unlock(&dev->struct_mutex);
678
679 return 0;
680 }
681
682 static int i915_gem_request_info(struct seq_file *m, void *data)
683 {
684 struct drm_info_node *node = m->private;
685 struct drm_device *dev = node->minor->dev;
686 struct drm_i915_private *dev_priv = dev->dev_private;
687 struct intel_engine_cs *ring;
688 struct drm_i915_gem_request *req;
689 int ret, any, i;
690
691 ret = mutex_lock_interruptible(&dev->struct_mutex);
692 if (ret)
693 return ret;
694
695 any = 0;
696 for_each_ring(ring, dev_priv, i) {
697 int count;
698
699 count = 0;
700 list_for_each_entry(req, &ring->request_list, list)
701 count++;
702 if (count == 0)
703 continue;
704
705 seq_printf(m, "%s requests: %d\n", ring->name, count);
706 list_for_each_entry(req, &ring->request_list, list) {
707 struct task_struct *task;
708
709 rcu_read_lock();
710 task = NULL;
711 if (req->pid)
712 task = pid_task(req->pid, PIDTYPE_PID);
713 seq_printf(m, " %x @ %d: %s [%d]\n",
714 req->seqno,
715 (int) (jiffies - req->emitted_jiffies),
716 task ? task->comm : "<unknown>",
717 task ? task->pid : -1);
718 rcu_read_unlock();
719 }
720
721 any++;
722 }
723 mutex_unlock(&dev->struct_mutex);
724
725 if (any == 0)
726 seq_puts(m, "No requests\n");
727
728 return 0;
729 }
730
731 static void i915_ring_seqno_info(struct seq_file *m,
732 struct intel_engine_cs *ring)
733 {
734 if (ring->get_seqno) {
735 seq_printf(m, "Current sequence (%s): %x\n",
736 ring->name, ring->get_seqno(ring, false));
737 }
738 }
739
740 static int i915_gem_seqno_info(struct seq_file *m, void *data)
741 {
742 struct drm_info_node *node = m->private;
743 struct drm_device *dev = node->minor->dev;
744 struct drm_i915_private *dev_priv = dev->dev_private;
745 struct intel_engine_cs *ring;
746 int ret, i;
747
748 ret = mutex_lock_interruptible(&dev->struct_mutex);
749 if (ret)
750 return ret;
751 intel_runtime_pm_get(dev_priv);
752
753 for_each_ring(ring, dev_priv, i)
754 i915_ring_seqno_info(m, ring);
755
756 intel_runtime_pm_put(dev_priv);
757 mutex_unlock(&dev->struct_mutex);
758
759 return 0;
760 }
761
762
763 static int i915_interrupt_info(struct seq_file *m, void *data)
764 {
765 struct drm_info_node *node = m->private;
766 struct drm_device *dev = node->minor->dev;
767 struct drm_i915_private *dev_priv = dev->dev_private;
768 struct intel_engine_cs *ring;
769 int ret, i, pipe;
770
771 ret = mutex_lock_interruptible(&dev->struct_mutex);
772 if (ret)
773 return ret;
774 intel_runtime_pm_get(dev_priv);
775
776 if (IS_CHERRYVIEW(dev)) {
777 seq_printf(m, "Master Interrupt Control:\t%08x\n",
778 I915_READ(GEN8_MASTER_IRQ));
779
780 seq_printf(m, "Display IER:\t%08x\n",
781 I915_READ(VLV_IER));
782 seq_printf(m, "Display IIR:\t%08x\n",
783 I915_READ(VLV_IIR));
784 seq_printf(m, "Display IIR_RW:\t%08x\n",
785 I915_READ(VLV_IIR_RW));
786 seq_printf(m, "Display IMR:\t%08x\n",
787 I915_READ(VLV_IMR));
788 for_each_pipe(dev_priv, pipe)
789 seq_printf(m, "Pipe %c stat:\t%08x\n",
790 pipe_name(pipe),
791 I915_READ(PIPESTAT(pipe)));
792
793 seq_printf(m, "Port hotplug:\t%08x\n",
794 I915_READ(PORT_HOTPLUG_EN));
795 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
796 I915_READ(VLV_DPFLIPSTAT));
797 seq_printf(m, "DPINVGTT:\t%08x\n",
798 I915_READ(DPINVGTT));
799
800 for (i = 0; i < 4; i++) {
801 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
802 i, I915_READ(GEN8_GT_IMR(i)));
803 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
804 i, I915_READ(GEN8_GT_IIR(i)));
805 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
806 i, I915_READ(GEN8_GT_IER(i)));
807 }
808
809 seq_printf(m, "PCU interrupt mask:\t%08x\n",
810 I915_READ(GEN8_PCU_IMR));
811 seq_printf(m, "PCU interrupt identity:\t%08x\n",
812 I915_READ(GEN8_PCU_IIR));
813 seq_printf(m, "PCU interrupt enable:\t%08x\n",
814 I915_READ(GEN8_PCU_IER));
815 } else if (INTEL_INFO(dev)->gen >= 8) {
816 seq_printf(m, "Master Interrupt Control:\t%08x\n",
817 I915_READ(GEN8_MASTER_IRQ));
818
819 for (i = 0; i < 4; i++) {
820 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
821 i, I915_READ(GEN8_GT_IMR(i)));
822 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
823 i, I915_READ(GEN8_GT_IIR(i)));
824 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
825 i, I915_READ(GEN8_GT_IER(i)));
826 }
827
828 for_each_pipe(dev_priv, pipe) {
829 if (!intel_display_power_is_enabled(dev_priv,
830 POWER_DOMAIN_PIPE(pipe))) {
831 seq_printf(m, "Pipe %c power disabled\n",
832 pipe_name(pipe));
833 continue;
834 }
835 seq_printf(m, "Pipe %c IMR:\t%08x\n",
836 pipe_name(pipe),
837 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
838 seq_printf(m, "Pipe %c IIR:\t%08x\n",
839 pipe_name(pipe),
840 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
841 seq_printf(m, "Pipe %c IER:\t%08x\n",
842 pipe_name(pipe),
843 I915_READ(GEN8_DE_PIPE_IER(pipe)));
844 }
845
846 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
847 I915_READ(GEN8_DE_PORT_IMR));
848 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
849 I915_READ(GEN8_DE_PORT_IIR));
850 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
851 I915_READ(GEN8_DE_PORT_IER));
852
853 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
854 I915_READ(GEN8_DE_MISC_IMR));
855 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
856 I915_READ(GEN8_DE_MISC_IIR));
857 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
858 I915_READ(GEN8_DE_MISC_IER));
859
860 seq_printf(m, "PCU interrupt mask:\t%08x\n",
861 I915_READ(GEN8_PCU_IMR));
862 seq_printf(m, "PCU interrupt identity:\t%08x\n",
863 I915_READ(GEN8_PCU_IIR));
864 seq_printf(m, "PCU interrupt enable:\t%08x\n",
865 I915_READ(GEN8_PCU_IER));
866 } else if (IS_VALLEYVIEW(dev)) {
867 seq_printf(m, "Display IER:\t%08x\n",
868 I915_READ(VLV_IER));
869 seq_printf(m, "Display IIR:\t%08x\n",
870 I915_READ(VLV_IIR));
871 seq_printf(m, "Display IIR_RW:\t%08x\n",
872 I915_READ(VLV_IIR_RW));
873 seq_printf(m, "Display IMR:\t%08x\n",
874 I915_READ(VLV_IMR));
875 for_each_pipe(dev_priv, pipe)
876 seq_printf(m, "Pipe %c stat:\t%08x\n",
877 pipe_name(pipe),
878 I915_READ(PIPESTAT(pipe)));
879
880 seq_printf(m, "Master IER:\t%08x\n",
881 I915_READ(VLV_MASTER_IER));
882
883 seq_printf(m, "Render IER:\t%08x\n",
884 I915_READ(GTIER));
885 seq_printf(m, "Render IIR:\t%08x\n",
886 I915_READ(GTIIR));
887 seq_printf(m, "Render IMR:\t%08x\n",
888 I915_READ(GTIMR));
889
890 seq_printf(m, "PM IER:\t\t%08x\n",
891 I915_READ(GEN6_PMIER));
892 seq_printf(m, "PM IIR:\t\t%08x\n",
893 I915_READ(GEN6_PMIIR));
894 seq_printf(m, "PM IMR:\t\t%08x\n",
895 I915_READ(GEN6_PMIMR));
896
897 seq_printf(m, "Port hotplug:\t%08x\n",
898 I915_READ(PORT_HOTPLUG_EN));
899 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
900 I915_READ(VLV_DPFLIPSTAT));
901 seq_printf(m, "DPINVGTT:\t%08x\n",
902 I915_READ(DPINVGTT));
903
904 } else if (!HAS_PCH_SPLIT(dev)) {
905 seq_printf(m, "Interrupt enable: %08x\n",
906 I915_READ(IER));
907 seq_printf(m, "Interrupt identity: %08x\n",
908 I915_READ(IIR));
909 seq_printf(m, "Interrupt mask: %08x\n",
910 I915_READ(IMR));
911 for_each_pipe(dev_priv, pipe)
912 seq_printf(m, "Pipe %c stat: %08x\n",
913 pipe_name(pipe),
914 I915_READ(PIPESTAT(pipe)));
915 } else {
916 seq_printf(m, "North Display Interrupt enable: %08x\n",
917 I915_READ(DEIER));
918 seq_printf(m, "North Display Interrupt identity: %08x\n",
919 I915_READ(DEIIR));
920 seq_printf(m, "North Display Interrupt mask: %08x\n",
921 I915_READ(DEIMR));
922 seq_printf(m, "South Display Interrupt enable: %08x\n",
923 I915_READ(SDEIER));
924 seq_printf(m, "South Display Interrupt identity: %08x\n",
925 I915_READ(SDEIIR));
926 seq_printf(m, "South Display Interrupt mask: %08x\n",
927 I915_READ(SDEIMR));
928 seq_printf(m, "Graphics Interrupt enable: %08x\n",
929 I915_READ(GTIER));
930 seq_printf(m, "Graphics Interrupt identity: %08x\n",
931 I915_READ(GTIIR));
932 seq_printf(m, "Graphics Interrupt mask: %08x\n",
933 I915_READ(GTIMR));
934 }
935 for_each_ring(ring, dev_priv, i) {
936 if (INTEL_INFO(dev)->gen >= 6) {
937 seq_printf(m,
938 "Graphics Interrupt mask (%s): %08x\n",
939 ring->name, I915_READ_IMR(ring));
940 }
941 i915_ring_seqno_info(m, ring);
942 }
943 intel_runtime_pm_put(dev_priv);
944 mutex_unlock(&dev->struct_mutex);
945
946 return 0;
947 }
948
949 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
950 {
951 struct drm_info_node *node = m->private;
952 struct drm_device *dev = node->minor->dev;
953 struct drm_i915_private *dev_priv = dev->dev_private;
954 int i, ret;
955
956 ret = mutex_lock_interruptible(&dev->struct_mutex);
957 if (ret)
958 return ret;
959
960 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
961 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
962 for (i = 0; i < dev_priv->num_fence_regs; i++) {
963 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
964
965 seq_printf(m, "Fence %d, pin count = %d, object = ",
966 i, dev_priv->fence_regs[i].pin_count);
967 if (obj == NULL)
968 seq_puts(m, "unused");
969 else
970 describe_obj(m, obj);
971 seq_putc(m, '\n');
972 }
973
974 mutex_unlock(&dev->struct_mutex);
975 return 0;
976 }
977
978 static int i915_hws_info(struct seq_file *m, void *data)
979 {
980 struct drm_info_node *node = m->private;
981 struct drm_device *dev = node->minor->dev;
982 struct drm_i915_private *dev_priv = dev->dev_private;
983 struct intel_engine_cs *ring;
984 const u32 *hws;
985 int i;
986
987 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
988 hws = ring->status_page.page_addr;
989 if (hws == NULL)
990 return 0;
991
992 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
993 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
994 i * 4,
995 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
996 }
997 return 0;
998 }
999
1000 static ssize_t
1001 i915_error_state_write(struct file *filp,
1002 const char __user *ubuf,
1003 size_t cnt,
1004 loff_t *ppos)
1005 {
1006 struct i915_error_state_file_priv *error_priv = filp->private_data;
1007 struct drm_device *dev = error_priv->dev;
1008 int ret;
1009
1010 DRM_DEBUG_DRIVER("Resetting error state\n");
1011
1012 ret = mutex_lock_interruptible(&dev->struct_mutex);
1013 if (ret)
1014 return ret;
1015
1016 i915_destroy_error_state(dev);
1017 mutex_unlock(&dev->struct_mutex);
1018
1019 return cnt;
1020 }
1021
1022 static int i915_error_state_open(struct inode *inode, struct file *file)
1023 {
1024 struct drm_device *dev = inode->i_private;
1025 struct i915_error_state_file_priv *error_priv;
1026
1027 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1028 if (!error_priv)
1029 return -ENOMEM;
1030
1031 error_priv->dev = dev;
1032
1033 i915_error_state_get(dev, error_priv);
1034
1035 file->private_data = error_priv;
1036
1037 return 0;
1038 }
1039
1040 static int i915_error_state_release(struct inode *inode, struct file *file)
1041 {
1042 struct i915_error_state_file_priv *error_priv = file->private_data;
1043
1044 i915_error_state_put(error_priv);
1045 kfree(error_priv);
1046
1047 return 0;
1048 }
1049
1050 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1051 size_t count, loff_t *pos)
1052 {
1053 struct i915_error_state_file_priv *error_priv = file->private_data;
1054 struct drm_i915_error_state_buf error_str;
1055 loff_t tmp_pos = 0;
1056 ssize_t ret_count = 0;
1057 int ret;
1058
1059 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1060 if (ret)
1061 return ret;
1062
1063 ret = i915_error_state_to_str(&error_str, error_priv);
1064 if (ret)
1065 goto out;
1066
1067 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1068 error_str.buf,
1069 error_str.bytes);
1070
1071 if (ret_count < 0)
1072 ret = ret_count;
1073 else
1074 *pos = error_str.start + ret_count;
1075 out:
1076 i915_error_state_buf_release(&error_str);
1077 return ret ?: ret_count;
1078 }
1079
1080 static const struct file_operations i915_error_state_fops = {
1081 .owner = THIS_MODULE,
1082 .open = i915_error_state_open,
1083 .read = i915_error_state_read,
1084 .write = i915_error_state_write,
1085 .llseek = default_llseek,
1086 .release = i915_error_state_release,
1087 };
1088
1089 static int
1090 i915_next_seqno_get(void *data, u64 *val)
1091 {
1092 struct drm_device *dev = data;
1093 struct drm_i915_private *dev_priv = dev->dev_private;
1094 int ret;
1095
1096 ret = mutex_lock_interruptible(&dev->struct_mutex);
1097 if (ret)
1098 return ret;
1099
1100 *val = dev_priv->next_seqno;
1101 mutex_unlock(&dev->struct_mutex);
1102
1103 return 0;
1104 }
1105
1106 static int
1107 i915_next_seqno_set(void *data, u64 val)
1108 {
1109 struct drm_device *dev = data;
1110 int ret;
1111
1112 ret = mutex_lock_interruptible(&dev->struct_mutex);
1113 if (ret)
1114 return ret;
1115
1116 ret = i915_gem_set_seqno(dev, val);
1117 mutex_unlock(&dev->struct_mutex);
1118
1119 return ret;
1120 }
1121
1122 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1123 i915_next_seqno_get, i915_next_seqno_set,
1124 "0x%llx\n");
1125
1126 static int i915_frequency_info(struct seq_file *m, void *unused)
1127 {
1128 struct drm_info_node *node = m->private;
1129 struct drm_device *dev = node->minor->dev;
1130 struct drm_i915_private *dev_priv = dev->dev_private;
1131 int ret = 0;
1132
1133 intel_runtime_pm_get(dev_priv);
1134
1135 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1136
1137 if (IS_GEN5(dev)) {
1138 u16 rgvswctl = I915_READ16(MEMSWCTL);
1139 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1140
1141 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1142 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1143 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1144 MEMSTAT_VID_SHIFT);
1145 seq_printf(m, "Current P-state: %d\n",
1146 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1147 } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1148 IS_BROADWELL(dev) || IS_GEN9(dev)) {
1149 u32 rp_state_limits;
1150 u32 gt_perf_status;
1151 u32 rp_state_cap;
1152 u32 rpmodectl, rpinclimit, rpdeclimit;
1153 u32 rpstat, cagf, reqf;
1154 u32 rpupei, rpcurup, rpprevup;
1155 u32 rpdownei, rpcurdown, rpprevdown;
1156 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1157 int max_freq;
1158
1159 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1160 if (IS_BROXTON(dev)) {
1161 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1162 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1163 } else {
1164 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1165 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1166 }
1167
1168 /* RPSTAT1 is in the GT power well */
1169 ret = mutex_lock_interruptible(&dev->struct_mutex);
1170 if (ret)
1171 goto out;
1172
1173 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1174
1175 reqf = I915_READ(GEN6_RPNSWREQ);
1176 if (IS_GEN9(dev))
1177 reqf >>= 23;
1178 else {
1179 reqf &= ~GEN6_TURBO_DISABLE;
1180 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1181 reqf >>= 24;
1182 else
1183 reqf >>= 25;
1184 }
1185 reqf = intel_gpu_freq(dev_priv, reqf);
1186
1187 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1188 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1189 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1190
1191 rpstat = I915_READ(GEN6_RPSTAT1);
1192 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1193 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1194 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1195 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1196 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1197 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1198 if (IS_GEN9(dev))
1199 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1200 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1201 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1202 else
1203 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1204 cagf = intel_gpu_freq(dev_priv, cagf);
1205
1206 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1207 mutex_unlock(&dev->struct_mutex);
1208
1209 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1210 pm_ier = I915_READ(GEN6_PMIER);
1211 pm_imr = I915_READ(GEN6_PMIMR);
1212 pm_isr = I915_READ(GEN6_PMISR);
1213 pm_iir = I915_READ(GEN6_PMIIR);
1214 pm_mask = I915_READ(GEN6_PMINTRMSK);
1215 } else {
1216 pm_ier = I915_READ(GEN8_GT_IER(2));
1217 pm_imr = I915_READ(GEN8_GT_IMR(2));
1218 pm_isr = I915_READ(GEN8_GT_ISR(2));
1219 pm_iir = I915_READ(GEN8_GT_IIR(2));
1220 pm_mask = I915_READ(GEN6_PMINTRMSK);
1221 }
1222 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1223 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1224 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1225 seq_printf(m, "Render p-state ratio: %d\n",
1226 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
1227 seq_printf(m, "Render p-state VID: %d\n",
1228 gt_perf_status & 0xff);
1229 seq_printf(m, "Render p-state limit: %d\n",
1230 rp_state_limits & 0xff);
1231 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1232 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1233 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1234 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1235 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1236 seq_printf(m, "CAGF: %dMHz\n", cagf);
1237 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1238 GEN6_CURICONT_MASK);
1239 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1240 GEN6_CURBSYTAVG_MASK);
1241 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1242 GEN6_CURBSYTAVG_MASK);
1243 seq_printf(m, "Up threshold: %d%%\n",
1244 dev_priv->rps.up_threshold);
1245
1246 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1247 GEN6_CURIAVG_MASK);
1248 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1249 GEN6_CURBSYTAVG_MASK);
1250 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1251 GEN6_CURBSYTAVG_MASK);
1252 seq_printf(m, "Down threshold: %d%%\n",
1253 dev_priv->rps.down_threshold);
1254
1255 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1256 rp_state_cap >> 16) & 0xff;
1257 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
1258 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1259 intel_gpu_freq(dev_priv, max_freq));
1260
1261 max_freq = (rp_state_cap & 0xff00) >> 8;
1262 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
1263 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1264 intel_gpu_freq(dev_priv, max_freq));
1265
1266 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1267 rp_state_cap >> 0) & 0xff;
1268 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
1269 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1270 intel_gpu_freq(dev_priv, max_freq));
1271 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1272 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1273
1274 seq_printf(m, "Current freq: %d MHz\n",
1275 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1276 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1277 seq_printf(m, "Idle freq: %d MHz\n",
1278 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1279 seq_printf(m, "Min freq: %d MHz\n",
1280 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1281 seq_printf(m, "Max freq: %d MHz\n",
1282 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1283 seq_printf(m,
1284 "efficient (RPe) frequency: %d MHz\n",
1285 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1286 } else if (IS_VALLEYVIEW(dev)) {
1287 u32 freq_sts;
1288
1289 mutex_lock(&dev_priv->rps.hw_lock);
1290 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1291 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1292 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1293
1294 seq_printf(m, "actual GPU freq: %d MHz\n",
1295 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1296
1297 seq_printf(m, "current GPU freq: %d MHz\n",
1298 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1299
1300 seq_printf(m, "max GPU freq: %d MHz\n",
1301 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1302
1303 seq_printf(m, "min GPU freq: %d MHz\n",
1304 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1305
1306 seq_printf(m, "idle GPU freq: %d MHz\n",
1307 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1308
1309 seq_printf(m,
1310 "efficient (RPe) frequency: %d MHz\n",
1311 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1312 mutex_unlock(&dev_priv->rps.hw_lock);
1313 } else {
1314 seq_puts(m, "no P-state info available\n");
1315 }
1316
1317 out:
1318 intel_runtime_pm_put(dev_priv);
1319 return ret;
1320 }
1321
1322 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1323 {
1324 struct drm_info_node *node = m->private;
1325 struct drm_device *dev = node->minor->dev;
1326 struct drm_i915_private *dev_priv = dev->dev_private;
1327 struct intel_engine_cs *ring;
1328 u64 acthd[I915_NUM_RINGS];
1329 u32 seqno[I915_NUM_RINGS];
1330 int i;
1331
1332 if (!i915.enable_hangcheck) {
1333 seq_printf(m, "Hangcheck disabled\n");
1334 return 0;
1335 }
1336
1337 intel_runtime_pm_get(dev_priv);
1338
1339 for_each_ring(ring, dev_priv, i) {
1340 seqno[i] = ring->get_seqno(ring, false);
1341 acthd[i] = intel_ring_get_active_head(ring);
1342 }
1343
1344 intel_runtime_pm_put(dev_priv);
1345
1346 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1347 seq_printf(m, "Hangcheck active, fires in %dms\n",
1348 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1349 jiffies));
1350 } else
1351 seq_printf(m, "Hangcheck inactive\n");
1352
1353 for_each_ring(ring, dev_priv, i) {
1354 seq_printf(m, "%s:\n", ring->name);
1355 seq_printf(m, "\tseqno = %x [current %x]\n",
1356 ring->hangcheck.seqno, seqno[i]);
1357 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1358 (long long)ring->hangcheck.acthd,
1359 (long long)acthd[i]);
1360 seq_printf(m, "\tmax ACTHD = 0x%08llx\n",
1361 (long long)ring->hangcheck.max_acthd);
1362 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score);
1363 seq_printf(m, "\taction = %d\n", ring->hangcheck.action);
1364 }
1365
1366 return 0;
1367 }
1368
1369 static int ironlake_drpc_info(struct seq_file *m)
1370 {
1371 struct drm_info_node *node = m->private;
1372 struct drm_device *dev = node->minor->dev;
1373 struct drm_i915_private *dev_priv = dev->dev_private;
1374 u32 rgvmodectl, rstdbyctl;
1375 u16 crstandvid;
1376 int ret;
1377
1378 ret = mutex_lock_interruptible(&dev->struct_mutex);
1379 if (ret)
1380 return ret;
1381 intel_runtime_pm_get(dev_priv);
1382
1383 rgvmodectl = I915_READ(MEMMODECTL);
1384 rstdbyctl = I915_READ(RSTDBYCTL);
1385 crstandvid = I915_READ16(CRSTANDVID);
1386
1387 intel_runtime_pm_put(dev_priv);
1388 mutex_unlock(&dev->struct_mutex);
1389
1390 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1391 "yes" : "no");
1392 seq_printf(m, "Boost freq: %d\n",
1393 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1394 MEMMODE_BOOST_FREQ_SHIFT);
1395 seq_printf(m, "HW control enabled: %s\n",
1396 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1397 seq_printf(m, "SW control enabled: %s\n",
1398 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1399 seq_printf(m, "Gated voltage change: %s\n",
1400 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1401 seq_printf(m, "Starting frequency: P%d\n",
1402 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1403 seq_printf(m, "Max P-state: P%d\n",
1404 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1405 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1406 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1407 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1408 seq_printf(m, "Render standby enabled: %s\n",
1409 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1410 seq_puts(m, "Current RS state: ");
1411 switch (rstdbyctl & RSX_STATUS_MASK) {
1412 case RSX_STATUS_ON:
1413 seq_puts(m, "on\n");
1414 break;
1415 case RSX_STATUS_RC1:
1416 seq_puts(m, "RC1\n");
1417 break;
1418 case RSX_STATUS_RC1E:
1419 seq_puts(m, "RC1E\n");
1420 break;
1421 case RSX_STATUS_RS1:
1422 seq_puts(m, "RS1\n");
1423 break;
1424 case RSX_STATUS_RS2:
1425 seq_puts(m, "RS2 (RC6)\n");
1426 break;
1427 case RSX_STATUS_RS3:
1428 seq_puts(m, "RC3 (RC6+)\n");
1429 break;
1430 default:
1431 seq_puts(m, "unknown\n");
1432 break;
1433 }
1434
1435 return 0;
1436 }
1437
1438 static int i915_forcewake_domains(struct seq_file *m, void *data)
1439 {
1440 struct drm_info_node *node = m->private;
1441 struct drm_device *dev = node->minor->dev;
1442 struct drm_i915_private *dev_priv = dev->dev_private;
1443 struct intel_uncore_forcewake_domain *fw_domain;
1444 int i;
1445
1446 spin_lock_irq(&dev_priv->uncore.lock);
1447 for_each_fw_domain(fw_domain, dev_priv, i) {
1448 seq_printf(m, "%s.wake_count = %u\n",
1449 intel_uncore_forcewake_domain_to_str(i),
1450 fw_domain->wake_count);
1451 }
1452 spin_unlock_irq(&dev_priv->uncore.lock);
1453
1454 return 0;
1455 }
1456
1457 static int vlv_drpc_info(struct seq_file *m)
1458 {
1459 struct drm_info_node *node = m->private;
1460 struct drm_device *dev = node->minor->dev;
1461 struct drm_i915_private *dev_priv = dev->dev_private;
1462 u32 rpmodectl1, rcctl1, pw_status;
1463
1464 intel_runtime_pm_get(dev_priv);
1465
1466 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1467 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1468 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1469
1470 intel_runtime_pm_put(dev_priv);
1471
1472 seq_printf(m, "Video Turbo Mode: %s\n",
1473 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1474 seq_printf(m, "Turbo enabled: %s\n",
1475 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1476 seq_printf(m, "HW control enabled: %s\n",
1477 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1478 seq_printf(m, "SW control enabled: %s\n",
1479 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1480 GEN6_RP_MEDIA_SW_MODE));
1481 seq_printf(m, "RC6 Enabled: %s\n",
1482 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1483 GEN6_RC_CTL_EI_MODE(1))));
1484 seq_printf(m, "Render Power Well: %s\n",
1485 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1486 seq_printf(m, "Media Power Well: %s\n",
1487 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1488
1489 seq_printf(m, "Render RC6 residency since boot: %u\n",
1490 I915_READ(VLV_GT_RENDER_RC6));
1491 seq_printf(m, "Media RC6 residency since boot: %u\n",
1492 I915_READ(VLV_GT_MEDIA_RC6));
1493
1494 return i915_forcewake_domains(m, NULL);
1495 }
1496
1497 static int gen6_drpc_info(struct seq_file *m)
1498 {
1499 struct drm_info_node *node = m->private;
1500 struct drm_device *dev = node->minor->dev;
1501 struct drm_i915_private *dev_priv = dev->dev_private;
1502 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1503 unsigned forcewake_count;
1504 int count = 0, ret;
1505
1506 ret = mutex_lock_interruptible(&dev->struct_mutex);
1507 if (ret)
1508 return ret;
1509 intel_runtime_pm_get(dev_priv);
1510
1511 spin_lock_irq(&dev_priv->uncore.lock);
1512 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1513 spin_unlock_irq(&dev_priv->uncore.lock);
1514
1515 if (forcewake_count) {
1516 seq_puts(m, "RC information inaccurate because somebody "
1517 "holds a forcewake reference \n");
1518 } else {
1519 /* NB: we cannot use forcewake, else we read the wrong values */
1520 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1521 udelay(10);
1522 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1523 }
1524
1525 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1526 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1527
1528 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1529 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1530 mutex_unlock(&dev->struct_mutex);
1531 mutex_lock(&dev_priv->rps.hw_lock);
1532 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1533 mutex_unlock(&dev_priv->rps.hw_lock);
1534
1535 intel_runtime_pm_put(dev_priv);
1536
1537 seq_printf(m, "Video Turbo Mode: %s\n",
1538 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1539 seq_printf(m, "HW control enabled: %s\n",
1540 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1541 seq_printf(m, "SW control enabled: %s\n",
1542 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1543 GEN6_RP_MEDIA_SW_MODE));
1544 seq_printf(m, "RC1e Enabled: %s\n",
1545 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1546 seq_printf(m, "RC6 Enabled: %s\n",
1547 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1548 seq_printf(m, "Deep RC6 Enabled: %s\n",
1549 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1550 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1551 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1552 seq_puts(m, "Current RC state: ");
1553 switch (gt_core_status & GEN6_RCn_MASK) {
1554 case GEN6_RC0:
1555 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1556 seq_puts(m, "Core Power Down\n");
1557 else
1558 seq_puts(m, "on\n");
1559 break;
1560 case GEN6_RC3:
1561 seq_puts(m, "RC3\n");
1562 break;
1563 case GEN6_RC6:
1564 seq_puts(m, "RC6\n");
1565 break;
1566 case GEN6_RC7:
1567 seq_puts(m, "RC7\n");
1568 break;
1569 default:
1570 seq_puts(m, "Unknown\n");
1571 break;
1572 }
1573
1574 seq_printf(m, "Core Power Down: %s\n",
1575 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1576
1577 /* Not exactly sure what this is */
1578 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1579 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1580 seq_printf(m, "RC6 residency since boot: %u\n",
1581 I915_READ(GEN6_GT_GFX_RC6));
1582 seq_printf(m, "RC6+ residency since boot: %u\n",
1583 I915_READ(GEN6_GT_GFX_RC6p));
1584 seq_printf(m, "RC6++ residency since boot: %u\n",
1585 I915_READ(GEN6_GT_GFX_RC6pp));
1586
1587 seq_printf(m, "RC6 voltage: %dmV\n",
1588 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1589 seq_printf(m, "RC6+ voltage: %dmV\n",
1590 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1591 seq_printf(m, "RC6++ voltage: %dmV\n",
1592 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1593 return 0;
1594 }
1595
1596 static int i915_drpc_info(struct seq_file *m, void *unused)
1597 {
1598 struct drm_info_node *node = m->private;
1599 struct drm_device *dev = node->minor->dev;
1600
1601 if (IS_VALLEYVIEW(dev))
1602 return vlv_drpc_info(m);
1603 else if (INTEL_INFO(dev)->gen >= 6)
1604 return gen6_drpc_info(m);
1605 else
1606 return ironlake_drpc_info(m);
1607 }
1608
1609 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1610 {
1611 struct drm_info_node *node = m->private;
1612 struct drm_device *dev = node->minor->dev;
1613 struct drm_i915_private *dev_priv = dev->dev_private;
1614
1615 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1616 dev_priv->fb_tracking.busy_bits);
1617
1618 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1619 dev_priv->fb_tracking.flip_bits);
1620
1621 return 0;
1622 }
1623
1624 static int i915_fbc_status(struct seq_file *m, void *unused)
1625 {
1626 struct drm_info_node *node = m->private;
1627 struct drm_device *dev = node->minor->dev;
1628 struct drm_i915_private *dev_priv = dev->dev_private;
1629
1630 if (!HAS_FBC(dev)) {
1631 seq_puts(m, "FBC unsupported on this chipset\n");
1632 return 0;
1633 }
1634
1635 intel_runtime_pm_get(dev_priv);
1636 mutex_lock(&dev_priv->fbc.lock);
1637
1638 if (intel_fbc_enabled(dev_priv))
1639 seq_puts(m, "FBC enabled\n");
1640 else
1641 seq_printf(m, "FBC disabled: %s\n",
1642 intel_no_fbc_reason_str(dev_priv->fbc.no_fbc_reason));
1643
1644 if (INTEL_INFO(dev_priv)->gen >= 7)
1645 seq_printf(m, "Compressing: %s\n",
1646 yesno(I915_READ(FBC_STATUS2) &
1647 FBC_COMPRESSION_MASK));
1648
1649 mutex_unlock(&dev_priv->fbc.lock);
1650 intel_runtime_pm_put(dev_priv);
1651
1652 return 0;
1653 }
1654
1655 static int i915_fbc_fc_get(void *data, u64 *val)
1656 {
1657 struct drm_device *dev = data;
1658 struct drm_i915_private *dev_priv = dev->dev_private;
1659
1660 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1661 return -ENODEV;
1662
1663 *val = dev_priv->fbc.false_color;
1664
1665 return 0;
1666 }
1667
1668 static int i915_fbc_fc_set(void *data, u64 val)
1669 {
1670 struct drm_device *dev = data;
1671 struct drm_i915_private *dev_priv = dev->dev_private;
1672 u32 reg;
1673
1674 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1675 return -ENODEV;
1676
1677 mutex_lock(&dev_priv->fbc.lock);
1678
1679 reg = I915_READ(ILK_DPFC_CONTROL);
1680 dev_priv->fbc.false_color = val;
1681
1682 I915_WRITE(ILK_DPFC_CONTROL, val ?
1683 (reg | FBC_CTL_FALSE_COLOR) :
1684 (reg & ~FBC_CTL_FALSE_COLOR));
1685
1686 mutex_unlock(&dev_priv->fbc.lock);
1687 return 0;
1688 }
1689
1690 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1691 i915_fbc_fc_get, i915_fbc_fc_set,
1692 "%llu\n");
1693
1694 static int i915_ips_status(struct seq_file *m, void *unused)
1695 {
1696 struct drm_info_node *node = m->private;
1697 struct drm_device *dev = node->minor->dev;
1698 struct drm_i915_private *dev_priv = dev->dev_private;
1699
1700 if (!HAS_IPS(dev)) {
1701 seq_puts(m, "not supported\n");
1702 return 0;
1703 }
1704
1705 intel_runtime_pm_get(dev_priv);
1706
1707 seq_printf(m, "Enabled by kernel parameter: %s\n",
1708 yesno(i915.enable_ips));
1709
1710 if (INTEL_INFO(dev)->gen >= 8) {
1711 seq_puts(m, "Currently: unknown\n");
1712 } else {
1713 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1714 seq_puts(m, "Currently: enabled\n");
1715 else
1716 seq_puts(m, "Currently: disabled\n");
1717 }
1718
1719 intel_runtime_pm_put(dev_priv);
1720
1721 return 0;
1722 }
1723
1724 static int i915_sr_status(struct seq_file *m, void *unused)
1725 {
1726 struct drm_info_node *node = m->private;
1727 struct drm_device *dev = node->minor->dev;
1728 struct drm_i915_private *dev_priv = dev->dev_private;
1729 bool sr_enabled = false;
1730
1731 intel_runtime_pm_get(dev_priv);
1732
1733 if (HAS_PCH_SPLIT(dev))
1734 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1735 else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1736 IS_I945G(dev) || IS_I945GM(dev))
1737 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1738 else if (IS_I915GM(dev))
1739 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1740 else if (IS_PINEVIEW(dev))
1741 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1742 else if (IS_VALLEYVIEW(dev))
1743 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1744
1745 intel_runtime_pm_put(dev_priv);
1746
1747 seq_printf(m, "self-refresh: %s\n",
1748 sr_enabled ? "enabled" : "disabled");
1749
1750 return 0;
1751 }
1752
1753 static int i915_emon_status(struct seq_file *m, void *unused)
1754 {
1755 struct drm_info_node *node = m->private;
1756 struct drm_device *dev = node->minor->dev;
1757 struct drm_i915_private *dev_priv = dev->dev_private;
1758 unsigned long temp, chipset, gfx;
1759 int ret;
1760
1761 if (!IS_GEN5(dev))
1762 return -ENODEV;
1763
1764 ret = mutex_lock_interruptible(&dev->struct_mutex);
1765 if (ret)
1766 return ret;
1767
1768 temp = i915_mch_val(dev_priv);
1769 chipset = i915_chipset_val(dev_priv);
1770 gfx = i915_gfx_val(dev_priv);
1771 mutex_unlock(&dev->struct_mutex);
1772
1773 seq_printf(m, "GMCH temp: %ld\n", temp);
1774 seq_printf(m, "Chipset power: %ld\n", chipset);
1775 seq_printf(m, "GFX power: %ld\n", gfx);
1776 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1777
1778 return 0;
1779 }
1780
1781 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1782 {
1783 struct drm_info_node *node = m->private;
1784 struct drm_device *dev = node->minor->dev;
1785 struct drm_i915_private *dev_priv = dev->dev_private;
1786 int ret = 0;
1787 int gpu_freq, ia_freq;
1788 unsigned int max_gpu_freq, min_gpu_freq;
1789
1790 if (!HAS_CORE_RING_FREQ(dev)) {
1791 seq_puts(m, "unsupported on this chipset\n");
1792 return 0;
1793 }
1794
1795 intel_runtime_pm_get(dev_priv);
1796
1797 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1798
1799 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1800 if (ret)
1801 goto out;
1802
1803 if (IS_SKYLAKE(dev)) {
1804 /* Convert GT frequency to 50 HZ units */
1805 min_gpu_freq =
1806 dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1807 max_gpu_freq =
1808 dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1809 } else {
1810 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1811 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1812 }
1813
1814 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1815
1816 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1817 ia_freq = gpu_freq;
1818 sandybridge_pcode_read(dev_priv,
1819 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1820 &ia_freq);
1821 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1822 intel_gpu_freq(dev_priv, (gpu_freq *
1823 (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1))),
1824 ((ia_freq >> 0) & 0xff) * 100,
1825 ((ia_freq >> 8) & 0xff) * 100);
1826 }
1827
1828 mutex_unlock(&dev_priv->rps.hw_lock);
1829
1830 out:
1831 intel_runtime_pm_put(dev_priv);
1832 return ret;
1833 }
1834
1835 static int i915_opregion(struct seq_file *m, void *unused)
1836 {
1837 struct drm_info_node *node = m->private;
1838 struct drm_device *dev = node->minor->dev;
1839 struct drm_i915_private *dev_priv = dev->dev_private;
1840 struct intel_opregion *opregion = &dev_priv->opregion;
1841 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1842 int ret;
1843
1844 if (data == NULL)
1845 return -ENOMEM;
1846
1847 ret = mutex_lock_interruptible(&dev->struct_mutex);
1848 if (ret)
1849 goto out;
1850
1851 if (opregion->header) {
1852 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1853 seq_write(m, data, OPREGION_SIZE);
1854 }
1855
1856 mutex_unlock(&dev->struct_mutex);
1857
1858 out:
1859 kfree(data);
1860 return 0;
1861 }
1862
1863 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1864 {
1865 struct drm_info_node *node = m->private;
1866 struct drm_device *dev = node->minor->dev;
1867 struct intel_fbdev *ifbdev = NULL;
1868 struct intel_framebuffer *fb;
1869 struct drm_framebuffer *drm_fb;
1870
1871 #ifdef CONFIG_DRM_I915_FBDEV
1872 struct drm_i915_private *dev_priv = dev->dev_private;
1873
1874 ifbdev = dev_priv->fbdev;
1875 fb = to_intel_framebuffer(ifbdev->helper.fb);
1876
1877 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1878 fb->base.width,
1879 fb->base.height,
1880 fb->base.depth,
1881 fb->base.bits_per_pixel,
1882 fb->base.modifier[0],
1883 atomic_read(&fb->base.refcount.refcount));
1884 describe_obj(m, fb->obj);
1885 seq_putc(m, '\n');
1886 #endif
1887
1888 mutex_lock(&dev->mode_config.fb_lock);
1889 drm_for_each_fb(drm_fb, dev) {
1890 fb = to_intel_framebuffer(drm_fb);
1891 if (ifbdev && &fb->base == ifbdev->helper.fb)
1892 continue;
1893
1894 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1895 fb->base.width,
1896 fb->base.height,
1897 fb->base.depth,
1898 fb->base.bits_per_pixel,
1899 fb->base.modifier[0],
1900 atomic_read(&fb->base.refcount.refcount));
1901 describe_obj(m, fb->obj);
1902 seq_putc(m, '\n');
1903 }
1904 mutex_unlock(&dev->mode_config.fb_lock);
1905
1906 return 0;
1907 }
1908
1909 static void describe_ctx_ringbuf(struct seq_file *m,
1910 struct intel_ringbuffer *ringbuf)
1911 {
1912 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1913 ringbuf->space, ringbuf->head, ringbuf->tail,
1914 ringbuf->last_retired_head);
1915 }
1916
1917 static int i915_context_status(struct seq_file *m, void *unused)
1918 {
1919 struct drm_info_node *node = m->private;
1920 struct drm_device *dev = node->minor->dev;
1921 struct drm_i915_private *dev_priv = dev->dev_private;
1922 struct intel_engine_cs *ring;
1923 struct intel_context *ctx;
1924 int ret, i;
1925
1926 ret = mutex_lock_interruptible(&dev->struct_mutex);
1927 if (ret)
1928 return ret;
1929
1930 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1931 if (!i915.enable_execlists &&
1932 ctx->legacy_hw_ctx.rcs_state == NULL)
1933 continue;
1934
1935 seq_puts(m, "HW context ");
1936 describe_ctx(m, ctx);
1937 for_each_ring(ring, dev_priv, i) {
1938 if (ring->default_context == ctx)
1939 seq_printf(m, "(default context %s) ",
1940 ring->name);
1941 }
1942
1943 if (i915.enable_execlists) {
1944 seq_putc(m, '\n');
1945 for_each_ring(ring, dev_priv, i) {
1946 struct drm_i915_gem_object *ctx_obj =
1947 ctx->engine[i].state;
1948 struct intel_ringbuffer *ringbuf =
1949 ctx->engine[i].ringbuf;
1950
1951 seq_printf(m, "%s: ", ring->name);
1952 if (ctx_obj)
1953 describe_obj(m, ctx_obj);
1954 if (ringbuf)
1955 describe_ctx_ringbuf(m, ringbuf);
1956 seq_putc(m, '\n');
1957 }
1958 } else {
1959 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1960 }
1961
1962 seq_putc(m, '\n');
1963 }
1964
1965 mutex_unlock(&dev->struct_mutex);
1966
1967 return 0;
1968 }
1969
1970 static void i915_dump_lrc_obj(struct seq_file *m,
1971 struct intel_engine_cs *ring,
1972 struct drm_i915_gem_object *ctx_obj)
1973 {
1974 struct page *page;
1975 uint32_t *reg_state;
1976 int j;
1977 unsigned long ggtt_offset = 0;
1978
1979 if (ctx_obj == NULL) {
1980 seq_printf(m, "Context on %s with no gem object\n",
1981 ring->name);
1982 return;
1983 }
1984
1985 seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1986 intel_execlists_ctx_id(ctx_obj));
1987
1988 if (!i915_gem_obj_ggtt_bound(ctx_obj))
1989 seq_puts(m, "\tNot bound in GGTT\n");
1990 else
1991 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1992
1993 if (i915_gem_object_get_pages(ctx_obj)) {
1994 seq_puts(m, "\tFailed to get pages for context object\n");
1995 return;
1996 }
1997
1998 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
1999 if (!WARN_ON(page == NULL)) {
2000 reg_state = kmap_atomic(page);
2001
2002 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2003 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2004 ggtt_offset + 4096 + (j * 4),
2005 reg_state[j], reg_state[j + 1],
2006 reg_state[j + 2], reg_state[j + 3]);
2007 }
2008 kunmap_atomic(reg_state);
2009 }
2010
2011 seq_putc(m, '\n');
2012 }
2013
2014 static int i915_dump_lrc(struct seq_file *m, void *unused)
2015 {
2016 struct drm_info_node *node = (struct drm_info_node *) m->private;
2017 struct drm_device *dev = node->minor->dev;
2018 struct drm_i915_private *dev_priv = dev->dev_private;
2019 struct intel_engine_cs *ring;
2020 struct intel_context *ctx;
2021 int ret, i;
2022
2023 if (!i915.enable_execlists) {
2024 seq_printf(m, "Logical Ring Contexts are disabled\n");
2025 return 0;
2026 }
2027
2028 ret = mutex_lock_interruptible(&dev->struct_mutex);
2029 if (ret)
2030 return ret;
2031
2032 list_for_each_entry(ctx, &dev_priv->context_list, link) {
2033 for_each_ring(ring, dev_priv, i) {
2034 if (ring->default_context != ctx)
2035 i915_dump_lrc_obj(m, ring,
2036 ctx->engine[i].state);
2037 }
2038 }
2039
2040 mutex_unlock(&dev->struct_mutex);
2041
2042 return 0;
2043 }
2044
2045 static int i915_execlists(struct seq_file *m, void *data)
2046 {
2047 struct drm_info_node *node = (struct drm_info_node *)m->private;
2048 struct drm_device *dev = node->minor->dev;
2049 struct drm_i915_private *dev_priv = dev->dev_private;
2050 struct intel_engine_cs *ring;
2051 u32 status_pointer;
2052 u8 read_pointer;
2053 u8 write_pointer;
2054 u32 status;
2055 u32 ctx_id;
2056 struct list_head *cursor;
2057 int ring_id, i;
2058 int ret;
2059
2060 if (!i915.enable_execlists) {
2061 seq_puts(m, "Logical Ring Contexts are disabled\n");
2062 return 0;
2063 }
2064
2065 ret = mutex_lock_interruptible(&dev->struct_mutex);
2066 if (ret)
2067 return ret;
2068
2069 intel_runtime_pm_get(dev_priv);
2070
2071 for_each_ring(ring, dev_priv, ring_id) {
2072 struct drm_i915_gem_request *head_req = NULL;
2073 int count = 0;
2074 unsigned long flags;
2075
2076 seq_printf(m, "%s\n", ring->name);
2077
2078 status = I915_READ(RING_EXECLIST_STATUS(ring));
2079 ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
2080 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2081 status, ctx_id);
2082
2083 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
2084 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2085
2086 read_pointer = ring->next_context_status_buffer;
2087 write_pointer = status_pointer & 0x07;
2088 if (read_pointer > write_pointer)
2089 write_pointer += 6;
2090 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2091 read_pointer, write_pointer);
2092
2093 for (i = 0; i < 6; i++) {
2094 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
2095 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4);
2096
2097 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2098 i, status, ctx_id);
2099 }
2100
2101 spin_lock_irqsave(&ring->execlist_lock, flags);
2102 list_for_each(cursor, &ring->execlist_queue)
2103 count++;
2104 head_req = list_first_entry_or_null(&ring->execlist_queue,
2105 struct drm_i915_gem_request, execlist_link);
2106 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2107
2108 seq_printf(m, "\t%d requests in queue\n", count);
2109 if (head_req) {
2110 struct drm_i915_gem_object *ctx_obj;
2111
2112 ctx_obj = head_req->ctx->engine[ring_id].state;
2113 seq_printf(m, "\tHead request id: %u\n",
2114 intel_execlists_ctx_id(ctx_obj));
2115 seq_printf(m, "\tHead request tail: %u\n",
2116 head_req->tail);
2117 }
2118
2119 seq_putc(m, '\n');
2120 }
2121
2122 intel_runtime_pm_put(dev_priv);
2123 mutex_unlock(&dev->struct_mutex);
2124
2125 return 0;
2126 }
2127
2128 static const char *swizzle_string(unsigned swizzle)
2129 {
2130 switch (swizzle) {
2131 case I915_BIT_6_SWIZZLE_NONE:
2132 return "none";
2133 case I915_BIT_6_SWIZZLE_9:
2134 return "bit9";
2135 case I915_BIT_6_SWIZZLE_9_10:
2136 return "bit9/bit10";
2137 case I915_BIT_6_SWIZZLE_9_11:
2138 return "bit9/bit11";
2139 case I915_BIT_6_SWIZZLE_9_10_11:
2140 return "bit9/bit10/bit11";
2141 case I915_BIT_6_SWIZZLE_9_17:
2142 return "bit9/bit17";
2143 case I915_BIT_6_SWIZZLE_9_10_17:
2144 return "bit9/bit10/bit17";
2145 case I915_BIT_6_SWIZZLE_UNKNOWN:
2146 return "unknown";
2147 }
2148
2149 return "bug";
2150 }
2151
2152 static int i915_swizzle_info(struct seq_file *m, void *data)
2153 {
2154 struct drm_info_node *node = m->private;
2155 struct drm_device *dev = node->minor->dev;
2156 struct drm_i915_private *dev_priv = dev->dev_private;
2157 int ret;
2158
2159 ret = mutex_lock_interruptible(&dev->struct_mutex);
2160 if (ret)
2161 return ret;
2162 intel_runtime_pm_get(dev_priv);
2163
2164 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2165 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2166 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2167 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2168
2169 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2170 seq_printf(m, "DDC = 0x%08x\n",
2171 I915_READ(DCC));
2172 seq_printf(m, "DDC2 = 0x%08x\n",
2173 I915_READ(DCC2));
2174 seq_printf(m, "C0DRB3 = 0x%04x\n",
2175 I915_READ16(C0DRB3));
2176 seq_printf(m, "C1DRB3 = 0x%04x\n",
2177 I915_READ16(C1DRB3));
2178 } else if (INTEL_INFO(dev)->gen >= 6) {
2179 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2180 I915_READ(MAD_DIMM_C0));
2181 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2182 I915_READ(MAD_DIMM_C1));
2183 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2184 I915_READ(MAD_DIMM_C2));
2185 seq_printf(m, "TILECTL = 0x%08x\n",
2186 I915_READ(TILECTL));
2187 if (INTEL_INFO(dev)->gen >= 8)
2188 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2189 I915_READ(GAMTARBMODE));
2190 else
2191 seq_printf(m, "ARB_MODE = 0x%08x\n",
2192 I915_READ(ARB_MODE));
2193 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2194 I915_READ(DISP_ARB_CTL));
2195 }
2196
2197 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2198 seq_puts(m, "L-shaped memory detected\n");
2199
2200 intel_runtime_pm_put(dev_priv);
2201 mutex_unlock(&dev->struct_mutex);
2202
2203 return 0;
2204 }
2205
2206 static int per_file_ctx(int id, void *ptr, void *data)
2207 {
2208 struct intel_context *ctx = ptr;
2209 struct seq_file *m = data;
2210 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2211
2212 if (!ppgtt) {
2213 seq_printf(m, " no ppgtt for context %d\n",
2214 ctx->user_handle);
2215 return 0;
2216 }
2217
2218 if (i915_gem_context_is_default(ctx))
2219 seq_puts(m, " default context:\n");
2220 else
2221 seq_printf(m, " context %d:\n", ctx->user_handle);
2222 ppgtt->debug_dump(ppgtt, m);
2223
2224 return 0;
2225 }
2226
2227 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2228 {
2229 struct drm_i915_private *dev_priv = dev->dev_private;
2230 struct intel_engine_cs *ring;
2231 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2232 int unused, i;
2233
2234 if (!ppgtt)
2235 return;
2236
2237 for_each_ring(ring, dev_priv, unused) {
2238 seq_printf(m, "%s\n", ring->name);
2239 for (i = 0; i < 4; i++) {
2240 u32 offset = 0x270 + i * 8;
2241 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
2242 pdp <<= 32;
2243 pdp |= I915_READ(ring->mmio_base + offset);
2244 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2245 }
2246 }
2247 }
2248
2249 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2250 {
2251 struct drm_i915_private *dev_priv = dev->dev_private;
2252 struct intel_engine_cs *ring;
2253 int i;
2254
2255 if (INTEL_INFO(dev)->gen == 6)
2256 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2257
2258 for_each_ring(ring, dev_priv, i) {
2259 seq_printf(m, "%s\n", ring->name);
2260 if (INTEL_INFO(dev)->gen == 7)
2261 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2262 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2263 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2264 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2265 }
2266 if (dev_priv->mm.aliasing_ppgtt) {
2267 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2268
2269 seq_puts(m, "aliasing PPGTT:\n");
2270 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2271
2272 ppgtt->debug_dump(ppgtt, m);
2273 }
2274
2275 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2276 }
2277
2278 static int i915_ppgtt_info(struct seq_file *m, void *data)
2279 {
2280 struct drm_info_node *node = m->private;
2281 struct drm_device *dev = node->minor->dev;
2282 struct drm_i915_private *dev_priv = dev->dev_private;
2283 struct drm_file *file;
2284
2285 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2286 if (ret)
2287 return ret;
2288 intel_runtime_pm_get(dev_priv);
2289
2290 if (INTEL_INFO(dev)->gen >= 8)
2291 gen8_ppgtt_info(m, dev);
2292 else if (INTEL_INFO(dev)->gen >= 6)
2293 gen6_ppgtt_info(m, dev);
2294
2295 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2296 struct drm_i915_file_private *file_priv = file->driver_priv;
2297
2298 seq_printf(m, "\nproc: %s\n",
2299 get_pid_task(file->pid, PIDTYPE_PID)->comm);
2300 idr_for_each(&file_priv->context_idr, per_file_ctx,
2301 (void *)(unsigned long)m);
2302 }
2303
2304 intel_runtime_pm_put(dev_priv);
2305 mutex_unlock(&dev->struct_mutex);
2306
2307 return 0;
2308 }
2309
2310 static int count_irq_waiters(struct drm_i915_private *i915)
2311 {
2312 struct intel_engine_cs *ring;
2313 int count = 0;
2314 int i;
2315
2316 for_each_ring(ring, i915, i)
2317 count += ring->irq_refcount;
2318
2319 return count;
2320 }
2321
2322 static int i915_rps_boost_info(struct seq_file *m, void *data)
2323 {
2324 struct drm_info_node *node = m->private;
2325 struct drm_device *dev = node->minor->dev;
2326 struct drm_i915_private *dev_priv = dev->dev_private;
2327 struct drm_file *file;
2328
2329 seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2330 seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
2331 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2332 seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2333 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2334 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2335 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2336 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2337 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2338 spin_lock(&dev_priv->rps.client_lock);
2339 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2340 struct drm_i915_file_private *file_priv = file->driver_priv;
2341 struct task_struct *task;
2342
2343 rcu_read_lock();
2344 task = pid_task(file->pid, PIDTYPE_PID);
2345 seq_printf(m, "%s [%d]: %d boosts%s\n",
2346 task ? task->comm : "<unknown>",
2347 task ? task->pid : -1,
2348 file_priv->rps.boosts,
2349 list_empty(&file_priv->rps.link) ? "" : ", active");
2350 rcu_read_unlock();
2351 }
2352 seq_printf(m, "Semaphore boosts: %d%s\n",
2353 dev_priv->rps.semaphores.boosts,
2354 list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");
2355 seq_printf(m, "MMIO flip boosts: %d%s\n",
2356 dev_priv->rps.mmioflips.boosts,
2357 list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
2358 seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
2359 spin_unlock(&dev_priv->rps.client_lock);
2360
2361 return 0;
2362 }
2363
2364 static int i915_llc(struct seq_file *m, void *data)
2365 {
2366 struct drm_info_node *node = m->private;
2367 struct drm_device *dev = node->minor->dev;
2368 struct drm_i915_private *dev_priv = dev->dev_private;
2369
2370 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2371 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2372 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2373
2374 return 0;
2375 }
2376
2377 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2378 {
2379 struct drm_info_node *node = m->private;
2380 struct drm_i915_private *dev_priv = node->minor->dev->dev_private;
2381 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2382 u32 tmp, i;
2383
2384 if (!HAS_GUC_UCODE(dev_priv->dev))
2385 return 0;
2386
2387 seq_printf(m, "GuC firmware status:\n");
2388 seq_printf(m, "\tpath: %s\n",
2389 guc_fw->guc_fw_path);
2390 seq_printf(m, "\tfetch: %s\n",
2391 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2392 seq_printf(m, "\tload: %s\n",
2393 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2394 seq_printf(m, "\tversion wanted: %d.%d\n",
2395 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2396 seq_printf(m, "\tversion found: %d.%d\n",
2397 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2398
2399 tmp = I915_READ(GUC_STATUS);
2400
2401 seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2402 seq_printf(m, "\tBootrom status = 0x%x\n",
2403 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2404 seq_printf(m, "\tuKernel status = 0x%x\n",
2405 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2406 seq_printf(m, "\tMIA Core status = 0x%x\n",
2407 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2408 seq_puts(m, "\nScratch registers:\n");
2409 for (i = 0; i < 16; i++)
2410 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2411
2412 return 0;
2413 }
2414
2415 static int i915_guc_log_dump(struct seq_file *m, void *data)
2416 {
2417 struct drm_info_node *node = m->private;
2418 struct drm_device *dev = node->minor->dev;
2419 struct drm_i915_private *dev_priv = dev->dev_private;
2420 struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;
2421 u32 *log;
2422 int i = 0, pg;
2423
2424 if (!log_obj)
2425 return 0;
2426
2427 for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) {
2428 log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));
2429
2430 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2431 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2432 *(log + i), *(log + i + 1),
2433 *(log + i + 2), *(log + i + 3));
2434
2435 kunmap_atomic(log);
2436 }
2437
2438 seq_putc(m, '\n');
2439
2440 return 0;
2441 }
2442
2443 static int i915_edp_psr_status(struct seq_file *m, void *data)
2444 {
2445 struct drm_info_node *node = m->private;
2446 struct drm_device *dev = node->minor->dev;
2447 struct drm_i915_private *dev_priv = dev->dev_private;
2448 u32 psrperf = 0;
2449 u32 stat[3];
2450 enum pipe pipe;
2451 bool enabled = false;
2452
2453 if (!HAS_PSR(dev)) {
2454 seq_puts(m, "PSR not supported\n");
2455 return 0;
2456 }
2457
2458 intel_runtime_pm_get(dev_priv);
2459
2460 mutex_lock(&dev_priv->psr.lock);
2461 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2462 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2463 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2464 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2465 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2466 dev_priv->psr.busy_frontbuffer_bits);
2467 seq_printf(m, "Re-enable work scheduled: %s\n",
2468 yesno(work_busy(&dev_priv->psr.work.work)));
2469
2470 if (HAS_DDI(dev))
2471 enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2472 else {
2473 for_each_pipe(dev_priv, pipe) {
2474 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2475 VLV_EDP_PSR_CURR_STATE_MASK;
2476 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2477 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2478 enabled = true;
2479 }
2480 }
2481 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2482
2483 if (!HAS_DDI(dev))
2484 for_each_pipe(dev_priv, pipe) {
2485 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2486 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2487 seq_printf(m, " pipe %c", pipe_name(pipe));
2488 }
2489 seq_puts(m, "\n");
2490
2491 /* CHV PSR has no kind of performance counter */
2492 if (HAS_DDI(dev)) {
2493 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2494 EDP_PSR_PERF_CNT_MASK;
2495
2496 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2497 }
2498 mutex_unlock(&dev_priv->psr.lock);
2499
2500 intel_runtime_pm_put(dev_priv);
2501 return 0;
2502 }
2503
2504 static int i915_sink_crc(struct seq_file *m, void *data)
2505 {
2506 struct drm_info_node *node = m->private;
2507 struct drm_device *dev = node->minor->dev;
2508 struct intel_encoder *encoder;
2509 struct intel_connector *connector;
2510 struct intel_dp *intel_dp = NULL;
2511 int ret;
2512 u8 crc[6];
2513
2514 drm_modeset_lock_all(dev);
2515 for_each_intel_connector(dev, connector) {
2516
2517 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2518 continue;
2519
2520 if (!connector->base.encoder)
2521 continue;
2522
2523 encoder = to_intel_encoder(connector->base.encoder);
2524 if (encoder->type != INTEL_OUTPUT_EDP)
2525 continue;
2526
2527 intel_dp = enc_to_intel_dp(&encoder->base);
2528
2529 ret = intel_dp_sink_crc(intel_dp, crc);
2530 if (ret)
2531 goto out;
2532
2533 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2534 crc[0], crc[1], crc[2],
2535 crc[3], crc[4], crc[5]);
2536 goto out;
2537 }
2538 ret = -ENODEV;
2539 out:
2540 drm_modeset_unlock_all(dev);
2541 return ret;
2542 }
2543
2544 static int i915_energy_uJ(struct seq_file *m, void *data)
2545 {
2546 struct drm_info_node *node = m->private;
2547 struct drm_device *dev = node->minor->dev;
2548 struct drm_i915_private *dev_priv = dev->dev_private;
2549 u64 power;
2550 u32 units;
2551
2552 if (INTEL_INFO(dev)->gen < 6)
2553 return -ENODEV;
2554
2555 intel_runtime_pm_get(dev_priv);
2556
2557 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2558 power = (power & 0x1f00) >> 8;
2559 units = 1000000 / (1 << power); /* convert to uJ */
2560 power = I915_READ(MCH_SECP_NRG_STTS);
2561 power *= units;
2562
2563 intel_runtime_pm_put(dev_priv);
2564
2565 seq_printf(m, "%llu", (long long unsigned)power);
2566
2567 return 0;
2568 }
2569
2570 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2571 {
2572 struct drm_info_node *node = m->private;
2573 struct drm_device *dev = node->minor->dev;
2574 struct drm_i915_private *dev_priv = dev->dev_private;
2575
2576 if (!HAS_RUNTIME_PM(dev)) {
2577 seq_puts(m, "not supported\n");
2578 return 0;
2579 }
2580
2581 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2582 seq_printf(m, "IRQs disabled: %s\n",
2583 yesno(!intel_irqs_enabled(dev_priv)));
2584 #ifdef CONFIG_PM
2585 seq_printf(m, "Usage count: %d\n",
2586 atomic_read(&dev->dev->power.usage_count));
2587 #else
2588 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2589 #endif
2590
2591 return 0;
2592 }
2593
2594 static const char *power_domain_str(enum intel_display_power_domain domain)
2595 {
2596 switch (domain) {
2597 case POWER_DOMAIN_PIPE_A:
2598 return "PIPE_A";
2599 case POWER_DOMAIN_PIPE_B:
2600 return "PIPE_B";
2601 case POWER_DOMAIN_PIPE_C:
2602 return "PIPE_C";
2603 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2604 return "PIPE_A_PANEL_FITTER";
2605 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2606 return "PIPE_B_PANEL_FITTER";
2607 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2608 return "PIPE_C_PANEL_FITTER";
2609 case POWER_DOMAIN_TRANSCODER_A:
2610 return "TRANSCODER_A";
2611 case POWER_DOMAIN_TRANSCODER_B:
2612 return "TRANSCODER_B";
2613 case POWER_DOMAIN_TRANSCODER_C:
2614 return "TRANSCODER_C";
2615 case POWER_DOMAIN_TRANSCODER_EDP:
2616 return "TRANSCODER_EDP";
2617 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2618 return "PORT_DDI_A_2_LANES";
2619 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2620 return "PORT_DDI_A_4_LANES";
2621 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2622 return "PORT_DDI_B_2_LANES";
2623 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2624 return "PORT_DDI_B_4_LANES";
2625 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2626 return "PORT_DDI_C_2_LANES";
2627 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2628 return "PORT_DDI_C_4_LANES";
2629 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2630 return "PORT_DDI_D_2_LANES";
2631 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2632 return "PORT_DDI_D_4_LANES";
2633 case POWER_DOMAIN_PORT_DSI:
2634 return "PORT_DSI";
2635 case POWER_DOMAIN_PORT_CRT:
2636 return "PORT_CRT";
2637 case POWER_DOMAIN_PORT_OTHER:
2638 return "PORT_OTHER";
2639 case POWER_DOMAIN_VGA:
2640 return "VGA";
2641 case POWER_DOMAIN_AUDIO:
2642 return "AUDIO";
2643 case POWER_DOMAIN_PLLS:
2644 return "PLLS";
2645 case POWER_DOMAIN_AUX_A:
2646 return "AUX_A";
2647 case POWER_DOMAIN_AUX_B:
2648 return "AUX_B";
2649 case POWER_DOMAIN_AUX_C:
2650 return "AUX_C";
2651 case POWER_DOMAIN_AUX_D:
2652 return "AUX_D";
2653 case POWER_DOMAIN_INIT:
2654 return "INIT";
2655 default:
2656 MISSING_CASE(domain);
2657 return "?";
2658 }
2659 }
2660
2661 static int i915_power_domain_info(struct seq_file *m, void *unused)
2662 {
2663 struct drm_info_node *node = m->private;
2664 struct drm_device *dev = node->minor->dev;
2665 struct drm_i915_private *dev_priv = dev->dev_private;
2666 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2667 int i;
2668
2669 mutex_lock(&power_domains->lock);
2670
2671 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2672 for (i = 0; i < power_domains->power_well_count; i++) {
2673 struct i915_power_well *power_well;
2674 enum intel_display_power_domain power_domain;
2675
2676 power_well = &power_domains->power_wells[i];
2677 seq_printf(m, "%-25s %d\n", power_well->name,
2678 power_well->count);
2679
2680 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2681 power_domain++) {
2682 if (!(BIT(power_domain) & power_well->domains))
2683 continue;
2684
2685 seq_printf(m, " %-23s %d\n",
2686 power_domain_str(power_domain),
2687 power_domains->domain_use_count[power_domain]);
2688 }
2689 }
2690
2691 mutex_unlock(&power_domains->lock);
2692
2693 return 0;
2694 }
2695
2696 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2697 struct drm_display_mode *mode)
2698 {
2699 int i;
2700
2701 for (i = 0; i < tabs; i++)
2702 seq_putc(m, '\t');
2703
2704 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2705 mode->base.id, mode->name,
2706 mode->vrefresh, mode->clock,
2707 mode->hdisplay, mode->hsync_start,
2708 mode->hsync_end, mode->htotal,
2709 mode->vdisplay, mode->vsync_start,
2710 mode->vsync_end, mode->vtotal,
2711 mode->type, mode->flags);
2712 }
2713
2714 static void intel_encoder_info(struct seq_file *m,
2715 struct intel_crtc *intel_crtc,
2716 struct intel_encoder *intel_encoder)
2717 {
2718 struct drm_info_node *node = m->private;
2719 struct drm_device *dev = node->minor->dev;
2720 struct drm_crtc *crtc = &intel_crtc->base;
2721 struct intel_connector *intel_connector;
2722 struct drm_encoder *encoder;
2723
2724 encoder = &intel_encoder->base;
2725 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2726 encoder->base.id, encoder->name);
2727 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2728 struct drm_connector *connector = &intel_connector->base;
2729 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2730 connector->base.id,
2731 connector->name,
2732 drm_get_connector_status_name(connector->status));
2733 if (connector->status == connector_status_connected) {
2734 struct drm_display_mode *mode = &crtc->mode;
2735 seq_printf(m, ", mode:\n");
2736 intel_seq_print_mode(m, 2, mode);
2737 } else {
2738 seq_putc(m, '\n');
2739 }
2740 }
2741 }
2742
2743 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2744 {
2745 struct drm_info_node *node = m->private;
2746 struct drm_device *dev = node->minor->dev;
2747 struct drm_crtc *crtc = &intel_crtc->base;
2748 struct intel_encoder *intel_encoder;
2749
2750 if (crtc->primary->fb)
2751 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2752 crtc->primary->fb->base.id, crtc->x, crtc->y,
2753 crtc->primary->fb->width, crtc->primary->fb->height);
2754 else
2755 seq_puts(m, "\tprimary plane disabled\n");
2756 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2757 intel_encoder_info(m, intel_crtc, intel_encoder);
2758 }
2759
2760 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2761 {
2762 struct drm_display_mode *mode = panel->fixed_mode;
2763
2764 seq_printf(m, "\tfixed mode:\n");
2765 intel_seq_print_mode(m, 2, mode);
2766 }
2767
2768 static void intel_dp_info(struct seq_file *m,
2769 struct intel_connector *intel_connector)
2770 {
2771 struct intel_encoder *intel_encoder = intel_connector->encoder;
2772 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2773
2774 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2775 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2776 "no");
2777 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2778 intel_panel_info(m, &intel_connector->panel);
2779 }
2780
2781 static void intel_hdmi_info(struct seq_file *m,
2782 struct intel_connector *intel_connector)
2783 {
2784 struct intel_encoder *intel_encoder = intel_connector->encoder;
2785 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2786
2787 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2788 "no");
2789 }
2790
2791 static void intel_lvds_info(struct seq_file *m,
2792 struct intel_connector *intel_connector)
2793 {
2794 intel_panel_info(m, &intel_connector->panel);
2795 }
2796
2797 static void intel_connector_info(struct seq_file *m,
2798 struct drm_connector *connector)
2799 {
2800 struct intel_connector *intel_connector = to_intel_connector(connector);
2801 struct intel_encoder *intel_encoder = intel_connector->encoder;
2802 struct drm_display_mode *mode;
2803
2804 seq_printf(m, "connector %d: type %s, status: %s\n",
2805 connector->base.id, connector->name,
2806 drm_get_connector_status_name(connector->status));
2807 if (connector->status == connector_status_connected) {
2808 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2809 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2810 connector->display_info.width_mm,
2811 connector->display_info.height_mm);
2812 seq_printf(m, "\tsubpixel order: %s\n",
2813 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2814 seq_printf(m, "\tCEA rev: %d\n",
2815 connector->display_info.cea_rev);
2816 }
2817 if (intel_encoder) {
2818 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2819 intel_encoder->type == INTEL_OUTPUT_EDP)
2820 intel_dp_info(m, intel_connector);
2821 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2822 intel_hdmi_info(m, intel_connector);
2823 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2824 intel_lvds_info(m, intel_connector);
2825 }
2826
2827 seq_printf(m, "\tmodes:\n");
2828 list_for_each_entry(mode, &connector->modes, head)
2829 intel_seq_print_mode(m, 2, mode);
2830 }
2831
2832 static bool cursor_active(struct drm_device *dev, int pipe)
2833 {
2834 struct drm_i915_private *dev_priv = dev->dev_private;
2835 u32 state;
2836
2837 if (IS_845G(dev) || IS_I865G(dev))
2838 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
2839 else
2840 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2841
2842 return state;
2843 }
2844
2845 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2846 {
2847 struct drm_i915_private *dev_priv = dev->dev_private;
2848 u32 pos;
2849
2850 pos = I915_READ(CURPOS(pipe));
2851
2852 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2853 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2854 *x = -*x;
2855
2856 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2857 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2858 *y = -*y;
2859
2860 return cursor_active(dev, pipe);
2861 }
2862
2863 static int i915_display_info(struct seq_file *m, void *unused)
2864 {
2865 struct drm_info_node *node = m->private;
2866 struct drm_device *dev = node->minor->dev;
2867 struct drm_i915_private *dev_priv = dev->dev_private;
2868 struct intel_crtc *crtc;
2869 struct drm_connector *connector;
2870
2871 intel_runtime_pm_get(dev_priv);
2872 drm_modeset_lock_all(dev);
2873 seq_printf(m, "CRTC info\n");
2874 seq_printf(m, "---------\n");
2875 for_each_intel_crtc(dev, crtc) {
2876 bool active;
2877 struct intel_crtc_state *pipe_config;
2878 int x, y;
2879
2880 pipe_config = to_intel_crtc_state(crtc->base.state);
2881
2882 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
2883 crtc->base.base.id, pipe_name(crtc->pipe),
2884 yesno(pipe_config->base.active),
2885 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
2886 if (pipe_config->base.active) {
2887 intel_crtc_info(m, crtc);
2888
2889 active = cursor_position(dev, crtc->pipe, &x, &y);
2890 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
2891 yesno(crtc->cursor_base),
2892 x, y, crtc->base.cursor->state->crtc_w,
2893 crtc->base.cursor->state->crtc_h,
2894 crtc->cursor_addr, yesno(active));
2895 }
2896
2897 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2898 yesno(!crtc->cpu_fifo_underrun_disabled),
2899 yesno(!crtc->pch_fifo_underrun_disabled));
2900 }
2901
2902 seq_printf(m, "\n");
2903 seq_printf(m, "Connector info\n");
2904 seq_printf(m, "--------------\n");
2905 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2906 intel_connector_info(m, connector);
2907 }
2908 drm_modeset_unlock_all(dev);
2909 intel_runtime_pm_put(dev_priv);
2910
2911 return 0;
2912 }
2913
2914 static int i915_semaphore_status(struct seq_file *m, void *unused)
2915 {
2916 struct drm_info_node *node = (struct drm_info_node *) m->private;
2917 struct drm_device *dev = node->minor->dev;
2918 struct drm_i915_private *dev_priv = dev->dev_private;
2919 struct intel_engine_cs *ring;
2920 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2921 int i, j, ret;
2922
2923 if (!i915_semaphore_is_enabled(dev)) {
2924 seq_puts(m, "Semaphores are disabled\n");
2925 return 0;
2926 }
2927
2928 ret = mutex_lock_interruptible(&dev->struct_mutex);
2929 if (ret)
2930 return ret;
2931 intel_runtime_pm_get(dev_priv);
2932
2933 if (IS_BROADWELL(dev)) {
2934 struct page *page;
2935 uint64_t *seqno;
2936
2937 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
2938
2939 seqno = (uint64_t *)kmap_atomic(page);
2940 for_each_ring(ring, dev_priv, i) {
2941 uint64_t offset;
2942
2943 seq_printf(m, "%s\n", ring->name);
2944
2945 seq_puts(m, " Last signal:");
2946 for (j = 0; j < num_rings; j++) {
2947 offset = i * I915_NUM_RINGS + j;
2948 seq_printf(m, "0x%08llx (0x%02llx) ",
2949 seqno[offset], offset * 8);
2950 }
2951 seq_putc(m, '\n');
2952
2953 seq_puts(m, " Last wait: ");
2954 for (j = 0; j < num_rings; j++) {
2955 offset = i + (j * I915_NUM_RINGS);
2956 seq_printf(m, "0x%08llx (0x%02llx) ",
2957 seqno[offset], offset * 8);
2958 }
2959 seq_putc(m, '\n');
2960
2961 }
2962 kunmap_atomic(seqno);
2963 } else {
2964 seq_puts(m, " Last signal:");
2965 for_each_ring(ring, dev_priv, i)
2966 for (j = 0; j < num_rings; j++)
2967 seq_printf(m, "0x%08x\n",
2968 I915_READ(ring->semaphore.mbox.signal[j]));
2969 seq_putc(m, '\n');
2970 }
2971
2972 seq_puts(m, "\nSync seqno:\n");
2973 for_each_ring(ring, dev_priv, i) {
2974 for (j = 0; j < num_rings; j++) {
2975 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]);
2976 }
2977 seq_putc(m, '\n');
2978 }
2979 seq_putc(m, '\n');
2980
2981 intel_runtime_pm_put(dev_priv);
2982 mutex_unlock(&dev->struct_mutex);
2983 return 0;
2984 }
2985
2986 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
2987 {
2988 struct drm_info_node *node = (struct drm_info_node *) m->private;
2989 struct drm_device *dev = node->minor->dev;
2990 struct drm_i915_private *dev_priv = dev->dev_private;
2991 int i;
2992
2993 drm_modeset_lock_all(dev);
2994 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2995 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
2996
2997 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
2998 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
2999 pll->config.crtc_mask, pll->active, yesno(pll->on));
3000 seq_printf(m, " tracked hardware state:\n");
3001 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
3002 seq_printf(m, " dpll_md: 0x%08x\n",
3003 pll->config.hw_state.dpll_md);
3004 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
3005 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
3006 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
3007 }
3008 drm_modeset_unlock_all(dev);
3009
3010 return 0;
3011 }
3012
3013 static int i915_wa_registers(struct seq_file *m, void *unused)
3014 {
3015 int i;
3016 int ret;
3017 struct drm_info_node *node = (struct drm_info_node *) m->private;
3018 struct drm_device *dev = node->minor->dev;
3019 struct drm_i915_private *dev_priv = dev->dev_private;
3020
3021 ret = mutex_lock_interruptible(&dev->struct_mutex);
3022 if (ret)
3023 return ret;
3024
3025 intel_runtime_pm_get(dev_priv);
3026
3027 seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
3028 for (i = 0; i < dev_priv->workarounds.count; ++i) {
3029 u32 addr, mask, value, read;
3030 bool ok;
3031
3032 addr = dev_priv->workarounds.reg[i].addr;
3033 mask = dev_priv->workarounds.reg[i].mask;
3034 value = dev_priv->workarounds.reg[i].value;
3035 read = I915_READ(addr);
3036 ok = (value & mask) == (read & mask);
3037 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3038 addr, value, mask, read, ok ? "OK" : "FAIL");
3039 }
3040
3041 intel_runtime_pm_put(dev_priv);
3042 mutex_unlock(&dev->struct_mutex);
3043
3044 return 0;
3045 }
3046
3047 static int i915_ddb_info(struct seq_file *m, void *unused)
3048 {
3049 struct drm_info_node *node = m->private;
3050 struct drm_device *dev = node->minor->dev;
3051 struct drm_i915_private *dev_priv = dev->dev_private;
3052 struct skl_ddb_allocation *ddb;
3053 struct skl_ddb_entry *entry;
3054 enum pipe pipe;
3055 int plane;
3056
3057 if (INTEL_INFO(dev)->gen < 9)
3058 return 0;
3059
3060 drm_modeset_lock_all(dev);
3061
3062 ddb = &dev_priv->wm.skl_hw.ddb;
3063
3064 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3065
3066 for_each_pipe(dev_priv, pipe) {
3067 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3068
3069 for_each_plane(dev_priv, pipe, plane) {
3070 entry = &ddb->plane[pipe][plane];
3071 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
3072 entry->start, entry->end,
3073 skl_ddb_entry_size(entry));
3074 }
3075
3076 entry = &ddb->cursor[pipe];
3077 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
3078 entry->end, skl_ddb_entry_size(entry));
3079 }
3080
3081 drm_modeset_unlock_all(dev);
3082
3083 return 0;
3084 }
3085
3086 static void drrs_status_per_crtc(struct seq_file *m,
3087 struct drm_device *dev, struct intel_crtc *intel_crtc)
3088 {
3089 struct intel_encoder *intel_encoder;
3090 struct drm_i915_private *dev_priv = dev->dev_private;
3091 struct i915_drrs *drrs = &dev_priv->drrs;
3092 int vrefresh = 0;
3093
3094 for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
3095 /* Encoder connected on this CRTC */
3096 switch (intel_encoder->type) {
3097 case INTEL_OUTPUT_EDP:
3098 seq_puts(m, "eDP:\n");
3099 break;
3100 case INTEL_OUTPUT_DSI:
3101 seq_puts(m, "DSI:\n");
3102 break;
3103 case INTEL_OUTPUT_HDMI:
3104 seq_puts(m, "HDMI:\n");
3105 break;
3106 case INTEL_OUTPUT_DISPLAYPORT:
3107 seq_puts(m, "DP:\n");
3108 break;
3109 default:
3110 seq_printf(m, "Other encoder (id=%d).\n",
3111 intel_encoder->type);
3112 return;
3113 }
3114 }
3115
3116 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3117 seq_puts(m, "\tVBT: DRRS_type: Static");
3118 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3119 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3120 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3121 seq_puts(m, "\tVBT: DRRS_type: None");
3122 else
3123 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3124
3125 seq_puts(m, "\n\n");
3126
3127 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3128 struct intel_panel *panel;
3129
3130 mutex_lock(&drrs->mutex);
3131 /* DRRS Supported */
3132 seq_puts(m, "\tDRRS Supported: Yes\n");
3133
3134 /* disable_drrs() will make drrs->dp NULL */
3135 if (!drrs->dp) {
3136 seq_puts(m, "Idleness DRRS: Disabled");
3137 mutex_unlock(&drrs->mutex);
3138 return;
3139 }
3140
3141 panel = &drrs->dp->attached_connector->panel;
3142 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3143 drrs->busy_frontbuffer_bits);
3144
3145 seq_puts(m, "\n\t\t");
3146 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3147 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3148 vrefresh = panel->fixed_mode->vrefresh;
3149 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3150 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3151 vrefresh = panel->downclock_mode->vrefresh;
3152 } else {
3153 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3154 drrs->refresh_rate_type);
3155 mutex_unlock(&drrs->mutex);
3156 return;
3157 }
3158 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3159
3160 seq_puts(m, "\n\t\t");
3161 mutex_unlock(&drrs->mutex);
3162 } else {
3163 /* DRRS not supported. Print the VBT parameter*/
3164 seq_puts(m, "\tDRRS Supported : No");
3165 }
3166 seq_puts(m, "\n");
3167 }
3168
3169 static int i915_drrs_status(struct seq_file *m, void *unused)
3170 {
3171 struct drm_info_node *node = m->private;
3172 struct drm_device *dev = node->minor->dev;
3173 struct intel_crtc *intel_crtc;
3174 int active_crtc_cnt = 0;
3175
3176 for_each_intel_crtc(dev, intel_crtc) {
3177 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3178
3179 if (intel_crtc->base.state->active) {
3180 active_crtc_cnt++;
3181 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3182
3183 drrs_status_per_crtc(m, dev, intel_crtc);
3184 }
3185
3186 drm_modeset_unlock(&intel_crtc->base.mutex);
3187 }
3188
3189 if (!active_crtc_cnt)
3190 seq_puts(m, "No active crtc found\n");
3191
3192 return 0;
3193 }
3194
3195 struct pipe_crc_info {
3196 const char *name;
3197 struct drm_device *dev;
3198 enum pipe pipe;
3199 };
3200
3201 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3202 {
3203 struct drm_info_node *node = (struct drm_info_node *) m->private;
3204 struct drm_device *dev = node->minor->dev;
3205 struct drm_encoder *encoder;
3206 struct intel_encoder *intel_encoder;
3207 struct intel_digital_port *intel_dig_port;
3208 drm_modeset_lock_all(dev);
3209 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3210 intel_encoder = to_intel_encoder(encoder);
3211 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3212 continue;
3213 intel_dig_port = enc_to_dig_port(encoder);
3214 if (!intel_dig_port->dp.can_mst)
3215 continue;
3216
3217 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3218 }
3219 drm_modeset_unlock_all(dev);
3220 return 0;
3221 }
3222
3223 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3224 {
3225 struct pipe_crc_info *info = inode->i_private;
3226 struct drm_i915_private *dev_priv = info->dev->dev_private;
3227 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3228
3229 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3230 return -ENODEV;
3231
3232 spin_lock_irq(&pipe_crc->lock);
3233
3234 if (pipe_crc->opened) {
3235 spin_unlock_irq(&pipe_crc->lock);
3236 return -EBUSY; /* already open */
3237 }
3238
3239 pipe_crc->opened = true;
3240 filep->private_data = inode->i_private;
3241
3242 spin_unlock_irq(&pipe_crc->lock);
3243
3244 return 0;
3245 }
3246
3247 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3248 {
3249 struct pipe_crc_info *info = inode->i_private;
3250 struct drm_i915_private *dev_priv = info->dev->dev_private;
3251 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3252
3253 spin_lock_irq(&pipe_crc->lock);
3254 pipe_crc->opened = false;
3255 spin_unlock_irq(&pipe_crc->lock);
3256
3257 return 0;
3258 }
3259
3260 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3261 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3262 /* account for \'0' */
3263 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3264
3265 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3266 {
3267 assert_spin_locked(&pipe_crc->lock);
3268 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3269 INTEL_PIPE_CRC_ENTRIES_NR);
3270 }
3271
3272 static ssize_t
3273 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3274 loff_t *pos)
3275 {
3276 struct pipe_crc_info *info = filep->private_data;
3277 struct drm_device *dev = info->dev;
3278 struct drm_i915_private *dev_priv = dev->dev_private;
3279 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3280 char buf[PIPE_CRC_BUFFER_LEN];
3281 int n_entries;
3282 ssize_t bytes_read;
3283
3284 /*
3285 * Don't allow user space to provide buffers not big enough to hold
3286 * a line of data.
3287 */
3288 if (count < PIPE_CRC_LINE_LEN)
3289 return -EINVAL;
3290
3291 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3292 return 0;
3293
3294 /* nothing to read */
3295 spin_lock_irq(&pipe_crc->lock);
3296 while (pipe_crc_data_count(pipe_crc) == 0) {
3297 int ret;
3298
3299 if (filep->f_flags & O_NONBLOCK) {
3300 spin_unlock_irq(&pipe_crc->lock);
3301 return -EAGAIN;
3302 }
3303
3304 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3305 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3306 if (ret) {
3307 spin_unlock_irq(&pipe_crc->lock);
3308 return ret;
3309 }
3310 }
3311
3312 /* We now have one or more entries to read */
3313 n_entries = count / PIPE_CRC_LINE_LEN;
3314
3315 bytes_read = 0;
3316 while (n_entries > 0) {
3317 struct intel_pipe_crc_entry *entry =
3318 &pipe_crc->entries[pipe_crc->tail];
3319 int ret;
3320
3321 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3322 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3323 break;
3324
3325 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3326 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3327
3328 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3329 "%8u %8x %8x %8x %8x %8x\n",
3330 entry->frame, entry->crc[0],
3331 entry->crc[1], entry->crc[2],
3332 entry->crc[3], entry->crc[4]);
3333
3334 spin_unlock_irq(&pipe_crc->lock);
3335
3336 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
3337 if (ret == PIPE_CRC_LINE_LEN)
3338 return -EFAULT;
3339
3340 user_buf += PIPE_CRC_LINE_LEN;
3341 n_entries--;
3342
3343 spin_lock_irq(&pipe_crc->lock);
3344 }
3345
3346 spin_unlock_irq(&pipe_crc->lock);
3347
3348 return bytes_read;
3349 }
3350
3351 static const struct file_operations i915_pipe_crc_fops = {
3352 .owner = THIS_MODULE,
3353 .open = i915_pipe_crc_open,
3354 .read = i915_pipe_crc_read,
3355 .release = i915_pipe_crc_release,
3356 };
3357
3358 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3359 {
3360 .name = "i915_pipe_A_crc",
3361 .pipe = PIPE_A,
3362 },
3363 {
3364 .name = "i915_pipe_B_crc",
3365 .pipe = PIPE_B,
3366 },
3367 {
3368 .name = "i915_pipe_C_crc",
3369 .pipe = PIPE_C,
3370 },
3371 };
3372
3373 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3374 enum pipe pipe)
3375 {
3376 struct drm_device *dev = minor->dev;
3377 struct dentry *ent;
3378 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3379
3380 info->dev = dev;
3381 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3382 &i915_pipe_crc_fops);
3383 if (!ent)
3384 return -ENOMEM;
3385
3386 return drm_add_fake_info_node(minor, ent, info);
3387 }
3388
3389 static const char * const pipe_crc_sources[] = {
3390 "none",
3391 "plane1",
3392 "plane2",
3393 "pf",
3394 "pipe",
3395 "TV",
3396 "DP-B",
3397 "DP-C",
3398 "DP-D",
3399 "auto",
3400 };
3401
3402 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3403 {
3404 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3405 return pipe_crc_sources[source];
3406 }
3407
3408 static int display_crc_ctl_show(struct seq_file *m, void *data)
3409 {
3410 struct drm_device *dev = m->private;
3411 struct drm_i915_private *dev_priv = dev->dev_private;
3412 int i;
3413
3414 for (i = 0; i < I915_MAX_PIPES; i++)
3415 seq_printf(m, "%c %s\n", pipe_name(i),
3416 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3417
3418 return 0;
3419 }
3420
3421 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3422 {
3423 struct drm_device *dev = inode->i_private;
3424
3425 return single_open(file, display_crc_ctl_show, dev);
3426 }
3427
3428 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3429 uint32_t *val)
3430 {
3431 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3432 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3433
3434 switch (*source) {
3435 case INTEL_PIPE_CRC_SOURCE_PIPE:
3436 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3437 break;
3438 case INTEL_PIPE_CRC_SOURCE_NONE:
3439 *val = 0;
3440 break;
3441 default:
3442 return -EINVAL;
3443 }
3444
3445 return 0;
3446 }
3447
3448 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3449 enum intel_pipe_crc_source *source)
3450 {
3451 struct intel_encoder *encoder;
3452 struct intel_crtc *crtc;
3453 struct intel_digital_port *dig_port;
3454 int ret = 0;
3455
3456 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3457
3458 drm_modeset_lock_all(dev);
3459 for_each_intel_encoder(dev, encoder) {
3460 if (!encoder->base.crtc)
3461 continue;
3462
3463 crtc = to_intel_crtc(encoder->base.crtc);
3464
3465 if (crtc->pipe != pipe)
3466 continue;
3467
3468 switch (encoder->type) {
3469 case INTEL_OUTPUT_TVOUT:
3470 *source = INTEL_PIPE_CRC_SOURCE_TV;
3471 break;
3472 case INTEL_OUTPUT_DISPLAYPORT:
3473 case INTEL_OUTPUT_EDP:
3474 dig_port = enc_to_dig_port(&encoder->base);
3475 switch (dig_port->port) {
3476 case PORT_B:
3477 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3478 break;
3479 case PORT_C:
3480 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3481 break;
3482 case PORT_D:
3483 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3484 break;
3485 default:
3486 WARN(1, "nonexisting DP port %c\n",
3487 port_name(dig_port->port));
3488 break;
3489 }
3490 break;
3491 default:
3492 break;
3493 }
3494 }
3495 drm_modeset_unlock_all(dev);
3496
3497 return ret;
3498 }
3499
3500 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3501 enum pipe pipe,
3502 enum intel_pipe_crc_source *source,
3503 uint32_t *val)
3504 {
3505 struct drm_i915_private *dev_priv = dev->dev_private;
3506 bool need_stable_symbols = false;
3507
3508 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3509 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3510 if (ret)
3511 return ret;
3512 }
3513
3514 switch (*source) {
3515 case INTEL_PIPE_CRC_SOURCE_PIPE:
3516 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3517 break;
3518 case INTEL_PIPE_CRC_SOURCE_DP_B:
3519 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3520 need_stable_symbols = true;
3521 break;
3522 case INTEL_PIPE_CRC_SOURCE_DP_C:
3523 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3524 need_stable_symbols = true;
3525 break;
3526 case INTEL_PIPE_CRC_SOURCE_DP_D:
3527 if (!IS_CHERRYVIEW(dev))
3528 return -EINVAL;
3529 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3530 need_stable_symbols = true;
3531 break;
3532 case INTEL_PIPE_CRC_SOURCE_NONE:
3533 *val = 0;
3534 break;
3535 default:
3536 return -EINVAL;
3537 }
3538
3539 /*
3540 * When the pipe CRC tap point is after the transcoders we need
3541 * to tweak symbol-level features to produce a deterministic series of
3542 * symbols for a given frame. We need to reset those features only once
3543 * a frame (instead of every nth symbol):
3544 * - DC-balance: used to ensure a better clock recovery from the data
3545 * link (SDVO)
3546 * - DisplayPort scrambling: used for EMI reduction
3547 */
3548 if (need_stable_symbols) {
3549 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3550
3551 tmp |= DC_BALANCE_RESET_VLV;
3552 switch (pipe) {
3553 case PIPE_A:
3554 tmp |= PIPE_A_SCRAMBLE_RESET;
3555 break;
3556 case PIPE_B:
3557 tmp |= PIPE_B_SCRAMBLE_RESET;
3558 break;
3559 case PIPE_C:
3560 tmp |= PIPE_C_SCRAMBLE_RESET;
3561 break;
3562 default:
3563 return -EINVAL;
3564 }
3565 I915_WRITE(PORT_DFT2_G4X, tmp);
3566 }
3567
3568 return 0;
3569 }
3570
3571 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3572 enum pipe pipe,
3573 enum intel_pipe_crc_source *source,
3574 uint32_t *val)
3575 {
3576 struct drm_i915_private *dev_priv = dev->dev_private;
3577 bool need_stable_symbols = false;
3578
3579 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3580 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3581 if (ret)
3582 return ret;
3583 }
3584
3585 switch (*source) {
3586 case INTEL_PIPE_CRC_SOURCE_PIPE:
3587 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3588 break;
3589 case INTEL_PIPE_CRC_SOURCE_TV:
3590 if (!SUPPORTS_TV(dev))
3591 return -EINVAL;
3592 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3593 break;
3594 case INTEL_PIPE_CRC_SOURCE_DP_B:
3595 if (!IS_G4X(dev))
3596 return -EINVAL;
3597 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3598 need_stable_symbols = true;
3599 break;
3600 case INTEL_PIPE_CRC_SOURCE_DP_C:
3601 if (!IS_G4X(dev))
3602 return -EINVAL;
3603 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3604 need_stable_symbols = true;
3605 break;
3606 case INTEL_PIPE_CRC_SOURCE_DP_D:
3607 if (!IS_G4X(dev))
3608 return -EINVAL;
3609 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3610 need_stable_symbols = true;
3611 break;
3612 case INTEL_PIPE_CRC_SOURCE_NONE:
3613 *val = 0;
3614 break;
3615 default:
3616 return -EINVAL;
3617 }
3618
3619 /*
3620 * When the pipe CRC tap point is after the transcoders we need
3621 * to tweak symbol-level features to produce a deterministic series of
3622 * symbols for a given frame. We need to reset those features only once
3623 * a frame (instead of every nth symbol):
3624 * - DC-balance: used to ensure a better clock recovery from the data
3625 * link (SDVO)
3626 * - DisplayPort scrambling: used for EMI reduction
3627 */
3628 if (need_stable_symbols) {
3629 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3630
3631 WARN_ON(!IS_G4X(dev));
3632
3633 I915_WRITE(PORT_DFT_I9XX,
3634 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3635
3636 if (pipe == PIPE_A)
3637 tmp |= PIPE_A_SCRAMBLE_RESET;
3638 else
3639 tmp |= PIPE_B_SCRAMBLE_RESET;
3640
3641 I915_WRITE(PORT_DFT2_G4X, tmp);
3642 }
3643
3644 return 0;
3645 }
3646
3647 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3648 enum pipe pipe)
3649 {
3650 struct drm_i915_private *dev_priv = dev->dev_private;
3651 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3652
3653 switch (pipe) {
3654 case PIPE_A:
3655 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3656 break;
3657 case PIPE_B:
3658 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3659 break;
3660 case PIPE_C:
3661 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3662 break;
3663 default:
3664 return;
3665 }
3666 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3667 tmp &= ~DC_BALANCE_RESET_VLV;
3668 I915_WRITE(PORT_DFT2_G4X, tmp);
3669
3670 }
3671
3672 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3673 enum pipe pipe)
3674 {
3675 struct drm_i915_private *dev_priv = dev->dev_private;
3676 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3677
3678 if (pipe == PIPE_A)
3679 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3680 else
3681 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3682 I915_WRITE(PORT_DFT2_G4X, tmp);
3683
3684 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3685 I915_WRITE(PORT_DFT_I9XX,
3686 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3687 }
3688 }
3689
3690 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3691 uint32_t *val)
3692 {
3693 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3694 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3695
3696 switch (*source) {
3697 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3698 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3699 break;
3700 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3701 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3702 break;
3703 case INTEL_PIPE_CRC_SOURCE_PIPE:
3704 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3705 break;
3706 case INTEL_PIPE_CRC_SOURCE_NONE:
3707 *val = 0;
3708 break;
3709 default:
3710 return -EINVAL;
3711 }
3712
3713 return 0;
3714 }
3715
3716 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
3717 {
3718 struct drm_i915_private *dev_priv = dev->dev_private;
3719 struct intel_crtc *crtc =
3720 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3721 struct intel_crtc_state *pipe_config;
3722 struct drm_atomic_state *state;
3723 int ret = 0;
3724
3725 drm_modeset_lock_all(dev);
3726 state = drm_atomic_state_alloc(dev);
3727 if (!state) {
3728 ret = -ENOMEM;
3729 goto out;
3730 }
3731
3732 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
3733 pipe_config = intel_atomic_get_crtc_state(state, crtc);
3734 if (IS_ERR(pipe_config)) {
3735 ret = PTR_ERR(pipe_config);
3736 goto out;
3737 }
3738
3739 pipe_config->pch_pfit.force_thru = enable;
3740 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
3741 pipe_config->pch_pfit.enabled != enable)
3742 pipe_config->base.connectors_changed = true;
3743
3744 ret = drm_atomic_commit(state);
3745 out:
3746 drm_modeset_unlock_all(dev);
3747 WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
3748 if (ret)
3749 drm_atomic_state_free(state);
3750 }
3751
3752 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3753 enum pipe pipe,
3754 enum intel_pipe_crc_source *source,
3755 uint32_t *val)
3756 {
3757 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3758 *source = INTEL_PIPE_CRC_SOURCE_PF;
3759
3760 switch (*source) {
3761 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3762 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3763 break;
3764 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3765 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3766 break;
3767 case INTEL_PIPE_CRC_SOURCE_PF:
3768 if (IS_HASWELL(dev) && pipe == PIPE_A)
3769 hsw_trans_edp_pipe_A_crc_wa(dev, true);
3770
3771 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3772 break;
3773 case INTEL_PIPE_CRC_SOURCE_NONE:
3774 *val = 0;
3775 break;
3776 default:
3777 return -EINVAL;
3778 }
3779
3780 return 0;
3781 }
3782
3783 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3784 enum intel_pipe_crc_source source)
3785 {
3786 struct drm_i915_private *dev_priv = dev->dev_private;
3787 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3788 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3789 pipe));
3790 u32 val = 0; /* shut up gcc */
3791 int ret;
3792
3793 if (pipe_crc->source == source)
3794 return 0;
3795
3796 /* forbid changing the source without going back to 'none' */
3797 if (pipe_crc->source && source)
3798 return -EINVAL;
3799
3800 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3801 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3802 return -EIO;
3803 }
3804
3805 if (IS_GEN2(dev))
3806 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
3807 else if (INTEL_INFO(dev)->gen < 5)
3808 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3809 else if (IS_VALLEYVIEW(dev))
3810 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3811 else if (IS_GEN5(dev) || IS_GEN6(dev))
3812 ret = ilk_pipe_crc_ctl_reg(&source, &val);
3813 else
3814 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3815
3816 if (ret != 0)
3817 return ret;
3818
3819 /* none -> real source transition */
3820 if (source) {
3821 struct intel_pipe_crc_entry *entries;
3822
3823 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3824 pipe_name(pipe), pipe_crc_source_name(source));
3825
3826 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
3827 sizeof(pipe_crc->entries[0]),
3828 GFP_KERNEL);
3829 if (!entries)
3830 return -ENOMEM;
3831
3832 /*
3833 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3834 * enabled and disabled dynamically based on package C states,
3835 * user space can't make reliable use of the CRCs, so let's just
3836 * completely disable it.
3837 */
3838 hsw_disable_ips(crtc);
3839
3840 spin_lock_irq(&pipe_crc->lock);
3841 kfree(pipe_crc->entries);
3842 pipe_crc->entries = entries;
3843 pipe_crc->head = 0;
3844 pipe_crc->tail = 0;
3845 spin_unlock_irq(&pipe_crc->lock);
3846 }
3847
3848 pipe_crc->source = source;
3849
3850 I915_WRITE(PIPE_CRC_CTL(pipe), val);
3851 POSTING_READ(PIPE_CRC_CTL(pipe));
3852
3853 /* real source -> none transition */
3854 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
3855 struct intel_pipe_crc_entry *entries;
3856 struct intel_crtc *crtc =
3857 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3858
3859 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3860 pipe_name(pipe));
3861
3862 drm_modeset_lock(&crtc->base.mutex, NULL);
3863 if (crtc->base.state->active)
3864 intel_wait_for_vblank(dev, pipe);
3865 drm_modeset_unlock(&crtc->base.mutex);
3866
3867 spin_lock_irq(&pipe_crc->lock);
3868 entries = pipe_crc->entries;
3869 pipe_crc->entries = NULL;
3870 pipe_crc->head = 0;
3871 pipe_crc->tail = 0;
3872 spin_unlock_irq(&pipe_crc->lock);
3873
3874 kfree(entries);
3875
3876 if (IS_G4X(dev))
3877 g4x_undo_pipe_scramble_reset(dev, pipe);
3878 else if (IS_VALLEYVIEW(dev))
3879 vlv_undo_pipe_scramble_reset(dev, pipe);
3880 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3881 hsw_trans_edp_pipe_A_crc_wa(dev, false);
3882
3883 hsw_enable_ips(crtc);
3884 }
3885
3886 return 0;
3887 }
3888
3889 /*
3890 * Parse pipe CRC command strings:
3891 * command: wsp* object wsp+ name wsp+ source wsp*
3892 * object: 'pipe'
3893 * name: (A | B | C)
3894 * source: (none | plane1 | plane2 | pf)
3895 * wsp: (#0x20 | #0x9 | #0xA)+
3896 *
3897 * eg.:
3898 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3899 * "pipe A none" -> Stop CRC
3900 */
3901 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
3902 {
3903 int n_words = 0;
3904
3905 while (*buf) {
3906 char *end;
3907
3908 /* skip leading white space */
3909 buf = skip_spaces(buf);
3910 if (!*buf)
3911 break; /* end of buffer */
3912
3913 /* find end of word */
3914 for (end = buf; *end && !isspace(*end); end++)
3915 ;
3916
3917 if (n_words == max_words) {
3918 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3919 max_words);
3920 return -EINVAL; /* ran out of words[] before bytes */
3921 }
3922
3923 if (*end)
3924 *end++ = '\0';
3925 words[n_words++] = buf;
3926 buf = end;
3927 }
3928
3929 return n_words;
3930 }
3931
3932 enum intel_pipe_crc_object {
3933 PIPE_CRC_OBJECT_PIPE,
3934 };
3935
3936 static const char * const pipe_crc_objects[] = {
3937 "pipe",
3938 };
3939
3940 static int
3941 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
3942 {
3943 int i;
3944
3945 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3946 if (!strcmp(buf, pipe_crc_objects[i])) {
3947 *o = i;
3948 return 0;
3949 }
3950
3951 return -EINVAL;
3952 }
3953
3954 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
3955 {
3956 const char name = buf[0];
3957
3958 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3959 return -EINVAL;
3960
3961 *pipe = name - 'A';
3962
3963 return 0;
3964 }
3965
3966 static int
3967 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
3968 {
3969 int i;
3970
3971 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3972 if (!strcmp(buf, pipe_crc_sources[i])) {
3973 *s = i;
3974 return 0;
3975 }
3976
3977 return -EINVAL;
3978 }
3979
3980 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
3981 {
3982 #define N_WORDS 3
3983 int n_words;
3984 char *words[N_WORDS];
3985 enum pipe pipe;
3986 enum intel_pipe_crc_object object;
3987 enum intel_pipe_crc_source source;
3988
3989 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
3990 if (n_words != N_WORDS) {
3991 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3992 N_WORDS);
3993 return -EINVAL;
3994 }
3995
3996 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
3997 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
3998 return -EINVAL;
3999 }
4000
4001 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4002 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4003 return -EINVAL;
4004 }
4005
4006 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4007 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4008 return -EINVAL;
4009 }
4010
4011 return pipe_crc_set_source(dev, pipe, source);
4012 }
4013
4014 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4015 size_t len, loff_t *offp)
4016 {
4017 struct seq_file *m = file->private_data;
4018 struct drm_device *dev = m->private;
4019 char *tmpbuf;
4020 int ret;
4021
4022 if (len == 0)
4023 return 0;
4024
4025 if (len > PAGE_SIZE - 1) {
4026 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4027 PAGE_SIZE);
4028 return -E2BIG;
4029 }
4030
4031 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4032 if (!tmpbuf)
4033 return -ENOMEM;
4034
4035 if (copy_from_user(tmpbuf, ubuf, len)) {
4036 ret = -EFAULT;
4037 goto out;
4038 }
4039 tmpbuf[len] = '\0';
4040
4041 ret = display_crc_ctl_parse(dev, tmpbuf, len);
4042
4043 out:
4044 kfree(tmpbuf);
4045 if (ret < 0)
4046 return ret;
4047
4048 *offp += len;
4049 return len;
4050 }
4051
4052 static const struct file_operations i915_display_crc_ctl_fops = {
4053 .owner = THIS_MODULE,
4054 .open = display_crc_ctl_open,
4055 .read = seq_read,
4056 .llseek = seq_lseek,
4057 .release = single_release,
4058 .write = display_crc_ctl_write
4059 };
4060
4061 static ssize_t i915_displayport_test_active_write(struct file *file,
4062 const char __user *ubuf,
4063 size_t len, loff_t *offp)
4064 {
4065 char *input_buffer;
4066 int status = 0;
4067 struct drm_device *dev;
4068 struct drm_connector *connector;
4069 struct list_head *connector_list;
4070 struct intel_dp *intel_dp;
4071 int val = 0;
4072
4073 dev = ((struct seq_file *)file->private_data)->private;
4074
4075 connector_list = &dev->mode_config.connector_list;
4076
4077 if (len == 0)
4078 return 0;
4079
4080 input_buffer = kmalloc(len + 1, GFP_KERNEL);
4081 if (!input_buffer)
4082 return -ENOMEM;
4083
4084 if (copy_from_user(input_buffer, ubuf, len)) {
4085 status = -EFAULT;
4086 goto out;
4087 }
4088
4089 input_buffer[len] = '\0';
4090 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4091
4092 list_for_each_entry(connector, connector_list, head) {
4093
4094 if (connector->connector_type !=
4095 DRM_MODE_CONNECTOR_DisplayPort)
4096 continue;
4097
4098 if (connector->status == connector_status_connected &&
4099 connector->encoder != NULL) {
4100 intel_dp = enc_to_intel_dp(connector->encoder);
4101 status = kstrtoint(input_buffer, 10, &val);
4102 if (status < 0)
4103 goto out;
4104 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4105 /* To prevent erroneous activation of the compliance
4106 * testing code, only accept an actual value of 1 here
4107 */
4108 if (val == 1)
4109 intel_dp->compliance_test_active = 1;
4110 else
4111 intel_dp->compliance_test_active = 0;
4112 }
4113 }
4114 out:
4115 kfree(input_buffer);
4116 if (status < 0)
4117 return status;
4118
4119 *offp += len;
4120 return len;
4121 }
4122
4123 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4124 {
4125 struct drm_device *dev = m->private;
4126 struct drm_connector *connector;
4127 struct list_head *connector_list = &dev->mode_config.connector_list;
4128 struct intel_dp *intel_dp;
4129
4130 list_for_each_entry(connector, connector_list, head) {
4131
4132 if (connector->connector_type !=
4133 DRM_MODE_CONNECTOR_DisplayPort)
4134 continue;
4135
4136 if (connector->status == connector_status_connected &&
4137 connector->encoder != NULL) {
4138 intel_dp = enc_to_intel_dp(connector->encoder);
4139 if (intel_dp->compliance_test_active)
4140 seq_puts(m, "1");
4141 else
4142 seq_puts(m, "0");
4143 } else
4144 seq_puts(m, "0");
4145 }
4146
4147 return 0;
4148 }
4149
4150 static int i915_displayport_test_active_open(struct inode *inode,
4151 struct file *file)
4152 {
4153 struct drm_device *dev = inode->i_private;
4154
4155 return single_open(file, i915_displayport_test_active_show, dev);
4156 }
4157
4158 static const struct file_operations i915_displayport_test_active_fops = {
4159 .owner = THIS_MODULE,
4160 .open = i915_displayport_test_active_open,
4161 .read = seq_read,
4162 .llseek = seq_lseek,
4163 .release = single_release,
4164 .write = i915_displayport_test_active_write
4165 };
4166
4167 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4168 {
4169 struct drm_device *dev = m->private;
4170 struct drm_connector *connector;
4171 struct list_head *connector_list = &dev->mode_config.connector_list;
4172 struct intel_dp *intel_dp;
4173
4174 list_for_each_entry(connector, connector_list, head) {
4175
4176 if (connector->connector_type !=
4177 DRM_MODE_CONNECTOR_DisplayPort)
4178 continue;
4179
4180 if (connector->status == connector_status_connected &&
4181 connector->encoder != NULL) {
4182 intel_dp = enc_to_intel_dp(connector->encoder);
4183 seq_printf(m, "%lx", intel_dp->compliance_test_data);
4184 } else
4185 seq_puts(m, "0");
4186 }
4187
4188 return 0;
4189 }
4190 static int i915_displayport_test_data_open(struct inode *inode,
4191 struct file *file)
4192 {
4193 struct drm_device *dev = inode->i_private;
4194
4195 return single_open(file, i915_displayport_test_data_show, dev);
4196 }
4197
4198 static const struct file_operations i915_displayport_test_data_fops = {
4199 .owner = THIS_MODULE,
4200 .open = i915_displayport_test_data_open,
4201 .read = seq_read,
4202 .llseek = seq_lseek,
4203 .release = single_release
4204 };
4205
4206 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4207 {
4208 struct drm_device *dev = m->private;
4209 struct drm_connector *connector;
4210 struct list_head *connector_list = &dev->mode_config.connector_list;
4211 struct intel_dp *intel_dp;
4212
4213 list_for_each_entry(connector, connector_list, head) {
4214
4215 if (connector->connector_type !=
4216 DRM_MODE_CONNECTOR_DisplayPort)
4217 continue;
4218
4219 if (connector->status == connector_status_connected &&
4220 connector->encoder != NULL) {
4221 intel_dp = enc_to_intel_dp(connector->encoder);
4222 seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4223 } else
4224 seq_puts(m, "0");
4225 }
4226
4227 return 0;
4228 }
4229
4230 static int i915_displayport_test_type_open(struct inode *inode,
4231 struct file *file)
4232 {
4233 struct drm_device *dev = inode->i_private;
4234
4235 return single_open(file, i915_displayport_test_type_show, dev);
4236 }
4237
4238 static const struct file_operations i915_displayport_test_type_fops = {
4239 .owner = THIS_MODULE,
4240 .open = i915_displayport_test_type_open,
4241 .read = seq_read,
4242 .llseek = seq_lseek,
4243 .release = single_release
4244 };
4245
4246 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4247 {
4248 struct drm_device *dev = m->private;
4249 int level;
4250 int num_levels;
4251
4252 if (IS_CHERRYVIEW(dev))
4253 num_levels = 3;
4254 else if (IS_VALLEYVIEW(dev))
4255 num_levels = 1;
4256 else
4257 num_levels = ilk_wm_max_level(dev) + 1;
4258
4259 drm_modeset_lock_all(dev);
4260
4261 for (level = 0; level < num_levels; level++) {
4262 unsigned int latency = wm[level];
4263
4264 /*
4265 * - WM1+ latency values in 0.5us units
4266 * - latencies are in us on gen9/vlv/chv
4267 */
4268 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev))
4269 latency *= 10;
4270 else if (level > 0)
4271 latency *= 5;
4272
4273 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4274 level, wm[level], latency / 10, latency % 10);
4275 }
4276
4277 drm_modeset_unlock_all(dev);
4278 }
4279
4280 static int pri_wm_latency_show(struct seq_file *m, void *data)
4281 {
4282 struct drm_device *dev = m->private;
4283 struct drm_i915_private *dev_priv = dev->dev_private;
4284 const uint16_t *latencies;
4285
4286 if (INTEL_INFO(dev)->gen >= 9)
4287 latencies = dev_priv->wm.skl_latency;
4288 else
4289 latencies = to_i915(dev)->wm.pri_latency;
4290
4291 wm_latency_show(m, latencies);
4292
4293 return 0;
4294 }
4295
4296 static int spr_wm_latency_show(struct seq_file *m, void *data)
4297 {
4298 struct drm_device *dev = m->private;
4299 struct drm_i915_private *dev_priv = dev->dev_private;
4300 const uint16_t *latencies;
4301
4302 if (INTEL_INFO(dev)->gen >= 9)
4303 latencies = dev_priv->wm.skl_latency;
4304 else
4305 latencies = to_i915(dev)->wm.spr_latency;
4306
4307 wm_latency_show(m, latencies);
4308
4309 return 0;
4310 }
4311
4312 static int cur_wm_latency_show(struct seq_file *m, void *data)
4313 {
4314 struct drm_device *dev = m->private;
4315 struct drm_i915_private *dev_priv = dev->dev_private;
4316 const uint16_t *latencies;
4317
4318 if (INTEL_INFO(dev)->gen >= 9)
4319 latencies = dev_priv->wm.skl_latency;
4320 else
4321 latencies = to_i915(dev)->wm.cur_latency;
4322
4323 wm_latency_show(m, latencies);
4324
4325 return 0;
4326 }
4327
4328 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4329 {
4330 struct drm_device *dev = inode->i_private;
4331
4332 if (INTEL_INFO(dev)->gen < 5)
4333 return -ENODEV;
4334
4335 return single_open(file, pri_wm_latency_show, dev);
4336 }
4337
4338 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4339 {
4340 struct drm_device *dev = inode->i_private;
4341
4342 if (HAS_GMCH_DISPLAY(dev))
4343 return -ENODEV;
4344
4345 return single_open(file, spr_wm_latency_show, dev);
4346 }
4347
4348 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4349 {
4350 struct drm_device *dev = inode->i_private;
4351
4352 if (HAS_GMCH_DISPLAY(dev))
4353 return -ENODEV;
4354
4355 return single_open(file, cur_wm_latency_show, dev);
4356 }
4357
4358 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4359 size_t len, loff_t *offp, uint16_t wm[8])
4360 {
4361 struct seq_file *m = file->private_data;
4362 struct drm_device *dev = m->private;
4363 uint16_t new[8] = { 0 };
4364 int num_levels;
4365 int level;
4366 int ret;
4367 char tmp[32];
4368
4369 if (IS_CHERRYVIEW(dev))
4370 num_levels = 3;
4371 else if (IS_VALLEYVIEW(dev))
4372 num_levels = 1;
4373 else
4374 num_levels = ilk_wm_max_level(dev) + 1;
4375
4376 if (len >= sizeof(tmp))
4377 return -EINVAL;
4378
4379 if (copy_from_user(tmp, ubuf, len))
4380 return -EFAULT;
4381
4382 tmp[len] = '\0';
4383
4384 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4385 &new[0], &new[1], &new[2], &new[3],
4386 &new[4], &new[5], &new[6], &new[7]);
4387 if (ret != num_levels)
4388 return -EINVAL;
4389
4390 drm_modeset_lock_all(dev);
4391
4392 for (level = 0; level < num_levels; level++)
4393 wm[level] = new[level];
4394
4395 drm_modeset_unlock_all(dev);
4396
4397 return len;
4398 }
4399
4400
4401 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4402 size_t len, loff_t *offp)
4403 {
4404 struct seq_file *m = file->private_data;
4405 struct drm_device *dev = m->private;
4406 struct drm_i915_private *dev_priv = dev->dev_private;
4407 uint16_t *latencies;
4408
4409 if (INTEL_INFO(dev)->gen >= 9)
4410 latencies = dev_priv->wm.skl_latency;
4411 else
4412 latencies = to_i915(dev)->wm.pri_latency;
4413
4414 return wm_latency_write(file, ubuf, len, offp, latencies);
4415 }
4416
4417 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4418 size_t len, loff_t *offp)
4419 {
4420 struct seq_file *m = file->private_data;
4421 struct drm_device *dev = m->private;
4422 struct drm_i915_private *dev_priv = dev->dev_private;
4423 uint16_t *latencies;
4424
4425 if (INTEL_INFO(dev)->gen >= 9)
4426 latencies = dev_priv->wm.skl_latency;
4427 else
4428 latencies = to_i915(dev)->wm.spr_latency;
4429
4430 return wm_latency_write(file, ubuf, len, offp, latencies);
4431 }
4432
4433 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4434 size_t len, loff_t *offp)
4435 {
4436 struct seq_file *m = file->private_data;
4437 struct drm_device *dev = m->private;
4438 struct drm_i915_private *dev_priv = dev->dev_private;
4439 uint16_t *latencies;
4440
4441 if (INTEL_INFO(dev)->gen >= 9)
4442 latencies = dev_priv->wm.skl_latency;
4443 else
4444 latencies = to_i915(dev)->wm.cur_latency;
4445
4446 return wm_latency_write(file, ubuf, len, offp, latencies);
4447 }
4448
4449 static const struct file_operations i915_pri_wm_latency_fops = {
4450 .owner = THIS_MODULE,
4451 .open = pri_wm_latency_open,
4452 .read = seq_read,
4453 .llseek = seq_lseek,
4454 .release = single_release,
4455 .write = pri_wm_latency_write
4456 };
4457
4458 static const struct file_operations i915_spr_wm_latency_fops = {
4459 .owner = THIS_MODULE,
4460 .open = spr_wm_latency_open,
4461 .read = seq_read,
4462 .llseek = seq_lseek,
4463 .release = single_release,
4464 .write = spr_wm_latency_write
4465 };
4466
4467 static const struct file_operations i915_cur_wm_latency_fops = {
4468 .owner = THIS_MODULE,
4469 .open = cur_wm_latency_open,
4470 .read = seq_read,
4471 .llseek = seq_lseek,
4472 .release = single_release,
4473 .write = cur_wm_latency_write
4474 };
4475
4476 static int
4477 i915_wedged_get(void *data, u64 *val)
4478 {
4479 struct drm_device *dev = data;
4480 struct drm_i915_private *dev_priv = dev->dev_private;
4481
4482 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
4483
4484 return 0;
4485 }
4486
4487 static int
4488 i915_wedged_set(void *data, u64 val)
4489 {
4490 struct drm_device *dev = data;
4491 struct drm_i915_private *dev_priv = dev->dev_private;
4492
4493 /*
4494 * There is no safeguard against this debugfs entry colliding
4495 * with the hangcheck calling same i915_handle_error() in
4496 * parallel, causing an explosion. For now we assume that the
4497 * test harness is responsible enough not to inject gpu hangs
4498 * while it is writing to 'i915_wedged'
4499 */
4500
4501 if (i915_reset_in_progress(&dev_priv->gpu_error))
4502 return -EAGAIN;
4503
4504 intel_runtime_pm_get(dev_priv);
4505
4506 i915_handle_error(dev, val,
4507 "Manually setting wedged to %llu", val);
4508
4509 intel_runtime_pm_put(dev_priv);
4510
4511 return 0;
4512 }
4513
4514 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4515 i915_wedged_get, i915_wedged_set,
4516 "%llu\n");
4517
4518 static int
4519 i915_ring_stop_get(void *data, u64 *val)
4520 {
4521 struct drm_device *dev = data;
4522 struct drm_i915_private *dev_priv = dev->dev_private;
4523
4524 *val = dev_priv->gpu_error.stop_rings;
4525
4526 return 0;
4527 }
4528
4529 static int
4530 i915_ring_stop_set(void *data, u64 val)
4531 {
4532 struct drm_device *dev = data;
4533 struct drm_i915_private *dev_priv = dev->dev_private;
4534 int ret;
4535
4536 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
4537
4538 ret = mutex_lock_interruptible(&dev->struct_mutex);
4539 if (ret)
4540 return ret;
4541
4542 dev_priv->gpu_error.stop_rings = val;
4543 mutex_unlock(&dev->struct_mutex);
4544
4545 return 0;
4546 }
4547
4548 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4549 i915_ring_stop_get, i915_ring_stop_set,
4550 "0x%08llx\n");
4551
4552 static int
4553 i915_ring_missed_irq_get(void *data, u64 *val)
4554 {
4555 struct drm_device *dev = data;
4556 struct drm_i915_private *dev_priv = dev->dev_private;
4557
4558 *val = dev_priv->gpu_error.missed_irq_rings;
4559 return 0;
4560 }
4561
4562 static int
4563 i915_ring_missed_irq_set(void *data, u64 val)
4564 {
4565 struct drm_device *dev = data;
4566 struct drm_i915_private *dev_priv = dev->dev_private;
4567 int ret;
4568
4569 /* Lock against concurrent debugfs callers */
4570 ret = mutex_lock_interruptible(&dev->struct_mutex);
4571 if (ret)
4572 return ret;
4573 dev_priv->gpu_error.missed_irq_rings = val;
4574 mutex_unlock(&dev->struct_mutex);
4575
4576 return 0;
4577 }
4578
4579 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4580 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4581 "0x%08llx\n");
4582
4583 static int
4584 i915_ring_test_irq_get(void *data, u64 *val)
4585 {
4586 struct drm_device *dev = data;
4587 struct drm_i915_private *dev_priv = dev->dev_private;
4588
4589 *val = dev_priv->gpu_error.test_irq_rings;
4590
4591 return 0;
4592 }
4593
4594 static int
4595 i915_ring_test_irq_set(void *data, u64 val)
4596 {
4597 struct drm_device *dev = data;
4598 struct drm_i915_private *dev_priv = dev->dev_private;
4599 int ret;
4600
4601 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4602
4603 /* Lock against concurrent debugfs callers */
4604 ret = mutex_lock_interruptible(&dev->struct_mutex);
4605 if (ret)
4606 return ret;
4607
4608 dev_priv->gpu_error.test_irq_rings = val;
4609 mutex_unlock(&dev->struct_mutex);
4610
4611 return 0;
4612 }
4613
4614 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4615 i915_ring_test_irq_get, i915_ring_test_irq_set,
4616 "0x%08llx\n");
4617
4618 #define DROP_UNBOUND 0x1
4619 #define DROP_BOUND 0x2
4620 #define DROP_RETIRE 0x4
4621 #define DROP_ACTIVE 0x8
4622 #define DROP_ALL (DROP_UNBOUND | \
4623 DROP_BOUND | \
4624 DROP_RETIRE | \
4625 DROP_ACTIVE)
4626 static int
4627 i915_drop_caches_get(void *data, u64 *val)
4628 {
4629 *val = DROP_ALL;
4630
4631 return 0;
4632 }
4633
4634 static int
4635 i915_drop_caches_set(void *data, u64 val)
4636 {
4637 struct drm_device *dev = data;
4638 struct drm_i915_private *dev_priv = dev->dev_private;
4639 int ret;
4640
4641 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4642
4643 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4644 * on ioctls on -EAGAIN. */
4645 ret = mutex_lock_interruptible(&dev->struct_mutex);
4646 if (ret)
4647 return ret;
4648
4649 if (val & DROP_ACTIVE) {
4650 ret = i915_gpu_idle(dev);
4651 if (ret)
4652 goto unlock;
4653 }
4654
4655 if (val & (DROP_RETIRE | DROP_ACTIVE))
4656 i915_gem_retire_requests(dev);
4657
4658 if (val & DROP_BOUND)
4659 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4660
4661 if (val & DROP_UNBOUND)
4662 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4663
4664 unlock:
4665 mutex_unlock(&dev->struct_mutex);
4666
4667 return ret;
4668 }
4669
4670 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4671 i915_drop_caches_get, i915_drop_caches_set,
4672 "0x%08llx\n");
4673
4674 static int
4675 i915_max_freq_get(void *data, u64 *val)
4676 {
4677 struct drm_device *dev = data;
4678 struct drm_i915_private *dev_priv = dev->dev_private;
4679 int ret;
4680
4681 if (INTEL_INFO(dev)->gen < 6)
4682 return -ENODEV;
4683
4684 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4685
4686 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4687 if (ret)
4688 return ret;
4689
4690 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4691 mutex_unlock(&dev_priv->rps.hw_lock);
4692
4693 return 0;
4694 }
4695
4696 static int
4697 i915_max_freq_set(void *data, u64 val)
4698 {
4699 struct drm_device *dev = data;
4700 struct drm_i915_private *dev_priv = dev->dev_private;
4701 u32 hw_max, hw_min;
4702 int ret;
4703
4704 if (INTEL_INFO(dev)->gen < 6)
4705 return -ENODEV;
4706
4707 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4708
4709 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4710
4711 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4712 if (ret)
4713 return ret;
4714
4715 /*
4716 * Turbo will still be enabled, but won't go above the set value.
4717 */
4718 val = intel_freq_opcode(dev_priv, val);
4719
4720 hw_max = dev_priv->rps.max_freq;
4721 hw_min = dev_priv->rps.min_freq;
4722
4723 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4724 mutex_unlock(&dev_priv->rps.hw_lock);
4725 return -EINVAL;
4726 }
4727
4728 dev_priv->rps.max_freq_softlimit = val;
4729
4730 intel_set_rps(dev, val);
4731
4732 mutex_unlock(&dev_priv->rps.hw_lock);
4733
4734 return 0;
4735 }
4736
4737 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4738 i915_max_freq_get, i915_max_freq_set,
4739 "%llu\n");
4740
4741 static int
4742 i915_min_freq_get(void *data, u64 *val)
4743 {
4744 struct drm_device *dev = data;
4745 struct drm_i915_private *dev_priv = dev->dev_private;
4746 int ret;
4747
4748 if (INTEL_INFO(dev)->gen < 6)
4749 return -ENODEV;
4750
4751 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4752
4753 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4754 if (ret)
4755 return ret;
4756
4757 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4758 mutex_unlock(&dev_priv->rps.hw_lock);
4759
4760 return 0;
4761 }
4762
4763 static int
4764 i915_min_freq_set(void *data, u64 val)
4765 {
4766 struct drm_device *dev = data;
4767 struct drm_i915_private *dev_priv = dev->dev_private;
4768 u32 hw_max, hw_min;
4769 int ret;
4770
4771 if (INTEL_INFO(dev)->gen < 6)
4772 return -ENODEV;
4773
4774 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4775
4776 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4777
4778 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4779 if (ret)
4780 return ret;
4781
4782 /*
4783 * Turbo will still be enabled, but won't go below the set value.
4784 */
4785 val = intel_freq_opcode(dev_priv, val);
4786
4787 hw_max = dev_priv->rps.max_freq;
4788 hw_min = dev_priv->rps.min_freq;
4789
4790 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
4791 mutex_unlock(&dev_priv->rps.hw_lock);
4792 return -EINVAL;
4793 }
4794
4795 dev_priv->rps.min_freq_softlimit = val;
4796
4797 intel_set_rps(dev, val);
4798
4799 mutex_unlock(&dev_priv->rps.hw_lock);
4800
4801 return 0;
4802 }
4803
4804 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4805 i915_min_freq_get, i915_min_freq_set,
4806 "%llu\n");
4807
4808 static int
4809 i915_cache_sharing_get(void *data, u64 *val)
4810 {
4811 struct drm_device *dev = data;
4812 struct drm_i915_private *dev_priv = dev->dev_private;
4813 u32 snpcr;
4814 int ret;
4815
4816 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4817 return -ENODEV;
4818
4819 ret = mutex_lock_interruptible(&dev->struct_mutex);
4820 if (ret)
4821 return ret;
4822 intel_runtime_pm_get(dev_priv);
4823
4824 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4825
4826 intel_runtime_pm_put(dev_priv);
4827 mutex_unlock(&dev_priv->dev->struct_mutex);
4828
4829 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
4830
4831 return 0;
4832 }
4833
4834 static int
4835 i915_cache_sharing_set(void *data, u64 val)
4836 {
4837 struct drm_device *dev = data;
4838 struct drm_i915_private *dev_priv = dev->dev_private;
4839 u32 snpcr;
4840
4841 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4842 return -ENODEV;
4843
4844 if (val > 3)
4845 return -EINVAL;
4846
4847 intel_runtime_pm_get(dev_priv);
4848 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
4849
4850 /* Update the cache sharing policy here as well */
4851 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4852 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4853 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4854 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4855
4856 intel_runtime_pm_put(dev_priv);
4857 return 0;
4858 }
4859
4860 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4861 i915_cache_sharing_get, i915_cache_sharing_set,
4862 "%llu\n");
4863
4864 struct sseu_dev_status {
4865 unsigned int slice_total;
4866 unsigned int subslice_total;
4867 unsigned int subslice_per_slice;
4868 unsigned int eu_total;
4869 unsigned int eu_per_subslice;
4870 };
4871
4872 static void cherryview_sseu_device_status(struct drm_device *dev,
4873 struct sseu_dev_status *stat)
4874 {
4875 struct drm_i915_private *dev_priv = dev->dev_private;
4876 const int ss_max = 2;
4877 int ss;
4878 u32 sig1[ss_max], sig2[ss_max];
4879
4880 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
4881 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
4882 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
4883 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
4884
4885 for (ss = 0; ss < ss_max; ss++) {
4886 unsigned int eu_cnt;
4887
4888 if (sig1[ss] & CHV_SS_PG_ENABLE)
4889 /* skip disabled subslice */
4890 continue;
4891
4892 stat->slice_total = 1;
4893 stat->subslice_per_slice++;
4894 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
4895 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
4896 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
4897 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
4898 stat->eu_total += eu_cnt;
4899 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
4900 }
4901 stat->subslice_total = stat->subslice_per_slice;
4902 }
4903
4904 static void gen9_sseu_device_status(struct drm_device *dev,
4905 struct sseu_dev_status *stat)
4906 {
4907 struct drm_i915_private *dev_priv = dev->dev_private;
4908 int s_max = 3, ss_max = 4;
4909 int s, ss;
4910 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
4911
4912 /* BXT has a single slice and at most 3 subslices. */
4913 if (IS_BROXTON(dev)) {
4914 s_max = 1;
4915 ss_max = 3;
4916 }
4917
4918 for (s = 0; s < s_max; s++) {
4919 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
4920 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
4921 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
4922 }
4923
4924 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4925 GEN9_PGCTL_SSA_EU19_ACK |
4926 GEN9_PGCTL_SSA_EU210_ACK |
4927 GEN9_PGCTL_SSA_EU311_ACK;
4928 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
4929 GEN9_PGCTL_SSB_EU19_ACK |
4930 GEN9_PGCTL_SSB_EU210_ACK |
4931 GEN9_PGCTL_SSB_EU311_ACK;
4932
4933 for (s = 0; s < s_max; s++) {
4934 unsigned int ss_cnt = 0;
4935
4936 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
4937 /* skip disabled slice */
4938 continue;
4939
4940 stat->slice_total++;
4941
4942 if (IS_SKYLAKE(dev))
4943 ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
4944
4945 for (ss = 0; ss < ss_max; ss++) {
4946 unsigned int eu_cnt;
4947
4948 if (IS_BROXTON(dev) &&
4949 !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
4950 /* skip disabled subslice */
4951 continue;
4952
4953 if (IS_BROXTON(dev))
4954 ss_cnt++;
4955
4956 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
4957 eu_mask[ss%2]);
4958 stat->eu_total += eu_cnt;
4959 stat->eu_per_subslice = max(stat->eu_per_subslice,
4960 eu_cnt);
4961 }
4962
4963 stat->subslice_total += ss_cnt;
4964 stat->subslice_per_slice = max(stat->subslice_per_slice,
4965 ss_cnt);
4966 }
4967 }
4968
4969 static int i915_sseu_status(struct seq_file *m, void *unused)
4970 {
4971 struct drm_info_node *node = (struct drm_info_node *) m->private;
4972 struct drm_device *dev = node->minor->dev;
4973 struct sseu_dev_status stat;
4974
4975 if ((INTEL_INFO(dev)->gen < 8) || IS_BROADWELL(dev))
4976 return -ENODEV;
4977
4978 seq_puts(m, "SSEU Device Info\n");
4979 seq_printf(m, " Available Slice Total: %u\n",
4980 INTEL_INFO(dev)->slice_total);
4981 seq_printf(m, " Available Subslice Total: %u\n",
4982 INTEL_INFO(dev)->subslice_total);
4983 seq_printf(m, " Available Subslice Per Slice: %u\n",
4984 INTEL_INFO(dev)->subslice_per_slice);
4985 seq_printf(m, " Available EU Total: %u\n",
4986 INTEL_INFO(dev)->eu_total);
4987 seq_printf(m, " Available EU Per Subslice: %u\n",
4988 INTEL_INFO(dev)->eu_per_subslice);
4989 seq_printf(m, " Has Slice Power Gating: %s\n",
4990 yesno(INTEL_INFO(dev)->has_slice_pg));
4991 seq_printf(m, " Has Subslice Power Gating: %s\n",
4992 yesno(INTEL_INFO(dev)->has_subslice_pg));
4993 seq_printf(m, " Has EU Power Gating: %s\n",
4994 yesno(INTEL_INFO(dev)->has_eu_pg));
4995
4996 seq_puts(m, "SSEU Device Status\n");
4997 memset(&stat, 0, sizeof(stat));
4998 if (IS_CHERRYVIEW(dev)) {
4999 cherryview_sseu_device_status(dev, &stat);
5000 } else if (INTEL_INFO(dev)->gen >= 9) {
5001 gen9_sseu_device_status(dev, &stat);
5002 }
5003 seq_printf(m, " Enabled Slice Total: %u\n",
5004 stat.slice_total);
5005 seq_printf(m, " Enabled Subslice Total: %u\n",
5006 stat.subslice_total);
5007 seq_printf(m, " Enabled Subslice Per Slice: %u\n",
5008 stat.subslice_per_slice);
5009 seq_printf(m, " Enabled EU Total: %u\n",
5010 stat.eu_total);
5011 seq_printf(m, " Enabled EU Per Subslice: %u\n",
5012 stat.eu_per_subslice);
5013
5014 return 0;
5015 }
5016
5017 static int i915_forcewake_open(struct inode *inode, struct file *file)
5018 {
5019 struct drm_device *dev = inode->i_private;
5020 struct drm_i915_private *dev_priv = dev->dev_private;
5021
5022 if (INTEL_INFO(dev)->gen < 6)
5023 return 0;
5024
5025 intel_runtime_pm_get(dev_priv);
5026 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5027
5028 return 0;
5029 }
5030
5031 static int i915_forcewake_release(struct inode *inode, struct file *file)
5032 {
5033 struct drm_device *dev = inode->i_private;
5034 struct drm_i915_private *dev_priv = dev->dev_private;
5035
5036 if (INTEL_INFO(dev)->gen < 6)
5037 return 0;
5038
5039 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5040 intel_runtime_pm_put(dev_priv);
5041
5042 return 0;
5043 }
5044
5045 static const struct file_operations i915_forcewake_fops = {
5046 .owner = THIS_MODULE,
5047 .open = i915_forcewake_open,
5048 .release = i915_forcewake_release,
5049 };
5050
5051 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5052 {
5053 struct drm_device *dev = minor->dev;
5054 struct dentry *ent;
5055
5056 ent = debugfs_create_file("i915_forcewake_user",
5057 S_IRUSR,
5058 root, dev,
5059 &i915_forcewake_fops);
5060 if (!ent)
5061 return -ENOMEM;
5062
5063 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5064 }
5065
5066 static int i915_debugfs_create(struct dentry *root,
5067 struct drm_minor *minor,
5068 const char *name,
5069 const struct file_operations *fops)
5070 {
5071 struct drm_device *dev = minor->dev;
5072 struct dentry *ent;
5073
5074 ent = debugfs_create_file(name,
5075 S_IRUGO | S_IWUSR,
5076 root, dev,
5077 fops);
5078 if (!ent)
5079 return -ENOMEM;
5080
5081 return drm_add_fake_info_node(minor, ent, fops);
5082 }
5083
5084 static const struct drm_info_list i915_debugfs_list[] = {
5085 {"i915_capabilities", i915_capabilities, 0},
5086 {"i915_gem_objects", i915_gem_object_info, 0},
5087 {"i915_gem_gtt", i915_gem_gtt_info, 0},
5088 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
5089 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
5090 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
5091 {"i915_gem_stolen", i915_gem_stolen_list_info },
5092 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5093 {"i915_gem_request", i915_gem_request_info, 0},
5094 {"i915_gem_seqno", i915_gem_seqno_info, 0},
5095 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5096 {"i915_gem_interrupt", i915_interrupt_info, 0},
5097 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5098 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5099 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5100 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5101 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5102 {"i915_guc_load_status", i915_guc_load_status_info, 0},
5103 {"i915_guc_log_dump", i915_guc_log_dump, 0},
5104 {"i915_frequency_info", i915_frequency_info, 0},
5105 {"i915_hangcheck_info", i915_hangcheck_info, 0},
5106 {"i915_drpc_info", i915_drpc_info, 0},
5107 {"i915_emon_status", i915_emon_status, 0},
5108 {"i915_ring_freq_table", i915_ring_freq_table, 0},
5109 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5110 {"i915_fbc_status", i915_fbc_status, 0},
5111 {"i915_ips_status", i915_ips_status, 0},
5112 {"i915_sr_status", i915_sr_status, 0},
5113 {"i915_opregion", i915_opregion, 0},
5114 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5115 {"i915_context_status", i915_context_status, 0},
5116 {"i915_dump_lrc", i915_dump_lrc, 0},
5117 {"i915_execlists", i915_execlists, 0},
5118 {"i915_forcewake_domains", i915_forcewake_domains, 0},
5119 {"i915_swizzle_info", i915_swizzle_info, 0},
5120 {"i915_ppgtt_info", i915_ppgtt_info, 0},
5121 {"i915_llc", i915_llc, 0},
5122 {"i915_edp_psr_status", i915_edp_psr_status, 0},
5123 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5124 {"i915_energy_uJ", i915_energy_uJ, 0},
5125 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5126 {"i915_power_domain_info", i915_power_domain_info, 0},
5127 {"i915_display_info", i915_display_info, 0},
5128 {"i915_semaphore_status", i915_semaphore_status, 0},
5129 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5130 {"i915_dp_mst_info", i915_dp_mst_info, 0},
5131 {"i915_wa_registers", i915_wa_registers, 0},
5132 {"i915_ddb_info", i915_ddb_info, 0},
5133 {"i915_sseu_status", i915_sseu_status, 0},
5134 {"i915_drrs_status", i915_drrs_status, 0},
5135 {"i915_rps_boost_info", i915_rps_boost_info, 0},
5136 };
5137 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5138
5139 static const struct i915_debugfs_files {
5140 const char *name;
5141 const struct file_operations *fops;
5142 } i915_debugfs_files[] = {
5143 {"i915_wedged", &i915_wedged_fops},
5144 {"i915_max_freq", &i915_max_freq_fops},
5145 {"i915_min_freq", &i915_min_freq_fops},
5146 {"i915_cache_sharing", &i915_cache_sharing_fops},
5147 {"i915_ring_stop", &i915_ring_stop_fops},
5148 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5149 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5150 {"i915_gem_drop_caches", &i915_drop_caches_fops},
5151 {"i915_error_state", &i915_error_state_fops},
5152 {"i915_next_seqno", &i915_next_seqno_fops},
5153 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5154 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5155 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5156 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5157 {"i915_fbc_false_color", &i915_fbc_fc_fops},
5158 {"i915_dp_test_data", &i915_displayport_test_data_fops},
5159 {"i915_dp_test_type", &i915_displayport_test_type_fops},
5160 {"i915_dp_test_active", &i915_displayport_test_active_fops}
5161 };
5162
5163 void intel_display_crc_init(struct drm_device *dev)
5164 {
5165 struct drm_i915_private *dev_priv = dev->dev_private;
5166 enum pipe pipe;
5167
5168 for_each_pipe(dev_priv, pipe) {
5169 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5170
5171 pipe_crc->opened = false;
5172 spin_lock_init(&pipe_crc->lock);
5173 init_waitqueue_head(&pipe_crc->wq);
5174 }
5175 }
5176
5177 int i915_debugfs_init(struct drm_minor *minor)
5178 {
5179 int ret, i;
5180
5181 ret = i915_forcewake_create(minor->debugfs_root, minor);
5182 if (ret)
5183 return ret;
5184
5185 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5186 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5187 if (ret)
5188 return ret;
5189 }
5190
5191 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5192 ret = i915_debugfs_create(minor->debugfs_root, minor,
5193 i915_debugfs_files[i].name,
5194 i915_debugfs_files[i].fops);
5195 if (ret)
5196 return ret;
5197 }
5198
5199 return drm_debugfs_create_files(i915_debugfs_list,
5200 I915_DEBUGFS_ENTRIES,
5201 minor->debugfs_root, minor);
5202 }
5203
5204 void i915_debugfs_cleanup(struct drm_minor *minor)
5205 {
5206 int i;
5207
5208 drm_debugfs_remove_files(i915_debugfs_list,
5209 I915_DEBUGFS_ENTRIES, minor);
5210
5211 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5212 1, minor);
5213
5214 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5215 struct drm_info_list *info_list =
5216 (struct drm_info_list *)&i915_pipe_crc_data[i];
5217
5218 drm_debugfs_remove_files(info_list, 1, minor);
5219 }
5220
5221 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5222 struct drm_info_list *info_list =
5223 (struct drm_info_list *) i915_debugfs_files[i].fops;
5224
5225 drm_debugfs_remove_files(info_list, 1, minor);
5226 }
5227 }
5228
5229 struct dpcd_block {
5230 /* DPCD dump start address. */
5231 unsigned int offset;
5232 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5233 unsigned int end;
5234 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5235 size_t size;
5236 /* Only valid for eDP. */
5237 bool edp;
5238 };
5239
5240 static const struct dpcd_block i915_dpcd_debug[] = {
5241 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5242 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5243 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5244 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5245 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5246 { .offset = DP_SET_POWER },
5247 { .offset = DP_EDP_DPCD_REV },
5248 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5249 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5250 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5251 };
5252
5253 static int i915_dpcd_show(struct seq_file *m, void *data)
5254 {
5255 struct drm_connector *connector = m->private;
5256 struct intel_dp *intel_dp =
5257 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5258 uint8_t buf[16];
5259 ssize_t err;
5260 int i;
5261
5262 if (connector->status != connector_status_connected)
5263 return -ENODEV;
5264
5265 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5266 const struct dpcd_block *b = &i915_dpcd_debug[i];
5267 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5268
5269 if (b->edp &&
5270 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5271 continue;
5272
5273 /* low tech for now */
5274 if (WARN_ON(size > sizeof(buf)))
5275 continue;
5276
5277 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5278 if (err <= 0) {
5279 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5280 size, b->offset, err);
5281 continue;
5282 }
5283
5284 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5285 }
5286
5287 return 0;
5288 }
5289
5290 static int i915_dpcd_open(struct inode *inode, struct file *file)
5291 {
5292 return single_open(file, i915_dpcd_show, inode->i_private);
5293 }
5294
5295 static const struct file_operations i915_dpcd_fops = {
5296 .owner = THIS_MODULE,
5297 .open = i915_dpcd_open,
5298 .read = seq_read,
5299 .llseek = seq_lseek,
5300 .release = single_release,
5301 };
5302
5303 /**
5304 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5305 * @connector: pointer to a registered drm_connector
5306 *
5307 * Cleanup will be done by drm_connector_unregister() through a call to
5308 * drm_debugfs_connector_remove().
5309 *
5310 * Returns 0 on success, negative error codes on error.
5311 */
5312 int i915_debugfs_connector_add(struct drm_connector *connector)
5313 {
5314 struct dentry *root = connector->debugfs_entry;
5315
5316 /* The connector must have been registered beforehands. */
5317 if (!root)
5318 return -ENODEV;
5319
5320 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5321 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5322 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5323 &i915_dpcd_fops);
5324
5325 return 0;
5326 }
Linux kernel - Deliverables
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