2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
49 static const char *yesno(int v
)
51 return v
? "yes" : "no";
54 /* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
57 drm_add_fake_info_node(struct drm_minor
*minor
,
61 struct drm_info_node
*node
;
63 node
= kmalloc(sizeof(*node
), GFP_KERNEL
);
71 node
->info_ent
= (void *) key
;
73 mutex_lock(&minor
->debugfs_lock
);
74 list_add(&node
->list
, &minor
->debugfs_list
);
75 mutex_unlock(&minor
->debugfs_lock
);
80 static int i915_capabilities(struct seq_file
*m
, void *data
)
82 struct drm_info_node
*node
= m
->private;
83 struct drm_device
*dev
= node
->minor
->dev
;
84 const struct intel_device_info
*info
= INTEL_INFO(dev
);
86 seq_printf(m
, "gen: %d\n", info
->gen
);
87 seq_printf(m
, "pch: %d\n", INTEL_PCH_TYPE(dev
));
88 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89 #define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG
, SEP_SEMICOLON
);
97 static const char *get_pin_flag(struct drm_i915_gem_object
*obj
)
99 if (i915_gem_obj_is_pinned(obj
))
105 static const char *get_tiling_flag(struct drm_i915_gem_object
*obj
)
107 switch (obj
->tiling_mode
) {
109 case I915_TILING_NONE
: return " ";
110 case I915_TILING_X
: return "X";
111 case I915_TILING_Y
: return "Y";
115 static inline const char *get_global_flag(struct drm_i915_gem_object
*obj
)
117 return i915_gem_obj_to_ggtt(obj
) ? "g" : " ";
121 describe_obj(struct seq_file
*m
, struct drm_i915_gem_object
*obj
)
123 struct i915_vma
*vma
;
126 seq_printf(m
, "%pK: %s%s%s %8zdKiB %02x %02x %x %x %x%s%s%s",
129 get_tiling_flag(obj
),
130 get_global_flag(obj
),
131 obj
->base
.size
/ 1024,
132 obj
->base
.read_domains
,
133 obj
->base
.write_domain
,
134 i915_gem_request_get_seqno(obj
->last_read_req
),
135 i915_gem_request_get_seqno(obj
->last_write_req
),
136 i915_gem_request_get_seqno(obj
->last_fenced_req
),
137 i915_cache_level_str(to_i915(obj
->base
.dev
), obj
->cache_level
),
138 obj
->dirty
? " dirty" : "",
139 obj
->madv
== I915_MADV_DONTNEED
? " purgeable" : "");
141 seq_printf(m
, " (name: %d)", obj
->base
.name
);
142 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
143 if (vma
->pin_count
> 0)
145 seq_printf(m
, " (pinned x %d)", pin_count
);
146 if (obj
->pin_display
)
147 seq_printf(m
, " (display)");
148 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
)
149 seq_printf(m
, " (fence: %d)", obj
->fence_reg
);
150 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
151 if (!i915_is_ggtt(vma
->vm
))
155 seq_printf(m
, "gtt offset: %08lx, size: %08lx, type: %u)",
156 vma
->node
.start
, vma
->node
.size
,
157 vma
->ggtt_view
.type
);
160 seq_printf(m
, " (stolen: %08lx)", obj
->stolen
->start
);
161 if (obj
->pin_mappable
|| obj
->fault_mappable
) {
163 if (obj
->pin_mappable
)
165 if (obj
->fault_mappable
)
168 seq_printf(m
, " (%s mappable)", s
);
170 if (obj
->last_read_req
!= NULL
)
171 seq_printf(m
, " (%s)",
172 i915_gem_request_get_ring(obj
->last_read_req
)->name
);
173 if (obj
->frontbuffer_bits
)
174 seq_printf(m
, " (frontbuffer: 0x%03x)", obj
->frontbuffer_bits
);
177 static void describe_ctx(struct seq_file
*m
, struct intel_context
*ctx
)
179 seq_putc(m
, ctx
->legacy_hw_ctx
.initialized
? 'I' : 'i');
180 seq_putc(m
, ctx
->remap_slice
? 'R' : 'r');
184 static int i915_gem_object_list_info(struct seq_file
*m
, void *data
)
186 struct drm_info_node
*node
= m
->private;
187 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
188 struct list_head
*head
;
189 struct drm_device
*dev
= node
->minor
->dev
;
190 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
191 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
192 struct i915_vma
*vma
;
193 size_t total_obj_size
, total_gtt_size
;
196 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
200 /* FIXME: the user of this interface might want more than just GGTT */
203 seq_puts(m
, "Active:\n");
204 head
= &vm
->active_list
;
207 seq_puts(m
, "Inactive:\n");
208 head
= &vm
->inactive_list
;
211 mutex_unlock(&dev
->struct_mutex
);
215 total_obj_size
= total_gtt_size
= count
= 0;
216 list_for_each_entry(vma
, head
, mm_list
) {
218 describe_obj(m
, vma
->obj
);
220 total_obj_size
+= vma
->obj
->base
.size
;
221 total_gtt_size
+= vma
->node
.size
;
224 mutex_unlock(&dev
->struct_mutex
);
226 seq_printf(m
, "Total %d objects, %zu bytes, %zu GTT size\n",
227 count
, total_obj_size
, total_gtt_size
);
231 static int obj_rank_by_stolen(void *priv
,
232 struct list_head
*A
, struct list_head
*B
)
234 struct drm_i915_gem_object
*a
=
235 container_of(A
, struct drm_i915_gem_object
, obj_exec_link
);
236 struct drm_i915_gem_object
*b
=
237 container_of(B
, struct drm_i915_gem_object
, obj_exec_link
);
239 return a
->stolen
->start
- b
->stolen
->start
;
242 static int i915_gem_stolen_list_info(struct seq_file
*m
, void *data
)
244 struct drm_info_node
*node
= m
->private;
245 struct drm_device
*dev
= node
->minor
->dev
;
246 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
247 struct drm_i915_gem_object
*obj
;
248 size_t total_obj_size
, total_gtt_size
;
252 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
256 total_obj_size
= total_gtt_size
= count
= 0;
257 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
258 if (obj
->stolen
== NULL
)
261 list_add(&obj
->obj_exec_link
, &stolen
);
263 total_obj_size
+= obj
->base
.size
;
264 total_gtt_size
+= i915_gem_obj_ggtt_size(obj
);
267 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
268 if (obj
->stolen
== NULL
)
271 list_add(&obj
->obj_exec_link
, &stolen
);
273 total_obj_size
+= obj
->base
.size
;
276 list_sort(NULL
, &stolen
, obj_rank_by_stolen
);
277 seq_puts(m
, "Stolen:\n");
278 while (!list_empty(&stolen
)) {
279 obj
= list_first_entry(&stolen
, typeof(*obj
), obj_exec_link
);
281 describe_obj(m
, obj
);
283 list_del_init(&obj
->obj_exec_link
);
285 mutex_unlock(&dev
->struct_mutex
);
287 seq_printf(m
, "Total %d objects, %zu bytes, %zu GTT size\n",
288 count
, total_obj_size
, total_gtt_size
);
292 #define count_objects(list, member) do { \
293 list_for_each_entry(obj, list, member) { \
294 size += i915_gem_obj_ggtt_size(obj); \
296 if (obj->map_and_fenceable) { \
297 mappable_size += i915_gem_obj_ggtt_size(obj); \
304 struct drm_i915_file_private
*file_priv
;
306 size_t total
, unbound
;
307 size_t global
, shared
;
308 size_t active
, inactive
;
311 static int per_file_stats(int id
, void *ptr
, void *data
)
313 struct drm_i915_gem_object
*obj
= ptr
;
314 struct file_stats
*stats
= data
;
315 struct i915_vma
*vma
;
318 stats
->total
+= obj
->base
.size
;
320 if (obj
->base
.name
|| obj
->base
.dma_buf
)
321 stats
->shared
+= obj
->base
.size
;
323 if (USES_FULL_PPGTT(obj
->base
.dev
)) {
324 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
325 struct i915_hw_ppgtt
*ppgtt
;
327 if (!drm_mm_node_allocated(&vma
->node
))
330 if (i915_is_ggtt(vma
->vm
)) {
331 stats
->global
+= obj
->base
.size
;
335 ppgtt
= container_of(vma
->vm
, struct i915_hw_ppgtt
, base
);
336 if (ppgtt
->file_priv
!= stats
->file_priv
)
339 if (obj
->active
) /* XXX per-vma statistic */
340 stats
->active
+= obj
->base
.size
;
342 stats
->inactive
+= obj
->base
.size
;
347 if (i915_gem_obj_ggtt_bound(obj
)) {
348 stats
->global
+= obj
->base
.size
;
350 stats
->active
+= obj
->base
.size
;
352 stats
->inactive
+= obj
->base
.size
;
357 if (!list_empty(&obj
->global_list
))
358 stats
->unbound
+= obj
->base
.size
;
363 #define print_file_stats(m, name, stats) \
364 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n", \
374 static void print_batch_pool_stats(struct seq_file
*m
,
375 struct drm_i915_private
*dev_priv
)
377 struct drm_i915_gem_object
*obj
;
378 struct file_stats stats
;
380 memset(&stats
, 0, sizeof(stats
));
382 list_for_each_entry(obj
,
383 &dev_priv
->mm
.batch_pool
.cache_list
,
385 per_file_stats(0, obj
, &stats
);
387 print_file_stats(m
, "batch pool", stats
);
390 #define count_vmas(list, member) do { \
391 list_for_each_entry(vma, list, member) { \
392 size += i915_gem_obj_ggtt_size(vma->obj); \
394 if (vma->obj->map_and_fenceable) { \
395 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
401 static int i915_gem_object_info(struct seq_file
*m
, void* data
)
403 struct drm_info_node
*node
= m
->private;
404 struct drm_device
*dev
= node
->minor
->dev
;
405 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
406 u32 count
, mappable_count
, purgeable_count
;
407 size_t size
, mappable_size
, purgeable_size
;
408 struct drm_i915_gem_object
*obj
;
409 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
410 struct drm_file
*file
;
411 struct i915_vma
*vma
;
414 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
418 seq_printf(m
, "%u objects, %zu bytes\n",
419 dev_priv
->mm
.object_count
,
420 dev_priv
->mm
.object_memory
);
422 size
= count
= mappable_size
= mappable_count
= 0;
423 count_objects(&dev_priv
->mm
.bound_list
, global_list
);
424 seq_printf(m
, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
425 count
, mappable_count
, size
, mappable_size
);
427 size
= count
= mappable_size
= mappable_count
= 0;
428 count_vmas(&vm
->active_list
, mm_list
);
429 seq_printf(m
, " %u [%u] active objects, %zu [%zu] bytes\n",
430 count
, mappable_count
, size
, mappable_size
);
432 size
= count
= mappable_size
= mappable_count
= 0;
433 count_vmas(&vm
->inactive_list
, mm_list
);
434 seq_printf(m
, " %u [%u] inactive objects, %zu [%zu] bytes\n",
435 count
, mappable_count
, size
, mappable_size
);
437 size
= count
= purgeable_size
= purgeable_count
= 0;
438 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
439 size
+= obj
->base
.size
, ++count
;
440 if (obj
->madv
== I915_MADV_DONTNEED
)
441 purgeable_size
+= obj
->base
.size
, ++purgeable_count
;
443 seq_printf(m
, "%u unbound objects, %zu bytes\n", count
, size
);
445 size
= count
= mappable_size
= mappable_count
= 0;
446 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
447 if (obj
->fault_mappable
) {
448 size
+= i915_gem_obj_ggtt_size(obj
);
451 if (obj
->pin_mappable
) {
452 mappable_size
+= i915_gem_obj_ggtt_size(obj
);
455 if (obj
->madv
== I915_MADV_DONTNEED
) {
456 purgeable_size
+= obj
->base
.size
;
460 seq_printf(m
, "%u purgeable objects, %zu bytes\n",
461 purgeable_count
, purgeable_size
);
462 seq_printf(m
, "%u pinned mappable objects, %zu bytes\n",
463 mappable_count
, mappable_size
);
464 seq_printf(m
, "%u fault mappable objects, %zu bytes\n",
467 seq_printf(m
, "%zu [%lu] gtt total\n",
468 dev_priv
->gtt
.base
.total
,
469 dev_priv
->gtt
.mappable_end
- dev_priv
->gtt
.base
.start
);
472 print_batch_pool_stats(m
, dev_priv
);
475 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
476 struct file_stats stats
;
477 struct task_struct
*task
;
479 memset(&stats
, 0, sizeof(stats
));
480 stats
.file_priv
= file
->driver_priv
;
481 spin_lock(&file
->table_lock
);
482 idr_for_each(&file
->object_idr
, per_file_stats
, &stats
);
483 spin_unlock(&file
->table_lock
);
485 * Although we have a valid reference on file->pid, that does
486 * not guarantee that the task_struct who called get_pid() is
487 * still alive (e.g. get_pid(current) => fork() => exit()).
488 * Therefore, we need to protect this ->comm access using RCU.
491 task
= pid_task(file
->pid
, PIDTYPE_PID
);
492 print_file_stats(m
, task
? task
->comm
: "<unknown>", stats
);
496 mutex_unlock(&dev
->struct_mutex
);
501 static int i915_gem_gtt_info(struct seq_file
*m
, void *data
)
503 struct drm_info_node
*node
= m
->private;
504 struct drm_device
*dev
= node
->minor
->dev
;
505 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
506 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
507 struct drm_i915_gem_object
*obj
;
508 size_t total_obj_size
, total_gtt_size
;
511 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
515 total_obj_size
= total_gtt_size
= count
= 0;
516 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
517 if (list
== PINNED_LIST
&& !i915_gem_obj_is_pinned(obj
))
521 describe_obj(m
, obj
);
523 total_obj_size
+= obj
->base
.size
;
524 total_gtt_size
+= i915_gem_obj_ggtt_size(obj
);
528 mutex_unlock(&dev
->struct_mutex
);
530 seq_printf(m
, "Total %d objects, %zu bytes, %zu GTT size\n",
531 count
, total_obj_size
, total_gtt_size
);
536 static int i915_gem_pageflip_info(struct seq_file
*m
, void *data
)
538 struct drm_info_node
*node
= m
->private;
539 struct drm_device
*dev
= node
->minor
->dev
;
540 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
541 struct intel_crtc
*crtc
;
544 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
548 for_each_intel_crtc(dev
, crtc
) {
549 const char pipe
= pipe_name(crtc
->pipe
);
550 const char plane
= plane_name(crtc
->plane
);
551 struct intel_unpin_work
*work
;
553 spin_lock_irq(&dev
->event_lock
);
554 work
= crtc
->unpin_work
;
556 seq_printf(m
, "No flip due on pipe %c (plane %c)\n",
561 if (atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
562 seq_printf(m
, "Flip queued on pipe %c (plane %c)\n",
565 seq_printf(m
, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
568 if (work
->flip_queued_req
) {
569 struct intel_engine_cs
*ring
=
570 i915_gem_request_get_ring(work
->flip_queued_req
);
572 seq_printf(m
, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
574 i915_gem_request_get_seqno(work
->flip_queued_req
),
575 dev_priv
->next_seqno
,
576 ring
->get_seqno(ring
, true),
577 i915_gem_request_completed(work
->flip_queued_req
, true));
579 seq_printf(m
, "Flip not associated with any ring\n");
580 seq_printf(m
, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
581 work
->flip_queued_vblank
,
582 work
->flip_ready_vblank
,
583 drm_crtc_vblank_count(&crtc
->base
));
584 if (work
->enable_stall_check
)
585 seq_puts(m
, "Stall check enabled, ");
587 seq_puts(m
, "Stall check waiting for page flip ioctl, ");
588 seq_printf(m
, "%d prepares\n", atomic_read(&work
->pending
));
590 if (INTEL_INFO(dev
)->gen
>= 4)
591 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(crtc
->plane
)));
593 addr
= I915_READ(DSPADDR(crtc
->plane
));
594 seq_printf(m
, "Current scanout address 0x%08x\n", addr
);
596 if (work
->pending_flip_obj
) {
597 seq_printf(m
, "New framebuffer address 0x%08lx\n", (long)work
->gtt_offset
);
598 seq_printf(m
, "MMIO update completed? %d\n", addr
== work
->gtt_offset
);
601 spin_unlock_irq(&dev
->event_lock
);
604 mutex_unlock(&dev
->struct_mutex
);
609 static int i915_gem_batch_pool_info(struct seq_file
*m
, void *data
)
611 struct drm_info_node
*node
= m
->private;
612 struct drm_device
*dev
= node
->minor
->dev
;
613 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
614 struct drm_i915_gem_object
*obj
;
618 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
622 seq_puts(m
, "cache:\n");
623 list_for_each_entry(obj
,
624 &dev_priv
->mm
.batch_pool
.cache_list
,
627 describe_obj(m
, obj
);
632 seq_printf(m
, "total: %d\n", count
);
634 mutex_unlock(&dev
->struct_mutex
);
639 static int i915_gem_request_info(struct seq_file
*m
, void *data
)
641 struct drm_info_node
*node
= m
->private;
642 struct drm_device
*dev
= node
->minor
->dev
;
643 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
644 struct intel_engine_cs
*ring
;
645 struct drm_i915_gem_request
*gem_request
;
648 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
653 for_each_ring(ring
, dev_priv
, i
) {
654 if (list_empty(&ring
->request_list
))
657 seq_printf(m
, "%s requests:\n", ring
->name
);
658 list_for_each_entry(gem_request
,
661 seq_printf(m
, " %x @ %d\n",
663 (int) (jiffies
- gem_request
->emitted_jiffies
));
667 mutex_unlock(&dev
->struct_mutex
);
670 seq_puts(m
, "No requests\n");
675 static void i915_ring_seqno_info(struct seq_file
*m
,
676 struct intel_engine_cs
*ring
)
678 if (ring
->get_seqno
) {
679 seq_printf(m
, "Current sequence (%s): %x\n",
680 ring
->name
, ring
->get_seqno(ring
, false));
684 static int i915_gem_seqno_info(struct seq_file
*m
, void *data
)
686 struct drm_info_node
*node
= m
->private;
687 struct drm_device
*dev
= node
->minor
->dev
;
688 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
689 struct intel_engine_cs
*ring
;
692 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
695 intel_runtime_pm_get(dev_priv
);
697 for_each_ring(ring
, dev_priv
, i
)
698 i915_ring_seqno_info(m
, ring
);
700 intel_runtime_pm_put(dev_priv
);
701 mutex_unlock(&dev
->struct_mutex
);
707 static int i915_interrupt_info(struct seq_file
*m
, void *data
)
709 struct drm_info_node
*node
= m
->private;
710 struct drm_device
*dev
= node
->minor
->dev
;
711 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
712 struct intel_engine_cs
*ring
;
715 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
718 intel_runtime_pm_get(dev_priv
);
720 if (IS_CHERRYVIEW(dev
)) {
721 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
722 I915_READ(GEN8_MASTER_IRQ
));
724 seq_printf(m
, "Display IER:\t%08x\n",
726 seq_printf(m
, "Display IIR:\t%08x\n",
728 seq_printf(m
, "Display IIR_RW:\t%08x\n",
729 I915_READ(VLV_IIR_RW
));
730 seq_printf(m
, "Display IMR:\t%08x\n",
732 for_each_pipe(dev_priv
, pipe
)
733 seq_printf(m
, "Pipe %c stat:\t%08x\n",
735 I915_READ(PIPESTAT(pipe
)));
737 seq_printf(m
, "Port hotplug:\t%08x\n",
738 I915_READ(PORT_HOTPLUG_EN
));
739 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
740 I915_READ(VLV_DPFLIPSTAT
));
741 seq_printf(m
, "DPINVGTT:\t%08x\n",
742 I915_READ(DPINVGTT
));
744 for (i
= 0; i
< 4; i
++) {
745 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
746 i
, I915_READ(GEN8_GT_IMR(i
)));
747 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
748 i
, I915_READ(GEN8_GT_IIR(i
)));
749 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
750 i
, I915_READ(GEN8_GT_IER(i
)));
753 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
754 I915_READ(GEN8_PCU_IMR
));
755 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
756 I915_READ(GEN8_PCU_IIR
));
757 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
758 I915_READ(GEN8_PCU_IER
));
759 } else if (INTEL_INFO(dev
)->gen
>= 8) {
760 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
761 I915_READ(GEN8_MASTER_IRQ
));
763 for (i
= 0; i
< 4; i
++) {
764 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
765 i
, I915_READ(GEN8_GT_IMR(i
)));
766 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
767 i
, I915_READ(GEN8_GT_IIR(i
)));
768 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
769 i
, I915_READ(GEN8_GT_IER(i
)));
772 for_each_pipe(dev_priv
, pipe
) {
773 if (!intel_display_power_is_enabled(dev_priv
,
774 POWER_DOMAIN_PIPE(pipe
))) {
775 seq_printf(m
, "Pipe %c power disabled\n",
779 seq_printf(m
, "Pipe %c IMR:\t%08x\n",
781 I915_READ(GEN8_DE_PIPE_IMR(pipe
)));
782 seq_printf(m
, "Pipe %c IIR:\t%08x\n",
784 I915_READ(GEN8_DE_PIPE_IIR(pipe
)));
785 seq_printf(m
, "Pipe %c IER:\t%08x\n",
787 I915_READ(GEN8_DE_PIPE_IER(pipe
)));
790 seq_printf(m
, "Display Engine port interrupt mask:\t%08x\n",
791 I915_READ(GEN8_DE_PORT_IMR
));
792 seq_printf(m
, "Display Engine port interrupt identity:\t%08x\n",
793 I915_READ(GEN8_DE_PORT_IIR
));
794 seq_printf(m
, "Display Engine port interrupt enable:\t%08x\n",
795 I915_READ(GEN8_DE_PORT_IER
));
797 seq_printf(m
, "Display Engine misc interrupt mask:\t%08x\n",
798 I915_READ(GEN8_DE_MISC_IMR
));
799 seq_printf(m
, "Display Engine misc interrupt identity:\t%08x\n",
800 I915_READ(GEN8_DE_MISC_IIR
));
801 seq_printf(m
, "Display Engine misc interrupt enable:\t%08x\n",
802 I915_READ(GEN8_DE_MISC_IER
));
804 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
805 I915_READ(GEN8_PCU_IMR
));
806 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
807 I915_READ(GEN8_PCU_IIR
));
808 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
809 I915_READ(GEN8_PCU_IER
));
810 } else if (IS_VALLEYVIEW(dev
)) {
811 seq_printf(m
, "Display IER:\t%08x\n",
813 seq_printf(m
, "Display IIR:\t%08x\n",
815 seq_printf(m
, "Display IIR_RW:\t%08x\n",
816 I915_READ(VLV_IIR_RW
));
817 seq_printf(m
, "Display IMR:\t%08x\n",
819 for_each_pipe(dev_priv
, pipe
)
820 seq_printf(m
, "Pipe %c stat:\t%08x\n",
822 I915_READ(PIPESTAT(pipe
)));
824 seq_printf(m
, "Master IER:\t%08x\n",
825 I915_READ(VLV_MASTER_IER
));
827 seq_printf(m
, "Render IER:\t%08x\n",
829 seq_printf(m
, "Render IIR:\t%08x\n",
831 seq_printf(m
, "Render IMR:\t%08x\n",
834 seq_printf(m
, "PM IER:\t\t%08x\n",
835 I915_READ(GEN6_PMIER
));
836 seq_printf(m
, "PM IIR:\t\t%08x\n",
837 I915_READ(GEN6_PMIIR
));
838 seq_printf(m
, "PM IMR:\t\t%08x\n",
839 I915_READ(GEN6_PMIMR
));
841 seq_printf(m
, "Port hotplug:\t%08x\n",
842 I915_READ(PORT_HOTPLUG_EN
));
843 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
844 I915_READ(VLV_DPFLIPSTAT
));
845 seq_printf(m
, "DPINVGTT:\t%08x\n",
846 I915_READ(DPINVGTT
));
848 } else if (!HAS_PCH_SPLIT(dev
)) {
849 seq_printf(m
, "Interrupt enable: %08x\n",
851 seq_printf(m
, "Interrupt identity: %08x\n",
853 seq_printf(m
, "Interrupt mask: %08x\n",
855 for_each_pipe(dev_priv
, pipe
)
856 seq_printf(m
, "Pipe %c stat: %08x\n",
858 I915_READ(PIPESTAT(pipe
)));
860 seq_printf(m
, "North Display Interrupt enable: %08x\n",
862 seq_printf(m
, "North Display Interrupt identity: %08x\n",
864 seq_printf(m
, "North Display Interrupt mask: %08x\n",
866 seq_printf(m
, "South Display Interrupt enable: %08x\n",
868 seq_printf(m
, "South Display Interrupt identity: %08x\n",
870 seq_printf(m
, "South Display Interrupt mask: %08x\n",
872 seq_printf(m
, "Graphics Interrupt enable: %08x\n",
874 seq_printf(m
, "Graphics Interrupt identity: %08x\n",
876 seq_printf(m
, "Graphics Interrupt mask: %08x\n",
879 for_each_ring(ring
, dev_priv
, i
) {
880 if (INTEL_INFO(dev
)->gen
>= 6) {
882 "Graphics Interrupt mask (%s): %08x\n",
883 ring
->name
, I915_READ_IMR(ring
));
885 i915_ring_seqno_info(m
, ring
);
887 intel_runtime_pm_put(dev_priv
);
888 mutex_unlock(&dev
->struct_mutex
);
893 static int i915_gem_fence_regs_info(struct seq_file
*m
, void *data
)
895 struct drm_info_node
*node
= m
->private;
896 struct drm_device
*dev
= node
->minor
->dev
;
897 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
900 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
904 seq_printf(m
, "Reserved fences = %d\n", dev_priv
->fence_reg_start
);
905 seq_printf(m
, "Total fences = %d\n", dev_priv
->num_fence_regs
);
906 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
907 struct drm_i915_gem_object
*obj
= dev_priv
->fence_regs
[i
].obj
;
909 seq_printf(m
, "Fence %d, pin count = %d, object = ",
910 i
, dev_priv
->fence_regs
[i
].pin_count
);
912 seq_puts(m
, "unused");
914 describe_obj(m
, obj
);
918 mutex_unlock(&dev
->struct_mutex
);
922 static int i915_hws_info(struct seq_file
*m
, void *data
)
924 struct drm_info_node
*node
= m
->private;
925 struct drm_device
*dev
= node
->minor
->dev
;
926 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
927 struct intel_engine_cs
*ring
;
931 ring
= &dev_priv
->ring
[(uintptr_t)node
->info_ent
->data
];
932 hws
= ring
->status_page
.page_addr
;
936 for (i
= 0; i
< 4096 / sizeof(u32
) / 4; i
+= 4) {
937 seq_printf(m
, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
939 hws
[i
], hws
[i
+ 1], hws
[i
+ 2], hws
[i
+ 3]);
945 i915_error_state_write(struct file
*filp
,
946 const char __user
*ubuf
,
950 struct i915_error_state_file_priv
*error_priv
= filp
->private_data
;
951 struct drm_device
*dev
= error_priv
->dev
;
954 DRM_DEBUG_DRIVER("Resetting error state\n");
956 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
960 i915_destroy_error_state(dev
);
961 mutex_unlock(&dev
->struct_mutex
);
966 static int i915_error_state_open(struct inode
*inode
, struct file
*file
)
968 struct drm_device
*dev
= inode
->i_private
;
969 struct i915_error_state_file_priv
*error_priv
;
971 error_priv
= kzalloc(sizeof(*error_priv
), GFP_KERNEL
);
975 error_priv
->dev
= dev
;
977 i915_error_state_get(dev
, error_priv
);
979 file
->private_data
= error_priv
;
984 static int i915_error_state_release(struct inode
*inode
, struct file
*file
)
986 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
988 i915_error_state_put(error_priv
);
994 static ssize_t
i915_error_state_read(struct file
*file
, char __user
*userbuf
,
995 size_t count
, loff_t
*pos
)
997 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
998 struct drm_i915_error_state_buf error_str
;
1000 ssize_t ret_count
= 0;
1003 ret
= i915_error_state_buf_init(&error_str
, to_i915(error_priv
->dev
), count
, *pos
);
1007 ret
= i915_error_state_to_str(&error_str
, error_priv
);
1011 ret_count
= simple_read_from_buffer(userbuf
, count
, &tmp_pos
,
1018 *pos
= error_str
.start
+ ret_count
;
1020 i915_error_state_buf_release(&error_str
);
1021 return ret
?: ret_count
;
1024 static const struct file_operations i915_error_state_fops
= {
1025 .owner
= THIS_MODULE
,
1026 .open
= i915_error_state_open
,
1027 .read
= i915_error_state_read
,
1028 .write
= i915_error_state_write
,
1029 .llseek
= default_llseek
,
1030 .release
= i915_error_state_release
,
1034 i915_next_seqno_get(void *data
, u64
*val
)
1036 struct drm_device
*dev
= data
;
1037 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1040 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1044 *val
= dev_priv
->next_seqno
;
1045 mutex_unlock(&dev
->struct_mutex
);
1051 i915_next_seqno_set(void *data
, u64 val
)
1053 struct drm_device
*dev
= data
;
1056 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1060 ret
= i915_gem_set_seqno(dev
, val
);
1061 mutex_unlock(&dev
->struct_mutex
);
1066 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops
,
1067 i915_next_seqno_get
, i915_next_seqno_set
,
1070 static int i915_frequency_info(struct seq_file
*m
, void *unused
)
1072 struct drm_info_node
*node
= m
->private;
1073 struct drm_device
*dev
= node
->minor
->dev
;
1074 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1077 intel_runtime_pm_get(dev_priv
);
1079 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
1082 u16 rgvswctl
= I915_READ16(MEMSWCTL
);
1083 u16 rgvstat
= I915_READ16(MEMSTAT_ILK
);
1085 seq_printf(m
, "Requested P-state: %d\n", (rgvswctl
>> 8) & 0xf);
1086 seq_printf(m
, "Requested VID: %d\n", rgvswctl
& 0x3f);
1087 seq_printf(m
, "Current VID: %d\n", (rgvstat
& MEMSTAT_VID_MASK
) >>
1089 seq_printf(m
, "Current P-state: %d\n",
1090 (rgvstat
& MEMSTAT_PSTATE_MASK
) >> MEMSTAT_PSTATE_SHIFT
);
1091 } else if (IS_GEN6(dev
) || (IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) ||
1092 IS_BROADWELL(dev
)) {
1093 u32 gt_perf_status
= I915_READ(GEN6_GT_PERF_STATUS
);
1094 u32 rp_state_limits
= I915_READ(GEN6_RP_STATE_LIMITS
);
1095 u32 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
1096 u32 rpmodectl
, rpinclimit
, rpdeclimit
;
1097 u32 rpstat
, cagf
, reqf
;
1098 u32 rpupei
, rpcurup
, rpprevup
;
1099 u32 rpdownei
, rpcurdown
, rpprevdown
;
1100 u32 pm_ier
, pm_imr
, pm_isr
, pm_iir
, pm_mask
;
1103 /* RPSTAT1 is in the GT power well */
1104 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1108 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
1110 reqf
= I915_READ(GEN6_RPNSWREQ
);
1111 reqf
&= ~GEN6_TURBO_DISABLE
;
1112 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1116 reqf
= intel_gpu_freq(dev_priv
, reqf
);
1118 rpmodectl
= I915_READ(GEN6_RP_CONTROL
);
1119 rpinclimit
= I915_READ(GEN6_RP_UP_THRESHOLD
);
1120 rpdeclimit
= I915_READ(GEN6_RP_DOWN_THRESHOLD
);
1122 rpstat
= I915_READ(GEN6_RPSTAT1
);
1123 rpupei
= I915_READ(GEN6_RP_CUR_UP_EI
);
1124 rpcurup
= I915_READ(GEN6_RP_CUR_UP
);
1125 rpprevup
= I915_READ(GEN6_RP_PREV_UP
);
1126 rpdownei
= I915_READ(GEN6_RP_CUR_DOWN_EI
);
1127 rpcurdown
= I915_READ(GEN6_RP_CUR_DOWN
);
1128 rpprevdown
= I915_READ(GEN6_RP_PREV_DOWN
);
1129 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1130 cagf
= (rpstat
& HSW_CAGF_MASK
) >> HSW_CAGF_SHIFT
;
1132 cagf
= (rpstat
& GEN6_CAGF_MASK
) >> GEN6_CAGF_SHIFT
;
1133 cagf
= intel_gpu_freq(dev_priv
, cagf
);
1135 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
1136 mutex_unlock(&dev
->struct_mutex
);
1138 if (IS_GEN6(dev
) || IS_GEN7(dev
)) {
1139 pm_ier
= I915_READ(GEN6_PMIER
);
1140 pm_imr
= I915_READ(GEN6_PMIMR
);
1141 pm_isr
= I915_READ(GEN6_PMISR
);
1142 pm_iir
= I915_READ(GEN6_PMIIR
);
1143 pm_mask
= I915_READ(GEN6_PMINTRMSK
);
1145 pm_ier
= I915_READ(GEN8_GT_IER(2));
1146 pm_imr
= I915_READ(GEN8_GT_IMR(2));
1147 pm_isr
= I915_READ(GEN8_GT_ISR(2));
1148 pm_iir
= I915_READ(GEN8_GT_IIR(2));
1149 pm_mask
= I915_READ(GEN6_PMINTRMSK
);
1151 seq_printf(m
, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1152 pm_ier
, pm_imr
, pm_isr
, pm_iir
, pm_mask
);
1153 seq_printf(m
, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status
);
1154 seq_printf(m
, "Render p-state ratio: %d\n",
1155 (gt_perf_status
& 0xff00) >> 8);
1156 seq_printf(m
, "Render p-state VID: %d\n",
1157 gt_perf_status
& 0xff);
1158 seq_printf(m
, "Render p-state limit: %d\n",
1159 rp_state_limits
& 0xff);
1160 seq_printf(m
, "RPSTAT1: 0x%08x\n", rpstat
);
1161 seq_printf(m
, "RPMODECTL: 0x%08x\n", rpmodectl
);
1162 seq_printf(m
, "RPINCLIMIT: 0x%08x\n", rpinclimit
);
1163 seq_printf(m
, "RPDECLIMIT: 0x%08x\n", rpdeclimit
);
1164 seq_printf(m
, "RPNSWREQ: %dMHz\n", reqf
);
1165 seq_printf(m
, "CAGF: %dMHz\n", cagf
);
1166 seq_printf(m
, "RP CUR UP EI: %dus\n", rpupei
&
1167 GEN6_CURICONT_MASK
);
1168 seq_printf(m
, "RP CUR UP: %dus\n", rpcurup
&
1169 GEN6_CURBSYTAVG_MASK
);
1170 seq_printf(m
, "RP PREV UP: %dus\n", rpprevup
&
1171 GEN6_CURBSYTAVG_MASK
);
1172 seq_printf(m
, "RP CUR DOWN EI: %dus\n", rpdownei
&
1174 seq_printf(m
, "RP CUR DOWN: %dus\n", rpcurdown
&
1175 GEN6_CURBSYTAVG_MASK
);
1176 seq_printf(m
, "RP PREV DOWN: %dus\n", rpprevdown
&
1177 GEN6_CURBSYTAVG_MASK
);
1179 max_freq
= (rp_state_cap
& 0xff0000) >> 16;
1180 seq_printf(m
, "Lowest (RPN) frequency: %dMHz\n",
1181 intel_gpu_freq(dev_priv
, max_freq
));
1183 max_freq
= (rp_state_cap
& 0xff00) >> 8;
1184 seq_printf(m
, "Nominal (RP1) frequency: %dMHz\n",
1185 intel_gpu_freq(dev_priv
, max_freq
));
1187 max_freq
= rp_state_cap
& 0xff;
1188 seq_printf(m
, "Max non-overclocked (RP0) frequency: %dMHz\n",
1189 intel_gpu_freq(dev_priv
, max_freq
));
1191 seq_printf(m
, "Max overclocked frequency: %dMHz\n",
1192 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1193 } else if (IS_VALLEYVIEW(dev
)) {
1196 mutex_lock(&dev_priv
->rps
.hw_lock
);
1197 freq_sts
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
1198 seq_printf(m
, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts
);
1199 seq_printf(m
, "DDR freq: %d MHz\n", dev_priv
->mem_freq
);
1201 seq_printf(m
, "max GPU freq: %d MHz\n",
1202 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1204 seq_printf(m
, "min GPU freq: %d MHz\n",
1205 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
));
1208 "efficient (RPe) frequency: %d MHz\n",
1209 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
));
1211 seq_printf(m
, "current GPU freq: %d MHz\n",
1212 intel_gpu_freq(dev_priv
, (freq_sts
>> 8) & 0xff));
1213 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1215 seq_puts(m
, "no P-state info available\n");
1219 intel_runtime_pm_put(dev_priv
);
1223 static int i915_hangcheck_info(struct seq_file
*m
, void *unused
)
1225 struct drm_info_node
*node
= m
->private;
1226 struct drm_i915_private
*dev_priv
= to_i915(node
->minor
->dev
);
1227 struct intel_engine_cs
*ring
;
1230 if (!i915
.enable_hangcheck
) {
1231 seq_printf(m
, "Hangcheck disabled\n");
1235 if (delayed_work_pending(&dev_priv
->gpu_error
.hangcheck_work
)) {
1236 seq_printf(m
, "Hangcheck active, fires in %dms\n",
1237 jiffies_to_msecs(dev_priv
->gpu_error
.hangcheck_work
.timer
.expires
-
1240 seq_printf(m
, "Hangcheck inactive\n");
1242 for_each_ring(ring
, dev_priv
, i
) {
1243 seq_printf(m
, "%s:\n", ring
->name
);
1244 seq_printf(m
, "\tseqno = %x [current %x]\n",
1245 ring
->hangcheck
.seqno
, ring
->get_seqno(ring
, false));
1246 seq_printf(m
, "\taction = %d\n", ring
->hangcheck
.action
);
1247 seq_printf(m
, "\tscore = %d\n", ring
->hangcheck
.score
);
1248 seq_printf(m
, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1249 (long long)ring
->hangcheck
.acthd
,
1250 (long long)intel_ring_get_active_head(ring
));
1251 seq_printf(m
, "\tmax ACTHD = 0x%08llx\n",
1252 (long long)ring
->hangcheck
.max_acthd
);
1258 static int ironlake_drpc_info(struct seq_file
*m
)
1260 struct drm_info_node
*node
= m
->private;
1261 struct drm_device
*dev
= node
->minor
->dev
;
1262 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1263 u32 rgvmodectl
, rstdbyctl
;
1267 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1270 intel_runtime_pm_get(dev_priv
);
1272 rgvmodectl
= I915_READ(MEMMODECTL
);
1273 rstdbyctl
= I915_READ(RSTDBYCTL
);
1274 crstandvid
= I915_READ16(CRSTANDVID
);
1276 intel_runtime_pm_put(dev_priv
);
1277 mutex_unlock(&dev
->struct_mutex
);
1279 seq_printf(m
, "HD boost: %s\n", (rgvmodectl
& MEMMODE_BOOST_EN
) ?
1281 seq_printf(m
, "Boost freq: %d\n",
1282 (rgvmodectl
& MEMMODE_BOOST_FREQ_MASK
) >>
1283 MEMMODE_BOOST_FREQ_SHIFT
);
1284 seq_printf(m
, "HW control enabled: %s\n",
1285 rgvmodectl
& MEMMODE_HWIDLE_EN
? "yes" : "no");
1286 seq_printf(m
, "SW control enabled: %s\n",
1287 rgvmodectl
& MEMMODE_SWMODE_EN
? "yes" : "no");
1288 seq_printf(m
, "Gated voltage change: %s\n",
1289 rgvmodectl
& MEMMODE_RCLK_GATE
? "yes" : "no");
1290 seq_printf(m
, "Starting frequency: P%d\n",
1291 (rgvmodectl
& MEMMODE_FSTART_MASK
) >> MEMMODE_FSTART_SHIFT
);
1292 seq_printf(m
, "Max P-state: P%d\n",
1293 (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
);
1294 seq_printf(m
, "Min P-state: P%d\n", (rgvmodectl
& MEMMODE_FMIN_MASK
));
1295 seq_printf(m
, "RS1 VID: %d\n", (crstandvid
& 0x3f));
1296 seq_printf(m
, "RS2 VID: %d\n", ((crstandvid
>> 8) & 0x3f));
1297 seq_printf(m
, "Render standby enabled: %s\n",
1298 (rstdbyctl
& RCX_SW_EXIT
) ? "no" : "yes");
1299 seq_puts(m
, "Current RS state: ");
1300 switch (rstdbyctl
& RSX_STATUS_MASK
) {
1302 seq_puts(m
, "on\n");
1304 case RSX_STATUS_RC1
:
1305 seq_puts(m
, "RC1\n");
1307 case RSX_STATUS_RC1E
:
1308 seq_puts(m
, "RC1E\n");
1310 case RSX_STATUS_RS1
:
1311 seq_puts(m
, "RS1\n");
1313 case RSX_STATUS_RS2
:
1314 seq_puts(m
, "RS2 (RC6)\n");
1316 case RSX_STATUS_RS3
:
1317 seq_puts(m
, "RC3 (RC6+)\n");
1320 seq_puts(m
, "unknown\n");
1327 static int i915_forcewake_domains(struct seq_file
*m
, void *data
)
1329 struct drm_info_node
*node
= m
->private;
1330 struct drm_device
*dev
= node
->minor
->dev
;
1331 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1332 struct intel_uncore_forcewake_domain
*fw_domain
;
1335 spin_lock_irq(&dev_priv
->uncore
.lock
);
1336 for_each_fw_domain(fw_domain
, dev_priv
, i
) {
1337 seq_printf(m
, "%s.wake_count = %u\n",
1338 intel_uncore_forcewake_domain_to_str(i
),
1339 fw_domain
->wake_count
);
1341 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1346 static int vlv_drpc_info(struct seq_file
*m
)
1348 struct drm_info_node
*node
= m
->private;
1349 struct drm_device
*dev
= node
->minor
->dev
;
1350 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1351 u32 rpmodectl1
, rcctl1
, pw_status
;
1353 intel_runtime_pm_get(dev_priv
);
1355 pw_status
= I915_READ(VLV_GTLC_PW_STATUS
);
1356 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1357 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1359 intel_runtime_pm_put(dev_priv
);
1361 seq_printf(m
, "Video Turbo Mode: %s\n",
1362 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1363 seq_printf(m
, "Turbo enabled: %s\n",
1364 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1365 seq_printf(m
, "HW control enabled: %s\n",
1366 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1367 seq_printf(m
, "SW control enabled: %s\n",
1368 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1369 GEN6_RP_MEDIA_SW_MODE
));
1370 seq_printf(m
, "RC6 Enabled: %s\n",
1371 yesno(rcctl1
& (GEN7_RC_CTL_TO_MODE
|
1372 GEN6_RC_CTL_EI_MODE(1))));
1373 seq_printf(m
, "Render Power Well: %s\n",
1374 (pw_status
& VLV_GTLC_PW_RENDER_STATUS_MASK
) ? "Up" : "Down");
1375 seq_printf(m
, "Media Power Well: %s\n",
1376 (pw_status
& VLV_GTLC_PW_MEDIA_STATUS_MASK
) ? "Up" : "Down");
1378 seq_printf(m
, "Render RC6 residency since boot: %u\n",
1379 I915_READ(VLV_GT_RENDER_RC6
));
1380 seq_printf(m
, "Media RC6 residency since boot: %u\n",
1381 I915_READ(VLV_GT_MEDIA_RC6
));
1383 return i915_forcewake_domains(m
, NULL
);
1386 static int gen6_drpc_info(struct seq_file
*m
)
1388 struct drm_info_node
*node
= m
->private;
1389 struct drm_device
*dev
= node
->minor
->dev
;
1390 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1391 u32 rpmodectl1
, gt_core_status
, rcctl1
, rc6vids
= 0;
1392 unsigned forcewake_count
;
1395 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1398 intel_runtime_pm_get(dev_priv
);
1400 spin_lock_irq(&dev_priv
->uncore
.lock
);
1401 forcewake_count
= dev_priv
->uncore
.fw_domain
[FW_DOMAIN_ID_RENDER
].wake_count
;
1402 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1404 if (forcewake_count
) {
1405 seq_puts(m
, "RC information inaccurate because somebody "
1406 "holds a forcewake reference \n");
1408 /* NB: we cannot use forcewake, else we read the wrong values */
1409 while (count
++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK
) & 1))
1411 seq_printf(m
, "RC information accurate: %s\n", yesno(count
< 51));
1414 gt_core_status
= readl(dev_priv
->regs
+ GEN6_GT_CORE_STATUS
);
1415 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS
, gt_core_status
, 4, true);
1417 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1418 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1419 mutex_unlock(&dev
->struct_mutex
);
1420 mutex_lock(&dev_priv
->rps
.hw_lock
);
1421 sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
1422 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1424 intel_runtime_pm_put(dev_priv
);
1426 seq_printf(m
, "Video Turbo Mode: %s\n",
1427 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1428 seq_printf(m
, "HW control enabled: %s\n",
1429 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1430 seq_printf(m
, "SW control enabled: %s\n",
1431 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1432 GEN6_RP_MEDIA_SW_MODE
));
1433 seq_printf(m
, "RC1e Enabled: %s\n",
1434 yesno(rcctl1
& GEN6_RC_CTL_RC1e_ENABLE
));
1435 seq_printf(m
, "RC6 Enabled: %s\n",
1436 yesno(rcctl1
& GEN6_RC_CTL_RC6_ENABLE
));
1437 seq_printf(m
, "Deep RC6 Enabled: %s\n",
1438 yesno(rcctl1
& GEN6_RC_CTL_RC6p_ENABLE
));
1439 seq_printf(m
, "Deepest RC6 Enabled: %s\n",
1440 yesno(rcctl1
& GEN6_RC_CTL_RC6pp_ENABLE
));
1441 seq_puts(m
, "Current RC state: ");
1442 switch (gt_core_status
& GEN6_RCn_MASK
) {
1444 if (gt_core_status
& GEN6_CORE_CPD_STATE_MASK
)
1445 seq_puts(m
, "Core Power Down\n");
1447 seq_puts(m
, "on\n");
1450 seq_puts(m
, "RC3\n");
1453 seq_puts(m
, "RC6\n");
1456 seq_puts(m
, "RC7\n");
1459 seq_puts(m
, "Unknown\n");
1463 seq_printf(m
, "Core Power Down: %s\n",
1464 yesno(gt_core_status
& GEN6_CORE_CPD_STATE_MASK
));
1466 /* Not exactly sure what this is */
1467 seq_printf(m
, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1468 I915_READ(GEN6_GT_GFX_RC6_LOCKED
));
1469 seq_printf(m
, "RC6 residency since boot: %u\n",
1470 I915_READ(GEN6_GT_GFX_RC6
));
1471 seq_printf(m
, "RC6+ residency since boot: %u\n",
1472 I915_READ(GEN6_GT_GFX_RC6p
));
1473 seq_printf(m
, "RC6++ residency since boot: %u\n",
1474 I915_READ(GEN6_GT_GFX_RC6pp
));
1476 seq_printf(m
, "RC6 voltage: %dmV\n",
1477 GEN6_DECODE_RC6_VID(((rc6vids
>> 0) & 0xff)));
1478 seq_printf(m
, "RC6+ voltage: %dmV\n",
1479 GEN6_DECODE_RC6_VID(((rc6vids
>> 8) & 0xff)));
1480 seq_printf(m
, "RC6++ voltage: %dmV\n",
1481 GEN6_DECODE_RC6_VID(((rc6vids
>> 16) & 0xff)));
1485 static int i915_drpc_info(struct seq_file
*m
, void *unused
)
1487 struct drm_info_node
*node
= m
->private;
1488 struct drm_device
*dev
= node
->minor
->dev
;
1490 if (IS_VALLEYVIEW(dev
))
1491 return vlv_drpc_info(m
);
1492 else if (INTEL_INFO(dev
)->gen
>= 6)
1493 return gen6_drpc_info(m
);
1495 return ironlake_drpc_info(m
);
1498 static int i915_fbc_status(struct seq_file
*m
, void *unused
)
1500 struct drm_info_node
*node
= m
->private;
1501 struct drm_device
*dev
= node
->minor
->dev
;
1502 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1504 if (!HAS_FBC(dev
)) {
1505 seq_puts(m
, "FBC unsupported on this chipset\n");
1509 intel_runtime_pm_get(dev_priv
);
1511 if (intel_fbc_enabled(dev
)) {
1512 seq_puts(m
, "FBC enabled\n");
1514 seq_puts(m
, "FBC disabled: ");
1515 switch (dev_priv
->fbc
.no_fbc_reason
) {
1517 seq_puts(m
, "FBC actived, but currently disabled in hardware");
1519 case FBC_UNSUPPORTED
:
1520 seq_puts(m
, "unsupported by this chipset");
1523 seq_puts(m
, "no outputs");
1525 case FBC_STOLEN_TOO_SMALL
:
1526 seq_puts(m
, "not enough stolen memory");
1528 case FBC_UNSUPPORTED_MODE
:
1529 seq_puts(m
, "mode not supported");
1531 case FBC_MODE_TOO_LARGE
:
1532 seq_puts(m
, "mode too large");
1535 seq_puts(m
, "FBC unsupported on plane");
1538 seq_puts(m
, "scanout buffer not tiled");
1540 case FBC_MULTIPLE_PIPES
:
1541 seq_puts(m
, "multiple pipes are enabled");
1543 case FBC_MODULE_PARAM
:
1544 seq_puts(m
, "disabled per module param (default off)");
1546 case FBC_CHIP_DEFAULT
:
1547 seq_puts(m
, "disabled per chip default");
1550 seq_puts(m
, "unknown reason");
1555 intel_runtime_pm_put(dev_priv
);
1560 static int i915_fbc_fc_get(void *data
, u64
*val
)
1562 struct drm_device
*dev
= data
;
1563 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1565 if (INTEL_INFO(dev
)->gen
< 7 || !HAS_FBC(dev
))
1568 drm_modeset_lock_all(dev
);
1569 *val
= dev_priv
->fbc
.false_color
;
1570 drm_modeset_unlock_all(dev
);
1575 static int i915_fbc_fc_set(void *data
, u64 val
)
1577 struct drm_device
*dev
= data
;
1578 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1581 if (INTEL_INFO(dev
)->gen
< 7 || !HAS_FBC(dev
))
1584 drm_modeset_lock_all(dev
);
1586 reg
= I915_READ(ILK_DPFC_CONTROL
);
1587 dev_priv
->fbc
.false_color
= val
;
1589 I915_WRITE(ILK_DPFC_CONTROL
, val
?
1590 (reg
| FBC_CTL_FALSE_COLOR
) :
1591 (reg
& ~FBC_CTL_FALSE_COLOR
));
1593 drm_modeset_unlock_all(dev
);
1597 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops
,
1598 i915_fbc_fc_get
, i915_fbc_fc_set
,
1601 static int i915_ips_status(struct seq_file
*m
, void *unused
)
1603 struct drm_info_node
*node
= m
->private;
1604 struct drm_device
*dev
= node
->minor
->dev
;
1605 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1607 if (!HAS_IPS(dev
)) {
1608 seq_puts(m
, "not supported\n");
1612 intel_runtime_pm_get(dev_priv
);
1614 seq_printf(m
, "Enabled by kernel parameter: %s\n",
1615 yesno(i915
.enable_ips
));
1617 if (INTEL_INFO(dev
)->gen
>= 8) {
1618 seq_puts(m
, "Currently: unknown\n");
1620 if (I915_READ(IPS_CTL
) & IPS_ENABLE
)
1621 seq_puts(m
, "Currently: enabled\n");
1623 seq_puts(m
, "Currently: disabled\n");
1626 intel_runtime_pm_put(dev_priv
);
1631 static int i915_sr_status(struct seq_file
*m
, void *unused
)
1633 struct drm_info_node
*node
= m
->private;
1634 struct drm_device
*dev
= node
->minor
->dev
;
1635 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1636 bool sr_enabled
= false;
1638 intel_runtime_pm_get(dev_priv
);
1640 if (HAS_PCH_SPLIT(dev
))
1641 sr_enabled
= I915_READ(WM1_LP_ILK
) & WM1_LP_SR_EN
;
1642 else if (IS_CRESTLINE(dev
) || IS_I945G(dev
) || IS_I945GM(dev
))
1643 sr_enabled
= I915_READ(FW_BLC_SELF
) & FW_BLC_SELF_EN
;
1644 else if (IS_I915GM(dev
))
1645 sr_enabled
= I915_READ(INSTPM
) & INSTPM_SELF_EN
;
1646 else if (IS_PINEVIEW(dev
))
1647 sr_enabled
= I915_READ(DSPFW3
) & PINEVIEW_SELF_REFRESH_EN
;
1649 intel_runtime_pm_put(dev_priv
);
1651 seq_printf(m
, "self-refresh: %s\n",
1652 sr_enabled
? "enabled" : "disabled");
1657 static int i915_emon_status(struct seq_file
*m
, void *unused
)
1659 struct drm_info_node
*node
= m
->private;
1660 struct drm_device
*dev
= node
->minor
->dev
;
1661 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1662 unsigned long temp
, chipset
, gfx
;
1668 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1672 temp
= i915_mch_val(dev_priv
);
1673 chipset
= i915_chipset_val(dev_priv
);
1674 gfx
= i915_gfx_val(dev_priv
);
1675 mutex_unlock(&dev
->struct_mutex
);
1677 seq_printf(m
, "GMCH temp: %ld\n", temp
);
1678 seq_printf(m
, "Chipset power: %ld\n", chipset
);
1679 seq_printf(m
, "GFX power: %ld\n", gfx
);
1680 seq_printf(m
, "Total power: %ld\n", chipset
+ gfx
);
1685 static int i915_ring_freq_table(struct seq_file
*m
, void *unused
)
1687 struct drm_info_node
*node
= m
->private;
1688 struct drm_device
*dev
= node
->minor
->dev
;
1689 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1691 int gpu_freq
, ia_freq
;
1693 if (!(IS_GEN6(dev
) || IS_GEN7(dev
))) {
1694 seq_puts(m
, "unsupported on this chipset\n");
1698 intel_runtime_pm_get(dev_priv
);
1700 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
1702 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
1706 seq_puts(m
, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1708 for (gpu_freq
= dev_priv
->rps
.min_freq_softlimit
;
1709 gpu_freq
<= dev_priv
->rps
.max_freq_softlimit
;
1712 sandybridge_pcode_read(dev_priv
,
1713 GEN6_PCODE_READ_MIN_FREQ_TABLE
,
1715 seq_printf(m
, "%d\t\t%d\t\t\t\t%d\n",
1716 intel_gpu_freq(dev_priv
, gpu_freq
),
1717 ((ia_freq
>> 0) & 0xff) * 100,
1718 ((ia_freq
>> 8) & 0xff) * 100);
1721 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1724 intel_runtime_pm_put(dev_priv
);
1728 static int i915_opregion(struct seq_file
*m
, void *unused
)
1730 struct drm_info_node
*node
= m
->private;
1731 struct drm_device
*dev
= node
->minor
->dev
;
1732 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1733 struct intel_opregion
*opregion
= &dev_priv
->opregion
;
1734 void *data
= kmalloc(OPREGION_SIZE
, GFP_KERNEL
);
1740 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1744 if (opregion
->header
) {
1745 memcpy_fromio(data
, opregion
->header
, OPREGION_SIZE
);
1746 seq_write(m
, data
, OPREGION_SIZE
);
1749 mutex_unlock(&dev
->struct_mutex
);
1756 static int i915_gem_framebuffer_info(struct seq_file
*m
, void *data
)
1758 struct drm_info_node
*node
= m
->private;
1759 struct drm_device
*dev
= node
->minor
->dev
;
1760 struct intel_fbdev
*ifbdev
= NULL
;
1761 struct intel_framebuffer
*fb
;
1763 #ifdef CONFIG_DRM_I915_FBDEV
1764 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1766 ifbdev
= dev_priv
->fbdev
;
1767 fb
= to_intel_framebuffer(ifbdev
->helper
.fb
);
1769 seq_printf(m
, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1773 fb
->base
.bits_per_pixel
,
1774 fb
->base
.modifier
[0],
1775 atomic_read(&fb
->base
.refcount
.refcount
));
1776 describe_obj(m
, fb
->obj
);
1780 mutex_lock(&dev
->mode_config
.fb_lock
);
1781 list_for_each_entry(fb
, &dev
->mode_config
.fb_list
, base
.head
) {
1782 if (ifbdev
&& &fb
->base
== ifbdev
->helper
.fb
)
1785 seq_printf(m
, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1789 fb
->base
.bits_per_pixel
,
1790 fb
->base
.modifier
[0],
1791 atomic_read(&fb
->base
.refcount
.refcount
));
1792 describe_obj(m
, fb
->obj
);
1795 mutex_unlock(&dev
->mode_config
.fb_lock
);
1800 static void describe_ctx_ringbuf(struct seq_file
*m
,
1801 struct intel_ringbuffer
*ringbuf
)
1803 seq_printf(m
, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1804 ringbuf
->space
, ringbuf
->head
, ringbuf
->tail
,
1805 ringbuf
->last_retired_head
);
1808 static int i915_context_status(struct seq_file
*m
, void *unused
)
1810 struct drm_info_node
*node
= m
->private;
1811 struct drm_device
*dev
= node
->minor
->dev
;
1812 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1813 struct intel_engine_cs
*ring
;
1814 struct intel_context
*ctx
;
1817 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1821 if (dev_priv
->ips
.pwrctx
) {
1822 seq_puts(m
, "power context ");
1823 describe_obj(m
, dev_priv
->ips
.pwrctx
);
1827 if (dev_priv
->ips
.renderctx
) {
1828 seq_puts(m
, "render context ");
1829 describe_obj(m
, dev_priv
->ips
.renderctx
);
1833 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
1834 if (!i915
.enable_execlists
&&
1835 ctx
->legacy_hw_ctx
.rcs_state
== NULL
)
1838 seq_puts(m
, "HW context ");
1839 describe_ctx(m
, ctx
);
1840 for_each_ring(ring
, dev_priv
, i
) {
1841 if (ring
->default_context
== ctx
)
1842 seq_printf(m
, "(default context %s) ",
1846 if (i915
.enable_execlists
) {
1848 for_each_ring(ring
, dev_priv
, i
) {
1849 struct drm_i915_gem_object
*ctx_obj
=
1850 ctx
->engine
[i
].state
;
1851 struct intel_ringbuffer
*ringbuf
=
1852 ctx
->engine
[i
].ringbuf
;
1854 seq_printf(m
, "%s: ", ring
->name
);
1856 describe_obj(m
, ctx_obj
);
1858 describe_ctx_ringbuf(m
, ringbuf
);
1862 describe_obj(m
, ctx
->legacy_hw_ctx
.rcs_state
);
1868 mutex_unlock(&dev
->struct_mutex
);
1873 static void i915_dump_lrc_obj(struct seq_file
*m
,
1874 struct intel_engine_cs
*ring
,
1875 struct drm_i915_gem_object
*ctx_obj
)
1878 uint32_t *reg_state
;
1880 unsigned long ggtt_offset
= 0;
1882 if (ctx_obj
== NULL
) {
1883 seq_printf(m
, "Context on %s with no gem object\n",
1888 seq_printf(m
, "CONTEXT: %s %u\n", ring
->name
,
1889 intel_execlists_ctx_id(ctx_obj
));
1891 if (!i915_gem_obj_ggtt_bound(ctx_obj
))
1892 seq_puts(m
, "\tNot bound in GGTT\n");
1894 ggtt_offset
= i915_gem_obj_ggtt_offset(ctx_obj
);
1896 if (i915_gem_object_get_pages(ctx_obj
)) {
1897 seq_puts(m
, "\tFailed to get pages for context object\n");
1901 page
= i915_gem_object_get_page(ctx_obj
, 1);
1902 if (!WARN_ON(page
== NULL
)) {
1903 reg_state
= kmap_atomic(page
);
1905 for (j
= 0; j
< 0x600 / sizeof(u32
) / 4; j
+= 4) {
1906 seq_printf(m
, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1907 ggtt_offset
+ 4096 + (j
* 4),
1908 reg_state
[j
], reg_state
[j
+ 1],
1909 reg_state
[j
+ 2], reg_state
[j
+ 3]);
1911 kunmap_atomic(reg_state
);
1917 static int i915_dump_lrc(struct seq_file
*m
, void *unused
)
1919 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1920 struct drm_device
*dev
= node
->minor
->dev
;
1921 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1922 struct intel_engine_cs
*ring
;
1923 struct intel_context
*ctx
;
1926 if (!i915
.enable_execlists
) {
1927 seq_printf(m
, "Logical Ring Contexts are disabled\n");
1931 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1935 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
1936 for_each_ring(ring
, dev_priv
, i
) {
1937 if (ring
->default_context
!= ctx
)
1938 i915_dump_lrc_obj(m
, ring
,
1939 ctx
->engine
[i
].state
);
1943 mutex_unlock(&dev
->struct_mutex
);
1948 static int i915_execlists(struct seq_file
*m
, void *data
)
1950 struct drm_info_node
*node
= (struct drm_info_node
*)m
->private;
1951 struct drm_device
*dev
= node
->minor
->dev
;
1952 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1953 struct intel_engine_cs
*ring
;
1959 struct list_head
*cursor
;
1963 if (!i915
.enable_execlists
) {
1964 seq_puts(m
, "Logical Ring Contexts are disabled\n");
1968 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1972 intel_runtime_pm_get(dev_priv
);
1974 for_each_ring(ring
, dev_priv
, ring_id
) {
1975 struct drm_i915_gem_request
*head_req
= NULL
;
1977 unsigned long flags
;
1979 seq_printf(m
, "%s\n", ring
->name
);
1981 status
= I915_READ(RING_EXECLIST_STATUS(ring
));
1982 ctx_id
= I915_READ(RING_EXECLIST_STATUS(ring
) + 4);
1983 seq_printf(m
, "\tExeclist status: 0x%08X, context: %u\n",
1986 status_pointer
= I915_READ(RING_CONTEXT_STATUS_PTR(ring
));
1987 seq_printf(m
, "\tStatus pointer: 0x%08X\n", status_pointer
);
1989 read_pointer
= ring
->next_context_status_buffer
;
1990 write_pointer
= status_pointer
& 0x07;
1991 if (read_pointer
> write_pointer
)
1993 seq_printf(m
, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
1994 read_pointer
, write_pointer
);
1996 for (i
= 0; i
< 6; i
++) {
1997 status
= I915_READ(RING_CONTEXT_STATUS_BUF(ring
) + 8*i
);
1998 ctx_id
= I915_READ(RING_CONTEXT_STATUS_BUF(ring
) + 8*i
+ 4);
2000 seq_printf(m
, "\tStatus buffer %d: 0x%08X, context: %u\n",
2004 spin_lock_irqsave(&ring
->execlist_lock
, flags
);
2005 list_for_each(cursor
, &ring
->execlist_queue
)
2007 head_req
= list_first_entry_or_null(&ring
->execlist_queue
,
2008 struct drm_i915_gem_request
, execlist_link
);
2009 spin_unlock_irqrestore(&ring
->execlist_lock
, flags
);
2011 seq_printf(m
, "\t%d requests in queue\n", count
);
2013 struct drm_i915_gem_object
*ctx_obj
;
2015 ctx_obj
= head_req
->ctx
->engine
[ring_id
].state
;
2016 seq_printf(m
, "\tHead request id: %u\n",
2017 intel_execlists_ctx_id(ctx_obj
));
2018 seq_printf(m
, "\tHead request tail: %u\n",
2025 intel_runtime_pm_put(dev_priv
);
2026 mutex_unlock(&dev
->struct_mutex
);
2031 static const char *swizzle_string(unsigned swizzle
)
2034 case I915_BIT_6_SWIZZLE_NONE
:
2036 case I915_BIT_6_SWIZZLE_9
:
2038 case I915_BIT_6_SWIZZLE_9_10
:
2039 return "bit9/bit10";
2040 case I915_BIT_6_SWIZZLE_9_11
:
2041 return "bit9/bit11";
2042 case I915_BIT_6_SWIZZLE_9_10_11
:
2043 return "bit9/bit10/bit11";
2044 case I915_BIT_6_SWIZZLE_9_17
:
2045 return "bit9/bit17";
2046 case I915_BIT_6_SWIZZLE_9_10_17
:
2047 return "bit9/bit10/bit17";
2048 case I915_BIT_6_SWIZZLE_UNKNOWN
:
2055 static int i915_swizzle_info(struct seq_file
*m
, void *data
)
2057 struct drm_info_node
*node
= m
->private;
2058 struct drm_device
*dev
= node
->minor
->dev
;
2059 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2062 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2065 intel_runtime_pm_get(dev_priv
);
2067 seq_printf(m
, "bit6 swizzle for X-tiling = %s\n",
2068 swizzle_string(dev_priv
->mm
.bit_6_swizzle_x
));
2069 seq_printf(m
, "bit6 swizzle for Y-tiling = %s\n",
2070 swizzle_string(dev_priv
->mm
.bit_6_swizzle_y
));
2072 if (IS_GEN3(dev
) || IS_GEN4(dev
)) {
2073 seq_printf(m
, "DDC = 0x%08x\n",
2075 seq_printf(m
, "DDC2 = 0x%08x\n",
2077 seq_printf(m
, "C0DRB3 = 0x%04x\n",
2078 I915_READ16(C0DRB3
));
2079 seq_printf(m
, "C1DRB3 = 0x%04x\n",
2080 I915_READ16(C1DRB3
));
2081 } else if (INTEL_INFO(dev
)->gen
>= 6) {
2082 seq_printf(m
, "MAD_DIMM_C0 = 0x%08x\n",
2083 I915_READ(MAD_DIMM_C0
));
2084 seq_printf(m
, "MAD_DIMM_C1 = 0x%08x\n",
2085 I915_READ(MAD_DIMM_C1
));
2086 seq_printf(m
, "MAD_DIMM_C2 = 0x%08x\n",
2087 I915_READ(MAD_DIMM_C2
));
2088 seq_printf(m
, "TILECTL = 0x%08x\n",
2089 I915_READ(TILECTL
));
2090 if (INTEL_INFO(dev
)->gen
>= 8)
2091 seq_printf(m
, "GAMTARBMODE = 0x%08x\n",
2092 I915_READ(GAMTARBMODE
));
2094 seq_printf(m
, "ARB_MODE = 0x%08x\n",
2095 I915_READ(ARB_MODE
));
2096 seq_printf(m
, "DISP_ARB_CTL = 0x%08x\n",
2097 I915_READ(DISP_ARB_CTL
));
2100 if (dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
)
2101 seq_puts(m
, "L-shaped memory detected\n");
2103 intel_runtime_pm_put(dev_priv
);
2104 mutex_unlock(&dev
->struct_mutex
);
2109 static int per_file_ctx(int id
, void *ptr
, void *data
)
2111 struct intel_context
*ctx
= ptr
;
2112 struct seq_file
*m
= data
;
2113 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
2116 seq_printf(m
, " no ppgtt for context %d\n",
2121 if (i915_gem_context_is_default(ctx
))
2122 seq_puts(m
, " default context:\n");
2124 seq_printf(m
, " context %d:\n", ctx
->user_handle
);
2125 ppgtt
->debug_dump(ppgtt
, m
);
2130 static void gen8_ppgtt_info(struct seq_file
*m
, struct drm_device
*dev
)
2132 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2133 struct intel_engine_cs
*ring
;
2134 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2140 seq_printf(m
, "Page directories: %d\n", ppgtt
->num_pd_pages
);
2141 seq_printf(m
, "Page tables: %d\n", ppgtt
->num_pd_entries
);
2142 for_each_ring(ring
, dev_priv
, unused
) {
2143 seq_printf(m
, "%s\n", ring
->name
);
2144 for (i
= 0; i
< 4; i
++) {
2145 u32 offset
= 0x270 + i
* 8;
2146 u64 pdp
= I915_READ(ring
->mmio_base
+ offset
+ 4);
2148 pdp
|= I915_READ(ring
->mmio_base
+ offset
);
2149 seq_printf(m
, "\tPDP%d 0x%016llx\n", i
, pdp
);
2154 static void gen6_ppgtt_info(struct seq_file
*m
, struct drm_device
*dev
)
2156 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2157 struct intel_engine_cs
*ring
;
2158 struct drm_file
*file
;
2161 if (INTEL_INFO(dev
)->gen
== 6)
2162 seq_printf(m
, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE
));
2164 for_each_ring(ring
, dev_priv
, i
) {
2165 seq_printf(m
, "%s\n", ring
->name
);
2166 if (INTEL_INFO(dev
)->gen
== 7)
2167 seq_printf(m
, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring
)));
2168 seq_printf(m
, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring
)));
2169 seq_printf(m
, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring
)));
2170 seq_printf(m
, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring
)));
2172 if (dev_priv
->mm
.aliasing_ppgtt
) {
2173 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2175 seq_puts(m
, "aliasing PPGTT:\n");
2176 seq_printf(m
, "pd gtt offset: 0x%08x\n", ppgtt
->pd_offset
);
2178 ppgtt
->debug_dump(ppgtt
, m
);
2181 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
2182 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2184 seq_printf(m
, "proc: %s\n",
2185 get_pid_task(file
->pid
, PIDTYPE_PID
)->comm
);
2186 idr_for_each(&file_priv
->context_idr
, per_file_ctx
, m
);
2188 seq_printf(m
, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK
));
2191 static int i915_ppgtt_info(struct seq_file
*m
, void *data
)
2193 struct drm_info_node
*node
= m
->private;
2194 struct drm_device
*dev
= node
->minor
->dev
;
2195 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2197 int ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2200 intel_runtime_pm_get(dev_priv
);
2202 if (INTEL_INFO(dev
)->gen
>= 8)
2203 gen8_ppgtt_info(m
, dev
);
2204 else if (INTEL_INFO(dev
)->gen
>= 6)
2205 gen6_ppgtt_info(m
, dev
);
2207 intel_runtime_pm_put(dev_priv
);
2208 mutex_unlock(&dev
->struct_mutex
);
2213 static int i915_llc(struct seq_file
*m
, void *data
)
2215 struct drm_info_node
*node
= m
->private;
2216 struct drm_device
*dev
= node
->minor
->dev
;
2217 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2219 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2220 seq_printf(m
, "LLC: %s\n", yesno(HAS_LLC(dev
)));
2221 seq_printf(m
, "eLLC: %zuMB\n", dev_priv
->ellc_size
);
2226 static int i915_edp_psr_status(struct seq_file
*m
, void *data
)
2228 struct drm_info_node
*node
= m
->private;
2229 struct drm_device
*dev
= node
->minor
->dev
;
2230 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2234 bool enabled
= false;
2236 intel_runtime_pm_get(dev_priv
);
2238 mutex_lock(&dev_priv
->psr
.lock
);
2239 seq_printf(m
, "Sink_Support: %s\n", yesno(dev_priv
->psr
.sink_support
));
2240 seq_printf(m
, "Source_OK: %s\n", yesno(dev_priv
->psr
.source_ok
));
2241 seq_printf(m
, "Enabled: %s\n", yesno((bool)dev_priv
->psr
.enabled
));
2242 seq_printf(m
, "Active: %s\n", yesno(dev_priv
->psr
.active
));
2243 seq_printf(m
, "Busy frontbuffer bits: 0x%03x\n",
2244 dev_priv
->psr
.busy_frontbuffer_bits
);
2245 seq_printf(m
, "Re-enable work scheduled: %s\n",
2246 yesno(work_busy(&dev_priv
->psr
.work
.work
)));
2250 enabled
= I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
;
2252 for_each_pipe(dev_priv
, pipe
) {
2253 stat
[pipe
] = I915_READ(VLV_PSRSTAT(pipe
)) &
2254 VLV_EDP_PSR_CURR_STATE_MASK
;
2255 if ((stat
[pipe
] == VLV_EDP_PSR_ACTIVE_NORFB_UP
) ||
2256 (stat
[pipe
] == VLV_EDP_PSR_ACTIVE_SF_UPDATE
))
2261 seq_printf(m
, "HW Enabled & Active bit: %s", yesno(enabled
));
2264 for_each_pipe(dev_priv
, pipe
) {
2265 if ((stat
[pipe
] == VLV_EDP_PSR_ACTIVE_NORFB_UP
) ||
2266 (stat
[pipe
] == VLV_EDP_PSR_ACTIVE_SF_UPDATE
))
2267 seq_printf(m
, " pipe %c", pipe_name(pipe
));
2271 seq_printf(m
, "Link standby: %s\n",
2272 yesno((bool)dev_priv
->psr
.link_standby
));
2274 /* CHV PSR has no kind of performance counter */
2275 if (HAS_PSR(dev
) && HAS_DDI(dev
)) {
2276 psrperf
= I915_READ(EDP_PSR_PERF_CNT(dev
)) &
2277 EDP_PSR_PERF_CNT_MASK
;
2279 seq_printf(m
, "Performance_Counter: %u\n", psrperf
);
2281 mutex_unlock(&dev_priv
->psr
.lock
);
2283 intel_runtime_pm_put(dev_priv
);
2287 static int i915_sink_crc(struct seq_file
*m
, void *data
)
2289 struct drm_info_node
*node
= m
->private;
2290 struct drm_device
*dev
= node
->minor
->dev
;
2291 struct intel_encoder
*encoder
;
2292 struct intel_connector
*connector
;
2293 struct intel_dp
*intel_dp
= NULL
;
2297 drm_modeset_lock_all(dev
);
2298 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
2301 if (connector
->base
.dpms
!= DRM_MODE_DPMS_ON
)
2304 if (!connector
->base
.encoder
)
2307 encoder
= to_intel_encoder(connector
->base
.encoder
);
2308 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2311 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2313 ret
= intel_dp_sink_crc(intel_dp
, crc
);
2317 seq_printf(m
, "%02x%02x%02x%02x%02x%02x\n",
2318 crc
[0], crc
[1], crc
[2],
2319 crc
[3], crc
[4], crc
[5]);
2324 drm_modeset_unlock_all(dev
);
2328 static int i915_energy_uJ(struct seq_file
*m
, void *data
)
2330 struct drm_info_node
*node
= m
->private;
2331 struct drm_device
*dev
= node
->minor
->dev
;
2332 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2336 if (INTEL_INFO(dev
)->gen
< 6)
2339 intel_runtime_pm_get(dev_priv
);
2341 rdmsrl(MSR_RAPL_POWER_UNIT
, power
);
2342 power
= (power
& 0x1f00) >> 8;
2343 units
= 1000000 / (1 << power
); /* convert to uJ */
2344 power
= I915_READ(MCH_SECP_NRG_STTS
);
2347 intel_runtime_pm_put(dev_priv
);
2349 seq_printf(m
, "%llu", (long long unsigned)power
);
2354 static int i915_pc8_status(struct seq_file
*m
, void *unused
)
2356 struct drm_info_node
*node
= m
->private;
2357 struct drm_device
*dev
= node
->minor
->dev
;
2358 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2360 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
2361 seq_puts(m
, "not supported\n");
2365 seq_printf(m
, "GPU idle: %s\n", yesno(!dev_priv
->mm
.busy
));
2366 seq_printf(m
, "IRQs disabled: %s\n",
2367 yesno(!intel_irqs_enabled(dev_priv
)));
2372 static const char *power_domain_str(enum intel_display_power_domain domain
)
2375 case POWER_DOMAIN_PIPE_A
:
2377 case POWER_DOMAIN_PIPE_B
:
2379 case POWER_DOMAIN_PIPE_C
:
2381 case POWER_DOMAIN_PIPE_A_PANEL_FITTER
:
2382 return "PIPE_A_PANEL_FITTER";
2383 case POWER_DOMAIN_PIPE_B_PANEL_FITTER
:
2384 return "PIPE_B_PANEL_FITTER";
2385 case POWER_DOMAIN_PIPE_C_PANEL_FITTER
:
2386 return "PIPE_C_PANEL_FITTER";
2387 case POWER_DOMAIN_TRANSCODER_A
:
2388 return "TRANSCODER_A";
2389 case POWER_DOMAIN_TRANSCODER_B
:
2390 return "TRANSCODER_B";
2391 case POWER_DOMAIN_TRANSCODER_C
:
2392 return "TRANSCODER_C";
2393 case POWER_DOMAIN_TRANSCODER_EDP
:
2394 return "TRANSCODER_EDP";
2395 case POWER_DOMAIN_PORT_DDI_A_2_LANES
:
2396 return "PORT_DDI_A_2_LANES";
2397 case POWER_DOMAIN_PORT_DDI_A_4_LANES
:
2398 return "PORT_DDI_A_4_LANES";
2399 case POWER_DOMAIN_PORT_DDI_B_2_LANES
:
2400 return "PORT_DDI_B_2_LANES";
2401 case POWER_DOMAIN_PORT_DDI_B_4_LANES
:
2402 return "PORT_DDI_B_4_LANES";
2403 case POWER_DOMAIN_PORT_DDI_C_2_LANES
:
2404 return "PORT_DDI_C_2_LANES";
2405 case POWER_DOMAIN_PORT_DDI_C_4_LANES
:
2406 return "PORT_DDI_C_4_LANES";
2407 case POWER_DOMAIN_PORT_DDI_D_2_LANES
:
2408 return "PORT_DDI_D_2_LANES";
2409 case POWER_DOMAIN_PORT_DDI_D_4_LANES
:
2410 return "PORT_DDI_D_4_LANES";
2411 case POWER_DOMAIN_PORT_DSI
:
2413 case POWER_DOMAIN_PORT_CRT
:
2415 case POWER_DOMAIN_PORT_OTHER
:
2416 return "PORT_OTHER";
2417 case POWER_DOMAIN_VGA
:
2419 case POWER_DOMAIN_AUDIO
:
2421 case POWER_DOMAIN_PLLS
:
2423 case POWER_DOMAIN_AUX_A
:
2425 case POWER_DOMAIN_AUX_B
:
2427 case POWER_DOMAIN_AUX_C
:
2429 case POWER_DOMAIN_AUX_D
:
2431 case POWER_DOMAIN_INIT
:
2434 MISSING_CASE(domain
);
2439 static int i915_power_domain_info(struct seq_file
*m
, void *unused
)
2441 struct drm_info_node
*node
= m
->private;
2442 struct drm_device
*dev
= node
->minor
->dev
;
2443 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2444 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
2447 mutex_lock(&power_domains
->lock
);
2449 seq_printf(m
, "%-25s %s\n", "Power well/domain", "Use count");
2450 for (i
= 0; i
< power_domains
->power_well_count
; i
++) {
2451 struct i915_power_well
*power_well
;
2452 enum intel_display_power_domain power_domain
;
2454 power_well
= &power_domains
->power_wells
[i
];
2455 seq_printf(m
, "%-25s %d\n", power_well
->name
,
2458 for (power_domain
= 0; power_domain
< POWER_DOMAIN_NUM
;
2460 if (!(BIT(power_domain
) & power_well
->domains
))
2463 seq_printf(m
, " %-23s %d\n",
2464 power_domain_str(power_domain
),
2465 power_domains
->domain_use_count
[power_domain
]);
2469 mutex_unlock(&power_domains
->lock
);
2474 static void intel_seq_print_mode(struct seq_file
*m
, int tabs
,
2475 struct drm_display_mode
*mode
)
2479 for (i
= 0; i
< tabs
; i
++)
2482 seq_printf(m
, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2483 mode
->base
.id
, mode
->name
,
2484 mode
->vrefresh
, mode
->clock
,
2485 mode
->hdisplay
, mode
->hsync_start
,
2486 mode
->hsync_end
, mode
->htotal
,
2487 mode
->vdisplay
, mode
->vsync_start
,
2488 mode
->vsync_end
, mode
->vtotal
,
2489 mode
->type
, mode
->flags
);
2492 static void intel_encoder_info(struct seq_file
*m
,
2493 struct intel_crtc
*intel_crtc
,
2494 struct intel_encoder
*intel_encoder
)
2496 struct drm_info_node
*node
= m
->private;
2497 struct drm_device
*dev
= node
->minor
->dev
;
2498 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2499 struct intel_connector
*intel_connector
;
2500 struct drm_encoder
*encoder
;
2502 encoder
= &intel_encoder
->base
;
2503 seq_printf(m
, "\tencoder %d: type: %s, connectors:\n",
2504 encoder
->base
.id
, encoder
->name
);
2505 for_each_connector_on_encoder(dev
, encoder
, intel_connector
) {
2506 struct drm_connector
*connector
= &intel_connector
->base
;
2507 seq_printf(m
, "\t\tconnector %d: type: %s, status: %s",
2510 drm_get_connector_status_name(connector
->status
));
2511 if (connector
->status
== connector_status_connected
) {
2512 struct drm_display_mode
*mode
= &crtc
->mode
;
2513 seq_printf(m
, ", mode:\n");
2514 intel_seq_print_mode(m
, 2, mode
);
2521 static void intel_crtc_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
2523 struct drm_info_node
*node
= m
->private;
2524 struct drm_device
*dev
= node
->minor
->dev
;
2525 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2526 struct intel_encoder
*intel_encoder
;
2528 if (crtc
->primary
->fb
)
2529 seq_printf(m
, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2530 crtc
->primary
->fb
->base
.id
, crtc
->x
, crtc
->y
,
2531 crtc
->primary
->fb
->width
, crtc
->primary
->fb
->height
);
2533 seq_puts(m
, "\tprimary plane disabled\n");
2534 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
2535 intel_encoder_info(m
, intel_crtc
, intel_encoder
);
2538 static void intel_panel_info(struct seq_file
*m
, struct intel_panel
*panel
)
2540 struct drm_display_mode
*mode
= panel
->fixed_mode
;
2542 seq_printf(m
, "\tfixed mode:\n");
2543 intel_seq_print_mode(m
, 2, mode
);
2546 static void intel_dp_info(struct seq_file
*m
,
2547 struct intel_connector
*intel_connector
)
2549 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2550 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
2552 seq_printf(m
, "\tDPCD rev: %x\n", intel_dp
->dpcd
[DP_DPCD_REV
]);
2553 seq_printf(m
, "\taudio support: %s\n", intel_dp
->has_audio
? "yes" :
2555 if (intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2556 intel_panel_info(m
, &intel_connector
->panel
);
2559 static void intel_hdmi_info(struct seq_file
*m
,
2560 struct intel_connector
*intel_connector
)
2562 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2563 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&intel_encoder
->base
);
2565 seq_printf(m
, "\taudio support: %s\n", intel_hdmi
->has_audio
? "yes" :
2569 static void intel_lvds_info(struct seq_file
*m
,
2570 struct intel_connector
*intel_connector
)
2572 intel_panel_info(m
, &intel_connector
->panel
);
2575 static void intel_connector_info(struct seq_file
*m
,
2576 struct drm_connector
*connector
)
2578 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2579 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2580 struct drm_display_mode
*mode
;
2582 seq_printf(m
, "connector %d: type %s, status: %s\n",
2583 connector
->base
.id
, connector
->name
,
2584 drm_get_connector_status_name(connector
->status
));
2585 if (connector
->status
== connector_status_connected
) {
2586 seq_printf(m
, "\tname: %s\n", connector
->display_info
.name
);
2587 seq_printf(m
, "\tphysical dimensions: %dx%dmm\n",
2588 connector
->display_info
.width_mm
,
2589 connector
->display_info
.height_mm
);
2590 seq_printf(m
, "\tsubpixel order: %s\n",
2591 drm_get_subpixel_order_name(connector
->display_info
.subpixel_order
));
2592 seq_printf(m
, "\tCEA rev: %d\n",
2593 connector
->display_info
.cea_rev
);
2595 if (intel_encoder
) {
2596 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
2597 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2598 intel_dp_info(m
, intel_connector
);
2599 else if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
)
2600 intel_hdmi_info(m
, intel_connector
);
2601 else if (intel_encoder
->type
== INTEL_OUTPUT_LVDS
)
2602 intel_lvds_info(m
, intel_connector
);
2605 seq_printf(m
, "\tmodes:\n");
2606 list_for_each_entry(mode
, &connector
->modes
, head
)
2607 intel_seq_print_mode(m
, 2, mode
);
2610 static bool cursor_active(struct drm_device
*dev
, int pipe
)
2612 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2615 if (IS_845G(dev
) || IS_I865G(dev
))
2616 state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
2618 state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
2623 static bool cursor_position(struct drm_device
*dev
, int pipe
, int *x
, int *y
)
2625 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2628 pos
= I915_READ(CURPOS(pipe
));
2630 *x
= (pos
>> CURSOR_X_SHIFT
) & CURSOR_POS_MASK
;
2631 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
))
2634 *y
= (pos
>> CURSOR_Y_SHIFT
) & CURSOR_POS_MASK
;
2635 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
))
2638 return cursor_active(dev
, pipe
);
2641 static int i915_display_info(struct seq_file
*m
, void *unused
)
2643 struct drm_info_node
*node
= m
->private;
2644 struct drm_device
*dev
= node
->minor
->dev
;
2645 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2646 struct intel_crtc
*crtc
;
2647 struct drm_connector
*connector
;
2649 intel_runtime_pm_get(dev_priv
);
2650 drm_modeset_lock_all(dev
);
2651 seq_printf(m
, "CRTC info\n");
2652 seq_printf(m
, "---------\n");
2653 for_each_intel_crtc(dev
, crtc
) {
2657 seq_printf(m
, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
2658 crtc
->base
.base
.id
, pipe_name(crtc
->pipe
),
2659 yesno(crtc
->active
), crtc
->config
->pipe_src_w
,
2660 crtc
->config
->pipe_src_h
);
2662 intel_crtc_info(m
, crtc
);
2664 active
= cursor_position(dev
, crtc
->pipe
, &x
, &y
);
2665 seq_printf(m
, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
2666 yesno(crtc
->cursor_base
),
2667 x
, y
, crtc
->cursor_width
, crtc
->cursor_height
,
2668 crtc
->cursor_addr
, yesno(active
));
2671 seq_printf(m
, "\tunderrun reporting: cpu=%s pch=%s \n",
2672 yesno(!crtc
->cpu_fifo_underrun_disabled
),
2673 yesno(!crtc
->pch_fifo_underrun_disabled
));
2676 seq_printf(m
, "\n");
2677 seq_printf(m
, "Connector info\n");
2678 seq_printf(m
, "--------------\n");
2679 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
2680 intel_connector_info(m
, connector
);
2682 drm_modeset_unlock_all(dev
);
2683 intel_runtime_pm_put(dev_priv
);
2688 static int i915_semaphore_status(struct seq_file
*m
, void *unused
)
2690 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2691 struct drm_device
*dev
= node
->minor
->dev
;
2692 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2693 struct intel_engine_cs
*ring
;
2694 int num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
2697 if (!i915_semaphore_is_enabled(dev
)) {
2698 seq_puts(m
, "Semaphores are disabled\n");
2702 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2705 intel_runtime_pm_get(dev_priv
);
2707 if (IS_BROADWELL(dev
)) {
2711 page
= i915_gem_object_get_page(dev_priv
->semaphore_obj
, 0);
2713 seqno
= (uint64_t *)kmap_atomic(page
);
2714 for_each_ring(ring
, dev_priv
, i
) {
2717 seq_printf(m
, "%s\n", ring
->name
);
2719 seq_puts(m
, " Last signal:");
2720 for (j
= 0; j
< num_rings
; j
++) {
2721 offset
= i
* I915_NUM_RINGS
+ j
;
2722 seq_printf(m
, "0x%08llx (0x%02llx) ",
2723 seqno
[offset
], offset
* 8);
2727 seq_puts(m
, " Last wait: ");
2728 for (j
= 0; j
< num_rings
; j
++) {
2729 offset
= i
+ (j
* I915_NUM_RINGS
);
2730 seq_printf(m
, "0x%08llx (0x%02llx) ",
2731 seqno
[offset
], offset
* 8);
2736 kunmap_atomic(seqno
);
2738 seq_puts(m
, " Last signal:");
2739 for_each_ring(ring
, dev_priv
, i
)
2740 for (j
= 0; j
< num_rings
; j
++)
2741 seq_printf(m
, "0x%08x\n",
2742 I915_READ(ring
->semaphore
.mbox
.signal
[j
]));
2746 seq_puts(m
, "\nSync seqno:\n");
2747 for_each_ring(ring
, dev_priv
, i
) {
2748 for (j
= 0; j
< num_rings
; j
++) {
2749 seq_printf(m
, " 0x%08x ", ring
->semaphore
.sync_seqno
[j
]);
2755 intel_runtime_pm_put(dev_priv
);
2756 mutex_unlock(&dev
->struct_mutex
);
2760 static int i915_shared_dplls_info(struct seq_file
*m
, void *unused
)
2762 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2763 struct drm_device
*dev
= node
->minor
->dev
;
2764 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2767 drm_modeset_lock_all(dev
);
2768 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
2769 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
2771 seq_printf(m
, "DPLL%i: %s, id: %i\n", i
, pll
->name
, pll
->id
);
2772 seq_printf(m
, " crtc_mask: 0x%08x, active: %d, on: %s\n",
2773 pll
->config
.crtc_mask
, pll
->active
, yesno(pll
->on
));
2774 seq_printf(m
, " tracked hardware state:\n");
2775 seq_printf(m
, " dpll: 0x%08x\n", pll
->config
.hw_state
.dpll
);
2776 seq_printf(m
, " dpll_md: 0x%08x\n",
2777 pll
->config
.hw_state
.dpll_md
);
2778 seq_printf(m
, " fp0: 0x%08x\n", pll
->config
.hw_state
.fp0
);
2779 seq_printf(m
, " fp1: 0x%08x\n", pll
->config
.hw_state
.fp1
);
2780 seq_printf(m
, " wrpll: 0x%08x\n", pll
->config
.hw_state
.wrpll
);
2782 drm_modeset_unlock_all(dev
);
2787 static int i915_wa_registers(struct seq_file
*m
, void *unused
)
2791 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2792 struct drm_device
*dev
= node
->minor
->dev
;
2793 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2795 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2799 intel_runtime_pm_get(dev_priv
);
2801 seq_printf(m
, "Workarounds applied: %d\n", dev_priv
->workarounds
.count
);
2802 for (i
= 0; i
< dev_priv
->workarounds
.count
; ++i
) {
2803 u32 addr
, mask
, value
, read
;
2806 addr
= dev_priv
->workarounds
.reg
[i
].addr
;
2807 mask
= dev_priv
->workarounds
.reg
[i
].mask
;
2808 value
= dev_priv
->workarounds
.reg
[i
].value
;
2809 read
= I915_READ(addr
);
2810 ok
= (value
& mask
) == (read
& mask
);
2811 seq_printf(m
, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2812 addr
, value
, mask
, read
, ok
? "OK" : "FAIL");
2815 intel_runtime_pm_put(dev_priv
);
2816 mutex_unlock(&dev
->struct_mutex
);
2821 static int i915_ddb_info(struct seq_file
*m
, void *unused
)
2823 struct drm_info_node
*node
= m
->private;
2824 struct drm_device
*dev
= node
->minor
->dev
;
2825 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2826 struct skl_ddb_allocation
*ddb
;
2827 struct skl_ddb_entry
*entry
;
2831 if (INTEL_INFO(dev
)->gen
< 9)
2834 drm_modeset_lock_all(dev
);
2836 ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
2838 seq_printf(m
, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
2840 for_each_pipe(dev_priv
, pipe
) {
2841 seq_printf(m
, "Pipe %c\n", pipe_name(pipe
));
2843 for_each_plane(pipe
, plane
) {
2844 entry
= &ddb
->plane
[pipe
][plane
];
2845 seq_printf(m
, " Plane%-8d%8u%8u%8u\n", plane
+ 1,
2846 entry
->start
, entry
->end
,
2847 skl_ddb_entry_size(entry
));
2850 entry
= &ddb
->cursor
[pipe
];
2851 seq_printf(m
, " %-13s%8u%8u%8u\n", "Cursor", entry
->start
,
2852 entry
->end
, skl_ddb_entry_size(entry
));
2855 drm_modeset_unlock_all(dev
);
2860 struct pipe_crc_info
{
2862 struct drm_device
*dev
;
2866 static int i915_dp_mst_info(struct seq_file
*m
, void *unused
)
2868 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2869 struct drm_device
*dev
= node
->minor
->dev
;
2870 struct drm_encoder
*encoder
;
2871 struct intel_encoder
*intel_encoder
;
2872 struct intel_digital_port
*intel_dig_port
;
2873 drm_modeset_lock_all(dev
);
2874 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
2875 intel_encoder
= to_intel_encoder(encoder
);
2876 if (intel_encoder
->type
!= INTEL_OUTPUT_DISPLAYPORT
)
2878 intel_dig_port
= enc_to_dig_port(encoder
);
2879 if (!intel_dig_port
->dp
.can_mst
)
2882 drm_dp_mst_dump_topology(m
, &intel_dig_port
->dp
.mst_mgr
);
2884 drm_modeset_unlock_all(dev
);
2888 static int i915_pipe_crc_open(struct inode
*inode
, struct file
*filep
)
2890 struct pipe_crc_info
*info
= inode
->i_private
;
2891 struct drm_i915_private
*dev_priv
= info
->dev
->dev_private
;
2892 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
2894 if (info
->pipe
>= INTEL_INFO(info
->dev
)->num_pipes
)
2897 spin_lock_irq(&pipe_crc
->lock
);
2899 if (pipe_crc
->opened
) {
2900 spin_unlock_irq(&pipe_crc
->lock
);
2901 return -EBUSY
; /* already open */
2904 pipe_crc
->opened
= true;
2905 filep
->private_data
= inode
->i_private
;
2907 spin_unlock_irq(&pipe_crc
->lock
);
2912 static int i915_pipe_crc_release(struct inode
*inode
, struct file
*filep
)
2914 struct pipe_crc_info
*info
= inode
->i_private
;
2915 struct drm_i915_private
*dev_priv
= info
->dev
->dev_private
;
2916 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
2918 spin_lock_irq(&pipe_crc
->lock
);
2919 pipe_crc
->opened
= false;
2920 spin_unlock_irq(&pipe_crc
->lock
);
2925 /* (6 fields, 8 chars each, space separated (5) + '\n') */
2926 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
2927 /* account for \'0' */
2928 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
2930 static int pipe_crc_data_count(struct intel_pipe_crc
*pipe_crc
)
2932 assert_spin_locked(&pipe_crc
->lock
);
2933 return CIRC_CNT(pipe_crc
->head
, pipe_crc
->tail
,
2934 INTEL_PIPE_CRC_ENTRIES_NR
);
2938 i915_pipe_crc_read(struct file
*filep
, char __user
*user_buf
, size_t count
,
2941 struct pipe_crc_info
*info
= filep
->private_data
;
2942 struct drm_device
*dev
= info
->dev
;
2943 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2944 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
2945 char buf
[PIPE_CRC_BUFFER_LEN
];
2950 * Don't allow user space to provide buffers not big enough to hold
2953 if (count
< PIPE_CRC_LINE_LEN
)
2956 if (pipe_crc
->source
== INTEL_PIPE_CRC_SOURCE_NONE
)
2959 /* nothing to read */
2960 spin_lock_irq(&pipe_crc
->lock
);
2961 while (pipe_crc_data_count(pipe_crc
) == 0) {
2964 if (filep
->f_flags
& O_NONBLOCK
) {
2965 spin_unlock_irq(&pipe_crc
->lock
);
2969 ret
= wait_event_interruptible_lock_irq(pipe_crc
->wq
,
2970 pipe_crc_data_count(pipe_crc
), pipe_crc
->lock
);
2972 spin_unlock_irq(&pipe_crc
->lock
);
2977 /* We now have one or more entries to read */
2978 n_entries
= count
/ PIPE_CRC_LINE_LEN
;
2981 while (n_entries
> 0) {
2982 struct intel_pipe_crc_entry
*entry
=
2983 &pipe_crc
->entries
[pipe_crc
->tail
];
2986 if (CIRC_CNT(pipe_crc
->head
, pipe_crc
->tail
,
2987 INTEL_PIPE_CRC_ENTRIES_NR
) < 1)
2990 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR
);
2991 pipe_crc
->tail
= (pipe_crc
->tail
+ 1) & (INTEL_PIPE_CRC_ENTRIES_NR
- 1);
2993 bytes_read
+= snprintf(buf
, PIPE_CRC_BUFFER_LEN
,
2994 "%8u %8x %8x %8x %8x %8x\n",
2995 entry
->frame
, entry
->crc
[0],
2996 entry
->crc
[1], entry
->crc
[2],
2997 entry
->crc
[3], entry
->crc
[4]);
2999 spin_unlock_irq(&pipe_crc
->lock
);
3001 ret
= copy_to_user(user_buf
, buf
, PIPE_CRC_LINE_LEN
);
3002 if (ret
== PIPE_CRC_LINE_LEN
)
3005 user_buf
+= PIPE_CRC_LINE_LEN
;
3008 spin_lock_irq(&pipe_crc
->lock
);
3011 spin_unlock_irq(&pipe_crc
->lock
);
3016 static const struct file_operations i915_pipe_crc_fops
= {
3017 .owner
= THIS_MODULE
,
3018 .open
= i915_pipe_crc_open
,
3019 .read
= i915_pipe_crc_read
,
3020 .release
= i915_pipe_crc_release
,
3023 static struct pipe_crc_info i915_pipe_crc_data
[I915_MAX_PIPES
] = {
3025 .name
= "i915_pipe_A_crc",
3029 .name
= "i915_pipe_B_crc",
3033 .name
= "i915_pipe_C_crc",
3038 static int i915_pipe_crc_create(struct dentry
*root
, struct drm_minor
*minor
,
3041 struct drm_device
*dev
= minor
->dev
;
3043 struct pipe_crc_info
*info
= &i915_pipe_crc_data
[pipe
];
3046 ent
= debugfs_create_file(info
->name
, S_IRUGO
, root
, info
,
3047 &i915_pipe_crc_fops
);
3051 return drm_add_fake_info_node(minor
, ent
, info
);
3054 static const char * const pipe_crc_sources
[] = {
3067 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source
)
3069 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources
) != INTEL_PIPE_CRC_SOURCE_MAX
);
3070 return pipe_crc_sources
[source
];
3073 static int display_crc_ctl_show(struct seq_file
*m
, void *data
)
3075 struct drm_device
*dev
= m
->private;
3076 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3079 for (i
= 0; i
< I915_MAX_PIPES
; i
++)
3080 seq_printf(m
, "%c %s\n", pipe_name(i
),
3081 pipe_crc_source_name(dev_priv
->pipe_crc
[i
].source
));
3086 static int display_crc_ctl_open(struct inode
*inode
, struct file
*file
)
3088 struct drm_device
*dev
= inode
->i_private
;
3090 return single_open(file
, display_crc_ctl_show
, dev
);
3093 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
3096 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3097 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3100 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3101 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_INCLUDE_BORDER_I8XX
;
3103 case INTEL_PIPE_CRC_SOURCE_NONE
:
3113 static int i9xx_pipe_crc_auto_source(struct drm_device
*dev
, enum pipe pipe
,
3114 enum intel_pipe_crc_source
*source
)
3116 struct intel_encoder
*encoder
;
3117 struct intel_crtc
*crtc
;
3118 struct intel_digital_port
*dig_port
;
3121 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3123 drm_modeset_lock_all(dev
);
3124 for_each_intel_encoder(dev
, encoder
) {
3125 if (!encoder
->base
.crtc
)
3128 crtc
= to_intel_crtc(encoder
->base
.crtc
);
3130 if (crtc
->pipe
!= pipe
)
3133 switch (encoder
->type
) {
3134 case INTEL_OUTPUT_TVOUT
:
3135 *source
= INTEL_PIPE_CRC_SOURCE_TV
;
3137 case INTEL_OUTPUT_DISPLAYPORT
:
3138 case INTEL_OUTPUT_EDP
:
3139 dig_port
= enc_to_dig_port(&encoder
->base
);
3140 switch (dig_port
->port
) {
3142 *source
= INTEL_PIPE_CRC_SOURCE_DP_B
;
3145 *source
= INTEL_PIPE_CRC_SOURCE_DP_C
;
3148 *source
= INTEL_PIPE_CRC_SOURCE_DP_D
;
3151 WARN(1, "nonexisting DP port %c\n",
3152 port_name(dig_port
->port
));
3160 drm_modeset_unlock_all(dev
);
3165 static int vlv_pipe_crc_ctl_reg(struct drm_device
*dev
,
3167 enum intel_pipe_crc_source
*source
,
3170 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3171 bool need_stable_symbols
= false;
3173 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
3174 int ret
= i9xx_pipe_crc_auto_source(dev
, pipe
, source
);
3180 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3181 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_VLV
;
3183 case INTEL_PIPE_CRC_SOURCE_DP_B
:
3184 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_VLV
;
3185 need_stable_symbols
= true;
3187 case INTEL_PIPE_CRC_SOURCE_DP_C
:
3188 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_VLV
;
3189 need_stable_symbols
= true;
3191 case INTEL_PIPE_CRC_SOURCE_DP_D
:
3192 if (!IS_CHERRYVIEW(dev
))
3194 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_D_VLV
;
3195 need_stable_symbols
= true;
3197 case INTEL_PIPE_CRC_SOURCE_NONE
:
3205 * When the pipe CRC tap point is after the transcoders we need
3206 * to tweak symbol-level features to produce a deterministic series of
3207 * symbols for a given frame. We need to reset those features only once
3208 * a frame (instead of every nth symbol):
3209 * - DC-balance: used to ensure a better clock recovery from the data
3211 * - DisplayPort scrambling: used for EMI reduction
3213 if (need_stable_symbols
) {
3214 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3216 tmp
|= DC_BALANCE_RESET_VLV
;
3219 tmp
|= PIPE_A_SCRAMBLE_RESET
;
3222 tmp
|= PIPE_B_SCRAMBLE_RESET
;
3225 tmp
|= PIPE_C_SCRAMBLE_RESET
;
3230 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3236 static int i9xx_pipe_crc_ctl_reg(struct drm_device
*dev
,
3238 enum intel_pipe_crc_source
*source
,
3241 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3242 bool need_stable_symbols
= false;
3244 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
3245 int ret
= i9xx_pipe_crc_auto_source(dev
, pipe
, source
);
3251 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3252 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_I9XX
;
3254 case INTEL_PIPE_CRC_SOURCE_TV
:
3255 if (!SUPPORTS_TV(dev
))
3257 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_TV_PRE
;
3259 case INTEL_PIPE_CRC_SOURCE_DP_B
:
3262 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_G4X
;
3263 need_stable_symbols
= true;
3265 case INTEL_PIPE_CRC_SOURCE_DP_C
:
3268 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_G4X
;
3269 need_stable_symbols
= true;
3271 case INTEL_PIPE_CRC_SOURCE_DP_D
:
3274 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_D_G4X
;
3275 need_stable_symbols
= true;
3277 case INTEL_PIPE_CRC_SOURCE_NONE
:
3285 * When the pipe CRC tap point is after the transcoders we need
3286 * to tweak symbol-level features to produce a deterministic series of
3287 * symbols for a given frame. We need to reset those features only once
3288 * a frame (instead of every nth symbol):
3289 * - DC-balance: used to ensure a better clock recovery from the data
3291 * - DisplayPort scrambling: used for EMI reduction
3293 if (need_stable_symbols
) {
3294 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3296 WARN_ON(!IS_G4X(dev
));
3298 I915_WRITE(PORT_DFT_I9XX
,
3299 I915_READ(PORT_DFT_I9XX
) | DC_BALANCE_RESET
);
3302 tmp
|= PIPE_A_SCRAMBLE_RESET
;
3304 tmp
|= PIPE_B_SCRAMBLE_RESET
;
3306 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3312 static void vlv_undo_pipe_scramble_reset(struct drm_device
*dev
,
3315 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3316 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3320 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
3323 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
3326 tmp
&= ~PIPE_C_SCRAMBLE_RESET
;
3331 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
))
3332 tmp
&= ~DC_BALANCE_RESET_VLV
;
3333 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3337 static void g4x_undo_pipe_scramble_reset(struct drm_device
*dev
,
3340 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3341 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3344 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
3346 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
3347 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3349 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
)) {
3350 I915_WRITE(PORT_DFT_I9XX
,
3351 I915_READ(PORT_DFT_I9XX
) & ~DC_BALANCE_RESET
);
3355 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
3358 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3359 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3362 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
3363 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_ILK
;
3365 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
3366 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_ILK
;
3368 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3369 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_ILK
;
3371 case INTEL_PIPE_CRC_SOURCE_NONE
:
3381 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device
*dev
)
3383 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3384 struct intel_crtc
*crtc
=
3385 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_A
]);
3387 drm_modeset_lock_all(dev
);
3389 * If we use the eDP transcoder we need to make sure that we don't
3390 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3391 * relevant on hsw with pipe A when using the always-on power well
3394 if (crtc
->config
->cpu_transcoder
== TRANSCODER_EDP
&&
3395 !crtc
->config
->pch_pfit
.enabled
) {
3396 crtc
->config
->pch_pfit
.force_thru
= true;
3398 intel_display_power_get(dev_priv
,
3399 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A
));
3401 dev_priv
->display
.crtc_disable(&crtc
->base
);
3402 dev_priv
->display
.crtc_enable(&crtc
->base
);
3404 drm_modeset_unlock_all(dev
);
3407 static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device
*dev
)
3409 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3410 struct intel_crtc
*crtc
=
3411 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_A
]);
3413 drm_modeset_lock_all(dev
);
3415 * If we use the eDP transcoder we need to make sure that we don't
3416 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3417 * relevant on hsw with pipe A when using the always-on power well
3420 if (crtc
->config
->pch_pfit
.force_thru
) {
3421 crtc
->config
->pch_pfit
.force_thru
= false;
3423 dev_priv
->display
.crtc_disable(&crtc
->base
);
3424 dev_priv
->display
.crtc_enable(&crtc
->base
);
3426 intel_display_power_put(dev_priv
,
3427 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A
));
3429 drm_modeset_unlock_all(dev
);
3432 static int ivb_pipe_crc_ctl_reg(struct drm_device
*dev
,
3434 enum intel_pipe_crc_source
*source
,
3437 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3438 *source
= INTEL_PIPE_CRC_SOURCE_PF
;
3441 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
3442 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_IVB
;
3444 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
3445 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_IVB
;
3447 case INTEL_PIPE_CRC_SOURCE_PF
:
3448 if (IS_HASWELL(dev
) && pipe
== PIPE_A
)
3449 hsw_trans_edp_pipe_A_crc_wa(dev
);
3451 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PF_IVB
;
3453 case INTEL_PIPE_CRC_SOURCE_NONE
:
3463 static int pipe_crc_set_source(struct drm_device
*dev
, enum pipe pipe
,
3464 enum intel_pipe_crc_source source
)
3466 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3467 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
3468 struct intel_crtc
*crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
,
3470 u32 val
= 0; /* shut up gcc */
3473 if (pipe_crc
->source
== source
)
3476 /* forbid changing the source without going back to 'none' */
3477 if (pipe_crc
->source
&& source
)
3480 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PIPE(pipe
))) {
3481 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3486 ret
= i8xx_pipe_crc_ctl_reg(&source
, &val
);
3487 else if (INTEL_INFO(dev
)->gen
< 5)
3488 ret
= i9xx_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
3489 else if (IS_VALLEYVIEW(dev
))
3490 ret
= vlv_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
3491 else if (IS_GEN5(dev
) || IS_GEN6(dev
))
3492 ret
= ilk_pipe_crc_ctl_reg(&source
, &val
);
3494 ret
= ivb_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
3499 /* none -> real source transition */
3501 struct intel_pipe_crc_entry
*entries
;
3503 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3504 pipe_name(pipe
), pipe_crc_source_name(source
));
3506 entries
= kcalloc(INTEL_PIPE_CRC_ENTRIES_NR
,
3507 sizeof(pipe_crc
->entries
[0]),
3513 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3514 * enabled and disabled dynamically based on package C states,
3515 * user space can't make reliable use of the CRCs, so let's just
3516 * completely disable it.
3518 hsw_disable_ips(crtc
);
3520 spin_lock_irq(&pipe_crc
->lock
);
3521 kfree(pipe_crc
->entries
);
3522 pipe_crc
->entries
= entries
;
3525 spin_unlock_irq(&pipe_crc
->lock
);
3528 pipe_crc
->source
= source
;
3530 I915_WRITE(PIPE_CRC_CTL(pipe
), val
);
3531 POSTING_READ(PIPE_CRC_CTL(pipe
));
3533 /* real source -> none transition */
3534 if (source
== INTEL_PIPE_CRC_SOURCE_NONE
) {
3535 struct intel_pipe_crc_entry
*entries
;
3536 struct intel_crtc
*crtc
=
3537 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
3539 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3542 drm_modeset_lock(&crtc
->base
.mutex
, NULL
);
3544 intel_wait_for_vblank(dev
, pipe
);
3545 drm_modeset_unlock(&crtc
->base
.mutex
);
3547 spin_lock_irq(&pipe_crc
->lock
);
3548 entries
= pipe_crc
->entries
;
3549 pipe_crc
->entries
= NULL
;
3552 spin_unlock_irq(&pipe_crc
->lock
);
3557 g4x_undo_pipe_scramble_reset(dev
, pipe
);
3558 else if (IS_VALLEYVIEW(dev
))
3559 vlv_undo_pipe_scramble_reset(dev
, pipe
);
3560 else if (IS_HASWELL(dev
) && pipe
== PIPE_A
)
3561 hsw_undo_trans_edp_pipe_A_crc_wa(dev
);
3563 hsw_enable_ips(crtc
);
3570 * Parse pipe CRC command strings:
3571 * command: wsp* object wsp+ name wsp+ source wsp*
3574 * source: (none | plane1 | plane2 | pf)
3575 * wsp: (#0x20 | #0x9 | #0xA)+
3578 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3579 * "pipe A none" -> Stop CRC
3581 static int display_crc_ctl_tokenize(char *buf
, char *words
[], int max_words
)
3588 /* skip leading white space */
3589 buf
= skip_spaces(buf
);
3591 break; /* end of buffer */
3593 /* find end of word */
3594 for (end
= buf
; *end
&& !isspace(*end
); end
++)
3597 if (n_words
== max_words
) {
3598 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3600 return -EINVAL
; /* ran out of words[] before bytes */
3605 words
[n_words
++] = buf
;
3612 enum intel_pipe_crc_object
{
3613 PIPE_CRC_OBJECT_PIPE
,
3616 static const char * const pipe_crc_objects
[] = {
3621 display_crc_ctl_parse_object(const char *buf
, enum intel_pipe_crc_object
*o
)
3625 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_objects
); i
++)
3626 if (!strcmp(buf
, pipe_crc_objects
[i
])) {
3634 static int display_crc_ctl_parse_pipe(const char *buf
, enum pipe
*pipe
)
3636 const char name
= buf
[0];
3638 if (name
< 'A' || name
>= pipe_name(I915_MAX_PIPES
))
3647 display_crc_ctl_parse_source(const char *buf
, enum intel_pipe_crc_source
*s
)
3651 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_sources
); i
++)
3652 if (!strcmp(buf
, pipe_crc_sources
[i
])) {
3660 static int display_crc_ctl_parse(struct drm_device
*dev
, char *buf
, size_t len
)
3664 char *words
[N_WORDS
];
3666 enum intel_pipe_crc_object object
;
3667 enum intel_pipe_crc_source source
;
3669 n_words
= display_crc_ctl_tokenize(buf
, words
, N_WORDS
);
3670 if (n_words
!= N_WORDS
) {
3671 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3676 if (display_crc_ctl_parse_object(words
[0], &object
) < 0) {
3677 DRM_DEBUG_DRIVER("unknown object %s\n", words
[0]);
3681 if (display_crc_ctl_parse_pipe(words
[1], &pipe
) < 0) {
3682 DRM_DEBUG_DRIVER("unknown pipe %s\n", words
[1]);
3686 if (display_crc_ctl_parse_source(words
[2], &source
) < 0) {
3687 DRM_DEBUG_DRIVER("unknown source %s\n", words
[2]);
3691 return pipe_crc_set_source(dev
, pipe
, source
);
3694 static ssize_t
display_crc_ctl_write(struct file
*file
, const char __user
*ubuf
,
3695 size_t len
, loff_t
*offp
)
3697 struct seq_file
*m
= file
->private_data
;
3698 struct drm_device
*dev
= m
->private;
3705 if (len
> PAGE_SIZE
- 1) {
3706 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3711 tmpbuf
= kmalloc(len
+ 1, GFP_KERNEL
);
3715 if (copy_from_user(tmpbuf
, ubuf
, len
)) {
3721 ret
= display_crc_ctl_parse(dev
, tmpbuf
, len
);
3732 static const struct file_operations i915_display_crc_ctl_fops
= {
3733 .owner
= THIS_MODULE
,
3734 .open
= display_crc_ctl_open
,
3736 .llseek
= seq_lseek
,
3737 .release
= single_release
,
3738 .write
= display_crc_ctl_write
3741 static void wm_latency_show(struct seq_file
*m
, const uint16_t wm
[8])
3743 struct drm_device
*dev
= m
->private;
3744 int num_levels
= ilk_wm_max_level(dev
) + 1;
3747 drm_modeset_lock_all(dev
);
3749 for (level
= 0; level
< num_levels
; level
++) {
3750 unsigned int latency
= wm
[level
];
3753 * - WM1+ latency values in 0.5us units
3754 * - latencies are in us on gen9
3756 if (INTEL_INFO(dev
)->gen
>= 9)
3761 seq_printf(m
, "WM%d %u (%u.%u usec)\n",
3762 level
, wm
[level
], latency
/ 10, latency
% 10);
3765 drm_modeset_unlock_all(dev
);
3768 static int pri_wm_latency_show(struct seq_file
*m
, void *data
)
3770 struct drm_device
*dev
= m
->private;
3771 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3772 const uint16_t *latencies
;
3774 if (INTEL_INFO(dev
)->gen
>= 9)
3775 latencies
= dev_priv
->wm
.skl_latency
;
3777 latencies
= to_i915(dev
)->wm
.pri_latency
;
3779 wm_latency_show(m
, latencies
);
3784 static int spr_wm_latency_show(struct seq_file
*m
, void *data
)
3786 struct drm_device
*dev
= m
->private;
3787 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3788 const uint16_t *latencies
;
3790 if (INTEL_INFO(dev
)->gen
>= 9)
3791 latencies
= dev_priv
->wm
.skl_latency
;
3793 latencies
= to_i915(dev
)->wm
.spr_latency
;
3795 wm_latency_show(m
, latencies
);
3800 static int cur_wm_latency_show(struct seq_file
*m
, void *data
)
3802 struct drm_device
*dev
= m
->private;
3803 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3804 const uint16_t *latencies
;
3806 if (INTEL_INFO(dev
)->gen
>= 9)
3807 latencies
= dev_priv
->wm
.skl_latency
;
3809 latencies
= to_i915(dev
)->wm
.cur_latency
;
3811 wm_latency_show(m
, latencies
);
3816 static int pri_wm_latency_open(struct inode
*inode
, struct file
*file
)
3818 struct drm_device
*dev
= inode
->i_private
;
3820 if (HAS_GMCH_DISPLAY(dev
))
3823 return single_open(file
, pri_wm_latency_show
, dev
);
3826 static int spr_wm_latency_open(struct inode
*inode
, struct file
*file
)
3828 struct drm_device
*dev
= inode
->i_private
;
3830 if (HAS_GMCH_DISPLAY(dev
))
3833 return single_open(file
, spr_wm_latency_show
, dev
);
3836 static int cur_wm_latency_open(struct inode
*inode
, struct file
*file
)
3838 struct drm_device
*dev
= inode
->i_private
;
3840 if (HAS_GMCH_DISPLAY(dev
))
3843 return single_open(file
, cur_wm_latency_show
, dev
);
3846 static ssize_t
wm_latency_write(struct file
*file
, const char __user
*ubuf
,
3847 size_t len
, loff_t
*offp
, uint16_t wm
[8])
3849 struct seq_file
*m
= file
->private_data
;
3850 struct drm_device
*dev
= m
->private;
3851 uint16_t new[8] = { 0 };
3852 int num_levels
= ilk_wm_max_level(dev
) + 1;
3857 if (len
>= sizeof(tmp
))
3860 if (copy_from_user(tmp
, ubuf
, len
))
3865 ret
= sscanf(tmp
, "%hu %hu %hu %hu %hu %hu %hu %hu",
3866 &new[0], &new[1], &new[2], &new[3],
3867 &new[4], &new[5], &new[6], &new[7]);
3868 if (ret
!= num_levels
)
3871 drm_modeset_lock_all(dev
);
3873 for (level
= 0; level
< num_levels
; level
++)
3874 wm
[level
] = new[level
];
3876 drm_modeset_unlock_all(dev
);
3882 static ssize_t
pri_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
3883 size_t len
, loff_t
*offp
)
3885 struct seq_file
*m
= file
->private_data
;
3886 struct drm_device
*dev
= m
->private;
3887 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3888 uint16_t *latencies
;
3890 if (INTEL_INFO(dev
)->gen
>= 9)
3891 latencies
= dev_priv
->wm
.skl_latency
;
3893 latencies
= to_i915(dev
)->wm
.pri_latency
;
3895 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
3898 static ssize_t
spr_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
3899 size_t len
, loff_t
*offp
)
3901 struct seq_file
*m
= file
->private_data
;
3902 struct drm_device
*dev
= m
->private;
3903 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3904 uint16_t *latencies
;
3906 if (INTEL_INFO(dev
)->gen
>= 9)
3907 latencies
= dev_priv
->wm
.skl_latency
;
3909 latencies
= to_i915(dev
)->wm
.spr_latency
;
3911 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
3914 static ssize_t
cur_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
3915 size_t len
, loff_t
*offp
)
3917 struct seq_file
*m
= file
->private_data
;
3918 struct drm_device
*dev
= m
->private;
3919 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3920 uint16_t *latencies
;
3922 if (INTEL_INFO(dev
)->gen
>= 9)
3923 latencies
= dev_priv
->wm
.skl_latency
;
3925 latencies
= to_i915(dev
)->wm
.cur_latency
;
3927 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
3930 static const struct file_operations i915_pri_wm_latency_fops
= {
3931 .owner
= THIS_MODULE
,
3932 .open
= pri_wm_latency_open
,
3934 .llseek
= seq_lseek
,
3935 .release
= single_release
,
3936 .write
= pri_wm_latency_write
3939 static const struct file_operations i915_spr_wm_latency_fops
= {
3940 .owner
= THIS_MODULE
,
3941 .open
= spr_wm_latency_open
,
3943 .llseek
= seq_lseek
,
3944 .release
= single_release
,
3945 .write
= spr_wm_latency_write
3948 static const struct file_operations i915_cur_wm_latency_fops
= {
3949 .owner
= THIS_MODULE
,
3950 .open
= cur_wm_latency_open
,
3952 .llseek
= seq_lseek
,
3953 .release
= single_release
,
3954 .write
= cur_wm_latency_write
3958 i915_wedged_get(void *data
, u64
*val
)
3960 struct drm_device
*dev
= data
;
3961 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3963 *val
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
3969 i915_wedged_set(void *data
, u64 val
)
3971 struct drm_device
*dev
= data
;
3972 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3975 * There is no safeguard against this debugfs entry colliding
3976 * with the hangcheck calling same i915_handle_error() in
3977 * parallel, causing an explosion. For now we assume that the
3978 * test harness is responsible enough not to inject gpu hangs
3979 * while it is writing to 'i915_wedged'
3982 if (i915_reset_in_progress(&dev_priv
->gpu_error
))
3985 intel_runtime_pm_get(dev_priv
);
3987 i915_handle_error(dev
, val
,
3988 "Manually setting wedged to %llu", val
);
3990 intel_runtime_pm_put(dev_priv
);
3995 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops
,
3996 i915_wedged_get
, i915_wedged_set
,
4000 i915_ring_stop_get(void *data
, u64
*val
)
4002 struct drm_device
*dev
= data
;
4003 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4005 *val
= dev_priv
->gpu_error
.stop_rings
;
4011 i915_ring_stop_set(void *data
, u64 val
)
4013 struct drm_device
*dev
= data
;
4014 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4017 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val
);
4019 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4023 dev_priv
->gpu_error
.stop_rings
= val
;
4024 mutex_unlock(&dev
->struct_mutex
);
4029 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops
,
4030 i915_ring_stop_get
, i915_ring_stop_set
,
4034 i915_ring_missed_irq_get(void *data
, u64
*val
)
4036 struct drm_device
*dev
= data
;
4037 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4039 *val
= dev_priv
->gpu_error
.missed_irq_rings
;
4044 i915_ring_missed_irq_set(void *data
, u64 val
)
4046 struct drm_device
*dev
= data
;
4047 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4050 /* Lock against concurrent debugfs callers */
4051 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4054 dev_priv
->gpu_error
.missed_irq_rings
= val
;
4055 mutex_unlock(&dev
->struct_mutex
);
4060 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops
,
4061 i915_ring_missed_irq_get
, i915_ring_missed_irq_set
,
4065 i915_ring_test_irq_get(void *data
, u64
*val
)
4067 struct drm_device
*dev
= data
;
4068 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4070 *val
= dev_priv
->gpu_error
.test_irq_rings
;
4076 i915_ring_test_irq_set(void *data
, u64 val
)
4078 struct drm_device
*dev
= data
;
4079 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4082 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val
);
4084 /* Lock against concurrent debugfs callers */
4085 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4089 dev_priv
->gpu_error
.test_irq_rings
= val
;
4090 mutex_unlock(&dev
->struct_mutex
);
4095 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops
,
4096 i915_ring_test_irq_get
, i915_ring_test_irq_set
,
4099 #define DROP_UNBOUND 0x1
4100 #define DROP_BOUND 0x2
4101 #define DROP_RETIRE 0x4
4102 #define DROP_ACTIVE 0x8
4103 #define DROP_ALL (DROP_UNBOUND | \
4108 i915_drop_caches_get(void *data
, u64
*val
)
4116 i915_drop_caches_set(void *data
, u64 val
)
4118 struct drm_device
*dev
= data
;
4119 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4122 DRM_DEBUG("Dropping caches: 0x%08llx\n", val
);
4124 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4125 * on ioctls on -EAGAIN. */
4126 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4130 if (val
& DROP_ACTIVE
) {
4131 ret
= i915_gpu_idle(dev
);
4136 if (val
& (DROP_RETIRE
| DROP_ACTIVE
))
4137 i915_gem_retire_requests(dev
);
4139 if (val
& DROP_BOUND
)
4140 i915_gem_shrink(dev_priv
, LONG_MAX
, I915_SHRINK_BOUND
);
4142 if (val
& DROP_UNBOUND
)
4143 i915_gem_shrink(dev_priv
, LONG_MAX
, I915_SHRINK_UNBOUND
);
4146 mutex_unlock(&dev
->struct_mutex
);
4151 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops
,
4152 i915_drop_caches_get
, i915_drop_caches_set
,
4156 i915_max_freq_get(void *data
, u64
*val
)
4158 struct drm_device
*dev
= data
;
4159 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4162 if (INTEL_INFO(dev
)->gen
< 6)
4165 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4167 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4171 *val
= intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq_softlimit
);
4172 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4178 i915_max_freq_set(void *data
, u64 val
)
4180 struct drm_device
*dev
= data
;
4181 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4182 u32 rp_state_cap
, hw_max
, hw_min
;
4185 if (INTEL_INFO(dev
)->gen
< 6)
4188 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4190 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val
);
4192 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4197 * Turbo will still be enabled, but won't go above the set value.
4199 if (IS_VALLEYVIEW(dev
)) {
4200 val
= intel_freq_opcode(dev_priv
, val
);
4202 hw_max
= dev_priv
->rps
.max_freq
;
4203 hw_min
= dev_priv
->rps
.min_freq
;
4205 val
= intel_freq_opcode(dev_priv
, val
);
4207 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
4208 hw_max
= dev_priv
->rps
.max_freq
;
4209 hw_min
= (rp_state_cap
>> 16) & 0xff;
4212 if (val
< hw_min
|| val
> hw_max
|| val
< dev_priv
->rps
.min_freq_softlimit
) {
4213 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4217 dev_priv
->rps
.max_freq_softlimit
= val
;
4219 intel_set_rps(dev
, val
);
4221 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4226 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops
,
4227 i915_max_freq_get
, i915_max_freq_set
,
4231 i915_min_freq_get(void *data
, u64
*val
)
4233 struct drm_device
*dev
= data
;
4234 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4237 if (INTEL_INFO(dev
)->gen
< 6)
4240 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4242 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4246 *val
= intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq_softlimit
);
4247 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4253 i915_min_freq_set(void *data
, u64 val
)
4255 struct drm_device
*dev
= data
;
4256 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4257 u32 rp_state_cap
, hw_max
, hw_min
;
4260 if (INTEL_INFO(dev
)->gen
< 6)
4263 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4265 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val
);
4267 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4272 * Turbo will still be enabled, but won't go below the set value.
4274 if (IS_VALLEYVIEW(dev
)) {
4275 val
= intel_freq_opcode(dev_priv
, val
);
4277 hw_max
= dev_priv
->rps
.max_freq
;
4278 hw_min
= dev_priv
->rps
.min_freq
;
4280 val
= intel_freq_opcode(dev_priv
, val
);
4282 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
4283 hw_max
= dev_priv
->rps
.max_freq
;
4284 hw_min
= (rp_state_cap
>> 16) & 0xff;
4287 if (val
< hw_min
|| val
> hw_max
|| val
> dev_priv
->rps
.max_freq_softlimit
) {
4288 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4292 dev_priv
->rps
.min_freq_softlimit
= val
;
4294 intel_set_rps(dev
, val
);
4296 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4301 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops
,
4302 i915_min_freq_get
, i915_min_freq_set
,
4306 i915_cache_sharing_get(void *data
, u64
*val
)
4308 struct drm_device
*dev
= data
;
4309 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4313 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
4316 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4319 intel_runtime_pm_get(dev_priv
);
4321 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
4323 intel_runtime_pm_put(dev_priv
);
4324 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
4326 *val
= (snpcr
& GEN6_MBC_SNPCR_MASK
) >> GEN6_MBC_SNPCR_SHIFT
;
4332 i915_cache_sharing_set(void *data
, u64 val
)
4334 struct drm_device
*dev
= data
;
4335 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4338 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
4344 intel_runtime_pm_get(dev_priv
);
4345 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val
);
4347 /* Update the cache sharing policy here as well */
4348 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
4349 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
4350 snpcr
|= (val
<< GEN6_MBC_SNPCR_SHIFT
);
4351 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
4353 intel_runtime_pm_put(dev_priv
);
4357 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops
,
4358 i915_cache_sharing_get
, i915_cache_sharing_set
,
4361 static int i915_sseu_status(struct seq_file
*m
, void *unused
)
4363 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
4364 struct drm_device
*dev
= node
->minor
->dev
;
4365 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4366 unsigned int s_tot
= 0, ss_tot
= 0, ss_per
= 0, eu_tot
= 0, eu_per
= 0;
4368 if (INTEL_INFO(dev
)->gen
< 9)
4371 seq_puts(m
, "SSEU Device Info\n");
4372 seq_printf(m
, " Available Slice Total: %u\n",
4373 INTEL_INFO(dev
)->slice_total
);
4374 seq_printf(m
, " Available Subslice Total: %u\n",
4375 INTEL_INFO(dev
)->subslice_total
);
4376 seq_printf(m
, " Available Subslice Per Slice: %u\n",
4377 INTEL_INFO(dev
)->subslice_per_slice
);
4378 seq_printf(m
, " Available EU Total: %u\n",
4379 INTEL_INFO(dev
)->eu_total
);
4380 seq_printf(m
, " Available EU Per Subslice: %u\n",
4381 INTEL_INFO(dev
)->eu_per_subslice
);
4382 seq_printf(m
, " Has Slice Power Gating: %s\n",
4383 yesno(INTEL_INFO(dev
)->has_slice_pg
));
4384 seq_printf(m
, " Has Subslice Power Gating: %s\n",
4385 yesno(INTEL_INFO(dev
)->has_subslice_pg
));
4386 seq_printf(m
, " Has EU Power Gating: %s\n",
4387 yesno(INTEL_INFO(dev
)->has_eu_pg
));
4389 seq_puts(m
, "SSEU Device Status\n");
4390 if (IS_SKYLAKE(dev
)) {
4391 const int s_max
= 3, ss_max
= 4;
4393 u32 s_reg
[s_max
], eu_reg
[2*s_max
], eu_mask
[2];
4395 s_reg
[0] = I915_READ(GEN9_SLICE0_PGCTL_ACK
);
4396 s_reg
[1] = I915_READ(GEN9_SLICE1_PGCTL_ACK
);
4397 s_reg
[2] = I915_READ(GEN9_SLICE2_PGCTL_ACK
);
4398 eu_reg
[0] = I915_READ(GEN9_SLICE0_SS01_EU_PGCTL_ACK
);
4399 eu_reg
[1] = I915_READ(GEN9_SLICE0_SS23_EU_PGCTL_ACK
);
4400 eu_reg
[2] = I915_READ(GEN9_SLICE1_SS01_EU_PGCTL_ACK
);
4401 eu_reg
[3] = I915_READ(GEN9_SLICE1_SS23_EU_PGCTL_ACK
);
4402 eu_reg
[4] = I915_READ(GEN9_SLICE2_SS01_EU_PGCTL_ACK
);
4403 eu_reg
[5] = I915_READ(GEN9_SLICE2_SS23_EU_PGCTL_ACK
);
4404 eu_mask
[0] = GEN9_PGCTL_SSA_EU08_ACK
|
4405 GEN9_PGCTL_SSA_EU19_ACK
|
4406 GEN9_PGCTL_SSA_EU210_ACK
|
4407 GEN9_PGCTL_SSA_EU311_ACK
;
4408 eu_mask
[1] = GEN9_PGCTL_SSB_EU08_ACK
|
4409 GEN9_PGCTL_SSB_EU19_ACK
|
4410 GEN9_PGCTL_SSB_EU210_ACK
|
4411 GEN9_PGCTL_SSB_EU311_ACK
;
4413 for (s
= 0; s
< s_max
; s
++) {
4414 if ((s_reg
[s
] & GEN9_PGCTL_SLICE_ACK
) == 0)
4415 /* skip disabled slice */
4419 ss_per
= INTEL_INFO(dev
)->subslice_per_slice
;
4421 for (ss
= 0; ss
< ss_max
; ss
++) {
4422 unsigned int eu_cnt
;
4424 eu_cnt
= 2 * hweight32(eu_reg
[2*s
+ ss
/2] &
4427 eu_per
= max(eu_per
, eu_cnt
);
4431 seq_printf(m
, " Enabled Slice Total: %u\n", s_tot
);
4432 seq_printf(m
, " Enabled Subslice Total: %u\n", ss_tot
);
4433 seq_printf(m
, " Enabled Subslice Per Slice: %u\n", ss_per
);
4434 seq_printf(m
, " Enabled EU Total: %u\n", eu_tot
);
4435 seq_printf(m
, " Enabled EU Per Subslice: %u\n", eu_per
);
4440 static int i915_forcewake_open(struct inode
*inode
, struct file
*file
)
4442 struct drm_device
*dev
= inode
->i_private
;
4443 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4445 if (INTEL_INFO(dev
)->gen
< 6)
4448 intel_runtime_pm_get(dev_priv
);
4449 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4454 static int i915_forcewake_release(struct inode
*inode
, struct file
*file
)
4456 struct drm_device
*dev
= inode
->i_private
;
4457 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4459 if (INTEL_INFO(dev
)->gen
< 6)
4462 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4463 intel_runtime_pm_put(dev_priv
);
4468 static const struct file_operations i915_forcewake_fops
= {
4469 .owner
= THIS_MODULE
,
4470 .open
= i915_forcewake_open
,
4471 .release
= i915_forcewake_release
,
4474 static int i915_forcewake_create(struct dentry
*root
, struct drm_minor
*minor
)
4476 struct drm_device
*dev
= minor
->dev
;
4479 ent
= debugfs_create_file("i915_forcewake_user",
4482 &i915_forcewake_fops
);
4486 return drm_add_fake_info_node(minor
, ent
, &i915_forcewake_fops
);
4489 static int i915_debugfs_create(struct dentry
*root
,
4490 struct drm_minor
*minor
,
4492 const struct file_operations
*fops
)
4494 struct drm_device
*dev
= minor
->dev
;
4497 ent
= debugfs_create_file(name
,
4504 return drm_add_fake_info_node(minor
, ent
, fops
);
4507 static const struct drm_info_list i915_debugfs_list
[] = {
4508 {"i915_capabilities", i915_capabilities
, 0},
4509 {"i915_gem_objects", i915_gem_object_info
, 0},
4510 {"i915_gem_gtt", i915_gem_gtt_info
, 0},
4511 {"i915_gem_pinned", i915_gem_gtt_info
, 0, (void *) PINNED_LIST
},
4512 {"i915_gem_active", i915_gem_object_list_info
, 0, (void *) ACTIVE_LIST
},
4513 {"i915_gem_inactive", i915_gem_object_list_info
, 0, (void *) INACTIVE_LIST
},
4514 {"i915_gem_stolen", i915_gem_stolen_list_info
},
4515 {"i915_gem_pageflip", i915_gem_pageflip_info
, 0},
4516 {"i915_gem_request", i915_gem_request_info
, 0},
4517 {"i915_gem_seqno", i915_gem_seqno_info
, 0},
4518 {"i915_gem_fence_regs", i915_gem_fence_regs_info
, 0},
4519 {"i915_gem_interrupt", i915_interrupt_info
, 0},
4520 {"i915_gem_hws", i915_hws_info
, 0, (void *)RCS
},
4521 {"i915_gem_hws_blt", i915_hws_info
, 0, (void *)BCS
},
4522 {"i915_gem_hws_bsd", i915_hws_info
, 0, (void *)VCS
},
4523 {"i915_gem_hws_vebox", i915_hws_info
, 0, (void *)VECS
},
4524 {"i915_gem_batch_pool", i915_gem_batch_pool_info
, 0},
4525 {"i915_frequency_info", i915_frequency_info
, 0},
4526 {"i915_hangcheck_info", i915_hangcheck_info
, 0},
4527 {"i915_drpc_info", i915_drpc_info
, 0},
4528 {"i915_emon_status", i915_emon_status
, 0},
4529 {"i915_ring_freq_table", i915_ring_freq_table
, 0},
4530 {"i915_fbc_status", i915_fbc_status
, 0},
4531 {"i915_ips_status", i915_ips_status
, 0},
4532 {"i915_sr_status", i915_sr_status
, 0},
4533 {"i915_opregion", i915_opregion
, 0},
4534 {"i915_gem_framebuffer", i915_gem_framebuffer_info
, 0},
4535 {"i915_context_status", i915_context_status
, 0},
4536 {"i915_dump_lrc", i915_dump_lrc
, 0},
4537 {"i915_execlists", i915_execlists
, 0},
4538 {"i915_forcewake_domains", i915_forcewake_domains
, 0},
4539 {"i915_swizzle_info", i915_swizzle_info
, 0},
4540 {"i915_ppgtt_info", i915_ppgtt_info
, 0},
4541 {"i915_llc", i915_llc
, 0},
4542 {"i915_edp_psr_status", i915_edp_psr_status
, 0},
4543 {"i915_sink_crc_eDP1", i915_sink_crc
, 0},
4544 {"i915_energy_uJ", i915_energy_uJ
, 0},
4545 {"i915_pc8_status", i915_pc8_status
, 0},
4546 {"i915_power_domain_info", i915_power_domain_info
, 0},
4547 {"i915_display_info", i915_display_info
, 0},
4548 {"i915_semaphore_status", i915_semaphore_status
, 0},
4549 {"i915_shared_dplls_info", i915_shared_dplls_info
, 0},
4550 {"i915_dp_mst_info", i915_dp_mst_info
, 0},
4551 {"i915_wa_registers", i915_wa_registers
, 0},
4552 {"i915_ddb_info", i915_ddb_info
, 0},
4553 {"i915_sseu_status", i915_sseu_status
, 0},
4555 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
4557 static const struct i915_debugfs_files
{
4559 const struct file_operations
*fops
;
4560 } i915_debugfs_files
[] = {
4561 {"i915_wedged", &i915_wedged_fops
},
4562 {"i915_max_freq", &i915_max_freq_fops
},
4563 {"i915_min_freq", &i915_min_freq_fops
},
4564 {"i915_cache_sharing", &i915_cache_sharing_fops
},
4565 {"i915_ring_stop", &i915_ring_stop_fops
},
4566 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops
},
4567 {"i915_ring_test_irq", &i915_ring_test_irq_fops
},
4568 {"i915_gem_drop_caches", &i915_drop_caches_fops
},
4569 {"i915_error_state", &i915_error_state_fops
},
4570 {"i915_next_seqno", &i915_next_seqno_fops
},
4571 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops
},
4572 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops
},
4573 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops
},
4574 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops
},
4575 {"i915_fbc_false_color", &i915_fbc_fc_fops
},
4578 void intel_display_crc_init(struct drm_device
*dev
)
4580 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4583 for_each_pipe(dev_priv
, pipe
) {
4584 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
4586 pipe_crc
->opened
= false;
4587 spin_lock_init(&pipe_crc
->lock
);
4588 init_waitqueue_head(&pipe_crc
->wq
);
4592 int i915_debugfs_init(struct drm_minor
*minor
)
4596 ret
= i915_forcewake_create(minor
->debugfs_root
, minor
);
4600 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
4601 ret
= i915_pipe_crc_create(minor
->debugfs_root
, minor
, i
);
4606 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
4607 ret
= i915_debugfs_create(minor
->debugfs_root
, minor
,
4608 i915_debugfs_files
[i
].name
,
4609 i915_debugfs_files
[i
].fops
);
4614 return drm_debugfs_create_files(i915_debugfs_list
,
4615 I915_DEBUGFS_ENTRIES
,
4616 minor
->debugfs_root
, minor
);
4619 void i915_debugfs_cleanup(struct drm_minor
*minor
)
4623 drm_debugfs_remove_files(i915_debugfs_list
,
4624 I915_DEBUGFS_ENTRIES
, minor
);
4626 drm_debugfs_remove_files((struct drm_info_list
*) &i915_forcewake_fops
,
4629 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
4630 struct drm_info_list
*info_list
=
4631 (struct drm_info_list
*)&i915_pipe_crc_data
[i
];
4633 drm_debugfs_remove_files(info_list
, 1, minor
);
4636 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
4637 struct drm_info_list
*info_list
=
4638 (struct drm_info_list
*) i915_debugfs_files
[i
].fops
;
4640 drm_debugfs_remove_files(info_list
, 1, minor
);