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[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29 #include <linux/seq_file.h>
30 #include <linux/debugfs.h>
31 #include <linux/slab.h>
32 #include <linux/export.h>
33 #include <generated/utsrelease.h>
34 #include <drm/drmP.h>
35 #include "intel_drv.h"
36 #include "intel_ringbuffer.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39
40 #define DRM_I915_RING_DEBUG 1
41
42
43 #if defined(CONFIG_DEBUG_FS)
44
45 enum {
46 ACTIVE_LIST,
47 INACTIVE_LIST,
48 PINNED_LIST,
49 };
50
51 static const char *yesno(int v)
52 {
53 return v ? "yes" : "no";
54 }
55
56 static int i915_capabilities(struct seq_file *m, void *data)
57 {
58 struct drm_info_node *node = (struct drm_info_node *) m->private;
59 struct drm_device *dev = node->minor->dev;
60 const struct intel_device_info *info = INTEL_INFO(dev);
61
62 seq_printf(m, "gen: %d\n", info->gen);
63 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
64 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
65 #define SEP_SEMICOLON ;
66 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
67 #undef PRINT_FLAG
68 #undef SEP_SEMICOLON
69
70 return 0;
71 }
72
73 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
74 {
75 if (obj->user_pin_count > 0)
76 return "P";
77 else if (obj->pin_count > 0)
78 return "p";
79 else
80 return " ";
81 }
82
83 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
84 {
85 switch (obj->tiling_mode) {
86 default:
87 case I915_TILING_NONE: return " ";
88 case I915_TILING_X: return "X";
89 case I915_TILING_Y: return "Y";
90 }
91 }
92
93 static const char *cache_level_str(int type)
94 {
95 switch (type) {
96 case I915_CACHE_NONE: return " uncached";
97 case I915_CACHE_LLC: return " snooped (LLC)";
98 case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)";
99 default: return "";
100 }
101 }
102
103 static void
104 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
105 {
106 seq_printf(m, "%pK: %s%s %8zdKiB %02x %02x %d %d %d%s%s%s",
107 &obj->base,
108 get_pin_flag(obj),
109 get_tiling_flag(obj),
110 obj->base.size / 1024,
111 obj->base.read_domains,
112 obj->base.write_domain,
113 obj->last_read_seqno,
114 obj->last_write_seqno,
115 obj->last_fenced_seqno,
116 cache_level_str(obj->cache_level),
117 obj->dirty ? " dirty" : "",
118 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
119 if (obj->base.name)
120 seq_printf(m, " (name: %d)", obj->base.name);
121 if (obj->pin_count)
122 seq_printf(m, " (pinned x %d)", obj->pin_count);
123 if (obj->fence_reg != I915_FENCE_REG_NONE)
124 seq_printf(m, " (fence: %d)", obj->fence_reg);
125 if (obj->gtt_space != NULL)
126 seq_printf(m, " (gtt offset: %08x, size: %08x)",
127 obj->gtt_offset, (unsigned int)obj->gtt_space->size);
128 if (obj->stolen)
129 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
130 if (obj->pin_mappable || obj->fault_mappable) {
131 char s[3], *t = s;
132 if (obj->pin_mappable)
133 *t++ = 'p';
134 if (obj->fault_mappable)
135 *t++ = 'f';
136 *t = '\0';
137 seq_printf(m, " (%s mappable)", s);
138 }
139 if (obj->ring != NULL)
140 seq_printf(m, " (%s)", obj->ring->name);
141 }
142
143 static int i915_gem_object_list_info(struct seq_file *m, void *data)
144 {
145 struct drm_info_node *node = (struct drm_info_node *) m->private;
146 uintptr_t list = (uintptr_t) node->info_ent->data;
147 struct list_head *head;
148 struct drm_device *dev = node->minor->dev;
149 drm_i915_private_t *dev_priv = dev->dev_private;
150 struct drm_i915_gem_object *obj;
151 size_t total_obj_size, total_gtt_size;
152 int count, ret;
153
154 ret = mutex_lock_interruptible(&dev->struct_mutex);
155 if (ret)
156 return ret;
157
158 switch (list) {
159 case ACTIVE_LIST:
160 seq_puts(m, "Active:\n");
161 head = &dev_priv->mm.active_list;
162 break;
163 case INACTIVE_LIST:
164 seq_puts(m, "Inactive:\n");
165 head = &dev_priv->mm.inactive_list;
166 break;
167 default:
168 mutex_unlock(&dev->struct_mutex);
169 return -EINVAL;
170 }
171
172 total_obj_size = total_gtt_size = count = 0;
173 list_for_each_entry(obj, head, mm_list) {
174 seq_puts(m, " ");
175 describe_obj(m, obj);
176 seq_putc(m, '\n');
177 total_obj_size += obj->base.size;
178 total_gtt_size += obj->gtt_space->size;
179 count++;
180 }
181 mutex_unlock(&dev->struct_mutex);
182
183 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
184 count, total_obj_size, total_gtt_size);
185 return 0;
186 }
187
188 #define count_objects(list, member) do { \
189 list_for_each_entry(obj, list, member) { \
190 size += obj->gtt_space->size; \
191 ++count; \
192 if (obj->map_and_fenceable) { \
193 mappable_size += obj->gtt_space->size; \
194 ++mappable_count; \
195 } \
196 } \
197 } while (0)
198
199 struct file_stats {
200 int count;
201 size_t total, active, inactive, unbound;
202 };
203
204 static int per_file_stats(int id, void *ptr, void *data)
205 {
206 struct drm_i915_gem_object *obj = ptr;
207 struct file_stats *stats = data;
208
209 stats->count++;
210 stats->total += obj->base.size;
211
212 if (obj->gtt_space) {
213 if (!list_empty(&obj->ring_list))
214 stats->active += obj->base.size;
215 else
216 stats->inactive += obj->base.size;
217 } else {
218 if (!list_empty(&obj->global_list))
219 stats->unbound += obj->base.size;
220 }
221
222 return 0;
223 }
224
225 static int i915_gem_object_info(struct seq_file *m, void *data)
226 {
227 struct drm_info_node *node = (struct drm_info_node *) m->private;
228 struct drm_device *dev = node->minor->dev;
229 struct drm_i915_private *dev_priv = dev->dev_private;
230 u32 count, mappable_count, purgeable_count;
231 size_t size, mappable_size, purgeable_size;
232 struct drm_i915_gem_object *obj;
233 struct drm_file *file;
234 int ret;
235
236 ret = mutex_lock_interruptible(&dev->struct_mutex);
237 if (ret)
238 return ret;
239
240 seq_printf(m, "%u objects, %zu bytes\n",
241 dev_priv->mm.object_count,
242 dev_priv->mm.object_memory);
243
244 size = count = mappable_size = mappable_count = 0;
245 count_objects(&dev_priv->mm.bound_list, global_list);
246 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
247 count, mappable_count, size, mappable_size);
248
249 size = count = mappable_size = mappable_count = 0;
250 count_objects(&dev_priv->mm.active_list, mm_list);
251 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
252 count, mappable_count, size, mappable_size);
253
254 size = count = mappable_size = mappable_count = 0;
255 count_objects(&dev_priv->mm.inactive_list, mm_list);
256 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
257 count, mappable_count, size, mappable_size);
258
259 size = count = purgeable_size = purgeable_count = 0;
260 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
261 size += obj->base.size, ++count;
262 if (obj->madv == I915_MADV_DONTNEED)
263 purgeable_size += obj->base.size, ++purgeable_count;
264 }
265 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
266
267 size = count = mappable_size = mappable_count = 0;
268 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
269 if (obj->fault_mappable) {
270 size += obj->gtt_space->size;
271 ++count;
272 }
273 if (obj->pin_mappable) {
274 mappable_size += obj->gtt_space->size;
275 ++mappable_count;
276 }
277 if (obj->madv == I915_MADV_DONTNEED) {
278 purgeable_size += obj->base.size;
279 ++purgeable_count;
280 }
281 }
282 seq_printf(m, "%u purgeable objects, %zu bytes\n",
283 purgeable_count, purgeable_size);
284 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
285 mappable_count, mappable_size);
286 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
287 count, size);
288
289 seq_printf(m, "%zu [%lu] gtt total\n",
290 dev_priv->gtt.total,
291 dev_priv->gtt.mappable_end - dev_priv->gtt.start);
292
293 seq_putc(m, '\n');
294 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
295 struct file_stats stats;
296
297 memset(&stats, 0, sizeof(stats));
298 idr_for_each(&file->object_idr, per_file_stats, &stats);
299 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n",
300 get_pid_task(file->pid, PIDTYPE_PID)->comm,
301 stats.count,
302 stats.total,
303 stats.active,
304 stats.inactive,
305 stats.unbound);
306 }
307
308 mutex_unlock(&dev->struct_mutex);
309
310 return 0;
311 }
312
313 static int i915_gem_gtt_info(struct seq_file *m, void *data)
314 {
315 struct drm_info_node *node = (struct drm_info_node *) m->private;
316 struct drm_device *dev = node->minor->dev;
317 uintptr_t list = (uintptr_t) node->info_ent->data;
318 struct drm_i915_private *dev_priv = dev->dev_private;
319 struct drm_i915_gem_object *obj;
320 size_t total_obj_size, total_gtt_size;
321 int count, ret;
322
323 ret = mutex_lock_interruptible(&dev->struct_mutex);
324 if (ret)
325 return ret;
326
327 total_obj_size = total_gtt_size = count = 0;
328 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
329 if (list == PINNED_LIST && obj->pin_count == 0)
330 continue;
331
332 seq_puts(m, " ");
333 describe_obj(m, obj);
334 seq_putc(m, '\n');
335 total_obj_size += obj->base.size;
336 total_gtt_size += obj->gtt_space->size;
337 count++;
338 }
339
340 mutex_unlock(&dev->struct_mutex);
341
342 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
343 count, total_obj_size, total_gtt_size);
344
345 return 0;
346 }
347
348 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
349 {
350 struct drm_info_node *node = (struct drm_info_node *) m->private;
351 struct drm_device *dev = node->minor->dev;
352 unsigned long flags;
353 struct intel_crtc *crtc;
354
355 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
356 const char pipe = pipe_name(crtc->pipe);
357 const char plane = plane_name(crtc->plane);
358 struct intel_unpin_work *work;
359
360 spin_lock_irqsave(&dev->event_lock, flags);
361 work = crtc->unpin_work;
362 if (work == NULL) {
363 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
364 pipe, plane);
365 } else {
366 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
367 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
368 pipe, plane);
369 } else {
370 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
371 pipe, plane);
372 }
373 if (work->enable_stall_check)
374 seq_puts(m, "Stall check enabled, ");
375 else
376 seq_puts(m, "Stall check waiting for page flip ioctl, ");
377 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
378
379 if (work->old_fb_obj) {
380 struct drm_i915_gem_object *obj = work->old_fb_obj;
381 if (obj)
382 seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
383 }
384 if (work->pending_flip_obj) {
385 struct drm_i915_gem_object *obj = work->pending_flip_obj;
386 if (obj)
387 seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
388 }
389 }
390 spin_unlock_irqrestore(&dev->event_lock, flags);
391 }
392
393 return 0;
394 }
395
396 static int i915_gem_request_info(struct seq_file *m, void *data)
397 {
398 struct drm_info_node *node = (struct drm_info_node *) m->private;
399 struct drm_device *dev = node->minor->dev;
400 drm_i915_private_t *dev_priv = dev->dev_private;
401 struct intel_ring_buffer *ring;
402 struct drm_i915_gem_request *gem_request;
403 int ret, count, i;
404
405 ret = mutex_lock_interruptible(&dev->struct_mutex);
406 if (ret)
407 return ret;
408
409 count = 0;
410 for_each_ring(ring, dev_priv, i) {
411 if (list_empty(&ring->request_list))
412 continue;
413
414 seq_printf(m, "%s requests:\n", ring->name);
415 list_for_each_entry(gem_request,
416 &ring->request_list,
417 list) {
418 seq_printf(m, " %d @ %d\n",
419 gem_request->seqno,
420 (int) (jiffies - gem_request->emitted_jiffies));
421 }
422 count++;
423 }
424 mutex_unlock(&dev->struct_mutex);
425
426 if (count == 0)
427 seq_puts(m, "No requests\n");
428
429 return 0;
430 }
431
432 static void i915_ring_seqno_info(struct seq_file *m,
433 struct intel_ring_buffer *ring)
434 {
435 if (ring->get_seqno) {
436 seq_printf(m, "Current sequence (%s): %u\n",
437 ring->name, ring->get_seqno(ring, false));
438 }
439 }
440
441 static int i915_gem_seqno_info(struct seq_file *m, void *data)
442 {
443 struct drm_info_node *node = (struct drm_info_node *) m->private;
444 struct drm_device *dev = node->minor->dev;
445 drm_i915_private_t *dev_priv = dev->dev_private;
446 struct intel_ring_buffer *ring;
447 int ret, i;
448
449 ret = mutex_lock_interruptible(&dev->struct_mutex);
450 if (ret)
451 return ret;
452
453 for_each_ring(ring, dev_priv, i)
454 i915_ring_seqno_info(m, ring);
455
456 mutex_unlock(&dev->struct_mutex);
457
458 return 0;
459 }
460
461
462 static int i915_interrupt_info(struct seq_file *m, void *data)
463 {
464 struct drm_info_node *node = (struct drm_info_node *) m->private;
465 struct drm_device *dev = node->minor->dev;
466 drm_i915_private_t *dev_priv = dev->dev_private;
467 struct intel_ring_buffer *ring;
468 int ret, i, pipe;
469
470 ret = mutex_lock_interruptible(&dev->struct_mutex);
471 if (ret)
472 return ret;
473
474 if (IS_VALLEYVIEW(dev)) {
475 seq_printf(m, "Display IER:\t%08x\n",
476 I915_READ(VLV_IER));
477 seq_printf(m, "Display IIR:\t%08x\n",
478 I915_READ(VLV_IIR));
479 seq_printf(m, "Display IIR_RW:\t%08x\n",
480 I915_READ(VLV_IIR_RW));
481 seq_printf(m, "Display IMR:\t%08x\n",
482 I915_READ(VLV_IMR));
483 for_each_pipe(pipe)
484 seq_printf(m, "Pipe %c stat:\t%08x\n",
485 pipe_name(pipe),
486 I915_READ(PIPESTAT(pipe)));
487
488 seq_printf(m, "Master IER:\t%08x\n",
489 I915_READ(VLV_MASTER_IER));
490
491 seq_printf(m, "Render IER:\t%08x\n",
492 I915_READ(GTIER));
493 seq_printf(m, "Render IIR:\t%08x\n",
494 I915_READ(GTIIR));
495 seq_printf(m, "Render IMR:\t%08x\n",
496 I915_READ(GTIMR));
497
498 seq_printf(m, "PM IER:\t\t%08x\n",
499 I915_READ(GEN6_PMIER));
500 seq_printf(m, "PM IIR:\t\t%08x\n",
501 I915_READ(GEN6_PMIIR));
502 seq_printf(m, "PM IMR:\t\t%08x\n",
503 I915_READ(GEN6_PMIMR));
504
505 seq_printf(m, "Port hotplug:\t%08x\n",
506 I915_READ(PORT_HOTPLUG_EN));
507 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
508 I915_READ(VLV_DPFLIPSTAT));
509 seq_printf(m, "DPINVGTT:\t%08x\n",
510 I915_READ(DPINVGTT));
511
512 } else if (!HAS_PCH_SPLIT(dev)) {
513 seq_printf(m, "Interrupt enable: %08x\n",
514 I915_READ(IER));
515 seq_printf(m, "Interrupt identity: %08x\n",
516 I915_READ(IIR));
517 seq_printf(m, "Interrupt mask: %08x\n",
518 I915_READ(IMR));
519 for_each_pipe(pipe)
520 seq_printf(m, "Pipe %c stat: %08x\n",
521 pipe_name(pipe),
522 I915_READ(PIPESTAT(pipe)));
523 } else {
524 seq_printf(m, "North Display Interrupt enable: %08x\n",
525 I915_READ(DEIER));
526 seq_printf(m, "North Display Interrupt identity: %08x\n",
527 I915_READ(DEIIR));
528 seq_printf(m, "North Display Interrupt mask: %08x\n",
529 I915_READ(DEIMR));
530 seq_printf(m, "South Display Interrupt enable: %08x\n",
531 I915_READ(SDEIER));
532 seq_printf(m, "South Display Interrupt identity: %08x\n",
533 I915_READ(SDEIIR));
534 seq_printf(m, "South Display Interrupt mask: %08x\n",
535 I915_READ(SDEIMR));
536 seq_printf(m, "Graphics Interrupt enable: %08x\n",
537 I915_READ(GTIER));
538 seq_printf(m, "Graphics Interrupt identity: %08x\n",
539 I915_READ(GTIIR));
540 seq_printf(m, "Graphics Interrupt mask: %08x\n",
541 I915_READ(GTIMR));
542 }
543 seq_printf(m, "Interrupts received: %d\n",
544 atomic_read(&dev_priv->irq_received));
545 for_each_ring(ring, dev_priv, i) {
546 if (IS_GEN6(dev) || IS_GEN7(dev)) {
547 seq_printf(m,
548 "Graphics Interrupt mask (%s): %08x\n",
549 ring->name, I915_READ_IMR(ring));
550 }
551 i915_ring_seqno_info(m, ring);
552 }
553 mutex_unlock(&dev->struct_mutex);
554
555 return 0;
556 }
557
558 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
559 {
560 struct drm_info_node *node = (struct drm_info_node *) m->private;
561 struct drm_device *dev = node->minor->dev;
562 drm_i915_private_t *dev_priv = dev->dev_private;
563 int i, ret;
564
565 ret = mutex_lock_interruptible(&dev->struct_mutex);
566 if (ret)
567 return ret;
568
569 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
570 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
571 for (i = 0; i < dev_priv->num_fence_regs; i++) {
572 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
573
574 seq_printf(m, "Fence %d, pin count = %d, object = ",
575 i, dev_priv->fence_regs[i].pin_count);
576 if (obj == NULL)
577 seq_puts(m, "unused");
578 else
579 describe_obj(m, obj);
580 seq_putc(m, '\n');
581 }
582
583 mutex_unlock(&dev->struct_mutex);
584 return 0;
585 }
586
587 static int i915_hws_info(struct seq_file *m, void *data)
588 {
589 struct drm_info_node *node = (struct drm_info_node *) m->private;
590 struct drm_device *dev = node->minor->dev;
591 drm_i915_private_t *dev_priv = dev->dev_private;
592 struct intel_ring_buffer *ring;
593 const u32 *hws;
594 int i;
595
596 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
597 hws = ring->status_page.page_addr;
598 if (hws == NULL)
599 return 0;
600
601 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
602 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
603 i * 4,
604 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
605 }
606 return 0;
607 }
608
609 static const char *ring_str(int ring)
610 {
611 switch (ring) {
612 case RCS: return "render";
613 case VCS: return "bsd";
614 case BCS: return "blt";
615 case VECS: return "vebox";
616 default: return "";
617 }
618 }
619
620 static const char *pin_flag(int pinned)
621 {
622 if (pinned > 0)
623 return " P";
624 else if (pinned < 0)
625 return " p";
626 else
627 return "";
628 }
629
630 static const char *tiling_flag(int tiling)
631 {
632 switch (tiling) {
633 default:
634 case I915_TILING_NONE: return "";
635 case I915_TILING_X: return " X";
636 case I915_TILING_Y: return " Y";
637 }
638 }
639
640 static const char *dirty_flag(int dirty)
641 {
642 return dirty ? " dirty" : "";
643 }
644
645 static const char *purgeable_flag(int purgeable)
646 {
647 return purgeable ? " purgeable" : "";
648 }
649
650 static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
651 {
652
653 if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
654 e->err = -ENOSPC;
655 return false;
656 }
657
658 if (e->bytes == e->size - 1 || e->err)
659 return false;
660
661 return true;
662 }
663
664 static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
665 unsigned len)
666 {
667 if (e->pos + len <= e->start) {
668 e->pos += len;
669 return false;
670 }
671
672 /* First vsnprintf needs to fit in its entirety for memmove */
673 if (len >= e->size) {
674 e->err = -EIO;
675 return false;
676 }
677
678 return true;
679 }
680
681 static void __i915_error_advance(struct drm_i915_error_state_buf *e,
682 unsigned len)
683 {
684 /* If this is first printf in this window, adjust it so that
685 * start position matches start of the buffer
686 */
687
688 if (e->pos < e->start) {
689 const size_t off = e->start - e->pos;
690
691 /* Should not happen but be paranoid */
692 if (off > len || e->bytes) {
693 e->err = -EIO;
694 return;
695 }
696
697 memmove(e->buf, e->buf + off, len - off);
698 e->bytes = len - off;
699 e->pos = e->start;
700 return;
701 }
702
703 e->bytes += len;
704 e->pos += len;
705 }
706
707 static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
708 const char *f, va_list args)
709 {
710 unsigned len;
711
712 if (!__i915_error_ok(e))
713 return;
714
715 /* Seek the first printf which is hits start position */
716 if (e->pos < e->start) {
717 len = vsnprintf(NULL, 0, f, args);
718 if (!__i915_error_seek(e, len))
719 return;
720 }
721
722 len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
723 if (len >= e->size - e->bytes)
724 len = e->size - e->bytes - 1;
725
726 __i915_error_advance(e, len);
727 }
728
729 static void i915_error_puts(struct drm_i915_error_state_buf *e,
730 const char *str)
731 {
732 unsigned len;
733
734 if (!__i915_error_ok(e))
735 return;
736
737 len = strlen(str);
738
739 /* Seek the first printf which is hits start position */
740 if (e->pos < e->start) {
741 if (!__i915_error_seek(e, len))
742 return;
743 }
744
745 if (len >= e->size - e->bytes)
746 len = e->size - e->bytes - 1;
747 memcpy(e->buf + e->bytes, str, len);
748
749 __i915_error_advance(e, len);
750 }
751
752 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
753 {
754 va_list args;
755
756 va_start(args, f);
757 i915_error_vprintf(e, f, args);
758 va_end(args);
759 }
760
761 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
762 #define err_puts(e, s) i915_error_puts(e, s)
763
764 static void print_error_buffers(struct drm_i915_error_state_buf *m,
765 const char *name,
766 struct drm_i915_error_buffer *err,
767 int count)
768 {
769 err_printf(m, "%s [%d]:\n", name, count);
770
771 while (count--) {
772 err_printf(m, " %08x %8u %02x %02x %x %x",
773 err->gtt_offset,
774 err->size,
775 err->read_domains,
776 err->write_domain,
777 err->rseqno, err->wseqno);
778 err_puts(m, pin_flag(err->pinned));
779 err_puts(m, tiling_flag(err->tiling));
780 err_puts(m, dirty_flag(err->dirty));
781 err_puts(m, purgeable_flag(err->purgeable));
782 err_puts(m, err->ring != -1 ? " " : "");
783 err_puts(m, ring_str(err->ring));
784 err_puts(m, cache_level_str(err->cache_level));
785
786 if (err->name)
787 err_printf(m, " (name: %d)", err->name);
788 if (err->fence_reg != I915_FENCE_REG_NONE)
789 err_printf(m, " (fence: %d)", err->fence_reg);
790
791 err_puts(m, "\n");
792 err++;
793 }
794 }
795
796 static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
797 struct drm_device *dev,
798 struct drm_i915_error_state *error,
799 unsigned ring)
800 {
801 BUG_ON(ring >= I915_NUM_RINGS); /* shut up confused gcc */
802 err_printf(m, "%s command stream:\n", ring_str(ring));
803 err_printf(m, " HEAD: 0x%08x\n", error->head[ring]);
804 err_printf(m, " TAIL: 0x%08x\n", error->tail[ring]);
805 err_printf(m, " CTL: 0x%08x\n", error->ctl[ring]);
806 err_printf(m, " ACTHD: 0x%08x\n", error->acthd[ring]);
807 err_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]);
808 err_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]);
809 err_printf(m, " INSTDONE: 0x%08x\n", error->instdone[ring]);
810 if (ring == RCS && INTEL_INFO(dev)->gen >= 4)
811 err_printf(m, " BBADDR: 0x%08llx\n", error->bbaddr);
812
813 if (INTEL_INFO(dev)->gen >= 4)
814 err_printf(m, " INSTPS: 0x%08x\n", error->instps[ring]);
815 err_printf(m, " INSTPM: 0x%08x\n", error->instpm[ring]);
816 err_printf(m, " FADDR: 0x%08x\n", error->faddr[ring]);
817 if (INTEL_INFO(dev)->gen >= 6) {
818 err_printf(m, " RC PSMI: 0x%08x\n", error->rc_psmi[ring]);
819 err_printf(m, " FAULT_REG: 0x%08x\n", error->fault_reg[ring]);
820 err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n",
821 error->semaphore_mboxes[ring][0],
822 error->semaphore_seqno[ring][0]);
823 err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n",
824 error->semaphore_mboxes[ring][1],
825 error->semaphore_seqno[ring][1]);
826 }
827 err_printf(m, " seqno: 0x%08x\n", error->seqno[ring]);
828 err_printf(m, " waiting: %s\n", yesno(error->waiting[ring]));
829 err_printf(m, " ring->head: 0x%08x\n", error->cpu_ring_head[ring]);
830 err_printf(m, " ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]);
831 }
832
833 int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
834 const struct i915_error_state_file_priv *error_priv)
835 {
836 struct drm_device *dev = error_priv->dev;
837 drm_i915_private_t *dev_priv = dev->dev_private;
838 struct drm_i915_error_state *error = error_priv->error;
839 struct intel_ring_buffer *ring;
840 int i, j, page, offset, elt;
841
842 if (!error) {
843 err_printf(m, "no error state collected\n");
844 goto out;
845 }
846
847 err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
848 error->time.tv_usec);
849 err_printf(m, "Kernel: " UTS_RELEASE "\n");
850 err_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
851 err_printf(m, "EIR: 0x%08x\n", error->eir);
852 err_printf(m, "IER: 0x%08x\n", error->ier);
853 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
854 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
855 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
856 err_printf(m, "CCID: 0x%08x\n", error->ccid);
857
858 for (i = 0; i < dev_priv->num_fence_regs; i++)
859 err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
860
861 for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
862 err_printf(m, " INSTDONE_%d: 0x%08x\n", i,
863 error->extra_instdone[i]);
864
865 if (INTEL_INFO(dev)->gen >= 6) {
866 err_printf(m, "ERROR: 0x%08x\n", error->error);
867 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
868 }
869
870 if (INTEL_INFO(dev)->gen == 7)
871 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
872
873 for_each_ring(ring, dev_priv, i)
874 i915_ring_error_state(m, dev, error, i);
875
876 if (error->active_bo)
877 print_error_buffers(m, "Active",
878 error->active_bo,
879 error->active_bo_count);
880
881 if (error->pinned_bo)
882 print_error_buffers(m, "Pinned",
883 error->pinned_bo,
884 error->pinned_bo_count);
885
886 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
887 struct drm_i915_error_object *obj;
888
889 if ((obj = error->ring[i].batchbuffer)) {
890 err_printf(m, "%s --- gtt_offset = 0x%08x\n",
891 dev_priv->ring[i].name,
892 obj->gtt_offset);
893 offset = 0;
894 for (page = 0; page < obj->page_count; page++) {
895 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
896 err_printf(m, "%08x : %08x\n", offset,
897 obj->pages[page][elt]);
898 offset += 4;
899 }
900 }
901 }
902
903 if (error->ring[i].num_requests) {
904 err_printf(m, "%s --- %d requests\n",
905 dev_priv->ring[i].name,
906 error->ring[i].num_requests);
907 for (j = 0; j < error->ring[i].num_requests; j++) {
908 err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
909 error->ring[i].requests[j].seqno,
910 error->ring[i].requests[j].jiffies,
911 error->ring[i].requests[j].tail);
912 }
913 }
914
915 if ((obj = error->ring[i].ringbuffer)) {
916 err_printf(m, "%s --- ringbuffer = 0x%08x\n",
917 dev_priv->ring[i].name,
918 obj->gtt_offset);
919 offset = 0;
920 for (page = 0; page < obj->page_count; page++) {
921 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
922 err_printf(m, "%08x : %08x\n",
923 offset,
924 obj->pages[page][elt]);
925 offset += 4;
926 }
927 }
928 }
929
930 obj = error->ring[i].ctx;
931 if (obj) {
932 err_printf(m, "%s --- HW Context = 0x%08x\n",
933 dev_priv->ring[i].name,
934 obj->gtt_offset);
935 offset = 0;
936 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
937 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
938 offset,
939 obj->pages[0][elt],
940 obj->pages[0][elt+1],
941 obj->pages[0][elt+2],
942 obj->pages[0][elt+3]);
943 offset += 16;
944 }
945 }
946 }
947
948 if (error->overlay)
949 intel_overlay_print_error_state(m, error->overlay);
950
951 if (error->display)
952 intel_display_print_error_state(m, dev, error->display);
953
954 out:
955 if (m->bytes == 0 && m->err)
956 return m->err;
957
958 return 0;
959 }
960
961 static ssize_t
962 i915_error_state_write(struct file *filp,
963 const char __user *ubuf,
964 size_t cnt,
965 loff_t *ppos)
966 {
967 struct i915_error_state_file_priv *error_priv = filp->private_data;
968 struct drm_device *dev = error_priv->dev;
969 int ret;
970
971 DRM_DEBUG_DRIVER("Resetting error state\n");
972
973 ret = mutex_lock_interruptible(&dev->struct_mutex);
974 if (ret)
975 return ret;
976
977 i915_destroy_error_state(dev);
978 mutex_unlock(&dev->struct_mutex);
979
980 return cnt;
981 }
982
983 static int i915_error_state_open(struct inode *inode, struct file *file)
984 {
985 struct drm_device *dev = inode->i_private;
986 drm_i915_private_t *dev_priv = dev->dev_private;
987 struct i915_error_state_file_priv *error_priv;
988 unsigned long flags;
989
990 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
991 if (!error_priv)
992 return -ENOMEM;
993
994 error_priv->dev = dev;
995
996 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
997 error_priv->error = dev_priv->gpu_error.first_error;
998 if (error_priv->error)
999 kref_get(&error_priv->error->ref);
1000 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1001
1002 file->private_data = error_priv;
1003
1004 return 0;
1005 }
1006
1007 static int i915_error_state_release(struct inode *inode, struct file *file)
1008 {
1009 struct i915_error_state_file_priv *error_priv = file->private_data;
1010
1011 if (error_priv->error)
1012 kref_put(&error_priv->error->ref, i915_error_state_free);
1013 kfree(error_priv);
1014
1015 return 0;
1016 }
1017
1018 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1019 size_t count, loff_t *pos)
1020 {
1021 struct i915_error_state_file_priv *error_priv = file->private_data;
1022 struct drm_i915_error_state_buf error_str;
1023 loff_t tmp_pos = 0;
1024 ssize_t ret_count = 0;
1025 int ret = 0;
1026
1027 memset(&error_str, 0, sizeof(error_str));
1028
1029 /* We need to have enough room to store any i915_error_state printf
1030 * so that we can move it to start position.
1031 */
1032 error_str.size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
1033 error_str.buf = kmalloc(error_str.size,
1034 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN);
1035
1036 if (error_str.buf == NULL) {
1037 error_str.size = PAGE_SIZE;
1038 error_str.buf = kmalloc(error_str.size, GFP_TEMPORARY);
1039 }
1040
1041 if (error_str.buf == NULL) {
1042 error_str.size = 128;
1043 error_str.buf = kmalloc(error_str.size, GFP_TEMPORARY);
1044 }
1045
1046 if (error_str.buf == NULL)
1047 return -ENOMEM;
1048
1049 error_str.start = *pos;
1050
1051 ret = i915_error_state_to_str(&error_str, error_priv);
1052 if (ret)
1053 goto out;
1054
1055 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1056 error_str.buf,
1057 error_str.bytes);
1058
1059 if (ret_count < 0)
1060 ret = ret_count;
1061 else
1062 *pos = error_str.start + ret_count;
1063 out:
1064 kfree(error_str.buf);
1065 return ret ?: ret_count;
1066 }
1067
1068 static const struct file_operations i915_error_state_fops = {
1069 .owner = THIS_MODULE,
1070 .open = i915_error_state_open,
1071 .read = i915_error_state_read,
1072 .write = i915_error_state_write,
1073 .llseek = default_llseek,
1074 .release = i915_error_state_release,
1075 };
1076
1077 static int
1078 i915_next_seqno_get(void *data, u64 *val)
1079 {
1080 struct drm_device *dev = data;
1081 drm_i915_private_t *dev_priv = dev->dev_private;
1082 int ret;
1083
1084 ret = mutex_lock_interruptible(&dev->struct_mutex);
1085 if (ret)
1086 return ret;
1087
1088 *val = dev_priv->next_seqno;
1089 mutex_unlock(&dev->struct_mutex);
1090
1091 return 0;
1092 }
1093
1094 static int
1095 i915_next_seqno_set(void *data, u64 val)
1096 {
1097 struct drm_device *dev = data;
1098 int ret;
1099
1100 ret = mutex_lock_interruptible(&dev->struct_mutex);
1101 if (ret)
1102 return ret;
1103
1104 ret = i915_gem_set_seqno(dev, val);
1105 mutex_unlock(&dev->struct_mutex);
1106
1107 return ret;
1108 }
1109
1110 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1111 i915_next_seqno_get, i915_next_seqno_set,
1112 "0x%llx\n");
1113
1114 static int i915_rstdby_delays(struct seq_file *m, void *unused)
1115 {
1116 struct drm_info_node *node = (struct drm_info_node *) m->private;
1117 struct drm_device *dev = node->minor->dev;
1118 drm_i915_private_t *dev_priv = dev->dev_private;
1119 u16 crstanddelay;
1120 int ret;
1121
1122 ret = mutex_lock_interruptible(&dev->struct_mutex);
1123 if (ret)
1124 return ret;
1125
1126 crstanddelay = I915_READ16(CRSTANDVID);
1127
1128 mutex_unlock(&dev->struct_mutex);
1129
1130 seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
1131
1132 return 0;
1133 }
1134
1135 static int i915_cur_delayinfo(struct seq_file *m, void *unused)
1136 {
1137 struct drm_info_node *node = (struct drm_info_node *) m->private;
1138 struct drm_device *dev = node->minor->dev;
1139 drm_i915_private_t *dev_priv = dev->dev_private;
1140 int ret;
1141
1142 if (IS_GEN5(dev)) {
1143 u16 rgvswctl = I915_READ16(MEMSWCTL);
1144 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1145
1146 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1147 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1148 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1149 MEMSTAT_VID_SHIFT);
1150 seq_printf(m, "Current P-state: %d\n",
1151 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1152 } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
1153 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1154 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1155 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1156 u32 rpstat, cagf;
1157 u32 rpupei, rpcurup, rpprevup;
1158 u32 rpdownei, rpcurdown, rpprevdown;
1159 int max_freq;
1160
1161 /* RPSTAT1 is in the GT power well */
1162 ret = mutex_lock_interruptible(&dev->struct_mutex);
1163 if (ret)
1164 return ret;
1165
1166 gen6_gt_force_wake_get(dev_priv);
1167
1168 rpstat = I915_READ(GEN6_RPSTAT1);
1169 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1170 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1171 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1172 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1173 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1174 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1175 if (IS_HASWELL(dev))
1176 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1177 else
1178 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1179 cagf *= GT_FREQUENCY_MULTIPLIER;
1180
1181 gen6_gt_force_wake_put(dev_priv);
1182 mutex_unlock(&dev->struct_mutex);
1183
1184 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1185 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1186 seq_printf(m, "Render p-state ratio: %d\n",
1187 (gt_perf_status & 0xff00) >> 8);
1188 seq_printf(m, "Render p-state VID: %d\n",
1189 gt_perf_status & 0xff);
1190 seq_printf(m, "Render p-state limit: %d\n",
1191 rp_state_limits & 0xff);
1192 seq_printf(m, "CAGF: %dMHz\n", cagf);
1193 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1194 GEN6_CURICONT_MASK);
1195 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1196 GEN6_CURBSYTAVG_MASK);
1197 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1198 GEN6_CURBSYTAVG_MASK);
1199 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1200 GEN6_CURIAVG_MASK);
1201 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1202 GEN6_CURBSYTAVG_MASK);
1203 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1204 GEN6_CURBSYTAVG_MASK);
1205
1206 max_freq = (rp_state_cap & 0xff0000) >> 16;
1207 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1208 max_freq * GT_FREQUENCY_MULTIPLIER);
1209
1210 max_freq = (rp_state_cap & 0xff00) >> 8;
1211 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1212 max_freq * GT_FREQUENCY_MULTIPLIER);
1213
1214 max_freq = rp_state_cap & 0xff;
1215 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1216 max_freq * GT_FREQUENCY_MULTIPLIER);
1217
1218 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1219 dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER);
1220 } else if (IS_VALLEYVIEW(dev)) {
1221 u32 freq_sts, val;
1222
1223 mutex_lock(&dev_priv->rps.hw_lock);
1224 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1225 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1226 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1227
1228 val = vlv_punit_read(dev_priv, PUNIT_FUSE_BUS1);
1229 seq_printf(m, "max GPU freq: %d MHz\n",
1230 vlv_gpu_freq(dev_priv->mem_freq, val));
1231
1232 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM);
1233 seq_printf(m, "min GPU freq: %d MHz\n",
1234 vlv_gpu_freq(dev_priv->mem_freq, val));
1235
1236 seq_printf(m, "current GPU freq: %d MHz\n",
1237 vlv_gpu_freq(dev_priv->mem_freq,
1238 (freq_sts >> 8) & 0xff));
1239 mutex_unlock(&dev_priv->rps.hw_lock);
1240 } else {
1241 seq_puts(m, "no P-state info available\n");
1242 }
1243
1244 return 0;
1245 }
1246
1247 static int i915_delayfreq_table(struct seq_file *m, void *unused)
1248 {
1249 struct drm_info_node *node = (struct drm_info_node *) m->private;
1250 struct drm_device *dev = node->minor->dev;
1251 drm_i915_private_t *dev_priv = dev->dev_private;
1252 u32 delayfreq;
1253 int ret, i;
1254
1255 ret = mutex_lock_interruptible(&dev->struct_mutex);
1256 if (ret)
1257 return ret;
1258
1259 for (i = 0; i < 16; i++) {
1260 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
1261 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
1262 (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
1263 }
1264
1265 mutex_unlock(&dev->struct_mutex);
1266
1267 return 0;
1268 }
1269
1270 static inline int MAP_TO_MV(int map)
1271 {
1272 return 1250 - (map * 25);
1273 }
1274
1275 static int i915_inttoext_table(struct seq_file *m, void *unused)
1276 {
1277 struct drm_info_node *node = (struct drm_info_node *) m->private;
1278 struct drm_device *dev = node->minor->dev;
1279 drm_i915_private_t *dev_priv = dev->dev_private;
1280 u32 inttoext;
1281 int ret, i;
1282
1283 ret = mutex_lock_interruptible(&dev->struct_mutex);
1284 if (ret)
1285 return ret;
1286
1287 for (i = 1; i <= 32; i++) {
1288 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
1289 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
1290 }
1291
1292 mutex_unlock(&dev->struct_mutex);
1293
1294 return 0;
1295 }
1296
1297 static int ironlake_drpc_info(struct seq_file *m)
1298 {
1299 struct drm_info_node *node = (struct drm_info_node *) m->private;
1300 struct drm_device *dev = node->minor->dev;
1301 drm_i915_private_t *dev_priv = dev->dev_private;
1302 u32 rgvmodectl, rstdbyctl;
1303 u16 crstandvid;
1304 int ret;
1305
1306 ret = mutex_lock_interruptible(&dev->struct_mutex);
1307 if (ret)
1308 return ret;
1309
1310 rgvmodectl = I915_READ(MEMMODECTL);
1311 rstdbyctl = I915_READ(RSTDBYCTL);
1312 crstandvid = I915_READ16(CRSTANDVID);
1313
1314 mutex_unlock(&dev->struct_mutex);
1315
1316 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1317 "yes" : "no");
1318 seq_printf(m, "Boost freq: %d\n",
1319 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1320 MEMMODE_BOOST_FREQ_SHIFT);
1321 seq_printf(m, "HW control enabled: %s\n",
1322 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1323 seq_printf(m, "SW control enabled: %s\n",
1324 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1325 seq_printf(m, "Gated voltage change: %s\n",
1326 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1327 seq_printf(m, "Starting frequency: P%d\n",
1328 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1329 seq_printf(m, "Max P-state: P%d\n",
1330 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1331 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1332 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1333 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1334 seq_printf(m, "Render standby enabled: %s\n",
1335 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1336 seq_puts(m, "Current RS state: ");
1337 switch (rstdbyctl & RSX_STATUS_MASK) {
1338 case RSX_STATUS_ON:
1339 seq_puts(m, "on\n");
1340 break;
1341 case RSX_STATUS_RC1:
1342 seq_puts(m, "RC1\n");
1343 break;
1344 case RSX_STATUS_RC1E:
1345 seq_puts(m, "RC1E\n");
1346 break;
1347 case RSX_STATUS_RS1:
1348 seq_puts(m, "RS1\n");
1349 break;
1350 case RSX_STATUS_RS2:
1351 seq_puts(m, "RS2 (RC6)\n");
1352 break;
1353 case RSX_STATUS_RS3:
1354 seq_puts(m, "RC3 (RC6+)\n");
1355 break;
1356 default:
1357 seq_puts(m, "unknown\n");
1358 break;
1359 }
1360
1361 return 0;
1362 }
1363
1364 static int gen6_drpc_info(struct seq_file *m)
1365 {
1366
1367 struct drm_info_node *node = (struct drm_info_node *) m->private;
1368 struct drm_device *dev = node->minor->dev;
1369 struct drm_i915_private *dev_priv = dev->dev_private;
1370 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1371 unsigned forcewake_count;
1372 int count = 0, ret;
1373
1374 ret = mutex_lock_interruptible(&dev->struct_mutex);
1375 if (ret)
1376 return ret;
1377
1378 spin_lock_irq(&dev_priv->gt_lock);
1379 forcewake_count = dev_priv->forcewake_count;
1380 spin_unlock_irq(&dev_priv->gt_lock);
1381
1382 if (forcewake_count) {
1383 seq_puts(m, "RC information inaccurate because somebody "
1384 "holds a forcewake reference \n");
1385 } else {
1386 /* NB: we cannot use forcewake, else we read the wrong values */
1387 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1388 udelay(10);
1389 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1390 }
1391
1392 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1393 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4);
1394
1395 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1396 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1397 mutex_unlock(&dev->struct_mutex);
1398 mutex_lock(&dev_priv->rps.hw_lock);
1399 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1400 mutex_unlock(&dev_priv->rps.hw_lock);
1401
1402 seq_printf(m, "Video Turbo Mode: %s\n",
1403 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1404 seq_printf(m, "HW control enabled: %s\n",
1405 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1406 seq_printf(m, "SW control enabled: %s\n",
1407 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1408 GEN6_RP_MEDIA_SW_MODE));
1409 seq_printf(m, "RC1e Enabled: %s\n",
1410 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1411 seq_printf(m, "RC6 Enabled: %s\n",
1412 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1413 seq_printf(m, "Deep RC6 Enabled: %s\n",
1414 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1415 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1416 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1417 seq_puts(m, "Current RC state: ");
1418 switch (gt_core_status & GEN6_RCn_MASK) {
1419 case GEN6_RC0:
1420 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1421 seq_puts(m, "Core Power Down\n");
1422 else
1423 seq_puts(m, "on\n");
1424 break;
1425 case GEN6_RC3:
1426 seq_puts(m, "RC3\n");
1427 break;
1428 case GEN6_RC6:
1429 seq_puts(m, "RC6\n");
1430 break;
1431 case GEN6_RC7:
1432 seq_puts(m, "RC7\n");
1433 break;
1434 default:
1435 seq_puts(m, "Unknown\n");
1436 break;
1437 }
1438
1439 seq_printf(m, "Core Power Down: %s\n",
1440 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1441
1442 /* Not exactly sure what this is */
1443 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1444 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1445 seq_printf(m, "RC6 residency since boot: %u\n",
1446 I915_READ(GEN6_GT_GFX_RC6));
1447 seq_printf(m, "RC6+ residency since boot: %u\n",
1448 I915_READ(GEN6_GT_GFX_RC6p));
1449 seq_printf(m, "RC6++ residency since boot: %u\n",
1450 I915_READ(GEN6_GT_GFX_RC6pp));
1451
1452 seq_printf(m, "RC6 voltage: %dmV\n",
1453 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1454 seq_printf(m, "RC6+ voltage: %dmV\n",
1455 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1456 seq_printf(m, "RC6++ voltage: %dmV\n",
1457 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1458 return 0;
1459 }
1460
1461 static int i915_drpc_info(struct seq_file *m, void *unused)
1462 {
1463 struct drm_info_node *node = (struct drm_info_node *) m->private;
1464 struct drm_device *dev = node->minor->dev;
1465
1466 if (IS_GEN6(dev) || IS_GEN7(dev))
1467 return gen6_drpc_info(m);
1468 else
1469 return ironlake_drpc_info(m);
1470 }
1471
1472 static int i915_fbc_status(struct seq_file *m, void *unused)
1473 {
1474 struct drm_info_node *node = (struct drm_info_node *) m->private;
1475 struct drm_device *dev = node->minor->dev;
1476 drm_i915_private_t *dev_priv = dev->dev_private;
1477
1478 if (!I915_HAS_FBC(dev)) {
1479 seq_puts(m, "FBC unsupported on this chipset\n");
1480 return 0;
1481 }
1482
1483 if (intel_fbc_enabled(dev)) {
1484 seq_puts(m, "FBC enabled\n");
1485 } else {
1486 seq_puts(m, "FBC disabled: ");
1487 switch (dev_priv->fbc.no_fbc_reason) {
1488 case FBC_NO_OUTPUT:
1489 seq_puts(m, "no outputs");
1490 break;
1491 case FBC_STOLEN_TOO_SMALL:
1492 seq_puts(m, "not enough stolen memory");
1493 break;
1494 case FBC_UNSUPPORTED_MODE:
1495 seq_puts(m, "mode not supported");
1496 break;
1497 case FBC_MODE_TOO_LARGE:
1498 seq_puts(m, "mode too large");
1499 break;
1500 case FBC_BAD_PLANE:
1501 seq_puts(m, "FBC unsupported on plane");
1502 break;
1503 case FBC_NOT_TILED:
1504 seq_puts(m, "scanout buffer not tiled");
1505 break;
1506 case FBC_MULTIPLE_PIPES:
1507 seq_puts(m, "multiple pipes are enabled");
1508 break;
1509 case FBC_MODULE_PARAM:
1510 seq_puts(m, "disabled per module param (default off)");
1511 break;
1512 case FBC_CHIP_DEFAULT:
1513 seq_puts(m, "disabled per chip default");
1514 break;
1515 default:
1516 seq_puts(m, "unknown reason");
1517 }
1518 seq_putc(m, '\n');
1519 }
1520 return 0;
1521 }
1522
1523 static int i915_ips_status(struct seq_file *m, void *unused)
1524 {
1525 struct drm_info_node *node = (struct drm_info_node *) m->private;
1526 struct drm_device *dev = node->minor->dev;
1527 struct drm_i915_private *dev_priv = dev->dev_private;
1528
1529 if (!HAS_IPS(dev)) {
1530 seq_puts(m, "not supported\n");
1531 return 0;
1532 }
1533
1534 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1535 seq_puts(m, "enabled\n");
1536 else
1537 seq_puts(m, "disabled\n");
1538
1539 return 0;
1540 }
1541
1542 static int i915_sr_status(struct seq_file *m, void *unused)
1543 {
1544 struct drm_info_node *node = (struct drm_info_node *) m->private;
1545 struct drm_device *dev = node->minor->dev;
1546 drm_i915_private_t *dev_priv = dev->dev_private;
1547 bool sr_enabled = false;
1548
1549 if (HAS_PCH_SPLIT(dev))
1550 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1551 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1552 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1553 else if (IS_I915GM(dev))
1554 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1555 else if (IS_PINEVIEW(dev))
1556 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1557
1558 seq_printf(m, "self-refresh: %s\n",
1559 sr_enabled ? "enabled" : "disabled");
1560
1561 return 0;
1562 }
1563
1564 static int i915_emon_status(struct seq_file *m, void *unused)
1565 {
1566 struct drm_info_node *node = (struct drm_info_node *) m->private;
1567 struct drm_device *dev = node->minor->dev;
1568 drm_i915_private_t *dev_priv = dev->dev_private;
1569 unsigned long temp, chipset, gfx;
1570 int ret;
1571
1572 if (!IS_GEN5(dev))
1573 return -ENODEV;
1574
1575 ret = mutex_lock_interruptible(&dev->struct_mutex);
1576 if (ret)
1577 return ret;
1578
1579 temp = i915_mch_val(dev_priv);
1580 chipset = i915_chipset_val(dev_priv);
1581 gfx = i915_gfx_val(dev_priv);
1582 mutex_unlock(&dev->struct_mutex);
1583
1584 seq_printf(m, "GMCH temp: %ld\n", temp);
1585 seq_printf(m, "Chipset power: %ld\n", chipset);
1586 seq_printf(m, "GFX power: %ld\n", gfx);
1587 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1588
1589 return 0;
1590 }
1591
1592 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1593 {
1594 struct drm_info_node *node = (struct drm_info_node *) m->private;
1595 struct drm_device *dev = node->minor->dev;
1596 drm_i915_private_t *dev_priv = dev->dev_private;
1597 int ret;
1598 int gpu_freq, ia_freq;
1599
1600 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1601 seq_puts(m, "unsupported on this chipset\n");
1602 return 0;
1603 }
1604
1605 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1606 if (ret)
1607 return ret;
1608
1609 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1610
1611 for (gpu_freq = dev_priv->rps.min_delay;
1612 gpu_freq <= dev_priv->rps.max_delay;
1613 gpu_freq++) {
1614 ia_freq = gpu_freq;
1615 sandybridge_pcode_read(dev_priv,
1616 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1617 &ia_freq);
1618 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1619 gpu_freq * GT_FREQUENCY_MULTIPLIER,
1620 ((ia_freq >> 0) & 0xff) * 100,
1621 ((ia_freq >> 8) & 0xff) * 100);
1622 }
1623
1624 mutex_unlock(&dev_priv->rps.hw_lock);
1625
1626 return 0;
1627 }
1628
1629 static int i915_gfxec(struct seq_file *m, void *unused)
1630 {
1631 struct drm_info_node *node = (struct drm_info_node *) m->private;
1632 struct drm_device *dev = node->minor->dev;
1633 drm_i915_private_t *dev_priv = dev->dev_private;
1634 int ret;
1635
1636 ret = mutex_lock_interruptible(&dev->struct_mutex);
1637 if (ret)
1638 return ret;
1639
1640 seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1641
1642 mutex_unlock(&dev->struct_mutex);
1643
1644 return 0;
1645 }
1646
1647 static int i915_opregion(struct seq_file *m, void *unused)
1648 {
1649 struct drm_info_node *node = (struct drm_info_node *) m->private;
1650 struct drm_device *dev = node->minor->dev;
1651 drm_i915_private_t *dev_priv = dev->dev_private;
1652 struct intel_opregion *opregion = &dev_priv->opregion;
1653 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1654 int ret;
1655
1656 if (data == NULL)
1657 return -ENOMEM;
1658
1659 ret = mutex_lock_interruptible(&dev->struct_mutex);
1660 if (ret)
1661 goto out;
1662
1663 if (opregion->header) {
1664 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1665 seq_write(m, data, OPREGION_SIZE);
1666 }
1667
1668 mutex_unlock(&dev->struct_mutex);
1669
1670 out:
1671 kfree(data);
1672 return 0;
1673 }
1674
1675 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1676 {
1677 struct drm_info_node *node = (struct drm_info_node *) m->private;
1678 struct drm_device *dev = node->minor->dev;
1679 drm_i915_private_t *dev_priv = dev->dev_private;
1680 struct intel_fbdev *ifbdev;
1681 struct intel_framebuffer *fb;
1682 int ret;
1683
1684 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1685 if (ret)
1686 return ret;
1687
1688 ifbdev = dev_priv->fbdev;
1689 fb = to_intel_framebuffer(ifbdev->helper.fb);
1690
1691 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1692 fb->base.width,
1693 fb->base.height,
1694 fb->base.depth,
1695 fb->base.bits_per_pixel,
1696 atomic_read(&fb->base.refcount.refcount));
1697 describe_obj(m, fb->obj);
1698 seq_putc(m, '\n');
1699 mutex_unlock(&dev->mode_config.mutex);
1700
1701 mutex_lock(&dev->mode_config.fb_lock);
1702 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1703 if (&fb->base == ifbdev->helper.fb)
1704 continue;
1705
1706 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1707 fb->base.width,
1708 fb->base.height,
1709 fb->base.depth,
1710 fb->base.bits_per_pixel,
1711 atomic_read(&fb->base.refcount.refcount));
1712 describe_obj(m, fb->obj);
1713 seq_putc(m, '\n');
1714 }
1715 mutex_unlock(&dev->mode_config.fb_lock);
1716
1717 return 0;
1718 }
1719
1720 static int i915_context_status(struct seq_file *m, void *unused)
1721 {
1722 struct drm_info_node *node = (struct drm_info_node *) m->private;
1723 struct drm_device *dev = node->minor->dev;
1724 drm_i915_private_t *dev_priv = dev->dev_private;
1725 struct intel_ring_buffer *ring;
1726 int ret, i;
1727
1728 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1729 if (ret)
1730 return ret;
1731
1732 if (dev_priv->ips.pwrctx) {
1733 seq_puts(m, "power context ");
1734 describe_obj(m, dev_priv->ips.pwrctx);
1735 seq_putc(m, '\n');
1736 }
1737
1738 if (dev_priv->ips.renderctx) {
1739 seq_puts(m, "render context ");
1740 describe_obj(m, dev_priv->ips.renderctx);
1741 seq_putc(m, '\n');
1742 }
1743
1744 for_each_ring(ring, dev_priv, i) {
1745 if (ring->default_context) {
1746 seq_printf(m, "HW default context %s ring ", ring->name);
1747 describe_obj(m, ring->default_context->obj);
1748 seq_putc(m, '\n');
1749 }
1750 }
1751
1752 mutex_unlock(&dev->mode_config.mutex);
1753
1754 return 0;
1755 }
1756
1757 static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1758 {
1759 struct drm_info_node *node = (struct drm_info_node *) m->private;
1760 struct drm_device *dev = node->minor->dev;
1761 struct drm_i915_private *dev_priv = dev->dev_private;
1762 unsigned forcewake_count;
1763
1764 spin_lock_irq(&dev_priv->gt_lock);
1765 forcewake_count = dev_priv->forcewake_count;
1766 spin_unlock_irq(&dev_priv->gt_lock);
1767
1768 seq_printf(m, "forcewake count = %u\n", forcewake_count);
1769
1770 return 0;
1771 }
1772
1773 static const char *swizzle_string(unsigned swizzle)
1774 {
1775 switch (swizzle) {
1776 case I915_BIT_6_SWIZZLE_NONE:
1777 return "none";
1778 case I915_BIT_6_SWIZZLE_9:
1779 return "bit9";
1780 case I915_BIT_6_SWIZZLE_9_10:
1781 return "bit9/bit10";
1782 case I915_BIT_6_SWIZZLE_9_11:
1783 return "bit9/bit11";
1784 case I915_BIT_6_SWIZZLE_9_10_11:
1785 return "bit9/bit10/bit11";
1786 case I915_BIT_6_SWIZZLE_9_17:
1787 return "bit9/bit17";
1788 case I915_BIT_6_SWIZZLE_9_10_17:
1789 return "bit9/bit10/bit17";
1790 case I915_BIT_6_SWIZZLE_UNKNOWN:
1791 return "unknown";
1792 }
1793
1794 return "bug";
1795 }
1796
1797 static int i915_swizzle_info(struct seq_file *m, void *data)
1798 {
1799 struct drm_info_node *node = (struct drm_info_node *) m->private;
1800 struct drm_device *dev = node->minor->dev;
1801 struct drm_i915_private *dev_priv = dev->dev_private;
1802 int ret;
1803
1804 ret = mutex_lock_interruptible(&dev->struct_mutex);
1805 if (ret)
1806 return ret;
1807
1808 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1809 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1810 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1811 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1812
1813 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1814 seq_printf(m, "DDC = 0x%08x\n",
1815 I915_READ(DCC));
1816 seq_printf(m, "C0DRB3 = 0x%04x\n",
1817 I915_READ16(C0DRB3));
1818 seq_printf(m, "C1DRB3 = 0x%04x\n",
1819 I915_READ16(C1DRB3));
1820 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1821 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1822 I915_READ(MAD_DIMM_C0));
1823 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1824 I915_READ(MAD_DIMM_C1));
1825 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1826 I915_READ(MAD_DIMM_C2));
1827 seq_printf(m, "TILECTL = 0x%08x\n",
1828 I915_READ(TILECTL));
1829 seq_printf(m, "ARB_MODE = 0x%08x\n",
1830 I915_READ(ARB_MODE));
1831 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1832 I915_READ(DISP_ARB_CTL));
1833 }
1834 mutex_unlock(&dev->struct_mutex);
1835
1836 return 0;
1837 }
1838
1839 static int i915_ppgtt_info(struct seq_file *m, void *data)
1840 {
1841 struct drm_info_node *node = (struct drm_info_node *) m->private;
1842 struct drm_device *dev = node->minor->dev;
1843 struct drm_i915_private *dev_priv = dev->dev_private;
1844 struct intel_ring_buffer *ring;
1845 int i, ret;
1846
1847
1848 ret = mutex_lock_interruptible(&dev->struct_mutex);
1849 if (ret)
1850 return ret;
1851 if (INTEL_INFO(dev)->gen == 6)
1852 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1853
1854 for_each_ring(ring, dev_priv, i) {
1855 seq_printf(m, "%s\n", ring->name);
1856 if (INTEL_INFO(dev)->gen == 7)
1857 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1858 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1859 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1860 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1861 }
1862 if (dev_priv->mm.aliasing_ppgtt) {
1863 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1864
1865 seq_puts(m, "aliasing PPGTT:\n");
1866 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1867 }
1868 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
1869 mutex_unlock(&dev->struct_mutex);
1870
1871 return 0;
1872 }
1873
1874 static int i915_dpio_info(struct seq_file *m, void *data)
1875 {
1876 struct drm_info_node *node = (struct drm_info_node *) m->private;
1877 struct drm_device *dev = node->minor->dev;
1878 struct drm_i915_private *dev_priv = dev->dev_private;
1879 int ret;
1880
1881
1882 if (!IS_VALLEYVIEW(dev)) {
1883 seq_puts(m, "unsupported\n");
1884 return 0;
1885 }
1886
1887 ret = mutex_lock_interruptible(&dev_priv->dpio_lock);
1888 if (ret)
1889 return ret;
1890
1891 seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
1892
1893 seq_printf(m, "DPIO_DIV_A: 0x%08x\n",
1894 vlv_dpio_read(dev_priv, _DPIO_DIV_A));
1895 seq_printf(m, "DPIO_DIV_B: 0x%08x\n",
1896 vlv_dpio_read(dev_priv, _DPIO_DIV_B));
1897
1898 seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n",
1899 vlv_dpio_read(dev_priv, _DPIO_REFSFR_A));
1900 seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n",
1901 vlv_dpio_read(dev_priv, _DPIO_REFSFR_B));
1902
1903 seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n",
1904 vlv_dpio_read(dev_priv, _DPIO_CORE_CLK_A));
1905 seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n",
1906 vlv_dpio_read(dev_priv, _DPIO_CORE_CLK_B));
1907
1908 seq_printf(m, "DPIO_LPF_COEFF_A: 0x%08x\n",
1909 vlv_dpio_read(dev_priv, _DPIO_LPF_COEFF_A));
1910 seq_printf(m, "DPIO_LPF_COEFF_B: 0x%08x\n",
1911 vlv_dpio_read(dev_priv, _DPIO_LPF_COEFF_B));
1912
1913 seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
1914 vlv_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE));
1915
1916 mutex_unlock(&dev_priv->dpio_lock);
1917
1918 return 0;
1919 }
1920
1921 static int
1922 i915_wedged_get(void *data, u64 *val)
1923 {
1924 struct drm_device *dev = data;
1925 drm_i915_private_t *dev_priv = dev->dev_private;
1926
1927 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
1928
1929 return 0;
1930 }
1931
1932 static int
1933 i915_wedged_set(void *data, u64 val)
1934 {
1935 struct drm_device *dev = data;
1936
1937 DRM_INFO("Manually setting wedged to %llu\n", val);
1938 i915_handle_error(dev, val);
1939
1940 return 0;
1941 }
1942
1943 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
1944 i915_wedged_get, i915_wedged_set,
1945 "%llu\n");
1946
1947 static int
1948 i915_ring_stop_get(void *data, u64 *val)
1949 {
1950 struct drm_device *dev = data;
1951 drm_i915_private_t *dev_priv = dev->dev_private;
1952
1953 *val = dev_priv->gpu_error.stop_rings;
1954
1955 return 0;
1956 }
1957
1958 static int
1959 i915_ring_stop_set(void *data, u64 val)
1960 {
1961 struct drm_device *dev = data;
1962 struct drm_i915_private *dev_priv = dev->dev_private;
1963 int ret;
1964
1965 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
1966
1967 ret = mutex_lock_interruptible(&dev->struct_mutex);
1968 if (ret)
1969 return ret;
1970
1971 dev_priv->gpu_error.stop_rings = val;
1972 mutex_unlock(&dev->struct_mutex);
1973
1974 return 0;
1975 }
1976
1977 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
1978 i915_ring_stop_get, i915_ring_stop_set,
1979 "0x%08llx\n");
1980
1981 #define DROP_UNBOUND 0x1
1982 #define DROP_BOUND 0x2
1983 #define DROP_RETIRE 0x4
1984 #define DROP_ACTIVE 0x8
1985 #define DROP_ALL (DROP_UNBOUND | \
1986 DROP_BOUND | \
1987 DROP_RETIRE | \
1988 DROP_ACTIVE)
1989 static int
1990 i915_drop_caches_get(void *data, u64 *val)
1991 {
1992 *val = DROP_ALL;
1993
1994 return 0;
1995 }
1996
1997 static int
1998 i915_drop_caches_set(void *data, u64 val)
1999 {
2000 struct drm_device *dev = data;
2001 struct drm_i915_private *dev_priv = dev->dev_private;
2002 struct drm_i915_gem_object *obj, *next;
2003 int ret;
2004
2005 DRM_DEBUG_DRIVER("Dropping caches: 0x%08llx\n", val);
2006
2007 /* No need to check and wait for gpu resets, only libdrm auto-restarts
2008 * on ioctls on -EAGAIN. */
2009 ret = mutex_lock_interruptible(&dev->struct_mutex);
2010 if (ret)
2011 return ret;
2012
2013 if (val & DROP_ACTIVE) {
2014 ret = i915_gpu_idle(dev);
2015 if (ret)
2016 goto unlock;
2017 }
2018
2019 if (val & (DROP_RETIRE | DROP_ACTIVE))
2020 i915_gem_retire_requests(dev);
2021
2022 if (val & DROP_BOUND) {
2023 list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list, mm_list)
2024 if (obj->pin_count == 0) {
2025 ret = i915_gem_object_unbind(obj);
2026 if (ret)
2027 goto unlock;
2028 }
2029 }
2030
2031 if (val & DROP_UNBOUND) {
2032 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
2033 global_list)
2034 if (obj->pages_pin_count == 0) {
2035 ret = i915_gem_object_put_pages(obj);
2036 if (ret)
2037 goto unlock;
2038 }
2039 }
2040
2041 unlock:
2042 mutex_unlock(&dev->struct_mutex);
2043
2044 return ret;
2045 }
2046
2047 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
2048 i915_drop_caches_get, i915_drop_caches_set,
2049 "0x%08llx\n");
2050
2051 static int
2052 i915_max_freq_get(void *data, u64 *val)
2053 {
2054 struct drm_device *dev = data;
2055 drm_i915_private_t *dev_priv = dev->dev_private;
2056 int ret;
2057
2058 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2059 return -ENODEV;
2060
2061 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2062 if (ret)
2063 return ret;
2064
2065 if (IS_VALLEYVIEW(dev))
2066 *val = vlv_gpu_freq(dev_priv->mem_freq,
2067 dev_priv->rps.max_delay);
2068 else
2069 *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
2070 mutex_unlock(&dev_priv->rps.hw_lock);
2071
2072 return 0;
2073 }
2074
2075 static int
2076 i915_max_freq_set(void *data, u64 val)
2077 {
2078 struct drm_device *dev = data;
2079 struct drm_i915_private *dev_priv = dev->dev_private;
2080 int ret;
2081
2082 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2083 return -ENODEV;
2084
2085 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
2086
2087 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2088 if (ret)
2089 return ret;
2090
2091 /*
2092 * Turbo will still be enabled, but won't go above the set value.
2093 */
2094 if (IS_VALLEYVIEW(dev)) {
2095 val = vlv_freq_opcode(dev_priv->mem_freq, val);
2096 dev_priv->rps.max_delay = val;
2097 gen6_set_rps(dev, val);
2098 } else {
2099 do_div(val, GT_FREQUENCY_MULTIPLIER);
2100 dev_priv->rps.max_delay = val;
2101 gen6_set_rps(dev, val);
2102 }
2103
2104 mutex_unlock(&dev_priv->rps.hw_lock);
2105
2106 return 0;
2107 }
2108
2109 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
2110 i915_max_freq_get, i915_max_freq_set,
2111 "%llu\n");
2112
2113 static int
2114 i915_min_freq_get(void *data, u64 *val)
2115 {
2116 struct drm_device *dev = data;
2117 drm_i915_private_t *dev_priv = dev->dev_private;
2118 int ret;
2119
2120 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2121 return -ENODEV;
2122
2123 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2124 if (ret)
2125 return ret;
2126
2127 if (IS_VALLEYVIEW(dev))
2128 *val = vlv_gpu_freq(dev_priv->mem_freq,
2129 dev_priv->rps.min_delay);
2130 else
2131 *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
2132 mutex_unlock(&dev_priv->rps.hw_lock);
2133
2134 return 0;
2135 }
2136
2137 static int
2138 i915_min_freq_set(void *data, u64 val)
2139 {
2140 struct drm_device *dev = data;
2141 struct drm_i915_private *dev_priv = dev->dev_private;
2142 int ret;
2143
2144 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2145 return -ENODEV;
2146
2147 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
2148
2149 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2150 if (ret)
2151 return ret;
2152
2153 /*
2154 * Turbo will still be enabled, but won't go below the set value.
2155 */
2156 if (IS_VALLEYVIEW(dev)) {
2157 val = vlv_freq_opcode(dev_priv->mem_freq, val);
2158 dev_priv->rps.min_delay = val;
2159 valleyview_set_rps(dev, val);
2160 } else {
2161 do_div(val, GT_FREQUENCY_MULTIPLIER);
2162 dev_priv->rps.min_delay = val;
2163 gen6_set_rps(dev, val);
2164 }
2165 mutex_unlock(&dev_priv->rps.hw_lock);
2166
2167 return 0;
2168 }
2169
2170 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
2171 i915_min_freq_get, i915_min_freq_set,
2172 "%llu\n");
2173
2174 static int
2175 i915_cache_sharing_get(void *data, u64 *val)
2176 {
2177 struct drm_device *dev = data;
2178 drm_i915_private_t *dev_priv = dev->dev_private;
2179 u32 snpcr;
2180 int ret;
2181
2182 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2183 return -ENODEV;
2184
2185 ret = mutex_lock_interruptible(&dev->struct_mutex);
2186 if (ret)
2187 return ret;
2188
2189 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
2190 mutex_unlock(&dev_priv->dev->struct_mutex);
2191
2192 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
2193
2194 return 0;
2195 }
2196
2197 static int
2198 i915_cache_sharing_set(void *data, u64 val)
2199 {
2200 struct drm_device *dev = data;
2201 struct drm_i915_private *dev_priv = dev->dev_private;
2202 u32 snpcr;
2203
2204 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2205 return -ENODEV;
2206
2207 if (val > 3)
2208 return -EINVAL;
2209
2210 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
2211
2212 /* Update the cache sharing policy here as well */
2213 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
2214 snpcr &= ~GEN6_MBC_SNPCR_MASK;
2215 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
2216 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
2217
2218 return 0;
2219 }
2220
2221 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
2222 i915_cache_sharing_get, i915_cache_sharing_set,
2223 "%llu\n");
2224
2225 /* As the drm_debugfs_init() routines are called before dev->dev_private is
2226 * allocated we need to hook into the minor for release. */
2227 static int
2228 drm_add_fake_info_node(struct drm_minor *minor,
2229 struct dentry *ent,
2230 const void *key)
2231 {
2232 struct drm_info_node *node;
2233
2234 node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL);
2235 if (node == NULL) {
2236 debugfs_remove(ent);
2237 return -ENOMEM;
2238 }
2239
2240 node->minor = minor;
2241 node->dent = ent;
2242 node->info_ent = (void *) key;
2243
2244 mutex_lock(&minor->debugfs_lock);
2245 list_add(&node->list, &minor->debugfs_list);
2246 mutex_unlock(&minor->debugfs_lock);
2247
2248 return 0;
2249 }
2250
2251 static int i915_forcewake_open(struct inode *inode, struct file *file)
2252 {
2253 struct drm_device *dev = inode->i_private;
2254 struct drm_i915_private *dev_priv = dev->dev_private;
2255
2256 if (INTEL_INFO(dev)->gen < 6)
2257 return 0;
2258
2259 gen6_gt_force_wake_get(dev_priv);
2260
2261 return 0;
2262 }
2263
2264 static int i915_forcewake_release(struct inode *inode, struct file *file)
2265 {
2266 struct drm_device *dev = inode->i_private;
2267 struct drm_i915_private *dev_priv = dev->dev_private;
2268
2269 if (INTEL_INFO(dev)->gen < 6)
2270 return 0;
2271
2272 gen6_gt_force_wake_put(dev_priv);
2273
2274 return 0;
2275 }
2276
2277 static const struct file_operations i915_forcewake_fops = {
2278 .owner = THIS_MODULE,
2279 .open = i915_forcewake_open,
2280 .release = i915_forcewake_release,
2281 };
2282
2283 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
2284 {
2285 struct drm_device *dev = minor->dev;
2286 struct dentry *ent;
2287
2288 ent = debugfs_create_file("i915_forcewake_user",
2289 S_IRUSR,
2290 root, dev,
2291 &i915_forcewake_fops);
2292 if (IS_ERR(ent))
2293 return PTR_ERR(ent);
2294
2295 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
2296 }
2297
2298 static int i915_debugfs_create(struct dentry *root,
2299 struct drm_minor *minor,
2300 const char *name,
2301 const struct file_operations *fops)
2302 {
2303 struct drm_device *dev = minor->dev;
2304 struct dentry *ent;
2305
2306 ent = debugfs_create_file(name,
2307 S_IRUGO | S_IWUSR,
2308 root, dev,
2309 fops);
2310 if (IS_ERR(ent))
2311 return PTR_ERR(ent);
2312
2313 return drm_add_fake_info_node(minor, ent, fops);
2314 }
2315
2316 static struct drm_info_list i915_debugfs_list[] = {
2317 {"i915_capabilities", i915_capabilities, 0},
2318 {"i915_gem_objects", i915_gem_object_info, 0},
2319 {"i915_gem_gtt", i915_gem_gtt_info, 0},
2320 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
2321 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
2322 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
2323 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2324 {"i915_gem_request", i915_gem_request_info, 0},
2325 {"i915_gem_seqno", i915_gem_seqno_info, 0},
2326 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2327 {"i915_gem_interrupt", i915_interrupt_info, 0},
2328 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
2329 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
2330 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
2331 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
2332 {"i915_rstdby_delays", i915_rstdby_delays, 0},
2333 {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
2334 {"i915_delayfreq_table", i915_delayfreq_table, 0},
2335 {"i915_inttoext_table", i915_inttoext_table, 0},
2336 {"i915_drpc_info", i915_drpc_info, 0},
2337 {"i915_emon_status", i915_emon_status, 0},
2338 {"i915_ring_freq_table", i915_ring_freq_table, 0},
2339 {"i915_gfxec", i915_gfxec, 0},
2340 {"i915_fbc_status", i915_fbc_status, 0},
2341 {"i915_ips_status", i915_ips_status, 0},
2342 {"i915_sr_status", i915_sr_status, 0},
2343 {"i915_opregion", i915_opregion, 0},
2344 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
2345 {"i915_context_status", i915_context_status, 0},
2346 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
2347 {"i915_swizzle_info", i915_swizzle_info, 0},
2348 {"i915_ppgtt_info", i915_ppgtt_info, 0},
2349 {"i915_dpio", i915_dpio_info, 0},
2350 };
2351 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2352
2353 int i915_debugfs_init(struct drm_minor *minor)
2354 {
2355 int ret;
2356
2357 ret = i915_debugfs_create(minor->debugfs_root, minor,
2358 "i915_wedged",
2359 &i915_wedged_fops);
2360 if (ret)
2361 return ret;
2362
2363 ret = i915_forcewake_create(minor->debugfs_root, minor);
2364 if (ret)
2365 return ret;
2366
2367 ret = i915_debugfs_create(minor->debugfs_root, minor,
2368 "i915_max_freq",
2369 &i915_max_freq_fops);
2370 if (ret)
2371 return ret;
2372
2373 ret = i915_debugfs_create(minor->debugfs_root, minor,
2374 "i915_min_freq",
2375 &i915_min_freq_fops);
2376 if (ret)
2377 return ret;
2378
2379 ret = i915_debugfs_create(minor->debugfs_root, minor,
2380 "i915_cache_sharing",
2381 &i915_cache_sharing_fops);
2382 if (ret)
2383 return ret;
2384
2385 ret = i915_debugfs_create(minor->debugfs_root, minor,
2386 "i915_ring_stop",
2387 &i915_ring_stop_fops);
2388 if (ret)
2389 return ret;
2390
2391 ret = i915_debugfs_create(minor->debugfs_root, minor,
2392 "i915_gem_drop_caches",
2393 &i915_drop_caches_fops);
2394 if (ret)
2395 return ret;
2396
2397 ret = i915_debugfs_create(minor->debugfs_root, minor,
2398 "i915_error_state",
2399 &i915_error_state_fops);
2400 if (ret)
2401 return ret;
2402
2403 ret = i915_debugfs_create(minor->debugfs_root, minor,
2404 "i915_next_seqno",
2405 &i915_next_seqno_fops);
2406 if (ret)
2407 return ret;
2408
2409 return drm_debugfs_create_files(i915_debugfs_list,
2410 I915_DEBUGFS_ENTRIES,
2411 minor->debugfs_root, minor);
2412 }
2413
2414 void i915_debugfs_cleanup(struct drm_minor *minor)
2415 {
2416 drm_debugfs_remove_files(i915_debugfs_list,
2417 I915_DEBUGFS_ENTRIES, minor);
2418 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
2419 1, minor);
2420 drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops,
2421 1, minor);
2422 drm_debugfs_remove_files((struct drm_info_list *) &i915_max_freq_fops,
2423 1, minor);
2424 drm_debugfs_remove_files((struct drm_info_list *) &i915_min_freq_fops,
2425 1, minor);
2426 drm_debugfs_remove_files((struct drm_info_list *) &i915_cache_sharing_fops,
2427 1, minor);
2428 drm_debugfs_remove_files((struct drm_info_list *) &i915_drop_caches_fops,
2429 1, minor);
2430 drm_debugfs_remove_files((struct drm_info_list *) &i915_ring_stop_fops,
2431 1, minor);
2432 drm_debugfs_remove_files((struct drm_info_list *) &i915_error_state_fops,
2433 1, minor);
2434 drm_debugfs_remove_files((struct drm_info_list *) &i915_next_seqno_fops,
2435 1, minor);
2436 }
2437
2438 #endif /* CONFIG_DEBUG_FS */
Linux kernel - Deliverables
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