2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
49 /* As the drm_debugfs_init() routines are called before dev->dev_private is
50 * allocated we need to hook into the minor for release. */
52 drm_add_fake_info_node(struct drm_minor
*minor
,
56 struct drm_info_node
*node
;
58 node
= kmalloc(sizeof(*node
), GFP_KERNEL
);
66 node
->info_ent
= (void *) key
;
68 mutex_lock(&minor
->debugfs_lock
);
69 list_add(&node
->list
, &minor
->debugfs_list
);
70 mutex_unlock(&minor
->debugfs_lock
);
75 static int i915_capabilities(struct seq_file
*m
, void *data
)
77 struct drm_info_node
*node
= m
->private;
78 struct drm_device
*dev
= node
->minor
->dev
;
79 const struct intel_device_info
*info
= INTEL_INFO(dev
);
81 seq_printf(m
, "gen: %d\n", info
->gen
);
82 seq_printf(m
, "pch: %d\n", INTEL_PCH_TYPE(dev
));
83 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
84 #define SEP_SEMICOLON ;
85 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG
, SEP_SEMICOLON
);
92 static char get_active_flag(struct drm_i915_gem_object
*obj
)
94 return obj
->active
? '*' : ' ';
97 static char get_pin_flag(struct drm_i915_gem_object
*obj
)
99 return obj
->pin_display
? 'p' : ' ';
102 static char get_tiling_flag(struct drm_i915_gem_object
*obj
)
104 switch (obj
->tiling_mode
) {
106 case I915_TILING_NONE
: return ' ';
107 case I915_TILING_X
: return 'X';
108 case I915_TILING_Y
: return 'Y';
112 static char get_global_flag(struct drm_i915_gem_object
*obj
)
114 return i915_gem_obj_to_ggtt(obj
) ? 'g' : ' ';
117 static char get_pin_mapped_flag(struct drm_i915_gem_object
*obj
)
119 return obj
->mapping
? 'M' : ' ';
122 static u64
i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object
*obj
)
125 struct i915_vma
*vma
;
127 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
128 if (vma
->is_ggtt
&& drm_mm_node_allocated(&vma
->node
))
129 size
+= vma
->node
.size
;
136 describe_obj(struct seq_file
*m
, struct drm_i915_gem_object
*obj
)
138 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
139 struct intel_engine_cs
*engine
;
140 struct i915_vma
*vma
;
142 enum intel_engine_id id
;
144 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
146 seq_printf(m
, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ",
148 get_active_flag(obj
),
150 get_tiling_flag(obj
),
151 get_global_flag(obj
),
152 get_pin_mapped_flag(obj
),
153 obj
->base
.size
/ 1024,
154 obj
->base
.read_domains
,
155 obj
->base
.write_domain
);
156 for_each_engine_id(engine
, dev_priv
, id
)
158 i915_gem_request_get_seqno(obj
->last_read_req
[id
]));
159 seq_printf(m
, "] %x %x%s%s%s",
160 i915_gem_request_get_seqno(obj
->last_write_req
),
161 i915_gem_request_get_seqno(obj
->last_fenced_req
),
162 i915_cache_level_str(to_i915(obj
->base
.dev
), obj
->cache_level
),
163 obj
->dirty
? " dirty" : "",
164 obj
->madv
== I915_MADV_DONTNEED
? " purgeable" : "");
166 seq_printf(m
, " (name: %d)", obj
->base
.name
);
167 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
168 if (vma
->pin_count
> 0)
171 seq_printf(m
, " (pinned x %d)", pin_count
);
172 if (obj
->pin_display
)
173 seq_printf(m
, " (display)");
174 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
)
175 seq_printf(m
, " (fence: %d)", obj
->fence_reg
);
176 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
177 seq_printf(m
, " (%sgtt offset: %08llx, size: %08llx",
178 vma
->is_ggtt
? "g" : "pp",
179 vma
->node
.start
, vma
->node
.size
);
181 seq_printf(m
, ", type: %u", vma
->ggtt_view
.type
);
185 seq_printf(m
, " (stolen: %08llx)", obj
->stolen
->start
);
186 if (obj
->pin_display
|| obj
->fault_mappable
) {
188 if (obj
->pin_display
)
190 if (obj
->fault_mappable
)
193 seq_printf(m
, " (%s mappable)", s
);
195 if (obj
->last_write_req
!= NULL
)
196 seq_printf(m
, " (%s)",
197 i915_gem_request_get_engine(obj
->last_write_req
)->name
);
198 if (obj
->frontbuffer_bits
)
199 seq_printf(m
, " (frontbuffer: 0x%03x)", obj
->frontbuffer_bits
);
202 static int i915_gem_object_list_info(struct seq_file
*m
, void *data
)
204 struct drm_info_node
*node
= m
->private;
205 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
206 struct list_head
*head
;
207 struct drm_device
*dev
= node
->minor
->dev
;
208 struct drm_i915_private
*dev_priv
= to_i915(dev
);
209 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
210 struct i915_vma
*vma
;
211 u64 total_obj_size
, total_gtt_size
;
214 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
218 /* FIXME: the user of this interface might want more than just GGTT */
221 seq_puts(m
, "Active:\n");
222 head
= &ggtt
->base
.active_list
;
225 seq_puts(m
, "Inactive:\n");
226 head
= &ggtt
->base
.inactive_list
;
229 mutex_unlock(&dev
->struct_mutex
);
233 total_obj_size
= total_gtt_size
= count
= 0;
234 list_for_each_entry(vma
, head
, vm_link
) {
236 describe_obj(m
, vma
->obj
);
238 total_obj_size
+= vma
->obj
->base
.size
;
239 total_gtt_size
+= vma
->node
.size
;
242 mutex_unlock(&dev
->struct_mutex
);
244 seq_printf(m
, "Total %d objects, %llu bytes, %llu GTT size\n",
245 count
, total_obj_size
, total_gtt_size
);
249 static int obj_rank_by_stolen(void *priv
,
250 struct list_head
*A
, struct list_head
*B
)
252 struct drm_i915_gem_object
*a
=
253 container_of(A
, struct drm_i915_gem_object
, obj_exec_link
);
254 struct drm_i915_gem_object
*b
=
255 container_of(B
, struct drm_i915_gem_object
, obj_exec_link
);
257 if (a
->stolen
->start
< b
->stolen
->start
)
259 if (a
->stolen
->start
> b
->stolen
->start
)
264 static int i915_gem_stolen_list_info(struct seq_file
*m
, void *data
)
266 struct drm_info_node
*node
= m
->private;
267 struct drm_device
*dev
= node
->minor
->dev
;
268 struct drm_i915_private
*dev_priv
= to_i915(dev
);
269 struct drm_i915_gem_object
*obj
;
270 u64 total_obj_size
, total_gtt_size
;
274 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
278 total_obj_size
= total_gtt_size
= count
= 0;
279 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
280 if (obj
->stolen
== NULL
)
283 list_add(&obj
->obj_exec_link
, &stolen
);
285 total_obj_size
+= obj
->base
.size
;
286 total_gtt_size
+= i915_gem_obj_total_ggtt_size(obj
);
289 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
290 if (obj
->stolen
== NULL
)
293 list_add(&obj
->obj_exec_link
, &stolen
);
295 total_obj_size
+= obj
->base
.size
;
298 list_sort(NULL
, &stolen
, obj_rank_by_stolen
);
299 seq_puts(m
, "Stolen:\n");
300 while (!list_empty(&stolen
)) {
301 obj
= list_first_entry(&stolen
, typeof(*obj
), obj_exec_link
);
303 describe_obj(m
, obj
);
305 list_del_init(&obj
->obj_exec_link
);
307 mutex_unlock(&dev
->struct_mutex
);
309 seq_printf(m
, "Total %d objects, %llu bytes, %llu GTT size\n",
310 count
, total_obj_size
, total_gtt_size
);
314 #define count_objects(list, member) do { \
315 list_for_each_entry(obj, list, member) { \
316 size += i915_gem_obj_total_ggtt_size(obj); \
318 if (obj->map_and_fenceable) { \
319 mappable_size += i915_gem_obj_ggtt_size(obj); \
326 struct drm_i915_file_private
*file_priv
;
330 u64 active
, inactive
;
333 static int per_file_stats(int id
, void *ptr
, void *data
)
335 struct drm_i915_gem_object
*obj
= ptr
;
336 struct file_stats
*stats
= data
;
337 struct i915_vma
*vma
;
340 stats
->total
+= obj
->base
.size
;
342 if (obj
->base
.name
|| obj
->base
.dma_buf
)
343 stats
->shared
+= obj
->base
.size
;
345 if (USES_FULL_PPGTT(obj
->base
.dev
)) {
346 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
347 struct i915_hw_ppgtt
*ppgtt
;
349 if (!drm_mm_node_allocated(&vma
->node
))
353 stats
->global
+= obj
->base
.size
;
357 ppgtt
= container_of(vma
->vm
, struct i915_hw_ppgtt
, base
);
358 if (ppgtt
->file_priv
!= stats
->file_priv
)
361 if (obj
->active
) /* XXX per-vma statistic */
362 stats
->active
+= obj
->base
.size
;
364 stats
->inactive
+= obj
->base
.size
;
369 if (i915_gem_obj_ggtt_bound(obj
)) {
370 stats
->global
+= obj
->base
.size
;
372 stats
->active
+= obj
->base
.size
;
374 stats
->inactive
+= obj
->base
.size
;
379 if (!list_empty(&obj
->global_list
))
380 stats
->unbound
+= obj
->base
.size
;
385 #define print_file_stats(m, name, stats) do { \
387 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
398 static void print_batch_pool_stats(struct seq_file
*m
,
399 struct drm_i915_private
*dev_priv
)
401 struct drm_i915_gem_object
*obj
;
402 struct file_stats stats
;
403 struct intel_engine_cs
*engine
;
406 memset(&stats
, 0, sizeof(stats
));
408 for_each_engine(engine
, dev_priv
) {
409 for (j
= 0; j
< ARRAY_SIZE(engine
->batch_pool
.cache_list
); j
++) {
410 list_for_each_entry(obj
,
411 &engine
->batch_pool
.cache_list
[j
],
413 per_file_stats(0, obj
, &stats
);
417 print_file_stats(m
, "[k]batch pool", stats
);
420 static int per_file_ctx_stats(int id
, void *ptr
, void *data
)
422 struct i915_gem_context
*ctx
= ptr
;
425 for (n
= 0; n
< ARRAY_SIZE(ctx
->engine
); n
++) {
426 if (ctx
->engine
[n
].state
)
427 per_file_stats(0, ctx
->engine
[n
].state
, data
);
428 if (ctx
->engine
[n
].ringbuf
)
429 per_file_stats(0, ctx
->engine
[n
].ringbuf
->obj
, data
);
435 static void print_context_stats(struct seq_file
*m
,
436 struct drm_i915_private
*dev_priv
)
438 struct file_stats stats
;
439 struct drm_file
*file
;
441 memset(&stats
, 0, sizeof(stats
));
443 mutex_lock(&dev_priv
->drm
.struct_mutex
);
444 if (dev_priv
->kernel_context
)
445 per_file_ctx_stats(0, dev_priv
->kernel_context
, &stats
);
447 list_for_each_entry(file
, &dev_priv
->drm
.filelist
, lhead
) {
448 struct drm_i915_file_private
*fpriv
= file
->driver_priv
;
449 idr_for_each(&fpriv
->context_idr
, per_file_ctx_stats
, &stats
);
451 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
453 print_file_stats(m
, "[k]contexts", stats
);
456 #define count_vmas(list, member) do { \
457 list_for_each_entry(vma, list, member) { \
458 size += i915_gem_obj_total_ggtt_size(vma->obj); \
460 if (vma->obj->map_and_fenceable) { \
461 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
467 static int i915_gem_object_info(struct seq_file
*m
, void* data
)
469 struct drm_info_node
*node
= m
->private;
470 struct drm_device
*dev
= node
->minor
->dev
;
471 struct drm_i915_private
*dev_priv
= to_i915(dev
);
472 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
473 u32 count
, mappable_count
, purgeable_count
;
474 u64 size
, mappable_size
, purgeable_size
;
475 unsigned long pin_mapped_count
= 0, pin_mapped_purgeable_count
= 0;
476 u64 pin_mapped_size
= 0, pin_mapped_purgeable_size
= 0;
477 struct drm_i915_gem_object
*obj
;
478 struct drm_file
*file
;
479 struct i915_vma
*vma
;
482 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
486 seq_printf(m
, "%u objects, %zu bytes\n",
487 dev_priv
->mm
.object_count
,
488 dev_priv
->mm
.object_memory
);
490 size
= count
= mappable_size
= mappable_count
= 0;
491 count_objects(&dev_priv
->mm
.bound_list
, global_list
);
492 seq_printf(m
, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
493 count
, mappable_count
, size
, mappable_size
);
495 size
= count
= mappable_size
= mappable_count
= 0;
496 count_vmas(&ggtt
->base
.active_list
, vm_link
);
497 seq_printf(m
, " %u [%u] active objects, %llu [%llu] bytes\n",
498 count
, mappable_count
, size
, mappable_size
);
500 size
= count
= mappable_size
= mappable_count
= 0;
501 count_vmas(&ggtt
->base
.inactive_list
, vm_link
);
502 seq_printf(m
, " %u [%u] inactive objects, %llu [%llu] bytes\n",
503 count
, mappable_count
, size
, mappable_size
);
505 size
= count
= purgeable_size
= purgeable_count
= 0;
506 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
507 size
+= obj
->base
.size
, ++count
;
508 if (obj
->madv
== I915_MADV_DONTNEED
)
509 purgeable_size
+= obj
->base
.size
, ++purgeable_count
;
512 pin_mapped_size
+= obj
->base
.size
;
513 if (obj
->pages_pin_count
== 0) {
514 pin_mapped_purgeable_count
++;
515 pin_mapped_purgeable_size
+= obj
->base
.size
;
519 seq_printf(m
, "%u unbound objects, %llu bytes\n", count
, size
);
521 size
= count
= mappable_size
= mappable_count
= 0;
522 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
523 if (obj
->fault_mappable
) {
524 size
+= i915_gem_obj_ggtt_size(obj
);
527 if (obj
->pin_display
) {
528 mappable_size
+= i915_gem_obj_ggtt_size(obj
);
531 if (obj
->madv
== I915_MADV_DONTNEED
) {
532 purgeable_size
+= obj
->base
.size
;
537 pin_mapped_size
+= obj
->base
.size
;
538 if (obj
->pages_pin_count
== 0) {
539 pin_mapped_purgeable_count
++;
540 pin_mapped_purgeable_size
+= obj
->base
.size
;
544 seq_printf(m
, "%u purgeable objects, %llu bytes\n",
545 purgeable_count
, purgeable_size
);
546 seq_printf(m
, "%u pinned mappable objects, %llu bytes\n",
547 mappable_count
, mappable_size
);
548 seq_printf(m
, "%u fault mappable objects, %llu bytes\n",
551 "%lu [%lu] pin mapped objects, %llu [%llu] bytes [purgeable]\n",
552 pin_mapped_count
, pin_mapped_purgeable_count
,
553 pin_mapped_size
, pin_mapped_purgeable_size
);
555 seq_printf(m
, "%llu [%llu] gtt total\n",
556 ggtt
->base
.total
, ggtt
->mappable_end
- ggtt
->base
.start
);
559 print_batch_pool_stats(m
, dev_priv
);
560 mutex_unlock(&dev
->struct_mutex
);
562 mutex_lock(&dev
->filelist_mutex
);
563 print_context_stats(m
, dev_priv
);
564 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
565 struct file_stats stats
;
566 struct task_struct
*task
;
568 memset(&stats
, 0, sizeof(stats
));
569 stats
.file_priv
= file
->driver_priv
;
570 spin_lock(&file
->table_lock
);
571 idr_for_each(&file
->object_idr
, per_file_stats
, &stats
);
572 spin_unlock(&file
->table_lock
);
574 * Although we have a valid reference on file->pid, that does
575 * not guarantee that the task_struct who called get_pid() is
576 * still alive (e.g. get_pid(current) => fork() => exit()).
577 * Therefore, we need to protect this ->comm access using RCU.
580 task
= pid_task(file
->pid
, PIDTYPE_PID
);
581 print_file_stats(m
, task
? task
->comm
: "<unknown>", stats
);
584 mutex_unlock(&dev
->filelist_mutex
);
589 static int i915_gem_gtt_info(struct seq_file
*m
, void *data
)
591 struct drm_info_node
*node
= m
->private;
592 struct drm_device
*dev
= node
->minor
->dev
;
593 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
594 struct drm_i915_private
*dev_priv
= to_i915(dev
);
595 struct drm_i915_gem_object
*obj
;
596 u64 total_obj_size
, total_gtt_size
;
599 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
603 total_obj_size
= total_gtt_size
= count
= 0;
604 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
605 if (list
== PINNED_LIST
&& !i915_gem_obj_is_pinned(obj
))
609 describe_obj(m
, obj
);
611 total_obj_size
+= obj
->base
.size
;
612 total_gtt_size
+= i915_gem_obj_total_ggtt_size(obj
);
616 mutex_unlock(&dev
->struct_mutex
);
618 seq_printf(m
, "Total %d objects, %llu bytes, %llu GTT size\n",
619 count
, total_obj_size
, total_gtt_size
);
624 static int i915_gem_pageflip_info(struct seq_file
*m
, void *data
)
626 struct drm_info_node
*node
= m
->private;
627 struct drm_device
*dev
= node
->minor
->dev
;
628 struct drm_i915_private
*dev_priv
= to_i915(dev
);
629 struct intel_crtc
*crtc
;
632 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
636 for_each_intel_crtc(dev
, crtc
) {
637 const char pipe
= pipe_name(crtc
->pipe
);
638 const char plane
= plane_name(crtc
->plane
);
639 struct intel_flip_work
*work
;
641 spin_lock_irq(&dev
->event_lock
);
642 work
= crtc
->flip_work
;
644 seq_printf(m
, "No flip due on pipe %c (plane %c)\n",
650 pending
= atomic_read(&work
->pending
);
652 seq_printf(m
, "Flip ioctl preparing on pipe %c (plane %c)\n",
655 seq_printf(m
, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
658 if (work
->flip_queued_req
) {
659 struct intel_engine_cs
*engine
= i915_gem_request_get_engine(work
->flip_queued_req
);
661 seq_printf(m
, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
663 i915_gem_request_get_seqno(work
->flip_queued_req
),
664 dev_priv
->next_seqno
,
665 intel_engine_get_seqno(engine
),
666 i915_gem_request_completed(work
->flip_queued_req
));
668 seq_printf(m
, "Flip not associated with any ring\n");
669 seq_printf(m
, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
670 work
->flip_queued_vblank
,
671 work
->flip_ready_vblank
,
672 intel_crtc_get_vblank_counter(crtc
));
673 seq_printf(m
, "%d prepares\n", atomic_read(&work
->pending
));
675 if (INTEL_INFO(dev
)->gen
>= 4)
676 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(crtc
->plane
)));
678 addr
= I915_READ(DSPADDR(crtc
->plane
));
679 seq_printf(m
, "Current scanout address 0x%08x\n", addr
);
681 if (work
->pending_flip_obj
) {
682 seq_printf(m
, "New framebuffer address 0x%08lx\n", (long)work
->gtt_offset
);
683 seq_printf(m
, "MMIO update completed? %d\n", addr
== work
->gtt_offset
);
686 spin_unlock_irq(&dev
->event_lock
);
689 mutex_unlock(&dev
->struct_mutex
);
694 static int i915_gem_batch_pool_info(struct seq_file
*m
, void *data
)
696 struct drm_info_node
*node
= m
->private;
697 struct drm_device
*dev
= node
->minor
->dev
;
698 struct drm_i915_private
*dev_priv
= to_i915(dev
);
699 struct drm_i915_gem_object
*obj
;
700 struct intel_engine_cs
*engine
;
704 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
708 for_each_engine(engine
, dev_priv
) {
709 for (j
= 0; j
< ARRAY_SIZE(engine
->batch_pool
.cache_list
); j
++) {
713 list_for_each_entry(obj
,
714 &engine
->batch_pool
.cache_list
[j
],
717 seq_printf(m
, "%s cache[%d]: %d objects\n",
718 engine
->name
, j
, count
);
720 list_for_each_entry(obj
,
721 &engine
->batch_pool
.cache_list
[j
],
724 describe_obj(m
, obj
);
732 seq_printf(m
, "total: %d\n", total
);
734 mutex_unlock(&dev
->struct_mutex
);
739 static int i915_gem_request_info(struct seq_file
*m
, void *data
)
741 struct drm_info_node
*node
= m
->private;
742 struct drm_device
*dev
= node
->minor
->dev
;
743 struct drm_i915_private
*dev_priv
= to_i915(dev
);
744 struct intel_engine_cs
*engine
;
745 struct drm_i915_gem_request
*req
;
748 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
753 for_each_engine(engine
, dev_priv
) {
757 list_for_each_entry(req
, &engine
->request_list
, list
)
762 seq_printf(m
, "%s requests: %d\n", engine
->name
, count
);
763 list_for_each_entry(req
, &engine
->request_list
, list
) {
764 struct task_struct
*task
;
769 task
= pid_task(req
->pid
, PIDTYPE_PID
);
770 seq_printf(m
, " %x @ %d: %s [%d]\n",
772 (int) (jiffies
- req
->emitted_jiffies
),
773 task
? task
->comm
: "<unknown>",
774 task
? task
->pid
: -1);
780 mutex_unlock(&dev
->struct_mutex
);
783 seq_puts(m
, "No requests\n");
788 static void i915_ring_seqno_info(struct seq_file
*m
,
789 struct intel_engine_cs
*engine
)
791 struct intel_breadcrumbs
*b
= &engine
->breadcrumbs
;
794 seq_printf(m
, "Current sequence (%s): %x\n",
795 engine
->name
, intel_engine_get_seqno(engine
));
796 seq_printf(m
, "Current user interrupts (%s): %lx\n",
797 engine
->name
, READ_ONCE(engine
->breadcrumbs
.irq_wakeups
));
800 for (rb
= rb_first(&b
->waiters
); rb
; rb
= rb_next(rb
)) {
801 struct intel_wait
*w
= container_of(rb
, typeof(*w
), node
);
803 seq_printf(m
, "Waiting (%s): %s [%d] on %x\n",
804 engine
->name
, w
->tsk
->comm
, w
->tsk
->pid
, w
->seqno
);
806 spin_unlock(&b
->lock
);
809 static int i915_gem_seqno_info(struct seq_file
*m
, void *data
)
811 struct drm_info_node
*node
= m
->private;
812 struct drm_device
*dev
= node
->minor
->dev
;
813 struct drm_i915_private
*dev_priv
= to_i915(dev
);
814 struct intel_engine_cs
*engine
;
817 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
820 intel_runtime_pm_get(dev_priv
);
822 for_each_engine(engine
, dev_priv
)
823 i915_ring_seqno_info(m
, engine
);
825 intel_runtime_pm_put(dev_priv
);
826 mutex_unlock(&dev
->struct_mutex
);
832 static int i915_interrupt_info(struct seq_file
*m
, void *data
)
834 struct drm_info_node
*node
= m
->private;
835 struct drm_device
*dev
= node
->minor
->dev
;
836 struct drm_i915_private
*dev_priv
= to_i915(dev
);
837 struct intel_engine_cs
*engine
;
840 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
843 intel_runtime_pm_get(dev_priv
);
845 if (IS_CHERRYVIEW(dev
)) {
846 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
847 I915_READ(GEN8_MASTER_IRQ
));
849 seq_printf(m
, "Display IER:\t%08x\n",
851 seq_printf(m
, "Display IIR:\t%08x\n",
853 seq_printf(m
, "Display IIR_RW:\t%08x\n",
854 I915_READ(VLV_IIR_RW
));
855 seq_printf(m
, "Display IMR:\t%08x\n",
857 for_each_pipe(dev_priv
, pipe
)
858 seq_printf(m
, "Pipe %c stat:\t%08x\n",
860 I915_READ(PIPESTAT(pipe
)));
862 seq_printf(m
, "Port hotplug:\t%08x\n",
863 I915_READ(PORT_HOTPLUG_EN
));
864 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
865 I915_READ(VLV_DPFLIPSTAT
));
866 seq_printf(m
, "DPINVGTT:\t%08x\n",
867 I915_READ(DPINVGTT
));
869 for (i
= 0; i
< 4; i
++) {
870 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
871 i
, I915_READ(GEN8_GT_IMR(i
)));
872 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
873 i
, I915_READ(GEN8_GT_IIR(i
)));
874 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
875 i
, I915_READ(GEN8_GT_IER(i
)));
878 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
879 I915_READ(GEN8_PCU_IMR
));
880 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
881 I915_READ(GEN8_PCU_IIR
));
882 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
883 I915_READ(GEN8_PCU_IER
));
884 } else if (INTEL_INFO(dev
)->gen
>= 8) {
885 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
886 I915_READ(GEN8_MASTER_IRQ
));
888 for (i
= 0; i
< 4; i
++) {
889 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
890 i
, I915_READ(GEN8_GT_IMR(i
)));
891 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
892 i
, I915_READ(GEN8_GT_IIR(i
)));
893 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
894 i
, I915_READ(GEN8_GT_IER(i
)));
897 for_each_pipe(dev_priv
, pipe
) {
898 enum intel_display_power_domain power_domain
;
900 power_domain
= POWER_DOMAIN_PIPE(pipe
);
901 if (!intel_display_power_get_if_enabled(dev_priv
,
903 seq_printf(m
, "Pipe %c power disabled\n",
907 seq_printf(m
, "Pipe %c IMR:\t%08x\n",
909 I915_READ(GEN8_DE_PIPE_IMR(pipe
)));
910 seq_printf(m
, "Pipe %c IIR:\t%08x\n",
912 I915_READ(GEN8_DE_PIPE_IIR(pipe
)));
913 seq_printf(m
, "Pipe %c IER:\t%08x\n",
915 I915_READ(GEN8_DE_PIPE_IER(pipe
)));
917 intel_display_power_put(dev_priv
, power_domain
);
920 seq_printf(m
, "Display Engine port interrupt mask:\t%08x\n",
921 I915_READ(GEN8_DE_PORT_IMR
));
922 seq_printf(m
, "Display Engine port interrupt identity:\t%08x\n",
923 I915_READ(GEN8_DE_PORT_IIR
));
924 seq_printf(m
, "Display Engine port interrupt enable:\t%08x\n",
925 I915_READ(GEN8_DE_PORT_IER
));
927 seq_printf(m
, "Display Engine misc interrupt mask:\t%08x\n",
928 I915_READ(GEN8_DE_MISC_IMR
));
929 seq_printf(m
, "Display Engine misc interrupt identity:\t%08x\n",
930 I915_READ(GEN8_DE_MISC_IIR
));
931 seq_printf(m
, "Display Engine misc interrupt enable:\t%08x\n",
932 I915_READ(GEN8_DE_MISC_IER
));
934 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
935 I915_READ(GEN8_PCU_IMR
));
936 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
937 I915_READ(GEN8_PCU_IIR
));
938 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
939 I915_READ(GEN8_PCU_IER
));
940 } else if (IS_VALLEYVIEW(dev
)) {
941 seq_printf(m
, "Display IER:\t%08x\n",
943 seq_printf(m
, "Display IIR:\t%08x\n",
945 seq_printf(m
, "Display IIR_RW:\t%08x\n",
946 I915_READ(VLV_IIR_RW
));
947 seq_printf(m
, "Display IMR:\t%08x\n",
949 for_each_pipe(dev_priv
, pipe
)
950 seq_printf(m
, "Pipe %c stat:\t%08x\n",
952 I915_READ(PIPESTAT(pipe
)));
954 seq_printf(m
, "Master IER:\t%08x\n",
955 I915_READ(VLV_MASTER_IER
));
957 seq_printf(m
, "Render IER:\t%08x\n",
959 seq_printf(m
, "Render IIR:\t%08x\n",
961 seq_printf(m
, "Render IMR:\t%08x\n",
964 seq_printf(m
, "PM IER:\t\t%08x\n",
965 I915_READ(GEN6_PMIER
));
966 seq_printf(m
, "PM IIR:\t\t%08x\n",
967 I915_READ(GEN6_PMIIR
));
968 seq_printf(m
, "PM IMR:\t\t%08x\n",
969 I915_READ(GEN6_PMIMR
));
971 seq_printf(m
, "Port hotplug:\t%08x\n",
972 I915_READ(PORT_HOTPLUG_EN
));
973 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
974 I915_READ(VLV_DPFLIPSTAT
));
975 seq_printf(m
, "DPINVGTT:\t%08x\n",
976 I915_READ(DPINVGTT
));
978 } else if (!HAS_PCH_SPLIT(dev
)) {
979 seq_printf(m
, "Interrupt enable: %08x\n",
981 seq_printf(m
, "Interrupt identity: %08x\n",
983 seq_printf(m
, "Interrupt mask: %08x\n",
985 for_each_pipe(dev_priv
, pipe
)
986 seq_printf(m
, "Pipe %c stat: %08x\n",
988 I915_READ(PIPESTAT(pipe
)));
990 seq_printf(m
, "North Display Interrupt enable: %08x\n",
992 seq_printf(m
, "North Display Interrupt identity: %08x\n",
994 seq_printf(m
, "North Display Interrupt mask: %08x\n",
996 seq_printf(m
, "South Display Interrupt enable: %08x\n",
998 seq_printf(m
, "South Display Interrupt identity: %08x\n",
1000 seq_printf(m
, "South Display Interrupt mask: %08x\n",
1002 seq_printf(m
, "Graphics Interrupt enable: %08x\n",
1004 seq_printf(m
, "Graphics Interrupt identity: %08x\n",
1006 seq_printf(m
, "Graphics Interrupt mask: %08x\n",
1009 for_each_engine(engine
, dev_priv
) {
1010 if (INTEL_INFO(dev
)->gen
>= 6) {
1012 "Graphics Interrupt mask (%s): %08x\n",
1013 engine
->name
, I915_READ_IMR(engine
));
1015 i915_ring_seqno_info(m
, engine
);
1017 intel_runtime_pm_put(dev_priv
);
1018 mutex_unlock(&dev
->struct_mutex
);
1023 static int i915_gem_fence_regs_info(struct seq_file
*m
, void *data
)
1025 struct drm_info_node
*node
= m
->private;
1026 struct drm_device
*dev
= node
->minor
->dev
;
1027 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1030 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1034 seq_printf(m
, "Total fences = %d\n", dev_priv
->num_fence_regs
);
1035 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
1036 struct drm_i915_gem_object
*obj
= dev_priv
->fence_regs
[i
].obj
;
1038 seq_printf(m
, "Fence %d, pin count = %d, object = ",
1039 i
, dev_priv
->fence_regs
[i
].pin_count
);
1041 seq_puts(m
, "unused");
1043 describe_obj(m
, obj
);
1047 mutex_unlock(&dev
->struct_mutex
);
1051 static int i915_hws_info(struct seq_file
*m
, void *data
)
1053 struct drm_info_node
*node
= m
->private;
1054 struct drm_device
*dev
= node
->minor
->dev
;
1055 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1056 struct intel_engine_cs
*engine
;
1060 engine
= &dev_priv
->engine
[(uintptr_t)node
->info_ent
->data
];
1061 hws
= engine
->status_page
.page_addr
;
1065 for (i
= 0; i
< 4096 / sizeof(u32
) / 4; i
+= 4) {
1066 seq_printf(m
, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1068 hws
[i
], hws
[i
+ 1], hws
[i
+ 2], hws
[i
+ 3]);
1074 i915_error_state_write(struct file
*filp
,
1075 const char __user
*ubuf
,
1079 struct i915_error_state_file_priv
*error_priv
= filp
->private_data
;
1080 struct drm_device
*dev
= error_priv
->dev
;
1083 DRM_DEBUG_DRIVER("Resetting error state\n");
1085 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1089 i915_destroy_error_state(dev
);
1090 mutex_unlock(&dev
->struct_mutex
);
1095 static int i915_error_state_open(struct inode
*inode
, struct file
*file
)
1097 struct drm_device
*dev
= inode
->i_private
;
1098 struct i915_error_state_file_priv
*error_priv
;
1100 error_priv
= kzalloc(sizeof(*error_priv
), GFP_KERNEL
);
1104 error_priv
->dev
= dev
;
1106 i915_error_state_get(dev
, error_priv
);
1108 file
->private_data
= error_priv
;
1113 static int i915_error_state_release(struct inode
*inode
, struct file
*file
)
1115 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
1117 i915_error_state_put(error_priv
);
1123 static ssize_t
i915_error_state_read(struct file
*file
, char __user
*userbuf
,
1124 size_t count
, loff_t
*pos
)
1126 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
1127 struct drm_i915_error_state_buf error_str
;
1129 ssize_t ret_count
= 0;
1132 ret
= i915_error_state_buf_init(&error_str
, to_i915(error_priv
->dev
), count
, *pos
);
1136 ret
= i915_error_state_to_str(&error_str
, error_priv
);
1140 ret_count
= simple_read_from_buffer(userbuf
, count
, &tmp_pos
,
1147 *pos
= error_str
.start
+ ret_count
;
1149 i915_error_state_buf_release(&error_str
);
1150 return ret
?: ret_count
;
1153 static const struct file_operations i915_error_state_fops
= {
1154 .owner
= THIS_MODULE
,
1155 .open
= i915_error_state_open
,
1156 .read
= i915_error_state_read
,
1157 .write
= i915_error_state_write
,
1158 .llseek
= default_llseek
,
1159 .release
= i915_error_state_release
,
1163 i915_next_seqno_get(void *data
, u64
*val
)
1165 struct drm_device
*dev
= data
;
1166 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1169 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1173 *val
= dev_priv
->next_seqno
;
1174 mutex_unlock(&dev
->struct_mutex
);
1180 i915_next_seqno_set(void *data
, u64 val
)
1182 struct drm_device
*dev
= data
;
1185 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1189 ret
= i915_gem_set_seqno(dev
, val
);
1190 mutex_unlock(&dev
->struct_mutex
);
1195 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops
,
1196 i915_next_seqno_get
, i915_next_seqno_set
,
1199 static int i915_frequency_info(struct seq_file
*m
, void *unused
)
1201 struct drm_info_node
*node
= m
->private;
1202 struct drm_device
*dev
= node
->minor
->dev
;
1203 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1206 intel_runtime_pm_get(dev_priv
);
1208 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
1211 u16 rgvswctl
= I915_READ16(MEMSWCTL
);
1212 u16 rgvstat
= I915_READ16(MEMSTAT_ILK
);
1214 seq_printf(m
, "Requested P-state: %d\n", (rgvswctl
>> 8) & 0xf);
1215 seq_printf(m
, "Requested VID: %d\n", rgvswctl
& 0x3f);
1216 seq_printf(m
, "Current VID: %d\n", (rgvstat
& MEMSTAT_VID_MASK
) >>
1218 seq_printf(m
, "Current P-state: %d\n",
1219 (rgvstat
& MEMSTAT_PSTATE_MASK
) >> MEMSTAT_PSTATE_SHIFT
);
1220 } else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
1223 mutex_lock(&dev_priv
->rps
.hw_lock
);
1224 freq_sts
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
1225 seq_printf(m
, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts
);
1226 seq_printf(m
, "DDR freq: %d MHz\n", dev_priv
->mem_freq
);
1228 seq_printf(m
, "actual GPU freq: %d MHz\n",
1229 intel_gpu_freq(dev_priv
, (freq_sts
>> 8) & 0xff));
1231 seq_printf(m
, "current GPU freq: %d MHz\n",
1232 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
));
1234 seq_printf(m
, "max GPU freq: %d MHz\n",
1235 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1237 seq_printf(m
, "min GPU freq: %d MHz\n",
1238 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
));
1240 seq_printf(m
, "idle GPU freq: %d MHz\n",
1241 intel_gpu_freq(dev_priv
, dev_priv
->rps
.idle_freq
));
1244 "efficient (RPe) frequency: %d MHz\n",
1245 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
));
1246 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1247 } else if (INTEL_INFO(dev
)->gen
>= 6) {
1248 u32 rp_state_limits
;
1251 u32 rpmodectl
, rpinclimit
, rpdeclimit
;
1252 u32 rpstat
, cagf
, reqf
;
1253 u32 rpupei
, rpcurup
, rpprevup
;
1254 u32 rpdownei
, rpcurdown
, rpprevdown
;
1255 u32 pm_ier
, pm_imr
, pm_isr
, pm_iir
, pm_mask
;
1258 rp_state_limits
= I915_READ(GEN6_RP_STATE_LIMITS
);
1259 if (IS_BROXTON(dev
)) {
1260 rp_state_cap
= I915_READ(BXT_RP_STATE_CAP
);
1261 gt_perf_status
= I915_READ(BXT_GT_PERF_STATUS
);
1263 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
1264 gt_perf_status
= I915_READ(GEN6_GT_PERF_STATUS
);
1267 /* RPSTAT1 is in the GT power well */
1268 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1272 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
1274 reqf
= I915_READ(GEN6_RPNSWREQ
);
1278 reqf
&= ~GEN6_TURBO_DISABLE
;
1279 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1284 reqf
= intel_gpu_freq(dev_priv
, reqf
);
1286 rpmodectl
= I915_READ(GEN6_RP_CONTROL
);
1287 rpinclimit
= I915_READ(GEN6_RP_UP_THRESHOLD
);
1288 rpdeclimit
= I915_READ(GEN6_RP_DOWN_THRESHOLD
);
1290 rpstat
= I915_READ(GEN6_RPSTAT1
);
1291 rpupei
= I915_READ(GEN6_RP_CUR_UP_EI
) & GEN6_CURICONT_MASK
;
1292 rpcurup
= I915_READ(GEN6_RP_CUR_UP
) & GEN6_CURBSYTAVG_MASK
;
1293 rpprevup
= I915_READ(GEN6_RP_PREV_UP
) & GEN6_CURBSYTAVG_MASK
;
1294 rpdownei
= I915_READ(GEN6_RP_CUR_DOWN_EI
) & GEN6_CURIAVG_MASK
;
1295 rpcurdown
= I915_READ(GEN6_RP_CUR_DOWN
) & GEN6_CURBSYTAVG_MASK
;
1296 rpprevdown
= I915_READ(GEN6_RP_PREV_DOWN
) & GEN6_CURBSYTAVG_MASK
;
1298 cagf
= (rpstat
& GEN9_CAGF_MASK
) >> GEN9_CAGF_SHIFT
;
1299 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1300 cagf
= (rpstat
& HSW_CAGF_MASK
) >> HSW_CAGF_SHIFT
;
1302 cagf
= (rpstat
& GEN6_CAGF_MASK
) >> GEN6_CAGF_SHIFT
;
1303 cagf
= intel_gpu_freq(dev_priv
, cagf
);
1305 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
1306 mutex_unlock(&dev
->struct_mutex
);
1308 if (IS_GEN6(dev
) || IS_GEN7(dev
)) {
1309 pm_ier
= I915_READ(GEN6_PMIER
);
1310 pm_imr
= I915_READ(GEN6_PMIMR
);
1311 pm_isr
= I915_READ(GEN6_PMISR
);
1312 pm_iir
= I915_READ(GEN6_PMIIR
);
1313 pm_mask
= I915_READ(GEN6_PMINTRMSK
);
1315 pm_ier
= I915_READ(GEN8_GT_IER(2));
1316 pm_imr
= I915_READ(GEN8_GT_IMR(2));
1317 pm_isr
= I915_READ(GEN8_GT_ISR(2));
1318 pm_iir
= I915_READ(GEN8_GT_IIR(2));
1319 pm_mask
= I915_READ(GEN6_PMINTRMSK
);
1321 seq_printf(m
, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1322 pm_ier
, pm_imr
, pm_isr
, pm_iir
, pm_mask
);
1323 seq_printf(m
, "pm_intr_keep: 0x%08x\n", dev_priv
->rps
.pm_intr_keep
);
1324 seq_printf(m
, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status
);
1325 seq_printf(m
, "Render p-state ratio: %d\n",
1326 (gt_perf_status
& (IS_GEN9(dev
) ? 0x1ff00 : 0xff00)) >> 8);
1327 seq_printf(m
, "Render p-state VID: %d\n",
1328 gt_perf_status
& 0xff);
1329 seq_printf(m
, "Render p-state limit: %d\n",
1330 rp_state_limits
& 0xff);
1331 seq_printf(m
, "RPSTAT1: 0x%08x\n", rpstat
);
1332 seq_printf(m
, "RPMODECTL: 0x%08x\n", rpmodectl
);
1333 seq_printf(m
, "RPINCLIMIT: 0x%08x\n", rpinclimit
);
1334 seq_printf(m
, "RPDECLIMIT: 0x%08x\n", rpdeclimit
);
1335 seq_printf(m
, "RPNSWREQ: %dMHz\n", reqf
);
1336 seq_printf(m
, "CAGF: %dMHz\n", cagf
);
1337 seq_printf(m
, "RP CUR UP EI: %d (%dus)\n",
1338 rpupei
, GT_PM_INTERVAL_TO_US(dev_priv
, rpupei
));
1339 seq_printf(m
, "RP CUR UP: %d (%dus)\n",
1340 rpcurup
, GT_PM_INTERVAL_TO_US(dev_priv
, rpcurup
));
1341 seq_printf(m
, "RP PREV UP: %d (%dus)\n",
1342 rpprevup
, GT_PM_INTERVAL_TO_US(dev_priv
, rpprevup
));
1343 seq_printf(m
, "Up threshold: %d%%\n",
1344 dev_priv
->rps
.up_threshold
);
1346 seq_printf(m
, "RP CUR DOWN EI: %d (%dus)\n",
1347 rpdownei
, GT_PM_INTERVAL_TO_US(dev_priv
, rpdownei
));
1348 seq_printf(m
, "RP CUR DOWN: %d (%dus)\n",
1349 rpcurdown
, GT_PM_INTERVAL_TO_US(dev_priv
, rpcurdown
));
1350 seq_printf(m
, "RP PREV DOWN: %d (%dus)\n",
1351 rpprevdown
, GT_PM_INTERVAL_TO_US(dev_priv
, rpprevdown
));
1352 seq_printf(m
, "Down threshold: %d%%\n",
1353 dev_priv
->rps
.down_threshold
);
1355 max_freq
= (IS_BROXTON(dev
) ? rp_state_cap
>> 0 :
1356 rp_state_cap
>> 16) & 0xff;
1357 max_freq
*= (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
) ?
1358 GEN9_FREQ_SCALER
: 1);
1359 seq_printf(m
, "Lowest (RPN) frequency: %dMHz\n",
1360 intel_gpu_freq(dev_priv
, max_freq
));
1362 max_freq
= (rp_state_cap
& 0xff00) >> 8;
1363 max_freq
*= (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
) ?
1364 GEN9_FREQ_SCALER
: 1);
1365 seq_printf(m
, "Nominal (RP1) frequency: %dMHz\n",
1366 intel_gpu_freq(dev_priv
, max_freq
));
1368 max_freq
= (IS_BROXTON(dev
) ? rp_state_cap
>> 16 :
1369 rp_state_cap
>> 0) & 0xff;
1370 max_freq
*= (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
) ?
1371 GEN9_FREQ_SCALER
: 1);
1372 seq_printf(m
, "Max non-overclocked (RP0) frequency: %dMHz\n",
1373 intel_gpu_freq(dev_priv
, max_freq
));
1374 seq_printf(m
, "Max overclocked frequency: %dMHz\n",
1375 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1377 seq_printf(m
, "Current freq: %d MHz\n",
1378 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
));
1379 seq_printf(m
, "Actual freq: %d MHz\n", cagf
);
1380 seq_printf(m
, "Idle freq: %d MHz\n",
1381 intel_gpu_freq(dev_priv
, dev_priv
->rps
.idle_freq
));
1382 seq_printf(m
, "Min freq: %d MHz\n",
1383 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
));
1384 seq_printf(m
, "Boost freq: %d MHz\n",
1385 intel_gpu_freq(dev_priv
, dev_priv
->rps
.boost_freq
));
1386 seq_printf(m
, "Max freq: %d MHz\n",
1387 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1389 "efficient (RPe) frequency: %d MHz\n",
1390 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
));
1392 seq_puts(m
, "no P-state info available\n");
1395 seq_printf(m
, "Current CD clock frequency: %d kHz\n", dev_priv
->cdclk_freq
);
1396 seq_printf(m
, "Max CD clock frequency: %d kHz\n", dev_priv
->max_cdclk_freq
);
1397 seq_printf(m
, "Max pixel clock frequency: %d kHz\n", dev_priv
->max_dotclk_freq
);
1400 intel_runtime_pm_put(dev_priv
);
1404 static int i915_hangcheck_info(struct seq_file
*m
, void *unused
)
1406 struct drm_info_node
*node
= m
->private;
1407 struct drm_device
*dev
= node
->minor
->dev
;
1408 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1409 struct intel_engine_cs
*engine
;
1410 u64 acthd
[I915_NUM_ENGINES
];
1411 u32 seqno
[I915_NUM_ENGINES
];
1412 u32 instdone
[I915_NUM_INSTDONE_REG
];
1413 enum intel_engine_id id
;
1416 if (!i915
.enable_hangcheck
) {
1417 seq_printf(m
, "Hangcheck disabled\n");
1421 intel_runtime_pm_get(dev_priv
);
1423 for_each_engine_id(engine
, dev_priv
, id
) {
1424 acthd
[id
] = intel_ring_get_active_head(engine
);
1425 seqno
[id
] = intel_engine_get_seqno(engine
);
1428 i915_get_extra_instdone(dev_priv
, instdone
);
1430 intel_runtime_pm_put(dev_priv
);
1432 if (delayed_work_pending(&dev_priv
->gpu_error
.hangcheck_work
)) {
1433 seq_printf(m
, "Hangcheck active, fires in %dms\n",
1434 jiffies_to_msecs(dev_priv
->gpu_error
.hangcheck_work
.timer
.expires
-
1437 seq_printf(m
, "Hangcheck inactive\n");
1439 for_each_engine_id(engine
, dev_priv
, id
) {
1440 seq_printf(m
, "%s:\n", engine
->name
);
1441 seq_printf(m
, "\tseqno = %x [current %x, last %x]\n",
1442 engine
->hangcheck
.seqno
,
1444 engine
->last_submitted_seqno
);
1445 seq_printf(m
, "\twaiters? %d\n",
1446 intel_engine_has_waiter(engine
));
1447 seq_printf(m
, "\tuser interrupts = %lx [current %lx]\n",
1448 engine
->hangcheck
.user_interrupts
,
1449 READ_ONCE(engine
->breadcrumbs
.irq_wakeups
));
1450 seq_printf(m
, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1451 (long long)engine
->hangcheck
.acthd
,
1452 (long long)acthd
[id
]);
1453 seq_printf(m
, "\tscore = %d\n", engine
->hangcheck
.score
);
1454 seq_printf(m
, "\taction = %d\n", engine
->hangcheck
.action
);
1456 if (engine
->id
== RCS
) {
1457 seq_puts(m
, "\tinstdone read =");
1459 for (j
= 0; j
< I915_NUM_INSTDONE_REG
; j
++)
1460 seq_printf(m
, " 0x%08x", instdone
[j
]);
1462 seq_puts(m
, "\n\tinstdone accu =");
1464 for (j
= 0; j
< I915_NUM_INSTDONE_REG
; j
++)
1465 seq_printf(m
, " 0x%08x",
1466 engine
->hangcheck
.instdone
[j
]);
1475 static int ironlake_drpc_info(struct seq_file
*m
)
1477 struct drm_info_node
*node
= m
->private;
1478 struct drm_device
*dev
= node
->minor
->dev
;
1479 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1480 u32 rgvmodectl
, rstdbyctl
;
1484 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1487 intel_runtime_pm_get(dev_priv
);
1489 rgvmodectl
= I915_READ(MEMMODECTL
);
1490 rstdbyctl
= I915_READ(RSTDBYCTL
);
1491 crstandvid
= I915_READ16(CRSTANDVID
);
1493 intel_runtime_pm_put(dev_priv
);
1494 mutex_unlock(&dev
->struct_mutex
);
1496 seq_printf(m
, "HD boost: %s\n", yesno(rgvmodectl
& MEMMODE_BOOST_EN
));
1497 seq_printf(m
, "Boost freq: %d\n",
1498 (rgvmodectl
& MEMMODE_BOOST_FREQ_MASK
) >>
1499 MEMMODE_BOOST_FREQ_SHIFT
);
1500 seq_printf(m
, "HW control enabled: %s\n",
1501 yesno(rgvmodectl
& MEMMODE_HWIDLE_EN
));
1502 seq_printf(m
, "SW control enabled: %s\n",
1503 yesno(rgvmodectl
& MEMMODE_SWMODE_EN
));
1504 seq_printf(m
, "Gated voltage change: %s\n",
1505 yesno(rgvmodectl
& MEMMODE_RCLK_GATE
));
1506 seq_printf(m
, "Starting frequency: P%d\n",
1507 (rgvmodectl
& MEMMODE_FSTART_MASK
) >> MEMMODE_FSTART_SHIFT
);
1508 seq_printf(m
, "Max P-state: P%d\n",
1509 (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
);
1510 seq_printf(m
, "Min P-state: P%d\n", (rgvmodectl
& MEMMODE_FMIN_MASK
));
1511 seq_printf(m
, "RS1 VID: %d\n", (crstandvid
& 0x3f));
1512 seq_printf(m
, "RS2 VID: %d\n", ((crstandvid
>> 8) & 0x3f));
1513 seq_printf(m
, "Render standby enabled: %s\n",
1514 yesno(!(rstdbyctl
& RCX_SW_EXIT
)));
1515 seq_puts(m
, "Current RS state: ");
1516 switch (rstdbyctl
& RSX_STATUS_MASK
) {
1518 seq_puts(m
, "on\n");
1520 case RSX_STATUS_RC1
:
1521 seq_puts(m
, "RC1\n");
1523 case RSX_STATUS_RC1E
:
1524 seq_puts(m
, "RC1E\n");
1526 case RSX_STATUS_RS1
:
1527 seq_puts(m
, "RS1\n");
1529 case RSX_STATUS_RS2
:
1530 seq_puts(m
, "RS2 (RC6)\n");
1532 case RSX_STATUS_RS3
:
1533 seq_puts(m
, "RC3 (RC6+)\n");
1536 seq_puts(m
, "unknown\n");
1543 static int i915_forcewake_domains(struct seq_file
*m
, void *data
)
1545 struct drm_info_node
*node
= m
->private;
1546 struct drm_device
*dev
= node
->minor
->dev
;
1547 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1548 struct intel_uncore_forcewake_domain
*fw_domain
;
1550 spin_lock_irq(&dev_priv
->uncore
.lock
);
1551 for_each_fw_domain(fw_domain
, dev_priv
) {
1552 seq_printf(m
, "%s.wake_count = %u\n",
1553 intel_uncore_forcewake_domain_to_str(fw_domain
->id
),
1554 fw_domain
->wake_count
);
1556 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1561 static int vlv_drpc_info(struct seq_file
*m
)
1563 struct drm_info_node
*node
= m
->private;
1564 struct drm_device
*dev
= node
->minor
->dev
;
1565 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1566 u32 rpmodectl1
, rcctl1
, pw_status
;
1568 intel_runtime_pm_get(dev_priv
);
1570 pw_status
= I915_READ(VLV_GTLC_PW_STATUS
);
1571 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1572 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1574 intel_runtime_pm_put(dev_priv
);
1576 seq_printf(m
, "Video Turbo Mode: %s\n",
1577 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1578 seq_printf(m
, "Turbo enabled: %s\n",
1579 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1580 seq_printf(m
, "HW control enabled: %s\n",
1581 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1582 seq_printf(m
, "SW control enabled: %s\n",
1583 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1584 GEN6_RP_MEDIA_SW_MODE
));
1585 seq_printf(m
, "RC6 Enabled: %s\n",
1586 yesno(rcctl1
& (GEN7_RC_CTL_TO_MODE
|
1587 GEN6_RC_CTL_EI_MODE(1))));
1588 seq_printf(m
, "Render Power Well: %s\n",
1589 (pw_status
& VLV_GTLC_PW_RENDER_STATUS_MASK
) ? "Up" : "Down");
1590 seq_printf(m
, "Media Power Well: %s\n",
1591 (pw_status
& VLV_GTLC_PW_MEDIA_STATUS_MASK
) ? "Up" : "Down");
1593 seq_printf(m
, "Render RC6 residency since boot: %u\n",
1594 I915_READ(VLV_GT_RENDER_RC6
));
1595 seq_printf(m
, "Media RC6 residency since boot: %u\n",
1596 I915_READ(VLV_GT_MEDIA_RC6
));
1598 return i915_forcewake_domains(m
, NULL
);
1601 static int gen6_drpc_info(struct seq_file
*m
)
1603 struct drm_info_node
*node
= m
->private;
1604 struct drm_device
*dev
= node
->minor
->dev
;
1605 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1606 u32 rpmodectl1
, gt_core_status
, rcctl1
, rc6vids
= 0;
1607 unsigned forcewake_count
;
1610 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1613 intel_runtime_pm_get(dev_priv
);
1615 spin_lock_irq(&dev_priv
->uncore
.lock
);
1616 forcewake_count
= dev_priv
->uncore
.fw_domain
[FW_DOMAIN_ID_RENDER
].wake_count
;
1617 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1619 if (forcewake_count
) {
1620 seq_puts(m
, "RC information inaccurate because somebody "
1621 "holds a forcewake reference \n");
1623 /* NB: we cannot use forcewake, else we read the wrong values */
1624 while (count
++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK
) & 1))
1626 seq_printf(m
, "RC information accurate: %s\n", yesno(count
< 51));
1629 gt_core_status
= I915_READ_FW(GEN6_GT_CORE_STATUS
);
1630 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS
, gt_core_status
, 4, true);
1632 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1633 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1634 mutex_unlock(&dev
->struct_mutex
);
1635 mutex_lock(&dev_priv
->rps
.hw_lock
);
1636 sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
1637 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1639 intel_runtime_pm_put(dev_priv
);
1641 seq_printf(m
, "Video Turbo Mode: %s\n",
1642 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1643 seq_printf(m
, "HW control enabled: %s\n",
1644 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1645 seq_printf(m
, "SW control enabled: %s\n",
1646 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1647 GEN6_RP_MEDIA_SW_MODE
));
1648 seq_printf(m
, "RC1e Enabled: %s\n",
1649 yesno(rcctl1
& GEN6_RC_CTL_RC1e_ENABLE
));
1650 seq_printf(m
, "RC6 Enabled: %s\n",
1651 yesno(rcctl1
& GEN6_RC_CTL_RC6_ENABLE
));
1652 seq_printf(m
, "Deep RC6 Enabled: %s\n",
1653 yesno(rcctl1
& GEN6_RC_CTL_RC6p_ENABLE
));
1654 seq_printf(m
, "Deepest RC6 Enabled: %s\n",
1655 yesno(rcctl1
& GEN6_RC_CTL_RC6pp_ENABLE
));
1656 seq_puts(m
, "Current RC state: ");
1657 switch (gt_core_status
& GEN6_RCn_MASK
) {
1659 if (gt_core_status
& GEN6_CORE_CPD_STATE_MASK
)
1660 seq_puts(m
, "Core Power Down\n");
1662 seq_puts(m
, "on\n");
1665 seq_puts(m
, "RC3\n");
1668 seq_puts(m
, "RC6\n");
1671 seq_puts(m
, "RC7\n");
1674 seq_puts(m
, "Unknown\n");
1678 seq_printf(m
, "Core Power Down: %s\n",
1679 yesno(gt_core_status
& GEN6_CORE_CPD_STATE_MASK
));
1681 /* Not exactly sure what this is */
1682 seq_printf(m
, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1683 I915_READ(GEN6_GT_GFX_RC6_LOCKED
));
1684 seq_printf(m
, "RC6 residency since boot: %u\n",
1685 I915_READ(GEN6_GT_GFX_RC6
));
1686 seq_printf(m
, "RC6+ residency since boot: %u\n",
1687 I915_READ(GEN6_GT_GFX_RC6p
));
1688 seq_printf(m
, "RC6++ residency since boot: %u\n",
1689 I915_READ(GEN6_GT_GFX_RC6pp
));
1691 seq_printf(m
, "RC6 voltage: %dmV\n",
1692 GEN6_DECODE_RC6_VID(((rc6vids
>> 0) & 0xff)));
1693 seq_printf(m
, "RC6+ voltage: %dmV\n",
1694 GEN6_DECODE_RC6_VID(((rc6vids
>> 8) & 0xff)));
1695 seq_printf(m
, "RC6++ voltage: %dmV\n",
1696 GEN6_DECODE_RC6_VID(((rc6vids
>> 16) & 0xff)));
1700 static int i915_drpc_info(struct seq_file
*m
, void *unused
)
1702 struct drm_info_node
*node
= m
->private;
1703 struct drm_device
*dev
= node
->minor
->dev
;
1705 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
1706 return vlv_drpc_info(m
);
1707 else if (INTEL_INFO(dev
)->gen
>= 6)
1708 return gen6_drpc_info(m
);
1710 return ironlake_drpc_info(m
);
1713 static int i915_frontbuffer_tracking(struct seq_file
*m
, void *unused
)
1715 struct drm_info_node
*node
= m
->private;
1716 struct drm_device
*dev
= node
->minor
->dev
;
1717 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1719 seq_printf(m
, "FB tracking busy bits: 0x%08x\n",
1720 dev_priv
->fb_tracking
.busy_bits
);
1722 seq_printf(m
, "FB tracking flip bits: 0x%08x\n",
1723 dev_priv
->fb_tracking
.flip_bits
);
1728 static int i915_fbc_status(struct seq_file
*m
, void *unused
)
1730 struct drm_info_node
*node
= m
->private;
1731 struct drm_device
*dev
= node
->minor
->dev
;
1732 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1734 if (!HAS_FBC(dev
)) {
1735 seq_puts(m
, "FBC unsupported on this chipset\n");
1739 intel_runtime_pm_get(dev_priv
);
1740 mutex_lock(&dev_priv
->fbc
.lock
);
1742 if (intel_fbc_is_active(dev_priv
))
1743 seq_puts(m
, "FBC enabled\n");
1745 seq_printf(m
, "FBC disabled: %s\n",
1746 dev_priv
->fbc
.no_fbc_reason
);
1748 if (INTEL_INFO(dev_priv
)->gen
>= 7)
1749 seq_printf(m
, "Compressing: %s\n",
1750 yesno(I915_READ(FBC_STATUS2
) &
1751 FBC_COMPRESSION_MASK
));
1753 mutex_unlock(&dev_priv
->fbc
.lock
);
1754 intel_runtime_pm_put(dev_priv
);
1759 static int i915_fbc_fc_get(void *data
, u64
*val
)
1761 struct drm_device
*dev
= data
;
1762 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1764 if (INTEL_INFO(dev
)->gen
< 7 || !HAS_FBC(dev
))
1767 *val
= dev_priv
->fbc
.false_color
;
1772 static int i915_fbc_fc_set(void *data
, u64 val
)
1774 struct drm_device
*dev
= data
;
1775 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1778 if (INTEL_INFO(dev
)->gen
< 7 || !HAS_FBC(dev
))
1781 mutex_lock(&dev_priv
->fbc
.lock
);
1783 reg
= I915_READ(ILK_DPFC_CONTROL
);
1784 dev_priv
->fbc
.false_color
= val
;
1786 I915_WRITE(ILK_DPFC_CONTROL
, val
?
1787 (reg
| FBC_CTL_FALSE_COLOR
) :
1788 (reg
& ~FBC_CTL_FALSE_COLOR
));
1790 mutex_unlock(&dev_priv
->fbc
.lock
);
1794 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops
,
1795 i915_fbc_fc_get
, i915_fbc_fc_set
,
1798 static int i915_ips_status(struct seq_file
*m
, void *unused
)
1800 struct drm_info_node
*node
= m
->private;
1801 struct drm_device
*dev
= node
->minor
->dev
;
1802 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1804 if (!HAS_IPS(dev
)) {
1805 seq_puts(m
, "not supported\n");
1809 intel_runtime_pm_get(dev_priv
);
1811 seq_printf(m
, "Enabled by kernel parameter: %s\n",
1812 yesno(i915
.enable_ips
));
1814 if (INTEL_INFO(dev
)->gen
>= 8) {
1815 seq_puts(m
, "Currently: unknown\n");
1817 if (I915_READ(IPS_CTL
) & IPS_ENABLE
)
1818 seq_puts(m
, "Currently: enabled\n");
1820 seq_puts(m
, "Currently: disabled\n");
1823 intel_runtime_pm_put(dev_priv
);
1828 static int i915_sr_status(struct seq_file
*m
, void *unused
)
1830 struct drm_info_node
*node
= m
->private;
1831 struct drm_device
*dev
= node
->minor
->dev
;
1832 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1833 bool sr_enabled
= false;
1835 intel_runtime_pm_get(dev_priv
);
1837 if (HAS_PCH_SPLIT(dev
))
1838 sr_enabled
= I915_READ(WM1_LP_ILK
) & WM1_LP_SR_EN
;
1839 else if (IS_CRESTLINE(dev
) || IS_G4X(dev
) ||
1840 IS_I945G(dev
) || IS_I945GM(dev
))
1841 sr_enabled
= I915_READ(FW_BLC_SELF
) & FW_BLC_SELF_EN
;
1842 else if (IS_I915GM(dev
))
1843 sr_enabled
= I915_READ(INSTPM
) & INSTPM_SELF_EN
;
1844 else if (IS_PINEVIEW(dev
))
1845 sr_enabled
= I915_READ(DSPFW3
) & PINEVIEW_SELF_REFRESH_EN
;
1846 else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
1847 sr_enabled
= I915_READ(FW_BLC_SELF_VLV
) & FW_CSPWRDWNEN
;
1849 intel_runtime_pm_put(dev_priv
);
1851 seq_printf(m
, "self-refresh: %s\n",
1852 sr_enabled
? "enabled" : "disabled");
1857 static int i915_emon_status(struct seq_file
*m
, void *unused
)
1859 struct drm_info_node
*node
= m
->private;
1860 struct drm_device
*dev
= node
->minor
->dev
;
1861 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1862 unsigned long temp
, chipset
, gfx
;
1868 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1872 temp
= i915_mch_val(dev_priv
);
1873 chipset
= i915_chipset_val(dev_priv
);
1874 gfx
= i915_gfx_val(dev_priv
);
1875 mutex_unlock(&dev
->struct_mutex
);
1877 seq_printf(m
, "GMCH temp: %ld\n", temp
);
1878 seq_printf(m
, "Chipset power: %ld\n", chipset
);
1879 seq_printf(m
, "GFX power: %ld\n", gfx
);
1880 seq_printf(m
, "Total power: %ld\n", chipset
+ gfx
);
1885 static int i915_ring_freq_table(struct seq_file
*m
, void *unused
)
1887 struct drm_info_node
*node
= m
->private;
1888 struct drm_device
*dev
= node
->minor
->dev
;
1889 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1891 int gpu_freq
, ia_freq
;
1892 unsigned int max_gpu_freq
, min_gpu_freq
;
1894 if (!HAS_CORE_RING_FREQ(dev
)) {
1895 seq_puts(m
, "unsupported on this chipset\n");
1899 intel_runtime_pm_get(dev_priv
);
1901 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
1903 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
1907 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
1908 /* Convert GT frequency to 50 HZ units */
1910 dev_priv
->rps
.min_freq_softlimit
/ GEN9_FREQ_SCALER
;
1912 dev_priv
->rps
.max_freq_softlimit
/ GEN9_FREQ_SCALER
;
1914 min_gpu_freq
= dev_priv
->rps
.min_freq_softlimit
;
1915 max_gpu_freq
= dev_priv
->rps
.max_freq_softlimit
;
1918 seq_puts(m
, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1920 for (gpu_freq
= min_gpu_freq
; gpu_freq
<= max_gpu_freq
; gpu_freq
++) {
1922 sandybridge_pcode_read(dev_priv
,
1923 GEN6_PCODE_READ_MIN_FREQ_TABLE
,
1925 seq_printf(m
, "%d\t\t%d\t\t\t\t%d\n",
1926 intel_gpu_freq(dev_priv
, (gpu_freq
*
1927 (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
) ?
1928 GEN9_FREQ_SCALER
: 1))),
1929 ((ia_freq
>> 0) & 0xff) * 100,
1930 ((ia_freq
>> 8) & 0xff) * 100);
1933 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1936 intel_runtime_pm_put(dev_priv
);
1940 static int i915_opregion(struct seq_file
*m
, void *unused
)
1942 struct drm_info_node
*node
= m
->private;
1943 struct drm_device
*dev
= node
->minor
->dev
;
1944 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1945 struct intel_opregion
*opregion
= &dev_priv
->opregion
;
1948 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1952 if (opregion
->header
)
1953 seq_write(m
, opregion
->header
, OPREGION_SIZE
);
1955 mutex_unlock(&dev
->struct_mutex
);
1961 static int i915_vbt(struct seq_file
*m
, void *unused
)
1963 struct drm_info_node
*node
= m
->private;
1964 struct drm_device
*dev
= node
->minor
->dev
;
1965 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1966 struct intel_opregion
*opregion
= &dev_priv
->opregion
;
1969 seq_write(m
, opregion
->vbt
, opregion
->vbt_size
);
1974 static int i915_gem_framebuffer_info(struct seq_file
*m
, void *data
)
1976 struct drm_info_node
*node
= m
->private;
1977 struct drm_device
*dev
= node
->minor
->dev
;
1978 struct intel_framebuffer
*fbdev_fb
= NULL
;
1979 struct drm_framebuffer
*drm_fb
;
1982 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1986 #ifdef CONFIG_DRM_FBDEV_EMULATION
1987 if (to_i915(dev
)->fbdev
) {
1988 fbdev_fb
= to_intel_framebuffer(to_i915(dev
)->fbdev
->helper
.fb
);
1990 seq_printf(m
, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1991 fbdev_fb
->base
.width
,
1992 fbdev_fb
->base
.height
,
1993 fbdev_fb
->base
.depth
,
1994 fbdev_fb
->base
.bits_per_pixel
,
1995 fbdev_fb
->base
.modifier
[0],
1996 drm_framebuffer_read_refcount(&fbdev_fb
->base
));
1997 describe_obj(m
, fbdev_fb
->obj
);
2002 mutex_lock(&dev
->mode_config
.fb_lock
);
2003 drm_for_each_fb(drm_fb
, dev
) {
2004 struct intel_framebuffer
*fb
= to_intel_framebuffer(drm_fb
);
2008 seq_printf(m
, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
2012 fb
->base
.bits_per_pixel
,
2013 fb
->base
.modifier
[0],
2014 drm_framebuffer_read_refcount(&fb
->base
));
2015 describe_obj(m
, fb
->obj
);
2018 mutex_unlock(&dev
->mode_config
.fb_lock
);
2019 mutex_unlock(&dev
->struct_mutex
);
2024 static void describe_ctx_ringbuf(struct seq_file
*m
,
2025 struct intel_ringbuffer
*ringbuf
)
2027 seq_printf(m
, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
2028 ringbuf
->space
, ringbuf
->head
, ringbuf
->tail
,
2029 ringbuf
->last_retired_head
);
2032 static int i915_context_status(struct seq_file
*m
, void *unused
)
2034 struct drm_info_node
*node
= m
->private;
2035 struct drm_device
*dev
= node
->minor
->dev
;
2036 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2037 struct intel_engine_cs
*engine
;
2038 struct i915_gem_context
*ctx
;
2041 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2045 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
2046 seq_printf(m
, "HW context %u ", ctx
->hw_id
);
2047 if (IS_ERR(ctx
->file_priv
)) {
2048 seq_puts(m
, "(deleted) ");
2049 } else if (ctx
->file_priv
) {
2050 struct pid
*pid
= ctx
->file_priv
->file
->pid
;
2051 struct task_struct
*task
;
2053 task
= get_pid_task(pid
, PIDTYPE_PID
);
2055 seq_printf(m
, "(%s [%d]) ",
2056 task
->comm
, task
->pid
);
2057 put_task_struct(task
);
2060 seq_puts(m
, "(kernel) ");
2063 seq_putc(m
, ctx
->remap_slice
? 'R' : 'r');
2066 for_each_engine(engine
, dev_priv
) {
2067 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
2069 seq_printf(m
, "%s: ", engine
->name
);
2070 seq_putc(m
, ce
->initialised
? 'I' : 'i');
2072 describe_obj(m
, ce
->state
);
2074 describe_ctx_ringbuf(m
, ce
->ringbuf
);
2081 mutex_unlock(&dev
->struct_mutex
);
2086 static void i915_dump_lrc_obj(struct seq_file
*m
,
2087 struct i915_gem_context
*ctx
,
2088 struct intel_engine_cs
*engine
)
2090 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[engine
->id
].state
;
2092 uint32_t *reg_state
;
2094 unsigned long ggtt_offset
= 0;
2096 seq_printf(m
, "CONTEXT: %s %u\n", engine
->name
, ctx
->hw_id
);
2098 if (ctx_obj
== NULL
) {
2099 seq_puts(m
, "\tNot allocated\n");
2103 if (!i915_gem_obj_ggtt_bound(ctx_obj
))
2104 seq_puts(m
, "\tNot bound in GGTT\n");
2106 ggtt_offset
= i915_gem_obj_ggtt_offset(ctx_obj
);
2108 if (i915_gem_object_get_pages(ctx_obj
)) {
2109 seq_puts(m
, "\tFailed to get pages for context object\n");
2113 page
= i915_gem_object_get_page(ctx_obj
, LRC_STATE_PN
);
2114 if (!WARN_ON(page
== NULL
)) {
2115 reg_state
= kmap_atomic(page
);
2117 for (j
= 0; j
< 0x600 / sizeof(u32
) / 4; j
+= 4) {
2118 seq_printf(m
, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2119 ggtt_offset
+ 4096 + (j
* 4),
2120 reg_state
[j
], reg_state
[j
+ 1],
2121 reg_state
[j
+ 2], reg_state
[j
+ 3]);
2123 kunmap_atomic(reg_state
);
2129 static int i915_dump_lrc(struct seq_file
*m
, void *unused
)
2131 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2132 struct drm_device
*dev
= node
->minor
->dev
;
2133 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2134 struct intel_engine_cs
*engine
;
2135 struct i915_gem_context
*ctx
;
2138 if (!i915
.enable_execlists
) {
2139 seq_printf(m
, "Logical Ring Contexts are disabled\n");
2143 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2147 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
)
2148 for_each_engine(engine
, dev_priv
)
2149 i915_dump_lrc_obj(m
, ctx
, engine
);
2151 mutex_unlock(&dev
->struct_mutex
);
2156 static int i915_execlists(struct seq_file
*m
, void *data
)
2158 struct drm_info_node
*node
= (struct drm_info_node
*)m
->private;
2159 struct drm_device
*dev
= node
->minor
->dev
;
2160 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2161 struct intel_engine_cs
*engine
;
2167 struct list_head
*cursor
;
2170 if (!i915
.enable_execlists
) {
2171 seq_puts(m
, "Logical Ring Contexts are disabled\n");
2175 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2179 intel_runtime_pm_get(dev_priv
);
2181 for_each_engine(engine
, dev_priv
) {
2182 struct drm_i915_gem_request
*head_req
= NULL
;
2185 seq_printf(m
, "%s\n", engine
->name
);
2187 status
= I915_READ(RING_EXECLIST_STATUS_LO(engine
));
2188 ctx_id
= I915_READ(RING_EXECLIST_STATUS_HI(engine
));
2189 seq_printf(m
, "\tExeclist status: 0x%08X, context: %u\n",
2192 status_pointer
= I915_READ(RING_CONTEXT_STATUS_PTR(engine
));
2193 seq_printf(m
, "\tStatus pointer: 0x%08X\n", status_pointer
);
2195 read_pointer
= engine
->next_context_status_buffer
;
2196 write_pointer
= GEN8_CSB_WRITE_PTR(status_pointer
);
2197 if (read_pointer
> write_pointer
)
2198 write_pointer
+= GEN8_CSB_ENTRIES
;
2199 seq_printf(m
, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2200 read_pointer
, write_pointer
);
2202 for (i
= 0; i
< GEN8_CSB_ENTRIES
; i
++) {
2203 status
= I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine
, i
));
2204 ctx_id
= I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine
, i
));
2206 seq_printf(m
, "\tStatus buffer %d: 0x%08X, context: %u\n",
2210 spin_lock_bh(&engine
->execlist_lock
);
2211 list_for_each(cursor
, &engine
->execlist_queue
)
2213 head_req
= list_first_entry_or_null(&engine
->execlist_queue
,
2214 struct drm_i915_gem_request
,
2216 spin_unlock_bh(&engine
->execlist_lock
);
2218 seq_printf(m
, "\t%d requests in queue\n", count
);
2220 seq_printf(m
, "\tHead request context: %u\n",
2221 head_req
->ctx
->hw_id
);
2222 seq_printf(m
, "\tHead request tail: %u\n",
2229 intel_runtime_pm_put(dev_priv
);
2230 mutex_unlock(&dev
->struct_mutex
);
2235 static const char *swizzle_string(unsigned swizzle
)
2238 case I915_BIT_6_SWIZZLE_NONE
:
2240 case I915_BIT_6_SWIZZLE_9
:
2242 case I915_BIT_6_SWIZZLE_9_10
:
2243 return "bit9/bit10";
2244 case I915_BIT_6_SWIZZLE_9_11
:
2245 return "bit9/bit11";
2246 case I915_BIT_6_SWIZZLE_9_10_11
:
2247 return "bit9/bit10/bit11";
2248 case I915_BIT_6_SWIZZLE_9_17
:
2249 return "bit9/bit17";
2250 case I915_BIT_6_SWIZZLE_9_10_17
:
2251 return "bit9/bit10/bit17";
2252 case I915_BIT_6_SWIZZLE_UNKNOWN
:
2259 static int i915_swizzle_info(struct seq_file
*m
, void *data
)
2261 struct drm_info_node
*node
= m
->private;
2262 struct drm_device
*dev
= node
->minor
->dev
;
2263 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2266 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2269 intel_runtime_pm_get(dev_priv
);
2271 seq_printf(m
, "bit6 swizzle for X-tiling = %s\n",
2272 swizzle_string(dev_priv
->mm
.bit_6_swizzle_x
));
2273 seq_printf(m
, "bit6 swizzle for Y-tiling = %s\n",
2274 swizzle_string(dev_priv
->mm
.bit_6_swizzle_y
));
2276 if (IS_GEN3(dev
) || IS_GEN4(dev
)) {
2277 seq_printf(m
, "DDC = 0x%08x\n",
2279 seq_printf(m
, "DDC2 = 0x%08x\n",
2281 seq_printf(m
, "C0DRB3 = 0x%04x\n",
2282 I915_READ16(C0DRB3
));
2283 seq_printf(m
, "C1DRB3 = 0x%04x\n",
2284 I915_READ16(C1DRB3
));
2285 } else if (INTEL_INFO(dev
)->gen
>= 6) {
2286 seq_printf(m
, "MAD_DIMM_C0 = 0x%08x\n",
2287 I915_READ(MAD_DIMM_C0
));
2288 seq_printf(m
, "MAD_DIMM_C1 = 0x%08x\n",
2289 I915_READ(MAD_DIMM_C1
));
2290 seq_printf(m
, "MAD_DIMM_C2 = 0x%08x\n",
2291 I915_READ(MAD_DIMM_C2
));
2292 seq_printf(m
, "TILECTL = 0x%08x\n",
2293 I915_READ(TILECTL
));
2294 if (INTEL_INFO(dev
)->gen
>= 8)
2295 seq_printf(m
, "GAMTARBMODE = 0x%08x\n",
2296 I915_READ(GAMTARBMODE
));
2298 seq_printf(m
, "ARB_MODE = 0x%08x\n",
2299 I915_READ(ARB_MODE
));
2300 seq_printf(m
, "DISP_ARB_CTL = 0x%08x\n",
2301 I915_READ(DISP_ARB_CTL
));
2304 if (dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
)
2305 seq_puts(m
, "L-shaped memory detected\n");
2307 intel_runtime_pm_put(dev_priv
);
2308 mutex_unlock(&dev
->struct_mutex
);
2313 static int per_file_ctx(int id
, void *ptr
, void *data
)
2315 struct i915_gem_context
*ctx
= ptr
;
2316 struct seq_file
*m
= data
;
2317 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
2320 seq_printf(m
, " no ppgtt for context %d\n",
2325 if (i915_gem_context_is_default(ctx
))
2326 seq_puts(m
, " default context:\n");
2328 seq_printf(m
, " context %d:\n", ctx
->user_handle
);
2329 ppgtt
->debug_dump(ppgtt
, m
);
2334 static void gen8_ppgtt_info(struct seq_file
*m
, struct drm_device
*dev
)
2336 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2337 struct intel_engine_cs
*engine
;
2338 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2344 for_each_engine(engine
, dev_priv
) {
2345 seq_printf(m
, "%s\n", engine
->name
);
2346 for (i
= 0; i
< 4; i
++) {
2347 u64 pdp
= I915_READ(GEN8_RING_PDP_UDW(engine
, i
));
2349 pdp
|= I915_READ(GEN8_RING_PDP_LDW(engine
, i
));
2350 seq_printf(m
, "\tPDP%d 0x%016llx\n", i
, pdp
);
2355 static void gen6_ppgtt_info(struct seq_file
*m
, struct drm_device
*dev
)
2357 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2358 struct intel_engine_cs
*engine
;
2360 if (IS_GEN6(dev_priv
))
2361 seq_printf(m
, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE
));
2363 for_each_engine(engine
, dev_priv
) {
2364 seq_printf(m
, "%s\n", engine
->name
);
2365 if (IS_GEN7(dev_priv
))
2366 seq_printf(m
, "GFX_MODE: 0x%08x\n",
2367 I915_READ(RING_MODE_GEN7(engine
)));
2368 seq_printf(m
, "PP_DIR_BASE: 0x%08x\n",
2369 I915_READ(RING_PP_DIR_BASE(engine
)));
2370 seq_printf(m
, "PP_DIR_BASE_READ: 0x%08x\n",
2371 I915_READ(RING_PP_DIR_BASE_READ(engine
)));
2372 seq_printf(m
, "PP_DIR_DCLV: 0x%08x\n",
2373 I915_READ(RING_PP_DIR_DCLV(engine
)));
2375 if (dev_priv
->mm
.aliasing_ppgtt
) {
2376 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2378 seq_puts(m
, "aliasing PPGTT:\n");
2379 seq_printf(m
, "pd gtt offset: 0x%08x\n", ppgtt
->pd
.base
.ggtt_offset
);
2381 ppgtt
->debug_dump(ppgtt
, m
);
2384 seq_printf(m
, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK
));
2387 static int i915_ppgtt_info(struct seq_file
*m
, void *data
)
2389 struct drm_info_node
*node
= m
->private;
2390 struct drm_device
*dev
= node
->minor
->dev
;
2391 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2392 struct drm_file
*file
;
2394 int ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2397 intel_runtime_pm_get(dev_priv
);
2399 if (INTEL_INFO(dev
)->gen
>= 8)
2400 gen8_ppgtt_info(m
, dev
);
2401 else if (INTEL_INFO(dev
)->gen
>= 6)
2402 gen6_ppgtt_info(m
, dev
);
2404 mutex_lock(&dev
->filelist_mutex
);
2405 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
2406 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2407 struct task_struct
*task
;
2409 task
= get_pid_task(file
->pid
, PIDTYPE_PID
);
2414 seq_printf(m
, "\nproc: %s\n", task
->comm
);
2415 put_task_struct(task
);
2416 idr_for_each(&file_priv
->context_idr
, per_file_ctx
,
2417 (void *)(unsigned long)m
);
2420 mutex_unlock(&dev
->filelist_mutex
);
2422 intel_runtime_pm_put(dev_priv
);
2423 mutex_unlock(&dev
->struct_mutex
);
2428 static int count_irq_waiters(struct drm_i915_private
*i915
)
2430 struct intel_engine_cs
*engine
;
2433 for_each_engine(engine
, i915
)
2434 count
+= intel_engine_has_waiter(engine
);
2439 static int i915_rps_boost_info(struct seq_file
*m
, void *data
)
2441 struct drm_info_node
*node
= m
->private;
2442 struct drm_device
*dev
= node
->minor
->dev
;
2443 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2444 struct drm_file
*file
;
2446 seq_printf(m
, "RPS enabled? %d\n", dev_priv
->rps
.enabled
);
2447 seq_printf(m
, "GPU busy? %s [%x]\n",
2448 yesno(dev_priv
->gt
.awake
), dev_priv
->gt
.active_engines
);
2449 seq_printf(m
, "CPU waiting? %d\n", count_irq_waiters(dev_priv
));
2450 seq_printf(m
, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2451 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
),
2452 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
2453 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq_softlimit
),
2454 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq_softlimit
),
2455 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
2457 mutex_lock(&dev
->filelist_mutex
);
2458 spin_lock(&dev_priv
->rps
.client_lock
);
2459 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
2460 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2461 struct task_struct
*task
;
2464 task
= pid_task(file
->pid
, PIDTYPE_PID
);
2465 seq_printf(m
, "%s [%d]: %d boosts%s\n",
2466 task
? task
->comm
: "<unknown>",
2467 task
? task
->pid
: -1,
2468 file_priv
->rps
.boosts
,
2469 list_empty(&file_priv
->rps
.link
) ? "" : ", active");
2472 seq_printf(m
, "Semaphore boosts: %d%s\n",
2473 dev_priv
->rps
.semaphores
.boosts
,
2474 list_empty(&dev_priv
->rps
.semaphores
.link
) ? "" : ", active");
2475 seq_printf(m
, "MMIO flip boosts: %d%s\n",
2476 dev_priv
->rps
.mmioflips
.boosts
,
2477 list_empty(&dev_priv
->rps
.mmioflips
.link
) ? "" : ", active");
2478 seq_printf(m
, "Kernel boosts: %d\n", dev_priv
->rps
.boosts
);
2479 spin_unlock(&dev_priv
->rps
.client_lock
);
2480 mutex_unlock(&dev
->filelist_mutex
);
2485 static int i915_llc(struct seq_file
*m
, void *data
)
2487 struct drm_info_node
*node
= m
->private;
2488 struct drm_device
*dev
= node
->minor
->dev
;
2489 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2490 const bool edram
= INTEL_GEN(dev_priv
) > 8;
2492 seq_printf(m
, "LLC: %s\n", yesno(HAS_LLC(dev
)));
2493 seq_printf(m
, "%s: %lluMB\n", edram
? "eDRAM" : "eLLC",
2494 intel_uncore_edram_size(dev_priv
)/1024/1024);
2499 static int i915_guc_load_status_info(struct seq_file
*m
, void *data
)
2501 struct drm_info_node
*node
= m
->private;
2502 struct drm_i915_private
*dev_priv
= to_i915(node
->minor
->dev
);
2503 struct intel_guc_fw
*guc_fw
= &dev_priv
->guc
.guc_fw
;
2506 if (!HAS_GUC_UCODE(dev_priv
))
2509 seq_printf(m
, "GuC firmware status:\n");
2510 seq_printf(m
, "\tpath: %s\n",
2511 guc_fw
->guc_fw_path
);
2512 seq_printf(m
, "\tfetch: %s\n",
2513 intel_guc_fw_status_repr(guc_fw
->guc_fw_fetch_status
));
2514 seq_printf(m
, "\tload: %s\n",
2515 intel_guc_fw_status_repr(guc_fw
->guc_fw_load_status
));
2516 seq_printf(m
, "\tversion wanted: %d.%d\n",
2517 guc_fw
->guc_fw_major_wanted
, guc_fw
->guc_fw_minor_wanted
);
2518 seq_printf(m
, "\tversion found: %d.%d\n",
2519 guc_fw
->guc_fw_major_found
, guc_fw
->guc_fw_minor_found
);
2520 seq_printf(m
, "\theader: offset is %d; size = %d\n",
2521 guc_fw
->header_offset
, guc_fw
->header_size
);
2522 seq_printf(m
, "\tuCode: offset is %d; size = %d\n",
2523 guc_fw
->ucode_offset
, guc_fw
->ucode_size
);
2524 seq_printf(m
, "\tRSA: offset is %d; size = %d\n",
2525 guc_fw
->rsa_offset
, guc_fw
->rsa_size
);
2527 tmp
= I915_READ(GUC_STATUS
);
2529 seq_printf(m
, "\nGuC status 0x%08x:\n", tmp
);
2530 seq_printf(m
, "\tBootrom status = 0x%x\n",
2531 (tmp
& GS_BOOTROM_MASK
) >> GS_BOOTROM_SHIFT
);
2532 seq_printf(m
, "\tuKernel status = 0x%x\n",
2533 (tmp
& GS_UKERNEL_MASK
) >> GS_UKERNEL_SHIFT
);
2534 seq_printf(m
, "\tMIA Core status = 0x%x\n",
2535 (tmp
& GS_MIA_MASK
) >> GS_MIA_SHIFT
);
2536 seq_puts(m
, "\nScratch registers:\n");
2537 for (i
= 0; i
< 16; i
++)
2538 seq_printf(m
, "\t%2d: \t0x%x\n", i
, I915_READ(SOFT_SCRATCH(i
)));
2543 static void i915_guc_client_info(struct seq_file
*m
,
2544 struct drm_i915_private
*dev_priv
,
2545 struct i915_guc_client
*client
)
2547 struct intel_engine_cs
*engine
;
2550 seq_printf(m
, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2551 client
->priority
, client
->ctx_index
, client
->proc_desc_offset
);
2552 seq_printf(m
, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2553 client
->doorbell_id
, client
->doorbell_offset
, client
->cookie
);
2554 seq_printf(m
, "\tWQ size %d, offset: 0x%x, tail %d\n",
2555 client
->wq_size
, client
->wq_offset
, client
->wq_tail
);
2557 seq_printf(m
, "\tWork queue full: %u\n", client
->no_wq_space
);
2558 seq_printf(m
, "\tFailed to queue: %u\n", client
->q_fail
);
2559 seq_printf(m
, "\tFailed doorbell: %u\n", client
->b_fail
);
2560 seq_printf(m
, "\tLast submission result: %d\n", client
->retcode
);
2562 for_each_engine(engine
, dev_priv
) {
2563 seq_printf(m
, "\tSubmissions: %llu %s\n",
2564 client
->submissions
[engine
->id
],
2566 tot
+= client
->submissions
[engine
->id
];
2568 seq_printf(m
, "\tTotal: %llu\n", tot
);
2571 static int i915_guc_info(struct seq_file
*m
, void *data
)
2573 struct drm_info_node
*node
= m
->private;
2574 struct drm_device
*dev
= node
->minor
->dev
;
2575 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2576 struct intel_guc guc
;
2577 struct i915_guc_client client
= {};
2578 struct intel_engine_cs
*engine
;
2581 if (!HAS_GUC_SCHED(dev_priv
))
2584 if (mutex_lock_interruptible(&dev
->struct_mutex
))
2587 /* Take a local copy of the GuC data, so we can dump it at leisure */
2588 guc
= dev_priv
->guc
;
2589 if (guc
.execbuf_client
)
2590 client
= *guc
.execbuf_client
;
2592 mutex_unlock(&dev
->struct_mutex
);
2594 seq_printf(m
, "Doorbell map:\n");
2595 seq_printf(m
, "\t%*pb\n", GUC_MAX_DOORBELLS
, guc
.doorbell_bitmap
);
2596 seq_printf(m
, "Doorbell next cacheline: 0x%x\n\n", guc
.db_cacheline
);
2598 seq_printf(m
, "GuC total action count: %llu\n", guc
.action_count
);
2599 seq_printf(m
, "GuC action failure count: %u\n", guc
.action_fail
);
2600 seq_printf(m
, "GuC last action command: 0x%x\n", guc
.action_cmd
);
2601 seq_printf(m
, "GuC last action status: 0x%x\n", guc
.action_status
);
2602 seq_printf(m
, "GuC last action error code: %d\n", guc
.action_err
);
2604 seq_printf(m
, "\nGuC submissions:\n");
2605 for_each_engine(engine
, dev_priv
) {
2606 seq_printf(m
, "\t%-24s: %10llu, last seqno 0x%08x\n",
2607 engine
->name
, guc
.submissions
[engine
->id
],
2608 guc
.last_seqno
[engine
->id
]);
2609 total
+= guc
.submissions
[engine
->id
];
2611 seq_printf(m
, "\t%s: %llu\n", "Total", total
);
2613 seq_printf(m
, "\nGuC execbuf client @ %p:\n", guc
.execbuf_client
);
2614 i915_guc_client_info(m
, dev_priv
, &client
);
2616 /* Add more as required ... */
2621 static int i915_guc_log_dump(struct seq_file
*m
, void *data
)
2623 struct drm_info_node
*node
= m
->private;
2624 struct drm_device
*dev
= node
->minor
->dev
;
2625 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2626 struct drm_i915_gem_object
*log_obj
= dev_priv
->guc
.log_obj
;
2633 for (pg
= 0; pg
< log_obj
->base
.size
/ PAGE_SIZE
; pg
++) {
2634 log
= kmap_atomic(i915_gem_object_get_page(log_obj
, pg
));
2636 for (i
= 0; i
< PAGE_SIZE
/ sizeof(u32
); i
+= 4)
2637 seq_printf(m
, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2638 *(log
+ i
), *(log
+ i
+ 1),
2639 *(log
+ i
+ 2), *(log
+ i
+ 3));
2649 static int i915_edp_psr_status(struct seq_file
*m
, void *data
)
2651 struct drm_info_node
*node
= m
->private;
2652 struct drm_device
*dev
= node
->minor
->dev
;
2653 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2657 bool enabled
= false;
2659 if (!HAS_PSR(dev
)) {
2660 seq_puts(m
, "PSR not supported\n");
2664 intel_runtime_pm_get(dev_priv
);
2666 mutex_lock(&dev_priv
->psr
.lock
);
2667 seq_printf(m
, "Sink_Support: %s\n", yesno(dev_priv
->psr
.sink_support
));
2668 seq_printf(m
, "Source_OK: %s\n", yesno(dev_priv
->psr
.source_ok
));
2669 seq_printf(m
, "Enabled: %s\n", yesno((bool)dev_priv
->psr
.enabled
));
2670 seq_printf(m
, "Active: %s\n", yesno(dev_priv
->psr
.active
));
2671 seq_printf(m
, "Busy frontbuffer bits: 0x%03x\n",
2672 dev_priv
->psr
.busy_frontbuffer_bits
);
2673 seq_printf(m
, "Re-enable work scheduled: %s\n",
2674 yesno(work_busy(&dev_priv
->psr
.work
.work
)));
2677 enabled
= I915_READ(EDP_PSR_CTL
) & EDP_PSR_ENABLE
;
2679 for_each_pipe(dev_priv
, pipe
) {
2680 stat
[pipe
] = I915_READ(VLV_PSRSTAT(pipe
)) &
2681 VLV_EDP_PSR_CURR_STATE_MASK
;
2682 if ((stat
[pipe
] == VLV_EDP_PSR_ACTIVE_NORFB_UP
) ||
2683 (stat
[pipe
] == VLV_EDP_PSR_ACTIVE_SF_UPDATE
))
2688 seq_printf(m
, "Main link in standby mode: %s\n",
2689 yesno(dev_priv
->psr
.link_standby
));
2691 seq_printf(m
, "HW Enabled & Active bit: %s", yesno(enabled
));
2694 for_each_pipe(dev_priv
, pipe
) {
2695 if ((stat
[pipe
] == VLV_EDP_PSR_ACTIVE_NORFB_UP
) ||
2696 (stat
[pipe
] == VLV_EDP_PSR_ACTIVE_SF_UPDATE
))
2697 seq_printf(m
, " pipe %c", pipe_name(pipe
));
2702 * VLV/CHV PSR has no kind of performance counter
2703 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2705 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2706 psrperf
= I915_READ(EDP_PSR_PERF_CNT
) &
2707 EDP_PSR_PERF_CNT_MASK
;
2709 seq_printf(m
, "Performance_Counter: %u\n", psrperf
);
2711 mutex_unlock(&dev_priv
->psr
.lock
);
2713 intel_runtime_pm_put(dev_priv
);
2717 static int i915_sink_crc(struct seq_file
*m
, void *data
)
2719 struct drm_info_node
*node
= m
->private;
2720 struct drm_device
*dev
= node
->minor
->dev
;
2721 struct intel_connector
*connector
;
2722 struct intel_dp
*intel_dp
= NULL
;
2726 drm_modeset_lock_all(dev
);
2727 for_each_intel_connector(dev
, connector
) {
2728 struct drm_crtc
*crtc
;
2730 if (!connector
->base
.state
->best_encoder
)
2733 crtc
= connector
->base
.state
->crtc
;
2734 if (!crtc
->state
->active
)
2737 if (connector
->base
.connector_type
!= DRM_MODE_CONNECTOR_eDP
)
2740 intel_dp
= enc_to_intel_dp(connector
->base
.state
->best_encoder
);
2742 ret
= intel_dp_sink_crc(intel_dp
, crc
);
2746 seq_printf(m
, "%02x%02x%02x%02x%02x%02x\n",
2747 crc
[0], crc
[1], crc
[2],
2748 crc
[3], crc
[4], crc
[5]);
2753 drm_modeset_unlock_all(dev
);
2757 static int i915_energy_uJ(struct seq_file
*m
, void *data
)
2759 struct drm_info_node
*node
= m
->private;
2760 struct drm_device
*dev
= node
->minor
->dev
;
2761 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2765 if (INTEL_INFO(dev
)->gen
< 6)
2768 intel_runtime_pm_get(dev_priv
);
2770 rdmsrl(MSR_RAPL_POWER_UNIT
, power
);
2771 power
= (power
& 0x1f00) >> 8;
2772 units
= 1000000 / (1 << power
); /* convert to uJ */
2773 power
= I915_READ(MCH_SECP_NRG_STTS
);
2776 intel_runtime_pm_put(dev_priv
);
2778 seq_printf(m
, "%llu", (long long unsigned)power
);
2783 static int i915_runtime_pm_status(struct seq_file
*m
, void *unused
)
2785 struct drm_info_node
*node
= m
->private;
2786 struct drm_device
*dev
= node
->minor
->dev
;
2787 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2789 if (!HAS_RUNTIME_PM(dev_priv
))
2790 seq_puts(m
, "Runtime power management not supported\n");
2792 seq_printf(m
, "GPU idle: %s\n", yesno(!dev_priv
->gt
.awake
));
2793 seq_printf(m
, "IRQs disabled: %s\n",
2794 yesno(!intel_irqs_enabled(dev_priv
)));
2796 seq_printf(m
, "Usage count: %d\n",
2797 atomic_read(&dev
->dev
->power
.usage_count
));
2799 seq_printf(m
, "Device Power Management (CONFIG_PM) disabled\n");
2801 seq_printf(m
, "PCI device power state: %s [%d]\n",
2802 pci_power_name(dev_priv
->drm
.pdev
->current_state
),
2803 dev_priv
->drm
.pdev
->current_state
);
2808 static int i915_power_domain_info(struct seq_file
*m
, void *unused
)
2810 struct drm_info_node
*node
= m
->private;
2811 struct drm_device
*dev
= node
->minor
->dev
;
2812 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2813 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
2816 mutex_lock(&power_domains
->lock
);
2818 seq_printf(m
, "%-25s %s\n", "Power well/domain", "Use count");
2819 for (i
= 0; i
< power_domains
->power_well_count
; i
++) {
2820 struct i915_power_well
*power_well
;
2821 enum intel_display_power_domain power_domain
;
2823 power_well
= &power_domains
->power_wells
[i
];
2824 seq_printf(m
, "%-25s %d\n", power_well
->name
,
2827 for (power_domain
= 0; power_domain
< POWER_DOMAIN_NUM
;
2829 if (!(BIT(power_domain
) & power_well
->domains
))
2832 seq_printf(m
, " %-23s %d\n",
2833 intel_display_power_domain_str(power_domain
),
2834 power_domains
->domain_use_count
[power_domain
]);
2838 mutex_unlock(&power_domains
->lock
);
2843 static int i915_dmc_info(struct seq_file
*m
, void *unused
)
2845 struct drm_info_node
*node
= m
->private;
2846 struct drm_device
*dev
= node
->minor
->dev
;
2847 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2848 struct intel_csr
*csr
;
2850 if (!HAS_CSR(dev
)) {
2851 seq_puts(m
, "not supported\n");
2855 csr
= &dev_priv
->csr
;
2857 intel_runtime_pm_get(dev_priv
);
2859 seq_printf(m
, "fw loaded: %s\n", yesno(csr
->dmc_payload
!= NULL
));
2860 seq_printf(m
, "path: %s\n", csr
->fw_path
);
2862 if (!csr
->dmc_payload
)
2865 seq_printf(m
, "version: %d.%d\n", CSR_VERSION_MAJOR(csr
->version
),
2866 CSR_VERSION_MINOR(csr
->version
));
2868 if (IS_SKYLAKE(dev
) && csr
->version
>= CSR_VERSION(1, 6)) {
2869 seq_printf(m
, "DC3 -> DC5 count: %d\n",
2870 I915_READ(SKL_CSR_DC3_DC5_COUNT
));
2871 seq_printf(m
, "DC5 -> DC6 count: %d\n",
2872 I915_READ(SKL_CSR_DC5_DC6_COUNT
));
2873 } else if (IS_BROXTON(dev
) && csr
->version
>= CSR_VERSION(1, 4)) {
2874 seq_printf(m
, "DC3 -> DC5 count: %d\n",
2875 I915_READ(BXT_CSR_DC3_DC5_COUNT
));
2879 seq_printf(m
, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2880 seq_printf(m
, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE
));
2881 seq_printf(m
, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL
));
2883 intel_runtime_pm_put(dev_priv
);
2888 static void intel_seq_print_mode(struct seq_file
*m
, int tabs
,
2889 struct drm_display_mode
*mode
)
2893 for (i
= 0; i
< tabs
; i
++)
2896 seq_printf(m
, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2897 mode
->base
.id
, mode
->name
,
2898 mode
->vrefresh
, mode
->clock
,
2899 mode
->hdisplay
, mode
->hsync_start
,
2900 mode
->hsync_end
, mode
->htotal
,
2901 mode
->vdisplay
, mode
->vsync_start
,
2902 mode
->vsync_end
, mode
->vtotal
,
2903 mode
->type
, mode
->flags
);
2906 static void intel_encoder_info(struct seq_file
*m
,
2907 struct intel_crtc
*intel_crtc
,
2908 struct intel_encoder
*intel_encoder
)
2910 struct drm_info_node
*node
= m
->private;
2911 struct drm_device
*dev
= node
->minor
->dev
;
2912 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2913 struct intel_connector
*intel_connector
;
2914 struct drm_encoder
*encoder
;
2916 encoder
= &intel_encoder
->base
;
2917 seq_printf(m
, "\tencoder %d: type: %s, connectors:\n",
2918 encoder
->base
.id
, encoder
->name
);
2919 for_each_connector_on_encoder(dev
, encoder
, intel_connector
) {
2920 struct drm_connector
*connector
= &intel_connector
->base
;
2921 seq_printf(m
, "\t\tconnector %d: type: %s, status: %s",
2924 drm_get_connector_status_name(connector
->status
));
2925 if (connector
->status
== connector_status_connected
) {
2926 struct drm_display_mode
*mode
= &crtc
->mode
;
2927 seq_printf(m
, ", mode:\n");
2928 intel_seq_print_mode(m
, 2, mode
);
2935 static void intel_crtc_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
2937 struct drm_info_node
*node
= m
->private;
2938 struct drm_device
*dev
= node
->minor
->dev
;
2939 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2940 struct intel_encoder
*intel_encoder
;
2941 struct drm_plane_state
*plane_state
= crtc
->primary
->state
;
2942 struct drm_framebuffer
*fb
= plane_state
->fb
;
2945 seq_printf(m
, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2946 fb
->base
.id
, plane_state
->src_x
>> 16,
2947 plane_state
->src_y
>> 16, fb
->width
, fb
->height
);
2949 seq_puts(m
, "\tprimary plane disabled\n");
2950 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
2951 intel_encoder_info(m
, intel_crtc
, intel_encoder
);
2954 static void intel_panel_info(struct seq_file
*m
, struct intel_panel
*panel
)
2956 struct drm_display_mode
*mode
= panel
->fixed_mode
;
2958 seq_printf(m
, "\tfixed mode:\n");
2959 intel_seq_print_mode(m
, 2, mode
);
2962 static void intel_dp_info(struct seq_file
*m
,
2963 struct intel_connector
*intel_connector
)
2965 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2966 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
2968 seq_printf(m
, "\tDPCD rev: %x\n", intel_dp
->dpcd
[DP_DPCD_REV
]);
2969 seq_printf(m
, "\taudio support: %s\n", yesno(intel_dp
->has_audio
));
2970 if (intel_connector
->base
.connector_type
== DRM_MODE_CONNECTOR_eDP
)
2971 intel_panel_info(m
, &intel_connector
->panel
);
2974 static void intel_hdmi_info(struct seq_file
*m
,
2975 struct intel_connector
*intel_connector
)
2977 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2978 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&intel_encoder
->base
);
2980 seq_printf(m
, "\taudio support: %s\n", yesno(intel_hdmi
->has_audio
));
2983 static void intel_lvds_info(struct seq_file
*m
,
2984 struct intel_connector
*intel_connector
)
2986 intel_panel_info(m
, &intel_connector
->panel
);
2989 static void intel_connector_info(struct seq_file
*m
,
2990 struct drm_connector
*connector
)
2992 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2993 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2994 struct drm_display_mode
*mode
;
2996 seq_printf(m
, "connector %d: type %s, status: %s\n",
2997 connector
->base
.id
, connector
->name
,
2998 drm_get_connector_status_name(connector
->status
));
2999 if (connector
->status
== connector_status_connected
) {
3000 seq_printf(m
, "\tname: %s\n", connector
->display_info
.name
);
3001 seq_printf(m
, "\tphysical dimensions: %dx%dmm\n",
3002 connector
->display_info
.width_mm
,
3003 connector
->display_info
.height_mm
);
3004 seq_printf(m
, "\tsubpixel order: %s\n",
3005 drm_get_subpixel_order_name(connector
->display_info
.subpixel_order
));
3006 seq_printf(m
, "\tCEA rev: %d\n",
3007 connector
->display_info
.cea_rev
);
3010 if (!intel_encoder
|| intel_encoder
->type
== INTEL_OUTPUT_DP_MST
)
3013 switch (connector
->connector_type
) {
3014 case DRM_MODE_CONNECTOR_DisplayPort
:
3015 case DRM_MODE_CONNECTOR_eDP
:
3016 intel_dp_info(m
, intel_connector
);
3018 case DRM_MODE_CONNECTOR_LVDS
:
3019 if (intel_encoder
->type
== INTEL_OUTPUT_LVDS
)
3020 intel_lvds_info(m
, intel_connector
);
3022 case DRM_MODE_CONNECTOR_HDMIA
:
3023 if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
||
3024 intel_encoder
->type
== INTEL_OUTPUT_UNKNOWN
)
3025 intel_hdmi_info(m
, intel_connector
);
3031 seq_printf(m
, "\tmodes:\n");
3032 list_for_each_entry(mode
, &connector
->modes
, head
)
3033 intel_seq_print_mode(m
, 2, mode
);
3036 static bool cursor_active(struct drm_device
*dev
, int pipe
)
3038 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3041 if (IS_845G(dev
) || IS_I865G(dev
))
3042 state
= I915_READ(CURCNTR(PIPE_A
)) & CURSOR_ENABLE
;
3044 state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
3049 static bool cursor_position(struct drm_device
*dev
, int pipe
, int *x
, int *y
)
3051 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3054 pos
= I915_READ(CURPOS(pipe
));
3056 *x
= (pos
>> CURSOR_X_SHIFT
) & CURSOR_POS_MASK
;
3057 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
))
3060 *y
= (pos
>> CURSOR_Y_SHIFT
) & CURSOR_POS_MASK
;
3061 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
))
3064 return cursor_active(dev
, pipe
);
3067 static const char *plane_type(enum drm_plane_type type
)
3070 case DRM_PLANE_TYPE_OVERLAY
:
3072 case DRM_PLANE_TYPE_PRIMARY
:
3074 case DRM_PLANE_TYPE_CURSOR
:
3077 * Deliberately omitting default: to generate compiler warnings
3078 * when a new drm_plane_type gets added.
3085 static const char *plane_rotation(unsigned int rotation
)
3087 static char buf
[48];
3089 * According to doc only one DRM_ROTATE_ is allowed but this
3090 * will print them all to visualize if the values are misused
3092 snprintf(buf
, sizeof(buf
),
3093 "%s%s%s%s%s%s(0x%08x)",
3094 (rotation
& BIT(DRM_ROTATE_0
)) ? "0 " : "",
3095 (rotation
& BIT(DRM_ROTATE_90
)) ? "90 " : "",
3096 (rotation
& BIT(DRM_ROTATE_180
)) ? "180 " : "",
3097 (rotation
& BIT(DRM_ROTATE_270
)) ? "270 " : "",
3098 (rotation
& BIT(DRM_REFLECT_X
)) ? "FLIPX " : "",
3099 (rotation
& BIT(DRM_REFLECT_Y
)) ? "FLIPY " : "",
3105 static void intel_plane_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
3107 struct drm_info_node
*node
= m
->private;
3108 struct drm_device
*dev
= node
->minor
->dev
;
3109 struct intel_plane
*intel_plane
;
3111 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
3112 struct drm_plane_state
*state
;
3113 struct drm_plane
*plane
= &intel_plane
->base
;
3115 if (!plane
->state
) {
3116 seq_puts(m
, "plane->state is NULL!\n");
3120 state
= plane
->state
;
3122 seq_printf(m
, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3124 plane_type(intel_plane
->base
.type
),
3125 state
->crtc_x
, state
->crtc_y
,
3126 state
->crtc_w
, state
->crtc_h
,
3127 (state
->src_x
>> 16),
3128 ((state
->src_x
& 0xffff) * 15625) >> 10,
3129 (state
->src_y
>> 16),
3130 ((state
->src_y
& 0xffff) * 15625) >> 10,
3131 (state
->src_w
>> 16),
3132 ((state
->src_w
& 0xffff) * 15625) >> 10,
3133 (state
->src_h
>> 16),
3134 ((state
->src_h
& 0xffff) * 15625) >> 10,
3135 state
->fb
? drm_get_format_name(state
->fb
->pixel_format
) : "N/A",
3136 plane_rotation(state
->rotation
));
3140 static void intel_scaler_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
3142 struct intel_crtc_state
*pipe_config
;
3143 int num_scalers
= intel_crtc
->num_scalers
;
3146 pipe_config
= to_intel_crtc_state(intel_crtc
->base
.state
);
3148 /* Not all platformas have a scaler */
3150 seq_printf(m
, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3152 pipe_config
->scaler_state
.scaler_users
,
3153 pipe_config
->scaler_state
.scaler_id
);
3155 for (i
= 0; i
< SKL_NUM_SCALERS
; i
++) {
3156 struct intel_scaler
*sc
=
3157 &pipe_config
->scaler_state
.scalers
[i
];
3159 seq_printf(m
, ", scalers[%d]: use=%s, mode=%x",
3160 i
, yesno(sc
->in_use
), sc
->mode
);
3164 seq_puts(m
, "\tNo scalers available on this platform\n");
3168 static int i915_display_info(struct seq_file
*m
, void *unused
)
3170 struct drm_info_node
*node
= m
->private;
3171 struct drm_device
*dev
= node
->minor
->dev
;
3172 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3173 struct intel_crtc
*crtc
;
3174 struct drm_connector
*connector
;
3176 intel_runtime_pm_get(dev_priv
);
3177 drm_modeset_lock_all(dev
);
3178 seq_printf(m
, "CRTC info\n");
3179 seq_printf(m
, "---------\n");
3180 for_each_intel_crtc(dev
, crtc
) {
3182 struct intel_crtc_state
*pipe_config
;
3185 pipe_config
= to_intel_crtc_state(crtc
->base
.state
);
3187 seq_printf(m
, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3188 crtc
->base
.base
.id
, pipe_name(crtc
->pipe
),
3189 yesno(pipe_config
->base
.active
),
3190 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
,
3191 yesno(pipe_config
->dither
), pipe_config
->pipe_bpp
);
3193 if (pipe_config
->base
.active
) {
3194 intel_crtc_info(m
, crtc
);
3196 active
= cursor_position(dev
, crtc
->pipe
, &x
, &y
);
3197 seq_printf(m
, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3198 yesno(crtc
->cursor_base
),
3199 x
, y
, crtc
->base
.cursor
->state
->crtc_w
,
3200 crtc
->base
.cursor
->state
->crtc_h
,
3201 crtc
->cursor_addr
, yesno(active
));
3202 intel_scaler_info(m
, crtc
);
3203 intel_plane_info(m
, crtc
);
3206 seq_printf(m
, "\tunderrun reporting: cpu=%s pch=%s \n",
3207 yesno(!crtc
->cpu_fifo_underrun_disabled
),
3208 yesno(!crtc
->pch_fifo_underrun_disabled
));
3211 seq_printf(m
, "\n");
3212 seq_printf(m
, "Connector info\n");
3213 seq_printf(m
, "--------------\n");
3214 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
3215 intel_connector_info(m
, connector
);
3217 drm_modeset_unlock_all(dev
);
3218 intel_runtime_pm_put(dev_priv
);
3223 static int i915_semaphore_status(struct seq_file
*m
, void *unused
)
3225 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3226 struct drm_device
*dev
= node
->minor
->dev
;
3227 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3228 struct intel_engine_cs
*engine
;
3229 int num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
3230 enum intel_engine_id id
;
3233 if (!i915_semaphore_is_enabled(dev_priv
)) {
3234 seq_puts(m
, "Semaphores are disabled\n");
3238 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3241 intel_runtime_pm_get(dev_priv
);
3243 if (IS_BROADWELL(dev
)) {
3247 page
= i915_gem_object_get_page(dev_priv
->semaphore_obj
, 0);
3249 seqno
= (uint64_t *)kmap_atomic(page
);
3250 for_each_engine_id(engine
, dev_priv
, id
) {
3253 seq_printf(m
, "%s\n", engine
->name
);
3255 seq_puts(m
, " Last signal:");
3256 for (j
= 0; j
< num_rings
; j
++) {
3257 offset
= id
* I915_NUM_ENGINES
+ j
;
3258 seq_printf(m
, "0x%08llx (0x%02llx) ",
3259 seqno
[offset
], offset
* 8);
3263 seq_puts(m
, " Last wait: ");
3264 for (j
= 0; j
< num_rings
; j
++) {
3265 offset
= id
+ (j
* I915_NUM_ENGINES
);
3266 seq_printf(m
, "0x%08llx (0x%02llx) ",
3267 seqno
[offset
], offset
* 8);
3272 kunmap_atomic(seqno
);
3274 seq_puts(m
, " Last signal:");
3275 for_each_engine(engine
, dev_priv
)
3276 for (j
= 0; j
< num_rings
; j
++)
3277 seq_printf(m
, "0x%08x\n",
3278 I915_READ(engine
->semaphore
.mbox
.signal
[j
]));
3282 seq_puts(m
, "\nSync seqno:\n");
3283 for_each_engine(engine
, dev_priv
) {
3284 for (j
= 0; j
< num_rings
; j
++)
3285 seq_printf(m
, " 0x%08x ",
3286 engine
->semaphore
.sync_seqno
[j
]);
3291 intel_runtime_pm_put(dev_priv
);
3292 mutex_unlock(&dev
->struct_mutex
);
3296 static int i915_shared_dplls_info(struct seq_file
*m
, void *unused
)
3298 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3299 struct drm_device
*dev
= node
->minor
->dev
;
3300 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3303 drm_modeset_lock_all(dev
);
3304 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3305 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
3307 seq_printf(m
, "DPLL%i: %s, id: %i\n", i
, pll
->name
, pll
->id
);
3308 seq_printf(m
, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3309 pll
->config
.crtc_mask
, pll
->active_mask
, yesno(pll
->on
));
3310 seq_printf(m
, " tracked hardware state:\n");
3311 seq_printf(m
, " dpll: 0x%08x\n", pll
->config
.hw_state
.dpll
);
3312 seq_printf(m
, " dpll_md: 0x%08x\n",
3313 pll
->config
.hw_state
.dpll_md
);
3314 seq_printf(m
, " fp0: 0x%08x\n", pll
->config
.hw_state
.fp0
);
3315 seq_printf(m
, " fp1: 0x%08x\n", pll
->config
.hw_state
.fp1
);
3316 seq_printf(m
, " wrpll: 0x%08x\n", pll
->config
.hw_state
.wrpll
);
3318 drm_modeset_unlock_all(dev
);
3323 static int i915_wa_registers(struct seq_file
*m
, void *unused
)
3327 struct intel_engine_cs
*engine
;
3328 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3329 struct drm_device
*dev
= node
->minor
->dev
;
3330 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3331 struct i915_workarounds
*workarounds
= &dev_priv
->workarounds
;
3332 enum intel_engine_id id
;
3334 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3338 intel_runtime_pm_get(dev_priv
);
3340 seq_printf(m
, "Workarounds applied: %d\n", workarounds
->count
);
3341 for_each_engine_id(engine
, dev_priv
, id
)
3342 seq_printf(m
, "HW whitelist count for %s: %d\n",
3343 engine
->name
, workarounds
->hw_whitelist_count
[id
]);
3344 for (i
= 0; i
< workarounds
->count
; ++i
) {
3346 u32 mask
, value
, read
;
3349 addr
= workarounds
->reg
[i
].addr
;
3350 mask
= workarounds
->reg
[i
].mask
;
3351 value
= workarounds
->reg
[i
].value
;
3352 read
= I915_READ(addr
);
3353 ok
= (value
& mask
) == (read
& mask
);
3354 seq_printf(m
, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3355 i915_mmio_reg_offset(addr
), value
, mask
, read
, ok
? "OK" : "FAIL");
3358 intel_runtime_pm_put(dev_priv
);
3359 mutex_unlock(&dev
->struct_mutex
);
3364 static int i915_ddb_info(struct seq_file
*m
, void *unused
)
3366 struct drm_info_node
*node
= m
->private;
3367 struct drm_device
*dev
= node
->minor
->dev
;
3368 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3369 struct skl_ddb_allocation
*ddb
;
3370 struct skl_ddb_entry
*entry
;
3374 if (INTEL_INFO(dev
)->gen
< 9)
3377 drm_modeset_lock_all(dev
);
3379 ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
3381 seq_printf(m
, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3383 for_each_pipe(dev_priv
, pipe
) {
3384 seq_printf(m
, "Pipe %c\n", pipe_name(pipe
));
3386 for_each_plane(dev_priv
, pipe
, plane
) {
3387 entry
= &ddb
->plane
[pipe
][plane
];
3388 seq_printf(m
, " Plane%-8d%8u%8u%8u\n", plane
+ 1,
3389 entry
->start
, entry
->end
,
3390 skl_ddb_entry_size(entry
));
3393 entry
= &ddb
->plane
[pipe
][PLANE_CURSOR
];
3394 seq_printf(m
, " %-13s%8u%8u%8u\n", "Cursor", entry
->start
,
3395 entry
->end
, skl_ddb_entry_size(entry
));
3398 drm_modeset_unlock_all(dev
);
3403 static void drrs_status_per_crtc(struct seq_file
*m
,
3404 struct drm_device
*dev
, struct intel_crtc
*intel_crtc
)
3406 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3407 struct i915_drrs
*drrs
= &dev_priv
->drrs
;
3409 struct drm_connector
*connector
;
3411 drm_for_each_connector(connector
, dev
) {
3412 if (connector
->state
->crtc
!= &intel_crtc
->base
)
3415 seq_printf(m
, "%s:\n", connector
->name
);
3418 if (dev_priv
->vbt
.drrs_type
== STATIC_DRRS_SUPPORT
)
3419 seq_puts(m
, "\tVBT: DRRS_type: Static");
3420 else if (dev_priv
->vbt
.drrs_type
== SEAMLESS_DRRS_SUPPORT
)
3421 seq_puts(m
, "\tVBT: DRRS_type: Seamless");
3422 else if (dev_priv
->vbt
.drrs_type
== DRRS_NOT_SUPPORTED
)
3423 seq_puts(m
, "\tVBT: DRRS_type: None");
3425 seq_puts(m
, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3427 seq_puts(m
, "\n\n");
3429 if (to_intel_crtc_state(intel_crtc
->base
.state
)->has_drrs
) {
3430 struct intel_panel
*panel
;
3432 mutex_lock(&drrs
->mutex
);
3433 /* DRRS Supported */
3434 seq_puts(m
, "\tDRRS Supported: Yes\n");
3436 /* disable_drrs() will make drrs->dp NULL */
3438 seq_puts(m
, "Idleness DRRS: Disabled");
3439 mutex_unlock(&drrs
->mutex
);
3443 panel
= &drrs
->dp
->attached_connector
->panel
;
3444 seq_printf(m
, "\t\tBusy_frontbuffer_bits: 0x%X",
3445 drrs
->busy_frontbuffer_bits
);
3447 seq_puts(m
, "\n\t\t");
3448 if (drrs
->refresh_rate_type
== DRRS_HIGH_RR
) {
3449 seq_puts(m
, "DRRS_State: DRRS_HIGH_RR\n");
3450 vrefresh
= panel
->fixed_mode
->vrefresh
;
3451 } else if (drrs
->refresh_rate_type
== DRRS_LOW_RR
) {
3452 seq_puts(m
, "DRRS_State: DRRS_LOW_RR\n");
3453 vrefresh
= panel
->downclock_mode
->vrefresh
;
3455 seq_printf(m
, "DRRS_State: Unknown(%d)\n",
3456 drrs
->refresh_rate_type
);
3457 mutex_unlock(&drrs
->mutex
);
3460 seq_printf(m
, "\t\tVrefresh: %d", vrefresh
);
3462 seq_puts(m
, "\n\t\t");
3463 mutex_unlock(&drrs
->mutex
);
3465 /* DRRS not supported. Print the VBT parameter*/
3466 seq_puts(m
, "\tDRRS Supported : No");
3471 static int i915_drrs_status(struct seq_file
*m
, void *unused
)
3473 struct drm_info_node
*node
= m
->private;
3474 struct drm_device
*dev
= node
->minor
->dev
;
3475 struct intel_crtc
*intel_crtc
;
3476 int active_crtc_cnt
= 0;
3478 drm_modeset_lock_all(dev
);
3479 for_each_intel_crtc(dev
, intel_crtc
) {
3480 if (intel_crtc
->base
.state
->active
) {
3482 seq_printf(m
, "\nCRTC %d: ", active_crtc_cnt
);
3484 drrs_status_per_crtc(m
, dev
, intel_crtc
);
3487 drm_modeset_unlock_all(dev
);
3489 if (!active_crtc_cnt
)
3490 seq_puts(m
, "No active crtc found\n");
3495 struct pipe_crc_info
{
3497 struct drm_device
*dev
;
3501 static int i915_dp_mst_info(struct seq_file
*m
, void *unused
)
3503 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3504 struct drm_device
*dev
= node
->minor
->dev
;
3505 struct intel_encoder
*intel_encoder
;
3506 struct intel_digital_port
*intel_dig_port
;
3507 struct drm_connector
*connector
;
3509 drm_modeset_lock_all(dev
);
3510 drm_for_each_connector(connector
, dev
) {
3511 if (connector
->connector_type
!= DRM_MODE_CONNECTOR_DisplayPort
)
3514 intel_encoder
= intel_attached_encoder(connector
);
3515 if (!intel_encoder
|| intel_encoder
->type
== INTEL_OUTPUT_DP_MST
)
3518 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
3519 if (!intel_dig_port
->dp
.can_mst
)
3522 seq_printf(m
, "MST Source Port %c\n",
3523 port_name(intel_dig_port
->port
));
3524 drm_dp_mst_dump_topology(m
, &intel_dig_port
->dp
.mst_mgr
);
3526 drm_modeset_unlock_all(dev
);
3530 static int i915_pipe_crc_open(struct inode
*inode
, struct file
*filep
)
3532 struct pipe_crc_info
*info
= inode
->i_private
;
3533 struct drm_i915_private
*dev_priv
= to_i915(info
->dev
);
3534 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
3536 if (info
->pipe
>= INTEL_INFO(info
->dev
)->num_pipes
)
3539 spin_lock_irq(&pipe_crc
->lock
);
3541 if (pipe_crc
->opened
) {
3542 spin_unlock_irq(&pipe_crc
->lock
);
3543 return -EBUSY
; /* already open */
3546 pipe_crc
->opened
= true;
3547 filep
->private_data
= inode
->i_private
;
3549 spin_unlock_irq(&pipe_crc
->lock
);
3554 static int i915_pipe_crc_release(struct inode
*inode
, struct file
*filep
)
3556 struct pipe_crc_info
*info
= inode
->i_private
;
3557 struct drm_i915_private
*dev_priv
= to_i915(info
->dev
);
3558 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
3560 spin_lock_irq(&pipe_crc
->lock
);
3561 pipe_crc
->opened
= false;
3562 spin_unlock_irq(&pipe_crc
->lock
);
3567 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3568 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3569 /* account for \'0' */
3570 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3572 static int pipe_crc_data_count(struct intel_pipe_crc
*pipe_crc
)
3574 assert_spin_locked(&pipe_crc
->lock
);
3575 return CIRC_CNT(pipe_crc
->head
, pipe_crc
->tail
,
3576 INTEL_PIPE_CRC_ENTRIES_NR
);
3580 i915_pipe_crc_read(struct file
*filep
, char __user
*user_buf
, size_t count
,
3583 struct pipe_crc_info
*info
= filep
->private_data
;
3584 struct drm_device
*dev
= info
->dev
;
3585 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3586 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
3587 char buf
[PIPE_CRC_BUFFER_LEN
];
3592 * Don't allow user space to provide buffers not big enough to hold
3595 if (count
< PIPE_CRC_LINE_LEN
)
3598 if (pipe_crc
->source
== INTEL_PIPE_CRC_SOURCE_NONE
)
3601 /* nothing to read */
3602 spin_lock_irq(&pipe_crc
->lock
);
3603 while (pipe_crc_data_count(pipe_crc
) == 0) {
3606 if (filep
->f_flags
& O_NONBLOCK
) {
3607 spin_unlock_irq(&pipe_crc
->lock
);
3611 ret
= wait_event_interruptible_lock_irq(pipe_crc
->wq
,
3612 pipe_crc_data_count(pipe_crc
), pipe_crc
->lock
);
3614 spin_unlock_irq(&pipe_crc
->lock
);
3619 /* We now have one or more entries to read */
3620 n_entries
= count
/ PIPE_CRC_LINE_LEN
;
3623 while (n_entries
> 0) {
3624 struct intel_pipe_crc_entry
*entry
=
3625 &pipe_crc
->entries
[pipe_crc
->tail
];
3628 if (CIRC_CNT(pipe_crc
->head
, pipe_crc
->tail
,
3629 INTEL_PIPE_CRC_ENTRIES_NR
) < 1)
3632 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR
);
3633 pipe_crc
->tail
= (pipe_crc
->tail
+ 1) & (INTEL_PIPE_CRC_ENTRIES_NR
- 1);
3635 bytes_read
+= snprintf(buf
, PIPE_CRC_BUFFER_LEN
,
3636 "%8u %8x %8x %8x %8x %8x\n",
3637 entry
->frame
, entry
->crc
[0],
3638 entry
->crc
[1], entry
->crc
[2],
3639 entry
->crc
[3], entry
->crc
[4]);
3641 spin_unlock_irq(&pipe_crc
->lock
);
3643 ret
= copy_to_user(user_buf
, buf
, PIPE_CRC_LINE_LEN
);
3644 if (ret
== PIPE_CRC_LINE_LEN
)
3647 user_buf
+= PIPE_CRC_LINE_LEN
;
3650 spin_lock_irq(&pipe_crc
->lock
);
3653 spin_unlock_irq(&pipe_crc
->lock
);
3658 static const struct file_operations i915_pipe_crc_fops
= {
3659 .owner
= THIS_MODULE
,
3660 .open
= i915_pipe_crc_open
,
3661 .read
= i915_pipe_crc_read
,
3662 .release
= i915_pipe_crc_release
,
3665 static struct pipe_crc_info i915_pipe_crc_data
[I915_MAX_PIPES
] = {
3667 .name
= "i915_pipe_A_crc",
3671 .name
= "i915_pipe_B_crc",
3675 .name
= "i915_pipe_C_crc",
3680 static int i915_pipe_crc_create(struct dentry
*root
, struct drm_minor
*minor
,
3683 struct drm_device
*dev
= minor
->dev
;
3685 struct pipe_crc_info
*info
= &i915_pipe_crc_data
[pipe
];
3688 ent
= debugfs_create_file(info
->name
, S_IRUGO
, root
, info
,
3689 &i915_pipe_crc_fops
);
3693 return drm_add_fake_info_node(minor
, ent
, info
);
3696 static const char * const pipe_crc_sources
[] = {
3709 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source
)
3711 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources
) != INTEL_PIPE_CRC_SOURCE_MAX
);
3712 return pipe_crc_sources
[source
];
3715 static int display_crc_ctl_show(struct seq_file
*m
, void *data
)
3717 struct drm_device
*dev
= m
->private;
3718 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3721 for (i
= 0; i
< I915_MAX_PIPES
; i
++)
3722 seq_printf(m
, "%c %s\n", pipe_name(i
),
3723 pipe_crc_source_name(dev_priv
->pipe_crc
[i
].source
));
3728 static int display_crc_ctl_open(struct inode
*inode
, struct file
*file
)
3730 struct drm_device
*dev
= inode
->i_private
;
3732 return single_open(file
, display_crc_ctl_show
, dev
);
3735 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
3738 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3739 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3742 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3743 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_INCLUDE_BORDER_I8XX
;
3745 case INTEL_PIPE_CRC_SOURCE_NONE
:
3755 static int i9xx_pipe_crc_auto_source(struct drm_device
*dev
, enum pipe pipe
,
3756 enum intel_pipe_crc_source
*source
)
3758 struct intel_encoder
*encoder
;
3759 struct intel_crtc
*crtc
;
3760 struct intel_digital_port
*dig_port
;
3763 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3765 drm_modeset_lock_all(dev
);
3766 for_each_intel_encoder(dev
, encoder
) {
3767 if (!encoder
->base
.crtc
)
3770 crtc
= to_intel_crtc(encoder
->base
.crtc
);
3772 if (crtc
->pipe
!= pipe
)
3775 switch (encoder
->type
) {
3776 case INTEL_OUTPUT_TVOUT
:
3777 *source
= INTEL_PIPE_CRC_SOURCE_TV
;
3779 case INTEL_OUTPUT_DP
:
3780 case INTEL_OUTPUT_EDP
:
3781 dig_port
= enc_to_dig_port(&encoder
->base
);
3782 switch (dig_port
->port
) {
3784 *source
= INTEL_PIPE_CRC_SOURCE_DP_B
;
3787 *source
= INTEL_PIPE_CRC_SOURCE_DP_C
;
3790 *source
= INTEL_PIPE_CRC_SOURCE_DP_D
;
3793 WARN(1, "nonexisting DP port %c\n",
3794 port_name(dig_port
->port
));
3802 drm_modeset_unlock_all(dev
);
3807 static int vlv_pipe_crc_ctl_reg(struct drm_device
*dev
,
3809 enum intel_pipe_crc_source
*source
,
3812 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3813 bool need_stable_symbols
= false;
3815 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
3816 int ret
= i9xx_pipe_crc_auto_source(dev
, pipe
, source
);
3822 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3823 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_VLV
;
3825 case INTEL_PIPE_CRC_SOURCE_DP_B
:
3826 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_VLV
;
3827 need_stable_symbols
= true;
3829 case INTEL_PIPE_CRC_SOURCE_DP_C
:
3830 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_VLV
;
3831 need_stable_symbols
= true;
3833 case INTEL_PIPE_CRC_SOURCE_DP_D
:
3834 if (!IS_CHERRYVIEW(dev
))
3836 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_D_VLV
;
3837 need_stable_symbols
= true;
3839 case INTEL_PIPE_CRC_SOURCE_NONE
:
3847 * When the pipe CRC tap point is after the transcoders we need
3848 * to tweak symbol-level features to produce a deterministic series of
3849 * symbols for a given frame. We need to reset those features only once
3850 * a frame (instead of every nth symbol):
3851 * - DC-balance: used to ensure a better clock recovery from the data
3853 * - DisplayPort scrambling: used for EMI reduction
3855 if (need_stable_symbols
) {
3856 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3858 tmp
|= DC_BALANCE_RESET_VLV
;
3861 tmp
|= PIPE_A_SCRAMBLE_RESET
;
3864 tmp
|= PIPE_B_SCRAMBLE_RESET
;
3867 tmp
|= PIPE_C_SCRAMBLE_RESET
;
3872 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3878 static int i9xx_pipe_crc_ctl_reg(struct drm_device
*dev
,
3880 enum intel_pipe_crc_source
*source
,
3883 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3884 bool need_stable_symbols
= false;
3886 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
3887 int ret
= i9xx_pipe_crc_auto_source(dev
, pipe
, source
);
3893 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3894 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_I9XX
;
3896 case INTEL_PIPE_CRC_SOURCE_TV
:
3897 if (!SUPPORTS_TV(dev
))
3899 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_TV_PRE
;
3901 case INTEL_PIPE_CRC_SOURCE_DP_B
:
3904 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_G4X
;
3905 need_stable_symbols
= true;
3907 case INTEL_PIPE_CRC_SOURCE_DP_C
:
3910 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_G4X
;
3911 need_stable_symbols
= true;
3913 case INTEL_PIPE_CRC_SOURCE_DP_D
:
3916 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_D_G4X
;
3917 need_stable_symbols
= true;
3919 case INTEL_PIPE_CRC_SOURCE_NONE
:
3927 * When the pipe CRC tap point is after the transcoders we need
3928 * to tweak symbol-level features to produce a deterministic series of
3929 * symbols for a given frame. We need to reset those features only once
3930 * a frame (instead of every nth symbol):
3931 * - DC-balance: used to ensure a better clock recovery from the data
3933 * - DisplayPort scrambling: used for EMI reduction
3935 if (need_stable_symbols
) {
3936 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3938 WARN_ON(!IS_G4X(dev
));
3940 I915_WRITE(PORT_DFT_I9XX
,
3941 I915_READ(PORT_DFT_I9XX
) | DC_BALANCE_RESET
);
3944 tmp
|= PIPE_A_SCRAMBLE_RESET
;
3946 tmp
|= PIPE_B_SCRAMBLE_RESET
;
3948 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3954 static void vlv_undo_pipe_scramble_reset(struct drm_device
*dev
,
3957 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3958 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3962 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
3965 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
3968 tmp
&= ~PIPE_C_SCRAMBLE_RESET
;
3973 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
))
3974 tmp
&= ~DC_BALANCE_RESET_VLV
;
3975 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3979 static void g4x_undo_pipe_scramble_reset(struct drm_device
*dev
,
3982 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3983 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3986 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
3988 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
3989 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3991 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
)) {
3992 I915_WRITE(PORT_DFT_I9XX
,
3993 I915_READ(PORT_DFT_I9XX
) & ~DC_BALANCE_RESET
);
3997 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
4000 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
4001 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
4004 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
4005 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_ILK
;
4007 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
4008 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_ILK
;
4010 case INTEL_PIPE_CRC_SOURCE_PIPE
:
4011 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_ILK
;
4013 case INTEL_PIPE_CRC_SOURCE_NONE
:
4023 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device
*dev
, bool enable
)
4025 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4026 struct intel_crtc
*crtc
=
4027 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_A
]);
4028 struct intel_crtc_state
*pipe_config
;
4029 struct drm_atomic_state
*state
;
4032 drm_modeset_lock_all(dev
);
4033 state
= drm_atomic_state_alloc(dev
);
4039 state
->acquire_ctx
= drm_modeset_legacy_acquire_ctx(&crtc
->base
);
4040 pipe_config
= intel_atomic_get_crtc_state(state
, crtc
);
4041 if (IS_ERR(pipe_config
)) {
4042 ret
= PTR_ERR(pipe_config
);
4046 pipe_config
->pch_pfit
.force_thru
= enable
;
4047 if (pipe_config
->cpu_transcoder
== TRANSCODER_EDP
&&
4048 pipe_config
->pch_pfit
.enabled
!= enable
)
4049 pipe_config
->base
.connectors_changed
= true;
4051 ret
= drm_atomic_commit(state
);
4053 drm_modeset_unlock_all(dev
);
4054 WARN(ret
, "Toggling workaround to %i returns %i\n", enable
, ret
);
4056 drm_atomic_state_free(state
);
4059 static int ivb_pipe_crc_ctl_reg(struct drm_device
*dev
,
4061 enum intel_pipe_crc_source
*source
,
4064 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
4065 *source
= INTEL_PIPE_CRC_SOURCE_PF
;
4068 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
4069 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_IVB
;
4071 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
4072 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_IVB
;
4074 case INTEL_PIPE_CRC_SOURCE_PF
:
4075 if (IS_HASWELL(dev
) && pipe
== PIPE_A
)
4076 hsw_trans_edp_pipe_A_crc_wa(dev
, true);
4078 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PF_IVB
;
4080 case INTEL_PIPE_CRC_SOURCE_NONE
:
4090 static int pipe_crc_set_source(struct drm_device
*dev
, enum pipe pipe
,
4091 enum intel_pipe_crc_source source
)
4093 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4094 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
4095 struct intel_crtc
*crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
,
4097 enum intel_display_power_domain power_domain
;
4098 u32 val
= 0; /* shut up gcc */
4101 if (pipe_crc
->source
== source
)
4104 /* forbid changing the source without going back to 'none' */
4105 if (pipe_crc
->source
&& source
)
4108 power_domain
= POWER_DOMAIN_PIPE(pipe
);
4109 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
)) {
4110 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4115 ret
= i8xx_pipe_crc_ctl_reg(&source
, &val
);
4116 else if (INTEL_INFO(dev
)->gen
< 5)
4117 ret
= i9xx_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
4118 else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
4119 ret
= vlv_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
4120 else if (IS_GEN5(dev
) || IS_GEN6(dev
))
4121 ret
= ilk_pipe_crc_ctl_reg(&source
, &val
);
4123 ret
= ivb_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
4128 /* none -> real source transition */
4130 struct intel_pipe_crc_entry
*entries
;
4132 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4133 pipe_name(pipe
), pipe_crc_source_name(source
));
4135 entries
= kcalloc(INTEL_PIPE_CRC_ENTRIES_NR
,
4136 sizeof(pipe_crc
->entries
[0]),
4144 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4145 * enabled and disabled dynamically based on package C states,
4146 * user space can't make reliable use of the CRCs, so let's just
4147 * completely disable it.
4149 hsw_disable_ips(crtc
);
4151 spin_lock_irq(&pipe_crc
->lock
);
4152 kfree(pipe_crc
->entries
);
4153 pipe_crc
->entries
= entries
;
4156 spin_unlock_irq(&pipe_crc
->lock
);
4159 pipe_crc
->source
= source
;
4161 I915_WRITE(PIPE_CRC_CTL(pipe
), val
);
4162 POSTING_READ(PIPE_CRC_CTL(pipe
));
4164 /* real source -> none transition */
4165 if (source
== INTEL_PIPE_CRC_SOURCE_NONE
) {
4166 struct intel_pipe_crc_entry
*entries
;
4167 struct intel_crtc
*crtc
=
4168 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
4170 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4173 drm_modeset_lock(&crtc
->base
.mutex
, NULL
);
4174 if (crtc
->base
.state
->active
)
4175 intel_wait_for_vblank(dev
, pipe
);
4176 drm_modeset_unlock(&crtc
->base
.mutex
);
4178 spin_lock_irq(&pipe_crc
->lock
);
4179 entries
= pipe_crc
->entries
;
4180 pipe_crc
->entries
= NULL
;
4183 spin_unlock_irq(&pipe_crc
->lock
);
4188 g4x_undo_pipe_scramble_reset(dev
, pipe
);
4189 else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
4190 vlv_undo_pipe_scramble_reset(dev
, pipe
);
4191 else if (IS_HASWELL(dev
) && pipe
== PIPE_A
)
4192 hsw_trans_edp_pipe_A_crc_wa(dev
, false);
4194 hsw_enable_ips(crtc
);
4200 intel_display_power_put(dev_priv
, power_domain
);
4206 * Parse pipe CRC command strings:
4207 * command: wsp* object wsp+ name wsp+ source wsp*
4210 * source: (none | plane1 | plane2 | pf)
4211 * wsp: (#0x20 | #0x9 | #0xA)+
4214 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
4215 * "pipe A none" -> Stop CRC
4217 static int display_crc_ctl_tokenize(char *buf
, char *words
[], int max_words
)
4224 /* skip leading white space */
4225 buf
= skip_spaces(buf
);
4227 break; /* end of buffer */
4229 /* find end of word */
4230 for (end
= buf
; *end
&& !isspace(*end
); end
++)
4233 if (n_words
== max_words
) {
4234 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4236 return -EINVAL
; /* ran out of words[] before bytes */
4241 words
[n_words
++] = buf
;
4248 enum intel_pipe_crc_object
{
4249 PIPE_CRC_OBJECT_PIPE
,
4252 static const char * const pipe_crc_objects
[] = {
4257 display_crc_ctl_parse_object(const char *buf
, enum intel_pipe_crc_object
*o
)
4261 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_objects
); i
++)
4262 if (!strcmp(buf
, pipe_crc_objects
[i
])) {
4270 static int display_crc_ctl_parse_pipe(const char *buf
, enum pipe
*pipe
)
4272 const char name
= buf
[0];
4274 if (name
< 'A' || name
>= pipe_name(I915_MAX_PIPES
))
4283 display_crc_ctl_parse_source(const char *buf
, enum intel_pipe_crc_source
*s
)
4287 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_sources
); i
++)
4288 if (!strcmp(buf
, pipe_crc_sources
[i
])) {
4296 static int display_crc_ctl_parse(struct drm_device
*dev
, char *buf
, size_t len
)
4300 char *words
[N_WORDS
];
4302 enum intel_pipe_crc_object object
;
4303 enum intel_pipe_crc_source source
;
4305 n_words
= display_crc_ctl_tokenize(buf
, words
, N_WORDS
);
4306 if (n_words
!= N_WORDS
) {
4307 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4312 if (display_crc_ctl_parse_object(words
[0], &object
) < 0) {
4313 DRM_DEBUG_DRIVER("unknown object %s\n", words
[0]);
4317 if (display_crc_ctl_parse_pipe(words
[1], &pipe
) < 0) {
4318 DRM_DEBUG_DRIVER("unknown pipe %s\n", words
[1]);
4322 if (display_crc_ctl_parse_source(words
[2], &source
) < 0) {
4323 DRM_DEBUG_DRIVER("unknown source %s\n", words
[2]);
4327 return pipe_crc_set_source(dev
, pipe
, source
);
4330 static ssize_t
display_crc_ctl_write(struct file
*file
, const char __user
*ubuf
,
4331 size_t len
, loff_t
*offp
)
4333 struct seq_file
*m
= file
->private_data
;
4334 struct drm_device
*dev
= m
->private;
4341 if (len
> PAGE_SIZE
- 1) {
4342 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4347 tmpbuf
= kmalloc(len
+ 1, GFP_KERNEL
);
4351 if (copy_from_user(tmpbuf
, ubuf
, len
)) {
4357 ret
= display_crc_ctl_parse(dev
, tmpbuf
, len
);
4368 static const struct file_operations i915_display_crc_ctl_fops
= {
4369 .owner
= THIS_MODULE
,
4370 .open
= display_crc_ctl_open
,
4372 .llseek
= seq_lseek
,
4373 .release
= single_release
,
4374 .write
= display_crc_ctl_write
4377 static ssize_t
i915_displayport_test_active_write(struct file
*file
,
4378 const char __user
*ubuf
,
4379 size_t len
, loff_t
*offp
)
4383 struct drm_device
*dev
;
4384 struct drm_connector
*connector
;
4385 struct list_head
*connector_list
;
4386 struct intel_dp
*intel_dp
;
4389 dev
= ((struct seq_file
*)file
->private_data
)->private;
4391 connector_list
= &dev
->mode_config
.connector_list
;
4396 input_buffer
= kmalloc(len
+ 1, GFP_KERNEL
);
4400 if (copy_from_user(input_buffer
, ubuf
, len
)) {
4405 input_buffer
[len
] = '\0';
4406 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len
);
4408 list_for_each_entry(connector
, connector_list
, head
) {
4410 if (connector
->connector_type
!=
4411 DRM_MODE_CONNECTOR_DisplayPort
)
4414 if (connector
->status
== connector_status_connected
&&
4415 connector
->encoder
!= NULL
) {
4416 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4417 status
= kstrtoint(input_buffer
, 10, &val
);
4420 DRM_DEBUG_DRIVER("Got %d for test active\n", val
);
4421 /* To prevent erroneous activation of the compliance
4422 * testing code, only accept an actual value of 1 here
4425 intel_dp
->compliance_test_active
= 1;
4427 intel_dp
->compliance_test_active
= 0;
4431 kfree(input_buffer
);
4439 static int i915_displayport_test_active_show(struct seq_file
*m
, void *data
)
4441 struct drm_device
*dev
= m
->private;
4442 struct drm_connector
*connector
;
4443 struct list_head
*connector_list
= &dev
->mode_config
.connector_list
;
4444 struct intel_dp
*intel_dp
;
4446 list_for_each_entry(connector
, connector_list
, head
) {
4448 if (connector
->connector_type
!=
4449 DRM_MODE_CONNECTOR_DisplayPort
)
4452 if (connector
->status
== connector_status_connected
&&
4453 connector
->encoder
!= NULL
) {
4454 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4455 if (intel_dp
->compliance_test_active
)
4466 static int i915_displayport_test_active_open(struct inode
*inode
,
4469 struct drm_device
*dev
= inode
->i_private
;
4471 return single_open(file
, i915_displayport_test_active_show
, dev
);
4474 static const struct file_operations i915_displayport_test_active_fops
= {
4475 .owner
= THIS_MODULE
,
4476 .open
= i915_displayport_test_active_open
,
4478 .llseek
= seq_lseek
,
4479 .release
= single_release
,
4480 .write
= i915_displayport_test_active_write
4483 static int i915_displayport_test_data_show(struct seq_file
*m
, void *data
)
4485 struct drm_device
*dev
= m
->private;
4486 struct drm_connector
*connector
;
4487 struct list_head
*connector_list
= &dev
->mode_config
.connector_list
;
4488 struct intel_dp
*intel_dp
;
4490 list_for_each_entry(connector
, connector_list
, head
) {
4492 if (connector
->connector_type
!=
4493 DRM_MODE_CONNECTOR_DisplayPort
)
4496 if (connector
->status
== connector_status_connected
&&
4497 connector
->encoder
!= NULL
) {
4498 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4499 seq_printf(m
, "%lx", intel_dp
->compliance_test_data
);
4506 static int i915_displayport_test_data_open(struct inode
*inode
,
4509 struct drm_device
*dev
= inode
->i_private
;
4511 return single_open(file
, i915_displayport_test_data_show
, dev
);
4514 static const struct file_operations i915_displayport_test_data_fops
= {
4515 .owner
= THIS_MODULE
,
4516 .open
= i915_displayport_test_data_open
,
4518 .llseek
= seq_lseek
,
4519 .release
= single_release
4522 static int i915_displayport_test_type_show(struct seq_file
*m
, void *data
)
4524 struct drm_device
*dev
= m
->private;
4525 struct drm_connector
*connector
;
4526 struct list_head
*connector_list
= &dev
->mode_config
.connector_list
;
4527 struct intel_dp
*intel_dp
;
4529 list_for_each_entry(connector
, connector_list
, head
) {
4531 if (connector
->connector_type
!=
4532 DRM_MODE_CONNECTOR_DisplayPort
)
4535 if (connector
->status
== connector_status_connected
&&
4536 connector
->encoder
!= NULL
) {
4537 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4538 seq_printf(m
, "%02lx", intel_dp
->compliance_test_type
);
4546 static int i915_displayport_test_type_open(struct inode
*inode
,
4549 struct drm_device
*dev
= inode
->i_private
;
4551 return single_open(file
, i915_displayport_test_type_show
, dev
);
4554 static const struct file_operations i915_displayport_test_type_fops
= {
4555 .owner
= THIS_MODULE
,
4556 .open
= i915_displayport_test_type_open
,
4558 .llseek
= seq_lseek
,
4559 .release
= single_release
4562 static void wm_latency_show(struct seq_file
*m
, const uint16_t wm
[8])
4564 struct drm_device
*dev
= m
->private;
4568 if (IS_CHERRYVIEW(dev
))
4570 else if (IS_VALLEYVIEW(dev
))
4573 num_levels
= ilk_wm_max_level(dev
) + 1;
4575 drm_modeset_lock_all(dev
);
4577 for (level
= 0; level
< num_levels
; level
++) {
4578 unsigned int latency
= wm
[level
];
4581 * - WM1+ latency values in 0.5us units
4582 * - latencies are in us on gen9/vlv/chv
4584 if (INTEL_INFO(dev
)->gen
>= 9 || IS_VALLEYVIEW(dev
) ||
4590 seq_printf(m
, "WM%d %u (%u.%u usec)\n",
4591 level
, wm
[level
], latency
/ 10, latency
% 10);
4594 drm_modeset_unlock_all(dev
);
4597 static int pri_wm_latency_show(struct seq_file
*m
, void *data
)
4599 struct drm_device
*dev
= m
->private;
4600 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4601 const uint16_t *latencies
;
4603 if (INTEL_INFO(dev
)->gen
>= 9)
4604 latencies
= dev_priv
->wm
.skl_latency
;
4606 latencies
= to_i915(dev
)->wm
.pri_latency
;
4608 wm_latency_show(m
, latencies
);
4613 static int spr_wm_latency_show(struct seq_file
*m
, void *data
)
4615 struct drm_device
*dev
= m
->private;
4616 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4617 const uint16_t *latencies
;
4619 if (INTEL_INFO(dev
)->gen
>= 9)
4620 latencies
= dev_priv
->wm
.skl_latency
;
4622 latencies
= to_i915(dev
)->wm
.spr_latency
;
4624 wm_latency_show(m
, latencies
);
4629 static int cur_wm_latency_show(struct seq_file
*m
, void *data
)
4631 struct drm_device
*dev
= m
->private;
4632 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4633 const uint16_t *latencies
;
4635 if (INTEL_INFO(dev
)->gen
>= 9)
4636 latencies
= dev_priv
->wm
.skl_latency
;
4638 latencies
= to_i915(dev
)->wm
.cur_latency
;
4640 wm_latency_show(m
, latencies
);
4645 static int pri_wm_latency_open(struct inode
*inode
, struct file
*file
)
4647 struct drm_device
*dev
= inode
->i_private
;
4649 if (INTEL_INFO(dev
)->gen
< 5)
4652 return single_open(file
, pri_wm_latency_show
, dev
);
4655 static int spr_wm_latency_open(struct inode
*inode
, struct file
*file
)
4657 struct drm_device
*dev
= inode
->i_private
;
4659 if (HAS_GMCH_DISPLAY(dev
))
4662 return single_open(file
, spr_wm_latency_show
, dev
);
4665 static int cur_wm_latency_open(struct inode
*inode
, struct file
*file
)
4667 struct drm_device
*dev
= inode
->i_private
;
4669 if (HAS_GMCH_DISPLAY(dev
))
4672 return single_open(file
, cur_wm_latency_show
, dev
);
4675 static ssize_t
wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4676 size_t len
, loff_t
*offp
, uint16_t wm
[8])
4678 struct seq_file
*m
= file
->private_data
;
4679 struct drm_device
*dev
= m
->private;
4680 uint16_t new[8] = { 0 };
4686 if (IS_CHERRYVIEW(dev
))
4688 else if (IS_VALLEYVIEW(dev
))
4691 num_levels
= ilk_wm_max_level(dev
) + 1;
4693 if (len
>= sizeof(tmp
))
4696 if (copy_from_user(tmp
, ubuf
, len
))
4701 ret
= sscanf(tmp
, "%hu %hu %hu %hu %hu %hu %hu %hu",
4702 &new[0], &new[1], &new[2], &new[3],
4703 &new[4], &new[5], &new[6], &new[7]);
4704 if (ret
!= num_levels
)
4707 drm_modeset_lock_all(dev
);
4709 for (level
= 0; level
< num_levels
; level
++)
4710 wm
[level
] = new[level
];
4712 drm_modeset_unlock_all(dev
);
4718 static ssize_t
pri_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4719 size_t len
, loff_t
*offp
)
4721 struct seq_file
*m
= file
->private_data
;
4722 struct drm_device
*dev
= m
->private;
4723 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4724 uint16_t *latencies
;
4726 if (INTEL_INFO(dev
)->gen
>= 9)
4727 latencies
= dev_priv
->wm
.skl_latency
;
4729 latencies
= to_i915(dev
)->wm
.pri_latency
;
4731 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
4734 static ssize_t
spr_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4735 size_t len
, loff_t
*offp
)
4737 struct seq_file
*m
= file
->private_data
;
4738 struct drm_device
*dev
= m
->private;
4739 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4740 uint16_t *latencies
;
4742 if (INTEL_INFO(dev
)->gen
>= 9)
4743 latencies
= dev_priv
->wm
.skl_latency
;
4745 latencies
= to_i915(dev
)->wm
.spr_latency
;
4747 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
4750 static ssize_t
cur_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4751 size_t len
, loff_t
*offp
)
4753 struct seq_file
*m
= file
->private_data
;
4754 struct drm_device
*dev
= m
->private;
4755 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4756 uint16_t *latencies
;
4758 if (INTEL_INFO(dev
)->gen
>= 9)
4759 latencies
= dev_priv
->wm
.skl_latency
;
4761 latencies
= to_i915(dev
)->wm
.cur_latency
;
4763 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
4766 static const struct file_operations i915_pri_wm_latency_fops
= {
4767 .owner
= THIS_MODULE
,
4768 .open
= pri_wm_latency_open
,
4770 .llseek
= seq_lseek
,
4771 .release
= single_release
,
4772 .write
= pri_wm_latency_write
4775 static const struct file_operations i915_spr_wm_latency_fops
= {
4776 .owner
= THIS_MODULE
,
4777 .open
= spr_wm_latency_open
,
4779 .llseek
= seq_lseek
,
4780 .release
= single_release
,
4781 .write
= spr_wm_latency_write
4784 static const struct file_operations i915_cur_wm_latency_fops
= {
4785 .owner
= THIS_MODULE
,
4786 .open
= cur_wm_latency_open
,
4788 .llseek
= seq_lseek
,
4789 .release
= single_release
,
4790 .write
= cur_wm_latency_write
4794 i915_wedged_get(void *data
, u64
*val
)
4796 struct drm_device
*dev
= data
;
4797 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4799 *val
= i915_terminally_wedged(&dev_priv
->gpu_error
);
4805 i915_wedged_set(void *data
, u64 val
)
4807 struct drm_device
*dev
= data
;
4808 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4811 * There is no safeguard against this debugfs entry colliding
4812 * with the hangcheck calling same i915_handle_error() in
4813 * parallel, causing an explosion. For now we assume that the
4814 * test harness is responsible enough not to inject gpu hangs
4815 * while it is writing to 'i915_wedged'
4818 if (i915_reset_in_progress(&dev_priv
->gpu_error
))
4821 intel_runtime_pm_get(dev_priv
);
4823 i915_handle_error(dev_priv
, val
,
4824 "Manually setting wedged to %llu", val
);
4826 intel_runtime_pm_put(dev_priv
);
4831 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops
,
4832 i915_wedged_get
, i915_wedged_set
,
4836 i915_ring_missed_irq_get(void *data
, u64
*val
)
4838 struct drm_device
*dev
= data
;
4839 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4841 *val
= dev_priv
->gpu_error
.missed_irq_rings
;
4846 i915_ring_missed_irq_set(void *data
, u64 val
)
4848 struct drm_device
*dev
= data
;
4849 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4852 /* Lock against concurrent debugfs callers */
4853 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4856 dev_priv
->gpu_error
.missed_irq_rings
= val
;
4857 mutex_unlock(&dev
->struct_mutex
);
4862 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops
,
4863 i915_ring_missed_irq_get
, i915_ring_missed_irq_set
,
4867 i915_ring_test_irq_get(void *data
, u64
*val
)
4869 struct drm_device
*dev
= data
;
4870 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4872 *val
= dev_priv
->gpu_error
.test_irq_rings
;
4878 i915_ring_test_irq_set(void *data
, u64 val
)
4880 struct drm_device
*dev
= data
;
4881 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4883 val
&= INTEL_INFO(dev_priv
)->ring_mask
;
4884 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val
);
4885 dev_priv
->gpu_error
.test_irq_rings
= val
;
4890 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops
,
4891 i915_ring_test_irq_get
, i915_ring_test_irq_set
,
4894 #define DROP_UNBOUND 0x1
4895 #define DROP_BOUND 0x2
4896 #define DROP_RETIRE 0x4
4897 #define DROP_ACTIVE 0x8
4898 #define DROP_ALL (DROP_UNBOUND | \
4903 i915_drop_caches_get(void *data
, u64
*val
)
4911 i915_drop_caches_set(void *data
, u64 val
)
4913 struct drm_device
*dev
= data
;
4914 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4917 DRM_DEBUG("Dropping caches: 0x%08llx\n", val
);
4919 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4920 * on ioctls on -EAGAIN. */
4921 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4925 if (val
& DROP_ACTIVE
) {
4926 ret
= i915_gem_wait_for_idle(dev_priv
);
4931 if (val
& (DROP_RETIRE
| DROP_ACTIVE
))
4932 i915_gem_retire_requests(dev_priv
);
4934 if (val
& DROP_BOUND
)
4935 i915_gem_shrink(dev_priv
, LONG_MAX
, I915_SHRINK_BOUND
);
4937 if (val
& DROP_UNBOUND
)
4938 i915_gem_shrink(dev_priv
, LONG_MAX
, I915_SHRINK_UNBOUND
);
4941 mutex_unlock(&dev
->struct_mutex
);
4946 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops
,
4947 i915_drop_caches_get
, i915_drop_caches_set
,
4951 i915_max_freq_get(void *data
, u64
*val
)
4953 struct drm_device
*dev
= data
;
4954 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4957 if (INTEL_INFO(dev
)->gen
< 6)
4960 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4962 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4966 *val
= intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq_softlimit
);
4967 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4973 i915_max_freq_set(void *data
, u64 val
)
4975 struct drm_device
*dev
= data
;
4976 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4980 if (INTEL_INFO(dev
)->gen
< 6)
4983 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4985 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val
);
4987 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4992 * Turbo will still be enabled, but won't go above the set value.
4994 val
= intel_freq_opcode(dev_priv
, val
);
4996 hw_max
= dev_priv
->rps
.max_freq
;
4997 hw_min
= dev_priv
->rps
.min_freq
;
4999 if (val
< hw_min
|| val
> hw_max
|| val
< dev_priv
->rps
.min_freq_softlimit
) {
5000 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5004 dev_priv
->rps
.max_freq_softlimit
= val
;
5006 intel_set_rps(dev_priv
, val
);
5008 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5013 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops
,
5014 i915_max_freq_get
, i915_max_freq_set
,
5018 i915_min_freq_get(void *data
, u64
*val
)
5020 struct drm_device
*dev
= data
;
5021 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5024 if (INTEL_INFO(dev
)->gen
< 6)
5027 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
5029 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
5033 *val
= intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq_softlimit
);
5034 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5040 i915_min_freq_set(void *data
, u64 val
)
5042 struct drm_device
*dev
= data
;
5043 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5047 if (INTEL_INFO(dev
)->gen
< 6)
5050 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
5052 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val
);
5054 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
5059 * Turbo will still be enabled, but won't go below the set value.
5061 val
= intel_freq_opcode(dev_priv
, val
);
5063 hw_max
= dev_priv
->rps
.max_freq
;
5064 hw_min
= dev_priv
->rps
.min_freq
;
5066 if (val
< hw_min
|| val
> hw_max
|| val
> dev_priv
->rps
.max_freq_softlimit
) {
5067 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5071 dev_priv
->rps
.min_freq_softlimit
= val
;
5073 intel_set_rps(dev_priv
, val
);
5075 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5080 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops
,
5081 i915_min_freq_get
, i915_min_freq_set
,
5085 i915_cache_sharing_get(void *data
, u64
*val
)
5087 struct drm_device
*dev
= data
;
5088 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5092 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
5095 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
5098 intel_runtime_pm_get(dev_priv
);
5100 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
5102 intel_runtime_pm_put(dev_priv
);
5103 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
5105 *val
= (snpcr
& GEN6_MBC_SNPCR_MASK
) >> GEN6_MBC_SNPCR_SHIFT
;
5111 i915_cache_sharing_set(void *data
, u64 val
)
5113 struct drm_device
*dev
= data
;
5114 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5117 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
5123 intel_runtime_pm_get(dev_priv
);
5124 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val
);
5126 /* Update the cache sharing policy here as well */
5127 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
5128 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
5129 snpcr
|= (val
<< GEN6_MBC_SNPCR_SHIFT
);
5130 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
5132 intel_runtime_pm_put(dev_priv
);
5136 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops
,
5137 i915_cache_sharing_get
, i915_cache_sharing_set
,
5140 struct sseu_dev_status
{
5141 unsigned int slice_total
;
5142 unsigned int subslice_total
;
5143 unsigned int subslice_per_slice
;
5144 unsigned int eu_total
;
5145 unsigned int eu_per_subslice
;
5148 static void cherryview_sseu_device_status(struct drm_device
*dev
,
5149 struct sseu_dev_status
*stat
)
5151 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5154 u32 sig1
[ss_max
], sig2
[ss_max
];
5156 sig1
[0] = I915_READ(CHV_POWER_SS0_SIG1
);
5157 sig1
[1] = I915_READ(CHV_POWER_SS1_SIG1
);
5158 sig2
[0] = I915_READ(CHV_POWER_SS0_SIG2
);
5159 sig2
[1] = I915_READ(CHV_POWER_SS1_SIG2
);
5161 for (ss
= 0; ss
< ss_max
; ss
++) {
5162 unsigned int eu_cnt
;
5164 if (sig1
[ss
] & CHV_SS_PG_ENABLE
)
5165 /* skip disabled subslice */
5168 stat
->slice_total
= 1;
5169 stat
->subslice_per_slice
++;
5170 eu_cnt
= ((sig1
[ss
] & CHV_EU08_PG_ENABLE
) ? 0 : 2) +
5171 ((sig1
[ss
] & CHV_EU19_PG_ENABLE
) ? 0 : 2) +
5172 ((sig1
[ss
] & CHV_EU210_PG_ENABLE
) ? 0 : 2) +
5173 ((sig2
[ss
] & CHV_EU311_PG_ENABLE
) ? 0 : 2);
5174 stat
->eu_total
+= eu_cnt
;
5175 stat
->eu_per_subslice
= max(stat
->eu_per_subslice
, eu_cnt
);
5177 stat
->subslice_total
= stat
->subslice_per_slice
;
5180 static void gen9_sseu_device_status(struct drm_device
*dev
,
5181 struct sseu_dev_status
*stat
)
5183 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5184 int s_max
= 3, ss_max
= 4;
5186 u32 s_reg
[s_max
], eu_reg
[2*s_max
], eu_mask
[2];
5188 /* BXT has a single slice and at most 3 subslices. */
5189 if (IS_BROXTON(dev
)) {
5194 for (s
= 0; s
< s_max
; s
++) {
5195 s_reg
[s
] = I915_READ(GEN9_SLICE_PGCTL_ACK(s
));
5196 eu_reg
[2*s
] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s
));
5197 eu_reg
[2*s
+ 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s
));
5200 eu_mask
[0] = GEN9_PGCTL_SSA_EU08_ACK
|
5201 GEN9_PGCTL_SSA_EU19_ACK
|
5202 GEN9_PGCTL_SSA_EU210_ACK
|
5203 GEN9_PGCTL_SSA_EU311_ACK
;
5204 eu_mask
[1] = GEN9_PGCTL_SSB_EU08_ACK
|
5205 GEN9_PGCTL_SSB_EU19_ACK
|
5206 GEN9_PGCTL_SSB_EU210_ACK
|
5207 GEN9_PGCTL_SSB_EU311_ACK
;
5209 for (s
= 0; s
< s_max
; s
++) {
5210 unsigned int ss_cnt
= 0;
5212 if ((s_reg
[s
] & GEN9_PGCTL_SLICE_ACK
) == 0)
5213 /* skip disabled slice */
5216 stat
->slice_total
++;
5218 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
))
5219 ss_cnt
= INTEL_INFO(dev
)->subslice_per_slice
;
5221 for (ss
= 0; ss
< ss_max
; ss
++) {
5222 unsigned int eu_cnt
;
5224 if (IS_BROXTON(dev
) &&
5225 !(s_reg
[s
] & (GEN9_PGCTL_SS_ACK(ss
))))
5226 /* skip disabled subslice */
5229 if (IS_BROXTON(dev
))
5232 eu_cnt
= 2 * hweight32(eu_reg
[2*s
+ ss
/2] &
5234 stat
->eu_total
+= eu_cnt
;
5235 stat
->eu_per_subslice
= max(stat
->eu_per_subslice
,
5239 stat
->subslice_total
+= ss_cnt
;
5240 stat
->subslice_per_slice
= max(stat
->subslice_per_slice
,
5245 static void broadwell_sseu_device_status(struct drm_device
*dev
,
5246 struct sseu_dev_status
*stat
)
5248 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5250 u32 slice_info
= I915_READ(GEN8_GT_SLICE_INFO
);
5252 stat
->slice_total
= hweight32(slice_info
& GEN8_LSLICESTAT_MASK
);
5254 if (stat
->slice_total
) {
5255 stat
->subslice_per_slice
= INTEL_INFO(dev
)->subslice_per_slice
;
5256 stat
->subslice_total
= stat
->slice_total
*
5257 stat
->subslice_per_slice
;
5258 stat
->eu_per_subslice
= INTEL_INFO(dev
)->eu_per_subslice
;
5259 stat
->eu_total
= stat
->eu_per_subslice
* stat
->subslice_total
;
5261 /* subtract fused off EU(s) from enabled slice(s) */
5262 for (s
= 0; s
< stat
->slice_total
; s
++) {
5263 u8 subslice_7eu
= INTEL_INFO(dev
)->subslice_7eu
[s
];
5265 stat
->eu_total
-= hweight8(subslice_7eu
);
5270 static int i915_sseu_status(struct seq_file
*m
, void *unused
)
5272 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
5273 struct drm_device
*dev
= node
->minor
->dev
;
5274 struct sseu_dev_status stat
;
5276 if (INTEL_INFO(dev
)->gen
< 8)
5279 seq_puts(m
, "SSEU Device Info\n");
5280 seq_printf(m
, " Available Slice Total: %u\n",
5281 INTEL_INFO(dev
)->slice_total
);
5282 seq_printf(m
, " Available Subslice Total: %u\n",
5283 INTEL_INFO(dev
)->subslice_total
);
5284 seq_printf(m
, " Available Subslice Per Slice: %u\n",
5285 INTEL_INFO(dev
)->subslice_per_slice
);
5286 seq_printf(m
, " Available EU Total: %u\n",
5287 INTEL_INFO(dev
)->eu_total
);
5288 seq_printf(m
, " Available EU Per Subslice: %u\n",
5289 INTEL_INFO(dev
)->eu_per_subslice
);
5290 seq_printf(m
, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev
)));
5291 if (HAS_POOLED_EU(dev
))
5292 seq_printf(m
, " Min EU in pool: %u\n",
5293 INTEL_INFO(dev
)->min_eu_in_pool
);
5294 seq_printf(m
, " Has Slice Power Gating: %s\n",
5295 yesno(INTEL_INFO(dev
)->has_slice_pg
));
5296 seq_printf(m
, " Has Subslice Power Gating: %s\n",
5297 yesno(INTEL_INFO(dev
)->has_subslice_pg
));
5298 seq_printf(m
, " Has EU Power Gating: %s\n",
5299 yesno(INTEL_INFO(dev
)->has_eu_pg
));
5301 seq_puts(m
, "SSEU Device Status\n");
5302 memset(&stat
, 0, sizeof(stat
));
5303 if (IS_CHERRYVIEW(dev
)) {
5304 cherryview_sseu_device_status(dev
, &stat
);
5305 } else if (IS_BROADWELL(dev
)) {
5306 broadwell_sseu_device_status(dev
, &stat
);
5307 } else if (INTEL_INFO(dev
)->gen
>= 9) {
5308 gen9_sseu_device_status(dev
, &stat
);
5310 seq_printf(m
, " Enabled Slice Total: %u\n",
5312 seq_printf(m
, " Enabled Subslice Total: %u\n",
5313 stat
.subslice_total
);
5314 seq_printf(m
, " Enabled Subslice Per Slice: %u\n",
5315 stat
.subslice_per_slice
);
5316 seq_printf(m
, " Enabled EU Total: %u\n",
5318 seq_printf(m
, " Enabled EU Per Subslice: %u\n",
5319 stat
.eu_per_subslice
);
5324 static int i915_forcewake_open(struct inode
*inode
, struct file
*file
)
5326 struct drm_device
*dev
= inode
->i_private
;
5327 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5329 if (INTEL_INFO(dev
)->gen
< 6)
5332 intel_runtime_pm_get(dev_priv
);
5333 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5338 static int i915_forcewake_release(struct inode
*inode
, struct file
*file
)
5340 struct drm_device
*dev
= inode
->i_private
;
5341 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5343 if (INTEL_INFO(dev
)->gen
< 6)
5346 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5347 intel_runtime_pm_put(dev_priv
);
5352 static const struct file_operations i915_forcewake_fops
= {
5353 .owner
= THIS_MODULE
,
5354 .open
= i915_forcewake_open
,
5355 .release
= i915_forcewake_release
,
5358 static int i915_forcewake_create(struct dentry
*root
, struct drm_minor
*minor
)
5360 struct drm_device
*dev
= minor
->dev
;
5363 ent
= debugfs_create_file("i915_forcewake_user",
5366 &i915_forcewake_fops
);
5370 return drm_add_fake_info_node(minor
, ent
, &i915_forcewake_fops
);
5373 static int i915_debugfs_create(struct dentry
*root
,
5374 struct drm_minor
*minor
,
5376 const struct file_operations
*fops
)
5378 struct drm_device
*dev
= minor
->dev
;
5381 ent
= debugfs_create_file(name
,
5388 return drm_add_fake_info_node(minor
, ent
, fops
);
5391 static const struct drm_info_list i915_debugfs_list
[] = {
5392 {"i915_capabilities", i915_capabilities
, 0},
5393 {"i915_gem_objects", i915_gem_object_info
, 0},
5394 {"i915_gem_gtt", i915_gem_gtt_info
, 0},
5395 {"i915_gem_pinned", i915_gem_gtt_info
, 0, (void *) PINNED_LIST
},
5396 {"i915_gem_active", i915_gem_object_list_info
, 0, (void *) ACTIVE_LIST
},
5397 {"i915_gem_inactive", i915_gem_object_list_info
, 0, (void *) INACTIVE_LIST
},
5398 {"i915_gem_stolen", i915_gem_stolen_list_info
},
5399 {"i915_gem_pageflip", i915_gem_pageflip_info
, 0},
5400 {"i915_gem_request", i915_gem_request_info
, 0},
5401 {"i915_gem_seqno", i915_gem_seqno_info
, 0},
5402 {"i915_gem_fence_regs", i915_gem_fence_regs_info
, 0},
5403 {"i915_gem_interrupt", i915_interrupt_info
, 0},
5404 {"i915_gem_hws", i915_hws_info
, 0, (void *)RCS
},
5405 {"i915_gem_hws_blt", i915_hws_info
, 0, (void *)BCS
},
5406 {"i915_gem_hws_bsd", i915_hws_info
, 0, (void *)VCS
},
5407 {"i915_gem_hws_vebox", i915_hws_info
, 0, (void *)VECS
},
5408 {"i915_gem_batch_pool", i915_gem_batch_pool_info
, 0},
5409 {"i915_guc_info", i915_guc_info
, 0},
5410 {"i915_guc_load_status", i915_guc_load_status_info
, 0},
5411 {"i915_guc_log_dump", i915_guc_log_dump
, 0},
5412 {"i915_frequency_info", i915_frequency_info
, 0},
5413 {"i915_hangcheck_info", i915_hangcheck_info
, 0},
5414 {"i915_drpc_info", i915_drpc_info
, 0},
5415 {"i915_emon_status", i915_emon_status
, 0},
5416 {"i915_ring_freq_table", i915_ring_freq_table
, 0},
5417 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking
, 0},
5418 {"i915_fbc_status", i915_fbc_status
, 0},
5419 {"i915_ips_status", i915_ips_status
, 0},
5420 {"i915_sr_status", i915_sr_status
, 0},
5421 {"i915_opregion", i915_opregion
, 0},
5422 {"i915_vbt", i915_vbt
, 0},
5423 {"i915_gem_framebuffer", i915_gem_framebuffer_info
, 0},
5424 {"i915_context_status", i915_context_status
, 0},
5425 {"i915_dump_lrc", i915_dump_lrc
, 0},
5426 {"i915_execlists", i915_execlists
, 0},
5427 {"i915_forcewake_domains", i915_forcewake_domains
, 0},
5428 {"i915_swizzle_info", i915_swizzle_info
, 0},
5429 {"i915_ppgtt_info", i915_ppgtt_info
, 0},
5430 {"i915_llc", i915_llc
, 0},
5431 {"i915_edp_psr_status", i915_edp_psr_status
, 0},
5432 {"i915_sink_crc_eDP1", i915_sink_crc
, 0},
5433 {"i915_energy_uJ", i915_energy_uJ
, 0},
5434 {"i915_runtime_pm_status", i915_runtime_pm_status
, 0},
5435 {"i915_power_domain_info", i915_power_domain_info
, 0},
5436 {"i915_dmc_info", i915_dmc_info
, 0},
5437 {"i915_display_info", i915_display_info
, 0},
5438 {"i915_semaphore_status", i915_semaphore_status
, 0},
5439 {"i915_shared_dplls_info", i915_shared_dplls_info
, 0},
5440 {"i915_dp_mst_info", i915_dp_mst_info
, 0},
5441 {"i915_wa_registers", i915_wa_registers
, 0},
5442 {"i915_ddb_info", i915_ddb_info
, 0},
5443 {"i915_sseu_status", i915_sseu_status
, 0},
5444 {"i915_drrs_status", i915_drrs_status
, 0},
5445 {"i915_rps_boost_info", i915_rps_boost_info
, 0},
5447 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5449 static const struct i915_debugfs_files
{
5451 const struct file_operations
*fops
;
5452 } i915_debugfs_files
[] = {
5453 {"i915_wedged", &i915_wedged_fops
},
5454 {"i915_max_freq", &i915_max_freq_fops
},
5455 {"i915_min_freq", &i915_min_freq_fops
},
5456 {"i915_cache_sharing", &i915_cache_sharing_fops
},
5457 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops
},
5458 {"i915_ring_test_irq", &i915_ring_test_irq_fops
},
5459 {"i915_gem_drop_caches", &i915_drop_caches_fops
},
5460 {"i915_error_state", &i915_error_state_fops
},
5461 {"i915_next_seqno", &i915_next_seqno_fops
},
5462 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops
},
5463 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops
},
5464 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops
},
5465 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops
},
5466 {"i915_fbc_false_color", &i915_fbc_fc_fops
},
5467 {"i915_dp_test_data", &i915_displayport_test_data_fops
},
5468 {"i915_dp_test_type", &i915_displayport_test_type_fops
},
5469 {"i915_dp_test_active", &i915_displayport_test_active_fops
}
5472 void intel_display_crc_init(struct drm_device
*dev
)
5474 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5477 for_each_pipe(dev_priv
, pipe
) {
5478 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
5480 pipe_crc
->opened
= false;
5481 spin_lock_init(&pipe_crc
->lock
);
5482 init_waitqueue_head(&pipe_crc
->wq
);
5486 int i915_debugfs_register(struct drm_i915_private
*dev_priv
)
5488 struct drm_minor
*minor
= dev_priv
->drm
.primary
;
5491 ret
= i915_forcewake_create(minor
->debugfs_root
, minor
);
5495 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
5496 ret
= i915_pipe_crc_create(minor
->debugfs_root
, minor
, i
);
5501 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
5502 ret
= i915_debugfs_create(minor
->debugfs_root
, minor
,
5503 i915_debugfs_files
[i
].name
,
5504 i915_debugfs_files
[i
].fops
);
5509 return drm_debugfs_create_files(i915_debugfs_list
,
5510 I915_DEBUGFS_ENTRIES
,
5511 minor
->debugfs_root
, minor
);
5514 void i915_debugfs_unregister(struct drm_i915_private
*dev_priv
)
5516 struct drm_minor
*minor
= dev_priv
->drm
.primary
;
5519 drm_debugfs_remove_files(i915_debugfs_list
,
5520 I915_DEBUGFS_ENTRIES
, minor
);
5522 drm_debugfs_remove_files((struct drm_info_list
*) &i915_forcewake_fops
,
5525 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
5526 struct drm_info_list
*info_list
=
5527 (struct drm_info_list
*)&i915_pipe_crc_data
[i
];
5529 drm_debugfs_remove_files(info_list
, 1, minor
);
5532 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
5533 struct drm_info_list
*info_list
=
5534 (struct drm_info_list
*) i915_debugfs_files
[i
].fops
;
5536 drm_debugfs_remove_files(info_list
, 1, minor
);
5541 /* DPCD dump start address. */
5542 unsigned int offset
;
5543 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5545 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5547 /* Only valid for eDP. */
5551 static const struct dpcd_block i915_dpcd_debug
[] = {
5552 { .offset
= DP_DPCD_REV
, .size
= DP_RECEIVER_CAP_SIZE
},
5553 { .offset
= DP_PSR_SUPPORT
, .end
= DP_PSR_CAPS
},
5554 { .offset
= DP_DOWNSTREAM_PORT_0
, .size
= 16 },
5555 { .offset
= DP_LINK_BW_SET
, .end
= DP_EDP_CONFIGURATION_SET
},
5556 { .offset
= DP_SINK_COUNT
, .end
= DP_ADJUST_REQUEST_LANE2_3
},
5557 { .offset
= DP_SET_POWER
},
5558 { .offset
= DP_EDP_DPCD_REV
},
5559 { .offset
= DP_EDP_GENERAL_CAP_1
, .end
= DP_EDP_GENERAL_CAP_3
},
5560 { .offset
= DP_EDP_DISPLAY_CONTROL_REGISTER
, .end
= DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB
},
5561 { .offset
= DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET
, .end
= DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET
},
5564 static int i915_dpcd_show(struct seq_file
*m
, void *data
)
5566 struct drm_connector
*connector
= m
->private;
5567 struct intel_dp
*intel_dp
=
5568 enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
5573 if (connector
->status
!= connector_status_connected
)
5576 for (i
= 0; i
< ARRAY_SIZE(i915_dpcd_debug
); i
++) {
5577 const struct dpcd_block
*b
= &i915_dpcd_debug
[i
];
5578 size_t size
= b
->end
? b
->end
- b
->offset
+ 1 : (b
->size
?: 1);
5581 connector
->connector_type
!= DRM_MODE_CONNECTOR_eDP
)
5584 /* low tech for now */
5585 if (WARN_ON(size
> sizeof(buf
)))
5588 err
= drm_dp_dpcd_read(&intel_dp
->aux
, b
->offset
, buf
, size
);
5590 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5591 size
, b
->offset
, err
);
5595 seq_printf(m
, "%04x: %*ph\n", b
->offset
, (int) size
, buf
);
5601 static int i915_dpcd_open(struct inode
*inode
, struct file
*file
)
5603 return single_open(file
, i915_dpcd_show
, inode
->i_private
);
5606 static const struct file_operations i915_dpcd_fops
= {
5607 .owner
= THIS_MODULE
,
5608 .open
= i915_dpcd_open
,
5610 .llseek
= seq_lseek
,
5611 .release
= single_release
,
5615 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5616 * @connector: pointer to a registered drm_connector
5618 * Cleanup will be done by drm_connector_unregister() through a call to
5619 * drm_debugfs_connector_remove().
5621 * Returns 0 on success, negative error codes on error.
5623 int i915_debugfs_connector_add(struct drm_connector
*connector
)
5625 struct dentry
*root
= connector
->debugfs_entry
;
5627 /* The connector must have been registered beforehands. */
5631 if (connector
->connector_type
== DRM_MODE_CONNECTOR_DisplayPort
||
5632 connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
5633 debugfs_create_file("i915_dpcd", S_IRUGO
, root
, connector
,