2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
49 static const char *yesno(int v
)
51 return v
? "yes" : "no";
54 /* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
57 drm_add_fake_info_node(struct drm_minor
*minor
,
61 struct drm_info_node
*node
;
63 node
= kmalloc(sizeof(*node
), GFP_KERNEL
);
71 node
->info_ent
= (void *) key
;
73 mutex_lock(&minor
->debugfs_lock
);
74 list_add(&node
->list
, &minor
->debugfs_list
);
75 mutex_unlock(&minor
->debugfs_lock
);
80 static int i915_capabilities(struct seq_file
*m
, void *data
)
82 struct drm_info_node
*node
= m
->private;
83 struct drm_device
*dev
= node
->minor
->dev
;
84 const struct intel_device_info
*info
= INTEL_INFO(dev
);
86 seq_printf(m
, "gen: %d\n", info
->gen
);
87 seq_printf(m
, "pch: %d\n", INTEL_PCH_TYPE(dev
));
88 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89 #define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG
, SEP_SEMICOLON
);
97 static const char *get_pin_flag(struct drm_i915_gem_object
*obj
)
99 if (i915_gem_obj_is_pinned(obj
))
105 static const char *get_tiling_flag(struct drm_i915_gem_object
*obj
)
107 switch (obj
->tiling_mode
) {
109 case I915_TILING_NONE
: return " ";
110 case I915_TILING_X
: return "X";
111 case I915_TILING_Y
: return "Y";
115 static inline const char *get_global_flag(struct drm_i915_gem_object
*obj
)
117 return i915_gem_obj_to_ggtt(obj
) ? "g" : " ";
121 describe_obj(struct seq_file
*m
, struct drm_i915_gem_object
*obj
)
123 struct i915_vma
*vma
;
126 seq_printf(m
, "%pK: %s%s%s %8zdKiB %02x %02x %x %x %x%s%s%s",
129 get_tiling_flag(obj
),
130 get_global_flag(obj
),
131 obj
->base
.size
/ 1024,
132 obj
->base
.read_domains
,
133 obj
->base
.write_domain
,
134 i915_gem_request_get_seqno(obj
->last_read_req
),
135 i915_gem_request_get_seqno(obj
->last_write_req
),
136 i915_gem_request_get_seqno(obj
->last_fenced_req
),
137 i915_cache_level_str(to_i915(obj
->base
.dev
), obj
->cache_level
),
138 obj
->dirty
? " dirty" : "",
139 obj
->madv
== I915_MADV_DONTNEED
? " purgeable" : "");
141 seq_printf(m
, " (name: %d)", obj
->base
.name
);
142 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
143 if (vma
->pin_count
> 0)
146 seq_printf(m
, " (pinned x %d)", pin_count
);
147 if (obj
->pin_display
)
148 seq_printf(m
, " (display)");
149 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
)
150 seq_printf(m
, " (fence: %d)", obj
->fence_reg
);
151 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
152 if (!i915_is_ggtt(vma
->vm
))
156 seq_printf(m
, "gtt offset: %08llx, size: %08llx, type: %u)",
157 vma
->node
.start
, vma
->node
.size
,
158 vma
->ggtt_view
.type
);
161 seq_printf(m
, " (stolen: %08llx)", obj
->stolen
->start
);
162 if (obj
->pin_mappable
|| obj
->fault_mappable
) {
164 if (obj
->pin_mappable
)
166 if (obj
->fault_mappable
)
169 seq_printf(m
, " (%s mappable)", s
);
171 if (obj
->last_read_req
!= NULL
)
172 seq_printf(m
, " (%s)",
173 i915_gem_request_get_ring(obj
->last_read_req
)->name
);
174 if (obj
->frontbuffer_bits
)
175 seq_printf(m
, " (frontbuffer: 0x%03x)", obj
->frontbuffer_bits
);
178 static void describe_ctx(struct seq_file
*m
, struct intel_context
*ctx
)
180 seq_putc(m
, ctx
->legacy_hw_ctx
.initialized
? 'I' : 'i');
181 seq_putc(m
, ctx
->remap_slice
? 'R' : 'r');
185 static int i915_gem_object_list_info(struct seq_file
*m
, void *data
)
187 struct drm_info_node
*node
= m
->private;
188 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
189 struct list_head
*head
;
190 struct drm_device
*dev
= node
->minor
->dev
;
191 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
192 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
193 struct i915_vma
*vma
;
194 size_t total_obj_size
, total_gtt_size
;
197 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
201 /* FIXME: the user of this interface might want more than just GGTT */
204 seq_puts(m
, "Active:\n");
205 head
= &vm
->active_list
;
208 seq_puts(m
, "Inactive:\n");
209 head
= &vm
->inactive_list
;
212 mutex_unlock(&dev
->struct_mutex
);
216 total_obj_size
= total_gtt_size
= count
= 0;
217 list_for_each_entry(vma
, head
, mm_list
) {
219 describe_obj(m
, vma
->obj
);
221 total_obj_size
+= vma
->obj
->base
.size
;
222 total_gtt_size
+= vma
->node
.size
;
225 mutex_unlock(&dev
->struct_mutex
);
227 seq_printf(m
, "Total %d objects, %zu bytes, %zu GTT size\n",
228 count
, total_obj_size
, total_gtt_size
);
232 static int obj_rank_by_stolen(void *priv
,
233 struct list_head
*A
, struct list_head
*B
)
235 struct drm_i915_gem_object
*a
=
236 container_of(A
, struct drm_i915_gem_object
, obj_exec_link
);
237 struct drm_i915_gem_object
*b
=
238 container_of(B
, struct drm_i915_gem_object
, obj_exec_link
);
240 return a
->stolen
->start
- b
->stolen
->start
;
243 static int i915_gem_stolen_list_info(struct seq_file
*m
, void *data
)
245 struct drm_info_node
*node
= m
->private;
246 struct drm_device
*dev
= node
->minor
->dev
;
247 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
248 struct drm_i915_gem_object
*obj
;
249 size_t total_obj_size
, total_gtt_size
;
253 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
257 total_obj_size
= total_gtt_size
= count
= 0;
258 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
259 if (obj
->stolen
== NULL
)
262 list_add(&obj
->obj_exec_link
, &stolen
);
264 total_obj_size
+= obj
->base
.size
;
265 total_gtt_size
+= i915_gem_obj_ggtt_size(obj
);
268 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
269 if (obj
->stolen
== NULL
)
272 list_add(&obj
->obj_exec_link
, &stolen
);
274 total_obj_size
+= obj
->base
.size
;
277 list_sort(NULL
, &stolen
, obj_rank_by_stolen
);
278 seq_puts(m
, "Stolen:\n");
279 while (!list_empty(&stolen
)) {
280 obj
= list_first_entry(&stolen
, typeof(*obj
), obj_exec_link
);
282 describe_obj(m
, obj
);
284 list_del_init(&obj
->obj_exec_link
);
286 mutex_unlock(&dev
->struct_mutex
);
288 seq_printf(m
, "Total %d objects, %zu bytes, %zu GTT size\n",
289 count
, total_obj_size
, total_gtt_size
);
293 #define count_objects(list, member) do { \
294 list_for_each_entry(obj, list, member) { \
295 size += i915_gem_obj_ggtt_size(obj); \
297 if (obj->map_and_fenceable) { \
298 mappable_size += i915_gem_obj_ggtt_size(obj); \
305 struct drm_i915_file_private
*file_priv
;
307 size_t total
, unbound
;
308 size_t global
, shared
;
309 size_t active
, inactive
;
312 static int per_file_stats(int id
, void *ptr
, void *data
)
314 struct drm_i915_gem_object
*obj
= ptr
;
315 struct file_stats
*stats
= data
;
316 struct i915_vma
*vma
;
319 stats
->total
+= obj
->base
.size
;
321 if (obj
->base
.name
|| obj
->base
.dma_buf
)
322 stats
->shared
+= obj
->base
.size
;
324 if (USES_FULL_PPGTT(obj
->base
.dev
)) {
325 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
326 struct i915_hw_ppgtt
*ppgtt
;
328 if (!drm_mm_node_allocated(&vma
->node
))
331 if (i915_is_ggtt(vma
->vm
)) {
332 stats
->global
+= obj
->base
.size
;
336 ppgtt
= container_of(vma
->vm
, struct i915_hw_ppgtt
, base
);
337 if (ppgtt
->file_priv
!= stats
->file_priv
)
340 if (obj
->active
) /* XXX per-vma statistic */
341 stats
->active
+= obj
->base
.size
;
343 stats
->inactive
+= obj
->base
.size
;
348 if (i915_gem_obj_ggtt_bound(obj
)) {
349 stats
->global
+= obj
->base
.size
;
351 stats
->active
+= obj
->base
.size
;
353 stats
->inactive
+= obj
->base
.size
;
358 if (!list_empty(&obj
->global_list
))
359 stats
->unbound
+= obj
->base
.size
;
364 #define print_file_stats(m, name, stats) \
365 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n", \
375 static void print_batch_pool_stats(struct seq_file
*m
,
376 struct drm_i915_private
*dev_priv
)
378 struct drm_i915_gem_object
*obj
;
379 struct file_stats stats
;
381 memset(&stats
, 0, sizeof(stats
));
383 list_for_each_entry(obj
,
384 &dev_priv
->mm
.batch_pool
.cache_list
,
386 per_file_stats(0, obj
, &stats
);
388 print_file_stats(m
, "batch pool", stats
);
391 #define count_vmas(list, member) do { \
392 list_for_each_entry(vma, list, member) { \
393 size += i915_gem_obj_ggtt_size(vma->obj); \
395 if (vma->obj->map_and_fenceable) { \
396 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
402 static int i915_gem_object_info(struct seq_file
*m
, void* data
)
404 struct drm_info_node
*node
= m
->private;
405 struct drm_device
*dev
= node
->minor
->dev
;
406 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
407 u32 count
, mappable_count
, purgeable_count
;
408 size_t size
, mappable_size
, purgeable_size
;
409 struct drm_i915_gem_object
*obj
;
410 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
411 struct drm_file
*file
;
412 struct i915_vma
*vma
;
415 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
419 seq_printf(m
, "%u objects, %zu bytes\n",
420 dev_priv
->mm
.object_count
,
421 dev_priv
->mm
.object_memory
);
423 size
= count
= mappable_size
= mappable_count
= 0;
424 count_objects(&dev_priv
->mm
.bound_list
, global_list
);
425 seq_printf(m
, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
426 count
, mappable_count
, size
, mappable_size
);
428 size
= count
= mappable_size
= mappable_count
= 0;
429 count_vmas(&vm
->active_list
, mm_list
);
430 seq_printf(m
, " %u [%u] active objects, %zu [%zu] bytes\n",
431 count
, mappable_count
, size
, mappable_size
);
433 size
= count
= mappable_size
= mappable_count
= 0;
434 count_vmas(&vm
->inactive_list
, mm_list
);
435 seq_printf(m
, " %u [%u] inactive objects, %zu [%zu] bytes\n",
436 count
, mappable_count
, size
, mappable_size
);
438 size
= count
= purgeable_size
= purgeable_count
= 0;
439 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
440 size
+= obj
->base
.size
, ++count
;
441 if (obj
->madv
== I915_MADV_DONTNEED
)
442 purgeable_size
+= obj
->base
.size
, ++purgeable_count
;
444 seq_printf(m
, "%u unbound objects, %zu bytes\n", count
, size
);
446 size
= count
= mappable_size
= mappable_count
= 0;
447 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
448 if (obj
->fault_mappable
) {
449 size
+= i915_gem_obj_ggtt_size(obj
);
452 if (obj
->pin_mappable
) {
453 mappable_size
+= i915_gem_obj_ggtt_size(obj
);
456 if (obj
->madv
== I915_MADV_DONTNEED
) {
457 purgeable_size
+= obj
->base
.size
;
461 seq_printf(m
, "%u purgeable objects, %zu bytes\n",
462 purgeable_count
, purgeable_size
);
463 seq_printf(m
, "%u pinned mappable objects, %zu bytes\n",
464 mappable_count
, mappable_size
);
465 seq_printf(m
, "%u fault mappable objects, %zu bytes\n",
468 seq_printf(m
, "%zu [%lu] gtt total\n",
469 dev_priv
->gtt
.base
.total
,
470 dev_priv
->gtt
.mappable_end
- dev_priv
->gtt
.base
.start
);
473 print_batch_pool_stats(m
, dev_priv
);
476 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
477 struct file_stats stats
;
478 struct task_struct
*task
;
480 memset(&stats
, 0, sizeof(stats
));
481 stats
.file_priv
= file
->driver_priv
;
482 spin_lock(&file
->table_lock
);
483 idr_for_each(&file
->object_idr
, per_file_stats
, &stats
);
484 spin_unlock(&file
->table_lock
);
486 * Although we have a valid reference on file->pid, that does
487 * not guarantee that the task_struct who called get_pid() is
488 * still alive (e.g. get_pid(current) => fork() => exit()).
489 * Therefore, we need to protect this ->comm access using RCU.
492 task
= pid_task(file
->pid
, PIDTYPE_PID
);
493 print_file_stats(m
, task
? task
->comm
: "<unknown>", stats
);
497 mutex_unlock(&dev
->struct_mutex
);
502 static int i915_gem_gtt_info(struct seq_file
*m
, void *data
)
504 struct drm_info_node
*node
= m
->private;
505 struct drm_device
*dev
= node
->minor
->dev
;
506 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
507 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
508 struct drm_i915_gem_object
*obj
;
509 size_t total_obj_size
, total_gtt_size
;
512 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
516 total_obj_size
= total_gtt_size
= count
= 0;
517 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
518 if (list
== PINNED_LIST
&& !i915_gem_obj_is_pinned(obj
))
522 describe_obj(m
, obj
);
524 total_obj_size
+= obj
->base
.size
;
525 total_gtt_size
+= i915_gem_obj_ggtt_size(obj
);
529 mutex_unlock(&dev
->struct_mutex
);
531 seq_printf(m
, "Total %d objects, %zu bytes, %zu GTT size\n",
532 count
, total_obj_size
, total_gtt_size
);
537 static int i915_gem_pageflip_info(struct seq_file
*m
, void *data
)
539 struct drm_info_node
*node
= m
->private;
540 struct drm_device
*dev
= node
->minor
->dev
;
541 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
542 struct intel_crtc
*crtc
;
545 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
549 for_each_intel_crtc(dev
, crtc
) {
550 const char pipe
= pipe_name(crtc
->pipe
);
551 const char plane
= plane_name(crtc
->plane
);
552 struct intel_unpin_work
*work
;
554 spin_lock_irq(&dev
->event_lock
);
555 work
= crtc
->unpin_work
;
557 seq_printf(m
, "No flip due on pipe %c (plane %c)\n",
562 if (atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
563 seq_printf(m
, "Flip queued on pipe %c (plane %c)\n",
566 seq_printf(m
, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
569 if (work
->flip_queued_req
) {
570 struct intel_engine_cs
*ring
=
571 i915_gem_request_get_ring(work
->flip_queued_req
);
573 seq_printf(m
, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
575 i915_gem_request_get_seqno(work
->flip_queued_req
),
576 dev_priv
->next_seqno
,
577 ring
->get_seqno(ring
, true),
578 i915_gem_request_completed(work
->flip_queued_req
, true));
580 seq_printf(m
, "Flip not associated with any ring\n");
581 seq_printf(m
, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
582 work
->flip_queued_vblank
,
583 work
->flip_ready_vblank
,
584 drm_crtc_vblank_count(&crtc
->base
));
585 if (work
->enable_stall_check
)
586 seq_puts(m
, "Stall check enabled, ");
588 seq_puts(m
, "Stall check waiting for page flip ioctl, ");
589 seq_printf(m
, "%d prepares\n", atomic_read(&work
->pending
));
591 if (INTEL_INFO(dev
)->gen
>= 4)
592 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(crtc
->plane
)));
594 addr
= I915_READ(DSPADDR(crtc
->plane
));
595 seq_printf(m
, "Current scanout address 0x%08x\n", addr
);
597 if (work
->pending_flip_obj
) {
598 seq_printf(m
, "New framebuffer address 0x%08lx\n", (long)work
->gtt_offset
);
599 seq_printf(m
, "MMIO update completed? %d\n", addr
== work
->gtt_offset
);
602 spin_unlock_irq(&dev
->event_lock
);
605 mutex_unlock(&dev
->struct_mutex
);
610 static int i915_gem_batch_pool_info(struct seq_file
*m
, void *data
)
612 struct drm_info_node
*node
= m
->private;
613 struct drm_device
*dev
= node
->minor
->dev
;
614 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
615 struct drm_i915_gem_object
*obj
;
619 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
623 seq_puts(m
, "cache:\n");
624 list_for_each_entry(obj
,
625 &dev_priv
->mm
.batch_pool
.cache_list
,
628 describe_obj(m
, obj
);
633 seq_printf(m
, "total: %d\n", count
);
635 mutex_unlock(&dev
->struct_mutex
);
640 static int i915_gem_request_info(struct seq_file
*m
, void *data
)
642 struct drm_info_node
*node
= m
->private;
643 struct drm_device
*dev
= node
->minor
->dev
;
644 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
645 struct intel_engine_cs
*ring
;
646 struct drm_i915_gem_request
*gem_request
;
649 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
654 for_each_ring(ring
, dev_priv
, i
) {
655 if (list_empty(&ring
->request_list
))
658 seq_printf(m
, "%s requests:\n", ring
->name
);
659 list_for_each_entry(gem_request
,
662 seq_printf(m
, " %x @ %d\n",
664 (int) (jiffies
- gem_request
->emitted_jiffies
));
668 mutex_unlock(&dev
->struct_mutex
);
671 seq_puts(m
, "No requests\n");
676 static void i915_ring_seqno_info(struct seq_file
*m
,
677 struct intel_engine_cs
*ring
)
679 if (ring
->get_seqno
) {
680 seq_printf(m
, "Current sequence (%s): %x\n",
681 ring
->name
, ring
->get_seqno(ring
, false));
685 static int i915_gem_seqno_info(struct seq_file
*m
, void *data
)
687 struct drm_info_node
*node
= m
->private;
688 struct drm_device
*dev
= node
->minor
->dev
;
689 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
690 struct intel_engine_cs
*ring
;
693 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
696 intel_runtime_pm_get(dev_priv
);
698 for_each_ring(ring
, dev_priv
, i
)
699 i915_ring_seqno_info(m
, ring
);
701 intel_runtime_pm_put(dev_priv
);
702 mutex_unlock(&dev
->struct_mutex
);
708 static int i915_interrupt_info(struct seq_file
*m
, void *data
)
710 struct drm_info_node
*node
= m
->private;
711 struct drm_device
*dev
= node
->minor
->dev
;
712 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
713 struct intel_engine_cs
*ring
;
716 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
719 intel_runtime_pm_get(dev_priv
);
721 if (IS_CHERRYVIEW(dev
)) {
722 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
723 I915_READ(GEN8_MASTER_IRQ
));
725 seq_printf(m
, "Display IER:\t%08x\n",
727 seq_printf(m
, "Display IIR:\t%08x\n",
729 seq_printf(m
, "Display IIR_RW:\t%08x\n",
730 I915_READ(VLV_IIR_RW
));
731 seq_printf(m
, "Display IMR:\t%08x\n",
733 for_each_pipe(dev_priv
, pipe
)
734 seq_printf(m
, "Pipe %c stat:\t%08x\n",
736 I915_READ(PIPESTAT(pipe
)));
738 seq_printf(m
, "Port hotplug:\t%08x\n",
739 I915_READ(PORT_HOTPLUG_EN
));
740 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
741 I915_READ(VLV_DPFLIPSTAT
));
742 seq_printf(m
, "DPINVGTT:\t%08x\n",
743 I915_READ(DPINVGTT
));
745 for (i
= 0; i
< 4; i
++) {
746 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
747 i
, I915_READ(GEN8_GT_IMR(i
)));
748 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
749 i
, I915_READ(GEN8_GT_IIR(i
)));
750 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
751 i
, I915_READ(GEN8_GT_IER(i
)));
754 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
755 I915_READ(GEN8_PCU_IMR
));
756 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
757 I915_READ(GEN8_PCU_IIR
));
758 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
759 I915_READ(GEN8_PCU_IER
));
760 } else if (INTEL_INFO(dev
)->gen
>= 8) {
761 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
762 I915_READ(GEN8_MASTER_IRQ
));
764 for (i
= 0; i
< 4; i
++) {
765 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
766 i
, I915_READ(GEN8_GT_IMR(i
)));
767 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
768 i
, I915_READ(GEN8_GT_IIR(i
)));
769 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
770 i
, I915_READ(GEN8_GT_IER(i
)));
773 for_each_pipe(dev_priv
, pipe
) {
774 if (!intel_display_power_is_enabled(dev_priv
,
775 POWER_DOMAIN_PIPE(pipe
))) {
776 seq_printf(m
, "Pipe %c power disabled\n",
780 seq_printf(m
, "Pipe %c IMR:\t%08x\n",
782 I915_READ(GEN8_DE_PIPE_IMR(pipe
)));
783 seq_printf(m
, "Pipe %c IIR:\t%08x\n",
785 I915_READ(GEN8_DE_PIPE_IIR(pipe
)));
786 seq_printf(m
, "Pipe %c IER:\t%08x\n",
788 I915_READ(GEN8_DE_PIPE_IER(pipe
)));
791 seq_printf(m
, "Display Engine port interrupt mask:\t%08x\n",
792 I915_READ(GEN8_DE_PORT_IMR
));
793 seq_printf(m
, "Display Engine port interrupt identity:\t%08x\n",
794 I915_READ(GEN8_DE_PORT_IIR
));
795 seq_printf(m
, "Display Engine port interrupt enable:\t%08x\n",
796 I915_READ(GEN8_DE_PORT_IER
));
798 seq_printf(m
, "Display Engine misc interrupt mask:\t%08x\n",
799 I915_READ(GEN8_DE_MISC_IMR
));
800 seq_printf(m
, "Display Engine misc interrupt identity:\t%08x\n",
801 I915_READ(GEN8_DE_MISC_IIR
));
802 seq_printf(m
, "Display Engine misc interrupt enable:\t%08x\n",
803 I915_READ(GEN8_DE_MISC_IER
));
805 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
806 I915_READ(GEN8_PCU_IMR
));
807 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
808 I915_READ(GEN8_PCU_IIR
));
809 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
810 I915_READ(GEN8_PCU_IER
));
811 } else if (IS_VALLEYVIEW(dev
)) {
812 seq_printf(m
, "Display IER:\t%08x\n",
814 seq_printf(m
, "Display IIR:\t%08x\n",
816 seq_printf(m
, "Display IIR_RW:\t%08x\n",
817 I915_READ(VLV_IIR_RW
));
818 seq_printf(m
, "Display IMR:\t%08x\n",
820 for_each_pipe(dev_priv
, pipe
)
821 seq_printf(m
, "Pipe %c stat:\t%08x\n",
823 I915_READ(PIPESTAT(pipe
)));
825 seq_printf(m
, "Master IER:\t%08x\n",
826 I915_READ(VLV_MASTER_IER
));
828 seq_printf(m
, "Render IER:\t%08x\n",
830 seq_printf(m
, "Render IIR:\t%08x\n",
832 seq_printf(m
, "Render IMR:\t%08x\n",
835 seq_printf(m
, "PM IER:\t\t%08x\n",
836 I915_READ(GEN6_PMIER
));
837 seq_printf(m
, "PM IIR:\t\t%08x\n",
838 I915_READ(GEN6_PMIIR
));
839 seq_printf(m
, "PM IMR:\t\t%08x\n",
840 I915_READ(GEN6_PMIMR
));
842 seq_printf(m
, "Port hotplug:\t%08x\n",
843 I915_READ(PORT_HOTPLUG_EN
));
844 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
845 I915_READ(VLV_DPFLIPSTAT
));
846 seq_printf(m
, "DPINVGTT:\t%08x\n",
847 I915_READ(DPINVGTT
));
849 } else if (!HAS_PCH_SPLIT(dev
)) {
850 seq_printf(m
, "Interrupt enable: %08x\n",
852 seq_printf(m
, "Interrupt identity: %08x\n",
854 seq_printf(m
, "Interrupt mask: %08x\n",
856 for_each_pipe(dev_priv
, pipe
)
857 seq_printf(m
, "Pipe %c stat: %08x\n",
859 I915_READ(PIPESTAT(pipe
)));
861 seq_printf(m
, "North Display Interrupt enable: %08x\n",
863 seq_printf(m
, "North Display Interrupt identity: %08x\n",
865 seq_printf(m
, "North Display Interrupt mask: %08x\n",
867 seq_printf(m
, "South Display Interrupt enable: %08x\n",
869 seq_printf(m
, "South Display Interrupt identity: %08x\n",
871 seq_printf(m
, "South Display Interrupt mask: %08x\n",
873 seq_printf(m
, "Graphics Interrupt enable: %08x\n",
875 seq_printf(m
, "Graphics Interrupt identity: %08x\n",
877 seq_printf(m
, "Graphics Interrupt mask: %08x\n",
880 for_each_ring(ring
, dev_priv
, i
) {
881 if (INTEL_INFO(dev
)->gen
>= 6) {
883 "Graphics Interrupt mask (%s): %08x\n",
884 ring
->name
, I915_READ_IMR(ring
));
886 i915_ring_seqno_info(m
, ring
);
888 intel_runtime_pm_put(dev_priv
);
889 mutex_unlock(&dev
->struct_mutex
);
894 static int i915_gem_fence_regs_info(struct seq_file
*m
, void *data
)
896 struct drm_info_node
*node
= m
->private;
897 struct drm_device
*dev
= node
->minor
->dev
;
898 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
901 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
905 seq_printf(m
, "Reserved fences = %d\n", dev_priv
->fence_reg_start
);
906 seq_printf(m
, "Total fences = %d\n", dev_priv
->num_fence_regs
);
907 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
908 struct drm_i915_gem_object
*obj
= dev_priv
->fence_regs
[i
].obj
;
910 seq_printf(m
, "Fence %d, pin count = %d, object = ",
911 i
, dev_priv
->fence_regs
[i
].pin_count
);
913 seq_puts(m
, "unused");
915 describe_obj(m
, obj
);
919 mutex_unlock(&dev
->struct_mutex
);
923 static int i915_hws_info(struct seq_file
*m
, void *data
)
925 struct drm_info_node
*node
= m
->private;
926 struct drm_device
*dev
= node
->minor
->dev
;
927 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
928 struct intel_engine_cs
*ring
;
932 ring
= &dev_priv
->ring
[(uintptr_t)node
->info_ent
->data
];
933 hws
= ring
->status_page
.page_addr
;
937 for (i
= 0; i
< 4096 / sizeof(u32
) / 4; i
+= 4) {
938 seq_printf(m
, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
940 hws
[i
], hws
[i
+ 1], hws
[i
+ 2], hws
[i
+ 3]);
946 i915_error_state_write(struct file
*filp
,
947 const char __user
*ubuf
,
951 struct i915_error_state_file_priv
*error_priv
= filp
->private_data
;
952 struct drm_device
*dev
= error_priv
->dev
;
955 DRM_DEBUG_DRIVER("Resetting error state\n");
957 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
961 i915_destroy_error_state(dev
);
962 mutex_unlock(&dev
->struct_mutex
);
967 static int i915_error_state_open(struct inode
*inode
, struct file
*file
)
969 struct drm_device
*dev
= inode
->i_private
;
970 struct i915_error_state_file_priv
*error_priv
;
972 error_priv
= kzalloc(sizeof(*error_priv
), GFP_KERNEL
);
976 error_priv
->dev
= dev
;
978 i915_error_state_get(dev
, error_priv
);
980 file
->private_data
= error_priv
;
985 static int i915_error_state_release(struct inode
*inode
, struct file
*file
)
987 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
989 i915_error_state_put(error_priv
);
995 static ssize_t
i915_error_state_read(struct file
*file
, char __user
*userbuf
,
996 size_t count
, loff_t
*pos
)
998 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
999 struct drm_i915_error_state_buf error_str
;
1001 ssize_t ret_count
= 0;
1004 ret
= i915_error_state_buf_init(&error_str
, to_i915(error_priv
->dev
), count
, *pos
);
1008 ret
= i915_error_state_to_str(&error_str
, error_priv
);
1012 ret_count
= simple_read_from_buffer(userbuf
, count
, &tmp_pos
,
1019 *pos
= error_str
.start
+ ret_count
;
1021 i915_error_state_buf_release(&error_str
);
1022 return ret
?: ret_count
;
1025 static const struct file_operations i915_error_state_fops
= {
1026 .owner
= THIS_MODULE
,
1027 .open
= i915_error_state_open
,
1028 .read
= i915_error_state_read
,
1029 .write
= i915_error_state_write
,
1030 .llseek
= default_llseek
,
1031 .release
= i915_error_state_release
,
1035 i915_next_seqno_get(void *data
, u64
*val
)
1037 struct drm_device
*dev
= data
;
1038 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1041 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1045 *val
= dev_priv
->next_seqno
;
1046 mutex_unlock(&dev
->struct_mutex
);
1052 i915_next_seqno_set(void *data
, u64 val
)
1054 struct drm_device
*dev
= data
;
1057 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1061 ret
= i915_gem_set_seqno(dev
, val
);
1062 mutex_unlock(&dev
->struct_mutex
);
1067 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops
,
1068 i915_next_seqno_get
, i915_next_seqno_set
,
1071 static int i915_frequency_info(struct seq_file
*m
, void *unused
)
1073 struct drm_info_node
*node
= m
->private;
1074 struct drm_device
*dev
= node
->minor
->dev
;
1075 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1078 intel_runtime_pm_get(dev_priv
);
1080 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
1083 u16 rgvswctl
= I915_READ16(MEMSWCTL
);
1084 u16 rgvstat
= I915_READ16(MEMSTAT_ILK
);
1086 seq_printf(m
, "Requested P-state: %d\n", (rgvswctl
>> 8) & 0xf);
1087 seq_printf(m
, "Requested VID: %d\n", rgvswctl
& 0x3f);
1088 seq_printf(m
, "Current VID: %d\n", (rgvstat
& MEMSTAT_VID_MASK
) >>
1090 seq_printf(m
, "Current P-state: %d\n",
1091 (rgvstat
& MEMSTAT_PSTATE_MASK
) >> MEMSTAT_PSTATE_SHIFT
);
1092 } else if (IS_GEN6(dev
) || (IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) ||
1093 IS_BROADWELL(dev
) || IS_GEN9(dev
)) {
1094 u32 gt_perf_status
= I915_READ(GEN6_GT_PERF_STATUS
);
1095 u32 rp_state_limits
= I915_READ(GEN6_RP_STATE_LIMITS
);
1096 u32 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
1097 u32 rpmodectl
, rpinclimit
, rpdeclimit
;
1098 u32 rpstat
, cagf
, reqf
;
1099 u32 rpupei
, rpcurup
, rpprevup
;
1100 u32 rpdownei
, rpcurdown
, rpprevdown
;
1101 u32 pm_ier
, pm_imr
, pm_isr
, pm_iir
, pm_mask
;
1104 /* RPSTAT1 is in the GT power well */
1105 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1109 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
1111 reqf
= I915_READ(GEN6_RPNSWREQ
);
1115 reqf
&= ~GEN6_TURBO_DISABLE
;
1116 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1121 reqf
= intel_gpu_freq(dev_priv
, reqf
);
1123 rpmodectl
= I915_READ(GEN6_RP_CONTROL
);
1124 rpinclimit
= I915_READ(GEN6_RP_UP_THRESHOLD
);
1125 rpdeclimit
= I915_READ(GEN6_RP_DOWN_THRESHOLD
);
1127 rpstat
= I915_READ(GEN6_RPSTAT1
);
1128 rpupei
= I915_READ(GEN6_RP_CUR_UP_EI
);
1129 rpcurup
= I915_READ(GEN6_RP_CUR_UP
);
1130 rpprevup
= I915_READ(GEN6_RP_PREV_UP
);
1131 rpdownei
= I915_READ(GEN6_RP_CUR_DOWN_EI
);
1132 rpcurdown
= I915_READ(GEN6_RP_CUR_DOWN
);
1133 rpprevdown
= I915_READ(GEN6_RP_PREV_DOWN
);
1135 cagf
= (rpstat
& GEN9_CAGF_MASK
) >> GEN9_CAGF_SHIFT
;
1136 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1137 cagf
= (rpstat
& HSW_CAGF_MASK
) >> HSW_CAGF_SHIFT
;
1139 cagf
= (rpstat
& GEN6_CAGF_MASK
) >> GEN6_CAGF_SHIFT
;
1140 cagf
= intel_gpu_freq(dev_priv
, cagf
);
1142 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
1143 mutex_unlock(&dev
->struct_mutex
);
1145 if (IS_GEN6(dev
) || IS_GEN7(dev
)) {
1146 pm_ier
= I915_READ(GEN6_PMIER
);
1147 pm_imr
= I915_READ(GEN6_PMIMR
);
1148 pm_isr
= I915_READ(GEN6_PMISR
);
1149 pm_iir
= I915_READ(GEN6_PMIIR
);
1150 pm_mask
= I915_READ(GEN6_PMINTRMSK
);
1152 pm_ier
= I915_READ(GEN8_GT_IER(2));
1153 pm_imr
= I915_READ(GEN8_GT_IMR(2));
1154 pm_isr
= I915_READ(GEN8_GT_ISR(2));
1155 pm_iir
= I915_READ(GEN8_GT_IIR(2));
1156 pm_mask
= I915_READ(GEN6_PMINTRMSK
);
1158 seq_printf(m
, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1159 pm_ier
, pm_imr
, pm_isr
, pm_iir
, pm_mask
);
1160 seq_printf(m
, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status
);
1161 seq_printf(m
, "Render p-state ratio: %d\n",
1162 (gt_perf_status
& (IS_GEN9(dev
) ? 0x1ff00 : 0xff00)) >> 8);
1163 seq_printf(m
, "Render p-state VID: %d\n",
1164 gt_perf_status
& 0xff);
1165 seq_printf(m
, "Render p-state limit: %d\n",
1166 rp_state_limits
& 0xff);
1167 seq_printf(m
, "RPSTAT1: 0x%08x\n", rpstat
);
1168 seq_printf(m
, "RPMODECTL: 0x%08x\n", rpmodectl
);
1169 seq_printf(m
, "RPINCLIMIT: 0x%08x\n", rpinclimit
);
1170 seq_printf(m
, "RPDECLIMIT: 0x%08x\n", rpdeclimit
);
1171 seq_printf(m
, "RPNSWREQ: %dMHz\n", reqf
);
1172 seq_printf(m
, "CAGF: %dMHz\n", cagf
);
1173 seq_printf(m
, "RP CUR UP EI: %dus\n", rpupei
&
1174 GEN6_CURICONT_MASK
);
1175 seq_printf(m
, "RP CUR UP: %dus\n", rpcurup
&
1176 GEN6_CURBSYTAVG_MASK
);
1177 seq_printf(m
, "RP PREV UP: %dus\n", rpprevup
&
1178 GEN6_CURBSYTAVG_MASK
);
1179 seq_printf(m
, "RP CUR DOWN EI: %dus\n", rpdownei
&
1181 seq_printf(m
, "RP CUR DOWN: %dus\n", rpcurdown
&
1182 GEN6_CURBSYTAVG_MASK
);
1183 seq_printf(m
, "RP PREV DOWN: %dus\n", rpprevdown
&
1184 GEN6_CURBSYTAVG_MASK
);
1186 max_freq
= (rp_state_cap
& 0xff0000) >> 16;
1187 max_freq
*= (IS_SKYLAKE(dev
) ? GEN9_FREQ_SCALER
: 1);
1188 seq_printf(m
, "Lowest (RPN) frequency: %dMHz\n",
1189 intel_gpu_freq(dev_priv
, max_freq
));
1191 max_freq
= (rp_state_cap
& 0xff00) >> 8;
1192 max_freq
*= (IS_SKYLAKE(dev
) ? GEN9_FREQ_SCALER
: 1);
1193 seq_printf(m
, "Nominal (RP1) frequency: %dMHz\n",
1194 intel_gpu_freq(dev_priv
, max_freq
));
1196 max_freq
= rp_state_cap
& 0xff;
1197 max_freq
*= (IS_SKYLAKE(dev
) ? GEN9_FREQ_SCALER
: 1);
1198 seq_printf(m
, "Max non-overclocked (RP0) frequency: %dMHz\n",
1199 intel_gpu_freq(dev_priv
, max_freq
));
1201 seq_printf(m
, "Max overclocked frequency: %dMHz\n",
1202 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1203 } else if (IS_VALLEYVIEW(dev
)) {
1206 mutex_lock(&dev_priv
->rps
.hw_lock
);
1207 freq_sts
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
1208 seq_printf(m
, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts
);
1209 seq_printf(m
, "DDR freq: %d MHz\n", dev_priv
->mem_freq
);
1211 seq_printf(m
, "max GPU freq: %d MHz\n",
1212 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1214 seq_printf(m
, "min GPU freq: %d MHz\n",
1215 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
));
1218 "efficient (RPe) frequency: %d MHz\n",
1219 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
));
1221 seq_printf(m
, "current GPU freq: %d MHz\n",
1222 intel_gpu_freq(dev_priv
, (freq_sts
>> 8) & 0xff));
1223 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1225 seq_puts(m
, "no P-state info available\n");
1229 intel_runtime_pm_put(dev_priv
);
1233 static int i915_hangcheck_info(struct seq_file
*m
, void *unused
)
1235 struct drm_info_node
*node
= m
->private;
1236 struct drm_device
*dev
= node
->minor
->dev
;
1237 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1238 struct intel_engine_cs
*ring
;
1239 u64 acthd
[I915_NUM_RINGS
];
1240 u32 seqno
[I915_NUM_RINGS
];
1243 if (!i915
.enable_hangcheck
) {
1244 seq_printf(m
, "Hangcheck disabled\n");
1248 intel_runtime_pm_get(dev_priv
);
1250 for_each_ring(ring
, dev_priv
, i
) {
1251 seqno
[i
] = ring
->get_seqno(ring
, false);
1252 acthd
[i
] = intel_ring_get_active_head(ring
);
1255 intel_runtime_pm_put(dev_priv
);
1257 if (delayed_work_pending(&dev_priv
->gpu_error
.hangcheck_work
)) {
1258 seq_printf(m
, "Hangcheck active, fires in %dms\n",
1259 jiffies_to_msecs(dev_priv
->gpu_error
.hangcheck_work
.timer
.expires
-
1262 seq_printf(m
, "Hangcheck inactive\n");
1264 for_each_ring(ring
, dev_priv
, i
) {
1265 seq_printf(m
, "%s:\n", ring
->name
);
1266 seq_printf(m
, "\tseqno = %x [current %x]\n",
1267 ring
->hangcheck
.seqno
, seqno
[i
]);
1268 seq_printf(m
, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1269 (long long)ring
->hangcheck
.acthd
,
1270 (long long)acthd
[i
]);
1271 seq_printf(m
, "\tmax ACTHD = 0x%08llx\n",
1272 (long long)ring
->hangcheck
.max_acthd
);
1273 seq_printf(m
, "\tscore = %d\n", ring
->hangcheck
.score
);
1274 seq_printf(m
, "\taction = %d\n", ring
->hangcheck
.action
);
1280 static int ironlake_drpc_info(struct seq_file
*m
)
1282 struct drm_info_node
*node
= m
->private;
1283 struct drm_device
*dev
= node
->minor
->dev
;
1284 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1285 u32 rgvmodectl
, rstdbyctl
;
1289 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1292 intel_runtime_pm_get(dev_priv
);
1294 rgvmodectl
= I915_READ(MEMMODECTL
);
1295 rstdbyctl
= I915_READ(RSTDBYCTL
);
1296 crstandvid
= I915_READ16(CRSTANDVID
);
1298 intel_runtime_pm_put(dev_priv
);
1299 mutex_unlock(&dev
->struct_mutex
);
1301 seq_printf(m
, "HD boost: %s\n", (rgvmodectl
& MEMMODE_BOOST_EN
) ?
1303 seq_printf(m
, "Boost freq: %d\n",
1304 (rgvmodectl
& MEMMODE_BOOST_FREQ_MASK
) >>
1305 MEMMODE_BOOST_FREQ_SHIFT
);
1306 seq_printf(m
, "HW control enabled: %s\n",
1307 rgvmodectl
& MEMMODE_HWIDLE_EN
? "yes" : "no");
1308 seq_printf(m
, "SW control enabled: %s\n",
1309 rgvmodectl
& MEMMODE_SWMODE_EN
? "yes" : "no");
1310 seq_printf(m
, "Gated voltage change: %s\n",
1311 rgvmodectl
& MEMMODE_RCLK_GATE
? "yes" : "no");
1312 seq_printf(m
, "Starting frequency: P%d\n",
1313 (rgvmodectl
& MEMMODE_FSTART_MASK
) >> MEMMODE_FSTART_SHIFT
);
1314 seq_printf(m
, "Max P-state: P%d\n",
1315 (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
);
1316 seq_printf(m
, "Min P-state: P%d\n", (rgvmodectl
& MEMMODE_FMIN_MASK
));
1317 seq_printf(m
, "RS1 VID: %d\n", (crstandvid
& 0x3f));
1318 seq_printf(m
, "RS2 VID: %d\n", ((crstandvid
>> 8) & 0x3f));
1319 seq_printf(m
, "Render standby enabled: %s\n",
1320 (rstdbyctl
& RCX_SW_EXIT
) ? "no" : "yes");
1321 seq_puts(m
, "Current RS state: ");
1322 switch (rstdbyctl
& RSX_STATUS_MASK
) {
1324 seq_puts(m
, "on\n");
1326 case RSX_STATUS_RC1
:
1327 seq_puts(m
, "RC1\n");
1329 case RSX_STATUS_RC1E
:
1330 seq_puts(m
, "RC1E\n");
1332 case RSX_STATUS_RS1
:
1333 seq_puts(m
, "RS1\n");
1335 case RSX_STATUS_RS2
:
1336 seq_puts(m
, "RS2 (RC6)\n");
1338 case RSX_STATUS_RS3
:
1339 seq_puts(m
, "RC3 (RC6+)\n");
1342 seq_puts(m
, "unknown\n");
1349 static int i915_forcewake_domains(struct seq_file
*m
, void *data
)
1351 struct drm_info_node
*node
= m
->private;
1352 struct drm_device
*dev
= node
->minor
->dev
;
1353 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1354 struct intel_uncore_forcewake_domain
*fw_domain
;
1357 spin_lock_irq(&dev_priv
->uncore
.lock
);
1358 for_each_fw_domain(fw_domain
, dev_priv
, i
) {
1359 seq_printf(m
, "%s.wake_count = %u\n",
1360 intel_uncore_forcewake_domain_to_str(i
),
1361 fw_domain
->wake_count
);
1363 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1368 static int vlv_drpc_info(struct seq_file
*m
)
1370 struct drm_info_node
*node
= m
->private;
1371 struct drm_device
*dev
= node
->minor
->dev
;
1372 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1373 u32 rpmodectl1
, rcctl1
, pw_status
;
1375 intel_runtime_pm_get(dev_priv
);
1377 pw_status
= I915_READ(VLV_GTLC_PW_STATUS
);
1378 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1379 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1381 intel_runtime_pm_put(dev_priv
);
1383 seq_printf(m
, "Video Turbo Mode: %s\n",
1384 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1385 seq_printf(m
, "Turbo enabled: %s\n",
1386 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1387 seq_printf(m
, "HW control enabled: %s\n",
1388 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1389 seq_printf(m
, "SW control enabled: %s\n",
1390 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1391 GEN6_RP_MEDIA_SW_MODE
));
1392 seq_printf(m
, "RC6 Enabled: %s\n",
1393 yesno(rcctl1
& (GEN7_RC_CTL_TO_MODE
|
1394 GEN6_RC_CTL_EI_MODE(1))));
1395 seq_printf(m
, "Render Power Well: %s\n",
1396 (pw_status
& VLV_GTLC_PW_RENDER_STATUS_MASK
) ? "Up" : "Down");
1397 seq_printf(m
, "Media Power Well: %s\n",
1398 (pw_status
& VLV_GTLC_PW_MEDIA_STATUS_MASK
) ? "Up" : "Down");
1400 seq_printf(m
, "Render RC6 residency since boot: %u\n",
1401 I915_READ(VLV_GT_RENDER_RC6
));
1402 seq_printf(m
, "Media RC6 residency since boot: %u\n",
1403 I915_READ(VLV_GT_MEDIA_RC6
));
1405 return i915_forcewake_domains(m
, NULL
);
1408 static int gen6_drpc_info(struct seq_file
*m
)
1410 struct drm_info_node
*node
= m
->private;
1411 struct drm_device
*dev
= node
->minor
->dev
;
1412 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1413 u32 rpmodectl1
, gt_core_status
, rcctl1
, rc6vids
= 0;
1414 unsigned forcewake_count
;
1417 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1420 intel_runtime_pm_get(dev_priv
);
1422 spin_lock_irq(&dev_priv
->uncore
.lock
);
1423 forcewake_count
= dev_priv
->uncore
.fw_domain
[FW_DOMAIN_ID_RENDER
].wake_count
;
1424 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1426 if (forcewake_count
) {
1427 seq_puts(m
, "RC information inaccurate because somebody "
1428 "holds a forcewake reference \n");
1430 /* NB: we cannot use forcewake, else we read the wrong values */
1431 while (count
++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK
) & 1))
1433 seq_printf(m
, "RC information accurate: %s\n", yesno(count
< 51));
1436 gt_core_status
= readl(dev_priv
->regs
+ GEN6_GT_CORE_STATUS
);
1437 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS
, gt_core_status
, 4, true);
1439 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1440 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1441 mutex_unlock(&dev
->struct_mutex
);
1442 mutex_lock(&dev_priv
->rps
.hw_lock
);
1443 sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
1444 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1446 intel_runtime_pm_put(dev_priv
);
1448 seq_printf(m
, "Video Turbo Mode: %s\n",
1449 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1450 seq_printf(m
, "HW control enabled: %s\n",
1451 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1452 seq_printf(m
, "SW control enabled: %s\n",
1453 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1454 GEN6_RP_MEDIA_SW_MODE
));
1455 seq_printf(m
, "RC1e Enabled: %s\n",
1456 yesno(rcctl1
& GEN6_RC_CTL_RC1e_ENABLE
));
1457 seq_printf(m
, "RC6 Enabled: %s\n",
1458 yesno(rcctl1
& GEN6_RC_CTL_RC6_ENABLE
));
1459 seq_printf(m
, "Deep RC6 Enabled: %s\n",
1460 yesno(rcctl1
& GEN6_RC_CTL_RC6p_ENABLE
));
1461 seq_printf(m
, "Deepest RC6 Enabled: %s\n",
1462 yesno(rcctl1
& GEN6_RC_CTL_RC6pp_ENABLE
));
1463 seq_puts(m
, "Current RC state: ");
1464 switch (gt_core_status
& GEN6_RCn_MASK
) {
1466 if (gt_core_status
& GEN6_CORE_CPD_STATE_MASK
)
1467 seq_puts(m
, "Core Power Down\n");
1469 seq_puts(m
, "on\n");
1472 seq_puts(m
, "RC3\n");
1475 seq_puts(m
, "RC6\n");
1478 seq_puts(m
, "RC7\n");
1481 seq_puts(m
, "Unknown\n");
1485 seq_printf(m
, "Core Power Down: %s\n",
1486 yesno(gt_core_status
& GEN6_CORE_CPD_STATE_MASK
));
1488 /* Not exactly sure what this is */
1489 seq_printf(m
, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1490 I915_READ(GEN6_GT_GFX_RC6_LOCKED
));
1491 seq_printf(m
, "RC6 residency since boot: %u\n",
1492 I915_READ(GEN6_GT_GFX_RC6
));
1493 seq_printf(m
, "RC6+ residency since boot: %u\n",
1494 I915_READ(GEN6_GT_GFX_RC6p
));
1495 seq_printf(m
, "RC6++ residency since boot: %u\n",
1496 I915_READ(GEN6_GT_GFX_RC6pp
));
1498 seq_printf(m
, "RC6 voltage: %dmV\n",
1499 GEN6_DECODE_RC6_VID(((rc6vids
>> 0) & 0xff)));
1500 seq_printf(m
, "RC6+ voltage: %dmV\n",
1501 GEN6_DECODE_RC6_VID(((rc6vids
>> 8) & 0xff)));
1502 seq_printf(m
, "RC6++ voltage: %dmV\n",
1503 GEN6_DECODE_RC6_VID(((rc6vids
>> 16) & 0xff)));
1507 static int i915_drpc_info(struct seq_file
*m
, void *unused
)
1509 struct drm_info_node
*node
= m
->private;
1510 struct drm_device
*dev
= node
->minor
->dev
;
1512 if (IS_VALLEYVIEW(dev
))
1513 return vlv_drpc_info(m
);
1514 else if (INTEL_INFO(dev
)->gen
>= 6)
1515 return gen6_drpc_info(m
);
1517 return ironlake_drpc_info(m
);
1520 static int i915_fbc_status(struct seq_file
*m
, void *unused
)
1522 struct drm_info_node
*node
= m
->private;
1523 struct drm_device
*dev
= node
->minor
->dev
;
1524 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1526 if (!HAS_FBC(dev
)) {
1527 seq_puts(m
, "FBC unsupported on this chipset\n");
1531 intel_runtime_pm_get(dev_priv
);
1533 if (intel_fbc_enabled(dev
)) {
1534 seq_puts(m
, "FBC enabled\n");
1536 seq_puts(m
, "FBC disabled: ");
1537 switch (dev_priv
->fbc
.no_fbc_reason
) {
1539 seq_puts(m
, "FBC actived, but currently disabled in hardware");
1541 case FBC_UNSUPPORTED
:
1542 seq_puts(m
, "unsupported by this chipset");
1545 seq_puts(m
, "no outputs");
1547 case FBC_STOLEN_TOO_SMALL
:
1548 seq_puts(m
, "not enough stolen memory");
1550 case FBC_UNSUPPORTED_MODE
:
1551 seq_puts(m
, "mode not supported");
1553 case FBC_MODE_TOO_LARGE
:
1554 seq_puts(m
, "mode too large");
1557 seq_puts(m
, "FBC unsupported on plane");
1560 seq_puts(m
, "scanout buffer not tiled");
1562 case FBC_MULTIPLE_PIPES
:
1563 seq_puts(m
, "multiple pipes are enabled");
1565 case FBC_MODULE_PARAM
:
1566 seq_puts(m
, "disabled per module param (default off)");
1568 case FBC_CHIP_DEFAULT
:
1569 seq_puts(m
, "disabled per chip default");
1572 seq_puts(m
, "unknown reason");
1577 intel_runtime_pm_put(dev_priv
);
1582 static int i915_fbc_fc_get(void *data
, u64
*val
)
1584 struct drm_device
*dev
= data
;
1585 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1587 if (INTEL_INFO(dev
)->gen
< 7 || !HAS_FBC(dev
))
1590 drm_modeset_lock_all(dev
);
1591 *val
= dev_priv
->fbc
.false_color
;
1592 drm_modeset_unlock_all(dev
);
1597 static int i915_fbc_fc_set(void *data
, u64 val
)
1599 struct drm_device
*dev
= data
;
1600 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1603 if (INTEL_INFO(dev
)->gen
< 7 || !HAS_FBC(dev
))
1606 drm_modeset_lock_all(dev
);
1608 reg
= I915_READ(ILK_DPFC_CONTROL
);
1609 dev_priv
->fbc
.false_color
= val
;
1611 I915_WRITE(ILK_DPFC_CONTROL
, val
?
1612 (reg
| FBC_CTL_FALSE_COLOR
) :
1613 (reg
& ~FBC_CTL_FALSE_COLOR
));
1615 drm_modeset_unlock_all(dev
);
1619 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops
,
1620 i915_fbc_fc_get
, i915_fbc_fc_set
,
1623 static int i915_ips_status(struct seq_file
*m
, void *unused
)
1625 struct drm_info_node
*node
= m
->private;
1626 struct drm_device
*dev
= node
->minor
->dev
;
1627 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1629 if (!HAS_IPS(dev
)) {
1630 seq_puts(m
, "not supported\n");
1634 intel_runtime_pm_get(dev_priv
);
1636 seq_printf(m
, "Enabled by kernel parameter: %s\n",
1637 yesno(i915
.enable_ips
));
1639 if (INTEL_INFO(dev
)->gen
>= 8) {
1640 seq_puts(m
, "Currently: unknown\n");
1642 if (I915_READ(IPS_CTL
) & IPS_ENABLE
)
1643 seq_puts(m
, "Currently: enabled\n");
1645 seq_puts(m
, "Currently: disabled\n");
1648 intel_runtime_pm_put(dev_priv
);
1653 static int i915_sr_status(struct seq_file
*m
, void *unused
)
1655 struct drm_info_node
*node
= m
->private;
1656 struct drm_device
*dev
= node
->minor
->dev
;
1657 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1658 bool sr_enabled
= false;
1660 intel_runtime_pm_get(dev_priv
);
1662 if (HAS_PCH_SPLIT(dev
))
1663 sr_enabled
= I915_READ(WM1_LP_ILK
) & WM1_LP_SR_EN
;
1664 else if (IS_CRESTLINE(dev
) || IS_I945G(dev
) || IS_I945GM(dev
))
1665 sr_enabled
= I915_READ(FW_BLC_SELF
) & FW_BLC_SELF_EN
;
1666 else if (IS_I915GM(dev
))
1667 sr_enabled
= I915_READ(INSTPM
) & INSTPM_SELF_EN
;
1668 else if (IS_PINEVIEW(dev
))
1669 sr_enabled
= I915_READ(DSPFW3
) & PINEVIEW_SELF_REFRESH_EN
;
1671 intel_runtime_pm_put(dev_priv
);
1673 seq_printf(m
, "self-refresh: %s\n",
1674 sr_enabled
? "enabled" : "disabled");
1679 static int i915_emon_status(struct seq_file
*m
, void *unused
)
1681 struct drm_info_node
*node
= m
->private;
1682 struct drm_device
*dev
= node
->minor
->dev
;
1683 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1684 unsigned long temp
, chipset
, gfx
;
1690 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1694 temp
= i915_mch_val(dev_priv
);
1695 chipset
= i915_chipset_val(dev_priv
);
1696 gfx
= i915_gfx_val(dev_priv
);
1697 mutex_unlock(&dev
->struct_mutex
);
1699 seq_printf(m
, "GMCH temp: %ld\n", temp
);
1700 seq_printf(m
, "Chipset power: %ld\n", chipset
);
1701 seq_printf(m
, "GFX power: %ld\n", gfx
);
1702 seq_printf(m
, "Total power: %ld\n", chipset
+ gfx
);
1707 static int i915_ring_freq_table(struct seq_file
*m
, void *unused
)
1709 struct drm_info_node
*node
= m
->private;
1710 struct drm_device
*dev
= node
->minor
->dev
;
1711 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1713 int gpu_freq
, ia_freq
;
1715 if (!(IS_GEN6(dev
) || IS_GEN7(dev
))) {
1716 seq_puts(m
, "unsupported on this chipset\n");
1720 intel_runtime_pm_get(dev_priv
);
1722 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
1724 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
1728 seq_puts(m
, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1730 for (gpu_freq
= dev_priv
->rps
.min_freq_softlimit
;
1731 gpu_freq
<= dev_priv
->rps
.max_freq_softlimit
;
1734 sandybridge_pcode_read(dev_priv
,
1735 GEN6_PCODE_READ_MIN_FREQ_TABLE
,
1737 seq_printf(m
, "%d\t\t%d\t\t\t\t%d\n",
1738 intel_gpu_freq(dev_priv
, gpu_freq
),
1739 ((ia_freq
>> 0) & 0xff) * 100,
1740 ((ia_freq
>> 8) & 0xff) * 100);
1743 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1746 intel_runtime_pm_put(dev_priv
);
1750 static int i915_opregion(struct seq_file
*m
, void *unused
)
1752 struct drm_info_node
*node
= m
->private;
1753 struct drm_device
*dev
= node
->minor
->dev
;
1754 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1755 struct intel_opregion
*opregion
= &dev_priv
->opregion
;
1756 void *data
= kmalloc(OPREGION_SIZE
, GFP_KERNEL
);
1762 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1766 if (opregion
->header
) {
1767 memcpy_fromio(data
, opregion
->header
, OPREGION_SIZE
);
1768 seq_write(m
, data
, OPREGION_SIZE
);
1771 mutex_unlock(&dev
->struct_mutex
);
1778 static int i915_gem_framebuffer_info(struct seq_file
*m
, void *data
)
1780 struct drm_info_node
*node
= m
->private;
1781 struct drm_device
*dev
= node
->minor
->dev
;
1782 struct intel_fbdev
*ifbdev
= NULL
;
1783 struct intel_framebuffer
*fb
;
1785 #ifdef CONFIG_DRM_I915_FBDEV
1786 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1788 ifbdev
= dev_priv
->fbdev
;
1789 fb
= to_intel_framebuffer(ifbdev
->helper
.fb
);
1791 seq_printf(m
, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1795 fb
->base
.bits_per_pixel
,
1796 fb
->base
.modifier
[0],
1797 atomic_read(&fb
->base
.refcount
.refcount
));
1798 describe_obj(m
, fb
->obj
);
1802 mutex_lock(&dev
->mode_config
.fb_lock
);
1803 list_for_each_entry(fb
, &dev
->mode_config
.fb_list
, base
.head
) {
1804 if (ifbdev
&& &fb
->base
== ifbdev
->helper
.fb
)
1807 seq_printf(m
, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1811 fb
->base
.bits_per_pixel
,
1812 fb
->base
.modifier
[0],
1813 atomic_read(&fb
->base
.refcount
.refcount
));
1814 describe_obj(m
, fb
->obj
);
1817 mutex_unlock(&dev
->mode_config
.fb_lock
);
1822 static void describe_ctx_ringbuf(struct seq_file
*m
,
1823 struct intel_ringbuffer
*ringbuf
)
1825 seq_printf(m
, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1826 ringbuf
->space
, ringbuf
->head
, ringbuf
->tail
,
1827 ringbuf
->last_retired_head
);
1830 static int i915_context_status(struct seq_file
*m
, void *unused
)
1832 struct drm_info_node
*node
= m
->private;
1833 struct drm_device
*dev
= node
->minor
->dev
;
1834 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1835 struct intel_engine_cs
*ring
;
1836 struct intel_context
*ctx
;
1839 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1843 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
1844 if (!i915
.enable_execlists
&&
1845 ctx
->legacy_hw_ctx
.rcs_state
== NULL
)
1848 seq_puts(m
, "HW context ");
1849 describe_ctx(m
, ctx
);
1850 for_each_ring(ring
, dev_priv
, i
) {
1851 if (ring
->default_context
== ctx
)
1852 seq_printf(m
, "(default context %s) ",
1856 if (i915
.enable_execlists
) {
1858 for_each_ring(ring
, dev_priv
, i
) {
1859 struct drm_i915_gem_object
*ctx_obj
=
1860 ctx
->engine
[i
].state
;
1861 struct intel_ringbuffer
*ringbuf
=
1862 ctx
->engine
[i
].ringbuf
;
1864 seq_printf(m
, "%s: ", ring
->name
);
1866 describe_obj(m
, ctx_obj
);
1868 describe_ctx_ringbuf(m
, ringbuf
);
1872 describe_obj(m
, ctx
->legacy_hw_ctx
.rcs_state
);
1878 mutex_unlock(&dev
->struct_mutex
);
1883 static void i915_dump_lrc_obj(struct seq_file
*m
,
1884 struct intel_engine_cs
*ring
,
1885 struct drm_i915_gem_object
*ctx_obj
)
1888 uint32_t *reg_state
;
1890 unsigned long ggtt_offset
= 0;
1892 if (ctx_obj
== NULL
) {
1893 seq_printf(m
, "Context on %s with no gem object\n",
1898 seq_printf(m
, "CONTEXT: %s %u\n", ring
->name
,
1899 intel_execlists_ctx_id(ctx_obj
));
1901 if (!i915_gem_obj_ggtt_bound(ctx_obj
))
1902 seq_puts(m
, "\tNot bound in GGTT\n");
1904 ggtt_offset
= i915_gem_obj_ggtt_offset(ctx_obj
);
1906 if (i915_gem_object_get_pages(ctx_obj
)) {
1907 seq_puts(m
, "\tFailed to get pages for context object\n");
1911 page
= i915_gem_object_get_page(ctx_obj
, 1);
1912 if (!WARN_ON(page
== NULL
)) {
1913 reg_state
= kmap_atomic(page
);
1915 for (j
= 0; j
< 0x600 / sizeof(u32
) / 4; j
+= 4) {
1916 seq_printf(m
, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1917 ggtt_offset
+ 4096 + (j
* 4),
1918 reg_state
[j
], reg_state
[j
+ 1],
1919 reg_state
[j
+ 2], reg_state
[j
+ 3]);
1921 kunmap_atomic(reg_state
);
1927 static int i915_dump_lrc(struct seq_file
*m
, void *unused
)
1929 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1930 struct drm_device
*dev
= node
->minor
->dev
;
1931 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1932 struct intel_engine_cs
*ring
;
1933 struct intel_context
*ctx
;
1936 if (!i915
.enable_execlists
) {
1937 seq_printf(m
, "Logical Ring Contexts are disabled\n");
1941 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1945 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
1946 for_each_ring(ring
, dev_priv
, i
) {
1947 if (ring
->default_context
!= ctx
)
1948 i915_dump_lrc_obj(m
, ring
,
1949 ctx
->engine
[i
].state
);
1953 mutex_unlock(&dev
->struct_mutex
);
1958 static int i915_execlists(struct seq_file
*m
, void *data
)
1960 struct drm_info_node
*node
= (struct drm_info_node
*)m
->private;
1961 struct drm_device
*dev
= node
->minor
->dev
;
1962 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1963 struct intel_engine_cs
*ring
;
1969 struct list_head
*cursor
;
1973 if (!i915
.enable_execlists
) {
1974 seq_puts(m
, "Logical Ring Contexts are disabled\n");
1978 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1982 intel_runtime_pm_get(dev_priv
);
1984 for_each_ring(ring
, dev_priv
, ring_id
) {
1985 struct drm_i915_gem_request
*head_req
= NULL
;
1987 unsigned long flags
;
1989 seq_printf(m
, "%s\n", ring
->name
);
1991 status
= I915_READ(RING_EXECLIST_STATUS(ring
));
1992 ctx_id
= I915_READ(RING_EXECLIST_STATUS(ring
) + 4);
1993 seq_printf(m
, "\tExeclist status: 0x%08X, context: %u\n",
1996 status_pointer
= I915_READ(RING_CONTEXT_STATUS_PTR(ring
));
1997 seq_printf(m
, "\tStatus pointer: 0x%08X\n", status_pointer
);
1999 read_pointer
= ring
->next_context_status_buffer
;
2000 write_pointer
= status_pointer
& 0x07;
2001 if (read_pointer
> write_pointer
)
2003 seq_printf(m
, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2004 read_pointer
, write_pointer
);
2006 for (i
= 0; i
< 6; i
++) {
2007 status
= I915_READ(RING_CONTEXT_STATUS_BUF(ring
) + 8*i
);
2008 ctx_id
= I915_READ(RING_CONTEXT_STATUS_BUF(ring
) + 8*i
+ 4);
2010 seq_printf(m
, "\tStatus buffer %d: 0x%08X, context: %u\n",
2014 spin_lock_irqsave(&ring
->execlist_lock
, flags
);
2015 list_for_each(cursor
, &ring
->execlist_queue
)
2017 head_req
= list_first_entry_or_null(&ring
->execlist_queue
,
2018 struct drm_i915_gem_request
, execlist_link
);
2019 spin_unlock_irqrestore(&ring
->execlist_lock
, flags
);
2021 seq_printf(m
, "\t%d requests in queue\n", count
);
2023 struct drm_i915_gem_object
*ctx_obj
;
2025 ctx_obj
= head_req
->ctx
->engine
[ring_id
].state
;
2026 seq_printf(m
, "\tHead request id: %u\n",
2027 intel_execlists_ctx_id(ctx_obj
));
2028 seq_printf(m
, "\tHead request tail: %u\n",
2035 intel_runtime_pm_put(dev_priv
);
2036 mutex_unlock(&dev
->struct_mutex
);
2041 static const char *swizzle_string(unsigned swizzle
)
2044 case I915_BIT_6_SWIZZLE_NONE
:
2046 case I915_BIT_6_SWIZZLE_9
:
2048 case I915_BIT_6_SWIZZLE_9_10
:
2049 return "bit9/bit10";
2050 case I915_BIT_6_SWIZZLE_9_11
:
2051 return "bit9/bit11";
2052 case I915_BIT_6_SWIZZLE_9_10_11
:
2053 return "bit9/bit10/bit11";
2054 case I915_BIT_6_SWIZZLE_9_17
:
2055 return "bit9/bit17";
2056 case I915_BIT_6_SWIZZLE_9_10_17
:
2057 return "bit9/bit10/bit17";
2058 case I915_BIT_6_SWIZZLE_UNKNOWN
:
2065 static int i915_swizzle_info(struct seq_file
*m
, void *data
)
2067 struct drm_info_node
*node
= m
->private;
2068 struct drm_device
*dev
= node
->minor
->dev
;
2069 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2072 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2075 intel_runtime_pm_get(dev_priv
);
2077 seq_printf(m
, "bit6 swizzle for X-tiling = %s\n",
2078 swizzle_string(dev_priv
->mm
.bit_6_swizzle_x
));
2079 seq_printf(m
, "bit6 swizzle for Y-tiling = %s\n",
2080 swizzle_string(dev_priv
->mm
.bit_6_swizzle_y
));
2082 if (IS_GEN3(dev
) || IS_GEN4(dev
)) {
2083 seq_printf(m
, "DDC = 0x%08x\n",
2085 seq_printf(m
, "DDC2 = 0x%08x\n",
2087 seq_printf(m
, "C0DRB3 = 0x%04x\n",
2088 I915_READ16(C0DRB3
));
2089 seq_printf(m
, "C1DRB3 = 0x%04x\n",
2090 I915_READ16(C1DRB3
));
2091 } else if (INTEL_INFO(dev
)->gen
>= 6) {
2092 seq_printf(m
, "MAD_DIMM_C0 = 0x%08x\n",
2093 I915_READ(MAD_DIMM_C0
));
2094 seq_printf(m
, "MAD_DIMM_C1 = 0x%08x\n",
2095 I915_READ(MAD_DIMM_C1
));
2096 seq_printf(m
, "MAD_DIMM_C2 = 0x%08x\n",
2097 I915_READ(MAD_DIMM_C2
));
2098 seq_printf(m
, "TILECTL = 0x%08x\n",
2099 I915_READ(TILECTL
));
2100 if (INTEL_INFO(dev
)->gen
>= 8)
2101 seq_printf(m
, "GAMTARBMODE = 0x%08x\n",
2102 I915_READ(GAMTARBMODE
));
2104 seq_printf(m
, "ARB_MODE = 0x%08x\n",
2105 I915_READ(ARB_MODE
));
2106 seq_printf(m
, "DISP_ARB_CTL = 0x%08x\n",
2107 I915_READ(DISP_ARB_CTL
));
2110 if (dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
)
2111 seq_puts(m
, "L-shaped memory detected\n");
2113 intel_runtime_pm_put(dev_priv
);
2114 mutex_unlock(&dev
->struct_mutex
);
2119 static int per_file_ctx(int id
, void *ptr
, void *data
)
2121 struct intel_context
*ctx
= ptr
;
2122 struct seq_file
*m
= data
;
2123 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
2126 seq_printf(m
, " no ppgtt for context %d\n",
2131 if (i915_gem_context_is_default(ctx
))
2132 seq_puts(m
, " default context:\n");
2134 seq_printf(m
, " context %d:\n", ctx
->user_handle
);
2135 ppgtt
->debug_dump(ppgtt
, m
);
2140 static void gen8_ppgtt_info(struct seq_file
*m
, struct drm_device
*dev
)
2142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2143 struct intel_engine_cs
*ring
;
2144 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2150 seq_printf(m
, "Page directories: %d\n", ppgtt
->num_pd_pages
);
2151 seq_printf(m
, "Page tables: %d\n", ppgtt
->num_pd_entries
);
2152 for_each_ring(ring
, dev_priv
, unused
) {
2153 seq_printf(m
, "%s\n", ring
->name
);
2154 for (i
= 0; i
< 4; i
++) {
2155 u32 offset
= 0x270 + i
* 8;
2156 u64 pdp
= I915_READ(ring
->mmio_base
+ offset
+ 4);
2158 pdp
|= I915_READ(ring
->mmio_base
+ offset
);
2159 seq_printf(m
, "\tPDP%d 0x%016llx\n", i
, pdp
);
2164 static void gen6_ppgtt_info(struct seq_file
*m
, struct drm_device
*dev
)
2166 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2167 struct intel_engine_cs
*ring
;
2168 struct drm_file
*file
;
2171 if (INTEL_INFO(dev
)->gen
== 6)
2172 seq_printf(m
, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE
));
2174 for_each_ring(ring
, dev_priv
, i
) {
2175 seq_printf(m
, "%s\n", ring
->name
);
2176 if (INTEL_INFO(dev
)->gen
== 7)
2177 seq_printf(m
, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring
)));
2178 seq_printf(m
, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring
)));
2179 seq_printf(m
, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring
)));
2180 seq_printf(m
, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring
)));
2182 if (dev_priv
->mm
.aliasing_ppgtt
) {
2183 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2185 seq_puts(m
, "aliasing PPGTT:\n");
2186 seq_printf(m
, "pd gtt offset: 0x%08x\n", ppgtt
->pd
.pd_offset
);
2188 ppgtt
->debug_dump(ppgtt
, m
);
2191 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
2192 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2194 seq_printf(m
, "proc: %s\n",
2195 get_pid_task(file
->pid
, PIDTYPE_PID
)->comm
);
2196 idr_for_each(&file_priv
->context_idr
, per_file_ctx
, m
);
2198 seq_printf(m
, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK
));
2201 static int i915_ppgtt_info(struct seq_file
*m
, void *data
)
2203 struct drm_info_node
*node
= m
->private;
2204 struct drm_device
*dev
= node
->minor
->dev
;
2205 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2207 int ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2210 intel_runtime_pm_get(dev_priv
);
2212 if (INTEL_INFO(dev
)->gen
>= 8)
2213 gen8_ppgtt_info(m
, dev
);
2214 else if (INTEL_INFO(dev
)->gen
>= 6)
2215 gen6_ppgtt_info(m
, dev
);
2217 intel_runtime_pm_put(dev_priv
);
2218 mutex_unlock(&dev
->struct_mutex
);
2223 static int i915_llc(struct seq_file
*m
, void *data
)
2225 struct drm_info_node
*node
= m
->private;
2226 struct drm_device
*dev
= node
->minor
->dev
;
2227 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2229 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2230 seq_printf(m
, "LLC: %s\n", yesno(HAS_LLC(dev
)));
2231 seq_printf(m
, "eLLC: %zuMB\n", dev_priv
->ellc_size
);
2236 static int i915_edp_psr_status(struct seq_file
*m
, void *data
)
2238 struct drm_info_node
*node
= m
->private;
2239 struct drm_device
*dev
= node
->minor
->dev
;
2240 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2244 bool enabled
= false;
2246 if (!HAS_PSR(dev
)) {
2247 seq_puts(m
, "PSR not supported\n");
2251 intel_runtime_pm_get(dev_priv
);
2253 mutex_lock(&dev_priv
->psr
.lock
);
2254 seq_printf(m
, "Sink_Support: %s\n", yesno(dev_priv
->psr
.sink_support
));
2255 seq_printf(m
, "Source_OK: %s\n", yesno(dev_priv
->psr
.source_ok
));
2256 seq_printf(m
, "Enabled: %s\n", yesno((bool)dev_priv
->psr
.enabled
));
2257 seq_printf(m
, "Active: %s\n", yesno(dev_priv
->psr
.active
));
2258 seq_printf(m
, "Busy frontbuffer bits: 0x%03x\n",
2259 dev_priv
->psr
.busy_frontbuffer_bits
);
2260 seq_printf(m
, "Re-enable work scheduled: %s\n",
2261 yesno(work_busy(&dev_priv
->psr
.work
.work
)));
2264 enabled
= I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
;
2266 for_each_pipe(dev_priv
, pipe
) {
2267 stat
[pipe
] = I915_READ(VLV_PSRSTAT(pipe
)) &
2268 VLV_EDP_PSR_CURR_STATE_MASK
;
2269 if ((stat
[pipe
] == VLV_EDP_PSR_ACTIVE_NORFB_UP
) ||
2270 (stat
[pipe
] == VLV_EDP_PSR_ACTIVE_SF_UPDATE
))
2274 seq_printf(m
, "HW Enabled & Active bit: %s", yesno(enabled
));
2277 for_each_pipe(dev_priv
, pipe
) {
2278 if ((stat
[pipe
] == VLV_EDP_PSR_ACTIVE_NORFB_UP
) ||
2279 (stat
[pipe
] == VLV_EDP_PSR_ACTIVE_SF_UPDATE
))
2280 seq_printf(m
, " pipe %c", pipe_name(pipe
));
2284 seq_printf(m
, "Link standby: %s\n",
2285 yesno((bool)dev_priv
->psr
.link_standby
));
2287 /* CHV PSR has no kind of performance counter */
2289 psrperf
= I915_READ(EDP_PSR_PERF_CNT(dev
)) &
2290 EDP_PSR_PERF_CNT_MASK
;
2292 seq_printf(m
, "Performance_Counter: %u\n", psrperf
);
2294 mutex_unlock(&dev_priv
->psr
.lock
);
2296 intel_runtime_pm_put(dev_priv
);
2300 static int i915_sink_crc(struct seq_file
*m
, void *data
)
2302 struct drm_info_node
*node
= m
->private;
2303 struct drm_device
*dev
= node
->minor
->dev
;
2304 struct intel_encoder
*encoder
;
2305 struct intel_connector
*connector
;
2306 struct intel_dp
*intel_dp
= NULL
;
2310 drm_modeset_lock_all(dev
);
2311 for_each_intel_encoder(dev
, connector
) {
2313 if (connector
->base
.dpms
!= DRM_MODE_DPMS_ON
)
2316 if (!connector
->base
.encoder
)
2319 encoder
= to_intel_encoder(connector
->base
.encoder
);
2320 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2323 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2325 ret
= intel_dp_sink_crc(intel_dp
, crc
);
2329 seq_printf(m
, "%02x%02x%02x%02x%02x%02x\n",
2330 crc
[0], crc
[1], crc
[2],
2331 crc
[3], crc
[4], crc
[5]);
2336 drm_modeset_unlock_all(dev
);
2340 static int i915_energy_uJ(struct seq_file
*m
, void *data
)
2342 struct drm_info_node
*node
= m
->private;
2343 struct drm_device
*dev
= node
->minor
->dev
;
2344 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2348 if (INTEL_INFO(dev
)->gen
< 6)
2351 intel_runtime_pm_get(dev_priv
);
2353 rdmsrl(MSR_RAPL_POWER_UNIT
, power
);
2354 power
= (power
& 0x1f00) >> 8;
2355 units
= 1000000 / (1 << power
); /* convert to uJ */
2356 power
= I915_READ(MCH_SECP_NRG_STTS
);
2359 intel_runtime_pm_put(dev_priv
);
2361 seq_printf(m
, "%llu", (long long unsigned)power
);
2366 static int i915_pc8_status(struct seq_file
*m
, void *unused
)
2368 struct drm_info_node
*node
= m
->private;
2369 struct drm_device
*dev
= node
->minor
->dev
;
2370 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2372 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
2373 seq_puts(m
, "not supported\n");
2377 seq_printf(m
, "GPU idle: %s\n", yesno(!dev_priv
->mm
.busy
));
2378 seq_printf(m
, "IRQs disabled: %s\n",
2379 yesno(!intel_irqs_enabled(dev_priv
)));
2384 static const char *power_domain_str(enum intel_display_power_domain domain
)
2387 case POWER_DOMAIN_PIPE_A
:
2389 case POWER_DOMAIN_PIPE_B
:
2391 case POWER_DOMAIN_PIPE_C
:
2393 case POWER_DOMAIN_PIPE_A_PANEL_FITTER
:
2394 return "PIPE_A_PANEL_FITTER";
2395 case POWER_DOMAIN_PIPE_B_PANEL_FITTER
:
2396 return "PIPE_B_PANEL_FITTER";
2397 case POWER_DOMAIN_PIPE_C_PANEL_FITTER
:
2398 return "PIPE_C_PANEL_FITTER";
2399 case POWER_DOMAIN_TRANSCODER_A
:
2400 return "TRANSCODER_A";
2401 case POWER_DOMAIN_TRANSCODER_B
:
2402 return "TRANSCODER_B";
2403 case POWER_DOMAIN_TRANSCODER_C
:
2404 return "TRANSCODER_C";
2405 case POWER_DOMAIN_TRANSCODER_EDP
:
2406 return "TRANSCODER_EDP";
2407 case POWER_DOMAIN_PORT_DDI_A_2_LANES
:
2408 return "PORT_DDI_A_2_LANES";
2409 case POWER_DOMAIN_PORT_DDI_A_4_LANES
:
2410 return "PORT_DDI_A_4_LANES";
2411 case POWER_DOMAIN_PORT_DDI_B_2_LANES
:
2412 return "PORT_DDI_B_2_LANES";
2413 case POWER_DOMAIN_PORT_DDI_B_4_LANES
:
2414 return "PORT_DDI_B_4_LANES";
2415 case POWER_DOMAIN_PORT_DDI_C_2_LANES
:
2416 return "PORT_DDI_C_2_LANES";
2417 case POWER_DOMAIN_PORT_DDI_C_4_LANES
:
2418 return "PORT_DDI_C_4_LANES";
2419 case POWER_DOMAIN_PORT_DDI_D_2_LANES
:
2420 return "PORT_DDI_D_2_LANES";
2421 case POWER_DOMAIN_PORT_DDI_D_4_LANES
:
2422 return "PORT_DDI_D_4_LANES";
2423 case POWER_DOMAIN_PORT_DSI
:
2425 case POWER_DOMAIN_PORT_CRT
:
2427 case POWER_DOMAIN_PORT_OTHER
:
2428 return "PORT_OTHER";
2429 case POWER_DOMAIN_VGA
:
2431 case POWER_DOMAIN_AUDIO
:
2433 case POWER_DOMAIN_PLLS
:
2435 case POWER_DOMAIN_AUX_A
:
2437 case POWER_DOMAIN_AUX_B
:
2439 case POWER_DOMAIN_AUX_C
:
2441 case POWER_DOMAIN_AUX_D
:
2443 case POWER_DOMAIN_INIT
:
2446 MISSING_CASE(domain
);
2451 static int i915_power_domain_info(struct seq_file
*m
, void *unused
)
2453 struct drm_info_node
*node
= m
->private;
2454 struct drm_device
*dev
= node
->minor
->dev
;
2455 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2456 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
2459 mutex_lock(&power_domains
->lock
);
2461 seq_printf(m
, "%-25s %s\n", "Power well/domain", "Use count");
2462 for (i
= 0; i
< power_domains
->power_well_count
; i
++) {
2463 struct i915_power_well
*power_well
;
2464 enum intel_display_power_domain power_domain
;
2466 power_well
= &power_domains
->power_wells
[i
];
2467 seq_printf(m
, "%-25s %d\n", power_well
->name
,
2470 for (power_domain
= 0; power_domain
< POWER_DOMAIN_NUM
;
2472 if (!(BIT(power_domain
) & power_well
->domains
))
2475 seq_printf(m
, " %-23s %d\n",
2476 power_domain_str(power_domain
),
2477 power_domains
->domain_use_count
[power_domain
]);
2481 mutex_unlock(&power_domains
->lock
);
2486 static void intel_seq_print_mode(struct seq_file
*m
, int tabs
,
2487 struct drm_display_mode
*mode
)
2491 for (i
= 0; i
< tabs
; i
++)
2494 seq_printf(m
, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2495 mode
->base
.id
, mode
->name
,
2496 mode
->vrefresh
, mode
->clock
,
2497 mode
->hdisplay
, mode
->hsync_start
,
2498 mode
->hsync_end
, mode
->htotal
,
2499 mode
->vdisplay
, mode
->vsync_start
,
2500 mode
->vsync_end
, mode
->vtotal
,
2501 mode
->type
, mode
->flags
);
2504 static void intel_encoder_info(struct seq_file
*m
,
2505 struct intel_crtc
*intel_crtc
,
2506 struct intel_encoder
*intel_encoder
)
2508 struct drm_info_node
*node
= m
->private;
2509 struct drm_device
*dev
= node
->minor
->dev
;
2510 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2511 struct intel_connector
*intel_connector
;
2512 struct drm_encoder
*encoder
;
2514 encoder
= &intel_encoder
->base
;
2515 seq_printf(m
, "\tencoder %d: type: %s, connectors:\n",
2516 encoder
->base
.id
, encoder
->name
);
2517 for_each_connector_on_encoder(dev
, encoder
, intel_connector
) {
2518 struct drm_connector
*connector
= &intel_connector
->base
;
2519 seq_printf(m
, "\t\tconnector %d: type: %s, status: %s",
2522 drm_get_connector_status_name(connector
->status
));
2523 if (connector
->status
== connector_status_connected
) {
2524 struct drm_display_mode
*mode
= &crtc
->mode
;
2525 seq_printf(m
, ", mode:\n");
2526 intel_seq_print_mode(m
, 2, mode
);
2533 static void intel_crtc_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
2535 struct drm_info_node
*node
= m
->private;
2536 struct drm_device
*dev
= node
->minor
->dev
;
2537 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2538 struct intel_encoder
*intel_encoder
;
2540 if (crtc
->primary
->fb
)
2541 seq_printf(m
, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2542 crtc
->primary
->fb
->base
.id
, crtc
->x
, crtc
->y
,
2543 crtc
->primary
->fb
->width
, crtc
->primary
->fb
->height
);
2545 seq_puts(m
, "\tprimary plane disabled\n");
2546 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
2547 intel_encoder_info(m
, intel_crtc
, intel_encoder
);
2550 static void intel_panel_info(struct seq_file
*m
, struct intel_panel
*panel
)
2552 struct drm_display_mode
*mode
= panel
->fixed_mode
;
2554 seq_printf(m
, "\tfixed mode:\n");
2555 intel_seq_print_mode(m
, 2, mode
);
2558 static void intel_dp_info(struct seq_file
*m
,
2559 struct intel_connector
*intel_connector
)
2561 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2562 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
2564 seq_printf(m
, "\tDPCD rev: %x\n", intel_dp
->dpcd
[DP_DPCD_REV
]);
2565 seq_printf(m
, "\taudio support: %s\n", intel_dp
->has_audio
? "yes" :
2567 if (intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2568 intel_panel_info(m
, &intel_connector
->panel
);
2571 static void intel_hdmi_info(struct seq_file
*m
,
2572 struct intel_connector
*intel_connector
)
2574 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2575 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&intel_encoder
->base
);
2577 seq_printf(m
, "\taudio support: %s\n", intel_hdmi
->has_audio
? "yes" :
2581 static void intel_lvds_info(struct seq_file
*m
,
2582 struct intel_connector
*intel_connector
)
2584 intel_panel_info(m
, &intel_connector
->panel
);
2587 static void intel_connector_info(struct seq_file
*m
,
2588 struct drm_connector
*connector
)
2590 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2591 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2592 struct drm_display_mode
*mode
;
2594 seq_printf(m
, "connector %d: type %s, status: %s\n",
2595 connector
->base
.id
, connector
->name
,
2596 drm_get_connector_status_name(connector
->status
));
2597 if (connector
->status
== connector_status_connected
) {
2598 seq_printf(m
, "\tname: %s\n", connector
->display_info
.name
);
2599 seq_printf(m
, "\tphysical dimensions: %dx%dmm\n",
2600 connector
->display_info
.width_mm
,
2601 connector
->display_info
.height_mm
);
2602 seq_printf(m
, "\tsubpixel order: %s\n",
2603 drm_get_subpixel_order_name(connector
->display_info
.subpixel_order
));
2604 seq_printf(m
, "\tCEA rev: %d\n",
2605 connector
->display_info
.cea_rev
);
2607 if (intel_encoder
) {
2608 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
2609 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2610 intel_dp_info(m
, intel_connector
);
2611 else if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
)
2612 intel_hdmi_info(m
, intel_connector
);
2613 else if (intel_encoder
->type
== INTEL_OUTPUT_LVDS
)
2614 intel_lvds_info(m
, intel_connector
);
2617 seq_printf(m
, "\tmodes:\n");
2618 list_for_each_entry(mode
, &connector
->modes
, head
)
2619 intel_seq_print_mode(m
, 2, mode
);
2622 static bool cursor_active(struct drm_device
*dev
, int pipe
)
2624 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2627 if (IS_845G(dev
) || IS_I865G(dev
))
2628 state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
2630 state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
2635 static bool cursor_position(struct drm_device
*dev
, int pipe
, int *x
, int *y
)
2637 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2640 pos
= I915_READ(CURPOS(pipe
));
2642 *x
= (pos
>> CURSOR_X_SHIFT
) & CURSOR_POS_MASK
;
2643 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
))
2646 *y
= (pos
>> CURSOR_Y_SHIFT
) & CURSOR_POS_MASK
;
2647 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
))
2650 return cursor_active(dev
, pipe
);
2653 static int i915_display_info(struct seq_file
*m
, void *unused
)
2655 struct drm_info_node
*node
= m
->private;
2656 struct drm_device
*dev
= node
->minor
->dev
;
2657 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2658 struct intel_crtc
*crtc
;
2659 struct drm_connector
*connector
;
2661 intel_runtime_pm_get(dev_priv
);
2662 drm_modeset_lock_all(dev
);
2663 seq_printf(m
, "CRTC info\n");
2664 seq_printf(m
, "---------\n");
2665 for_each_intel_crtc(dev
, crtc
) {
2669 seq_printf(m
, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
2670 crtc
->base
.base
.id
, pipe_name(crtc
->pipe
),
2671 yesno(crtc
->active
), crtc
->config
->pipe_src_w
,
2672 crtc
->config
->pipe_src_h
);
2674 intel_crtc_info(m
, crtc
);
2676 active
= cursor_position(dev
, crtc
->pipe
, &x
, &y
);
2677 seq_printf(m
, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
2678 yesno(crtc
->cursor_base
),
2679 x
, y
, crtc
->base
.cursor
->state
->crtc_w
,
2680 crtc
->base
.cursor
->state
->crtc_h
,
2681 crtc
->cursor_addr
, yesno(active
));
2684 seq_printf(m
, "\tunderrun reporting: cpu=%s pch=%s \n",
2685 yesno(!crtc
->cpu_fifo_underrun_disabled
),
2686 yesno(!crtc
->pch_fifo_underrun_disabled
));
2689 seq_printf(m
, "\n");
2690 seq_printf(m
, "Connector info\n");
2691 seq_printf(m
, "--------------\n");
2692 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
2693 intel_connector_info(m
, connector
);
2695 drm_modeset_unlock_all(dev
);
2696 intel_runtime_pm_put(dev_priv
);
2701 static int i915_semaphore_status(struct seq_file
*m
, void *unused
)
2703 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2704 struct drm_device
*dev
= node
->minor
->dev
;
2705 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2706 struct intel_engine_cs
*ring
;
2707 int num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
2710 if (!i915_semaphore_is_enabled(dev
)) {
2711 seq_puts(m
, "Semaphores are disabled\n");
2715 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2718 intel_runtime_pm_get(dev_priv
);
2720 if (IS_BROADWELL(dev
)) {
2724 page
= i915_gem_object_get_page(dev_priv
->semaphore_obj
, 0);
2726 seqno
= (uint64_t *)kmap_atomic(page
);
2727 for_each_ring(ring
, dev_priv
, i
) {
2730 seq_printf(m
, "%s\n", ring
->name
);
2732 seq_puts(m
, " Last signal:");
2733 for (j
= 0; j
< num_rings
; j
++) {
2734 offset
= i
* I915_NUM_RINGS
+ j
;
2735 seq_printf(m
, "0x%08llx (0x%02llx) ",
2736 seqno
[offset
], offset
* 8);
2740 seq_puts(m
, " Last wait: ");
2741 for (j
= 0; j
< num_rings
; j
++) {
2742 offset
= i
+ (j
* I915_NUM_RINGS
);
2743 seq_printf(m
, "0x%08llx (0x%02llx) ",
2744 seqno
[offset
], offset
* 8);
2749 kunmap_atomic(seqno
);
2751 seq_puts(m
, " Last signal:");
2752 for_each_ring(ring
, dev_priv
, i
)
2753 for (j
= 0; j
< num_rings
; j
++)
2754 seq_printf(m
, "0x%08x\n",
2755 I915_READ(ring
->semaphore
.mbox
.signal
[j
]));
2759 seq_puts(m
, "\nSync seqno:\n");
2760 for_each_ring(ring
, dev_priv
, i
) {
2761 for (j
= 0; j
< num_rings
; j
++) {
2762 seq_printf(m
, " 0x%08x ", ring
->semaphore
.sync_seqno
[j
]);
2768 intel_runtime_pm_put(dev_priv
);
2769 mutex_unlock(&dev
->struct_mutex
);
2773 static int i915_shared_dplls_info(struct seq_file
*m
, void *unused
)
2775 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2776 struct drm_device
*dev
= node
->minor
->dev
;
2777 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2780 drm_modeset_lock_all(dev
);
2781 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
2782 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
2784 seq_printf(m
, "DPLL%i: %s, id: %i\n", i
, pll
->name
, pll
->id
);
2785 seq_printf(m
, " crtc_mask: 0x%08x, active: %d, on: %s\n",
2786 pll
->config
.crtc_mask
, pll
->active
, yesno(pll
->on
));
2787 seq_printf(m
, " tracked hardware state:\n");
2788 seq_printf(m
, " dpll: 0x%08x\n", pll
->config
.hw_state
.dpll
);
2789 seq_printf(m
, " dpll_md: 0x%08x\n",
2790 pll
->config
.hw_state
.dpll_md
);
2791 seq_printf(m
, " fp0: 0x%08x\n", pll
->config
.hw_state
.fp0
);
2792 seq_printf(m
, " fp1: 0x%08x\n", pll
->config
.hw_state
.fp1
);
2793 seq_printf(m
, " wrpll: 0x%08x\n", pll
->config
.hw_state
.wrpll
);
2795 drm_modeset_unlock_all(dev
);
2800 static int i915_wa_registers(struct seq_file
*m
, void *unused
)
2804 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2805 struct drm_device
*dev
= node
->minor
->dev
;
2806 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2808 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2812 intel_runtime_pm_get(dev_priv
);
2814 seq_printf(m
, "Workarounds applied: %d\n", dev_priv
->workarounds
.count
);
2815 for (i
= 0; i
< dev_priv
->workarounds
.count
; ++i
) {
2816 u32 addr
, mask
, value
, read
;
2819 addr
= dev_priv
->workarounds
.reg
[i
].addr
;
2820 mask
= dev_priv
->workarounds
.reg
[i
].mask
;
2821 value
= dev_priv
->workarounds
.reg
[i
].value
;
2822 read
= I915_READ(addr
);
2823 ok
= (value
& mask
) == (read
& mask
);
2824 seq_printf(m
, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2825 addr
, value
, mask
, read
, ok
? "OK" : "FAIL");
2828 intel_runtime_pm_put(dev_priv
);
2829 mutex_unlock(&dev
->struct_mutex
);
2834 static int i915_ddb_info(struct seq_file
*m
, void *unused
)
2836 struct drm_info_node
*node
= m
->private;
2837 struct drm_device
*dev
= node
->minor
->dev
;
2838 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2839 struct skl_ddb_allocation
*ddb
;
2840 struct skl_ddb_entry
*entry
;
2844 if (INTEL_INFO(dev
)->gen
< 9)
2847 drm_modeset_lock_all(dev
);
2849 ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
2851 seq_printf(m
, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
2853 for_each_pipe(dev_priv
, pipe
) {
2854 seq_printf(m
, "Pipe %c\n", pipe_name(pipe
));
2856 for_each_plane(dev_priv
, pipe
, plane
) {
2857 entry
= &ddb
->plane
[pipe
][plane
];
2858 seq_printf(m
, " Plane%-8d%8u%8u%8u\n", plane
+ 1,
2859 entry
->start
, entry
->end
,
2860 skl_ddb_entry_size(entry
));
2863 entry
= &ddb
->cursor
[pipe
];
2864 seq_printf(m
, " %-13s%8u%8u%8u\n", "Cursor", entry
->start
,
2865 entry
->end
, skl_ddb_entry_size(entry
));
2868 drm_modeset_unlock_all(dev
);
2873 static void drrs_status_per_crtc(struct seq_file
*m
,
2874 struct drm_device
*dev
, struct intel_crtc
*intel_crtc
)
2876 struct intel_encoder
*intel_encoder
;
2877 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2878 struct i915_drrs
*drrs
= &dev_priv
->drrs
;
2881 for_each_encoder_on_crtc(dev
, &intel_crtc
->base
, intel_encoder
) {
2882 /* Encoder connected on this CRTC */
2883 switch (intel_encoder
->type
) {
2884 case INTEL_OUTPUT_EDP
:
2885 seq_puts(m
, "eDP:\n");
2887 case INTEL_OUTPUT_DSI
:
2888 seq_puts(m
, "DSI:\n");
2890 case INTEL_OUTPUT_HDMI
:
2891 seq_puts(m
, "HDMI:\n");
2893 case INTEL_OUTPUT_DISPLAYPORT
:
2894 seq_puts(m
, "DP:\n");
2897 seq_printf(m
, "Other encoder (id=%d).\n",
2898 intel_encoder
->type
);
2903 if (dev_priv
->vbt
.drrs_type
== STATIC_DRRS_SUPPORT
)
2904 seq_puts(m
, "\tVBT: DRRS_type: Static");
2905 else if (dev_priv
->vbt
.drrs_type
== SEAMLESS_DRRS_SUPPORT
)
2906 seq_puts(m
, "\tVBT: DRRS_type: Seamless");
2907 else if (dev_priv
->vbt
.drrs_type
== DRRS_NOT_SUPPORTED
)
2908 seq_puts(m
, "\tVBT: DRRS_type: None");
2910 seq_puts(m
, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
2912 seq_puts(m
, "\n\n");
2914 if (intel_crtc
->config
->has_drrs
) {
2915 struct intel_panel
*panel
;
2917 mutex_lock(&drrs
->mutex
);
2918 /* DRRS Supported */
2919 seq_puts(m
, "\tDRRS Supported: Yes\n");
2921 /* disable_drrs() will make drrs->dp NULL */
2923 seq_puts(m
, "Idleness DRRS: Disabled");
2924 mutex_unlock(&drrs
->mutex
);
2928 panel
= &drrs
->dp
->attached_connector
->panel
;
2929 seq_printf(m
, "\t\tBusy_frontbuffer_bits: 0x%X",
2930 drrs
->busy_frontbuffer_bits
);
2932 seq_puts(m
, "\n\t\t");
2933 if (drrs
->refresh_rate_type
== DRRS_HIGH_RR
) {
2934 seq_puts(m
, "DRRS_State: DRRS_HIGH_RR\n");
2935 vrefresh
= panel
->fixed_mode
->vrefresh
;
2936 } else if (drrs
->refresh_rate_type
== DRRS_LOW_RR
) {
2937 seq_puts(m
, "DRRS_State: DRRS_LOW_RR\n");
2938 vrefresh
= panel
->downclock_mode
->vrefresh
;
2940 seq_printf(m
, "DRRS_State: Unknown(%d)\n",
2941 drrs
->refresh_rate_type
);
2942 mutex_unlock(&drrs
->mutex
);
2945 seq_printf(m
, "\t\tVrefresh: %d", vrefresh
);
2947 seq_puts(m
, "\n\t\t");
2948 mutex_unlock(&drrs
->mutex
);
2950 /* DRRS not supported. Print the VBT parameter*/
2951 seq_puts(m
, "\tDRRS Supported : No");
2956 static int i915_drrs_status(struct seq_file
*m
, void *unused
)
2958 struct drm_info_node
*node
= m
->private;
2959 struct drm_device
*dev
= node
->minor
->dev
;
2960 struct intel_crtc
*intel_crtc
;
2961 int active_crtc_cnt
= 0;
2963 for_each_intel_crtc(dev
, intel_crtc
) {
2964 drm_modeset_lock(&intel_crtc
->base
.mutex
, NULL
);
2966 if (intel_crtc
->active
) {
2968 seq_printf(m
, "\nCRTC %d: ", active_crtc_cnt
);
2970 drrs_status_per_crtc(m
, dev
, intel_crtc
);
2973 drm_modeset_unlock(&intel_crtc
->base
.mutex
);
2976 if (!active_crtc_cnt
)
2977 seq_puts(m
, "No active crtc found\n");
2982 struct pipe_crc_info
{
2984 struct drm_device
*dev
;
2988 static int i915_dp_mst_info(struct seq_file
*m
, void *unused
)
2990 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2991 struct drm_device
*dev
= node
->minor
->dev
;
2992 struct drm_encoder
*encoder
;
2993 struct intel_encoder
*intel_encoder
;
2994 struct intel_digital_port
*intel_dig_port
;
2995 drm_modeset_lock_all(dev
);
2996 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
2997 intel_encoder
= to_intel_encoder(encoder
);
2998 if (intel_encoder
->type
!= INTEL_OUTPUT_DISPLAYPORT
)
3000 intel_dig_port
= enc_to_dig_port(encoder
);
3001 if (!intel_dig_port
->dp
.can_mst
)
3004 drm_dp_mst_dump_topology(m
, &intel_dig_port
->dp
.mst_mgr
);
3006 drm_modeset_unlock_all(dev
);
3010 static int i915_pipe_crc_open(struct inode
*inode
, struct file
*filep
)
3012 struct pipe_crc_info
*info
= inode
->i_private
;
3013 struct drm_i915_private
*dev_priv
= info
->dev
->dev_private
;
3014 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
3016 if (info
->pipe
>= INTEL_INFO(info
->dev
)->num_pipes
)
3019 spin_lock_irq(&pipe_crc
->lock
);
3021 if (pipe_crc
->opened
) {
3022 spin_unlock_irq(&pipe_crc
->lock
);
3023 return -EBUSY
; /* already open */
3026 pipe_crc
->opened
= true;
3027 filep
->private_data
= inode
->i_private
;
3029 spin_unlock_irq(&pipe_crc
->lock
);
3034 static int i915_pipe_crc_release(struct inode
*inode
, struct file
*filep
)
3036 struct pipe_crc_info
*info
= inode
->i_private
;
3037 struct drm_i915_private
*dev_priv
= info
->dev
->dev_private
;
3038 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
3040 spin_lock_irq(&pipe_crc
->lock
);
3041 pipe_crc
->opened
= false;
3042 spin_unlock_irq(&pipe_crc
->lock
);
3047 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3048 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3049 /* account for \'0' */
3050 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3052 static int pipe_crc_data_count(struct intel_pipe_crc
*pipe_crc
)
3054 assert_spin_locked(&pipe_crc
->lock
);
3055 return CIRC_CNT(pipe_crc
->head
, pipe_crc
->tail
,
3056 INTEL_PIPE_CRC_ENTRIES_NR
);
3060 i915_pipe_crc_read(struct file
*filep
, char __user
*user_buf
, size_t count
,
3063 struct pipe_crc_info
*info
= filep
->private_data
;
3064 struct drm_device
*dev
= info
->dev
;
3065 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3066 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
3067 char buf
[PIPE_CRC_BUFFER_LEN
];
3072 * Don't allow user space to provide buffers not big enough to hold
3075 if (count
< PIPE_CRC_LINE_LEN
)
3078 if (pipe_crc
->source
== INTEL_PIPE_CRC_SOURCE_NONE
)
3081 /* nothing to read */
3082 spin_lock_irq(&pipe_crc
->lock
);
3083 while (pipe_crc_data_count(pipe_crc
) == 0) {
3086 if (filep
->f_flags
& O_NONBLOCK
) {
3087 spin_unlock_irq(&pipe_crc
->lock
);
3091 ret
= wait_event_interruptible_lock_irq(pipe_crc
->wq
,
3092 pipe_crc_data_count(pipe_crc
), pipe_crc
->lock
);
3094 spin_unlock_irq(&pipe_crc
->lock
);
3099 /* We now have one or more entries to read */
3100 n_entries
= count
/ PIPE_CRC_LINE_LEN
;
3103 while (n_entries
> 0) {
3104 struct intel_pipe_crc_entry
*entry
=
3105 &pipe_crc
->entries
[pipe_crc
->tail
];
3108 if (CIRC_CNT(pipe_crc
->head
, pipe_crc
->tail
,
3109 INTEL_PIPE_CRC_ENTRIES_NR
) < 1)
3112 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR
);
3113 pipe_crc
->tail
= (pipe_crc
->tail
+ 1) & (INTEL_PIPE_CRC_ENTRIES_NR
- 1);
3115 bytes_read
+= snprintf(buf
, PIPE_CRC_BUFFER_LEN
,
3116 "%8u %8x %8x %8x %8x %8x\n",
3117 entry
->frame
, entry
->crc
[0],
3118 entry
->crc
[1], entry
->crc
[2],
3119 entry
->crc
[3], entry
->crc
[4]);
3121 spin_unlock_irq(&pipe_crc
->lock
);
3123 ret
= copy_to_user(user_buf
, buf
, PIPE_CRC_LINE_LEN
);
3124 if (ret
== PIPE_CRC_LINE_LEN
)
3127 user_buf
+= PIPE_CRC_LINE_LEN
;
3130 spin_lock_irq(&pipe_crc
->lock
);
3133 spin_unlock_irq(&pipe_crc
->lock
);
3138 static const struct file_operations i915_pipe_crc_fops
= {
3139 .owner
= THIS_MODULE
,
3140 .open
= i915_pipe_crc_open
,
3141 .read
= i915_pipe_crc_read
,
3142 .release
= i915_pipe_crc_release
,
3145 static struct pipe_crc_info i915_pipe_crc_data
[I915_MAX_PIPES
] = {
3147 .name
= "i915_pipe_A_crc",
3151 .name
= "i915_pipe_B_crc",
3155 .name
= "i915_pipe_C_crc",
3160 static int i915_pipe_crc_create(struct dentry
*root
, struct drm_minor
*minor
,
3163 struct drm_device
*dev
= minor
->dev
;
3165 struct pipe_crc_info
*info
= &i915_pipe_crc_data
[pipe
];
3168 ent
= debugfs_create_file(info
->name
, S_IRUGO
, root
, info
,
3169 &i915_pipe_crc_fops
);
3173 return drm_add_fake_info_node(minor
, ent
, info
);
3176 static const char * const pipe_crc_sources
[] = {
3189 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source
)
3191 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources
) != INTEL_PIPE_CRC_SOURCE_MAX
);
3192 return pipe_crc_sources
[source
];
3195 static int display_crc_ctl_show(struct seq_file
*m
, void *data
)
3197 struct drm_device
*dev
= m
->private;
3198 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3201 for (i
= 0; i
< I915_MAX_PIPES
; i
++)
3202 seq_printf(m
, "%c %s\n", pipe_name(i
),
3203 pipe_crc_source_name(dev_priv
->pipe_crc
[i
].source
));
3208 static int display_crc_ctl_open(struct inode
*inode
, struct file
*file
)
3210 struct drm_device
*dev
= inode
->i_private
;
3212 return single_open(file
, display_crc_ctl_show
, dev
);
3215 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
3218 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3219 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3222 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3223 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_INCLUDE_BORDER_I8XX
;
3225 case INTEL_PIPE_CRC_SOURCE_NONE
:
3235 static int i9xx_pipe_crc_auto_source(struct drm_device
*dev
, enum pipe pipe
,
3236 enum intel_pipe_crc_source
*source
)
3238 struct intel_encoder
*encoder
;
3239 struct intel_crtc
*crtc
;
3240 struct intel_digital_port
*dig_port
;
3243 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3245 drm_modeset_lock_all(dev
);
3246 for_each_intel_encoder(dev
, encoder
) {
3247 if (!encoder
->base
.crtc
)
3250 crtc
= to_intel_crtc(encoder
->base
.crtc
);
3252 if (crtc
->pipe
!= pipe
)
3255 switch (encoder
->type
) {
3256 case INTEL_OUTPUT_TVOUT
:
3257 *source
= INTEL_PIPE_CRC_SOURCE_TV
;
3259 case INTEL_OUTPUT_DISPLAYPORT
:
3260 case INTEL_OUTPUT_EDP
:
3261 dig_port
= enc_to_dig_port(&encoder
->base
);
3262 switch (dig_port
->port
) {
3264 *source
= INTEL_PIPE_CRC_SOURCE_DP_B
;
3267 *source
= INTEL_PIPE_CRC_SOURCE_DP_C
;
3270 *source
= INTEL_PIPE_CRC_SOURCE_DP_D
;
3273 WARN(1, "nonexisting DP port %c\n",
3274 port_name(dig_port
->port
));
3282 drm_modeset_unlock_all(dev
);
3287 static int vlv_pipe_crc_ctl_reg(struct drm_device
*dev
,
3289 enum intel_pipe_crc_source
*source
,
3292 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3293 bool need_stable_symbols
= false;
3295 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
3296 int ret
= i9xx_pipe_crc_auto_source(dev
, pipe
, source
);
3302 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3303 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_VLV
;
3305 case INTEL_PIPE_CRC_SOURCE_DP_B
:
3306 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_VLV
;
3307 need_stable_symbols
= true;
3309 case INTEL_PIPE_CRC_SOURCE_DP_C
:
3310 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_VLV
;
3311 need_stable_symbols
= true;
3313 case INTEL_PIPE_CRC_SOURCE_DP_D
:
3314 if (!IS_CHERRYVIEW(dev
))
3316 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_D_VLV
;
3317 need_stable_symbols
= true;
3319 case INTEL_PIPE_CRC_SOURCE_NONE
:
3327 * When the pipe CRC tap point is after the transcoders we need
3328 * to tweak symbol-level features to produce a deterministic series of
3329 * symbols for a given frame. We need to reset those features only once
3330 * a frame (instead of every nth symbol):
3331 * - DC-balance: used to ensure a better clock recovery from the data
3333 * - DisplayPort scrambling: used for EMI reduction
3335 if (need_stable_symbols
) {
3336 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3338 tmp
|= DC_BALANCE_RESET_VLV
;
3341 tmp
|= PIPE_A_SCRAMBLE_RESET
;
3344 tmp
|= PIPE_B_SCRAMBLE_RESET
;
3347 tmp
|= PIPE_C_SCRAMBLE_RESET
;
3352 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3358 static int i9xx_pipe_crc_ctl_reg(struct drm_device
*dev
,
3360 enum intel_pipe_crc_source
*source
,
3363 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3364 bool need_stable_symbols
= false;
3366 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
3367 int ret
= i9xx_pipe_crc_auto_source(dev
, pipe
, source
);
3373 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3374 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_I9XX
;
3376 case INTEL_PIPE_CRC_SOURCE_TV
:
3377 if (!SUPPORTS_TV(dev
))
3379 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_TV_PRE
;
3381 case INTEL_PIPE_CRC_SOURCE_DP_B
:
3384 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_G4X
;
3385 need_stable_symbols
= true;
3387 case INTEL_PIPE_CRC_SOURCE_DP_C
:
3390 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_G4X
;
3391 need_stable_symbols
= true;
3393 case INTEL_PIPE_CRC_SOURCE_DP_D
:
3396 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_D_G4X
;
3397 need_stable_symbols
= true;
3399 case INTEL_PIPE_CRC_SOURCE_NONE
:
3407 * When the pipe CRC tap point is after the transcoders we need
3408 * to tweak symbol-level features to produce a deterministic series of
3409 * symbols for a given frame. We need to reset those features only once
3410 * a frame (instead of every nth symbol):
3411 * - DC-balance: used to ensure a better clock recovery from the data
3413 * - DisplayPort scrambling: used for EMI reduction
3415 if (need_stable_symbols
) {
3416 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3418 WARN_ON(!IS_G4X(dev
));
3420 I915_WRITE(PORT_DFT_I9XX
,
3421 I915_READ(PORT_DFT_I9XX
) | DC_BALANCE_RESET
);
3424 tmp
|= PIPE_A_SCRAMBLE_RESET
;
3426 tmp
|= PIPE_B_SCRAMBLE_RESET
;
3428 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3434 static void vlv_undo_pipe_scramble_reset(struct drm_device
*dev
,
3437 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3438 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3442 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
3445 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
3448 tmp
&= ~PIPE_C_SCRAMBLE_RESET
;
3453 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
))
3454 tmp
&= ~DC_BALANCE_RESET_VLV
;
3455 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3459 static void g4x_undo_pipe_scramble_reset(struct drm_device
*dev
,
3462 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3463 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3466 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
3468 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
3469 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3471 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
)) {
3472 I915_WRITE(PORT_DFT_I9XX
,
3473 I915_READ(PORT_DFT_I9XX
) & ~DC_BALANCE_RESET
);
3477 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
3480 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3481 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3484 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
3485 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_ILK
;
3487 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
3488 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_ILK
;
3490 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3491 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_ILK
;
3493 case INTEL_PIPE_CRC_SOURCE_NONE
:
3503 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device
*dev
)
3505 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3506 struct intel_crtc
*crtc
=
3507 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_A
]);
3509 drm_modeset_lock_all(dev
);
3511 * If we use the eDP transcoder we need to make sure that we don't
3512 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3513 * relevant on hsw with pipe A when using the always-on power well
3516 if (crtc
->config
->cpu_transcoder
== TRANSCODER_EDP
&&
3517 !crtc
->config
->pch_pfit
.enabled
) {
3518 crtc
->config
->pch_pfit
.force_thru
= true;
3520 intel_display_power_get(dev_priv
,
3521 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A
));
3523 dev_priv
->display
.crtc_disable(&crtc
->base
);
3524 dev_priv
->display
.crtc_enable(&crtc
->base
);
3526 drm_modeset_unlock_all(dev
);
3529 static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device
*dev
)
3531 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3532 struct intel_crtc
*crtc
=
3533 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_A
]);
3535 drm_modeset_lock_all(dev
);
3537 * If we use the eDP transcoder we need to make sure that we don't
3538 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3539 * relevant on hsw with pipe A when using the always-on power well
3542 if (crtc
->config
->pch_pfit
.force_thru
) {
3543 crtc
->config
->pch_pfit
.force_thru
= false;
3545 dev_priv
->display
.crtc_disable(&crtc
->base
);
3546 dev_priv
->display
.crtc_enable(&crtc
->base
);
3548 intel_display_power_put(dev_priv
,
3549 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A
));
3551 drm_modeset_unlock_all(dev
);
3554 static int ivb_pipe_crc_ctl_reg(struct drm_device
*dev
,
3556 enum intel_pipe_crc_source
*source
,
3559 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3560 *source
= INTEL_PIPE_CRC_SOURCE_PF
;
3563 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
3564 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_IVB
;
3566 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
3567 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_IVB
;
3569 case INTEL_PIPE_CRC_SOURCE_PF
:
3570 if (IS_HASWELL(dev
) && pipe
== PIPE_A
)
3571 hsw_trans_edp_pipe_A_crc_wa(dev
);
3573 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PF_IVB
;
3575 case INTEL_PIPE_CRC_SOURCE_NONE
:
3585 static int pipe_crc_set_source(struct drm_device
*dev
, enum pipe pipe
,
3586 enum intel_pipe_crc_source source
)
3588 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3589 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
3590 struct intel_crtc
*crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
,
3592 u32 val
= 0; /* shut up gcc */
3595 if (pipe_crc
->source
== source
)
3598 /* forbid changing the source without going back to 'none' */
3599 if (pipe_crc
->source
&& source
)
3602 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PIPE(pipe
))) {
3603 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3608 ret
= i8xx_pipe_crc_ctl_reg(&source
, &val
);
3609 else if (INTEL_INFO(dev
)->gen
< 5)
3610 ret
= i9xx_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
3611 else if (IS_VALLEYVIEW(dev
))
3612 ret
= vlv_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
3613 else if (IS_GEN5(dev
) || IS_GEN6(dev
))
3614 ret
= ilk_pipe_crc_ctl_reg(&source
, &val
);
3616 ret
= ivb_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
3621 /* none -> real source transition */
3623 struct intel_pipe_crc_entry
*entries
;
3625 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3626 pipe_name(pipe
), pipe_crc_source_name(source
));
3628 entries
= kcalloc(INTEL_PIPE_CRC_ENTRIES_NR
,
3629 sizeof(pipe_crc
->entries
[0]),
3635 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3636 * enabled and disabled dynamically based on package C states,
3637 * user space can't make reliable use of the CRCs, so let's just
3638 * completely disable it.
3640 hsw_disable_ips(crtc
);
3642 spin_lock_irq(&pipe_crc
->lock
);
3643 kfree(pipe_crc
->entries
);
3644 pipe_crc
->entries
= entries
;
3647 spin_unlock_irq(&pipe_crc
->lock
);
3650 pipe_crc
->source
= source
;
3652 I915_WRITE(PIPE_CRC_CTL(pipe
), val
);
3653 POSTING_READ(PIPE_CRC_CTL(pipe
));
3655 /* real source -> none transition */
3656 if (source
== INTEL_PIPE_CRC_SOURCE_NONE
) {
3657 struct intel_pipe_crc_entry
*entries
;
3658 struct intel_crtc
*crtc
=
3659 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
3661 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3664 drm_modeset_lock(&crtc
->base
.mutex
, NULL
);
3666 intel_wait_for_vblank(dev
, pipe
);
3667 drm_modeset_unlock(&crtc
->base
.mutex
);
3669 spin_lock_irq(&pipe_crc
->lock
);
3670 entries
= pipe_crc
->entries
;
3671 pipe_crc
->entries
= NULL
;
3674 spin_unlock_irq(&pipe_crc
->lock
);
3679 g4x_undo_pipe_scramble_reset(dev
, pipe
);
3680 else if (IS_VALLEYVIEW(dev
))
3681 vlv_undo_pipe_scramble_reset(dev
, pipe
);
3682 else if (IS_HASWELL(dev
) && pipe
== PIPE_A
)
3683 hsw_undo_trans_edp_pipe_A_crc_wa(dev
);
3685 hsw_enable_ips(crtc
);
3692 * Parse pipe CRC command strings:
3693 * command: wsp* object wsp+ name wsp+ source wsp*
3696 * source: (none | plane1 | plane2 | pf)
3697 * wsp: (#0x20 | #0x9 | #0xA)+
3700 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3701 * "pipe A none" -> Stop CRC
3703 static int display_crc_ctl_tokenize(char *buf
, char *words
[], int max_words
)
3710 /* skip leading white space */
3711 buf
= skip_spaces(buf
);
3713 break; /* end of buffer */
3715 /* find end of word */
3716 for (end
= buf
; *end
&& !isspace(*end
); end
++)
3719 if (n_words
== max_words
) {
3720 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3722 return -EINVAL
; /* ran out of words[] before bytes */
3727 words
[n_words
++] = buf
;
3734 enum intel_pipe_crc_object
{
3735 PIPE_CRC_OBJECT_PIPE
,
3738 static const char * const pipe_crc_objects
[] = {
3743 display_crc_ctl_parse_object(const char *buf
, enum intel_pipe_crc_object
*o
)
3747 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_objects
); i
++)
3748 if (!strcmp(buf
, pipe_crc_objects
[i
])) {
3756 static int display_crc_ctl_parse_pipe(const char *buf
, enum pipe
*pipe
)
3758 const char name
= buf
[0];
3760 if (name
< 'A' || name
>= pipe_name(I915_MAX_PIPES
))
3769 display_crc_ctl_parse_source(const char *buf
, enum intel_pipe_crc_source
*s
)
3773 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_sources
); i
++)
3774 if (!strcmp(buf
, pipe_crc_sources
[i
])) {
3782 static int display_crc_ctl_parse(struct drm_device
*dev
, char *buf
, size_t len
)
3786 char *words
[N_WORDS
];
3788 enum intel_pipe_crc_object object
;
3789 enum intel_pipe_crc_source source
;
3791 n_words
= display_crc_ctl_tokenize(buf
, words
, N_WORDS
);
3792 if (n_words
!= N_WORDS
) {
3793 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3798 if (display_crc_ctl_parse_object(words
[0], &object
) < 0) {
3799 DRM_DEBUG_DRIVER("unknown object %s\n", words
[0]);
3803 if (display_crc_ctl_parse_pipe(words
[1], &pipe
) < 0) {
3804 DRM_DEBUG_DRIVER("unknown pipe %s\n", words
[1]);
3808 if (display_crc_ctl_parse_source(words
[2], &source
) < 0) {
3809 DRM_DEBUG_DRIVER("unknown source %s\n", words
[2]);
3813 return pipe_crc_set_source(dev
, pipe
, source
);
3816 static ssize_t
display_crc_ctl_write(struct file
*file
, const char __user
*ubuf
,
3817 size_t len
, loff_t
*offp
)
3819 struct seq_file
*m
= file
->private_data
;
3820 struct drm_device
*dev
= m
->private;
3827 if (len
> PAGE_SIZE
- 1) {
3828 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3833 tmpbuf
= kmalloc(len
+ 1, GFP_KERNEL
);
3837 if (copy_from_user(tmpbuf
, ubuf
, len
)) {
3843 ret
= display_crc_ctl_parse(dev
, tmpbuf
, len
);
3854 static const struct file_operations i915_display_crc_ctl_fops
= {
3855 .owner
= THIS_MODULE
,
3856 .open
= display_crc_ctl_open
,
3858 .llseek
= seq_lseek
,
3859 .release
= single_release
,
3860 .write
= display_crc_ctl_write
3863 static void wm_latency_show(struct seq_file
*m
, const uint16_t wm
[8])
3865 struct drm_device
*dev
= m
->private;
3866 int num_levels
= ilk_wm_max_level(dev
) + 1;
3869 drm_modeset_lock_all(dev
);
3871 for (level
= 0; level
< num_levels
; level
++) {
3872 unsigned int latency
= wm
[level
];
3875 * - WM1+ latency values in 0.5us units
3876 * - latencies are in us on gen9
3878 if (INTEL_INFO(dev
)->gen
>= 9)
3883 seq_printf(m
, "WM%d %u (%u.%u usec)\n",
3884 level
, wm
[level
], latency
/ 10, latency
% 10);
3887 drm_modeset_unlock_all(dev
);
3890 static int pri_wm_latency_show(struct seq_file
*m
, void *data
)
3892 struct drm_device
*dev
= m
->private;
3893 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3894 const uint16_t *latencies
;
3896 if (INTEL_INFO(dev
)->gen
>= 9)
3897 latencies
= dev_priv
->wm
.skl_latency
;
3899 latencies
= to_i915(dev
)->wm
.pri_latency
;
3901 wm_latency_show(m
, latencies
);
3906 static int spr_wm_latency_show(struct seq_file
*m
, void *data
)
3908 struct drm_device
*dev
= m
->private;
3909 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3910 const uint16_t *latencies
;
3912 if (INTEL_INFO(dev
)->gen
>= 9)
3913 latencies
= dev_priv
->wm
.skl_latency
;
3915 latencies
= to_i915(dev
)->wm
.spr_latency
;
3917 wm_latency_show(m
, latencies
);
3922 static int cur_wm_latency_show(struct seq_file
*m
, void *data
)
3924 struct drm_device
*dev
= m
->private;
3925 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3926 const uint16_t *latencies
;
3928 if (INTEL_INFO(dev
)->gen
>= 9)
3929 latencies
= dev_priv
->wm
.skl_latency
;
3931 latencies
= to_i915(dev
)->wm
.cur_latency
;
3933 wm_latency_show(m
, latencies
);
3938 static int pri_wm_latency_open(struct inode
*inode
, struct file
*file
)
3940 struct drm_device
*dev
= inode
->i_private
;
3942 if (HAS_GMCH_DISPLAY(dev
))
3945 return single_open(file
, pri_wm_latency_show
, dev
);
3948 static int spr_wm_latency_open(struct inode
*inode
, struct file
*file
)
3950 struct drm_device
*dev
= inode
->i_private
;
3952 if (HAS_GMCH_DISPLAY(dev
))
3955 return single_open(file
, spr_wm_latency_show
, dev
);
3958 static int cur_wm_latency_open(struct inode
*inode
, struct file
*file
)
3960 struct drm_device
*dev
= inode
->i_private
;
3962 if (HAS_GMCH_DISPLAY(dev
))
3965 return single_open(file
, cur_wm_latency_show
, dev
);
3968 static ssize_t
wm_latency_write(struct file
*file
, const char __user
*ubuf
,
3969 size_t len
, loff_t
*offp
, uint16_t wm
[8])
3971 struct seq_file
*m
= file
->private_data
;
3972 struct drm_device
*dev
= m
->private;
3973 uint16_t new[8] = { 0 };
3974 int num_levels
= ilk_wm_max_level(dev
) + 1;
3979 if (len
>= sizeof(tmp
))
3982 if (copy_from_user(tmp
, ubuf
, len
))
3987 ret
= sscanf(tmp
, "%hu %hu %hu %hu %hu %hu %hu %hu",
3988 &new[0], &new[1], &new[2], &new[3],
3989 &new[4], &new[5], &new[6], &new[7]);
3990 if (ret
!= num_levels
)
3993 drm_modeset_lock_all(dev
);
3995 for (level
= 0; level
< num_levels
; level
++)
3996 wm
[level
] = new[level
];
3998 drm_modeset_unlock_all(dev
);
4004 static ssize_t
pri_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4005 size_t len
, loff_t
*offp
)
4007 struct seq_file
*m
= file
->private_data
;
4008 struct drm_device
*dev
= m
->private;
4009 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4010 uint16_t *latencies
;
4012 if (INTEL_INFO(dev
)->gen
>= 9)
4013 latencies
= dev_priv
->wm
.skl_latency
;
4015 latencies
= to_i915(dev
)->wm
.pri_latency
;
4017 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
4020 static ssize_t
spr_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4021 size_t len
, loff_t
*offp
)
4023 struct seq_file
*m
= file
->private_data
;
4024 struct drm_device
*dev
= m
->private;
4025 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4026 uint16_t *latencies
;
4028 if (INTEL_INFO(dev
)->gen
>= 9)
4029 latencies
= dev_priv
->wm
.skl_latency
;
4031 latencies
= to_i915(dev
)->wm
.spr_latency
;
4033 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
4036 static ssize_t
cur_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4037 size_t len
, loff_t
*offp
)
4039 struct seq_file
*m
= file
->private_data
;
4040 struct drm_device
*dev
= m
->private;
4041 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4042 uint16_t *latencies
;
4044 if (INTEL_INFO(dev
)->gen
>= 9)
4045 latencies
= dev_priv
->wm
.skl_latency
;
4047 latencies
= to_i915(dev
)->wm
.cur_latency
;
4049 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
4052 static const struct file_operations i915_pri_wm_latency_fops
= {
4053 .owner
= THIS_MODULE
,
4054 .open
= pri_wm_latency_open
,
4056 .llseek
= seq_lseek
,
4057 .release
= single_release
,
4058 .write
= pri_wm_latency_write
4061 static const struct file_operations i915_spr_wm_latency_fops
= {
4062 .owner
= THIS_MODULE
,
4063 .open
= spr_wm_latency_open
,
4065 .llseek
= seq_lseek
,
4066 .release
= single_release
,
4067 .write
= spr_wm_latency_write
4070 static const struct file_operations i915_cur_wm_latency_fops
= {
4071 .owner
= THIS_MODULE
,
4072 .open
= cur_wm_latency_open
,
4074 .llseek
= seq_lseek
,
4075 .release
= single_release
,
4076 .write
= cur_wm_latency_write
4080 i915_wedged_get(void *data
, u64
*val
)
4082 struct drm_device
*dev
= data
;
4083 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4085 *val
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
4091 i915_wedged_set(void *data
, u64 val
)
4093 struct drm_device
*dev
= data
;
4094 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4097 * There is no safeguard against this debugfs entry colliding
4098 * with the hangcheck calling same i915_handle_error() in
4099 * parallel, causing an explosion. For now we assume that the
4100 * test harness is responsible enough not to inject gpu hangs
4101 * while it is writing to 'i915_wedged'
4104 if (i915_reset_in_progress(&dev_priv
->gpu_error
))
4107 intel_runtime_pm_get(dev_priv
);
4109 i915_handle_error(dev
, val
,
4110 "Manually setting wedged to %llu", val
);
4112 intel_runtime_pm_put(dev_priv
);
4117 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops
,
4118 i915_wedged_get
, i915_wedged_set
,
4122 i915_ring_stop_get(void *data
, u64
*val
)
4124 struct drm_device
*dev
= data
;
4125 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4127 *val
= dev_priv
->gpu_error
.stop_rings
;
4133 i915_ring_stop_set(void *data
, u64 val
)
4135 struct drm_device
*dev
= data
;
4136 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4139 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val
);
4141 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4145 dev_priv
->gpu_error
.stop_rings
= val
;
4146 mutex_unlock(&dev
->struct_mutex
);
4151 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops
,
4152 i915_ring_stop_get
, i915_ring_stop_set
,
4156 i915_ring_missed_irq_get(void *data
, u64
*val
)
4158 struct drm_device
*dev
= data
;
4159 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4161 *val
= dev_priv
->gpu_error
.missed_irq_rings
;
4166 i915_ring_missed_irq_set(void *data
, u64 val
)
4168 struct drm_device
*dev
= data
;
4169 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4172 /* Lock against concurrent debugfs callers */
4173 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4176 dev_priv
->gpu_error
.missed_irq_rings
= val
;
4177 mutex_unlock(&dev
->struct_mutex
);
4182 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops
,
4183 i915_ring_missed_irq_get
, i915_ring_missed_irq_set
,
4187 i915_ring_test_irq_get(void *data
, u64
*val
)
4189 struct drm_device
*dev
= data
;
4190 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4192 *val
= dev_priv
->gpu_error
.test_irq_rings
;
4198 i915_ring_test_irq_set(void *data
, u64 val
)
4200 struct drm_device
*dev
= data
;
4201 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4204 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val
);
4206 /* Lock against concurrent debugfs callers */
4207 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4211 dev_priv
->gpu_error
.test_irq_rings
= val
;
4212 mutex_unlock(&dev
->struct_mutex
);
4217 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops
,
4218 i915_ring_test_irq_get
, i915_ring_test_irq_set
,
4221 #define DROP_UNBOUND 0x1
4222 #define DROP_BOUND 0x2
4223 #define DROP_RETIRE 0x4
4224 #define DROP_ACTIVE 0x8
4225 #define DROP_ALL (DROP_UNBOUND | \
4230 i915_drop_caches_get(void *data
, u64
*val
)
4238 i915_drop_caches_set(void *data
, u64 val
)
4240 struct drm_device
*dev
= data
;
4241 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4244 DRM_DEBUG("Dropping caches: 0x%08llx\n", val
);
4246 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4247 * on ioctls on -EAGAIN. */
4248 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4252 if (val
& DROP_ACTIVE
) {
4253 ret
= i915_gpu_idle(dev
);
4258 if (val
& (DROP_RETIRE
| DROP_ACTIVE
))
4259 i915_gem_retire_requests(dev
);
4261 if (val
& DROP_BOUND
)
4262 i915_gem_shrink(dev_priv
, LONG_MAX
, I915_SHRINK_BOUND
);
4264 if (val
& DROP_UNBOUND
)
4265 i915_gem_shrink(dev_priv
, LONG_MAX
, I915_SHRINK_UNBOUND
);
4268 mutex_unlock(&dev
->struct_mutex
);
4273 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops
,
4274 i915_drop_caches_get
, i915_drop_caches_set
,
4278 i915_max_freq_get(void *data
, u64
*val
)
4280 struct drm_device
*dev
= data
;
4281 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4284 if (INTEL_INFO(dev
)->gen
< 6)
4287 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4289 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4293 *val
= intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq_softlimit
);
4294 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4300 i915_max_freq_set(void *data
, u64 val
)
4302 struct drm_device
*dev
= data
;
4303 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4307 if (INTEL_INFO(dev
)->gen
< 6)
4310 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4312 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val
);
4314 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4319 * Turbo will still be enabled, but won't go above the set value.
4321 val
= intel_freq_opcode(dev_priv
, val
);
4323 hw_max
= dev_priv
->rps
.max_freq
;
4324 hw_min
= dev_priv
->rps
.min_freq
;
4326 if (val
< hw_min
|| val
> hw_max
|| val
< dev_priv
->rps
.min_freq_softlimit
) {
4327 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4331 dev_priv
->rps
.max_freq_softlimit
= val
;
4333 intel_set_rps(dev
, val
);
4335 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4340 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops
,
4341 i915_max_freq_get
, i915_max_freq_set
,
4345 i915_min_freq_get(void *data
, u64
*val
)
4347 struct drm_device
*dev
= data
;
4348 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4351 if (INTEL_INFO(dev
)->gen
< 6)
4354 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4356 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4360 *val
= intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq_softlimit
);
4361 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4367 i915_min_freq_set(void *data
, u64 val
)
4369 struct drm_device
*dev
= data
;
4370 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4374 if (INTEL_INFO(dev
)->gen
< 6)
4377 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4379 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val
);
4381 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4386 * Turbo will still be enabled, but won't go below the set value.
4388 val
= intel_freq_opcode(dev_priv
, val
);
4390 hw_max
= dev_priv
->rps
.max_freq
;
4391 hw_min
= dev_priv
->rps
.min_freq
;
4393 if (val
< hw_min
|| val
> hw_max
|| val
> dev_priv
->rps
.max_freq_softlimit
) {
4394 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4398 dev_priv
->rps
.min_freq_softlimit
= val
;
4400 intel_set_rps(dev
, val
);
4402 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4407 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops
,
4408 i915_min_freq_get
, i915_min_freq_set
,
4412 i915_cache_sharing_get(void *data
, u64
*val
)
4414 struct drm_device
*dev
= data
;
4415 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4419 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
4422 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4425 intel_runtime_pm_get(dev_priv
);
4427 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
4429 intel_runtime_pm_put(dev_priv
);
4430 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
4432 *val
= (snpcr
& GEN6_MBC_SNPCR_MASK
) >> GEN6_MBC_SNPCR_SHIFT
;
4438 i915_cache_sharing_set(void *data
, u64 val
)
4440 struct drm_device
*dev
= data
;
4441 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4444 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
4450 intel_runtime_pm_get(dev_priv
);
4451 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val
);
4453 /* Update the cache sharing policy here as well */
4454 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
4455 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
4456 snpcr
|= (val
<< GEN6_MBC_SNPCR_SHIFT
);
4457 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
4459 intel_runtime_pm_put(dev_priv
);
4463 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops
,
4464 i915_cache_sharing_get
, i915_cache_sharing_set
,
4467 static int i915_sseu_status(struct seq_file
*m
, void *unused
)
4469 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
4470 struct drm_device
*dev
= node
->minor
->dev
;
4471 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4472 unsigned int s_tot
= 0, ss_tot
= 0, ss_per
= 0, eu_tot
= 0, eu_per
= 0;
4474 if ((INTEL_INFO(dev
)->gen
< 8) || IS_BROADWELL(dev
))
4477 seq_puts(m
, "SSEU Device Info\n");
4478 seq_printf(m
, " Available Slice Total: %u\n",
4479 INTEL_INFO(dev
)->slice_total
);
4480 seq_printf(m
, " Available Subslice Total: %u\n",
4481 INTEL_INFO(dev
)->subslice_total
);
4482 seq_printf(m
, " Available Subslice Per Slice: %u\n",
4483 INTEL_INFO(dev
)->subslice_per_slice
);
4484 seq_printf(m
, " Available EU Total: %u\n",
4485 INTEL_INFO(dev
)->eu_total
);
4486 seq_printf(m
, " Available EU Per Subslice: %u\n",
4487 INTEL_INFO(dev
)->eu_per_subslice
);
4488 seq_printf(m
, " Has Slice Power Gating: %s\n",
4489 yesno(INTEL_INFO(dev
)->has_slice_pg
));
4490 seq_printf(m
, " Has Subslice Power Gating: %s\n",
4491 yesno(INTEL_INFO(dev
)->has_subslice_pg
));
4492 seq_printf(m
, " Has EU Power Gating: %s\n",
4493 yesno(INTEL_INFO(dev
)->has_eu_pg
));
4495 seq_puts(m
, "SSEU Device Status\n");
4496 if (IS_CHERRYVIEW(dev
)) {
4497 const int ss_max
= 2;
4499 u32 sig1
[ss_max
], sig2
[ss_max
];
4501 sig1
[0] = I915_READ(CHV_POWER_SS0_SIG1
);
4502 sig1
[1] = I915_READ(CHV_POWER_SS1_SIG1
);
4503 sig2
[0] = I915_READ(CHV_POWER_SS0_SIG2
);
4504 sig2
[1] = I915_READ(CHV_POWER_SS1_SIG2
);
4506 for (ss
= 0; ss
< ss_max
; ss
++) {
4507 unsigned int eu_cnt
;
4509 if (sig1
[ss
] & CHV_SS_PG_ENABLE
)
4510 /* skip disabled subslice */
4515 eu_cnt
= ((sig1
[ss
] & CHV_EU08_PG_ENABLE
) ? 0 : 2) +
4516 ((sig1
[ss
] & CHV_EU19_PG_ENABLE
) ? 0 : 2) +
4517 ((sig1
[ss
] & CHV_EU210_PG_ENABLE
) ? 0 : 2) +
4518 ((sig2
[ss
] & CHV_EU311_PG_ENABLE
) ? 0 : 2);
4520 eu_per
= max(eu_per
, eu_cnt
);
4523 } else if (IS_SKYLAKE(dev
)) {
4524 const int s_max
= 3, ss_max
= 4;
4526 u32 s_reg
[s_max
], eu_reg
[2*s_max
], eu_mask
[2];
4528 s_reg
[0] = I915_READ(GEN9_SLICE0_PGCTL_ACK
);
4529 s_reg
[1] = I915_READ(GEN9_SLICE1_PGCTL_ACK
);
4530 s_reg
[2] = I915_READ(GEN9_SLICE2_PGCTL_ACK
);
4531 eu_reg
[0] = I915_READ(GEN9_SLICE0_SS01_EU_PGCTL_ACK
);
4532 eu_reg
[1] = I915_READ(GEN9_SLICE0_SS23_EU_PGCTL_ACK
);
4533 eu_reg
[2] = I915_READ(GEN9_SLICE1_SS01_EU_PGCTL_ACK
);
4534 eu_reg
[3] = I915_READ(GEN9_SLICE1_SS23_EU_PGCTL_ACK
);
4535 eu_reg
[4] = I915_READ(GEN9_SLICE2_SS01_EU_PGCTL_ACK
);
4536 eu_reg
[5] = I915_READ(GEN9_SLICE2_SS23_EU_PGCTL_ACK
);
4537 eu_mask
[0] = GEN9_PGCTL_SSA_EU08_ACK
|
4538 GEN9_PGCTL_SSA_EU19_ACK
|
4539 GEN9_PGCTL_SSA_EU210_ACK
|
4540 GEN9_PGCTL_SSA_EU311_ACK
;
4541 eu_mask
[1] = GEN9_PGCTL_SSB_EU08_ACK
|
4542 GEN9_PGCTL_SSB_EU19_ACK
|
4543 GEN9_PGCTL_SSB_EU210_ACK
|
4544 GEN9_PGCTL_SSB_EU311_ACK
;
4546 for (s
= 0; s
< s_max
; s
++) {
4547 if ((s_reg
[s
] & GEN9_PGCTL_SLICE_ACK
) == 0)
4548 /* skip disabled slice */
4552 ss_per
= INTEL_INFO(dev
)->subslice_per_slice
;
4554 for (ss
= 0; ss
< ss_max
; ss
++) {
4555 unsigned int eu_cnt
;
4557 eu_cnt
= 2 * hweight32(eu_reg
[2*s
+ ss
/2] &
4560 eu_per
= max(eu_per
, eu_cnt
);
4564 seq_printf(m
, " Enabled Slice Total: %u\n", s_tot
);
4565 seq_printf(m
, " Enabled Subslice Total: %u\n", ss_tot
);
4566 seq_printf(m
, " Enabled Subslice Per Slice: %u\n", ss_per
);
4567 seq_printf(m
, " Enabled EU Total: %u\n", eu_tot
);
4568 seq_printf(m
, " Enabled EU Per Subslice: %u\n", eu_per
);
4573 static int i915_forcewake_open(struct inode
*inode
, struct file
*file
)
4575 struct drm_device
*dev
= inode
->i_private
;
4576 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4578 if (INTEL_INFO(dev
)->gen
< 6)
4581 intel_runtime_pm_get(dev_priv
);
4582 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4587 static int i915_forcewake_release(struct inode
*inode
, struct file
*file
)
4589 struct drm_device
*dev
= inode
->i_private
;
4590 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4592 if (INTEL_INFO(dev
)->gen
< 6)
4595 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4596 intel_runtime_pm_put(dev_priv
);
4601 static const struct file_operations i915_forcewake_fops
= {
4602 .owner
= THIS_MODULE
,
4603 .open
= i915_forcewake_open
,
4604 .release
= i915_forcewake_release
,
4607 static int i915_forcewake_create(struct dentry
*root
, struct drm_minor
*minor
)
4609 struct drm_device
*dev
= minor
->dev
;
4612 ent
= debugfs_create_file("i915_forcewake_user",
4615 &i915_forcewake_fops
);
4619 return drm_add_fake_info_node(minor
, ent
, &i915_forcewake_fops
);
4622 static int i915_debugfs_create(struct dentry
*root
,
4623 struct drm_minor
*minor
,
4625 const struct file_operations
*fops
)
4627 struct drm_device
*dev
= minor
->dev
;
4630 ent
= debugfs_create_file(name
,
4637 return drm_add_fake_info_node(minor
, ent
, fops
);
4640 static const struct drm_info_list i915_debugfs_list
[] = {
4641 {"i915_capabilities", i915_capabilities
, 0},
4642 {"i915_gem_objects", i915_gem_object_info
, 0},
4643 {"i915_gem_gtt", i915_gem_gtt_info
, 0},
4644 {"i915_gem_pinned", i915_gem_gtt_info
, 0, (void *) PINNED_LIST
},
4645 {"i915_gem_active", i915_gem_object_list_info
, 0, (void *) ACTIVE_LIST
},
4646 {"i915_gem_inactive", i915_gem_object_list_info
, 0, (void *) INACTIVE_LIST
},
4647 {"i915_gem_stolen", i915_gem_stolen_list_info
},
4648 {"i915_gem_pageflip", i915_gem_pageflip_info
, 0},
4649 {"i915_gem_request", i915_gem_request_info
, 0},
4650 {"i915_gem_seqno", i915_gem_seqno_info
, 0},
4651 {"i915_gem_fence_regs", i915_gem_fence_regs_info
, 0},
4652 {"i915_gem_interrupt", i915_interrupt_info
, 0},
4653 {"i915_gem_hws", i915_hws_info
, 0, (void *)RCS
},
4654 {"i915_gem_hws_blt", i915_hws_info
, 0, (void *)BCS
},
4655 {"i915_gem_hws_bsd", i915_hws_info
, 0, (void *)VCS
},
4656 {"i915_gem_hws_vebox", i915_hws_info
, 0, (void *)VECS
},
4657 {"i915_gem_batch_pool", i915_gem_batch_pool_info
, 0},
4658 {"i915_frequency_info", i915_frequency_info
, 0},
4659 {"i915_hangcheck_info", i915_hangcheck_info
, 0},
4660 {"i915_drpc_info", i915_drpc_info
, 0},
4661 {"i915_emon_status", i915_emon_status
, 0},
4662 {"i915_ring_freq_table", i915_ring_freq_table
, 0},
4663 {"i915_fbc_status", i915_fbc_status
, 0},
4664 {"i915_ips_status", i915_ips_status
, 0},
4665 {"i915_sr_status", i915_sr_status
, 0},
4666 {"i915_opregion", i915_opregion
, 0},
4667 {"i915_gem_framebuffer", i915_gem_framebuffer_info
, 0},
4668 {"i915_context_status", i915_context_status
, 0},
4669 {"i915_dump_lrc", i915_dump_lrc
, 0},
4670 {"i915_execlists", i915_execlists
, 0},
4671 {"i915_forcewake_domains", i915_forcewake_domains
, 0},
4672 {"i915_swizzle_info", i915_swizzle_info
, 0},
4673 {"i915_ppgtt_info", i915_ppgtt_info
, 0},
4674 {"i915_llc", i915_llc
, 0},
4675 {"i915_edp_psr_status", i915_edp_psr_status
, 0},
4676 {"i915_sink_crc_eDP1", i915_sink_crc
, 0},
4677 {"i915_energy_uJ", i915_energy_uJ
, 0},
4678 {"i915_pc8_status", i915_pc8_status
, 0},
4679 {"i915_power_domain_info", i915_power_domain_info
, 0},
4680 {"i915_display_info", i915_display_info
, 0},
4681 {"i915_semaphore_status", i915_semaphore_status
, 0},
4682 {"i915_shared_dplls_info", i915_shared_dplls_info
, 0},
4683 {"i915_dp_mst_info", i915_dp_mst_info
, 0},
4684 {"i915_wa_registers", i915_wa_registers
, 0},
4685 {"i915_ddb_info", i915_ddb_info
, 0},
4686 {"i915_sseu_status", i915_sseu_status
, 0},
4687 {"i915_drrs_status", i915_drrs_status
, 0},
4689 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
4691 static const struct i915_debugfs_files
{
4693 const struct file_operations
*fops
;
4694 } i915_debugfs_files
[] = {
4695 {"i915_wedged", &i915_wedged_fops
},
4696 {"i915_max_freq", &i915_max_freq_fops
},
4697 {"i915_min_freq", &i915_min_freq_fops
},
4698 {"i915_cache_sharing", &i915_cache_sharing_fops
},
4699 {"i915_ring_stop", &i915_ring_stop_fops
},
4700 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops
},
4701 {"i915_ring_test_irq", &i915_ring_test_irq_fops
},
4702 {"i915_gem_drop_caches", &i915_drop_caches_fops
},
4703 {"i915_error_state", &i915_error_state_fops
},
4704 {"i915_next_seqno", &i915_next_seqno_fops
},
4705 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops
},
4706 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops
},
4707 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops
},
4708 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops
},
4709 {"i915_fbc_false_color", &i915_fbc_fc_fops
},
4712 void intel_display_crc_init(struct drm_device
*dev
)
4714 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4717 for_each_pipe(dev_priv
, pipe
) {
4718 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
4720 pipe_crc
->opened
= false;
4721 spin_lock_init(&pipe_crc
->lock
);
4722 init_waitqueue_head(&pipe_crc
->wq
);
4726 int i915_debugfs_init(struct drm_minor
*minor
)
4730 ret
= i915_forcewake_create(minor
->debugfs_root
, minor
);
4734 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
4735 ret
= i915_pipe_crc_create(minor
->debugfs_root
, minor
, i
);
4740 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
4741 ret
= i915_debugfs_create(minor
->debugfs_root
, minor
,
4742 i915_debugfs_files
[i
].name
,
4743 i915_debugfs_files
[i
].fops
);
4748 return drm_debugfs_create_files(i915_debugfs_list
,
4749 I915_DEBUGFS_ENTRIES
,
4750 minor
->debugfs_root
, minor
);
4753 void i915_debugfs_cleanup(struct drm_minor
*minor
)
4757 drm_debugfs_remove_files(i915_debugfs_list
,
4758 I915_DEBUGFS_ENTRIES
, minor
);
4760 drm_debugfs_remove_files((struct drm_info_list
*) &i915_forcewake_fops
,
4763 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
4764 struct drm_info_list
*info_list
=
4765 (struct drm_info_list
*)&i915_pipe_crc_data
[i
];
4767 drm_debugfs_remove_files(info_list
, 1, minor
);
4770 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
4771 struct drm_info_list
*info_list
=
4772 (struct drm_info_list
*) i915_debugfs_files
[i
].fops
;
4774 drm_debugfs_remove_files(info_list
, 1, minor
);