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drm/i915: Include engine->last_submitted_seqno in GPU error state
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
37 #include <drm/drmP.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
41 #include "i915_drv.h"
42
43 enum {
44 ACTIVE_LIST,
45 INACTIVE_LIST,
46 PINNED_LIST,
47 };
48
49 /* As the drm_debugfs_init() routines are called before dev->dev_private is
50 * allocated we need to hook into the minor for release. */
51 static int
52 drm_add_fake_info_node(struct drm_minor *minor,
53 struct dentry *ent,
54 const void *key)
55 {
56 struct drm_info_node *node;
57
58 node = kmalloc(sizeof(*node), GFP_KERNEL);
59 if (node == NULL) {
60 debugfs_remove(ent);
61 return -ENOMEM;
62 }
63
64 node->minor = minor;
65 node->dent = ent;
66 node->info_ent = (void *) key;
67
68 mutex_lock(&minor->debugfs_lock);
69 list_add(&node->list, &minor->debugfs_list);
70 mutex_unlock(&minor->debugfs_lock);
71
72 return 0;
73 }
74
75 static int i915_capabilities(struct seq_file *m, void *data)
76 {
77 struct drm_info_node *node = m->private;
78 struct drm_device *dev = node->minor->dev;
79 const struct intel_device_info *info = INTEL_INFO(dev);
80
81 seq_printf(m, "gen: %d\n", info->gen);
82 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
83 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
84 #define SEP_SEMICOLON ;
85 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
86 #undef PRINT_FLAG
87 #undef SEP_SEMICOLON
88
89 return 0;
90 }
91
92 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
93 {
94 if (obj->pin_display)
95 return "p";
96 else
97 return " ";
98 }
99
100 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
101 {
102 switch (obj->tiling_mode) {
103 default:
104 case I915_TILING_NONE: return " ";
105 case I915_TILING_X: return "X";
106 case I915_TILING_Y: return "Y";
107 }
108 }
109
110 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
111 {
112 return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
113 }
114
115 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
116 {
117 u64 size = 0;
118 struct i915_vma *vma;
119
120 list_for_each_entry(vma, &obj->vma_list, obj_link) {
121 if (vma->is_ggtt && drm_mm_node_allocated(&vma->node))
122 size += vma->node.size;
123 }
124
125 return size;
126 }
127
128 static void
129 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
130 {
131 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
132 struct intel_engine_cs *engine;
133 struct i915_vma *vma;
134 int pin_count = 0;
135 enum intel_engine_id id;
136
137 lockdep_assert_held(&obj->base.dev->struct_mutex);
138
139 seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ",
140 &obj->base,
141 obj->active ? "*" : " ",
142 get_pin_flag(obj),
143 get_tiling_flag(obj),
144 get_global_flag(obj),
145 obj->base.size / 1024,
146 obj->base.read_domains,
147 obj->base.write_domain);
148 for_each_engine_id(engine, dev_priv, id)
149 seq_printf(m, "%x ",
150 i915_gem_request_get_seqno(obj->last_read_req[id]));
151 seq_printf(m, "] %x %x%s%s%s",
152 i915_gem_request_get_seqno(obj->last_write_req),
153 i915_gem_request_get_seqno(obj->last_fenced_req),
154 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
155 obj->dirty ? " dirty" : "",
156 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
157 if (obj->base.name)
158 seq_printf(m, " (name: %d)", obj->base.name);
159 list_for_each_entry(vma, &obj->vma_list, obj_link) {
160 if (vma->pin_count > 0)
161 pin_count++;
162 }
163 seq_printf(m, " (pinned x %d)", pin_count);
164 if (obj->pin_display)
165 seq_printf(m, " (display)");
166 if (obj->fence_reg != I915_FENCE_REG_NONE)
167 seq_printf(m, " (fence: %d)", obj->fence_reg);
168 list_for_each_entry(vma, &obj->vma_list, obj_link) {
169 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
170 vma->is_ggtt ? "g" : "pp",
171 vma->node.start, vma->node.size);
172 if (vma->is_ggtt)
173 seq_printf(m, ", type: %u", vma->ggtt_view.type);
174 seq_puts(m, ")");
175 }
176 if (obj->stolen)
177 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
178 if (obj->pin_display || obj->fault_mappable) {
179 char s[3], *t = s;
180 if (obj->pin_display)
181 *t++ = 'p';
182 if (obj->fault_mappable)
183 *t++ = 'f';
184 *t = '\0';
185 seq_printf(m, " (%s mappable)", s);
186 }
187 if (obj->last_write_req != NULL)
188 seq_printf(m, " (%s)",
189 i915_gem_request_get_engine(obj->last_write_req)->name);
190 if (obj->frontbuffer_bits)
191 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
192 }
193
194 static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
195 {
196 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
197 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
198 seq_putc(m, ' ');
199 }
200
201 static int i915_gem_object_list_info(struct seq_file *m, void *data)
202 {
203 struct drm_info_node *node = m->private;
204 uintptr_t list = (uintptr_t) node->info_ent->data;
205 struct list_head *head;
206 struct drm_device *dev = node->minor->dev;
207 struct drm_i915_private *dev_priv = to_i915(dev);
208 struct i915_ggtt *ggtt = &dev_priv->ggtt;
209 struct i915_vma *vma;
210 u64 total_obj_size, total_gtt_size;
211 int count, ret;
212
213 ret = mutex_lock_interruptible(&dev->struct_mutex);
214 if (ret)
215 return ret;
216
217 /* FIXME: the user of this interface might want more than just GGTT */
218 switch (list) {
219 case ACTIVE_LIST:
220 seq_puts(m, "Active:\n");
221 head = &ggtt->base.active_list;
222 break;
223 case INACTIVE_LIST:
224 seq_puts(m, "Inactive:\n");
225 head = &ggtt->base.inactive_list;
226 break;
227 default:
228 mutex_unlock(&dev->struct_mutex);
229 return -EINVAL;
230 }
231
232 total_obj_size = total_gtt_size = count = 0;
233 list_for_each_entry(vma, head, vm_link) {
234 seq_printf(m, " ");
235 describe_obj(m, vma->obj);
236 seq_printf(m, "\n");
237 total_obj_size += vma->obj->base.size;
238 total_gtt_size += vma->node.size;
239 count++;
240 }
241 mutex_unlock(&dev->struct_mutex);
242
243 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
244 count, total_obj_size, total_gtt_size);
245 return 0;
246 }
247
248 static int obj_rank_by_stolen(void *priv,
249 struct list_head *A, struct list_head *B)
250 {
251 struct drm_i915_gem_object *a =
252 container_of(A, struct drm_i915_gem_object, obj_exec_link);
253 struct drm_i915_gem_object *b =
254 container_of(B, struct drm_i915_gem_object, obj_exec_link);
255
256 if (a->stolen->start < b->stolen->start)
257 return -1;
258 if (a->stolen->start > b->stolen->start)
259 return 1;
260 return 0;
261 }
262
263 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
264 {
265 struct drm_info_node *node = m->private;
266 struct drm_device *dev = node->minor->dev;
267 struct drm_i915_private *dev_priv = dev->dev_private;
268 struct drm_i915_gem_object *obj;
269 u64 total_obj_size, total_gtt_size;
270 LIST_HEAD(stolen);
271 int count, ret;
272
273 ret = mutex_lock_interruptible(&dev->struct_mutex);
274 if (ret)
275 return ret;
276
277 total_obj_size = total_gtt_size = count = 0;
278 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
279 if (obj->stolen == NULL)
280 continue;
281
282 list_add(&obj->obj_exec_link, &stolen);
283
284 total_obj_size += obj->base.size;
285 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
286 count++;
287 }
288 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
289 if (obj->stolen == NULL)
290 continue;
291
292 list_add(&obj->obj_exec_link, &stolen);
293
294 total_obj_size += obj->base.size;
295 count++;
296 }
297 list_sort(NULL, &stolen, obj_rank_by_stolen);
298 seq_puts(m, "Stolen:\n");
299 while (!list_empty(&stolen)) {
300 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
301 seq_puts(m, " ");
302 describe_obj(m, obj);
303 seq_putc(m, '\n');
304 list_del_init(&obj->obj_exec_link);
305 }
306 mutex_unlock(&dev->struct_mutex);
307
308 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
309 count, total_obj_size, total_gtt_size);
310 return 0;
311 }
312
313 #define count_objects(list, member) do { \
314 list_for_each_entry(obj, list, member) { \
315 size += i915_gem_obj_total_ggtt_size(obj); \
316 ++count; \
317 if (obj->map_and_fenceable) { \
318 mappable_size += i915_gem_obj_ggtt_size(obj); \
319 ++mappable_count; \
320 } \
321 } \
322 } while (0)
323
324 struct file_stats {
325 struct drm_i915_file_private *file_priv;
326 unsigned long count;
327 u64 total, unbound;
328 u64 global, shared;
329 u64 active, inactive;
330 };
331
332 static int per_file_stats(int id, void *ptr, void *data)
333 {
334 struct drm_i915_gem_object *obj = ptr;
335 struct file_stats *stats = data;
336 struct i915_vma *vma;
337
338 stats->count++;
339 stats->total += obj->base.size;
340
341 if (obj->base.name || obj->base.dma_buf)
342 stats->shared += obj->base.size;
343
344 if (USES_FULL_PPGTT(obj->base.dev)) {
345 list_for_each_entry(vma, &obj->vma_list, obj_link) {
346 struct i915_hw_ppgtt *ppgtt;
347
348 if (!drm_mm_node_allocated(&vma->node))
349 continue;
350
351 if (vma->is_ggtt) {
352 stats->global += obj->base.size;
353 continue;
354 }
355
356 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
357 if (ppgtt->file_priv != stats->file_priv)
358 continue;
359
360 if (obj->active) /* XXX per-vma statistic */
361 stats->active += obj->base.size;
362 else
363 stats->inactive += obj->base.size;
364
365 return 0;
366 }
367 } else {
368 if (i915_gem_obj_ggtt_bound(obj)) {
369 stats->global += obj->base.size;
370 if (obj->active)
371 stats->active += obj->base.size;
372 else
373 stats->inactive += obj->base.size;
374 return 0;
375 }
376 }
377
378 if (!list_empty(&obj->global_list))
379 stats->unbound += obj->base.size;
380
381 return 0;
382 }
383
384 #define print_file_stats(m, name, stats) do { \
385 if (stats.count) \
386 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
387 name, \
388 stats.count, \
389 stats.total, \
390 stats.active, \
391 stats.inactive, \
392 stats.global, \
393 stats.shared, \
394 stats.unbound); \
395 } while (0)
396
397 static void print_batch_pool_stats(struct seq_file *m,
398 struct drm_i915_private *dev_priv)
399 {
400 struct drm_i915_gem_object *obj;
401 struct file_stats stats;
402 struct intel_engine_cs *engine;
403 int j;
404
405 memset(&stats, 0, sizeof(stats));
406
407 for_each_engine(engine, dev_priv) {
408 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
409 list_for_each_entry(obj,
410 &engine->batch_pool.cache_list[j],
411 batch_pool_link)
412 per_file_stats(0, obj, &stats);
413 }
414 }
415
416 print_file_stats(m, "[k]batch pool", stats);
417 }
418
419 #define count_vmas(list, member) do { \
420 list_for_each_entry(vma, list, member) { \
421 size += i915_gem_obj_total_ggtt_size(vma->obj); \
422 ++count; \
423 if (vma->obj->map_and_fenceable) { \
424 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
425 ++mappable_count; \
426 } \
427 } \
428 } while (0)
429
430 static int i915_gem_object_info(struct seq_file *m, void* data)
431 {
432 struct drm_info_node *node = m->private;
433 struct drm_device *dev = node->minor->dev;
434 struct drm_i915_private *dev_priv = to_i915(dev);
435 struct i915_ggtt *ggtt = &dev_priv->ggtt;
436 u32 count, mappable_count, purgeable_count;
437 u64 size, mappable_size, purgeable_size;
438 struct drm_i915_gem_object *obj;
439 struct drm_file *file;
440 struct i915_vma *vma;
441 int ret;
442
443 ret = mutex_lock_interruptible(&dev->struct_mutex);
444 if (ret)
445 return ret;
446
447 seq_printf(m, "%u objects, %zu bytes\n",
448 dev_priv->mm.object_count,
449 dev_priv->mm.object_memory);
450
451 size = count = mappable_size = mappable_count = 0;
452 count_objects(&dev_priv->mm.bound_list, global_list);
453 seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
454 count, mappable_count, size, mappable_size);
455
456 size = count = mappable_size = mappable_count = 0;
457 count_vmas(&ggtt->base.active_list, vm_link);
458 seq_printf(m, " %u [%u] active objects, %llu [%llu] bytes\n",
459 count, mappable_count, size, mappable_size);
460
461 size = count = mappable_size = mappable_count = 0;
462 count_vmas(&ggtt->base.inactive_list, vm_link);
463 seq_printf(m, " %u [%u] inactive objects, %llu [%llu] bytes\n",
464 count, mappable_count, size, mappable_size);
465
466 size = count = purgeable_size = purgeable_count = 0;
467 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
468 size += obj->base.size, ++count;
469 if (obj->madv == I915_MADV_DONTNEED)
470 purgeable_size += obj->base.size, ++purgeable_count;
471 }
472 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
473
474 size = count = mappable_size = mappable_count = 0;
475 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
476 if (obj->fault_mappable) {
477 size += i915_gem_obj_ggtt_size(obj);
478 ++count;
479 }
480 if (obj->pin_display) {
481 mappable_size += i915_gem_obj_ggtt_size(obj);
482 ++mappable_count;
483 }
484 if (obj->madv == I915_MADV_DONTNEED) {
485 purgeable_size += obj->base.size;
486 ++purgeable_count;
487 }
488 }
489 seq_printf(m, "%u purgeable objects, %llu bytes\n",
490 purgeable_count, purgeable_size);
491 seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
492 mappable_count, mappable_size);
493 seq_printf(m, "%u fault mappable objects, %llu bytes\n",
494 count, size);
495
496 seq_printf(m, "%llu [%llu] gtt total\n",
497 ggtt->base.total, ggtt->mappable_end - ggtt->base.start);
498
499 seq_putc(m, '\n');
500 print_batch_pool_stats(m, dev_priv);
501 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
502 struct file_stats stats;
503 struct task_struct *task;
504
505 memset(&stats, 0, sizeof(stats));
506 stats.file_priv = file->driver_priv;
507 spin_lock(&file->table_lock);
508 idr_for_each(&file->object_idr, per_file_stats, &stats);
509 spin_unlock(&file->table_lock);
510 /*
511 * Although we have a valid reference on file->pid, that does
512 * not guarantee that the task_struct who called get_pid() is
513 * still alive (e.g. get_pid(current) => fork() => exit()).
514 * Therefore, we need to protect this ->comm access using RCU.
515 */
516 rcu_read_lock();
517 task = pid_task(file->pid, PIDTYPE_PID);
518 print_file_stats(m, task ? task->comm : "<unknown>", stats);
519 rcu_read_unlock();
520 }
521
522 mutex_unlock(&dev->struct_mutex);
523
524 return 0;
525 }
526
527 static int i915_gem_gtt_info(struct seq_file *m, void *data)
528 {
529 struct drm_info_node *node = m->private;
530 struct drm_device *dev = node->minor->dev;
531 uintptr_t list = (uintptr_t) node->info_ent->data;
532 struct drm_i915_private *dev_priv = dev->dev_private;
533 struct drm_i915_gem_object *obj;
534 u64 total_obj_size, total_gtt_size;
535 int count, ret;
536
537 ret = mutex_lock_interruptible(&dev->struct_mutex);
538 if (ret)
539 return ret;
540
541 total_obj_size = total_gtt_size = count = 0;
542 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
543 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
544 continue;
545
546 seq_puts(m, " ");
547 describe_obj(m, obj);
548 seq_putc(m, '\n');
549 total_obj_size += obj->base.size;
550 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
551 count++;
552 }
553
554 mutex_unlock(&dev->struct_mutex);
555
556 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
557 count, total_obj_size, total_gtt_size);
558
559 return 0;
560 }
561
562 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
563 {
564 struct drm_info_node *node = m->private;
565 struct drm_device *dev = node->minor->dev;
566 struct drm_i915_private *dev_priv = dev->dev_private;
567 struct intel_crtc *crtc;
568 int ret;
569
570 ret = mutex_lock_interruptible(&dev->struct_mutex);
571 if (ret)
572 return ret;
573
574 for_each_intel_crtc(dev, crtc) {
575 const char pipe = pipe_name(crtc->pipe);
576 const char plane = plane_name(crtc->plane);
577 struct intel_unpin_work *work;
578
579 spin_lock_irq(&dev->event_lock);
580 work = crtc->unpin_work;
581 if (work == NULL) {
582 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
583 pipe, plane);
584 } else {
585 u32 addr;
586
587 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
588 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
589 pipe, plane);
590 } else {
591 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
592 pipe, plane);
593 }
594 if (work->flip_queued_req) {
595 struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req);
596
597 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
598 engine->name,
599 i915_gem_request_get_seqno(work->flip_queued_req),
600 dev_priv->next_seqno,
601 engine->get_seqno(engine, true),
602 i915_gem_request_completed(work->flip_queued_req, true));
603 } else
604 seq_printf(m, "Flip not associated with any ring\n");
605 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
606 work->flip_queued_vblank,
607 work->flip_ready_vblank,
608 drm_crtc_vblank_count(&crtc->base));
609 if (work->enable_stall_check)
610 seq_puts(m, "Stall check enabled, ");
611 else
612 seq_puts(m, "Stall check waiting for page flip ioctl, ");
613 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
614
615 if (INTEL_INFO(dev)->gen >= 4)
616 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
617 else
618 addr = I915_READ(DSPADDR(crtc->plane));
619 seq_printf(m, "Current scanout address 0x%08x\n", addr);
620
621 if (work->pending_flip_obj) {
622 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
623 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
624 }
625 }
626 spin_unlock_irq(&dev->event_lock);
627 }
628
629 mutex_unlock(&dev->struct_mutex);
630
631 return 0;
632 }
633
634 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
635 {
636 struct drm_info_node *node = m->private;
637 struct drm_device *dev = node->minor->dev;
638 struct drm_i915_private *dev_priv = dev->dev_private;
639 struct drm_i915_gem_object *obj;
640 struct intel_engine_cs *engine;
641 int total = 0;
642 int ret, j;
643
644 ret = mutex_lock_interruptible(&dev->struct_mutex);
645 if (ret)
646 return ret;
647
648 for_each_engine(engine, dev_priv) {
649 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
650 int count;
651
652 count = 0;
653 list_for_each_entry(obj,
654 &engine->batch_pool.cache_list[j],
655 batch_pool_link)
656 count++;
657 seq_printf(m, "%s cache[%d]: %d objects\n",
658 engine->name, j, count);
659
660 list_for_each_entry(obj,
661 &engine->batch_pool.cache_list[j],
662 batch_pool_link) {
663 seq_puts(m, " ");
664 describe_obj(m, obj);
665 seq_putc(m, '\n');
666 }
667
668 total += count;
669 }
670 }
671
672 seq_printf(m, "total: %d\n", total);
673
674 mutex_unlock(&dev->struct_mutex);
675
676 return 0;
677 }
678
679 static int i915_gem_request_info(struct seq_file *m, void *data)
680 {
681 struct drm_info_node *node = m->private;
682 struct drm_device *dev = node->minor->dev;
683 struct drm_i915_private *dev_priv = dev->dev_private;
684 struct intel_engine_cs *engine;
685 struct drm_i915_gem_request *req;
686 int ret, any;
687
688 ret = mutex_lock_interruptible(&dev->struct_mutex);
689 if (ret)
690 return ret;
691
692 any = 0;
693 for_each_engine(engine, dev_priv) {
694 int count;
695
696 count = 0;
697 list_for_each_entry(req, &engine->request_list, list)
698 count++;
699 if (count == 0)
700 continue;
701
702 seq_printf(m, "%s requests: %d\n", engine->name, count);
703 list_for_each_entry(req, &engine->request_list, list) {
704 struct task_struct *task;
705
706 rcu_read_lock();
707 task = NULL;
708 if (req->pid)
709 task = pid_task(req->pid, PIDTYPE_PID);
710 seq_printf(m, " %x @ %d: %s [%d]\n",
711 req->seqno,
712 (int) (jiffies - req->emitted_jiffies),
713 task ? task->comm : "<unknown>",
714 task ? task->pid : -1);
715 rcu_read_unlock();
716 }
717
718 any++;
719 }
720 mutex_unlock(&dev->struct_mutex);
721
722 if (any == 0)
723 seq_puts(m, "No requests\n");
724
725 return 0;
726 }
727
728 static void i915_ring_seqno_info(struct seq_file *m,
729 struct intel_engine_cs *engine)
730 {
731 if (engine->get_seqno) {
732 seq_printf(m, "Current sequence (%s): %x\n",
733 engine->name, engine->get_seqno(engine, false));
734 }
735 }
736
737 static int i915_gem_seqno_info(struct seq_file *m, void *data)
738 {
739 struct drm_info_node *node = m->private;
740 struct drm_device *dev = node->minor->dev;
741 struct drm_i915_private *dev_priv = dev->dev_private;
742 struct intel_engine_cs *engine;
743 int ret;
744
745 ret = mutex_lock_interruptible(&dev->struct_mutex);
746 if (ret)
747 return ret;
748 intel_runtime_pm_get(dev_priv);
749
750 for_each_engine(engine, dev_priv)
751 i915_ring_seqno_info(m, engine);
752
753 intel_runtime_pm_put(dev_priv);
754 mutex_unlock(&dev->struct_mutex);
755
756 return 0;
757 }
758
759
760 static int i915_interrupt_info(struct seq_file *m, void *data)
761 {
762 struct drm_info_node *node = m->private;
763 struct drm_device *dev = node->minor->dev;
764 struct drm_i915_private *dev_priv = dev->dev_private;
765 struct intel_engine_cs *engine;
766 int ret, i, pipe;
767
768 ret = mutex_lock_interruptible(&dev->struct_mutex);
769 if (ret)
770 return ret;
771 intel_runtime_pm_get(dev_priv);
772
773 if (IS_CHERRYVIEW(dev)) {
774 seq_printf(m, "Master Interrupt Control:\t%08x\n",
775 I915_READ(GEN8_MASTER_IRQ));
776
777 seq_printf(m, "Display IER:\t%08x\n",
778 I915_READ(VLV_IER));
779 seq_printf(m, "Display IIR:\t%08x\n",
780 I915_READ(VLV_IIR));
781 seq_printf(m, "Display IIR_RW:\t%08x\n",
782 I915_READ(VLV_IIR_RW));
783 seq_printf(m, "Display IMR:\t%08x\n",
784 I915_READ(VLV_IMR));
785 for_each_pipe(dev_priv, pipe)
786 seq_printf(m, "Pipe %c stat:\t%08x\n",
787 pipe_name(pipe),
788 I915_READ(PIPESTAT(pipe)));
789
790 seq_printf(m, "Port hotplug:\t%08x\n",
791 I915_READ(PORT_HOTPLUG_EN));
792 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
793 I915_READ(VLV_DPFLIPSTAT));
794 seq_printf(m, "DPINVGTT:\t%08x\n",
795 I915_READ(DPINVGTT));
796
797 for (i = 0; i < 4; i++) {
798 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
799 i, I915_READ(GEN8_GT_IMR(i)));
800 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
801 i, I915_READ(GEN8_GT_IIR(i)));
802 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
803 i, I915_READ(GEN8_GT_IER(i)));
804 }
805
806 seq_printf(m, "PCU interrupt mask:\t%08x\n",
807 I915_READ(GEN8_PCU_IMR));
808 seq_printf(m, "PCU interrupt identity:\t%08x\n",
809 I915_READ(GEN8_PCU_IIR));
810 seq_printf(m, "PCU interrupt enable:\t%08x\n",
811 I915_READ(GEN8_PCU_IER));
812 } else if (INTEL_INFO(dev)->gen >= 8) {
813 seq_printf(m, "Master Interrupt Control:\t%08x\n",
814 I915_READ(GEN8_MASTER_IRQ));
815
816 for (i = 0; i < 4; i++) {
817 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
818 i, I915_READ(GEN8_GT_IMR(i)));
819 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
820 i, I915_READ(GEN8_GT_IIR(i)));
821 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
822 i, I915_READ(GEN8_GT_IER(i)));
823 }
824
825 for_each_pipe(dev_priv, pipe) {
826 enum intel_display_power_domain power_domain;
827
828 power_domain = POWER_DOMAIN_PIPE(pipe);
829 if (!intel_display_power_get_if_enabled(dev_priv,
830 power_domain)) {
831 seq_printf(m, "Pipe %c power disabled\n",
832 pipe_name(pipe));
833 continue;
834 }
835 seq_printf(m, "Pipe %c IMR:\t%08x\n",
836 pipe_name(pipe),
837 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
838 seq_printf(m, "Pipe %c IIR:\t%08x\n",
839 pipe_name(pipe),
840 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
841 seq_printf(m, "Pipe %c IER:\t%08x\n",
842 pipe_name(pipe),
843 I915_READ(GEN8_DE_PIPE_IER(pipe)));
844
845 intel_display_power_put(dev_priv, power_domain);
846 }
847
848 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
849 I915_READ(GEN8_DE_PORT_IMR));
850 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
851 I915_READ(GEN8_DE_PORT_IIR));
852 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
853 I915_READ(GEN8_DE_PORT_IER));
854
855 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
856 I915_READ(GEN8_DE_MISC_IMR));
857 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
858 I915_READ(GEN8_DE_MISC_IIR));
859 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
860 I915_READ(GEN8_DE_MISC_IER));
861
862 seq_printf(m, "PCU interrupt mask:\t%08x\n",
863 I915_READ(GEN8_PCU_IMR));
864 seq_printf(m, "PCU interrupt identity:\t%08x\n",
865 I915_READ(GEN8_PCU_IIR));
866 seq_printf(m, "PCU interrupt enable:\t%08x\n",
867 I915_READ(GEN8_PCU_IER));
868 } else if (IS_VALLEYVIEW(dev)) {
869 seq_printf(m, "Display IER:\t%08x\n",
870 I915_READ(VLV_IER));
871 seq_printf(m, "Display IIR:\t%08x\n",
872 I915_READ(VLV_IIR));
873 seq_printf(m, "Display IIR_RW:\t%08x\n",
874 I915_READ(VLV_IIR_RW));
875 seq_printf(m, "Display IMR:\t%08x\n",
876 I915_READ(VLV_IMR));
877 for_each_pipe(dev_priv, pipe)
878 seq_printf(m, "Pipe %c stat:\t%08x\n",
879 pipe_name(pipe),
880 I915_READ(PIPESTAT(pipe)));
881
882 seq_printf(m, "Master IER:\t%08x\n",
883 I915_READ(VLV_MASTER_IER));
884
885 seq_printf(m, "Render IER:\t%08x\n",
886 I915_READ(GTIER));
887 seq_printf(m, "Render IIR:\t%08x\n",
888 I915_READ(GTIIR));
889 seq_printf(m, "Render IMR:\t%08x\n",
890 I915_READ(GTIMR));
891
892 seq_printf(m, "PM IER:\t\t%08x\n",
893 I915_READ(GEN6_PMIER));
894 seq_printf(m, "PM IIR:\t\t%08x\n",
895 I915_READ(GEN6_PMIIR));
896 seq_printf(m, "PM IMR:\t\t%08x\n",
897 I915_READ(GEN6_PMIMR));
898
899 seq_printf(m, "Port hotplug:\t%08x\n",
900 I915_READ(PORT_HOTPLUG_EN));
901 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
902 I915_READ(VLV_DPFLIPSTAT));
903 seq_printf(m, "DPINVGTT:\t%08x\n",
904 I915_READ(DPINVGTT));
905
906 } else if (!HAS_PCH_SPLIT(dev)) {
907 seq_printf(m, "Interrupt enable: %08x\n",
908 I915_READ(IER));
909 seq_printf(m, "Interrupt identity: %08x\n",
910 I915_READ(IIR));
911 seq_printf(m, "Interrupt mask: %08x\n",
912 I915_READ(IMR));
913 for_each_pipe(dev_priv, pipe)
914 seq_printf(m, "Pipe %c stat: %08x\n",
915 pipe_name(pipe),
916 I915_READ(PIPESTAT(pipe)));
917 } else {
918 seq_printf(m, "North Display Interrupt enable: %08x\n",
919 I915_READ(DEIER));
920 seq_printf(m, "North Display Interrupt identity: %08x\n",
921 I915_READ(DEIIR));
922 seq_printf(m, "North Display Interrupt mask: %08x\n",
923 I915_READ(DEIMR));
924 seq_printf(m, "South Display Interrupt enable: %08x\n",
925 I915_READ(SDEIER));
926 seq_printf(m, "South Display Interrupt identity: %08x\n",
927 I915_READ(SDEIIR));
928 seq_printf(m, "South Display Interrupt mask: %08x\n",
929 I915_READ(SDEIMR));
930 seq_printf(m, "Graphics Interrupt enable: %08x\n",
931 I915_READ(GTIER));
932 seq_printf(m, "Graphics Interrupt identity: %08x\n",
933 I915_READ(GTIIR));
934 seq_printf(m, "Graphics Interrupt mask: %08x\n",
935 I915_READ(GTIMR));
936 }
937 for_each_engine(engine, dev_priv) {
938 if (INTEL_INFO(dev)->gen >= 6) {
939 seq_printf(m,
940 "Graphics Interrupt mask (%s): %08x\n",
941 engine->name, I915_READ_IMR(engine));
942 }
943 i915_ring_seqno_info(m, engine);
944 }
945 intel_runtime_pm_put(dev_priv);
946 mutex_unlock(&dev->struct_mutex);
947
948 return 0;
949 }
950
951 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
952 {
953 struct drm_info_node *node = m->private;
954 struct drm_device *dev = node->minor->dev;
955 struct drm_i915_private *dev_priv = dev->dev_private;
956 int i, ret;
957
958 ret = mutex_lock_interruptible(&dev->struct_mutex);
959 if (ret)
960 return ret;
961
962 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
963 for (i = 0; i < dev_priv->num_fence_regs; i++) {
964 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
965
966 seq_printf(m, "Fence %d, pin count = %d, object = ",
967 i, dev_priv->fence_regs[i].pin_count);
968 if (obj == NULL)
969 seq_puts(m, "unused");
970 else
971 describe_obj(m, obj);
972 seq_putc(m, '\n');
973 }
974
975 mutex_unlock(&dev->struct_mutex);
976 return 0;
977 }
978
979 static int i915_hws_info(struct seq_file *m, void *data)
980 {
981 struct drm_info_node *node = m->private;
982 struct drm_device *dev = node->minor->dev;
983 struct drm_i915_private *dev_priv = dev->dev_private;
984 struct intel_engine_cs *engine;
985 const u32 *hws;
986 int i;
987
988 engine = &dev_priv->engine[(uintptr_t)node->info_ent->data];
989 hws = engine->status_page.page_addr;
990 if (hws == NULL)
991 return 0;
992
993 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
994 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
995 i * 4,
996 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
997 }
998 return 0;
999 }
1000
1001 static ssize_t
1002 i915_error_state_write(struct file *filp,
1003 const char __user *ubuf,
1004 size_t cnt,
1005 loff_t *ppos)
1006 {
1007 struct i915_error_state_file_priv *error_priv = filp->private_data;
1008 struct drm_device *dev = error_priv->dev;
1009 int ret;
1010
1011 DRM_DEBUG_DRIVER("Resetting error state\n");
1012
1013 ret = mutex_lock_interruptible(&dev->struct_mutex);
1014 if (ret)
1015 return ret;
1016
1017 i915_destroy_error_state(dev);
1018 mutex_unlock(&dev->struct_mutex);
1019
1020 return cnt;
1021 }
1022
1023 static int i915_error_state_open(struct inode *inode, struct file *file)
1024 {
1025 struct drm_device *dev = inode->i_private;
1026 struct i915_error_state_file_priv *error_priv;
1027
1028 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1029 if (!error_priv)
1030 return -ENOMEM;
1031
1032 error_priv->dev = dev;
1033
1034 i915_error_state_get(dev, error_priv);
1035
1036 file->private_data = error_priv;
1037
1038 return 0;
1039 }
1040
1041 static int i915_error_state_release(struct inode *inode, struct file *file)
1042 {
1043 struct i915_error_state_file_priv *error_priv = file->private_data;
1044
1045 i915_error_state_put(error_priv);
1046 kfree(error_priv);
1047
1048 return 0;
1049 }
1050
1051 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1052 size_t count, loff_t *pos)
1053 {
1054 struct i915_error_state_file_priv *error_priv = file->private_data;
1055 struct drm_i915_error_state_buf error_str;
1056 loff_t tmp_pos = 0;
1057 ssize_t ret_count = 0;
1058 int ret;
1059
1060 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1061 if (ret)
1062 return ret;
1063
1064 ret = i915_error_state_to_str(&error_str, error_priv);
1065 if (ret)
1066 goto out;
1067
1068 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1069 error_str.buf,
1070 error_str.bytes);
1071
1072 if (ret_count < 0)
1073 ret = ret_count;
1074 else
1075 *pos = error_str.start + ret_count;
1076 out:
1077 i915_error_state_buf_release(&error_str);
1078 return ret ?: ret_count;
1079 }
1080
1081 static const struct file_operations i915_error_state_fops = {
1082 .owner = THIS_MODULE,
1083 .open = i915_error_state_open,
1084 .read = i915_error_state_read,
1085 .write = i915_error_state_write,
1086 .llseek = default_llseek,
1087 .release = i915_error_state_release,
1088 };
1089
1090 static int
1091 i915_next_seqno_get(void *data, u64 *val)
1092 {
1093 struct drm_device *dev = data;
1094 struct drm_i915_private *dev_priv = dev->dev_private;
1095 int ret;
1096
1097 ret = mutex_lock_interruptible(&dev->struct_mutex);
1098 if (ret)
1099 return ret;
1100
1101 *val = dev_priv->next_seqno;
1102 mutex_unlock(&dev->struct_mutex);
1103
1104 return 0;
1105 }
1106
1107 static int
1108 i915_next_seqno_set(void *data, u64 val)
1109 {
1110 struct drm_device *dev = data;
1111 int ret;
1112
1113 ret = mutex_lock_interruptible(&dev->struct_mutex);
1114 if (ret)
1115 return ret;
1116
1117 ret = i915_gem_set_seqno(dev, val);
1118 mutex_unlock(&dev->struct_mutex);
1119
1120 return ret;
1121 }
1122
1123 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1124 i915_next_seqno_get, i915_next_seqno_set,
1125 "0x%llx\n");
1126
1127 static int i915_frequency_info(struct seq_file *m, void *unused)
1128 {
1129 struct drm_info_node *node = m->private;
1130 struct drm_device *dev = node->minor->dev;
1131 struct drm_i915_private *dev_priv = dev->dev_private;
1132 int ret = 0;
1133
1134 intel_runtime_pm_get(dev_priv);
1135
1136 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1137
1138 if (IS_GEN5(dev)) {
1139 u16 rgvswctl = I915_READ16(MEMSWCTL);
1140 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1141
1142 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1143 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1144 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1145 MEMSTAT_VID_SHIFT);
1146 seq_printf(m, "Current P-state: %d\n",
1147 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1148 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1149 u32 freq_sts;
1150
1151 mutex_lock(&dev_priv->rps.hw_lock);
1152 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1153 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1154 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1155
1156 seq_printf(m, "actual GPU freq: %d MHz\n",
1157 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1158
1159 seq_printf(m, "current GPU freq: %d MHz\n",
1160 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1161
1162 seq_printf(m, "max GPU freq: %d MHz\n",
1163 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1164
1165 seq_printf(m, "min GPU freq: %d MHz\n",
1166 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1167
1168 seq_printf(m, "idle GPU freq: %d MHz\n",
1169 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1170
1171 seq_printf(m,
1172 "efficient (RPe) frequency: %d MHz\n",
1173 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1174 mutex_unlock(&dev_priv->rps.hw_lock);
1175 } else if (INTEL_INFO(dev)->gen >= 6) {
1176 u32 rp_state_limits;
1177 u32 gt_perf_status;
1178 u32 rp_state_cap;
1179 u32 rpmodectl, rpinclimit, rpdeclimit;
1180 u32 rpstat, cagf, reqf;
1181 u32 rpupei, rpcurup, rpprevup;
1182 u32 rpdownei, rpcurdown, rpprevdown;
1183 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1184 int max_freq;
1185
1186 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1187 if (IS_BROXTON(dev)) {
1188 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1189 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1190 } else {
1191 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1192 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1193 }
1194
1195 /* RPSTAT1 is in the GT power well */
1196 ret = mutex_lock_interruptible(&dev->struct_mutex);
1197 if (ret)
1198 goto out;
1199
1200 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1201
1202 reqf = I915_READ(GEN6_RPNSWREQ);
1203 if (IS_GEN9(dev))
1204 reqf >>= 23;
1205 else {
1206 reqf &= ~GEN6_TURBO_DISABLE;
1207 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1208 reqf >>= 24;
1209 else
1210 reqf >>= 25;
1211 }
1212 reqf = intel_gpu_freq(dev_priv, reqf);
1213
1214 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1215 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1216 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1217
1218 rpstat = I915_READ(GEN6_RPSTAT1);
1219 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1220 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1221 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1222 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1223 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1224 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1225 if (IS_GEN9(dev))
1226 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1227 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1228 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1229 else
1230 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1231 cagf = intel_gpu_freq(dev_priv, cagf);
1232
1233 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1234 mutex_unlock(&dev->struct_mutex);
1235
1236 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1237 pm_ier = I915_READ(GEN6_PMIER);
1238 pm_imr = I915_READ(GEN6_PMIMR);
1239 pm_isr = I915_READ(GEN6_PMISR);
1240 pm_iir = I915_READ(GEN6_PMIIR);
1241 pm_mask = I915_READ(GEN6_PMINTRMSK);
1242 } else {
1243 pm_ier = I915_READ(GEN8_GT_IER(2));
1244 pm_imr = I915_READ(GEN8_GT_IMR(2));
1245 pm_isr = I915_READ(GEN8_GT_ISR(2));
1246 pm_iir = I915_READ(GEN8_GT_IIR(2));
1247 pm_mask = I915_READ(GEN6_PMINTRMSK);
1248 }
1249 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1250 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1251 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1252 seq_printf(m, "Render p-state ratio: %d\n",
1253 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
1254 seq_printf(m, "Render p-state VID: %d\n",
1255 gt_perf_status & 0xff);
1256 seq_printf(m, "Render p-state limit: %d\n",
1257 rp_state_limits & 0xff);
1258 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1259 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1260 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1261 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1262 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1263 seq_printf(m, "CAGF: %dMHz\n", cagf);
1264 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1265 GEN6_CURICONT_MASK);
1266 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1267 GEN6_CURBSYTAVG_MASK);
1268 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1269 GEN6_CURBSYTAVG_MASK);
1270 seq_printf(m, "Up threshold: %d%%\n",
1271 dev_priv->rps.up_threshold);
1272
1273 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1274 GEN6_CURIAVG_MASK);
1275 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1276 GEN6_CURBSYTAVG_MASK);
1277 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1278 GEN6_CURBSYTAVG_MASK);
1279 seq_printf(m, "Down threshold: %d%%\n",
1280 dev_priv->rps.down_threshold);
1281
1282 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1283 rp_state_cap >> 16) & 0xff;
1284 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1285 GEN9_FREQ_SCALER : 1);
1286 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1287 intel_gpu_freq(dev_priv, max_freq));
1288
1289 max_freq = (rp_state_cap & 0xff00) >> 8;
1290 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1291 GEN9_FREQ_SCALER : 1);
1292 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1293 intel_gpu_freq(dev_priv, max_freq));
1294
1295 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1296 rp_state_cap >> 0) & 0xff;
1297 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1298 GEN9_FREQ_SCALER : 1);
1299 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1300 intel_gpu_freq(dev_priv, max_freq));
1301 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1302 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1303
1304 seq_printf(m, "Current freq: %d MHz\n",
1305 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1306 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1307 seq_printf(m, "Idle freq: %d MHz\n",
1308 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1309 seq_printf(m, "Min freq: %d MHz\n",
1310 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1311 seq_printf(m, "Max freq: %d MHz\n",
1312 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1313 seq_printf(m,
1314 "efficient (RPe) frequency: %d MHz\n",
1315 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1316 } else {
1317 seq_puts(m, "no P-state info available\n");
1318 }
1319
1320 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1321 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1322 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1323
1324 out:
1325 intel_runtime_pm_put(dev_priv);
1326 return ret;
1327 }
1328
1329 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1330 {
1331 struct drm_info_node *node = m->private;
1332 struct drm_device *dev = node->minor->dev;
1333 struct drm_i915_private *dev_priv = dev->dev_private;
1334 struct intel_engine_cs *engine;
1335 u64 acthd[I915_NUM_ENGINES];
1336 u32 seqno[I915_NUM_ENGINES];
1337 u32 instdone[I915_NUM_INSTDONE_REG];
1338 enum intel_engine_id id;
1339 int j;
1340
1341 if (!i915.enable_hangcheck) {
1342 seq_printf(m, "Hangcheck disabled\n");
1343 return 0;
1344 }
1345
1346 intel_runtime_pm_get(dev_priv);
1347
1348 for_each_engine_id(engine, dev_priv, id) {
1349 seqno[id] = engine->get_seqno(engine, false);
1350 acthd[id] = intel_ring_get_active_head(engine);
1351 }
1352
1353 i915_get_extra_instdone(dev, instdone);
1354
1355 intel_runtime_pm_put(dev_priv);
1356
1357 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1358 seq_printf(m, "Hangcheck active, fires in %dms\n",
1359 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1360 jiffies));
1361 } else
1362 seq_printf(m, "Hangcheck inactive\n");
1363
1364 for_each_engine_id(engine, dev_priv, id) {
1365 seq_printf(m, "%s:\n", engine->name);
1366 seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
1367 engine->hangcheck.seqno,
1368 seqno[id],
1369 engine->last_submitted_seqno);
1370 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1371 (long long)engine->hangcheck.acthd,
1372 (long long)acthd[id]);
1373 seq_printf(m, "\tscore = %d\n", engine->hangcheck.score);
1374 seq_printf(m, "\taction = %d\n", engine->hangcheck.action);
1375
1376 if (engine->id == RCS) {
1377 seq_puts(m, "\tinstdone read =");
1378
1379 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1380 seq_printf(m, " 0x%08x", instdone[j]);
1381
1382 seq_puts(m, "\n\tinstdone accu =");
1383
1384 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1385 seq_printf(m, " 0x%08x",
1386 engine->hangcheck.instdone[j]);
1387
1388 seq_puts(m, "\n");
1389 }
1390 }
1391
1392 return 0;
1393 }
1394
1395 static int ironlake_drpc_info(struct seq_file *m)
1396 {
1397 struct drm_info_node *node = m->private;
1398 struct drm_device *dev = node->minor->dev;
1399 struct drm_i915_private *dev_priv = dev->dev_private;
1400 u32 rgvmodectl, rstdbyctl;
1401 u16 crstandvid;
1402 int ret;
1403
1404 ret = mutex_lock_interruptible(&dev->struct_mutex);
1405 if (ret)
1406 return ret;
1407 intel_runtime_pm_get(dev_priv);
1408
1409 rgvmodectl = I915_READ(MEMMODECTL);
1410 rstdbyctl = I915_READ(RSTDBYCTL);
1411 crstandvid = I915_READ16(CRSTANDVID);
1412
1413 intel_runtime_pm_put(dev_priv);
1414 mutex_unlock(&dev->struct_mutex);
1415
1416 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1417 seq_printf(m, "Boost freq: %d\n",
1418 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1419 MEMMODE_BOOST_FREQ_SHIFT);
1420 seq_printf(m, "HW control enabled: %s\n",
1421 yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1422 seq_printf(m, "SW control enabled: %s\n",
1423 yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1424 seq_printf(m, "Gated voltage change: %s\n",
1425 yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1426 seq_printf(m, "Starting frequency: P%d\n",
1427 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1428 seq_printf(m, "Max P-state: P%d\n",
1429 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1430 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1431 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1432 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1433 seq_printf(m, "Render standby enabled: %s\n",
1434 yesno(!(rstdbyctl & RCX_SW_EXIT)));
1435 seq_puts(m, "Current RS state: ");
1436 switch (rstdbyctl & RSX_STATUS_MASK) {
1437 case RSX_STATUS_ON:
1438 seq_puts(m, "on\n");
1439 break;
1440 case RSX_STATUS_RC1:
1441 seq_puts(m, "RC1\n");
1442 break;
1443 case RSX_STATUS_RC1E:
1444 seq_puts(m, "RC1E\n");
1445 break;
1446 case RSX_STATUS_RS1:
1447 seq_puts(m, "RS1\n");
1448 break;
1449 case RSX_STATUS_RS2:
1450 seq_puts(m, "RS2 (RC6)\n");
1451 break;
1452 case RSX_STATUS_RS3:
1453 seq_puts(m, "RC3 (RC6+)\n");
1454 break;
1455 default:
1456 seq_puts(m, "unknown\n");
1457 break;
1458 }
1459
1460 return 0;
1461 }
1462
1463 static int i915_forcewake_domains(struct seq_file *m, void *data)
1464 {
1465 struct drm_info_node *node = m->private;
1466 struct drm_device *dev = node->minor->dev;
1467 struct drm_i915_private *dev_priv = dev->dev_private;
1468 struct intel_uncore_forcewake_domain *fw_domain;
1469 int i;
1470
1471 spin_lock_irq(&dev_priv->uncore.lock);
1472 for_each_fw_domain(fw_domain, dev_priv, i) {
1473 seq_printf(m, "%s.wake_count = %u\n",
1474 intel_uncore_forcewake_domain_to_str(i),
1475 fw_domain->wake_count);
1476 }
1477 spin_unlock_irq(&dev_priv->uncore.lock);
1478
1479 return 0;
1480 }
1481
1482 static int vlv_drpc_info(struct seq_file *m)
1483 {
1484 struct drm_info_node *node = m->private;
1485 struct drm_device *dev = node->minor->dev;
1486 struct drm_i915_private *dev_priv = dev->dev_private;
1487 u32 rpmodectl1, rcctl1, pw_status;
1488
1489 intel_runtime_pm_get(dev_priv);
1490
1491 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1492 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1493 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1494
1495 intel_runtime_pm_put(dev_priv);
1496
1497 seq_printf(m, "Video Turbo Mode: %s\n",
1498 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1499 seq_printf(m, "Turbo enabled: %s\n",
1500 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1501 seq_printf(m, "HW control enabled: %s\n",
1502 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1503 seq_printf(m, "SW control enabled: %s\n",
1504 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1505 GEN6_RP_MEDIA_SW_MODE));
1506 seq_printf(m, "RC6 Enabled: %s\n",
1507 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1508 GEN6_RC_CTL_EI_MODE(1))));
1509 seq_printf(m, "Render Power Well: %s\n",
1510 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1511 seq_printf(m, "Media Power Well: %s\n",
1512 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1513
1514 seq_printf(m, "Render RC6 residency since boot: %u\n",
1515 I915_READ(VLV_GT_RENDER_RC6));
1516 seq_printf(m, "Media RC6 residency since boot: %u\n",
1517 I915_READ(VLV_GT_MEDIA_RC6));
1518
1519 return i915_forcewake_domains(m, NULL);
1520 }
1521
1522 static int gen6_drpc_info(struct seq_file *m)
1523 {
1524 struct drm_info_node *node = m->private;
1525 struct drm_device *dev = node->minor->dev;
1526 struct drm_i915_private *dev_priv = dev->dev_private;
1527 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1528 unsigned forcewake_count;
1529 int count = 0, ret;
1530
1531 ret = mutex_lock_interruptible(&dev->struct_mutex);
1532 if (ret)
1533 return ret;
1534 intel_runtime_pm_get(dev_priv);
1535
1536 spin_lock_irq(&dev_priv->uncore.lock);
1537 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1538 spin_unlock_irq(&dev_priv->uncore.lock);
1539
1540 if (forcewake_count) {
1541 seq_puts(m, "RC information inaccurate because somebody "
1542 "holds a forcewake reference \n");
1543 } else {
1544 /* NB: we cannot use forcewake, else we read the wrong values */
1545 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1546 udelay(10);
1547 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1548 }
1549
1550 gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1551 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1552
1553 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1554 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1555 mutex_unlock(&dev->struct_mutex);
1556 mutex_lock(&dev_priv->rps.hw_lock);
1557 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1558 mutex_unlock(&dev_priv->rps.hw_lock);
1559
1560 intel_runtime_pm_put(dev_priv);
1561
1562 seq_printf(m, "Video Turbo Mode: %s\n",
1563 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1564 seq_printf(m, "HW control enabled: %s\n",
1565 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1566 seq_printf(m, "SW control enabled: %s\n",
1567 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1568 GEN6_RP_MEDIA_SW_MODE));
1569 seq_printf(m, "RC1e Enabled: %s\n",
1570 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1571 seq_printf(m, "RC6 Enabled: %s\n",
1572 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1573 seq_printf(m, "Deep RC6 Enabled: %s\n",
1574 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1575 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1576 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1577 seq_puts(m, "Current RC state: ");
1578 switch (gt_core_status & GEN6_RCn_MASK) {
1579 case GEN6_RC0:
1580 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1581 seq_puts(m, "Core Power Down\n");
1582 else
1583 seq_puts(m, "on\n");
1584 break;
1585 case GEN6_RC3:
1586 seq_puts(m, "RC3\n");
1587 break;
1588 case GEN6_RC6:
1589 seq_puts(m, "RC6\n");
1590 break;
1591 case GEN6_RC7:
1592 seq_puts(m, "RC7\n");
1593 break;
1594 default:
1595 seq_puts(m, "Unknown\n");
1596 break;
1597 }
1598
1599 seq_printf(m, "Core Power Down: %s\n",
1600 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1601
1602 /* Not exactly sure what this is */
1603 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1604 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1605 seq_printf(m, "RC6 residency since boot: %u\n",
1606 I915_READ(GEN6_GT_GFX_RC6));
1607 seq_printf(m, "RC6+ residency since boot: %u\n",
1608 I915_READ(GEN6_GT_GFX_RC6p));
1609 seq_printf(m, "RC6++ residency since boot: %u\n",
1610 I915_READ(GEN6_GT_GFX_RC6pp));
1611
1612 seq_printf(m, "RC6 voltage: %dmV\n",
1613 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1614 seq_printf(m, "RC6+ voltage: %dmV\n",
1615 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1616 seq_printf(m, "RC6++ voltage: %dmV\n",
1617 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1618 return 0;
1619 }
1620
1621 static int i915_drpc_info(struct seq_file *m, void *unused)
1622 {
1623 struct drm_info_node *node = m->private;
1624 struct drm_device *dev = node->minor->dev;
1625
1626 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1627 return vlv_drpc_info(m);
1628 else if (INTEL_INFO(dev)->gen >= 6)
1629 return gen6_drpc_info(m);
1630 else
1631 return ironlake_drpc_info(m);
1632 }
1633
1634 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1635 {
1636 struct drm_info_node *node = m->private;
1637 struct drm_device *dev = node->minor->dev;
1638 struct drm_i915_private *dev_priv = dev->dev_private;
1639
1640 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1641 dev_priv->fb_tracking.busy_bits);
1642
1643 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1644 dev_priv->fb_tracking.flip_bits);
1645
1646 return 0;
1647 }
1648
1649 static int i915_fbc_status(struct seq_file *m, void *unused)
1650 {
1651 struct drm_info_node *node = m->private;
1652 struct drm_device *dev = node->minor->dev;
1653 struct drm_i915_private *dev_priv = dev->dev_private;
1654
1655 if (!HAS_FBC(dev)) {
1656 seq_puts(m, "FBC unsupported on this chipset\n");
1657 return 0;
1658 }
1659
1660 intel_runtime_pm_get(dev_priv);
1661 mutex_lock(&dev_priv->fbc.lock);
1662
1663 if (intel_fbc_is_active(dev_priv))
1664 seq_puts(m, "FBC enabled\n");
1665 else
1666 seq_printf(m, "FBC disabled: %s\n",
1667 dev_priv->fbc.no_fbc_reason);
1668
1669 if (INTEL_INFO(dev_priv)->gen >= 7)
1670 seq_printf(m, "Compressing: %s\n",
1671 yesno(I915_READ(FBC_STATUS2) &
1672 FBC_COMPRESSION_MASK));
1673
1674 mutex_unlock(&dev_priv->fbc.lock);
1675 intel_runtime_pm_put(dev_priv);
1676
1677 return 0;
1678 }
1679
1680 static int i915_fbc_fc_get(void *data, u64 *val)
1681 {
1682 struct drm_device *dev = data;
1683 struct drm_i915_private *dev_priv = dev->dev_private;
1684
1685 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1686 return -ENODEV;
1687
1688 *val = dev_priv->fbc.false_color;
1689
1690 return 0;
1691 }
1692
1693 static int i915_fbc_fc_set(void *data, u64 val)
1694 {
1695 struct drm_device *dev = data;
1696 struct drm_i915_private *dev_priv = dev->dev_private;
1697 u32 reg;
1698
1699 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1700 return -ENODEV;
1701
1702 mutex_lock(&dev_priv->fbc.lock);
1703
1704 reg = I915_READ(ILK_DPFC_CONTROL);
1705 dev_priv->fbc.false_color = val;
1706
1707 I915_WRITE(ILK_DPFC_CONTROL, val ?
1708 (reg | FBC_CTL_FALSE_COLOR) :
1709 (reg & ~FBC_CTL_FALSE_COLOR));
1710
1711 mutex_unlock(&dev_priv->fbc.lock);
1712 return 0;
1713 }
1714
1715 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1716 i915_fbc_fc_get, i915_fbc_fc_set,
1717 "%llu\n");
1718
1719 static int i915_ips_status(struct seq_file *m, void *unused)
1720 {
1721 struct drm_info_node *node = m->private;
1722 struct drm_device *dev = node->minor->dev;
1723 struct drm_i915_private *dev_priv = dev->dev_private;
1724
1725 if (!HAS_IPS(dev)) {
1726 seq_puts(m, "not supported\n");
1727 return 0;
1728 }
1729
1730 intel_runtime_pm_get(dev_priv);
1731
1732 seq_printf(m, "Enabled by kernel parameter: %s\n",
1733 yesno(i915.enable_ips));
1734
1735 if (INTEL_INFO(dev)->gen >= 8) {
1736 seq_puts(m, "Currently: unknown\n");
1737 } else {
1738 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1739 seq_puts(m, "Currently: enabled\n");
1740 else
1741 seq_puts(m, "Currently: disabled\n");
1742 }
1743
1744 intel_runtime_pm_put(dev_priv);
1745
1746 return 0;
1747 }
1748
1749 static int i915_sr_status(struct seq_file *m, void *unused)
1750 {
1751 struct drm_info_node *node = m->private;
1752 struct drm_device *dev = node->minor->dev;
1753 struct drm_i915_private *dev_priv = dev->dev_private;
1754 bool sr_enabled = false;
1755
1756 intel_runtime_pm_get(dev_priv);
1757
1758 if (HAS_PCH_SPLIT(dev))
1759 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1760 else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1761 IS_I945G(dev) || IS_I945GM(dev))
1762 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1763 else if (IS_I915GM(dev))
1764 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1765 else if (IS_PINEVIEW(dev))
1766 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1767 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1768 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1769
1770 intel_runtime_pm_put(dev_priv);
1771
1772 seq_printf(m, "self-refresh: %s\n",
1773 sr_enabled ? "enabled" : "disabled");
1774
1775 return 0;
1776 }
1777
1778 static int i915_emon_status(struct seq_file *m, void *unused)
1779 {
1780 struct drm_info_node *node = m->private;
1781 struct drm_device *dev = node->minor->dev;
1782 struct drm_i915_private *dev_priv = dev->dev_private;
1783 unsigned long temp, chipset, gfx;
1784 int ret;
1785
1786 if (!IS_GEN5(dev))
1787 return -ENODEV;
1788
1789 ret = mutex_lock_interruptible(&dev->struct_mutex);
1790 if (ret)
1791 return ret;
1792
1793 temp = i915_mch_val(dev_priv);
1794 chipset = i915_chipset_val(dev_priv);
1795 gfx = i915_gfx_val(dev_priv);
1796 mutex_unlock(&dev->struct_mutex);
1797
1798 seq_printf(m, "GMCH temp: %ld\n", temp);
1799 seq_printf(m, "Chipset power: %ld\n", chipset);
1800 seq_printf(m, "GFX power: %ld\n", gfx);
1801 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1802
1803 return 0;
1804 }
1805
1806 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1807 {
1808 struct drm_info_node *node = m->private;
1809 struct drm_device *dev = node->minor->dev;
1810 struct drm_i915_private *dev_priv = dev->dev_private;
1811 int ret = 0;
1812 int gpu_freq, ia_freq;
1813 unsigned int max_gpu_freq, min_gpu_freq;
1814
1815 if (!HAS_CORE_RING_FREQ(dev)) {
1816 seq_puts(m, "unsupported on this chipset\n");
1817 return 0;
1818 }
1819
1820 intel_runtime_pm_get(dev_priv);
1821
1822 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1823
1824 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1825 if (ret)
1826 goto out;
1827
1828 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
1829 /* Convert GT frequency to 50 HZ units */
1830 min_gpu_freq =
1831 dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1832 max_gpu_freq =
1833 dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1834 } else {
1835 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1836 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1837 }
1838
1839 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1840
1841 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1842 ia_freq = gpu_freq;
1843 sandybridge_pcode_read(dev_priv,
1844 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1845 &ia_freq);
1846 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1847 intel_gpu_freq(dev_priv, (gpu_freq *
1848 (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1849 GEN9_FREQ_SCALER : 1))),
1850 ((ia_freq >> 0) & 0xff) * 100,
1851 ((ia_freq >> 8) & 0xff) * 100);
1852 }
1853
1854 mutex_unlock(&dev_priv->rps.hw_lock);
1855
1856 out:
1857 intel_runtime_pm_put(dev_priv);
1858 return ret;
1859 }
1860
1861 static int i915_opregion(struct seq_file *m, void *unused)
1862 {
1863 struct drm_info_node *node = m->private;
1864 struct drm_device *dev = node->minor->dev;
1865 struct drm_i915_private *dev_priv = dev->dev_private;
1866 struct intel_opregion *opregion = &dev_priv->opregion;
1867 int ret;
1868
1869 ret = mutex_lock_interruptible(&dev->struct_mutex);
1870 if (ret)
1871 goto out;
1872
1873 if (opregion->header)
1874 seq_write(m, opregion->header, OPREGION_SIZE);
1875
1876 mutex_unlock(&dev->struct_mutex);
1877
1878 out:
1879 return 0;
1880 }
1881
1882 static int i915_vbt(struct seq_file *m, void *unused)
1883 {
1884 struct drm_info_node *node = m->private;
1885 struct drm_device *dev = node->minor->dev;
1886 struct drm_i915_private *dev_priv = dev->dev_private;
1887 struct intel_opregion *opregion = &dev_priv->opregion;
1888
1889 if (opregion->vbt)
1890 seq_write(m, opregion->vbt, opregion->vbt_size);
1891
1892 return 0;
1893 }
1894
1895 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1896 {
1897 struct drm_info_node *node = m->private;
1898 struct drm_device *dev = node->minor->dev;
1899 struct intel_framebuffer *fbdev_fb = NULL;
1900 struct drm_framebuffer *drm_fb;
1901 int ret;
1902
1903 ret = mutex_lock_interruptible(&dev->struct_mutex);
1904 if (ret)
1905 return ret;
1906
1907 #ifdef CONFIG_DRM_FBDEV_EMULATION
1908 if (to_i915(dev)->fbdev) {
1909 fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb);
1910
1911 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1912 fbdev_fb->base.width,
1913 fbdev_fb->base.height,
1914 fbdev_fb->base.depth,
1915 fbdev_fb->base.bits_per_pixel,
1916 fbdev_fb->base.modifier[0],
1917 atomic_read(&fbdev_fb->base.refcount.refcount));
1918 describe_obj(m, fbdev_fb->obj);
1919 seq_putc(m, '\n');
1920 }
1921 #endif
1922
1923 mutex_lock(&dev->mode_config.fb_lock);
1924 drm_for_each_fb(drm_fb, dev) {
1925 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1926 if (fb == fbdev_fb)
1927 continue;
1928
1929 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1930 fb->base.width,
1931 fb->base.height,
1932 fb->base.depth,
1933 fb->base.bits_per_pixel,
1934 fb->base.modifier[0],
1935 atomic_read(&fb->base.refcount.refcount));
1936 describe_obj(m, fb->obj);
1937 seq_putc(m, '\n');
1938 }
1939 mutex_unlock(&dev->mode_config.fb_lock);
1940 mutex_unlock(&dev->struct_mutex);
1941
1942 return 0;
1943 }
1944
1945 static void describe_ctx_ringbuf(struct seq_file *m,
1946 struct intel_ringbuffer *ringbuf)
1947 {
1948 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1949 ringbuf->space, ringbuf->head, ringbuf->tail,
1950 ringbuf->last_retired_head);
1951 }
1952
1953 static int i915_context_status(struct seq_file *m, void *unused)
1954 {
1955 struct drm_info_node *node = m->private;
1956 struct drm_device *dev = node->minor->dev;
1957 struct drm_i915_private *dev_priv = dev->dev_private;
1958 struct intel_engine_cs *engine;
1959 struct intel_context *ctx;
1960 enum intel_engine_id id;
1961 int ret;
1962
1963 ret = mutex_lock_interruptible(&dev->struct_mutex);
1964 if (ret)
1965 return ret;
1966
1967 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1968 if (!i915.enable_execlists &&
1969 ctx->legacy_hw_ctx.rcs_state == NULL)
1970 continue;
1971
1972 seq_puts(m, "HW context ");
1973 describe_ctx(m, ctx);
1974 if (ctx == dev_priv->kernel_context)
1975 seq_printf(m, "(kernel context) ");
1976
1977 if (i915.enable_execlists) {
1978 seq_putc(m, '\n');
1979 for_each_engine_id(engine, dev_priv, id) {
1980 struct drm_i915_gem_object *ctx_obj =
1981 ctx->engine[id].state;
1982 struct intel_ringbuffer *ringbuf =
1983 ctx->engine[id].ringbuf;
1984
1985 seq_printf(m, "%s: ", engine->name);
1986 if (ctx_obj)
1987 describe_obj(m, ctx_obj);
1988 if (ringbuf)
1989 describe_ctx_ringbuf(m, ringbuf);
1990 seq_putc(m, '\n');
1991 }
1992 } else {
1993 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1994 }
1995
1996 seq_putc(m, '\n');
1997 }
1998
1999 mutex_unlock(&dev->struct_mutex);
2000
2001 return 0;
2002 }
2003
2004 static void i915_dump_lrc_obj(struct seq_file *m,
2005 struct intel_context *ctx,
2006 struct intel_engine_cs *engine)
2007 {
2008 struct page *page;
2009 uint32_t *reg_state;
2010 int j;
2011 struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state;
2012 unsigned long ggtt_offset = 0;
2013
2014 if (ctx_obj == NULL) {
2015 seq_printf(m, "Context on %s with no gem object\n",
2016 engine->name);
2017 return;
2018 }
2019
2020 seq_printf(m, "CONTEXT: %s %u\n", engine->name,
2021 intel_execlists_ctx_id(ctx, engine));
2022
2023 if (!i915_gem_obj_ggtt_bound(ctx_obj))
2024 seq_puts(m, "\tNot bound in GGTT\n");
2025 else
2026 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
2027
2028 if (i915_gem_object_get_pages(ctx_obj)) {
2029 seq_puts(m, "\tFailed to get pages for context object\n");
2030 return;
2031 }
2032
2033 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
2034 if (!WARN_ON(page == NULL)) {
2035 reg_state = kmap_atomic(page);
2036
2037 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2038 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2039 ggtt_offset + 4096 + (j * 4),
2040 reg_state[j], reg_state[j + 1],
2041 reg_state[j + 2], reg_state[j + 3]);
2042 }
2043 kunmap_atomic(reg_state);
2044 }
2045
2046 seq_putc(m, '\n');
2047 }
2048
2049 static int i915_dump_lrc(struct seq_file *m, void *unused)
2050 {
2051 struct drm_info_node *node = (struct drm_info_node *) m->private;
2052 struct drm_device *dev = node->minor->dev;
2053 struct drm_i915_private *dev_priv = dev->dev_private;
2054 struct intel_engine_cs *engine;
2055 struct intel_context *ctx;
2056 int ret;
2057
2058 if (!i915.enable_execlists) {
2059 seq_printf(m, "Logical Ring Contexts are disabled\n");
2060 return 0;
2061 }
2062
2063 ret = mutex_lock_interruptible(&dev->struct_mutex);
2064 if (ret)
2065 return ret;
2066
2067 list_for_each_entry(ctx, &dev_priv->context_list, link)
2068 if (ctx != dev_priv->kernel_context)
2069 for_each_engine(engine, dev_priv)
2070 i915_dump_lrc_obj(m, ctx, engine);
2071
2072 mutex_unlock(&dev->struct_mutex);
2073
2074 return 0;
2075 }
2076
2077 static int i915_execlists(struct seq_file *m, void *data)
2078 {
2079 struct drm_info_node *node = (struct drm_info_node *)m->private;
2080 struct drm_device *dev = node->minor->dev;
2081 struct drm_i915_private *dev_priv = dev->dev_private;
2082 struct intel_engine_cs *engine;
2083 u32 status_pointer;
2084 u8 read_pointer;
2085 u8 write_pointer;
2086 u32 status;
2087 u32 ctx_id;
2088 struct list_head *cursor;
2089 int i, ret;
2090
2091 if (!i915.enable_execlists) {
2092 seq_puts(m, "Logical Ring Contexts are disabled\n");
2093 return 0;
2094 }
2095
2096 ret = mutex_lock_interruptible(&dev->struct_mutex);
2097 if (ret)
2098 return ret;
2099
2100 intel_runtime_pm_get(dev_priv);
2101
2102 for_each_engine(engine, dev_priv) {
2103 struct drm_i915_gem_request *head_req = NULL;
2104 int count = 0;
2105
2106 seq_printf(m, "%s\n", engine->name);
2107
2108 status = I915_READ(RING_EXECLIST_STATUS_LO(engine));
2109 ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(engine));
2110 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2111 status, ctx_id);
2112
2113 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
2114 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2115
2116 read_pointer = engine->next_context_status_buffer;
2117 write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
2118 if (read_pointer > write_pointer)
2119 write_pointer += GEN8_CSB_ENTRIES;
2120 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2121 read_pointer, write_pointer);
2122
2123 for (i = 0; i < GEN8_CSB_ENTRIES; i++) {
2124 status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, i));
2125 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, i));
2126
2127 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2128 i, status, ctx_id);
2129 }
2130
2131 spin_lock_bh(&engine->execlist_lock);
2132 list_for_each(cursor, &engine->execlist_queue)
2133 count++;
2134 head_req = list_first_entry_or_null(&engine->execlist_queue,
2135 struct drm_i915_gem_request,
2136 execlist_link);
2137 spin_unlock_bh(&engine->execlist_lock);
2138
2139 seq_printf(m, "\t%d requests in queue\n", count);
2140 if (head_req) {
2141 seq_printf(m, "\tHead request id: %u\n",
2142 intel_execlists_ctx_id(head_req->ctx, engine));
2143 seq_printf(m, "\tHead request tail: %u\n",
2144 head_req->tail);
2145 }
2146
2147 seq_putc(m, '\n');
2148 }
2149
2150 intel_runtime_pm_put(dev_priv);
2151 mutex_unlock(&dev->struct_mutex);
2152
2153 return 0;
2154 }
2155
2156 static const char *swizzle_string(unsigned swizzle)
2157 {
2158 switch (swizzle) {
2159 case I915_BIT_6_SWIZZLE_NONE:
2160 return "none";
2161 case I915_BIT_6_SWIZZLE_9:
2162 return "bit9";
2163 case I915_BIT_6_SWIZZLE_9_10:
2164 return "bit9/bit10";
2165 case I915_BIT_6_SWIZZLE_9_11:
2166 return "bit9/bit11";
2167 case I915_BIT_6_SWIZZLE_9_10_11:
2168 return "bit9/bit10/bit11";
2169 case I915_BIT_6_SWIZZLE_9_17:
2170 return "bit9/bit17";
2171 case I915_BIT_6_SWIZZLE_9_10_17:
2172 return "bit9/bit10/bit17";
2173 case I915_BIT_6_SWIZZLE_UNKNOWN:
2174 return "unknown";
2175 }
2176
2177 return "bug";
2178 }
2179
2180 static int i915_swizzle_info(struct seq_file *m, void *data)
2181 {
2182 struct drm_info_node *node = m->private;
2183 struct drm_device *dev = node->minor->dev;
2184 struct drm_i915_private *dev_priv = dev->dev_private;
2185 int ret;
2186
2187 ret = mutex_lock_interruptible(&dev->struct_mutex);
2188 if (ret)
2189 return ret;
2190 intel_runtime_pm_get(dev_priv);
2191
2192 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2193 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2194 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2195 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2196
2197 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2198 seq_printf(m, "DDC = 0x%08x\n",
2199 I915_READ(DCC));
2200 seq_printf(m, "DDC2 = 0x%08x\n",
2201 I915_READ(DCC2));
2202 seq_printf(m, "C0DRB3 = 0x%04x\n",
2203 I915_READ16(C0DRB3));
2204 seq_printf(m, "C1DRB3 = 0x%04x\n",
2205 I915_READ16(C1DRB3));
2206 } else if (INTEL_INFO(dev)->gen >= 6) {
2207 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2208 I915_READ(MAD_DIMM_C0));
2209 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2210 I915_READ(MAD_DIMM_C1));
2211 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2212 I915_READ(MAD_DIMM_C2));
2213 seq_printf(m, "TILECTL = 0x%08x\n",
2214 I915_READ(TILECTL));
2215 if (INTEL_INFO(dev)->gen >= 8)
2216 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2217 I915_READ(GAMTARBMODE));
2218 else
2219 seq_printf(m, "ARB_MODE = 0x%08x\n",
2220 I915_READ(ARB_MODE));
2221 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2222 I915_READ(DISP_ARB_CTL));
2223 }
2224
2225 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2226 seq_puts(m, "L-shaped memory detected\n");
2227
2228 intel_runtime_pm_put(dev_priv);
2229 mutex_unlock(&dev->struct_mutex);
2230
2231 return 0;
2232 }
2233
2234 static int per_file_ctx(int id, void *ptr, void *data)
2235 {
2236 struct intel_context *ctx = ptr;
2237 struct seq_file *m = data;
2238 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2239
2240 if (!ppgtt) {
2241 seq_printf(m, " no ppgtt for context %d\n",
2242 ctx->user_handle);
2243 return 0;
2244 }
2245
2246 if (i915_gem_context_is_default(ctx))
2247 seq_puts(m, " default context:\n");
2248 else
2249 seq_printf(m, " context %d:\n", ctx->user_handle);
2250 ppgtt->debug_dump(ppgtt, m);
2251
2252 return 0;
2253 }
2254
2255 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2256 {
2257 struct drm_i915_private *dev_priv = dev->dev_private;
2258 struct intel_engine_cs *engine;
2259 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2260 int i;
2261
2262 if (!ppgtt)
2263 return;
2264
2265 for_each_engine(engine, dev_priv) {
2266 seq_printf(m, "%s\n", engine->name);
2267 for (i = 0; i < 4; i++) {
2268 u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2269 pdp <<= 32;
2270 pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2271 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2272 }
2273 }
2274 }
2275
2276 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2277 {
2278 struct drm_i915_private *dev_priv = dev->dev_private;
2279 struct intel_engine_cs *engine;
2280
2281 if (INTEL_INFO(dev)->gen == 6)
2282 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2283
2284 for_each_engine(engine, dev_priv) {
2285 seq_printf(m, "%s\n", engine->name);
2286 if (INTEL_INFO(dev)->gen == 7)
2287 seq_printf(m, "GFX_MODE: 0x%08x\n",
2288 I915_READ(RING_MODE_GEN7(engine)));
2289 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2290 I915_READ(RING_PP_DIR_BASE(engine)));
2291 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2292 I915_READ(RING_PP_DIR_BASE_READ(engine)));
2293 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2294 I915_READ(RING_PP_DIR_DCLV(engine)));
2295 }
2296 if (dev_priv->mm.aliasing_ppgtt) {
2297 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2298
2299 seq_puts(m, "aliasing PPGTT:\n");
2300 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2301
2302 ppgtt->debug_dump(ppgtt, m);
2303 }
2304
2305 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2306 }
2307
2308 static int i915_ppgtt_info(struct seq_file *m, void *data)
2309 {
2310 struct drm_info_node *node = m->private;
2311 struct drm_device *dev = node->minor->dev;
2312 struct drm_i915_private *dev_priv = dev->dev_private;
2313 struct drm_file *file;
2314
2315 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2316 if (ret)
2317 return ret;
2318 intel_runtime_pm_get(dev_priv);
2319
2320 if (INTEL_INFO(dev)->gen >= 8)
2321 gen8_ppgtt_info(m, dev);
2322 else if (INTEL_INFO(dev)->gen >= 6)
2323 gen6_ppgtt_info(m, dev);
2324
2325 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2326 struct drm_i915_file_private *file_priv = file->driver_priv;
2327 struct task_struct *task;
2328
2329 task = get_pid_task(file->pid, PIDTYPE_PID);
2330 if (!task) {
2331 ret = -ESRCH;
2332 goto out_put;
2333 }
2334 seq_printf(m, "\nproc: %s\n", task->comm);
2335 put_task_struct(task);
2336 idr_for_each(&file_priv->context_idr, per_file_ctx,
2337 (void *)(unsigned long)m);
2338 }
2339
2340 out_put:
2341 intel_runtime_pm_put(dev_priv);
2342 mutex_unlock(&dev->struct_mutex);
2343
2344 return ret;
2345 }
2346
2347 static int count_irq_waiters(struct drm_i915_private *i915)
2348 {
2349 struct intel_engine_cs *engine;
2350 int count = 0;
2351
2352 for_each_engine(engine, i915)
2353 count += engine->irq_refcount;
2354
2355 return count;
2356 }
2357
2358 static int i915_rps_boost_info(struct seq_file *m, void *data)
2359 {
2360 struct drm_info_node *node = m->private;
2361 struct drm_device *dev = node->minor->dev;
2362 struct drm_i915_private *dev_priv = dev->dev_private;
2363 struct drm_file *file;
2364
2365 seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2366 seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
2367 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2368 seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2369 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2370 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2371 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2372 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2373 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2374 spin_lock(&dev_priv->rps.client_lock);
2375 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2376 struct drm_i915_file_private *file_priv = file->driver_priv;
2377 struct task_struct *task;
2378
2379 rcu_read_lock();
2380 task = pid_task(file->pid, PIDTYPE_PID);
2381 seq_printf(m, "%s [%d]: %d boosts%s\n",
2382 task ? task->comm : "<unknown>",
2383 task ? task->pid : -1,
2384 file_priv->rps.boosts,
2385 list_empty(&file_priv->rps.link) ? "" : ", active");
2386 rcu_read_unlock();
2387 }
2388 seq_printf(m, "Semaphore boosts: %d%s\n",
2389 dev_priv->rps.semaphores.boosts,
2390 list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");
2391 seq_printf(m, "MMIO flip boosts: %d%s\n",
2392 dev_priv->rps.mmioflips.boosts,
2393 list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
2394 seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
2395 spin_unlock(&dev_priv->rps.client_lock);
2396
2397 return 0;
2398 }
2399
2400 static int i915_llc(struct seq_file *m, void *data)
2401 {
2402 struct drm_info_node *node = m->private;
2403 struct drm_device *dev = node->minor->dev;
2404 struct drm_i915_private *dev_priv = dev->dev_private;
2405
2406 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2407 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2408 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2409
2410 return 0;
2411 }
2412
2413 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2414 {
2415 struct drm_info_node *node = m->private;
2416 struct drm_i915_private *dev_priv = node->minor->dev->dev_private;
2417 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2418 u32 tmp, i;
2419
2420 if (!HAS_GUC_UCODE(dev_priv))
2421 return 0;
2422
2423 seq_printf(m, "GuC firmware status:\n");
2424 seq_printf(m, "\tpath: %s\n",
2425 guc_fw->guc_fw_path);
2426 seq_printf(m, "\tfetch: %s\n",
2427 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2428 seq_printf(m, "\tload: %s\n",
2429 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2430 seq_printf(m, "\tversion wanted: %d.%d\n",
2431 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2432 seq_printf(m, "\tversion found: %d.%d\n",
2433 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2434 seq_printf(m, "\theader: offset is %d; size = %d\n",
2435 guc_fw->header_offset, guc_fw->header_size);
2436 seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2437 guc_fw->ucode_offset, guc_fw->ucode_size);
2438 seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2439 guc_fw->rsa_offset, guc_fw->rsa_size);
2440
2441 tmp = I915_READ(GUC_STATUS);
2442
2443 seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2444 seq_printf(m, "\tBootrom status = 0x%x\n",
2445 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2446 seq_printf(m, "\tuKernel status = 0x%x\n",
2447 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2448 seq_printf(m, "\tMIA Core status = 0x%x\n",
2449 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2450 seq_puts(m, "\nScratch registers:\n");
2451 for (i = 0; i < 16; i++)
2452 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2453
2454 return 0;
2455 }
2456
2457 static void i915_guc_client_info(struct seq_file *m,
2458 struct drm_i915_private *dev_priv,
2459 struct i915_guc_client *client)
2460 {
2461 struct intel_engine_cs *engine;
2462 uint64_t tot = 0;
2463
2464 seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2465 client->priority, client->ctx_index, client->proc_desc_offset);
2466 seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2467 client->doorbell_id, client->doorbell_offset, client->cookie);
2468 seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2469 client->wq_size, client->wq_offset, client->wq_tail);
2470
2471 seq_printf(m, "\tFailed to queue: %u\n", client->q_fail);
2472 seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2473 seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2474
2475 for_each_engine(engine, dev_priv) {
2476 seq_printf(m, "\tSubmissions: %llu %s\n",
2477 client->submissions[engine->guc_id],
2478 engine->name);
2479 tot += client->submissions[engine->guc_id];
2480 }
2481 seq_printf(m, "\tTotal: %llu\n", tot);
2482 }
2483
2484 static int i915_guc_info(struct seq_file *m, void *data)
2485 {
2486 struct drm_info_node *node = m->private;
2487 struct drm_device *dev = node->minor->dev;
2488 struct drm_i915_private *dev_priv = dev->dev_private;
2489 struct intel_guc guc;
2490 struct i915_guc_client client = {};
2491 struct intel_engine_cs *engine;
2492 u64 total = 0;
2493
2494 if (!HAS_GUC_SCHED(dev_priv))
2495 return 0;
2496
2497 if (mutex_lock_interruptible(&dev->struct_mutex))
2498 return 0;
2499
2500 /* Take a local copy of the GuC data, so we can dump it at leisure */
2501 guc = dev_priv->guc;
2502 if (guc.execbuf_client)
2503 client = *guc.execbuf_client;
2504
2505 mutex_unlock(&dev->struct_mutex);
2506
2507 seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2508 seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2509 seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2510 seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2511 seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2512
2513 seq_printf(m, "\nGuC submissions:\n");
2514 for_each_engine(engine, dev_priv) {
2515 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
2516 engine->name, guc.submissions[engine->guc_id],
2517 guc.last_seqno[engine->guc_id]);
2518 total += guc.submissions[engine->guc_id];
2519 }
2520 seq_printf(m, "\t%s: %llu\n", "Total", total);
2521
2522 seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2523 i915_guc_client_info(m, dev_priv, &client);
2524
2525 /* Add more as required ... */
2526
2527 return 0;
2528 }
2529
2530 static int i915_guc_log_dump(struct seq_file *m, void *data)
2531 {
2532 struct drm_info_node *node = m->private;
2533 struct drm_device *dev = node->minor->dev;
2534 struct drm_i915_private *dev_priv = dev->dev_private;
2535 struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;
2536 u32 *log;
2537 int i = 0, pg;
2538
2539 if (!log_obj)
2540 return 0;
2541
2542 for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) {
2543 log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));
2544
2545 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2546 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2547 *(log + i), *(log + i + 1),
2548 *(log + i + 2), *(log + i + 3));
2549
2550 kunmap_atomic(log);
2551 }
2552
2553 seq_putc(m, '\n');
2554
2555 return 0;
2556 }
2557
2558 static int i915_edp_psr_status(struct seq_file *m, void *data)
2559 {
2560 struct drm_info_node *node = m->private;
2561 struct drm_device *dev = node->minor->dev;
2562 struct drm_i915_private *dev_priv = dev->dev_private;
2563 u32 psrperf = 0;
2564 u32 stat[3];
2565 enum pipe pipe;
2566 bool enabled = false;
2567
2568 if (!HAS_PSR(dev)) {
2569 seq_puts(m, "PSR not supported\n");
2570 return 0;
2571 }
2572
2573 intel_runtime_pm_get(dev_priv);
2574
2575 mutex_lock(&dev_priv->psr.lock);
2576 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2577 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2578 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2579 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2580 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2581 dev_priv->psr.busy_frontbuffer_bits);
2582 seq_printf(m, "Re-enable work scheduled: %s\n",
2583 yesno(work_busy(&dev_priv->psr.work.work)));
2584
2585 if (HAS_DDI(dev))
2586 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2587 else {
2588 for_each_pipe(dev_priv, pipe) {
2589 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2590 VLV_EDP_PSR_CURR_STATE_MASK;
2591 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2592 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2593 enabled = true;
2594 }
2595 }
2596
2597 seq_printf(m, "Main link in standby mode: %s\n",
2598 yesno(dev_priv->psr.link_standby));
2599
2600 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2601
2602 if (!HAS_DDI(dev))
2603 for_each_pipe(dev_priv, pipe) {
2604 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2605 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2606 seq_printf(m, " pipe %c", pipe_name(pipe));
2607 }
2608 seq_puts(m, "\n");
2609
2610 /*
2611 * VLV/CHV PSR has no kind of performance counter
2612 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2613 */
2614 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2615 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2616 EDP_PSR_PERF_CNT_MASK;
2617
2618 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2619 }
2620 mutex_unlock(&dev_priv->psr.lock);
2621
2622 intel_runtime_pm_put(dev_priv);
2623 return 0;
2624 }
2625
2626 static int i915_sink_crc(struct seq_file *m, void *data)
2627 {
2628 struct drm_info_node *node = m->private;
2629 struct drm_device *dev = node->minor->dev;
2630 struct intel_encoder *encoder;
2631 struct intel_connector *connector;
2632 struct intel_dp *intel_dp = NULL;
2633 int ret;
2634 u8 crc[6];
2635
2636 drm_modeset_lock_all(dev);
2637 for_each_intel_connector(dev, connector) {
2638
2639 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2640 continue;
2641
2642 if (!connector->base.encoder)
2643 continue;
2644
2645 encoder = to_intel_encoder(connector->base.encoder);
2646 if (encoder->type != INTEL_OUTPUT_EDP)
2647 continue;
2648
2649 intel_dp = enc_to_intel_dp(&encoder->base);
2650
2651 ret = intel_dp_sink_crc(intel_dp, crc);
2652 if (ret)
2653 goto out;
2654
2655 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2656 crc[0], crc[1], crc[2],
2657 crc[3], crc[4], crc[5]);
2658 goto out;
2659 }
2660 ret = -ENODEV;
2661 out:
2662 drm_modeset_unlock_all(dev);
2663 return ret;
2664 }
2665
2666 static int i915_energy_uJ(struct seq_file *m, void *data)
2667 {
2668 struct drm_info_node *node = m->private;
2669 struct drm_device *dev = node->minor->dev;
2670 struct drm_i915_private *dev_priv = dev->dev_private;
2671 u64 power;
2672 u32 units;
2673
2674 if (INTEL_INFO(dev)->gen < 6)
2675 return -ENODEV;
2676
2677 intel_runtime_pm_get(dev_priv);
2678
2679 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2680 power = (power & 0x1f00) >> 8;
2681 units = 1000000 / (1 << power); /* convert to uJ */
2682 power = I915_READ(MCH_SECP_NRG_STTS);
2683 power *= units;
2684
2685 intel_runtime_pm_put(dev_priv);
2686
2687 seq_printf(m, "%llu", (long long unsigned)power);
2688
2689 return 0;
2690 }
2691
2692 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2693 {
2694 struct drm_info_node *node = m->private;
2695 struct drm_device *dev = node->minor->dev;
2696 struct drm_i915_private *dev_priv = dev->dev_private;
2697
2698 if (!HAS_RUNTIME_PM(dev_priv))
2699 seq_puts(m, "Runtime power management not supported\n");
2700
2701 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2702 seq_printf(m, "IRQs disabled: %s\n",
2703 yesno(!intel_irqs_enabled(dev_priv)));
2704 #ifdef CONFIG_PM
2705 seq_printf(m, "Usage count: %d\n",
2706 atomic_read(&dev->dev->power.usage_count));
2707 #else
2708 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2709 #endif
2710 seq_printf(m, "PCI device power state: %s [%d]\n",
2711 pci_power_name(dev_priv->dev->pdev->current_state),
2712 dev_priv->dev->pdev->current_state);
2713
2714 return 0;
2715 }
2716
2717 static int i915_power_domain_info(struct seq_file *m, void *unused)
2718 {
2719 struct drm_info_node *node = m->private;
2720 struct drm_device *dev = node->minor->dev;
2721 struct drm_i915_private *dev_priv = dev->dev_private;
2722 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2723 int i;
2724
2725 mutex_lock(&power_domains->lock);
2726
2727 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2728 for (i = 0; i < power_domains->power_well_count; i++) {
2729 struct i915_power_well *power_well;
2730 enum intel_display_power_domain power_domain;
2731
2732 power_well = &power_domains->power_wells[i];
2733 seq_printf(m, "%-25s %d\n", power_well->name,
2734 power_well->count);
2735
2736 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2737 power_domain++) {
2738 if (!(BIT(power_domain) & power_well->domains))
2739 continue;
2740
2741 seq_printf(m, " %-23s %d\n",
2742 intel_display_power_domain_str(power_domain),
2743 power_domains->domain_use_count[power_domain]);
2744 }
2745 }
2746
2747 mutex_unlock(&power_domains->lock);
2748
2749 return 0;
2750 }
2751
2752 static int i915_dmc_info(struct seq_file *m, void *unused)
2753 {
2754 struct drm_info_node *node = m->private;
2755 struct drm_device *dev = node->minor->dev;
2756 struct drm_i915_private *dev_priv = dev->dev_private;
2757 struct intel_csr *csr;
2758
2759 if (!HAS_CSR(dev)) {
2760 seq_puts(m, "not supported\n");
2761 return 0;
2762 }
2763
2764 csr = &dev_priv->csr;
2765
2766 intel_runtime_pm_get(dev_priv);
2767
2768 seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2769 seq_printf(m, "path: %s\n", csr->fw_path);
2770
2771 if (!csr->dmc_payload)
2772 goto out;
2773
2774 seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2775 CSR_VERSION_MINOR(csr->version));
2776
2777 if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
2778 seq_printf(m, "DC3 -> DC5 count: %d\n",
2779 I915_READ(SKL_CSR_DC3_DC5_COUNT));
2780 seq_printf(m, "DC5 -> DC6 count: %d\n",
2781 I915_READ(SKL_CSR_DC5_DC6_COUNT));
2782 } else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) {
2783 seq_printf(m, "DC3 -> DC5 count: %d\n",
2784 I915_READ(BXT_CSR_DC3_DC5_COUNT));
2785 }
2786
2787 out:
2788 seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2789 seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2790 seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2791
2792 intel_runtime_pm_put(dev_priv);
2793
2794 return 0;
2795 }
2796
2797 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2798 struct drm_display_mode *mode)
2799 {
2800 int i;
2801
2802 for (i = 0; i < tabs; i++)
2803 seq_putc(m, '\t');
2804
2805 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2806 mode->base.id, mode->name,
2807 mode->vrefresh, mode->clock,
2808 mode->hdisplay, mode->hsync_start,
2809 mode->hsync_end, mode->htotal,
2810 mode->vdisplay, mode->vsync_start,
2811 mode->vsync_end, mode->vtotal,
2812 mode->type, mode->flags);
2813 }
2814
2815 static void intel_encoder_info(struct seq_file *m,
2816 struct intel_crtc *intel_crtc,
2817 struct intel_encoder *intel_encoder)
2818 {
2819 struct drm_info_node *node = m->private;
2820 struct drm_device *dev = node->minor->dev;
2821 struct drm_crtc *crtc = &intel_crtc->base;
2822 struct intel_connector *intel_connector;
2823 struct drm_encoder *encoder;
2824
2825 encoder = &intel_encoder->base;
2826 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2827 encoder->base.id, encoder->name);
2828 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2829 struct drm_connector *connector = &intel_connector->base;
2830 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2831 connector->base.id,
2832 connector->name,
2833 drm_get_connector_status_name(connector->status));
2834 if (connector->status == connector_status_connected) {
2835 struct drm_display_mode *mode = &crtc->mode;
2836 seq_printf(m, ", mode:\n");
2837 intel_seq_print_mode(m, 2, mode);
2838 } else {
2839 seq_putc(m, '\n');
2840 }
2841 }
2842 }
2843
2844 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2845 {
2846 struct drm_info_node *node = m->private;
2847 struct drm_device *dev = node->minor->dev;
2848 struct drm_crtc *crtc = &intel_crtc->base;
2849 struct intel_encoder *intel_encoder;
2850 struct drm_plane_state *plane_state = crtc->primary->state;
2851 struct drm_framebuffer *fb = plane_state->fb;
2852
2853 if (fb)
2854 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2855 fb->base.id, plane_state->src_x >> 16,
2856 plane_state->src_y >> 16, fb->width, fb->height);
2857 else
2858 seq_puts(m, "\tprimary plane disabled\n");
2859 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2860 intel_encoder_info(m, intel_crtc, intel_encoder);
2861 }
2862
2863 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2864 {
2865 struct drm_display_mode *mode = panel->fixed_mode;
2866
2867 seq_printf(m, "\tfixed mode:\n");
2868 intel_seq_print_mode(m, 2, mode);
2869 }
2870
2871 static void intel_dp_info(struct seq_file *m,
2872 struct intel_connector *intel_connector)
2873 {
2874 struct intel_encoder *intel_encoder = intel_connector->encoder;
2875 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2876
2877 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2878 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2879 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2880 intel_panel_info(m, &intel_connector->panel);
2881 }
2882
2883 static void intel_dp_mst_info(struct seq_file *m,
2884 struct intel_connector *intel_connector)
2885 {
2886 struct intel_encoder *intel_encoder = intel_connector->encoder;
2887 struct intel_dp_mst_encoder *intel_mst =
2888 enc_to_mst(&intel_encoder->base);
2889 struct intel_digital_port *intel_dig_port = intel_mst->primary;
2890 struct intel_dp *intel_dp = &intel_dig_port->dp;
2891 bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr,
2892 intel_connector->port);
2893
2894 seq_printf(m, "\taudio support: %s\n", yesno(has_audio));
2895 }
2896
2897 static void intel_hdmi_info(struct seq_file *m,
2898 struct intel_connector *intel_connector)
2899 {
2900 struct intel_encoder *intel_encoder = intel_connector->encoder;
2901 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2902
2903 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2904 }
2905
2906 static void intel_lvds_info(struct seq_file *m,
2907 struct intel_connector *intel_connector)
2908 {
2909 intel_panel_info(m, &intel_connector->panel);
2910 }
2911
2912 static void intel_connector_info(struct seq_file *m,
2913 struct drm_connector *connector)
2914 {
2915 struct intel_connector *intel_connector = to_intel_connector(connector);
2916 struct intel_encoder *intel_encoder = intel_connector->encoder;
2917 struct drm_display_mode *mode;
2918
2919 seq_printf(m, "connector %d: type %s, status: %s\n",
2920 connector->base.id, connector->name,
2921 drm_get_connector_status_name(connector->status));
2922 if (connector->status == connector_status_connected) {
2923 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2924 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2925 connector->display_info.width_mm,
2926 connector->display_info.height_mm);
2927 seq_printf(m, "\tsubpixel order: %s\n",
2928 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2929 seq_printf(m, "\tCEA rev: %d\n",
2930 connector->display_info.cea_rev);
2931 }
2932 if (intel_encoder) {
2933 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2934 intel_encoder->type == INTEL_OUTPUT_EDP)
2935 intel_dp_info(m, intel_connector);
2936 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2937 intel_hdmi_info(m, intel_connector);
2938 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2939 intel_lvds_info(m, intel_connector);
2940 else if (intel_encoder->type == INTEL_OUTPUT_DP_MST)
2941 intel_dp_mst_info(m, intel_connector);
2942 }
2943
2944 seq_printf(m, "\tmodes:\n");
2945 list_for_each_entry(mode, &connector->modes, head)
2946 intel_seq_print_mode(m, 2, mode);
2947 }
2948
2949 static bool cursor_active(struct drm_device *dev, int pipe)
2950 {
2951 struct drm_i915_private *dev_priv = dev->dev_private;
2952 u32 state;
2953
2954 if (IS_845G(dev) || IS_I865G(dev))
2955 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
2956 else
2957 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2958
2959 return state;
2960 }
2961
2962 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2963 {
2964 struct drm_i915_private *dev_priv = dev->dev_private;
2965 u32 pos;
2966
2967 pos = I915_READ(CURPOS(pipe));
2968
2969 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2970 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2971 *x = -*x;
2972
2973 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2974 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2975 *y = -*y;
2976
2977 return cursor_active(dev, pipe);
2978 }
2979
2980 static const char *plane_type(enum drm_plane_type type)
2981 {
2982 switch (type) {
2983 case DRM_PLANE_TYPE_OVERLAY:
2984 return "OVL";
2985 case DRM_PLANE_TYPE_PRIMARY:
2986 return "PRI";
2987 case DRM_PLANE_TYPE_CURSOR:
2988 return "CUR";
2989 /*
2990 * Deliberately omitting default: to generate compiler warnings
2991 * when a new drm_plane_type gets added.
2992 */
2993 }
2994
2995 return "unknown";
2996 }
2997
2998 static const char *plane_rotation(unsigned int rotation)
2999 {
3000 static char buf[48];
3001 /*
3002 * According to doc only one DRM_ROTATE_ is allowed but this
3003 * will print them all to visualize if the values are misused
3004 */
3005 snprintf(buf, sizeof(buf),
3006 "%s%s%s%s%s%s(0x%08x)",
3007 (rotation & BIT(DRM_ROTATE_0)) ? "0 " : "",
3008 (rotation & BIT(DRM_ROTATE_90)) ? "90 " : "",
3009 (rotation & BIT(DRM_ROTATE_180)) ? "180 " : "",
3010 (rotation & BIT(DRM_ROTATE_270)) ? "270 " : "",
3011 (rotation & BIT(DRM_REFLECT_X)) ? "FLIPX " : "",
3012 (rotation & BIT(DRM_REFLECT_Y)) ? "FLIPY " : "",
3013 rotation);
3014
3015 return buf;
3016 }
3017
3018 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3019 {
3020 struct drm_info_node *node = m->private;
3021 struct drm_device *dev = node->minor->dev;
3022 struct intel_plane *intel_plane;
3023
3024 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3025 struct drm_plane_state *state;
3026 struct drm_plane *plane = &intel_plane->base;
3027
3028 if (!plane->state) {
3029 seq_puts(m, "plane->state is NULL!\n");
3030 continue;
3031 }
3032
3033 state = plane->state;
3034
3035 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3036 plane->base.id,
3037 plane_type(intel_plane->base.type),
3038 state->crtc_x, state->crtc_y,
3039 state->crtc_w, state->crtc_h,
3040 (state->src_x >> 16),
3041 ((state->src_x & 0xffff) * 15625) >> 10,
3042 (state->src_y >> 16),
3043 ((state->src_y & 0xffff) * 15625) >> 10,
3044 (state->src_w >> 16),
3045 ((state->src_w & 0xffff) * 15625) >> 10,
3046 (state->src_h >> 16),
3047 ((state->src_h & 0xffff) * 15625) >> 10,
3048 state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A",
3049 plane_rotation(state->rotation));
3050 }
3051 }
3052
3053 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3054 {
3055 struct intel_crtc_state *pipe_config;
3056 int num_scalers = intel_crtc->num_scalers;
3057 int i;
3058
3059 pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3060
3061 /* Not all platformas have a scaler */
3062 if (num_scalers) {
3063 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3064 num_scalers,
3065 pipe_config->scaler_state.scaler_users,
3066 pipe_config->scaler_state.scaler_id);
3067
3068 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3069 struct intel_scaler *sc =
3070 &pipe_config->scaler_state.scalers[i];
3071
3072 seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3073 i, yesno(sc->in_use), sc->mode);
3074 }
3075 seq_puts(m, "\n");
3076 } else {
3077 seq_puts(m, "\tNo scalers available on this platform\n");
3078 }
3079 }
3080
3081 static int i915_display_info(struct seq_file *m, void *unused)
3082 {
3083 struct drm_info_node *node = m->private;
3084 struct drm_device *dev = node->minor->dev;
3085 struct drm_i915_private *dev_priv = dev->dev_private;
3086 struct intel_crtc *crtc;
3087 struct drm_connector *connector;
3088
3089 intel_runtime_pm_get(dev_priv);
3090 drm_modeset_lock_all(dev);
3091 seq_printf(m, "CRTC info\n");
3092 seq_printf(m, "---------\n");
3093 for_each_intel_crtc(dev, crtc) {
3094 bool active;
3095 struct intel_crtc_state *pipe_config;
3096 int x, y;
3097
3098 pipe_config = to_intel_crtc_state(crtc->base.state);
3099
3100 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3101 crtc->base.base.id, pipe_name(crtc->pipe),
3102 yesno(pipe_config->base.active),
3103 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3104 yesno(pipe_config->dither), pipe_config->pipe_bpp);
3105
3106 if (pipe_config->base.active) {
3107 intel_crtc_info(m, crtc);
3108
3109 active = cursor_position(dev, crtc->pipe, &x, &y);
3110 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3111 yesno(crtc->cursor_base),
3112 x, y, crtc->base.cursor->state->crtc_w,
3113 crtc->base.cursor->state->crtc_h,
3114 crtc->cursor_addr, yesno(active));
3115 intel_scaler_info(m, crtc);
3116 intel_plane_info(m, crtc);
3117 }
3118
3119 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3120 yesno(!crtc->cpu_fifo_underrun_disabled),
3121 yesno(!crtc->pch_fifo_underrun_disabled));
3122 }
3123
3124 seq_printf(m, "\n");
3125 seq_printf(m, "Connector info\n");
3126 seq_printf(m, "--------------\n");
3127 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3128 intel_connector_info(m, connector);
3129 }
3130 drm_modeset_unlock_all(dev);
3131 intel_runtime_pm_put(dev_priv);
3132
3133 return 0;
3134 }
3135
3136 static int i915_semaphore_status(struct seq_file *m, void *unused)
3137 {
3138 struct drm_info_node *node = (struct drm_info_node *) m->private;
3139 struct drm_device *dev = node->minor->dev;
3140 struct drm_i915_private *dev_priv = dev->dev_private;
3141 struct intel_engine_cs *engine;
3142 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
3143 enum intel_engine_id id;
3144 int j, ret;
3145
3146 if (!i915_semaphore_is_enabled(dev)) {
3147 seq_puts(m, "Semaphores are disabled\n");
3148 return 0;
3149 }
3150
3151 ret = mutex_lock_interruptible(&dev->struct_mutex);
3152 if (ret)
3153 return ret;
3154 intel_runtime_pm_get(dev_priv);
3155
3156 if (IS_BROADWELL(dev)) {
3157 struct page *page;
3158 uint64_t *seqno;
3159
3160 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
3161
3162 seqno = (uint64_t *)kmap_atomic(page);
3163 for_each_engine_id(engine, dev_priv, id) {
3164 uint64_t offset;
3165
3166 seq_printf(m, "%s\n", engine->name);
3167
3168 seq_puts(m, " Last signal:");
3169 for (j = 0; j < num_rings; j++) {
3170 offset = id * I915_NUM_ENGINES + j;
3171 seq_printf(m, "0x%08llx (0x%02llx) ",
3172 seqno[offset], offset * 8);
3173 }
3174 seq_putc(m, '\n');
3175
3176 seq_puts(m, " Last wait: ");
3177 for (j = 0; j < num_rings; j++) {
3178 offset = id + (j * I915_NUM_ENGINES);
3179 seq_printf(m, "0x%08llx (0x%02llx) ",
3180 seqno[offset], offset * 8);
3181 }
3182 seq_putc(m, '\n');
3183
3184 }
3185 kunmap_atomic(seqno);
3186 } else {
3187 seq_puts(m, " Last signal:");
3188 for_each_engine(engine, dev_priv)
3189 for (j = 0; j < num_rings; j++)
3190 seq_printf(m, "0x%08x\n",
3191 I915_READ(engine->semaphore.mbox.signal[j]));
3192 seq_putc(m, '\n');
3193 }
3194
3195 seq_puts(m, "\nSync seqno:\n");
3196 for_each_engine(engine, dev_priv) {
3197 for (j = 0; j < num_rings; j++)
3198 seq_printf(m, " 0x%08x ",
3199 engine->semaphore.sync_seqno[j]);
3200 seq_putc(m, '\n');
3201 }
3202 seq_putc(m, '\n');
3203
3204 intel_runtime_pm_put(dev_priv);
3205 mutex_unlock(&dev->struct_mutex);
3206 return 0;
3207 }
3208
3209 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3210 {
3211 struct drm_info_node *node = (struct drm_info_node *) m->private;
3212 struct drm_device *dev = node->minor->dev;
3213 struct drm_i915_private *dev_priv = dev->dev_private;
3214 int i;
3215
3216 drm_modeset_lock_all(dev);
3217 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3218 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3219
3220 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3221 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3222 pll->config.crtc_mask, pll->active_mask, yesno(pll->on));
3223 seq_printf(m, " tracked hardware state:\n");
3224 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
3225 seq_printf(m, " dpll_md: 0x%08x\n",
3226 pll->config.hw_state.dpll_md);
3227 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
3228 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
3229 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
3230 }
3231 drm_modeset_unlock_all(dev);
3232
3233 return 0;
3234 }
3235
3236 static int i915_wa_registers(struct seq_file *m, void *unused)
3237 {
3238 int i;
3239 int ret;
3240 struct intel_engine_cs *engine;
3241 struct drm_info_node *node = (struct drm_info_node *) m->private;
3242 struct drm_device *dev = node->minor->dev;
3243 struct drm_i915_private *dev_priv = dev->dev_private;
3244 struct i915_workarounds *workarounds = &dev_priv->workarounds;
3245 enum intel_engine_id id;
3246
3247 ret = mutex_lock_interruptible(&dev->struct_mutex);
3248 if (ret)
3249 return ret;
3250
3251 intel_runtime_pm_get(dev_priv);
3252
3253 seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3254 for_each_engine_id(engine, dev_priv, id)
3255 seq_printf(m, "HW whitelist count for %s: %d\n",
3256 engine->name, workarounds->hw_whitelist_count[id]);
3257 for (i = 0; i < workarounds->count; ++i) {
3258 i915_reg_t addr;
3259 u32 mask, value, read;
3260 bool ok;
3261
3262 addr = workarounds->reg[i].addr;
3263 mask = workarounds->reg[i].mask;
3264 value = workarounds->reg[i].value;
3265 read = I915_READ(addr);
3266 ok = (value & mask) == (read & mask);
3267 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3268 i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3269 }
3270
3271 intel_runtime_pm_put(dev_priv);
3272 mutex_unlock(&dev->struct_mutex);
3273
3274 return 0;
3275 }
3276
3277 static int i915_ddb_info(struct seq_file *m, void *unused)
3278 {
3279 struct drm_info_node *node = m->private;
3280 struct drm_device *dev = node->minor->dev;
3281 struct drm_i915_private *dev_priv = dev->dev_private;
3282 struct skl_ddb_allocation *ddb;
3283 struct skl_ddb_entry *entry;
3284 enum pipe pipe;
3285 int plane;
3286
3287 if (INTEL_INFO(dev)->gen < 9)
3288 return 0;
3289
3290 drm_modeset_lock_all(dev);
3291
3292 ddb = &dev_priv->wm.skl_hw.ddb;
3293
3294 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3295
3296 for_each_pipe(dev_priv, pipe) {
3297 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3298
3299 for_each_plane(dev_priv, pipe, plane) {
3300 entry = &ddb->plane[pipe][plane];
3301 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
3302 entry->start, entry->end,
3303 skl_ddb_entry_size(entry));
3304 }
3305
3306 entry = &ddb->plane[pipe][PLANE_CURSOR];
3307 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
3308 entry->end, skl_ddb_entry_size(entry));
3309 }
3310
3311 drm_modeset_unlock_all(dev);
3312
3313 return 0;
3314 }
3315
3316 static void drrs_status_per_crtc(struct seq_file *m,
3317 struct drm_device *dev, struct intel_crtc *intel_crtc)
3318 {
3319 struct intel_encoder *intel_encoder;
3320 struct drm_i915_private *dev_priv = dev->dev_private;
3321 struct i915_drrs *drrs = &dev_priv->drrs;
3322 int vrefresh = 0;
3323
3324 for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
3325 /* Encoder connected on this CRTC */
3326 switch (intel_encoder->type) {
3327 case INTEL_OUTPUT_EDP:
3328 seq_puts(m, "eDP:\n");
3329 break;
3330 case INTEL_OUTPUT_DSI:
3331 seq_puts(m, "DSI:\n");
3332 break;
3333 case INTEL_OUTPUT_HDMI:
3334 seq_puts(m, "HDMI:\n");
3335 break;
3336 case INTEL_OUTPUT_DISPLAYPORT:
3337 seq_puts(m, "DP:\n");
3338 break;
3339 default:
3340 seq_printf(m, "Other encoder (id=%d).\n",
3341 intel_encoder->type);
3342 return;
3343 }
3344 }
3345
3346 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3347 seq_puts(m, "\tVBT: DRRS_type: Static");
3348 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3349 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3350 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3351 seq_puts(m, "\tVBT: DRRS_type: None");
3352 else
3353 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3354
3355 seq_puts(m, "\n\n");
3356
3357 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3358 struct intel_panel *panel;
3359
3360 mutex_lock(&drrs->mutex);
3361 /* DRRS Supported */
3362 seq_puts(m, "\tDRRS Supported: Yes\n");
3363
3364 /* disable_drrs() will make drrs->dp NULL */
3365 if (!drrs->dp) {
3366 seq_puts(m, "Idleness DRRS: Disabled");
3367 mutex_unlock(&drrs->mutex);
3368 return;
3369 }
3370
3371 panel = &drrs->dp->attached_connector->panel;
3372 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3373 drrs->busy_frontbuffer_bits);
3374
3375 seq_puts(m, "\n\t\t");
3376 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3377 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3378 vrefresh = panel->fixed_mode->vrefresh;
3379 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3380 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3381 vrefresh = panel->downclock_mode->vrefresh;
3382 } else {
3383 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3384 drrs->refresh_rate_type);
3385 mutex_unlock(&drrs->mutex);
3386 return;
3387 }
3388 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3389
3390 seq_puts(m, "\n\t\t");
3391 mutex_unlock(&drrs->mutex);
3392 } else {
3393 /* DRRS not supported. Print the VBT parameter*/
3394 seq_puts(m, "\tDRRS Supported : No");
3395 }
3396 seq_puts(m, "\n");
3397 }
3398
3399 static int i915_drrs_status(struct seq_file *m, void *unused)
3400 {
3401 struct drm_info_node *node = m->private;
3402 struct drm_device *dev = node->minor->dev;
3403 struct intel_crtc *intel_crtc;
3404 int active_crtc_cnt = 0;
3405
3406 for_each_intel_crtc(dev, intel_crtc) {
3407 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3408
3409 if (intel_crtc->base.state->active) {
3410 active_crtc_cnt++;
3411 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3412
3413 drrs_status_per_crtc(m, dev, intel_crtc);
3414 }
3415
3416 drm_modeset_unlock(&intel_crtc->base.mutex);
3417 }
3418
3419 if (!active_crtc_cnt)
3420 seq_puts(m, "No active crtc found\n");
3421
3422 return 0;
3423 }
3424
3425 struct pipe_crc_info {
3426 const char *name;
3427 struct drm_device *dev;
3428 enum pipe pipe;
3429 };
3430
3431 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3432 {
3433 struct drm_info_node *node = (struct drm_info_node *) m->private;
3434 struct drm_device *dev = node->minor->dev;
3435 struct drm_encoder *encoder;
3436 struct intel_encoder *intel_encoder;
3437 struct intel_digital_port *intel_dig_port;
3438 drm_modeset_lock_all(dev);
3439 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3440 intel_encoder = to_intel_encoder(encoder);
3441 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3442 continue;
3443 intel_dig_port = enc_to_dig_port(encoder);
3444 if (!intel_dig_port->dp.can_mst)
3445 continue;
3446
3447 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3448 }
3449 drm_modeset_unlock_all(dev);
3450 return 0;
3451 }
3452
3453 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3454 {
3455 struct pipe_crc_info *info = inode->i_private;
3456 struct drm_i915_private *dev_priv = info->dev->dev_private;
3457 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3458
3459 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3460 return -ENODEV;
3461
3462 spin_lock_irq(&pipe_crc->lock);
3463
3464 if (pipe_crc->opened) {
3465 spin_unlock_irq(&pipe_crc->lock);
3466 return -EBUSY; /* already open */
3467 }
3468
3469 pipe_crc->opened = true;
3470 filep->private_data = inode->i_private;
3471
3472 spin_unlock_irq(&pipe_crc->lock);
3473
3474 return 0;
3475 }
3476
3477 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3478 {
3479 struct pipe_crc_info *info = inode->i_private;
3480 struct drm_i915_private *dev_priv = info->dev->dev_private;
3481 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3482
3483 spin_lock_irq(&pipe_crc->lock);
3484 pipe_crc->opened = false;
3485 spin_unlock_irq(&pipe_crc->lock);
3486
3487 return 0;
3488 }
3489
3490 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3491 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3492 /* account for \'0' */
3493 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3494
3495 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3496 {
3497 assert_spin_locked(&pipe_crc->lock);
3498 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3499 INTEL_PIPE_CRC_ENTRIES_NR);
3500 }
3501
3502 static ssize_t
3503 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3504 loff_t *pos)
3505 {
3506 struct pipe_crc_info *info = filep->private_data;
3507 struct drm_device *dev = info->dev;
3508 struct drm_i915_private *dev_priv = dev->dev_private;
3509 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3510 char buf[PIPE_CRC_BUFFER_LEN];
3511 int n_entries;
3512 ssize_t bytes_read;
3513
3514 /*
3515 * Don't allow user space to provide buffers not big enough to hold
3516 * a line of data.
3517 */
3518 if (count < PIPE_CRC_LINE_LEN)
3519 return -EINVAL;
3520
3521 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3522 return 0;
3523
3524 /* nothing to read */
3525 spin_lock_irq(&pipe_crc->lock);
3526 while (pipe_crc_data_count(pipe_crc) == 0) {
3527 int ret;
3528
3529 if (filep->f_flags & O_NONBLOCK) {
3530 spin_unlock_irq(&pipe_crc->lock);
3531 return -EAGAIN;
3532 }
3533
3534 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3535 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3536 if (ret) {
3537 spin_unlock_irq(&pipe_crc->lock);
3538 return ret;
3539 }
3540 }
3541
3542 /* We now have one or more entries to read */
3543 n_entries = count / PIPE_CRC_LINE_LEN;
3544
3545 bytes_read = 0;
3546 while (n_entries > 0) {
3547 struct intel_pipe_crc_entry *entry =
3548 &pipe_crc->entries[pipe_crc->tail];
3549 int ret;
3550
3551 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3552 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3553 break;
3554
3555 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3556 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3557
3558 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3559 "%8u %8x %8x %8x %8x %8x\n",
3560 entry->frame, entry->crc[0],
3561 entry->crc[1], entry->crc[2],
3562 entry->crc[3], entry->crc[4]);
3563
3564 spin_unlock_irq(&pipe_crc->lock);
3565
3566 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
3567 if (ret == PIPE_CRC_LINE_LEN)
3568 return -EFAULT;
3569
3570 user_buf += PIPE_CRC_LINE_LEN;
3571 n_entries--;
3572
3573 spin_lock_irq(&pipe_crc->lock);
3574 }
3575
3576 spin_unlock_irq(&pipe_crc->lock);
3577
3578 return bytes_read;
3579 }
3580
3581 static const struct file_operations i915_pipe_crc_fops = {
3582 .owner = THIS_MODULE,
3583 .open = i915_pipe_crc_open,
3584 .read = i915_pipe_crc_read,
3585 .release = i915_pipe_crc_release,
3586 };
3587
3588 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3589 {
3590 .name = "i915_pipe_A_crc",
3591 .pipe = PIPE_A,
3592 },
3593 {
3594 .name = "i915_pipe_B_crc",
3595 .pipe = PIPE_B,
3596 },
3597 {
3598 .name = "i915_pipe_C_crc",
3599 .pipe = PIPE_C,
3600 },
3601 };
3602
3603 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3604 enum pipe pipe)
3605 {
3606 struct drm_device *dev = minor->dev;
3607 struct dentry *ent;
3608 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3609
3610 info->dev = dev;
3611 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3612 &i915_pipe_crc_fops);
3613 if (!ent)
3614 return -ENOMEM;
3615
3616 return drm_add_fake_info_node(minor, ent, info);
3617 }
3618
3619 static const char * const pipe_crc_sources[] = {
3620 "none",
3621 "plane1",
3622 "plane2",
3623 "pf",
3624 "pipe",
3625 "TV",
3626 "DP-B",
3627 "DP-C",
3628 "DP-D",
3629 "auto",
3630 };
3631
3632 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3633 {
3634 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3635 return pipe_crc_sources[source];
3636 }
3637
3638 static int display_crc_ctl_show(struct seq_file *m, void *data)
3639 {
3640 struct drm_device *dev = m->private;
3641 struct drm_i915_private *dev_priv = dev->dev_private;
3642 int i;
3643
3644 for (i = 0; i < I915_MAX_PIPES; i++)
3645 seq_printf(m, "%c %s\n", pipe_name(i),
3646 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3647
3648 return 0;
3649 }
3650
3651 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3652 {
3653 struct drm_device *dev = inode->i_private;
3654
3655 return single_open(file, display_crc_ctl_show, dev);
3656 }
3657
3658 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3659 uint32_t *val)
3660 {
3661 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3662 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3663
3664 switch (*source) {
3665 case INTEL_PIPE_CRC_SOURCE_PIPE:
3666 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3667 break;
3668 case INTEL_PIPE_CRC_SOURCE_NONE:
3669 *val = 0;
3670 break;
3671 default:
3672 return -EINVAL;
3673 }
3674
3675 return 0;
3676 }
3677
3678 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3679 enum intel_pipe_crc_source *source)
3680 {
3681 struct intel_encoder *encoder;
3682 struct intel_crtc *crtc;
3683 struct intel_digital_port *dig_port;
3684 int ret = 0;
3685
3686 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3687
3688 drm_modeset_lock_all(dev);
3689 for_each_intel_encoder(dev, encoder) {
3690 if (!encoder->base.crtc)
3691 continue;
3692
3693 crtc = to_intel_crtc(encoder->base.crtc);
3694
3695 if (crtc->pipe != pipe)
3696 continue;
3697
3698 switch (encoder->type) {
3699 case INTEL_OUTPUT_TVOUT:
3700 *source = INTEL_PIPE_CRC_SOURCE_TV;
3701 break;
3702 case INTEL_OUTPUT_DISPLAYPORT:
3703 case INTEL_OUTPUT_EDP:
3704 dig_port = enc_to_dig_port(&encoder->base);
3705 switch (dig_port->port) {
3706 case PORT_B:
3707 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3708 break;
3709 case PORT_C:
3710 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3711 break;
3712 case PORT_D:
3713 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3714 break;
3715 default:
3716 WARN(1, "nonexisting DP port %c\n",
3717 port_name(dig_port->port));
3718 break;
3719 }
3720 break;
3721 default:
3722 break;
3723 }
3724 }
3725 drm_modeset_unlock_all(dev);
3726
3727 return ret;
3728 }
3729
3730 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3731 enum pipe pipe,
3732 enum intel_pipe_crc_source *source,
3733 uint32_t *val)
3734 {
3735 struct drm_i915_private *dev_priv = dev->dev_private;
3736 bool need_stable_symbols = false;
3737
3738 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3739 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3740 if (ret)
3741 return ret;
3742 }
3743
3744 switch (*source) {
3745 case INTEL_PIPE_CRC_SOURCE_PIPE:
3746 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3747 break;
3748 case INTEL_PIPE_CRC_SOURCE_DP_B:
3749 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3750 need_stable_symbols = true;
3751 break;
3752 case INTEL_PIPE_CRC_SOURCE_DP_C:
3753 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3754 need_stable_symbols = true;
3755 break;
3756 case INTEL_PIPE_CRC_SOURCE_DP_D:
3757 if (!IS_CHERRYVIEW(dev))
3758 return -EINVAL;
3759 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3760 need_stable_symbols = true;
3761 break;
3762 case INTEL_PIPE_CRC_SOURCE_NONE:
3763 *val = 0;
3764 break;
3765 default:
3766 return -EINVAL;
3767 }
3768
3769 /*
3770 * When the pipe CRC tap point is after the transcoders we need
3771 * to tweak symbol-level features to produce a deterministic series of
3772 * symbols for a given frame. We need to reset those features only once
3773 * a frame (instead of every nth symbol):
3774 * - DC-balance: used to ensure a better clock recovery from the data
3775 * link (SDVO)
3776 * - DisplayPort scrambling: used for EMI reduction
3777 */
3778 if (need_stable_symbols) {
3779 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3780
3781 tmp |= DC_BALANCE_RESET_VLV;
3782 switch (pipe) {
3783 case PIPE_A:
3784 tmp |= PIPE_A_SCRAMBLE_RESET;
3785 break;
3786 case PIPE_B:
3787 tmp |= PIPE_B_SCRAMBLE_RESET;
3788 break;
3789 case PIPE_C:
3790 tmp |= PIPE_C_SCRAMBLE_RESET;
3791 break;
3792 default:
3793 return -EINVAL;
3794 }
3795 I915_WRITE(PORT_DFT2_G4X, tmp);
3796 }
3797
3798 return 0;
3799 }
3800
3801 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3802 enum pipe pipe,
3803 enum intel_pipe_crc_source *source,
3804 uint32_t *val)
3805 {
3806 struct drm_i915_private *dev_priv = dev->dev_private;
3807 bool need_stable_symbols = false;
3808
3809 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3810 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3811 if (ret)
3812 return ret;
3813 }
3814
3815 switch (*source) {
3816 case INTEL_PIPE_CRC_SOURCE_PIPE:
3817 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3818 break;
3819 case INTEL_PIPE_CRC_SOURCE_TV:
3820 if (!SUPPORTS_TV(dev))
3821 return -EINVAL;
3822 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3823 break;
3824 case INTEL_PIPE_CRC_SOURCE_DP_B:
3825 if (!IS_G4X(dev))
3826 return -EINVAL;
3827 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3828 need_stable_symbols = true;
3829 break;
3830 case INTEL_PIPE_CRC_SOURCE_DP_C:
3831 if (!IS_G4X(dev))
3832 return -EINVAL;
3833 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3834 need_stable_symbols = true;
3835 break;
3836 case INTEL_PIPE_CRC_SOURCE_DP_D:
3837 if (!IS_G4X(dev))
3838 return -EINVAL;
3839 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3840 need_stable_symbols = true;
3841 break;
3842 case INTEL_PIPE_CRC_SOURCE_NONE:
3843 *val = 0;
3844 break;
3845 default:
3846 return -EINVAL;
3847 }
3848
3849 /*
3850 * When the pipe CRC tap point is after the transcoders we need
3851 * to tweak symbol-level features to produce a deterministic series of
3852 * symbols for a given frame. We need to reset those features only once
3853 * a frame (instead of every nth symbol):
3854 * - DC-balance: used to ensure a better clock recovery from the data
3855 * link (SDVO)
3856 * - DisplayPort scrambling: used for EMI reduction
3857 */
3858 if (need_stable_symbols) {
3859 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3860
3861 WARN_ON(!IS_G4X(dev));
3862
3863 I915_WRITE(PORT_DFT_I9XX,
3864 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3865
3866 if (pipe == PIPE_A)
3867 tmp |= PIPE_A_SCRAMBLE_RESET;
3868 else
3869 tmp |= PIPE_B_SCRAMBLE_RESET;
3870
3871 I915_WRITE(PORT_DFT2_G4X, tmp);
3872 }
3873
3874 return 0;
3875 }
3876
3877 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3878 enum pipe pipe)
3879 {
3880 struct drm_i915_private *dev_priv = dev->dev_private;
3881 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3882
3883 switch (pipe) {
3884 case PIPE_A:
3885 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3886 break;
3887 case PIPE_B:
3888 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3889 break;
3890 case PIPE_C:
3891 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3892 break;
3893 default:
3894 return;
3895 }
3896 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3897 tmp &= ~DC_BALANCE_RESET_VLV;
3898 I915_WRITE(PORT_DFT2_G4X, tmp);
3899
3900 }
3901
3902 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3903 enum pipe pipe)
3904 {
3905 struct drm_i915_private *dev_priv = dev->dev_private;
3906 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3907
3908 if (pipe == PIPE_A)
3909 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3910 else
3911 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3912 I915_WRITE(PORT_DFT2_G4X, tmp);
3913
3914 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3915 I915_WRITE(PORT_DFT_I9XX,
3916 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3917 }
3918 }
3919
3920 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3921 uint32_t *val)
3922 {
3923 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3924 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3925
3926 switch (*source) {
3927 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3928 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3929 break;
3930 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3931 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3932 break;
3933 case INTEL_PIPE_CRC_SOURCE_PIPE:
3934 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3935 break;
3936 case INTEL_PIPE_CRC_SOURCE_NONE:
3937 *val = 0;
3938 break;
3939 default:
3940 return -EINVAL;
3941 }
3942
3943 return 0;
3944 }
3945
3946 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
3947 {
3948 struct drm_i915_private *dev_priv = dev->dev_private;
3949 struct intel_crtc *crtc =
3950 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3951 struct intel_crtc_state *pipe_config;
3952 struct drm_atomic_state *state;
3953 int ret = 0;
3954
3955 drm_modeset_lock_all(dev);
3956 state = drm_atomic_state_alloc(dev);
3957 if (!state) {
3958 ret = -ENOMEM;
3959 goto out;
3960 }
3961
3962 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
3963 pipe_config = intel_atomic_get_crtc_state(state, crtc);
3964 if (IS_ERR(pipe_config)) {
3965 ret = PTR_ERR(pipe_config);
3966 goto out;
3967 }
3968
3969 pipe_config->pch_pfit.force_thru = enable;
3970 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
3971 pipe_config->pch_pfit.enabled != enable)
3972 pipe_config->base.connectors_changed = true;
3973
3974 ret = drm_atomic_commit(state);
3975 out:
3976 drm_modeset_unlock_all(dev);
3977 WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
3978 if (ret)
3979 drm_atomic_state_free(state);
3980 }
3981
3982 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3983 enum pipe pipe,
3984 enum intel_pipe_crc_source *source,
3985 uint32_t *val)
3986 {
3987 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3988 *source = INTEL_PIPE_CRC_SOURCE_PF;
3989
3990 switch (*source) {
3991 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3992 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3993 break;
3994 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3995 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3996 break;
3997 case INTEL_PIPE_CRC_SOURCE_PF:
3998 if (IS_HASWELL(dev) && pipe == PIPE_A)
3999 hsw_trans_edp_pipe_A_crc_wa(dev, true);
4000
4001 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
4002 break;
4003 case INTEL_PIPE_CRC_SOURCE_NONE:
4004 *val = 0;
4005 break;
4006 default:
4007 return -EINVAL;
4008 }
4009
4010 return 0;
4011 }
4012
4013 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
4014 enum intel_pipe_crc_source source)
4015 {
4016 struct drm_i915_private *dev_priv = dev->dev_private;
4017 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4018 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
4019 pipe));
4020 enum intel_display_power_domain power_domain;
4021 u32 val = 0; /* shut up gcc */
4022 int ret;
4023
4024 if (pipe_crc->source == source)
4025 return 0;
4026
4027 /* forbid changing the source without going back to 'none' */
4028 if (pipe_crc->source && source)
4029 return -EINVAL;
4030
4031 power_domain = POWER_DOMAIN_PIPE(pipe);
4032 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
4033 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4034 return -EIO;
4035 }
4036
4037 if (IS_GEN2(dev))
4038 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
4039 else if (INTEL_INFO(dev)->gen < 5)
4040 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4041 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4042 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4043 else if (IS_GEN5(dev) || IS_GEN6(dev))
4044 ret = ilk_pipe_crc_ctl_reg(&source, &val);
4045 else
4046 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4047
4048 if (ret != 0)
4049 goto out;
4050
4051 /* none -> real source transition */
4052 if (source) {
4053 struct intel_pipe_crc_entry *entries;
4054
4055 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4056 pipe_name(pipe), pipe_crc_source_name(source));
4057
4058 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4059 sizeof(pipe_crc->entries[0]),
4060 GFP_KERNEL);
4061 if (!entries) {
4062 ret = -ENOMEM;
4063 goto out;
4064 }
4065
4066 /*
4067 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4068 * enabled and disabled dynamically based on package C states,
4069 * user space can't make reliable use of the CRCs, so let's just
4070 * completely disable it.
4071 */
4072 hsw_disable_ips(crtc);
4073
4074 spin_lock_irq(&pipe_crc->lock);
4075 kfree(pipe_crc->entries);
4076 pipe_crc->entries = entries;
4077 pipe_crc->head = 0;
4078 pipe_crc->tail = 0;
4079 spin_unlock_irq(&pipe_crc->lock);
4080 }
4081
4082 pipe_crc->source = source;
4083
4084 I915_WRITE(PIPE_CRC_CTL(pipe), val);
4085 POSTING_READ(PIPE_CRC_CTL(pipe));
4086
4087 /* real source -> none transition */
4088 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
4089 struct intel_pipe_crc_entry *entries;
4090 struct intel_crtc *crtc =
4091 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
4092
4093 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4094 pipe_name(pipe));
4095
4096 drm_modeset_lock(&crtc->base.mutex, NULL);
4097 if (crtc->base.state->active)
4098 intel_wait_for_vblank(dev, pipe);
4099 drm_modeset_unlock(&crtc->base.mutex);
4100
4101 spin_lock_irq(&pipe_crc->lock);
4102 entries = pipe_crc->entries;
4103 pipe_crc->entries = NULL;
4104 pipe_crc->head = 0;
4105 pipe_crc->tail = 0;
4106 spin_unlock_irq(&pipe_crc->lock);
4107
4108 kfree(entries);
4109
4110 if (IS_G4X(dev))
4111 g4x_undo_pipe_scramble_reset(dev, pipe);
4112 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4113 vlv_undo_pipe_scramble_reset(dev, pipe);
4114 else if (IS_HASWELL(dev) && pipe == PIPE_A)
4115 hsw_trans_edp_pipe_A_crc_wa(dev, false);
4116
4117 hsw_enable_ips(crtc);
4118 }
4119
4120 ret = 0;
4121
4122 out:
4123 intel_display_power_put(dev_priv, power_domain);
4124
4125 return ret;
4126 }
4127
4128 /*
4129 * Parse pipe CRC command strings:
4130 * command: wsp* object wsp+ name wsp+ source wsp*
4131 * object: 'pipe'
4132 * name: (A | B | C)
4133 * source: (none | plane1 | plane2 | pf)
4134 * wsp: (#0x20 | #0x9 | #0xA)+
4135 *
4136 * eg.:
4137 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
4138 * "pipe A none" -> Stop CRC
4139 */
4140 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
4141 {
4142 int n_words = 0;
4143
4144 while (*buf) {
4145 char *end;
4146
4147 /* skip leading white space */
4148 buf = skip_spaces(buf);
4149 if (!*buf)
4150 break; /* end of buffer */
4151
4152 /* find end of word */
4153 for (end = buf; *end && !isspace(*end); end++)
4154 ;
4155
4156 if (n_words == max_words) {
4157 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4158 max_words);
4159 return -EINVAL; /* ran out of words[] before bytes */
4160 }
4161
4162 if (*end)
4163 *end++ = '\0';
4164 words[n_words++] = buf;
4165 buf = end;
4166 }
4167
4168 return n_words;
4169 }
4170
4171 enum intel_pipe_crc_object {
4172 PIPE_CRC_OBJECT_PIPE,
4173 };
4174
4175 static const char * const pipe_crc_objects[] = {
4176 "pipe",
4177 };
4178
4179 static int
4180 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4181 {
4182 int i;
4183
4184 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4185 if (!strcmp(buf, pipe_crc_objects[i])) {
4186 *o = i;
4187 return 0;
4188 }
4189
4190 return -EINVAL;
4191 }
4192
4193 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4194 {
4195 const char name = buf[0];
4196
4197 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4198 return -EINVAL;
4199
4200 *pipe = name - 'A';
4201
4202 return 0;
4203 }
4204
4205 static int
4206 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4207 {
4208 int i;
4209
4210 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4211 if (!strcmp(buf, pipe_crc_sources[i])) {
4212 *s = i;
4213 return 0;
4214 }
4215
4216 return -EINVAL;
4217 }
4218
4219 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
4220 {
4221 #define N_WORDS 3
4222 int n_words;
4223 char *words[N_WORDS];
4224 enum pipe pipe;
4225 enum intel_pipe_crc_object object;
4226 enum intel_pipe_crc_source source;
4227
4228 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4229 if (n_words != N_WORDS) {
4230 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4231 N_WORDS);
4232 return -EINVAL;
4233 }
4234
4235 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4236 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4237 return -EINVAL;
4238 }
4239
4240 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4241 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4242 return -EINVAL;
4243 }
4244
4245 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4246 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4247 return -EINVAL;
4248 }
4249
4250 return pipe_crc_set_source(dev, pipe, source);
4251 }
4252
4253 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4254 size_t len, loff_t *offp)
4255 {
4256 struct seq_file *m = file->private_data;
4257 struct drm_device *dev = m->private;
4258 char *tmpbuf;
4259 int ret;
4260
4261 if (len == 0)
4262 return 0;
4263
4264 if (len > PAGE_SIZE - 1) {
4265 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4266 PAGE_SIZE);
4267 return -E2BIG;
4268 }
4269
4270 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4271 if (!tmpbuf)
4272 return -ENOMEM;
4273
4274 if (copy_from_user(tmpbuf, ubuf, len)) {
4275 ret = -EFAULT;
4276 goto out;
4277 }
4278 tmpbuf[len] = '\0';
4279
4280 ret = display_crc_ctl_parse(dev, tmpbuf, len);
4281
4282 out:
4283 kfree(tmpbuf);
4284 if (ret < 0)
4285 return ret;
4286
4287 *offp += len;
4288 return len;
4289 }
4290
4291 static const struct file_operations i915_display_crc_ctl_fops = {
4292 .owner = THIS_MODULE,
4293 .open = display_crc_ctl_open,
4294 .read = seq_read,
4295 .llseek = seq_lseek,
4296 .release = single_release,
4297 .write = display_crc_ctl_write
4298 };
4299
4300 static ssize_t i915_displayport_test_active_write(struct file *file,
4301 const char __user *ubuf,
4302 size_t len, loff_t *offp)
4303 {
4304 char *input_buffer;
4305 int status = 0;
4306 struct drm_device *dev;
4307 struct drm_connector *connector;
4308 struct list_head *connector_list;
4309 struct intel_dp *intel_dp;
4310 int val = 0;
4311
4312 dev = ((struct seq_file *)file->private_data)->private;
4313
4314 connector_list = &dev->mode_config.connector_list;
4315
4316 if (len == 0)
4317 return 0;
4318
4319 input_buffer = kmalloc(len + 1, GFP_KERNEL);
4320 if (!input_buffer)
4321 return -ENOMEM;
4322
4323 if (copy_from_user(input_buffer, ubuf, len)) {
4324 status = -EFAULT;
4325 goto out;
4326 }
4327
4328 input_buffer[len] = '\0';
4329 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4330
4331 list_for_each_entry(connector, connector_list, head) {
4332
4333 if (connector->connector_type !=
4334 DRM_MODE_CONNECTOR_DisplayPort)
4335 continue;
4336
4337 if (connector->status == connector_status_connected &&
4338 connector->encoder != NULL) {
4339 intel_dp = enc_to_intel_dp(connector->encoder);
4340 status = kstrtoint(input_buffer, 10, &val);
4341 if (status < 0)
4342 goto out;
4343 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4344 /* To prevent erroneous activation of the compliance
4345 * testing code, only accept an actual value of 1 here
4346 */
4347 if (val == 1)
4348 intel_dp->compliance_test_active = 1;
4349 else
4350 intel_dp->compliance_test_active = 0;
4351 }
4352 }
4353 out:
4354 kfree(input_buffer);
4355 if (status < 0)
4356 return status;
4357
4358 *offp += len;
4359 return len;
4360 }
4361
4362 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4363 {
4364 struct drm_device *dev = m->private;
4365 struct drm_connector *connector;
4366 struct list_head *connector_list = &dev->mode_config.connector_list;
4367 struct intel_dp *intel_dp;
4368
4369 list_for_each_entry(connector, connector_list, head) {
4370
4371 if (connector->connector_type !=
4372 DRM_MODE_CONNECTOR_DisplayPort)
4373 continue;
4374
4375 if (connector->status == connector_status_connected &&
4376 connector->encoder != NULL) {
4377 intel_dp = enc_to_intel_dp(connector->encoder);
4378 if (intel_dp->compliance_test_active)
4379 seq_puts(m, "1");
4380 else
4381 seq_puts(m, "0");
4382 } else
4383 seq_puts(m, "0");
4384 }
4385
4386 return 0;
4387 }
4388
4389 static int i915_displayport_test_active_open(struct inode *inode,
4390 struct file *file)
4391 {
4392 struct drm_device *dev = inode->i_private;
4393
4394 return single_open(file, i915_displayport_test_active_show, dev);
4395 }
4396
4397 static const struct file_operations i915_displayport_test_active_fops = {
4398 .owner = THIS_MODULE,
4399 .open = i915_displayport_test_active_open,
4400 .read = seq_read,
4401 .llseek = seq_lseek,
4402 .release = single_release,
4403 .write = i915_displayport_test_active_write
4404 };
4405
4406 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4407 {
4408 struct drm_device *dev = m->private;
4409 struct drm_connector *connector;
4410 struct list_head *connector_list = &dev->mode_config.connector_list;
4411 struct intel_dp *intel_dp;
4412
4413 list_for_each_entry(connector, connector_list, head) {
4414
4415 if (connector->connector_type !=
4416 DRM_MODE_CONNECTOR_DisplayPort)
4417 continue;
4418
4419 if (connector->status == connector_status_connected &&
4420 connector->encoder != NULL) {
4421 intel_dp = enc_to_intel_dp(connector->encoder);
4422 seq_printf(m, "%lx", intel_dp->compliance_test_data);
4423 } else
4424 seq_puts(m, "0");
4425 }
4426
4427 return 0;
4428 }
4429 static int i915_displayport_test_data_open(struct inode *inode,
4430 struct file *file)
4431 {
4432 struct drm_device *dev = inode->i_private;
4433
4434 return single_open(file, i915_displayport_test_data_show, dev);
4435 }
4436
4437 static const struct file_operations i915_displayport_test_data_fops = {
4438 .owner = THIS_MODULE,
4439 .open = i915_displayport_test_data_open,
4440 .read = seq_read,
4441 .llseek = seq_lseek,
4442 .release = single_release
4443 };
4444
4445 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4446 {
4447 struct drm_device *dev = m->private;
4448 struct drm_connector *connector;
4449 struct list_head *connector_list = &dev->mode_config.connector_list;
4450 struct intel_dp *intel_dp;
4451
4452 list_for_each_entry(connector, connector_list, head) {
4453
4454 if (connector->connector_type !=
4455 DRM_MODE_CONNECTOR_DisplayPort)
4456 continue;
4457
4458 if (connector->status == connector_status_connected &&
4459 connector->encoder != NULL) {
4460 intel_dp = enc_to_intel_dp(connector->encoder);
4461 seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4462 } else
4463 seq_puts(m, "0");
4464 }
4465
4466 return 0;
4467 }
4468
4469 static int i915_displayport_test_type_open(struct inode *inode,
4470 struct file *file)
4471 {
4472 struct drm_device *dev = inode->i_private;
4473
4474 return single_open(file, i915_displayport_test_type_show, dev);
4475 }
4476
4477 static const struct file_operations i915_displayport_test_type_fops = {
4478 .owner = THIS_MODULE,
4479 .open = i915_displayport_test_type_open,
4480 .read = seq_read,
4481 .llseek = seq_lseek,
4482 .release = single_release
4483 };
4484
4485 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4486 {
4487 struct drm_device *dev = m->private;
4488 int level;
4489 int num_levels;
4490
4491 if (IS_CHERRYVIEW(dev))
4492 num_levels = 3;
4493 else if (IS_VALLEYVIEW(dev))
4494 num_levels = 1;
4495 else
4496 num_levels = ilk_wm_max_level(dev) + 1;
4497
4498 drm_modeset_lock_all(dev);
4499
4500 for (level = 0; level < num_levels; level++) {
4501 unsigned int latency = wm[level];
4502
4503 /*
4504 * - WM1+ latency values in 0.5us units
4505 * - latencies are in us on gen9/vlv/chv
4506 */
4507 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) ||
4508 IS_CHERRYVIEW(dev))
4509 latency *= 10;
4510 else if (level > 0)
4511 latency *= 5;
4512
4513 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4514 level, wm[level], latency / 10, latency % 10);
4515 }
4516
4517 drm_modeset_unlock_all(dev);
4518 }
4519
4520 static int pri_wm_latency_show(struct seq_file *m, void *data)
4521 {
4522 struct drm_device *dev = m->private;
4523 struct drm_i915_private *dev_priv = dev->dev_private;
4524 const uint16_t *latencies;
4525
4526 if (INTEL_INFO(dev)->gen >= 9)
4527 latencies = dev_priv->wm.skl_latency;
4528 else
4529 latencies = to_i915(dev)->wm.pri_latency;
4530
4531 wm_latency_show(m, latencies);
4532
4533 return 0;
4534 }
4535
4536 static int spr_wm_latency_show(struct seq_file *m, void *data)
4537 {
4538 struct drm_device *dev = m->private;
4539 struct drm_i915_private *dev_priv = dev->dev_private;
4540 const uint16_t *latencies;
4541
4542 if (INTEL_INFO(dev)->gen >= 9)
4543 latencies = dev_priv->wm.skl_latency;
4544 else
4545 latencies = to_i915(dev)->wm.spr_latency;
4546
4547 wm_latency_show(m, latencies);
4548
4549 return 0;
4550 }
4551
4552 static int cur_wm_latency_show(struct seq_file *m, void *data)
4553 {
4554 struct drm_device *dev = m->private;
4555 struct drm_i915_private *dev_priv = dev->dev_private;
4556 const uint16_t *latencies;
4557
4558 if (INTEL_INFO(dev)->gen >= 9)
4559 latencies = dev_priv->wm.skl_latency;
4560 else
4561 latencies = to_i915(dev)->wm.cur_latency;
4562
4563 wm_latency_show(m, latencies);
4564
4565 return 0;
4566 }
4567
4568 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4569 {
4570 struct drm_device *dev = inode->i_private;
4571
4572 if (INTEL_INFO(dev)->gen < 5)
4573 return -ENODEV;
4574
4575 return single_open(file, pri_wm_latency_show, dev);
4576 }
4577
4578 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4579 {
4580 struct drm_device *dev = inode->i_private;
4581
4582 if (HAS_GMCH_DISPLAY(dev))
4583 return -ENODEV;
4584
4585 return single_open(file, spr_wm_latency_show, dev);
4586 }
4587
4588 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4589 {
4590 struct drm_device *dev = inode->i_private;
4591
4592 if (HAS_GMCH_DISPLAY(dev))
4593 return -ENODEV;
4594
4595 return single_open(file, cur_wm_latency_show, dev);
4596 }
4597
4598 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4599 size_t len, loff_t *offp, uint16_t wm[8])
4600 {
4601 struct seq_file *m = file->private_data;
4602 struct drm_device *dev = m->private;
4603 uint16_t new[8] = { 0 };
4604 int num_levels;
4605 int level;
4606 int ret;
4607 char tmp[32];
4608
4609 if (IS_CHERRYVIEW(dev))
4610 num_levels = 3;
4611 else if (IS_VALLEYVIEW(dev))
4612 num_levels = 1;
4613 else
4614 num_levels = ilk_wm_max_level(dev) + 1;
4615
4616 if (len >= sizeof(tmp))
4617 return -EINVAL;
4618
4619 if (copy_from_user(tmp, ubuf, len))
4620 return -EFAULT;
4621
4622 tmp[len] = '\0';
4623
4624 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4625 &new[0], &new[1], &new[2], &new[3],
4626 &new[4], &new[5], &new[6], &new[7]);
4627 if (ret != num_levels)
4628 return -EINVAL;
4629
4630 drm_modeset_lock_all(dev);
4631
4632 for (level = 0; level < num_levels; level++)
4633 wm[level] = new[level];
4634
4635 drm_modeset_unlock_all(dev);
4636
4637 return len;
4638 }
4639
4640
4641 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4642 size_t len, loff_t *offp)
4643 {
4644 struct seq_file *m = file->private_data;
4645 struct drm_device *dev = m->private;
4646 struct drm_i915_private *dev_priv = dev->dev_private;
4647 uint16_t *latencies;
4648
4649 if (INTEL_INFO(dev)->gen >= 9)
4650 latencies = dev_priv->wm.skl_latency;
4651 else
4652 latencies = to_i915(dev)->wm.pri_latency;
4653
4654 return wm_latency_write(file, ubuf, len, offp, latencies);
4655 }
4656
4657 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4658 size_t len, loff_t *offp)
4659 {
4660 struct seq_file *m = file->private_data;
4661 struct drm_device *dev = m->private;
4662 struct drm_i915_private *dev_priv = dev->dev_private;
4663 uint16_t *latencies;
4664
4665 if (INTEL_INFO(dev)->gen >= 9)
4666 latencies = dev_priv->wm.skl_latency;
4667 else
4668 latencies = to_i915(dev)->wm.spr_latency;
4669
4670 return wm_latency_write(file, ubuf, len, offp, latencies);
4671 }
4672
4673 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4674 size_t len, loff_t *offp)
4675 {
4676 struct seq_file *m = file->private_data;
4677 struct drm_device *dev = m->private;
4678 struct drm_i915_private *dev_priv = dev->dev_private;
4679 uint16_t *latencies;
4680
4681 if (INTEL_INFO(dev)->gen >= 9)
4682 latencies = dev_priv->wm.skl_latency;
4683 else
4684 latencies = to_i915(dev)->wm.cur_latency;
4685
4686 return wm_latency_write(file, ubuf, len, offp, latencies);
4687 }
4688
4689 static const struct file_operations i915_pri_wm_latency_fops = {
4690 .owner = THIS_MODULE,
4691 .open = pri_wm_latency_open,
4692 .read = seq_read,
4693 .llseek = seq_lseek,
4694 .release = single_release,
4695 .write = pri_wm_latency_write
4696 };
4697
4698 static const struct file_operations i915_spr_wm_latency_fops = {
4699 .owner = THIS_MODULE,
4700 .open = spr_wm_latency_open,
4701 .read = seq_read,
4702 .llseek = seq_lseek,
4703 .release = single_release,
4704 .write = spr_wm_latency_write
4705 };
4706
4707 static const struct file_operations i915_cur_wm_latency_fops = {
4708 .owner = THIS_MODULE,
4709 .open = cur_wm_latency_open,
4710 .read = seq_read,
4711 .llseek = seq_lseek,
4712 .release = single_release,
4713 .write = cur_wm_latency_write
4714 };
4715
4716 static int
4717 i915_wedged_get(void *data, u64 *val)
4718 {
4719 struct drm_device *dev = data;
4720 struct drm_i915_private *dev_priv = dev->dev_private;
4721
4722 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
4723
4724 return 0;
4725 }
4726
4727 static int
4728 i915_wedged_set(void *data, u64 val)
4729 {
4730 struct drm_device *dev = data;
4731 struct drm_i915_private *dev_priv = dev->dev_private;
4732
4733 /*
4734 * There is no safeguard against this debugfs entry colliding
4735 * with the hangcheck calling same i915_handle_error() in
4736 * parallel, causing an explosion. For now we assume that the
4737 * test harness is responsible enough not to inject gpu hangs
4738 * while it is writing to 'i915_wedged'
4739 */
4740
4741 if (i915_reset_in_progress(&dev_priv->gpu_error))
4742 return -EAGAIN;
4743
4744 intel_runtime_pm_get(dev_priv);
4745
4746 i915_handle_error(dev, val,
4747 "Manually setting wedged to %llu", val);
4748
4749 intel_runtime_pm_put(dev_priv);
4750
4751 return 0;
4752 }
4753
4754 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4755 i915_wedged_get, i915_wedged_set,
4756 "%llu\n");
4757
4758 static int
4759 i915_ring_stop_get(void *data, u64 *val)
4760 {
4761 struct drm_device *dev = data;
4762 struct drm_i915_private *dev_priv = dev->dev_private;
4763
4764 *val = dev_priv->gpu_error.stop_rings;
4765
4766 return 0;
4767 }
4768
4769 static int
4770 i915_ring_stop_set(void *data, u64 val)
4771 {
4772 struct drm_device *dev = data;
4773 struct drm_i915_private *dev_priv = dev->dev_private;
4774 int ret;
4775
4776 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
4777
4778 ret = mutex_lock_interruptible(&dev->struct_mutex);
4779 if (ret)
4780 return ret;
4781
4782 dev_priv->gpu_error.stop_rings = val;
4783 mutex_unlock(&dev->struct_mutex);
4784
4785 return 0;
4786 }
4787
4788 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4789 i915_ring_stop_get, i915_ring_stop_set,
4790 "0x%08llx\n");
4791
4792 static int
4793 i915_ring_missed_irq_get(void *data, u64 *val)
4794 {
4795 struct drm_device *dev = data;
4796 struct drm_i915_private *dev_priv = dev->dev_private;
4797
4798 *val = dev_priv->gpu_error.missed_irq_rings;
4799 return 0;
4800 }
4801
4802 static int
4803 i915_ring_missed_irq_set(void *data, u64 val)
4804 {
4805 struct drm_device *dev = data;
4806 struct drm_i915_private *dev_priv = dev->dev_private;
4807 int ret;
4808
4809 /* Lock against concurrent debugfs callers */
4810 ret = mutex_lock_interruptible(&dev->struct_mutex);
4811 if (ret)
4812 return ret;
4813 dev_priv->gpu_error.missed_irq_rings = val;
4814 mutex_unlock(&dev->struct_mutex);
4815
4816 return 0;
4817 }
4818
4819 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4820 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4821 "0x%08llx\n");
4822
4823 static int
4824 i915_ring_test_irq_get(void *data, u64 *val)
4825 {
4826 struct drm_device *dev = data;
4827 struct drm_i915_private *dev_priv = dev->dev_private;
4828
4829 *val = dev_priv->gpu_error.test_irq_rings;
4830
4831 return 0;
4832 }
4833
4834 static int
4835 i915_ring_test_irq_set(void *data, u64 val)
4836 {
4837 struct drm_device *dev = data;
4838 struct drm_i915_private *dev_priv = dev->dev_private;
4839 int ret;
4840
4841 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4842
4843 /* Lock against concurrent debugfs callers */
4844 ret = mutex_lock_interruptible(&dev->struct_mutex);
4845 if (ret)
4846 return ret;
4847
4848 dev_priv->gpu_error.test_irq_rings = val;
4849 mutex_unlock(&dev->struct_mutex);
4850
4851 return 0;
4852 }
4853
4854 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4855 i915_ring_test_irq_get, i915_ring_test_irq_set,
4856 "0x%08llx\n");
4857
4858 #define DROP_UNBOUND 0x1
4859 #define DROP_BOUND 0x2
4860 #define DROP_RETIRE 0x4
4861 #define DROP_ACTIVE 0x8
4862 #define DROP_ALL (DROP_UNBOUND | \
4863 DROP_BOUND | \
4864 DROP_RETIRE | \
4865 DROP_ACTIVE)
4866 static int
4867 i915_drop_caches_get(void *data, u64 *val)
4868 {
4869 *val = DROP_ALL;
4870
4871 return 0;
4872 }
4873
4874 static int
4875 i915_drop_caches_set(void *data, u64 val)
4876 {
4877 struct drm_device *dev = data;
4878 struct drm_i915_private *dev_priv = dev->dev_private;
4879 int ret;
4880
4881 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4882
4883 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4884 * on ioctls on -EAGAIN. */
4885 ret = mutex_lock_interruptible(&dev->struct_mutex);
4886 if (ret)
4887 return ret;
4888
4889 if (val & DROP_ACTIVE) {
4890 ret = i915_gpu_idle(dev);
4891 if (ret)
4892 goto unlock;
4893 }
4894
4895 if (val & (DROP_RETIRE | DROP_ACTIVE))
4896 i915_gem_retire_requests(dev);
4897
4898 if (val & DROP_BOUND)
4899 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4900
4901 if (val & DROP_UNBOUND)
4902 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4903
4904 unlock:
4905 mutex_unlock(&dev->struct_mutex);
4906
4907 return ret;
4908 }
4909
4910 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4911 i915_drop_caches_get, i915_drop_caches_set,
4912 "0x%08llx\n");
4913
4914 static int
4915 i915_max_freq_get(void *data, u64 *val)
4916 {
4917 struct drm_device *dev = data;
4918 struct drm_i915_private *dev_priv = dev->dev_private;
4919 int ret;
4920
4921 if (INTEL_INFO(dev)->gen < 6)
4922 return -ENODEV;
4923
4924 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4925
4926 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4927 if (ret)
4928 return ret;
4929
4930 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4931 mutex_unlock(&dev_priv->rps.hw_lock);
4932
4933 return 0;
4934 }
4935
4936 static int
4937 i915_max_freq_set(void *data, u64 val)
4938 {
4939 struct drm_device *dev = data;
4940 struct drm_i915_private *dev_priv = dev->dev_private;
4941 u32 hw_max, hw_min;
4942 int ret;
4943
4944 if (INTEL_INFO(dev)->gen < 6)
4945 return -ENODEV;
4946
4947 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4948
4949 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4950
4951 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4952 if (ret)
4953 return ret;
4954
4955 /*
4956 * Turbo will still be enabled, but won't go above the set value.
4957 */
4958 val = intel_freq_opcode(dev_priv, val);
4959
4960 hw_max = dev_priv->rps.max_freq;
4961 hw_min = dev_priv->rps.min_freq;
4962
4963 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4964 mutex_unlock(&dev_priv->rps.hw_lock);
4965 return -EINVAL;
4966 }
4967
4968 dev_priv->rps.max_freq_softlimit = val;
4969
4970 intel_set_rps(dev, val);
4971
4972 mutex_unlock(&dev_priv->rps.hw_lock);
4973
4974 return 0;
4975 }
4976
4977 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4978 i915_max_freq_get, i915_max_freq_set,
4979 "%llu\n");
4980
4981 static int
4982 i915_min_freq_get(void *data, u64 *val)
4983 {
4984 struct drm_device *dev = data;
4985 struct drm_i915_private *dev_priv = dev->dev_private;
4986 int ret;
4987
4988 if (INTEL_INFO(dev)->gen < 6)
4989 return -ENODEV;
4990
4991 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4992
4993 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4994 if (ret)
4995 return ret;
4996
4997 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4998 mutex_unlock(&dev_priv->rps.hw_lock);
4999
5000 return 0;
5001 }
5002
5003 static int
5004 i915_min_freq_set(void *data, u64 val)
5005 {
5006 struct drm_device *dev = data;
5007 struct drm_i915_private *dev_priv = dev->dev_private;
5008 u32 hw_max, hw_min;
5009 int ret;
5010
5011 if (INTEL_INFO(dev)->gen < 6)
5012 return -ENODEV;
5013
5014 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5015
5016 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
5017
5018 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5019 if (ret)
5020 return ret;
5021
5022 /*
5023 * Turbo will still be enabled, but won't go below the set value.
5024 */
5025 val = intel_freq_opcode(dev_priv, val);
5026
5027 hw_max = dev_priv->rps.max_freq;
5028 hw_min = dev_priv->rps.min_freq;
5029
5030 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
5031 mutex_unlock(&dev_priv->rps.hw_lock);
5032 return -EINVAL;
5033 }
5034
5035 dev_priv->rps.min_freq_softlimit = val;
5036
5037 intel_set_rps(dev, val);
5038
5039 mutex_unlock(&dev_priv->rps.hw_lock);
5040
5041 return 0;
5042 }
5043
5044 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
5045 i915_min_freq_get, i915_min_freq_set,
5046 "%llu\n");
5047
5048 static int
5049 i915_cache_sharing_get(void *data, u64 *val)
5050 {
5051 struct drm_device *dev = data;
5052 struct drm_i915_private *dev_priv = dev->dev_private;
5053 u32 snpcr;
5054 int ret;
5055
5056 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5057 return -ENODEV;
5058
5059 ret = mutex_lock_interruptible(&dev->struct_mutex);
5060 if (ret)
5061 return ret;
5062 intel_runtime_pm_get(dev_priv);
5063
5064 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5065
5066 intel_runtime_pm_put(dev_priv);
5067 mutex_unlock(&dev_priv->dev->struct_mutex);
5068
5069 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
5070
5071 return 0;
5072 }
5073
5074 static int
5075 i915_cache_sharing_set(void *data, u64 val)
5076 {
5077 struct drm_device *dev = data;
5078 struct drm_i915_private *dev_priv = dev->dev_private;
5079 u32 snpcr;
5080
5081 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5082 return -ENODEV;
5083
5084 if (val > 3)
5085 return -EINVAL;
5086
5087 intel_runtime_pm_get(dev_priv);
5088 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
5089
5090 /* Update the cache sharing policy here as well */
5091 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5092 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5093 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5094 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5095
5096 intel_runtime_pm_put(dev_priv);
5097 return 0;
5098 }
5099
5100 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5101 i915_cache_sharing_get, i915_cache_sharing_set,
5102 "%llu\n");
5103
5104 struct sseu_dev_status {
5105 unsigned int slice_total;
5106 unsigned int subslice_total;
5107 unsigned int subslice_per_slice;
5108 unsigned int eu_total;
5109 unsigned int eu_per_subslice;
5110 };
5111
5112 static void cherryview_sseu_device_status(struct drm_device *dev,
5113 struct sseu_dev_status *stat)
5114 {
5115 struct drm_i915_private *dev_priv = dev->dev_private;
5116 int ss_max = 2;
5117 int ss;
5118 u32 sig1[ss_max], sig2[ss_max];
5119
5120 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5121 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5122 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5123 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5124
5125 for (ss = 0; ss < ss_max; ss++) {
5126 unsigned int eu_cnt;
5127
5128 if (sig1[ss] & CHV_SS_PG_ENABLE)
5129 /* skip disabled subslice */
5130 continue;
5131
5132 stat->slice_total = 1;
5133 stat->subslice_per_slice++;
5134 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5135 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5136 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5137 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5138 stat->eu_total += eu_cnt;
5139 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
5140 }
5141 stat->subslice_total = stat->subslice_per_slice;
5142 }
5143
5144 static void gen9_sseu_device_status(struct drm_device *dev,
5145 struct sseu_dev_status *stat)
5146 {
5147 struct drm_i915_private *dev_priv = dev->dev_private;
5148 int s_max = 3, ss_max = 4;
5149 int s, ss;
5150 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5151
5152 /* BXT has a single slice and at most 3 subslices. */
5153 if (IS_BROXTON(dev)) {
5154 s_max = 1;
5155 ss_max = 3;
5156 }
5157
5158 for (s = 0; s < s_max; s++) {
5159 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5160 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5161 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5162 }
5163
5164 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5165 GEN9_PGCTL_SSA_EU19_ACK |
5166 GEN9_PGCTL_SSA_EU210_ACK |
5167 GEN9_PGCTL_SSA_EU311_ACK;
5168 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5169 GEN9_PGCTL_SSB_EU19_ACK |
5170 GEN9_PGCTL_SSB_EU210_ACK |
5171 GEN9_PGCTL_SSB_EU311_ACK;
5172
5173 for (s = 0; s < s_max; s++) {
5174 unsigned int ss_cnt = 0;
5175
5176 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5177 /* skip disabled slice */
5178 continue;
5179
5180 stat->slice_total++;
5181
5182 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
5183 ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
5184
5185 for (ss = 0; ss < ss_max; ss++) {
5186 unsigned int eu_cnt;
5187
5188 if (IS_BROXTON(dev) &&
5189 !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5190 /* skip disabled subslice */
5191 continue;
5192
5193 if (IS_BROXTON(dev))
5194 ss_cnt++;
5195
5196 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5197 eu_mask[ss%2]);
5198 stat->eu_total += eu_cnt;
5199 stat->eu_per_subslice = max(stat->eu_per_subslice,
5200 eu_cnt);
5201 }
5202
5203 stat->subslice_total += ss_cnt;
5204 stat->subslice_per_slice = max(stat->subslice_per_slice,
5205 ss_cnt);
5206 }
5207 }
5208
5209 static void broadwell_sseu_device_status(struct drm_device *dev,
5210 struct sseu_dev_status *stat)
5211 {
5212 struct drm_i915_private *dev_priv = dev->dev_private;
5213 int s;
5214 u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5215
5216 stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK);
5217
5218 if (stat->slice_total) {
5219 stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice;
5220 stat->subslice_total = stat->slice_total *
5221 stat->subslice_per_slice;
5222 stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice;
5223 stat->eu_total = stat->eu_per_subslice * stat->subslice_total;
5224
5225 /* subtract fused off EU(s) from enabled slice(s) */
5226 for (s = 0; s < stat->slice_total; s++) {
5227 u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s];
5228
5229 stat->eu_total -= hweight8(subslice_7eu);
5230 }
5231 }
5232 }
5233
5234 static int i915_sseu_status(struct seq_file *m, void *unused)
5235 {
5236 struct drm_info_node *node = (struct drm_info_node *) m->private;
5237 struct drm_device *dev = node->minor->dev;
5238 struct sseu_dev_status stat;
5239
5240 if (INTEL_INFO(dev)->gen < 8)
5241 return -ENODEV;
5242
5243 seq_puts(m, "SSEU Device Info\n");
5244 seq_printf(m, " Available Slice Total: %u\n",
5245 INTEL_INFO(dev)->slice_total);
5246 seq_printf(m, " Available Subslice Total: %u\n",
5247 INTEL_INFO(dev)->subslice_total);
5248 seq_printf(m, " Available Subslice Per Slice: %u\n",
5249 INTEL_INFO(dev)->subslice_per_slice);
5250 seq_printf(m, " Available EU Total: %u\n",
5251 INTEL_INFO(dev)->eu_total);
5252 seq_printf(m, " Available EU Per Subslice: %u\n",
5253 INTEL_INFO(dev)->eu_per_subslice);
5254 seq_printf(m, " Has Slice Power Gating: %s\n",
5255 yesno(INTEL_INFO(dev)->has_slice_pg));
5256 seq_printf(m, " Has Subslice Power Gating: %s\n",
5257 yesno(INTEL_INFO(dev)->has_subslice_pg));
5258 seq_printf(m, " Has EU Power Gating: %s\n",
5259 yesno(INTEL_INFO(dev)->has_eu_pg));
5260
5261 seq_puts(m, "SSEU Device Status\n");
5262 memset(&stat, 0, sizeof(stat));
5263 if (IS_CHERRYVIEW(dev)) {
5264 cherryview_sseu_device_status(dev, &stat);
5265 } else if (IS_BROADWELL(dev)) {
5266 broadwell_sseu_device_status(dev, &stat);
5267 } else if (INTEL_INFO(dev)->gen >= 9) {
5268 gen9_sseu_device_status(dev, &stat);
5269 }
5270 seq_printf(m, " Enabled Slice Total: %u\n",
5271 stat.slice_total);
5272 seq_printf(m, " Enabled Subslice Total: %u\n",
5273 stat.subslice_total);
5274 seq_printf(m, " Enabled Subslice Per Slice: %u\n",
5275 stat.subslice_per_slice);
5276 seq_printf(m, " Enabled EU Total: %u\n",
5277 stat.eu_total);
5278 seq_printf(m, " Enabled EU Per Subslice: %u\n",
5279 stat.eu_per_subslice);
5280
5281 return 0;
5282 }
5283
5284 static int i915_forcewake_open(struct inode *inode, struct file *file)
5285 {
5286 struct drm_device *dev = inode->i_private;
5287 struct drm_i915_private *dev_priv = dev->dev_private;
5288
5289 if (INTEL_INFO(dev)->gen < 6)
5290 return 0;
5291
5292 intel_runtime_pm_get(dev_priv);
5293 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5294
5295 return 0;
5296 }
5297
5298 static int i915_forcewake_release(struct inode *inode, struct file *file)
5299 {
5300 struct drm_device *dev = inode->i_private;
5301 struct drm_i915_private *dev_priv = dev->dev_private;
5302
5303 if (INTEL_INFO(dev)->gen < 6)
5304 return 0;
5305
5306 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5307 intel_runtime_pm_put(dev_priv);
5308
5309 return 0;
5310 }
5311
5312 static const struct file_operations i915_forcewake_fops = {
5313 .owner = THIS_MODULE,
5314 .open = i915_forcewake_open,
5315 .release = i915_forcewake_release,
5316 };
5317
5318 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5319 {
5320 struct drm_device *dev = minor->dev;
5321 struct dentry *ent;
5322
5323 ent = debugfs_create_file("i915_forcewake_user",
5324 S_IRUSR,
5325 root, dev,
5326 &i915_forcewake_fops);
5327 if (!ent)
5328 return -ENOMEM;
5329
5330 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5331 }
5332
5333 static int i915_debugfs_create(struct dentry *root,
5334 struct drm_minor *minor,
5335 const char *name,
5336 const struct file_operations *fops)
5337 {
5338 struct drm_device *dev = minor->dev;
5339 struct dentry *ent;
5340
5341 ent = debugfs_create_file(name,
5342 S_IRUGO | S_IWUSR,
5343 root, dev,
5344 fops);
5345 if (!ent)
5346 return -ENOMEM;
5347
5348 return drm_add_fake_info_node(minor, ent, fops);
5349 }
5350
5351 static const struct drm_info_list i915_debugfs_list[] = {
5352 {"i915_capabilities", i915_capabilities, 0},
5353 {"i915_gem_objects", i915_gem_object_info, 0},
5354 {"i915_gem_gtt", i915_gem_gtt_info, 0},
5355 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
5356 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
5357 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
5358 {"i915_gem_stolen", i915_gem_stolen_list_info },
5359 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5360 {"i915_gem_request", i915_gem_request_info, 0},
5361 {"i915_gem_seqno", i915_gem_seqno_info, 0},
5362 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5363 {"i915_gem_interrupt", i915_interrupt_info, 0},
5364 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5365 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5366 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5367 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5368 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5369 {"i915_guc_info", i915_guc_info, 0},
5370 {"i915_guc_load_status", i915_guc_load_status_info, 0},
5371 {"i915_guc_log_dump", i915_guc_log_dump, 0},
5372 {"i915_frequency_info", i915_frequency_info, 0},
5373 {"i915_hangcheck_info", i915_hangcheck_info, 0},
5374 {"i915_drpc_info", i915_drpc_info, 0},
5375 {"i915_emon_status", i915_emon_status, 0},
5376 {"i915_ring_freq_table", i915_ring_freq_table, 0},
5377 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5378 {"i915_fbc_status", i915_fbc_status, 0},
5379 {"i915_ips_status", i915_ips_status, 0},
5380 {"i915_sr_status", i915_sr_status, 0},
5381 {"i915_opregion", i915_opregion, 0},
5382 {"i915_vbt", i915_vbt, 0},
5383 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5384 {"i915_context_status", i915_context_status, 0},
5385 {"i915_dump_lrc", i915_dump_lrc, 0},
5386 {"i915_execlists", i915_execlists, 0},
5387 {"i915_forcewake_domains", i915_forcewake_domains, 0},
5388 {"i915_swizzle_info", i915_swizzle_info, 0},
5389 {"i915_ppgtt_info", i915_ppgtt_info, 0},
5390 {"i915_llc", i915_llc, 0},
5391 {"i915_edp_psr_status", i915_edp_psr_status, 0},
5392 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5393 {"i915_energy_uJ", i915_energy_uJ, 0},
5394 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5395 {"i915_power_domain_info", i915_power_domain_info, 0},
5396 {"i915_dmc_info", i915_dmc_info, 0},
5397 {"i915_display_info", i915_display_info, 0},
5398 {"i915_semaphore_status", i915_semaphore_status, 0},
5399 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5400 {"i915_dp_mst_info", i915_dp_mst_info, 0},
5401 {"i915_wa_registers", i915_wa_registers, 0},
5402 {"i915_ddb_info", i915_ddb_info, 0},
5403 {"i915_sseu_status", i915_sseu_status, 0},
5404 {"i915_drrs_status", i915_drrs_status, 0},
5405 {"i915_rps_boost_info", i915_rps_boost_info, 0},
5406 };
5407 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5408
5409 static const struct i915_debugfs_files {
5410 const char *name;
5411 const struct file_operations *fops;
5412 } i915_debugfs_files[] = {
5413 {"i915_wedged", &i915_wedged_fops},
5414 {"i915_max_freq", &i915_max_freq_fops},
5415 {"i915_min_freq", &i915_min_freq_fops},
5416 {"i915_cache_sharing", &i915_cache_sharing_fops},
5417 {"i915_ring_stop", &i915_ring_stop_fops},
5418 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5419 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5420 {"i915_gem_drop_caches", &i915_drop_caches_fops},
5421 {"i915_error_state", &i915_error_state_fops},
5422 {"i915_next_seqno", &i915_next_seqno_fops},
5423 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5424 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5425 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5426 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5427 {"i915_fbc_false_color", &i915_fbc_fc_fops},
5428 {"i915_dp_test_data", &i915_displayport_test_data_fops},
5429 {"i915_dp_test_type", &i915_displayport_test_type_fops},
5430 {"i915_dp_test_active", &i915_displayport_test_active_fops}
5431 };
5432
5433 void intel_display_crc_init(struct drm_device *dev)
5434 {
5435 struct drm_i915_private *dev_priv = dev->dev_private;
5436 enum pipe pipe;
5437
5438 for_each_pipe(dev_priv, pipe) {
5439 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5440
5441 pipe_crc->opened = false;
5442 spin_lock_init(&pipe_crc->lock);
5443 init_waitqueue_head(&pipe_crc->wq);
5444 }
5445 }
5446
5447 int i915_debugfs_init(struct drm_minor *minor)
5448 {
5449 int ret, i;
5450
5451 ret = i915_forcewake_create(minor->debugfs_root, minor);
5452 if (ret)
5453 return ret;
5454
5455 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5456 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5457 if (ret)
5458 return ret;
5459 }
5460
5461 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5462 ret = i915_debugfs_create(minor->debugfs_root, minor,
5463 i915_debugfs_files[i].name,
5464 i915_debugfs_files[i].fops);
5465 if (ret)
5466 return ret;
5467 }
5468
5469 return drm_debugfs_create_files(i915_debugfs_list,
5470 I915_DEBUGFS_ENTRIES,
5471 minor->debugfs_root, minor);
5472 }
5473
5474 void i915_debugfs_cleanup(struct drm_minor *minor)
5475 {
5476 int i;
5477
5478 drm_debugfs_remove_files(i915_debugfs_list,
5479 I915_DEBUGFS_ENTRIES, minor);
5480
5481 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5482 1, minor);
5483
5484 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5485 struct drm_info_list *info_list =
5486 (struct drm_info_list *)&i915_pipe_crc_data[i];
5487
5488 drm_debugfs_remove_files(info_list, 1, minor);
5489 }
5490
5491 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5492 struct drm_info_list *info_list =
5493 (struct drm_info_list *) i915_debugfs_files[i].fops;
5494
5495 drm_debugfs_remove_files(info_list, 1, minor);
5496 }
5497 }
5498
5499 struct dpcd_block {
5500 /* DPCD dump start address. */
5501 unsigned int offset;
5502 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5503 unsigned int end;
5504 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5505 size_t size;
5506 /* Only valid for eDP. */
5507 bool edp;
5508 };
5509
5510 static const struct dpcd_block i915_dpcd_debug[] = {
5511 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5512 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5513 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5514 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5515 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5516 { .offset = DP_SET_POWER },
5517 { .offset = DP_EDP_DPCD_REV },
5518 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5519 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5520 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5521 };
5522
5523 static int i915_dpcd_show(struct seq_file *m, void *data)
5524 {
5525 struct drm_connector *connector = m->private;
5526 struct intel_dp *intel_dp =
5527 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5528 uint8_t buf[16];
5529 ssize_t err;
5530 int i;
5531
5532 if (connector->status != connector_status_connected)
5533 return -ENODEV;
5534
5535 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5536 const struct dpcd_block *b = &i915_dpcd_debug[i];
5537 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5538
5539 if (b->edp &&
5540 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5541 continue;
5542
5543 /* low tech for now */
5544 if (WARN_ON(size > sizeof(buf)))
5545 continue;
5546
5547 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5548 if (err <= 0) {
5549 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5550 size, b->offset, err);
5551 continue;
5552 }
5553
5554 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5555 }
5556
5557 return 0;
5558 }
5559
5560 static int i915_dpcd_open(struct inode *inode, struct file *file)
5561 {
5562 return single_open(file, i915_dpcd_show, inode->i_private);
5563 }
5564
5565 static const struct file_operations i915_dpcd_fops = {
5566 .owner = THIS_MODULE,
5567 .open = i915_dpcd_open,
5568 .read = seq_read,
5569 .llseek = seq_lseek,
5570 .release = single_release,
5571 };
5572
5573 /**
5574 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5575 * @connector: pointer to a registered drm_connector
5576 *
5577 * Cleanup will be done by drm_connector_unregister() through a call to
5578 * drm_debugfs_connector_remove().
5579 *
5580 * Returns 0 on success, negative error codes on error.
5581 */
5582 int i915_debugfs_connector_add(struct drm_connector *connector)
5583 {
5584 struct dentry *root = connector->debugfs_entry;
5585
5586 /* The connector must have been registered beforehands. */
5587 if (!root)
5588 return -ENODEV;
5589
5590 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5591 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5592 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5593 &i915_dpcd_fops);
5594
5595 return 0;
5596 }
Linux kernel - Deliverables
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