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drm/i915: Disable waitboosting for mmioflips/semaphores
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
37 #include <drm/drmP.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
41 #include "i915_drv.h"
42
43 enum {
44 ACTIVE_LIST,
45 INACTIVE_LIST,
46 PINNED_LIST,
47 };
48
49 /* As the drm_debugfs_init() routines are called before dev->dev_private is
50 * allocated we need to hook into the minor for release. */
51 static int
52 drm_add_fake_info_node(struct drm_minor *minor,
53 struct dentry *ent,
54 const void *key)
55 {
56 struct drm_info_node *node;
57
58 node = kmalloc(sizeof(*node), GFP_KERNEL);
59 if (node == NULL) {
60 debugfs_remove(ent);
61 return -ENOMEM;
62 }
63
64 node->minor = minor;
65 node->dent = ent;
66 node->info_ent = (void *) key;
67
68 mutex_lock(&minor->debugfs_lock);
69 list_add(&node->list, &minor->debugfs_list);
70 mutex_unlock(&minor->debugfs_lock);
71
72 return 0;
73 }
74
75 static int i915_capabilities(struct seq_file *m, void *data)
76 {
77 struct drm_info_node *node = m->private;
78 struct drm_device *dev = node->minor->dev;
79 const struct intel_device_info *info = INTEL_INFO(dev);
80
81 seq_printf(m, "gen: %d\n", info->gen);
82 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
83 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
84 #define SEP_SEMICOLON ;
85 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
86 #undef PRINT_FLAG
87 #undef SEP_SEMICOLON
88
89 return 0;
90 }
91
92 static char get_active_flag(struct drm_i915_gem_object *obj)
93 {
94 return obj->active ? '*' : ' ';
95 }
96
97 static char get_pin_flag(struct drm_i915_gem_object *obj)
98 {
99 return obj->pin_display ? 'p' : ' ';
100 }
101
102 static char get_tiling_flag(struct drm_i915_gem_object *obj)
103 {
104 switch (obj->tiling_mode) {
105 default:
106 case I915_TILING_NONE: return ' ';
107 case I915_TILING_X: return 'X';
108 case I915_TILING_Y: return 'Y';
109 }
110 }
111
112 static char get_global_flag(struct drm_i915_gem_object *obj)
113 {
114 return i915_gem_obj_to_ggtt(obj) ? 'g' : ' ';
115 }
116
117 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
118 {
119 return obj->mapping ? 'M' : ' ';
120 }
121
122 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
123 {
124 u64 size = 0;
125 struct i915_vma *vma;
126
127 list_for_each_entry(vma, &obj->vma_list, obj_link) {
128 if (vma->is_ggtt && drm_mm_node_allocated(&vma->node))
129 size += vma->node.size;
130 }
131
132 return size;
133 }
134
135 static void
136 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
137 {
138 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
139 struct intel_engine_cs *engine;
140 struct i915_vma *vma;
141 int pin_count = 0;
142 enum intel_engine_id id;
143
144 lockdep_assert_held(&obj->base.dev->struct_mutex);
145
146 seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ",
147 &obj->base,
148 get_active_flag(obj),
149 get_pin_flag(obj),
150 get_tiling_flag(obj),
151 get_global_flag(obj),
152 get_pin_mapped_flag(obj),
153 obj->base.size / 1024,
154 obj->base.read_domains,
155 obj->base.write_domain);
156 for_each_engine_id(engine, dev_priv, id)
157 seq_printf(m, "%x ",
158 i915_gem_request_get_seqno(obj->last_read_req[id]));
159 seq_printf(m, "] %x %x%s%s%s",
160 i915_gem_request_get_seqno(obj->last_write_req),
161 i915_gem_request_get_seqno(obj->last_fenced_req),
162 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
163 obj->dirty ? " dirty" : "",
164 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
165 if (obj->base.name)
166 seq_printf(m, " (name: %d)", obj->base.name);
167 list_for_each_entry(vma, &obj->vma_list, obj_link) {
168 if (vma->pin_count > 0)
169 pin_count++;
170 }
171 seq_printf(m, " (pinned x %d)", pin_count);
172 if (obj->pin_display)
173 seq_printf(m, " (display)");
174 if (obj->fence_reg != I915_FENCE_REG_NONE)
175 seq_printf(m, " (fence: %d)", obj->fence_reg);
176 list_for_each_entry(vma, &obj->vma_list, obj_link) {
177 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
178 vma->is_ggtt ? "g" : "pp",
179 vma->node.start, vma->node.size);
180 if (vma->is_ggtt)
181 seq_printf(m, ", type: %u", vma->ggtt_view.type);
182 seq_puts(m, ")");
183 }
184 if (obj->stolen)
185 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
186 if (obj->pin_display || obj->fault_mappable) {
187 char s[3], *t = s;
188 if (obj->pin_display)
189 *t++ = 'p';
190 if (obj->fault_mappable)
191 *t++ = 'f';
192 *t = '\0';
193 seq_printf(m, " (%s mappable)", s);
194 }
195 if (obj->last_write_req != NULL)
196 seq_printf(m, " (%s)",
197 i915_gem_request_get_engine(obj->last_write_req)->name);
198 if (obj->frontbuffer_bits)
199 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
200 }
201
202 static int i915_gem_object_list_info(struct seq_file *m, void *data)
203 {
204 struct drm_info_node *node = m->private;
205 uintptr_t list = (uintptr_t) node->info_ent->data;
206 struct list_head *head;
207 struct drm_device *dev = node->minor->dev;
208 struct drm_i915_private *dev_priv = to_i915(dev);
209 struct i915_ggtt *ggtt = &dev_priv->ggtt;
210 struct i915_vma *vma;
211 u64 total_obj_size, total_gtt_size;
212 int count, ret;
213
214 ret = mutex_lock_interruptible(&dev->struct_mutex);
215 if (ret)
216 return ret;
217
218 /* FIXME: the user of this interface might want more than just GGTT */
219 switch (list) {
220 case ACTIVE_LIST:
221 seq_puts(m, "Active:\n");
222 head = &ggtt->base.active_list;
223 break;
224 case INACTIVE_LIST:
225 seq_puts(m, "Inactive:\n");
226 head = &ggtt->base.inactive_list;
227 break;
228 default:
229 mutex_unlock(&dev->struct_mutex);
230 return -EINVAL;
231 }
232
233 total_obj_size = total_gtt_size = count = 0;
234 list_for_each_entry(vma, head, vm_link) {
235 seq_printf(m, " ");
236 describe_obj(m, vma->obj);
237 seq_printf(m, "\n");
238 total_obj_size += vma->obj->base.size;
239 total_gtt_size += vma->node.size;
240 count++;
241 }
242 mutex_unlock(&dev->struct_mutex);
243
244 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
245 count, total_obj_size, total_gtt_size);
246 return 0;
247 }
248
249 static int obj_rank_by_stolen(void *priv,
250 struct list_head *A, struct list_head *B)
251 {
252 struct drm_i915_gem_object *a =
253 container_of(A, struct drm_i915_gem_object, obj_exec_link);
254 struct drm_i915_gem_object *b =
255 container_of(B, struct drm_i915_gem_object, obj_exec_link);
256
257 if (a->stolen->start < b->stolen->start)
258 return -1;
259 if (a->stolen->start > b->stolen->start)
260 return 1;
261 return 0;
262 }
263
264 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
265 {
266 struct drm_info_node *node = m->private;
267 struct drm_device *dev = node->minor->dev;
268 struct drm_i915_private *dev_priv = to_i915(dev);
269 struct drm_i915_gem_object *obj;
270 u64 total_obj_size, total_gtt_size;
271 LIST_HEAD(stolen);
272 int count, ret;
273
274 ret = mutex_lock_interruptible(&dev->struct_mutex);
275 if (ret)
276 return ret;
277
278 total_obj_size = total_gtt_size = count = 0;
279 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
280 if (obj->stolen == NULL)
281 continue;
282
283 list_add(&obj->obj_exec_link, &stolen);
284
285 total_obj_size += obj->base.size;
286 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
287 count++;
288 }
289 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
290 if (obj->stolen == NULL)
291 continue;
292
293 list_add(&obj->obj_exec_link, &stolen);
294
295 total_obj_size += obj->base.size;
296 count++;
297 }
298 list_sort(NULL, &stolen, obj_rank_by_stolen);
299 seq_puts(m, "Stolen:\n");
300 while (!list_empty(&stolen)) {
301 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
302 seq_puts(m, " ");
303 describe_obj(m, obj);
304 seq_putc(m, '\n');
305 list_del_init(&obj->obj_exec_link);
306 }
307 mutex_unlock(&dev->struct_mutex);
308
309 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
310 count, total_obj_size, total_gtt_size);
311 return 0;
312 }
313
314 #define count_objects(list, member) do { \
315 list_for_each_entry(obj, list, member) { \
316 size += i915_gem_obj_total_ggtt_size(obj); \
317 ++count; \
318 if (obj->map_and_fenceable) { \
319 mappable_size += i915_gem_obj_ggtt_size(obj); \
320 ++mappable_count; \
321 } \
322 } \
323 } while (0)
324
325 struct file_stats {
326 struct drm_i915_file_private *file_priv;
327 unsigned long count;
328 u64 total, unbound;
329 u64 global, shared;
330 u64 active, inactive;
331 };
332
333 static int per_file_stats(int id, void *ptr, void *data)
334 {
335 struct drm_i915_gem_object *obj = ptr;
336 struct file_stats *stats = data;
337 struct i915_vma *vma;
338
339 stats->count++;
340 stats->total += obj->base.size;
341
342 if (obj->base.name || obj->base.dma_buf)
343 stats->shared += obj->base.size;
344
345 if (USES_FULL_PPGTT(obj->base.dev)) {
346 list_for_each_entry(vma, &obj->vma_list, obj_link) {
347 struct i915_hw_ppgtt *ppgtt;
348
349 if (!drm_mm_node_allocated(&vma->node))
350 continue;
351
352 if (vma->is_ggtt) {
353 stats->global += obj->base.size;
354 continue;
355 }
356
357 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
358 if (ppgtt->file_priv != stats->file_priv)
359 continue;
360
361 if (obj->active) /* XXX per-vma statistic */
362 stats->active += obj->base.size;
363 else
364 stats->inactive += obj->base.size;
365
366 return 0;
367 }
368 } else {
369 if (i915_gem_obj_ggtt_bound(obj)) {
370 stats->global += obj->base.size;
371 if (obj->active)
372 stats->active += obj->base.size;
373 else
374 stats->inactive += obj->base.size;
375 return 0;
376 }
377 }
378
379 if (!list_empty(&obj->global_list))
380 stats->unbound += obj->base.size;
381
382 return 0;
383 }
384
385 #define print_file_stats(m, name, stats) do { \
386 if (stats.count) \
387 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
388 name, \
389 stats.count, \
390 stats.total, \
391 stats.active, \
392 stats.inactive, \
393 stats.global, \
394 stats.shared, \
395 stats.unbound); \
396 } while (0)
397
398 static void print_batch_pool_stats(struct seq_file *m,
399 struct drm_i915_private *dev_priv)
400 {
401 struct drm_i915_gem_object *obj;
402 struct file_stats stats;
403 struct intel_engine_cs *engine;
404 int j;
405
406 memset(&stats, 0, sizeof(stats));
407
408 for_each_engine(engine, dev_priv) {
409 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
410 list_for_each_entry(obj,
411 &engine->batch_pool.cache_list[j],
412 batch_pool_link)
413 per_file_stats(0, obj, &stats);
414 }
415 }
416
417 print_file_stats(m, "[k]batch pool", stats);
418 }
419
420 static int per_file_ctx_stats(int id, void *ptr, void *data)
421 {
422 struct i915_gem_context *ctx = ptr;
423 int n;
424
425 for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
426 if (ctx->engine[n].state)
427 per_file_stats(0, ctx->engine[n].state, data);
428 if (ctx->engine[n].ringbuf)
429 per_file_stats(0, ctx->engine[n].ringbuf->obj, data);
430 }
431
432 return 0;
433 }
434
435 static void print_context_stats(struct seq_file *m,
436 struct drm_i915_private *dev_priv)
437 {
438 struct file_stats stats;
439 struct drm_file *file;
440
441 memset(&stats, 0, sizeof(stats));
442
443 mutex_lock(&dev_priv->drm.struct_mutex);
444 if (dev_priv->kernel_context)
445 per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
446
447 list_for_each_entry(file, &dev_priv->drm.filelist, lhead) {
448 struct drm_i915_file_private *fpriv = file->driver_priv;
449 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
450 }
451 mutex_unlock(&dev_priv->drm.struct_mutex);
452
453 print_file_stats(m, "[k]contexts", stats);
454 }
455
456 #define count_vmas(list, member) do { \
457 list_for_each_entry(vma, list, member) { \
458 size += i915_gem_obj_total_ggtt_size(vma->obj); \
459 ++count; \
460 if (vma->obj->map_and_fenceable) { \
461 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
462 ++mappable_count; \
463 } \
464 } \
465 } while (0)
466
467 static int i915_gem_object_info(struct seq_file *m, void* data)
468 {
469 struct drm_info_node *node = m->private;
470 struct drm_device *dev = node->minor->dev;
471 struct drm_i915_private *dev_priv = to_i915(dev);
472 struct i915_ggtt *ggtt = &dev_priv->ggtt;
473 u32 count, mappable_count, purgeable_count;
474 u64 size, mappable_size, purgeable_size;
475 unsigned long pin_mapped_count = 0, pin_mapped_purgeable_count = 0;
476 u64 pin_mapped_size = 0, pin_mapped_purgeable_size = 0;
477 struct drm_i915_gem_object *obj;
478 struct drm_file *file;
479 struct i915_vma *vma;
480 int ret;
481
482 ret = mutex_lock_interruptible(&dev->struct_mutex);
483 if (ret)
484 return ret;
485
486 seq_printf(m, "%u objects, %zu bytes\n",
487 dev_priv->mm.object_count,
488 dev_priv->mm.object_memory);
489
490 size = count = mappable_size = mappable_count = 0;
491 count_objects(&dev_priv->mm.bound_list, global_list);
492 seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
493 count, mappable_count, size, mappable_size);
494
495 size = count = mappable_size = mappable_count = 0;
496 count_vmas(&ggtt->base.active_list, vm_link);
497 seq_printf(m, " %u [%u] active objects, %llu [%llu] bytes\n",
498 count, mappable_count, size, mappable_size);
499
500 size = count = mappable_size = mappable_count = 0;
501 count_vmas(&ggtt->base.inactive_list, vm_link);
502 seq_printf(m, " %u [%u] inactive objects, %llu [%llu] bytes\n",
503 count, mappable_count, size, mappable_size);
504
505 size = count = purgeable_size = purgeable_count = 0;
506 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
507 size += obj->base.size, ++count;
508 if (obj->madv == I915_MADV_DONTNEED)
509 purgeable_size += obj->base.size, ++purgeable_count;
510 if (obj->mapping) {
511 pin_mapped_count++;
512 pin_mapped_size += obj->base.size;
513 if (obj->pages_pin_count == 0) {
514 pin_mapped_purgeable_count++;
515 pin_mapped_purgeable_size += obj->base.size;
516 }
517 }
518 }
519 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
520
521 size = count = mappable_size = mappable_count = 0;
522 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
523 if (obj->fault_mappable) {
524 size += i915_gem_obj_ggtt_size(obj);
525 ++count;
526 }
527 if (obj->pin_display) {
528 mappable_size += i915_gem_obj_ggtt_size(obj);
529 ++mappable_count;
530 }
531 if (obj->madv == I915_MADV_DONTNEED) {
532 purgeable_size += obj->base.size;
533 ++purgeable_count;
534 }
535 if (obj->mapping) {
536 pin_mapped_count++;
537 pin_mapped_size += obj->base.size;
538 if (obj->pages_pin_count == 0) {
539 pin_mapped_purgeable_count++;
540 pin_mapped_purgeable_size += obj->base.size;
541 }
542 }
543 }
544 seq_printf(m, "%u purgeable objects, %llu bytes\n",
545 purgeable_count, purgeable_size);
546 seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
547 mappable_count, mappable_size);
548 seq_printf(m, "%u fault mappable objects, %llu bytes\n",
549 count, size);
550 seq_printf(m,
551 "%lu [%lu] pin mapped objects, %llu [%llu] bytes [purgeable]\n",
552 pin_mapped_count, pin_mapped_purgeable_count,
553 pin_mapped_size, pin_mapped_purgeable_size);
554
555 seq_printf(m, "%llu [%llu] gtt total\n",
556 ggtt->base.total, ggtt->mappable_end - ggtt->base.start);
557
558 seq_putc(m, '\n');
559 print_batch_pool_stats(m, dev_priv);
560 mutex_unlock(&dev->struct_mutex);
561
562 mutex_lock(&dev->filelist_mutex);
563 print_context_stats(m, dev_priv);
564 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
565 struct file_stats stats;
566 struct task_struct *task;
567
568 memset(&stats, 0, sizeof(stats));
569 stats.file_priv = file->driver_priv;
570 spin_lock(&file->table_lock);
571 idr_for_each(&file->object_idr, per_file_stats, &stats);
572 spin_unlock(&file->table_lock);
573 /*
574 * Although we have a valid reference on file->pid, that does
575 * not guarantee that the task_struct who called get_pid() is
576 * still alive (e.g. get_pid(current) => fork() => exit()).
577 * Therefore, we need to protect this ->comm access using RCU.
578 */
579 rcu_read_lock();
580 task = pid_task(file->pid, PIDTYPE_PID);
581 print_file_stats(m, task ? task->comm : "<unknown>", stats);
582 rcu_read_unlock();
583 }
584 mutex_unlock(&dev->filelist_mutex);
585
586 return 0;
587 }
588
589 static int i915_gem_gtt_info(struct seq_file *m, void *data)
590 {
591 struct drm_info_node *node = m->private;
592 struct drm_device *dev = node->minor->dev;
593 uintptr_t list = (uintptr_t) node->info_ent->data;
594 struct drm_i915_private *dev_priv = to_i915(dev);
595 struct drm_i915_gem_object *obj;
596 u64 total_obj_size, total_gtt_size;
597 int count, ret;
598
599 ret = mutex_lock_interruptible(&dev->struct_mutex);
600 if (ret)
601 return ret;
602
603 total_obj_size = total_gtt_size = count = 0;
604 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
605 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
606 continue;
607
608 seq_puts(m, " ");
609 describe_obj(m, obj);
610 seq_putc(m, '\n');
611 total_obj_size += obj->base.size;
612 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
613 count++;
614 }
615
616 mutex_unlock(&dev->struct_mutex);
617
618 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
619 count, total_obj_size, total_gtt_size);
620
621 return 0;
622 }
623
624 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
625 {
626 struct drm_info_node *node = m->private;
627 struct drm_device *dev = node->minor->dev;
628 struct drm_i915_private *dev_priv = to_i915(dev);
629 struct intel_crtc *crtc;
630 int ret;
631
632 ret = mutex_lock_interruptible(&dev->struct_mutex);
633 if (ret)
634 return ret;
635
636 for_each_intel_crtc(dev, crtc) {
637 const char pipe = pipe_name(crtc->pipe);
638 const char plane = plane_name(crtc->plane);
639 struct intel_flip_work *work;
640
641 spin_lock_irq(&dev->event_lock);
642 work = crtc->flip_work;
643 if (work == NULL) {
644 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
645 pipe, plane);
646 } else {
647 u32 pending;
648 u32 addr;
649
650 pending = atomic_read(&work->pending);
651 if (pending) {
652 seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n",
653 pipe, plane);
654 } else {
655 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
656 pipe, plane);
657 }
658 if (work->flip_queued_req) {
659 struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req);
660
661 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
662 engine->name,
663 i915_gem_request_get_seqno(work->flip_queued_req),
664 dev_priv->next_seqno,
665 intel_engine_get_seqno(engine),
666 i915_gem_request_completed(work->flip_queued_req));
667 } else
668 seq_printf(m, "Flip not associated with any ring\n");
669 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
670 work->flip_queued_vblank,
671 work->flip_ready_vblank,
672 intel_crtc_get_vblank_counter(crtc));
673 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
674
675 if (INTEL_INFO(dev)->gen >= 4)
676 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
677 else
678 addr = I915_READ(DSPADDR(crtc->plane));
679 seq_printf(m, "Current scanout address 0x%08x\n", addr);
680
681 if (work->pending_flip_obj) {
682 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
683 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
684 }
685 }
686 spin_unlock_irq(&dev->event_lock);
687 }
688
689 mutex_unlock(&dev->struct_mutex);
690
691 return 0;
692 }
693
694 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
695 {
696 struct drm_info_node *node = m->private;
697 struct drm_device *dev = node->minor->dev;
698 struct drm_i915_private *dev_priv = to_i915(dev);
699 struct drm_i915_gem_object *obj;
700 struct intel_engine_cs *engine;
701 int total = 0;
702 int ret, j;
703
704 ret = mutex_lock_interruptible(&dev->struct_mutex);
705 if (ret)
706 return ret;
707
708 for_each_engine(engine, dev_priv) {
709 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
710 int count;
711
712 count = 0;
713 list_for_each_entry(obj,
714 &engine->batch_pool.cache_list[j],
715 batch_pool_link)
716 count++;
717 seq_printf(m, "%s cache[%d]: %d objects\n",
718 engine->name, j, count);
719
720 list_for_each_entry(obj,
721 &engine->batch_pool.cache_list[j],
722 batch_pool_link) {
723 seq_puts(m, " ");
724 describe_obj(m, obj);
725 seq_putc(m, '\n');
726 }
727
728 total += count;
729 }
730 }
731
732 seq_printf(m, "total: %d\n", total);
733
734 mutex_unlock(&dev->struct_mutex);
735
736 return 0;
737 }
738
739 static int i915_gem_request_info(struct seq_file *m, void *data)
740 {
741 struct drm_info_node *node = m->private;
742 struct drm_device *dev = node->minor->dev;
743 struct drm_i915_private *dev_priv = to_i915(dev);
744 struct intel_engine_cs *engine;
745 struct drm_i915_gem_request *req;
746 int ret, any;
747
748 ret = mutex_lock_interruptible(&dev->struct_mutex);
749 if (ret)
750 return ret;
751
752 any = 0;
753 for_each_engine(engine, dev_priv) {
754 int count;
755
756 count = 0;
757 list_for_each_entry(req, &engine->request_list, list)
758 count++;
759 if (count == 0)
760 continue;
761
762 seq_printf(m, "%s requests: %d\n", engine->name, count);
763 list_for_each_entry(req, &engine->request_list, list) {
764 struct task_struct *task;
765
766 rcu_read_lock();
767 task = NULL;
768 if (req->pid)
769 task = pid_task(req->pid, PIDTYPE_PID);
770 seq_printf(m, " %x @ %d: %s [%d]\n",
771 req->fence.seqno,
772 (int) (jiffies - req->emitted_jiffies),
773 task ? task->comm : "<unknown>",
774 task ? task->pid : -1);
775 rcu_read_unlock();
776 }
777
778 any++;
779 }
780 mutex_unlock(&dev->struct_mutex);
781
782 if (any == 0)
783 seq_puts(m, "No requests\n");
784
785 return 0;
786 }
787
788 static void i915_ring_seqno_info(struct seq_file *m,
789 struct intel_engine_cs *engine)
790 {
791 struct intel_breadcrumbs *b = &engine->breadcrumbs;
792 struct rb_node *rb;
793
794 seq_printf(m, "Current sequence (%s): %x\n",
795 engine->name, intel_engine_get_seqno(engine));
796 seq_printf(m, "Current user interrupts (%s): %lx\n",
797 engine->name, READ_ONCE(engine->breadcrumbs.irq_wakeups));
798
799 spin_lock(&b->lock);
800 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
801 struct intel_wait *w = container_of(rb, typeof(*w), node);
802
803 seq_printf(m, "Waiting (%s): %s [%d] on %x\n",
804 engine->name, w->tsk->comm, w->tsk->pid, w->seqno);
805 }
806 spin_unlock(&b->lock);
807 }
808
809 static int i915_gem_seqno_info(struct seq_file *m, void *data)
810 {
811 struct drm_info_node *node = m->private;
812 struct drm_device *dev = node->minor->dev;
813 struct drm_i915_private *dev_priv = to_i915(dev);
814 struct intel_engine_cs *engine;
815 int ret;
816
817 ret = mutex_lock_interruptible(&dev->struct_mutex);
818 if (ret)
819 return ret;
820 intel_runtime_pm_get(dev_priv);
821
822 for_each_engine(engine, dev_priv)
823 i915_ring_seqno_info(m, engine);
824
825 intel_runtime_pm_put(dev_priv);
826 mutex_unlock(&dev->struct_mutex);
827
828 return 0;
829 }
830
831
832 static int i915_interrupt_info(struct seq_file *m, void *data)
833 {
834 struct drm_info_node *node = m->private;
835 struct drm_device *dev = node->minor->dev;
836 struct drm_i915_private *dev_priv = to_i915(dev);
837 struct intel_engine_cs *engine;
838 int ret, i, pipe;
839
840 ret = mutex_lock_interruptible(&dev->struct_mutex);
841 if (ret)
842 return ret;
843 intel_runtime_pm_get(dev_priv);
844
845 if (IS_CHERRYVIEW(dev)) {
846 seq_printf(m, "Master Interrupt Control:\t%08x\n",
847 I915_READ(GEN8_MASTER_IRQ));
848
849 seq_printf(m, "Display IER:\t%08x\n",
850 I915_READ(VLV_IER));
851 seq_printf(m, "Display IIR:\t%08x\n",
852 I915_READ(VLV_IIR));
853 seq_printf(m, "Display IIR_RW:\t%08x\n",
854 I915_READ(VLV_IIR_RW));
855 seq_printf(m, "Display IMR:\t%08x\n",
856 I915_READ(VLV_IMR));
857 for_each_pipe(dev_priv, pipe)
858 seq_printf(m, "Pipe %c stat:\t%08x\n",
859 pipe_name(pipe),
860 I915_READ(PIPESTAT(pipe)));
861
862 seq_printf(m, "Port hotplug:\t%08x\n",
863 I915_READ(PORT_HOTPLUG_EN));
864 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
865 I915_READ(VLV_DPFLIPSTAT));
866 seq_printf(m, "DPINVGTT:\t%08x\n",
867 I915_READ(DPINVGTT));
868
869 for (i = 0; i < 4; i++) {
870 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
871 i, I915_READ(GEN8_GT_IMR(i)));
872 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
873 i, I915_READ(GEN8_GT_IIR(i)));
874 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
875 i, I915_READ(GEN8_GT_IER(i)));
876 }
877
878 seq_printf(m, "PCU interrupt mask:\t%08x\n",
879 I915_READ(GEN8_PCU_IMR));
880 seq_printf(m, "PCU interrupt identity:\t%08x\n",
881 I915_READ(GEN8_PCU_IIR));
882 seq_printf(m, "PCU interrupt enable:\t%08x\n",
883 I915_READ(GEN8_PCU_IER));
884 } else if (INTEL_INFO(dev)->gen >= 8) {
885 seq_printf(m, "Master Interrupt Control:\t%08x\n",
886 I915_READ(GEN8_MASTER_IRQ));
887
888 for (i = 0; i < 4; i++) {
889 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
890 i, I915_READ(GEN8_GT_IMR(i)));
891 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
892 i, I915_READ(GEN8_GT_IIR(i)));
893 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
894 i, I915_READ(GEN8_GT_IER(i)));
895 }
896
897 for_each_pipe(dev_priv, pipe) {
898 enum intel_display_power_domain power_domain;
899
900 power_domain = POWER_DOMAIN_PIPE(pipe);
901 if (!intel_display_power_get_if_enabled(dev_priv,
902 power_domain)) {
903 seq_printf(m, "Pipe %c power disabled\n",
904 pipe_name(pipe));
905 continue;
906 }
907 seq_printf(m, "Pipe %c IMR:\t%08x\n",
908 pipe_name(pipe),
909 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
910 seq_printf(m, "Pipe %c IIR:\t%08x\n",
911 pipe_name(pipe),
912 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
913 seq_printf(m, "Pipe %c IER:\t%08x\n",
914 pipe_name(pipe),
915 I915_READ(GEN8_DE_PIPE_IER(pipe)));
916
917 intel_display_power_put(dev_priv, power_domain);
918 }
919
920 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
921 I915_READ(GEN8_DE_PORT_IMR));
922 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
923 I915_READ(GEN8_DE_PORT_IIR));
924 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
925 I915_READ(GEN8_DE_PORT_IER));
926
927 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
928 I915_READ(GEN8_DE_MISC_IMR));
929 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
930 I915_READ(GEN8_DE_MISC_IIR));
931 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
932 I915_READ(GEN8_DE_MISC_IER));
933
934 seq_printf(m, "PCU interrupt mask:\t%08x\n",
935 I915_READ(GEN8_PCU_IMR));
936 seq_printf(m, "PCU interrupt identity:\t%08x\n",
937 I915_READ(GEN8_PCU_IIR));
938 seq_printf(m, "PCU interrupt enable:\t%08x\n",
939 I915_READ(GEN8_PCU_IER));
940 } else if (IS_VALLEYVIEW(dev)) {
941 seq_printf(m, "Display IER:\t%08x\n",
942 I915_READ(VLV_IER));
943 seq_printf(m, "Display IIR:\t%08x\n",
944 I915_READ(VLV_IIR));
945 seq_printf(m, "Display IIR_RW:\t%08x\n",
946 I915_READ(VLV_IIR_RW));
947 seq_printf(m, "Display IMR:\t%08x\n",
948 I915_READ(VLV_IMR));
949 for_each_pipe(dev_priv, pipe)
950 seq_printf(m, "Pipe %c stat:\t%08x\n",
951 pipe_name(pipe),
952 I915_READ(PIPESTAT(pipe)));
953
954 seq_printf(m, "Master IER:\t%08x\n",
955 I915_READ(VLV_MASTER_IER));
956
957 seq_printf(m, "Render IER:\t%08x\n",
958 I915_READ(GTIER));
959 seq_printf(m, "Render IIR:\t%08x\n",
960 I915_READ(GTIIR));
961 seq_printf(m, "Render IMR:\t%08x\n",
962 I915_READ(GTIMR));
963
964 seq_printf(m, "PM IER:\t\t%08x\n",
965 I915_READ(GEN6_PMIER));
966 seq_printf(m, "PM IIR:\t\t%08x\n",
967 I915_READ(GEN6_PMIIR));
968 seq_printf(m, "PM IMR:\t\t%08x\n",
969 I915_READ(GEN6_PMIMR));
970
971 seq_printf(m, "Port hotplug:\t%08x\n",
972 I915_READ(PORT_HOTPLUG_EN));
973 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
974 I915_READ(VLV_DPFLIPSTAT));
975 seq_printf(m, "DPINVGTT:\t%08x\n",
976 I915_READ(DPINVGTT));
977
978 } else if (!HAS_PCH_SPLIT(dev)) {
979 seq_printf(m, "Interrupt enable: %08x\n",
980 I915_READ(IER));
981 seq_printf(m, "Interrupt identity: %08x\n",
982 I915_READ(IIR));
983 seq_printf(m, "Interrupt mask: %08x\n",
984 I915_READ(IMR));
985 for_each_pipe(dev_priv, pipe)
986 seq_printf(m, "Pipe %c stat: %08x\n",
987 pipe_name(pipe),
988 I915_READ(PIPESTAT(pipe)));
989 } else {
990 seq_printf(m, "North Display Interrupt enable: %08x\n",
991 I915_READ(DEIER));
992 seq_printf(m, "North Display Interrupt identity: %08x\n",
993 I915_READ(DEIIR));
994 seq_printf(m, "North Display Interrupt mask: %08x\n",
995 I915_READ(DEIMR));
996 seq_printf(m, "South Display Interrupt enable: %08x\n",
997 I915_READ(SDEIER));
998 seq_printf(m, "South Display Interrupt identity: %08x\n",
999 I915_READ(SDEIIR));
1000 seq_printf(m, "South Display Interrupt mask: %08x\n",
1001 I915_READ(SDEIMR));
1002 seq_printf(m, "Graphics Interrupt enable: %08x\n",
1003 I915_READ(GTIER));
1004 seq_printf(m, "Graphics Interrupt identity: %08x\n",
1005 I915_READ(GTIIR));
1006 seq_printf(m, "Graphics Interrupt mask: %08x\n",
1007 I915_READ(GTIMR));
1008 }
1009 for_each_engine(engine, dev_priv) {
1010 if (INTEL_INFO(dev)->gen >= 6) {
1011 seq_printf(m,
1012 "Graphics Interrupt mask (%s): %08x\n",
1013 engine->name, I915_READ_IMR(engine));
1014 }
1015 i915_ring_seqno_info(m, engine);
1016 }
1017 intel_runtime_pm_put(dev_priv);
1018 mutex_unlock(&dev->struct_mutex);
1019
1020 return 0;
1021 }
1022
1023 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
1024 {
1025 struct drm_info_node *node = m->private;
1026 struct drm_device *dev = node->minor->dev;
1027 struct drm_i915_private *dev_priv = to_i915(dev);
1028 int i, ret;
1029
1030 ret = mutex_lock_interruptible(&dev->struct_mutex);
1031 if (ret)
1032 return ret;
1033
1034 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
1035 for (i = 0; i < dev_priv->num_fence_regs; i++) {
1036 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
1037
1038 seq_printf(m, "Fence %d, pin count = %d, object = ",
1039 i, dev_priv->fence_regs[i].pin_count);
1040 if (obj == NULL)
1041 seq_puts(m, "unused");
1042 else
1043 describe_obj(m, obj);
1044 seq_putc(m, '\n');
1045 }
1046
1047 mutex_unlock(&dev->struct_mutex);
1048 return 0;
1049 }
1050
1051 static int i915_hws_info(struct seq_file *m, void *data)
1052 {
1053 struct drm_info_node *node = m->private;
1054 struct drm_device *dev = node->minor->dev;
1055 struct drm_i915_private *dev_priv = to_i915(dev);
1056 struct intel_engine_cs *engine;
1057 const u32 *hws;
1058 int i;
1059
1060 engine = &dev_priv->engine[(uintptr_t)node->info_ent->data];
1061 hws = engine->status_page.page_addr;
1062 if (hws == NULL)
1063 return 0;
1064
1065 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
1066 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1067 i * 4,
1068 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
1069 }
1070 return 0;
1071 }
1072
1073 static ssize_t
1074 i915_error_state_write(struct file *filp,
1075 const char __user *ubuf,
1076 size_t cnt,
1077 loff_t *ppos)
1078 {
1079 struct i915_error_state_file_priv *error_priv = filp->private_data;
1080 struct drm_device *dev = error_priv->dev;
1081 int ret;
1082
1083 DRM_DEBUG_DRIVER("Resetting error state\n");
1084
1085 ret = mutex_lock_interruptible(&dev->struct_mutex);
1086 if (ret)
1087 return ret;
1088
1089 i915_destroy_error_state(dev);
1090 mutex_unlock(&dev->struct_mutex);
1091
1092 return cnt;
1093 }
1094
1095 static int i915_error_state_open(struct inode *inode, struct file *file)
1096 {
1097 struct drm_device *dev = inode->i_private;
1098 struct i915_error_state_file_priv *error_priv;
1099
1100 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1101 if (!error_priv)
1102 return -ENOMEM;
1103
1104 error_priv->dev = dev;
1105
1106 i915_error_state_get(dev, error_priv);
1107
1108 file->private_data = error_priv;
1109
1110 return 0;
1111 }
1112
1113 static int i915_error_state_release(struct inode *inode, struct file *file)
1114 {
1115 struct i915_error_state_file_priv *error_priv = file->private_data;
1116
1117 i915_error_state_put(error_priv);
1118 kfree(error_priv);
1119
1120 return 0;
1121 }
1122
1123 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1124 size_t count, loff_t *pos)
1125 {
1126 struct i915_error_state_file_priv *error_priv = file->private_data;
1127 struct drm_i915_error_state_buf error_str;
1128 loff_t tmp_pos = 0;
1129 ssize_t ret_count = 0;
1130 int ret;
1131
1132 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1133 if (ret)
1134 return ret;
1135
1136 ret = i915_error_state_to_str(&error_str, error_priv);
1137 if (ret)
1138 goto out;
1139
1140 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1141 error_str.buf,
1142 error_str.bytes);
1143
1144 if (ret_count < 0)
1145 ret = ret_count;
1146 else
1147 *pos = error_str.start + ret_count;
1148 out:
1149 i915_error_state_buf_release(&error_str);
1150 return ret ?: ret_count;
1151 }
1152
1153 static const struct file_operations i915_error_state_fops = {
1154 .owner = THIS_MODULE,
1155 .open = i915_error_state_open,
1156 .read = i915_error_state_read,
1157 .write = i915_error_state_write,
1158 .llseek = default_llseek,
1159 .release = i915_error_state_release,
1160 };
1161
1162 static int
1163 i915_next_seqno_get(void *data, u64 *val)
1164 {
1165 struct drm_device *dev = data;
1166 struct drm_i915_private *dev_priv = to_i915(dev);
1167 int ret;
1168
1169 ret = mutex_lock_interruptible(&dev->struct_mutex);
1170 if (ret)
1171 return ret;
1172
1173 *val = dev_priv->next_seqno;
1174 mutex_unlock(&dev->struct_mutex);
1175
1176 return 0;
1177 }
1178
1179 static int
1180 i915_next_seqno_set(void *data, u64 val)
1181 {
1182 struct drm_device *dev = data;
1183 int ret;
1184
1185 ret = mutex_lock_interruptible(&dev->struct_mutex);
1186 if (ret)
1187 return ret;
1188
1189 ret = i915_gem_set_seqno(dev, val);
1190 mutex_unlock(&dev->struct_mutex);
1191
1192 return ret;
1193 }
1194
1195 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1196 i915_next_seqno_get, i915_next_seqno_set,
1197 "0x%llx\n");
1198
1199 static int i915_frequency_info(struct seq_file *m, void *unused)
1200 {
1201 struct drm_info_node *node = m->private;
1202 struct drm_device *dev = node->minor->dev;
1203 struct drm_i915_private *dev_priv = to_i915(dev);
1204 int ret = 0;
1205
1206 intel_runtime_pm_get(dev_priv);
1207
1208 if (IS_GEN5(dev)) {
1209 u16 rgvswctl = I915_READ16(MEMSWCTL);
1210 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1211
1212 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1213 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1214 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1215 MEMSTAT_VID_SHIFT);
1216 seq_printf(m, "Current P-state: %d\n",
1217 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1218 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1219 u32 freq_sts;
1220
1221 mutex_lock(&dev_priv->rps.hw_lock);
1222 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1223 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1224 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1225
1226 seq_printf(m, "actual GPU freq: %d MHz\n",
1227 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1228
1229 seq_printf(m, "current GPU freq: %d MHz\n",
1230 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1231
1232 seq_printf(m, "max GPU freq: %d MHz\n",
1233 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1234
1235 seq_printf(m, "min GPU freq: %d MHz\n",
1236 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1237
1238 seq_printf(m, "idle GPU freq: %d MHz\n",
1239 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1240
1241 seq_printf(m,
1242 "efficient (RPe) frequency: %d MHz\n",
1243 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1244 mutex_unlock(&dev_priv->rps.hw_lock);
1245 } else if (INTEL_INFO(dev)->gen >= 6) {
1246 u32 rp_state_limits;
1247 u32 gt_perf_status;
1248 u32 rp_state_cap;
1249 u32 rpmodectl, rpinclimit, rpdeclimit;
1250 u32 rpstat, cagf, reqf;
1251 u32 rpupei, rpcurup, rpprevup;
1252 u32 rpdownei, rpcurdown, rpprevdown;
1253 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1254 int max_freq;
1255
1256 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1257 if (IS_BROXTON(dev)) {
1258 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1259 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1260 } else {
1261 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1262 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1263 }
1264
1265 /* RPSTAT1 is in the GT power well */
1266 ret = mutex_lock_interruptible(&dev->struct_mutex);
1267 if (ret)
1268 goto out;
1269
1270 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1271
1272 reqf = I915_READ(GEN6_RPNSWREQ);
1273 if (IS_GEN9(dev))
1274 reqf >>= 23;
1275 else {
1276 reqf &= ~GEN6_TURBO_DISABLE;
1277 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1278 reqf >>= 24;
1279 else
1280 reqf >>= 25;
1281 }
1282 reqf = intel_gpu_freq(dev_priv, reqf);
1283
1284 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1285 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1286 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1287
1288 rpstat = I915_READ(GEN6_RPSTAT1);
1289 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1290 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1291 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1292 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1293 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1294 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1295 if (IS_GEN9(dev))
1296 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1297 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1298 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1299 else
1300 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1301 cagf = intel_gpu_freq(dev_priv, cagf);
1302
1303 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1304 mutex_unlock(&dev->struct_mutex);
1305
1306 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1307 pm_ier = I915_READ(GEN6_PMIER);
1308 pm_imr = I915_READ(GEN6_PMIMR);
1309 pm_isr = I915_READ(GEN6_PMISR);
1310 pm_iir = I915_READ(GEN6_PMIIR);
1311 pm_mask = I915_READ(GEN6_PMINTRMSK);
1312 } else {
1313 pm_ier = I915_READ(GEN8_GT_IER(2));
1314 pm_imr = I915_READ(GEN8_GT_IMR(2));
1315 pm_isr = I915_READ(GEN8_GT_ISR(2));
1316 pm_iir = I915_READ(GEN8_GT_IIR(2));
1317 pm_mask = I915_READ(GEN6_PMINTRMSK);
1318 }
1319 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1320 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1321 seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep);
1322 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1323 seq_printf(m, "Render p-state ratio: %d\n",
1324 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
1325 seq_printf(m, "Render p-state VID: %d\n",
1326 gt_perf_status & 0xff);
1327 seq_printf(m, "Render p-state limit: %d\n",
1328 rp_state_limits & 0xff);
1329 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1330 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1331 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1332 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1333 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1334 seq_printf(m, "CAGF: %dMHz\n", cagf);
1335 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1336 rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1337 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1338 rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1339 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1340 rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1341 seq_printf(m, "Up threshold: %d%%\n",
1342 dev_priv->rps.up_threshold);
1343
1344 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1345 rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1346 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1347 rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1348 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1349 rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1350 seq_printf(m, "Down threshold: %d%%\n",
1351 dev_priv->rps.down_threshold);
1352
1353 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1354 rp_state_cap >> 16) & 0xff;
1355 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1356 GEN9_FREQ_SCALER : 1);
1357 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1358 intel_gpu_freq(dev_priv, max_freq));
1359
1360 max_freq = (rp_state_cap & 0xff00) >> 8;
1361 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1362 GEN9_FREQ_SCALER : 1);
1363 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1364 intel_gpu_freq(dev_priv, max_freq));
1365
1366 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1367 rp_state_cap >> 0) & 0xff;
1368 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1369 GEN9_FREQ_SCALER : 1);
1370 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1371 intel_gpu_freq(dev_priv, max_freq));
1372 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1373 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1374
1375 seq_printf(m, "Current freq: %d MHz\n",
1376 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1377 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1378 seq_printf(m, "Idle freq: %d MHz\n",
1379 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1380 seq_printf(m, "Min freq: %d MHz\n",
1381 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1382 seq_printf(m, "Boost freq: %d MHz\n",
1383 intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
1384 seq_printf(m, "Max freq: %d MHz\n",
1385 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1386 seq_printf(m,
1387 "efficient (RPe) frequency: %d MHz\n",
1388 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1389 } else {
1390 seq_puts(m, "no P-state info available\n");
1391 }
1392
1393 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1394 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1395 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1396
1397 out:
1398 intel_runtime_pm_put(dev_priv);
1399 return ret;
1400 }
1401
1402 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1403 {
1404 struct drm_info_node *node = m->private;
1405 struct drm_device *dev = node->minor->dev;
1406 struct drm_i915_private *dev_priv = to_i915(dev);
1407 struct intel_engine_cs *engine;
1408 u64 acthd[I915_NUM_ENGINES];
1409 u32 seqno[I915_NUM_ENGINES];
1410 u32 instdone[I915_NUM_INSTDONE_REG];
1411 enum intel_engine_id id;
1412 int j;
1413
1414 if (!i915.enable_hangcheck) {
1415 seq_printf(m, "Hangcheck disabled\n");
1416 return 0;
1417 }
1418
1419 intel_runtime_pm_get(dev_priv);
1420
1421 for_each_engine_id(engine, dev_priv, id) {
1422 acthd[id] = intel_ring_get_active_head(engine);
1423 seqno[id] = intel_engine_get_seqno(engine);
1424 }
1425
1426 i915_get_extra_instdone(dev_priv, instdone);
1427
1428 intel_runtime_pm_put(dev_priv);
1429
1430 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1431 seq_printf(m, "Hangcheck active, fires in %dms\n",
1432 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1433 jiffies));
1434 } else
1435 seq_printf(m, "Hangcheck inactive\n");
1436
1437 for_each_engine_id(engine, dev_priv, id) {
1438 seq_printf(m, "%s:\n", engine->name);
1439 seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
1440 engine->hangcheck.seqno,
1441 seqno[id],
1442 engine->last_submitted_seqno);
1443 seq_printf(m, "\twaiters? %d\n",
1444 intel_engine_has_waiter(engine));
1445 seq_printf(m, "\tuser interrupts = %lx [current %lx]\n",
1446 engine->hangcheck.user_interrupts,
1447 READ_ONCE(engine->breadcrumbs.irq_wakeups));
1448 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1449 (long long)engine->hangcheck.acthd,
1450 (long long)acthd[id]);
1451 seq_printf(m, "\tscore = %d\n", engine->hangcheck.score);
1452 seq_printf(m, "\taction = %d\n", engine->hangcheck.action);
1453
1454 if (engine->id == RCS) {
1455 seq_puts(m, "\tinstdone read =");
1456
1457 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1458 seq_printf(m, " 0x%08x", instdone[j]);
1459
1460 seq_puts(m, "\n\tinstdone accu =");
1461
1462 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1463 seq_printf(m, " 0x%08x",
1464 engine->hangcheck.instdone[j]);
1465
1466 seq_puts(m, "\n");
1467 }
1468 }
1469
1470 return 0;
1471 }
1472
1473 static int ironlake_drpc_info(struct seq_file *m)
1474 {
1475 struct drm_info_node *node = m->private;
1476 struct drm_device *dev = node->minor->dev;
1477 struct drm_i915_private *dev_priv = to_i915(dev);
1478 u32 rgvmodectl, rstdbyctl;
1479 u16 crstandvid;
1480 int ret;
1481
1482 ret = mutex_lock_interruptible(&dev->struct_mutex);
1483 if (ret)
1484 return ret;
1485 intel_runtime_pm_get(dev_priv);
1486
1487 rgvmodectl = I915_READ(MEMMODECTL);
1488 rstdbyctl = I915_READ(RSTDBYCTL);
1489 crstandvid = I915_READ16(CRSTANDVID);
1490
1491 intel_runtime_pm_put(dev_priv);
1492 mutex_unlock(&dev->struct_mutex);
1493
1494 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1495 seq_printf(m, "Boost freq: %d\n",
1496 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1497 MEMMODE_BOOST_FREQ_SHIFT);
1498 seq_printf(m, "HW control enabled: %s\n",
1499 yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1500 seq_printf(m, "SW control enabled: %s\n",
1501 yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1502 seq_printf(m, "Gated voltage change: %s\n",
1503 yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1504 seq_printf(m, "Starting frequency: P%d\n",
1505 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1506 seq_printf(m, "Max P-state: P%d\n",
1507 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1508 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1509 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1510 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1511 seq_printf(m, "Render standby enabled: %s\n",
1512 yesno(!(rstdbyctl & RCX_SW_EXIT)));
1513 seq_puts(m, "Current RS state: ");
1514 switch (rstdbyctl & RSX_STATUS_MASK) {
1515 case RSX_STATUS_ON:
1516 seq_puts(m, "on\n");
1517 break;
1518 case RSX_STATUS_RC1:
1519 seq_puts(m, "RC1\n");
1520 break;
1521 case RSX_STATUS_RC1E:
1522 seq_puts(m, "RC1E\n");
1523 break;
1524 case RSX_STATUS_RS1:
1525 seq_puts(m, "RS1\n");
1526 break;
1527 case RSX_STATUS_RS2:
1528 seq_puts(m, "RS2 (RC6)\n");
1529 break;
1530 case RSX_STATUS_RS3:
1531 seq_puts(m, "RC3 (RC6+)\n");
1532 break;
1533 default:
1534 seq_puts(m, "unknown\n");
1535 break;
1536 }
1537
1538 return 0;
1539 }
1540
1541 static int i915_forcewake_domains(struct seq_file *m, void *data)
1542 {
1543 struct drm_info_node *node = m->private;
1544 struct drm_device *dev = node->minor->dev;
1545 struct drm_i915_private *dev_priv = to_i915(dev);
1546 struct intel_uncore_forcewake_domain *fw_domain;
1547
1548 spin_lock_irq(&dev_priv->uncore.lock);
1549 for_each_fw_domain(fw_domain, dev_priv) {
1550 seq_printf(m, "%s.wake_count = %u\n",
1551 intel_uncore_forcewake_domain_to_str(fw_domain->id),
1552 fw_domain->wake_count);
1553 }
1554 spin_unlock_irq(&dev_priv->uncore.lock);
1555
1556 return 0;
1557 }
1558
1559 static int vlv_drpc_info(struct seq_file *m)
1560 {
1561 struct drm_info_node *node = m->private;
1562 struct drm_device *dev = node->minor->dev;
1563 struct drm_i915_private *dev_priv = to_i915(dev);
1564 u32 rpmodectl1, rcctl1, pw_status;
1565
1566 intel_runtime_pm_get(dev_priv);
1567
1568 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1569 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1570 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1571
1572 intel_runtime_pm_put(dev_priv);
1573
1574 seq_printf(m, "Video Turbo Mode: %s\n",
1575 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1576 seq_printf(m, "Turbo enabled: %s\n",
1577 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1578 seq_printf(m, "HW control enabled: %s\n",
1579 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1580 seq_printf(m, "SW control enabled: %s\n",
1581 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1582 GEN6_RP_MEDIA_SW_MODE));
1583 seq_printf(m, "RC6 Enabled: %s\n",
1584 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1585 GEN6_RC_CTL_EI_MODE(1))));
1586 seq_printf(m, "Render Power Well: %s\n",
1587 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1588 seq_printf(m, "Media Power Well: %s\n",
1589 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1590
1591 seq_printf(m, "Render RC6 residency since boot: %u\n",
1592 I915_READ(VLV_GT_RENDER_RC6));
1593 seq_printf(m, "Media RC6 residency since boot: %u\n",
1594 I915_READ(VLV_GT_MEDIA_RC6));
1595
1596 return i915_forcewake_domains(m, NULL);
1597 }
1598
1599 static int gen6_drpc_info(struct seq_file *m)
1600 {
1601 struct drm_info_node *node = m->private;
1602 struct drm_device *dev = node->minor->dev;
1603 struct drm_i915_private *dev_priv = to_i915(dev);
1604 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1605 unsigned forcewake_count;
1606 int count = 0, ret;
1607
1608 ret = mutex_lock_interruptible(&dev->struct_mutex);
1609 if (ret)
1610 return ret;
1611 intel_runtime_pm_get(dev_priv);
1612
1613 spin_lock_irq(&dev_priv->uncore.lock);
1614 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1615 spin_unlock_irq(&dev_priv->uncore.lock);
1616
1617 if (forcewake_count) {
1618 seq_puts(m, "RC information inaccurate because somebody "
1619 "holds a forcewake reference \n");
1620 } else {
1621 /* NB: we cannot use forcewake, else we read the wrong values */
1622 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1623 udelay(10);
1624 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1625 }
1626
1627 gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1628 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1629
1630 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1631 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1632 mutex_unlock(&dev->struct_mutex);
1633 mutex_lock(&dev_priv->rps.hw_lock);
1634 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1635 mutex_unlock(&dev_priv->rps.hw_lock);
1636
1637 intel_runtime_pm_put(dev_priv);
1638
1639 seq_printf(m, "Video Turbo Mode: %s\n",
1640 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1641 seq_printf(m, "HW control enabled: %s\n",
1642 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1643 seq_printf(m, "SW control enabled: %s\n",
1644 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1645 GEN6_RP_MEDIA_SW_MODE));
1646 seq_printf(m, "RC1e Enabled: %s\n",
1647 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1648 seq_printf(m, "RC6 Enabled: %s\n",
1649 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1650 seq_printf(m, "Deep RC6 Enabled: %s\n",
1651 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1652 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1653 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1654 seq_puts(m, "Current RC state: ");
1655 switch (gt_core_status & GEN6_RCn_MASK) {
1656 case GEN6_RC0:
1657 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1658 seq_puts(m, "Core Power Down\n");
1659 else
1660 seq_puts(m, "on\n");
1661 break;
1662 case GEN6_RC3:
1663 seq_puts(m, "RC3\n");
1664 break;
1665 case GEN6_RC6:
1666 seq_puts(m, "RC6\n");
1667 break;
1668 case GEN6_RC7:
1669 seq_puts(m, "RC7\n");
1670 break;
1671 default:
1672 seq_puts(m, "Unknown\n");
1673 break;
1674 }
1675
1676 seq_printf(m, "Core Power Down: %s\n",
1677 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1678
1679 /* Not exactly sure what this is */
1680 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1681 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1682 seq_printf(m, "RC6 residency since boot: %u\n",
1683 I915_READ(GEN6_GT_GFX_RC6));
1684 seq_printf(m, "RC6+ residency since boot: %u\n",
1685 I915_READ(GEN6_GT_GFX_RC6p));
1686 seq_printf(m, "RC6++ residency since boot: %u\n",
1687 I915_READ(GEN6_GT_GFX_RC6pp));
1688
1689 seq_printf(m, "RC6 voltage: %dmV\n",
1690 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1691 seq_printf(m, "RC6+ voltage: %dmV\n",
1692 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1693 seq_printf(m, "RC6++ voltage: %dmV\n",
1694 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1695 return 0;
1696 }
1697
1698 static int i915_drpc_info(struct seq_file *m, void *unused)
1699 {
1700 struct drm_info_node *node = m->private;
1701 struct drm_device *dev = node->minor->dev;
1702
1703 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1704 return vlv_drpc_info(m);
1705 else if (INTEL_INFO(dev)->gen >= 6)
1706 return gen6_drpc_info(m);
1707 else
1708 return ironlake_drpc_info(m);
1709 }
1710
1711 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1712 {
1713 struct drm_info_node *node = m->private;
1714 struct drm_device *dev = node->minor->dev;
1715 struct drm_i915_private *dev_priv = to_i915(dev);
1716
1717 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1718 dev_priv->fb_tracking.busy_bits);
1719
1720 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1721 dev_priv->fb_tracking.flip_bits);
1722
1723 return 0;
1724 }
1725
1726 static int i915_fbc_status(struct seq_file *m, void *unused)
1727 {
1728 struct drm_info_node *node = m->private;
1729 struct drm_device *dev = node->minor->dev;
1730 struct drm_i915_private *dev_priv = to_i915(dev);
1731
1732 if (!HAS_FBC(dev)) {
1733 seq_puts(m, "FBC unsupported on this chipset\n");
1734 return 0;
1735 }
1736
1737 intel_runtime_pm_get(dev_priv);
1738 mutex_lock(&dev_priv->fbc.lock);
1739
1740 if (intel_fbc_is_active(dev_priv))
1741 seq_puts(m, "FBC enabled\n");
1742 else
1743 seq_printf(m, "FBC disabled: %s\n",
1744 dev_priv->fbc.no_fbc_reason);
1745
1746 if (INTEL_INFO(dev_priv)->gen >= 7)
1747 seq_printf(m, "Compressing: %s\n",
1748 yesno(I915_READ(FBC_STATUS2) &
1749 FBC_COMPRESSION_MASK));
1750
1751 mutex_unlock(&dev_priv->fbc.lock);
1752 intel_runtime_pm_put(dev_priv);
1753
1754 return 0;
1755 }
1756
1757 static int i915_fbc_fc_get(void *data, u64 *val)
1758 {
1759 struct drm_device *dev = data;
1760 struct drm_i915_private *dev_priv = to_i915(dev);
1761
1762 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1763 return -ENODEV;
1764
1765 *val = dev_priv->fbc.false_color;
1766
1767 return 0;
1768 }
1769
1770 static int i915_fbc_fc_set(void *data, u64 val)
1771 {
1772 struct drm_device *dev = data;
1773 struct drm_i915_private *dev_priv = to_i915(dev);
1774 u32 reg;
1775
1776 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1777 return -ENODEV;
1778
1779 mutex_lock(&dev_priv->fbc.lock);
1780
1781 reg = I915_READ(ILK_DPFC_CONTROL);
1782 dev_priv->fbc.false_color = val;
1783
1784 I915_WRITE(ILK_DPFC_CONTROL, val ?
1785 (reg | FBC_CTL_FALSE_COLOR) :
1786 (reg & ~FBC_CTL_FALSE_COLOR));
1787
1788 mutex_unlock(&dev_priv->fbc.lock);
1789 return 0;
1790 }
1791
1792 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1793 i915_fbc_fc_get, i915_fbc_fc_set,
1794 "%llu\n");
1795
1796 static int i915_ips_status(struct seq_file *m, void *unused)
1797 {
1798 struct drm_info_node *node = m->private;
1799 struct drm_device *dev = node->minor->dev;
1800 struct drm_i915_private *dev_priv = to_i915(dev);
1801
1802 if (!HAS_IPS(dev)) {
1803 seq_puts(m, "not supported\n");
1804 return 0;
1805 }
1806
1807 intel_runtime_pm_get(dev_priv);
1808
1809 seq_printf(m, "Enabled by kernel parameter: %s\n",
1810 yesno(i915.enable_ips));
1811
1812 if (INTEL_INFO(dev)->gen >= 8) {
1813 seq_puts(m, "Currently: unknown\n");
1814 } else {
1815 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1816 seq_puts(m, "Currently: enabled\n");
1817 else
1818 seq_puts(m, "Currently: disabled\n");
1819 }
1820
1821 intel_runtime_pm_put(dev_priv);
1822
1823 return 0;
1824 }
1825
1826 static int i915_sr_status(struct seq_file *m, void *unused)
1827 {
1828 struct drm_info_node *node = m->private;
1829 struct drm_device *dev = node->minor->dev;
1830 struct drm_i915_private *dev_priv = to_i915(dev);
1831 bool sr_enabled = false;
1832
1833 intel_runtime_pm_get(dev_priv);
1834
1835 if (HAS_PCH_SPLIT(dev))
1836 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1837 else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1838 IS_I945G(dev) || IS_I945GM(dev))
1839 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1840 else if (IS_I915GM(dev))
1841 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1842 else if (IS_PINEVIEW(dev))
1843 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1844 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1845 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1846
1847 intel_runtime_pm_put(dev_priv);
1848
1849 seq_printf(m, "self-refresh: %s\n",
1850 sr_enabled ? "enabled" : "disabled");
1851
1852 return 0;
1853 }
1854
1855 static int i915_emon_status(struct seq_file *m, void *unused)
1856 {
1857 struct drm_info_node *node = m->private;
1858 struct drm_device *dev = node->minor->dev;
1859 struct drm_i915_private *dev_priv = to_i915(dev);
1860 unsigned long temp, chipset, gfx;
1861 int ret;
1862
1863 if (!IS_GEN5(dev))
1864 return -ENODEV;
1865
1866 ret = mutex_lock_interruptible(&dev->struct_mutex);
1867 if (ret)
1868 return ret;
1869
1870 temp = i915_mch_val(dev_priv);
1871 chipset = i915_chipset_val(dev_priv);
1872 gfx = i915_gfx_val(dev_priv);
1873 mutex_unlock(&dev->struct_mutex);
1874
1875 seq_printf(m, "GMCH temp: %ld\n", temp);
1876 seq_printf(m, "Chipset power: %ld\n", chipset);
1877 seq_printf(m, "GFX power: %ld\n", gfx);
1878 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1879
1880 return 0;
1881 }
1882
1883 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1884 {
1885 struct drm_info_node *node = m->private;
1886 struct drm_device *dev = node->minor->dev;
1887 struct drm_i915_private *dev_priv = to_i915(dev);
1888 int ret = 0;
1889 int gpu_freq, ia_freq;
1890 unsigned int max_gpu_freq, min_gpu_freq;
1891
1892 if (!HAS_CORE_RING_FREQ(dev)) {
1893 seq_puts(m, "unsupported on this chipset\n");
1894 return 0;
1895 }
1896
1897 intel_runtime_pm_get(dev_priv);
1898
1899 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1900 if (ret)
1901 goto out;
1902
1903 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
1904 /* Convert GT frequency to 50 HZ units */
1905 min_gpu_freq =
1906 dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1907 max_gpu_freq =
1908 dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1909 } else {
1910 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1911 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1912 }
1913
1914 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1915
1916 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1917 ia_freq = gpu_freq;
1918 sandybridge_pcode_read(dev_priv,
1919 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1920 &ia_freq);
1921 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1922 intel_gpu_freq(dev_priv, (gpu_freq *
1923 (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1924 GEN9_FREQ_SCALER : 1))),
1925 ((ia_freq >> 0) & 0xff) * 100,
1926 ((ia_freq >> 8) & 0xff) * 100);
1927 }
1928
1929 mutex_unlock(&dev_priv->rps.hw_lock);
1930
1931 out:
1932 intel_runtime_pm_put(dev_priv);
1933 return ret;
1934 }
1935
1936 static int i915_opregion(struct seq_file *m, void *unused)
1937 {
1938 struct drm_info_node *node = m->private;
1939 struct drm_device *dev = node->minor->dev;
1940 struct drm_i915_private *dev_priv = to_i915(dev);
1941 struct intel_opregion *opregion = &dev_priv->opregion;
1942 int ret;
1943
1944 ret = mutex_lock_interruptible(&dev->struct_mutex);
1945 if (ret)
1946 goto out;
1947
1948 if (opregion->header)
1949 seq_write(m, opregion->header, OPREGION_SIZE);
1950
1951 mutex_unlock(&dev->struct_mutex);
1952
1953 out:
1954 return 0;
1955 }
1956
1957 static int i915_vbt(struct seq_file *m, void *unused)
1958 {
1959 struct drm_info_node *node = m->private;
1960 struct drm_device *dev = node->minor->dev;
1961 struct drm_i915_private *dev_priv = to_i915(dev);
1962 struct intel_opregion *opregion = &dev_priv->opregion;
1963
1964 if (opregion->vbt)
1965 seq_write(m, opregion->vbt, opregion->vbt_size);
1966
1967 return 0;
1968 }
1969
1970 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1971 {
1972 struct drm_info_node *node = m->private;
1973 struct drm_device *dev = node->minor->dev;
1974 struct intel_framebuffer *fbdev_fb = NULL;
1975 struct drm_framebuffer *drm_fb;
1976 int ret;
1977
1978 ret = mutex_lock_interruptible(&dev->struct_mutex);
1979 if (ret)
1980 return ret;
1981
1982 #ifdef CONFIG_DRM_FBDEV_EMULATION
1983 if (to_i915(dev)->fbdev) {
1984 fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb);
1985
1986 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1987 fbdev_fb->base.width,
1988 fbdev_fb->base.height,
1989 fbdev_fb->base.depth,
1990 fbdev_fb->base.bits_per_pixel,
1991 fbdev_fb->base.modifier[0],
1992 drm_framebuffer_read_refcount(&fbdev_fb->base));
1993 describe_obj(m, fbdev_fb->obj);
1994 seq_putc(m, '\n');
1995 }
1996 #endif
1997
1998 mutex_lock(&dev->mode_config.fb_lock);
1999 drm_for_each_fb(drm_fb, dev) {
2000 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
2001 if (fb == fbdev_fb)
2002 continue;
2003
2004 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
2005 fb->base.width,
2006 fb->base.height,
2007 fb->base.depth,
2008 fb->base.bits_per_pixel,
2009 fb->base.modifier[0],
2010 drm_framebuffer_read_refcount(&fb->base));
2011 describe_obj(m, fb->obj);
2012 seq_putc(m, '\n');
2013 }
2014 mutex_unlock(&dev->mode_config.fb_lock);
2015 mutex_unlock(&dev->struct_mutex);
2016
2017 return 0;
2018 }
2019
2020 static void describe_ctx_ringbuf(struct seq_file *m,
2021 struct intel_ringbuffer *ringbuf)
2022 {
2023 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
2024 ringbuf->space, ringbuf->head, ringbuf->tail,
2025 ringbuf->last_retired_head);
2026 }
2027
2028 static int i915_context_status(struct seq_file *m, void *unused)
2029 {
2030 struct drm_info_node *node = m->private;
2031 struct drm_device *dev = node->minor->dev;
2032 struct drm_i915_private *dev_priv = to_i915(dev);
2033 struct intel_engine_cs *engine;
2034 struct i915_gem_context *ctx;
2035 int ret;
2036
2037 ret = mutex_lock_interruptible(&dev->struct_mutex);
2038 if (ret)
2039 return ret;
2040
2041 list_for_each_entry(ctx, &dev_priv->context_list, link) {
2042 seq_printf(m, "HW context %u ", ctx->hw_id);
2043 if (IS_ERR(ctx->file_priv)) {
2044 seq_puts(m, "(deleted) ");
2045 } else if (ctx->file_priv) {
2046 struct pid *pid = ctx->file_priv->file->pid;
2047 struct task_struct *task;
2048
2049 task = get_pid_task(pid, PIDTYPE_PID);
2050 if (task) {
2051 seq_printf(m, "(%s [%d]) ",
2052 task->comm, task->pid);
2053 put_task_struct(task);
2054 }
2055 } else {
2056 seq_puts(m, "(kernel) ");
2057 }
2058
2059 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
2060 seq_putc(m, '\n');
2061
2062 for_each_engine(engine, dev_priv) {
2063 struct intel_context *ce = &ctx->engine[engine->id];
2064
2065 seq_printf(m, "%s: ", engine->name);
2066 seq_putc(m, ce->initialised ? 'I' : 'i');
2067 if (ce->state)
2068 describe_obj(m, ce->state);
2069 if (ce->ringbuf)
2070 describe_ctx_ringbuf(m, ce->ringbuf);
2071 seq_putc(m, '\n');
2072 }
2073
2074 seq_putc(m, '\n');
2075 }
2076
2077 mutex_unlock(&dev->struct_mutex);
2078
2079 return 0;
2080 }
2081
2082 static void i915_dump_lrc_obj(struct seq_file *m,
2083 struct i915_gem_context *ctx,
2084 struct intel_engine_cs *engine)
2085 {
2086 struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state;
2087 struct page *page;
2088 uint32_t *reg_state;
2089 int j;
2090 unsigned long ggtt_offset = 0;
2091
2092 seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
2093
2094 if (ctx_obj == NULL) {
2095 seq_puts(m, "\tNot allocated\n");
2096 return;
2097 }
2098
2099 if (!i915_gem_obj_ggtt_bound(ctx_obj))
2100 seq_puts(m, "\tNot bound in GGTT\n");
2101 else
2102 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
2103
2104 if (i915_gem_object_get_pages(ctx_obj)) {
2105 seq_puts(m, "\tFailed to get pages for context object\n");
2106 return;
2107 }
2108
2109 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
2110 if (!WARN_ON(page == NULL)) {
2111 reg_state = kmap_atomic(page);
2112
2113 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2114 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2115 ggtt_offset + 4096 + (j * 4),
2116 reg_state[j], reg_state[j + 1],
2117 reg_state[j + 2], reg_state[j + 3]);
2118 }
2119 kunmap_atomic(reg_state);
2120 }
2121
2122 seq_putc(m, '\n');
2123 }
2124
2125 static int i915_dump_lrc(struct seq_file *m, void *unused)
2126 {
2127 struct drm_info_node *node = (struct drm_info_node *) m->private;
2128 struct drm_device *dev = node->minor->dev;
2129 struct drm_i915_private *dev_priv = to_i915(dev);
2130 struct intel_engine_cs *engine;
2131 struct i915_gem_context *ctx;
2132 int ret;
2133
2134 if (!i915.enable_execlists) {
2135 seq_printf(m, "Logical Ring Contexts are disabled\n");
2136 return 0;
2137 }
2138
2139 ret = mutex_lock_interruptible(&dev->struct_mutex);
2140 if (ret)
2141 return ret;
2142
2143 list_for_each_entry(ctx, &dev_priv->context_list, link)
2144 for_each_engine(engine, dev_priv)
2145 i915_dump_lrc_obj(m, ctx, engine);
2146
2147 mutex_unlock(&dev->struct_mutex);
2148
2149 return 0;
2150 }
2151
2152 static int i915_execlists(struct seq_file *m, void *data)
2153 {
2154 struct drm_info_node *node = (struct drm_info_node *)m->private;
2155 struct drm_device *dev = node->minor->dev;
2156 struct drm_i915_private *dev_priv = to_i915(dev);
2157 struct intel_engine_cs *engine;
2158 u32 status_pointer;
2159 u8 read_pointer;
2160 u8 write_pointer;
2161 u32 status;
2162 u32 ctx_id;
2163 struct list_head *cursor;
2164 int i, ret;
2165
2166 if (!i915.enable_execlists) {
2167 seq_puts(m, "Logical Ring Contexts are disabled\n");
2168 return 0;
2169 }
2170
2171 ret = mutex_lock_interruptible(&dev->struct_mutex);
2172 if (ret)
2173 return ret;
2174
2175 intel_runtime_pm_get(dev_priv);
2176
2177 for_each_engine(engine, dev_priv) {
2178 struct drm_i915_gem_request *head_req = NULL;
2179 int count = 0;
2180
2181 seq_printf(m, "%s\n", engine->name);
2182
2183 status = I915_READ(RING_EXECLIST_STATUS_LO(engine));
2184 ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(engine));
2185 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2186 status, ctx_id);
2187
2188 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
2189 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2190
2191 read_pointer = engine->next_context_status_buffer;
2192 write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
2193 if (read_pointer > write_pointer)
2194 write_pointer += GEN8_CSB_ENTRIES;
2195 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2196 read_pointer, write_pointer);
2197
2198 for (i = 0; i < GEN8_CSB_ENTRIES; i++) {
2199 status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, i));
2200 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, i));
2201
2202 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2203 i, status, ctx_id);
2204 }
2205
2206 spin_lock_bh(&engine->execlist_lock);
2207 list_for_each(cursor, &engine->execlist_queue)
2208 count++;
2209 head_req = list_first_entry_or_null(&engine->execlist_queue,
2210 struct drm_i915_gem_request,
2211 execlist_link);
2212 spin_unlock_bh(&engine->execlist_lock);
2213
2214 seq_printf(m, "\t%d requests in queue\n", count);
2215 if (head_req) {
2216 seq_printf(m, "\tHead request context: %u\n",
2217 head_req->ctx->hw_id);
2218 seq_printf(m, "\tHead request tail: %u\n",
2219 head_req->tail);
2220 }
2221
2222 seq_putc(m, '\n');
2223 }
2224
2225 intel_runtime_pm_put(dev_priv);
2226 mutex_unlock(&dev->struct_mutex);
2227
2228 return 0;
2229 }
2230
2231 static const char *swizzle_string(unsigned swizzle)
2232 {
2233 switch (swizzle) {
2234 case I915_BIT_6_SWIZZLE_NONE:
2235 return "none";
2236 case I915_BIT_6_SWIZZLE_9:
2237 return "bit9";
2238 case I915_BIT_6_SWIZZLE_9_10:
2239 return "bit9/bit10";
2240 case I915_BIT_6_SWIZZLE_9_11:
2241 return "bit9/bit11";
2242 case I915_BIT_6_SWIZZLE_9_10_11:
2243 return "bit9/bit10/bit11";
2244 case I915_BIT_6_SWIZZLE_9_17:
2245 return "bit9/bit17";
2246 case I915_BIT_6_SWIZZLE_9_10_17:
2247 return "bit9/bit10/bit17";
2248 case I915_BIT_6_SWIZZLE_UNKNOWN:
2249 return "unknown";
2250 }
2251
2252 return "bug";
2253 }
2254
2255 static int i915_swizzle_info(struct seq_file *m, void *data)
2256 {
2257 struct drm_info_node *node = m->private;
2258 struct drm_device *dev = node->minor->dev;
2259 struct drm_i915_private *dev_priv = to_i915(dev);
2260 int ret;
2261
2262 ret = mutex_lock_interruptible(&dev->struct_mutex);
2263 if (ret)
2264 return ret;
2265 intel_runtime_pm_get(dev_priv);
2266
2267 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2268 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2269 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2270 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2271
2272 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2273 seq_printf(m, "DDC = 0x%08x\n",
2274 I915_READ(DCC));
2275 seq_printf(m, "DDC2 = 0x%08x\n",
2276 I915_READ(DCC2));
2277 seq_printf(m, "C0DRB3 = 0x%04x\n",
2278 I915_READ16(C0DRB3));
2279 seq_printf(m, "C1DRB3 = 0x%04x\n",
2280 I915_READ16(C1DRB3));
2281 } else if (INTEL_INFO(dev)->gen >= 6) {
2282 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2283 I915_READ(MAD_DIMM_C0));
2284 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2285 I915_READ(MAD_DIMM_C1));
2286 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2287 I915_READ(MAD_DIMM_C2));
2288 seq_printf(m, "TILECTL = 0x%08x\n",
2289 I915_READ(TILECTL));
2290 if (INTEL_INFO(dev)->gen >= 8)
2291 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2292 I915_READ(GAMTARBMODE));
2293 else
2294 seq_printf(m, "ARB_MODE = 0x%08x\n",
2295 I915_READ(ARB_MODE));
2296 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2297 I915_READ(DISP_ARB_CTL));
2298 }
2299
2300 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2301 seq_puts(m, "L-shaped memory detected\n");
2302
2303 intel_runtime_pm_put(dev_priv);
2304 mutex_unlock(&dev->struct_mutex);
2305
2306 return 0;
2307 }
2308
2309 static int per_file_ctx(int id, void *ptr, void *data)
2310 {
2311 struct i915_gem_context *ctx = ptr;
2312 struct seq_file *m = data;
2313 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2314
2315 if (!ppgtt) {
2316 seq_printf(m, " no ppgtt for context %d\n",
2317 ctx->user_handle);
2318 return 0;
2319 }
2320
2321 if (i915_gem_context_is_default(ctx))
2322 seq_puts(m, " default context:\n");
2323 else
2324 seq_printf(m, " context %d:\n", ctx->user_handle);
2325 ppgtt->debug_dump(ppgtt, m);
2326
2327 return 0;
2328 }
2329
2330 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2331 {
2332 struct drm_i915_private *dev_priv = to_i915(dev);
2333 struct intel_engine_cs *engine;
2334 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2335 int i;
2336
2337 if (!ppgtt)
2338 return;
2339
2340 for_each_engine(engine, dev_priv) {
2341 seq_printf(m, "%s\n", engine->name);
2342 for (i = 0; i < 4; i++) {
2343 u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2344 pdp <<= 32;
2345 pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2346 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2347 }
2348 }
2349 }
2350
2351 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2352 {
2353 struct drm_i915_private *dev_priv = to_i915(dev);
2354 struct intel_engine_cs *engine;
2355
2356 if (IS_GEN6(dev_priv))
2357 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2358
2359 for_each_engine(engine, dev_priv) {
2360 seq_printf(m, "%s\n", engine->name);
2361 if (IS_GEN7(dev_priv))
2362 seq_printf(m, "GFX_MODE: 0x%08x\n",
2363 I915_READ(RING_MODE_GEN7(engine)));
2364 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2365 I915_READ(RING_PP_DIR_BASE(engine)));
2366 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2367 I915_READ(RING_PP_DIR_BASE_READ(engine)));
2368 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2369 I915_READ(RING_PP_DIR_DCLV(engine)));
2370 }
2371 if (dev_priv->mm.aliasing_ppgtt) {
2372 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2373
2374 seq_puts(m, "aliasing PPGTT:\n");
2375 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2376
2377 ppgtt->debug_dump(ppgtt, m);
2378 }
2379
2380 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2381 }
2382
2383 static int i915_ppgtt_info(struct seq_file *m, void *data)
2384 {
2385 struct drm_info_node *node = m->private;
2386 struct drm_device *dev = node->minor->dev;
2387 struct drm_i915_private *dev_priv = to_i915(dev);
2388 struct drm_file *file;
2389
2390 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2391 if (ret)
2392 return ret;
2393 intel_runtime_pm_get(dev_priv);
2394
2395 if (INTEL_INFO(dev)->gen >= 8)
2396 gen8_ppgtt_info(m, dev);
2397 else if (INTEL_INFO(dev)->gen >= 6)
2398 gen6_ppgtt_info(m, dev);
2399
2400 mutex_lock(&dev->filelist_mutex);
2401 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2402 struct drm_i915_file_private *file_priv = file->driver_priv;
2403 struct task_struct *task;
2404
2405 task = get_pid_task(file->pid, PIDTYPE_PID);
2406 if (!task) {
2407 ret = -ESRCH;
2408 goto out_unlock;
2409 }
2410 seq_printf(m, "\nproc: %s\n", task->comm);
2411 put_task_struct(task);
2412 idr_for_each(&file_priv->context_idr, per_file_ctx,
2413 (void *)(unsigned long)m);
2414 }
2415 out_unlock:
2416 mutex_unlock(&dev->filelist_mutex);
2417
2418 intel_runtime_pm_put(dev_priv);
2419 mutex_unlock(&dev->struct_mutex);
2420
2421 return ret;
2422 }
2423
2424 static int count_irq_waiters(struct drm_i915_private *i915)
2425 {
2426 struct intel_engine_cs *engine;
2427 int count = 0;
2428
2429 for_each_engine(engine, i915)
2430 count += intel_engine_has_waiter(engine);
2431
2432 return count;
2433 }
2434
2435 static int i915_rps_boost_info(struct seq_file *m, void *data)
2436 {
2437 struct drm_info_node *node = m->private;
2438 struct drm_device *dev = node->minor->dev;
2439 struct drm_i915_private *dev_priv = to_i915(dev);
2440 struct drm_file *file;
2441
2442 seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2443 seq_printf(m, "GPU busy? %s [%x]\n",
2444 yesno(dev_priv->gt.awake), dev_priv->gt.active_engines);
2445 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2446 seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2447 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2448 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2449 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2450 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2451 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2452
2453 mutex_lock(&dev->filelist_mutex);
2454 spin_lock(&dev_priv->rps.client_lock);
2455 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2456 struct drm_i915_file_private *file_priv = file->driver_priv;
2457 struct task_struct *task;
2458
2459 rcu_read_lock();
2460 task = pid_task(file->pid, PIDTYPE_PID);
2461 seq_printf(m, "%s [%d]: %d boosts%s\n",
2462 task ? task->comm : "<unknown>",
2463 task ? task->pid : -1,
2464 file_priv->rps.boosts,
2465 list_empty(&file_priv->rps.link) ? "" : ", active");
2466 rcu_read_unlock();
2467 }
2468 seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts);
2469 spin_unlock(&dev_priv->rps.client_lock);
2470 mutex_unlock(&dev->filelist_mutex);
2471
2472 return 0;
2473 }
2474
2475 static int i915_llc(struct seq_file *m, void *data)
2476 {
2477 struct drm_info_node *node = m->private;
2478 struct drm_device *dev = node->minor->dev;
2479 struct drm_i915_private *dev_priv = to_i915(dev);
2480 const bool edram = INTEL_GEN(dev_priv) > 8;
2481
2482 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2483 seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2484 intel_uncore_edram_size(dev_priv)/1024/1024);
2485
2486 return 0;
2487 }
2488
2489 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2490 {
2491 struct drm_info_node *node = m->private;
2492 struct drm_i915_private *dev_priv = to_i915(node->minor->dev);
2493 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2494 u32 tmp, i;
2495
2496 if (!HAS_GUC_UCODE(dev_priv))
2497 return 0;
2498
2499 seq_printf(m, "GuC firmware status:\n");
2500 seq_printf(m, "\tpath: %s\n",
2501 guc_fw->guc_fw_path);
2502 seq_printf(m, "\tfetch: %s\n",
2503 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2504 seq_printf(m, "\tload: %s\n",
2505 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2506 seq_printf(m, "\tversion wanted: %d.%d\n",
2507 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2508 seq_printf(m, "\tversion found: %d.%d\n",
2509 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2510 seq_printf(m, "\theader: offset is %d; size = %d\n",
2511 guc_fw->header_offset, guc_fw->header_size);
2512 seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2513 guc_fw->ucode_offset, guc_fw->ucode_size);
2514 seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2515 guc_fw->rsa_offset, guc_fw->rsa_size);
2516
2517 tmp = I915_READ(GUC_STATUS);
2518
2519 seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2520 seq_printf(m, "\tBootrom status = 0x%x\n",
2521 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2522 seq_printf(m, "\tuKernel status = 0x%x\n",
2523 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2524 seq_printf(m, "\tMIA Core status = 0x%x\n",
2525 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2526 seq_puts(m, "\nScratch registers:\n");
2527 for (i = 0; i < 16; i++)
2528 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2529
2530 return 0;
2531 }
2532
2533 static void i915_guc_client_info(struct seq_file *m,
2534 struct drm_i915_private *dev_priv,
2535 struct i915_guc_client *client)
2536 {
2537 struct intel_engine_cs *engine;
2538 uint64_t tot = 0;
2539
2540 seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2541 client->priority, client->ctx_index, client->proc_desc_offset);
2542 seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2543 client->doorbell_id, client->doorbell_offset, client->cookie);
2544 seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2545 client->wq_size, client->wq_offset, client->wq_tail);
2546
2547 seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);
2548 seq_printf(m, "\tFailed to queue: %u\n", client->q_fail);
2549 seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2550 seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2551
2552 for_each_engine(engine, dev_priv) {
2553 seq_printf(m, "\tSubmissions: %llu %s\n",
2554 client->submissions[engine->id],
2555 engine->name);
2556 tot += client->submissions[engine->id];
2557 }
2558 seq_printf(m, "\tTotal: %llu\n", tot);
2559 }
2560
2561 static int i915_guc_info(struct seq_file *m, void *data)
2562 {
2563 struct drm_info_node *node = m->private;
2564 struct drm_device *dev = node->minor->dev;
2565 struct drm_i915_private *dev_priv = to_i915(dev);
2566 struct intel_guc guc;
2567 struct i915_guc_client client = {};
2568 struct intel_engine_cs *engine;
2569 u64 total = 0;
2570
2571 if (!HAS_GUC_SCHED(dev_priv))
2572 return 0;
2573
2574 if (mutex_lock_interruptible(&dev->struct_mutex))
2575 return 0;
2576
2577 /* Take a local copy of the GuC data, so we can dump it at leisure */
2578 guc = dev_priv->guc;
2579 if (guc.execbuf_client)
2580 client = *guc.execbuf_client;
2581
2582 mutex_unlock(&dev->struct_mutex);
2583
2584 seq_printf(m, "Doorbell map:\n");
2585 seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc.doorbell_bitmap);
2586 seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc.db_cacheline);
2587
2588 seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2589 seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2590 seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2591 seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2592 seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2593
2594 seq_printf(m, "\nGuC submissions:\n");
2595 for_each_engine(engine, dev_priv) {
2596 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
2597 engine->name, guc.submissions[engine->id],
2598 guc.last_seqno[engine->id]);
2599 total += guc.submissions[engine->id];
2600 }
2601 seq_printf(m, "\t%s: %llu\n", "Total", total);
2602
2603 seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2604 i915_guc_client_info(m, dev_priv, &client);
2605
2606 /* Add more as required ... */
2607
2608 return 0;
2609 }
2610
2611 static int i915_guc_log_dump(struct seq_file *m, void *data)
2612 {
2613 struct drm_info_node *node = m->private;
2614 struct drm_device *dev = node->minor->dev;
2615 struct drm_i915_private *dev_priv = to_i915(dev);
2616 struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;
2617 u32 *log;
2618 int i = 0, pg;
2619
2620 if (!log_obj)
2621 return 0;
2622
2623 for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) {
2624 log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));
2625
2626 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2627 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2628 *(log + i), *(log + i + 1),
2629 *(log + i + 2), *(log + i + 3));
2630
2631 kunmap_atomic(log);
2632 }
2633
2634 seq_putc(m, '\n');
2635
2636 return 0;
2637 }
2638
2639 static int i915_edp_psr_status(struct seq_file *m, void *data)
2640 {
2641 struct drm_info_node *node = m->private;
2642 struct drm_device *dev = node->minor->dev;
2643 struct drm_i915_private *dev_priv = to_i915(dev);
2644 u32 psrperf = 0;
2645 u32 stat[3];
2646 enum pipe pipe;
2647 bool enabled = false;
2648
2649 if (!HAS_PSR(dev)) {
2650 seq_puts(m, "PSR not supported\n");
2651 return 0;
2652 }
2653
2654 intel_runtime_pm_get(dev_priv);
2655
2656 mutex_lock(&dev_priv->psr.lock);
2657 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2658 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2659 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2660 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2661 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2662 dev_priv->psr.busy_frontbuffer_bits);
2663 seq_printf(m, "Re-enable work scheduled: %s\n",
2664 yesno(work_busy(&dev_priv->psr.work.work)));
2665
2666 if (HAS_DDI(dev))
2667 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2668 else {
2669 for_each_pipe(dev_priv, pipe) {
2670 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2671 VLV_EDP_PSR_CURR_STATE_MASK;
2672 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2673 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2674 enabled = true;
2675 }
2676 }
2677
2678 seq_printf(m, "Main link in standby mode: %s\n",
2679 yesno(dev_priv->psr.link_standby));
2680
2681 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2682
2683 if (!HAS_DDI(dev))
2684 for_each_pipe(dev_priv, pipe) {
2685 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2686 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2687 seq_printf(m, " pipe %c", pipe_name(pipe));
2688 }
2689 seq_puts(m, "\n");
2690
2691 /*
2692 * VLV/CHV PSR has no kind of performance counter
2693 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2694 */
2695 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2696 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2697 EDP_PSR_PERF_CNT_MASK;
2698
2699 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2700 }
2701 mutex_unlock(&dev_priv->psr.lock);
2702
2703 intel_runtime_pm_put(dev_priv);
2704 return 0;
2705 }
2706
2707 static int i915_sink_crc(struct seq_file *m, void *data)
2708 {
2709 struct drm_info_node *node = m->private;
2710 struct drm_device *dev = node->minor->dev;
2711 struct intel_connector *connector;
2712 struct intel_dp *intel_dp = NULL;
2713 int ret;
2714 u8 crc[6];
2715
2716 drm_modeset_lock_all(dev);
2717 for_each_intel_connector(dev, connector) {
2718 struct drm_crtc *crtc;
2719
2720 if (!connector->base.state->best_encoder)
2721 continue;
2722
2723 crtc = connector->base.state->crtc;
2724 if (!crtc->state->active)
2725 continue;
2726
2727 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
2728 continue;
2729
2730 intel_dp = enc_to_intel_dp(connector->base.state->best_encoder);
2731
2732 ret = intel_dp_sink_crc(intel_dp, crc);
2733 if (ret)
2734 goto out;
2735
2736 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2737 crc[0], crc[1], crc[2],
2738 crc[3], crc[4], crc[5]);
2739 goto out;
2740 }
2741 ret = -ENODEV;
2742 out:
2743 drm_modeset_unlock_all(dev);
2744 return ret;
2745 }
2746
2747 static int i915_energy_uJ(struct seq_file *m, void *data)
2748 {
2749 struct drm_info_node *node = m->private;
2750 struct drm_device *dev = node->minor->dev;
2751 struct drm_i915_private *dev_priv = to_i915(dev);
2752 u64 power;
2753 u32 units;
2754
2755 if (INTEL_INFO(dev)->gen < 6)
2756 return -ENODEV;
2757
2758 intel_runtime_pm_get(dev_priv);
2759
2760 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2761 power = (power & 0x1f00) >> 8;
2762 units = 1000000 / (1 << power); /* convert to uJ */
2763 power = I915_READ(MCH_SECP_NRG_STTS);
2764 power *= units;
2765
2766 intel_runtime_pm_put(dev_priv);
2767
2768 seq_printf(m, "%llu", (long long unsigned)power);
2769
2770 return 0;
2771 }
2772
2773 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2774 {
2775 struct drm_info_node *node = m->private;
2776 struct drm_device *dev = node->minor->dev;
2777 struct drm_i915_private *dev_priv = to_i915(dev);
2778
2779 if (!HAS_RUNTIME_PM(dev_priv))
2780 seq_puts(m, "Runtime power management not supported\n");
2781
2782 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
2783 seq_printf(m, "IRQs disabled: %s\n",
2784 yesno(!intel_irqs_enabled(dev_priv)));
2785 #ifdef CONFIG_PM
2786 seq_printf(m, "Usage count: %d\n",
2787 atomic_read(&dev->dev->power.usage_count));
2788 #else
2789 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2790 #endif
2791 seq_printf(m, "PCI device power state: %s [%d]\n",
2792 pci_power_name(dev_priv->drm.pdev->current_state),
2793 dev_priv->drm.pdev->current_state);
2794
2795 return 0;
2796 }
2797
2798 static int i915_power_domain_info(struct seq_file *m, void *unused)
2799 {
2800 struct drm_info_node *node = m->private;
2801 struct drm_device *dev = node->minor->dev;
2802 struct drm_i915_private *dev_priv = to_i915(dev);
2803 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2804 int i;
2805
2806 mutex_lock(&power_domains->lock);
2807
2808 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2809 for (i = 0; i < power_domains->power_well_count; i++) {
2810 struct i915_power_well *power_well;
2811 enum intel_display_power_domain power_domain;
2812
2813 power_well = &power_domains->power_wells[i];
2814 seq_printf(m, "%-25s %d\n", power_well->name,
2815 power_well->count);
2816
2817 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2818 power_domain++) {
2819 if (!(BIT(power_domain) & power_well->domains))
2820 continue;
2821
2822 seq_printf(m, " %-23s %d\n",
2823 intel_display_power_domain_str(power_domain),
2824 power_domains->domain_use_count[power_domain]);
2825 }
2826 }
2827
2828 mutex_unlock(&power_domains->lock);
2829
2830 return 0;
2831 }
2832
2833 static int i915_dmc_info(struct seq_file *m, void *unused)
2834 {
2835 struct drm_info_node *node = m->private;
2836 struct drm_device *dev = node->minor->dev;
2837 struct drm_i915_private *dev_priv = to_i915(dev);
2838 struct intel_csr *csr;
2839
2840 if (!HAS_CSR(dev)) {
2841 seq_puts(m, "not supported\n");
2842 return 0;
2843 }
2844
2845 csr = &dev_priv->csr;
2846
2847 intel_runtime_pm_get(dev_priv);
2848
2849 seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2850 seq_printf(m, "path: %s\n", csr->fw_path);
2851
2852 if (!csr->dmc_payload)
2853 goto out;
2854
2855 seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2856 CSR_VERSION_MINOR(csr->version));
2857
2858 if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
2859 seq_printf(m, "DC3 -> DC5 count: %d\n",
2860 I915_READ(SKL_CSR_DC3_DC5_COUNT));
2861 seq_printf(m, "DC5 -> DC6 count: %d\n",
2862 I915_READ(SKL_CSR_DC5_DC6_COUNT));
2863 } else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) {
2864 seq_printf(m, "DC3 -> DC5 count: %d\n",
2865 I915_READ(BXT_CSR_DC3_DC5_COUNT));
2866 }
2867
2868 out:
2869 seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2870 seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2871 seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2872
2873 intel_runtime_pm_put(dev_priv);
2874
2875 return 0;
2876 }
2877
2878 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2879 struct drm_display_mode *mode)
2880 {
2881 int i;
2882
2883 for (i = 0; i < tabs; i++)
2884 seq_putc(m, '\t');
2885
2886 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2887 mode->base.id, mode->name,
2888 mode->vrefresh, mode->clock,
2889 mode->hdisplay, mode->hsync_start,
2890 mode->hsync_end, mode->htotal,
2891 mode->vdisplay, mode->vsync_start,
2892 mode->vsync_end, mode->vtotal,
2893 mode->type, mode->flags);
2894 }
2895
2896 static void intel_encoder_info(struct seq_file *m,
2897 struct intel_crtc *intel_crtc,
2898 struct intel_encoder *intel_encoder)
2899 {
2900 struct drm_info_node *node = m->private;
2901 struct drm_device *dev = node->minor->dev;
2902 struct drm_crtc *crtc = &intel_crtc->base;
2903 struct intel_connector *intel_connector;
2904 struct drm_encoder *encoder;
2905
2906 encoder = &intel_encoder->base;
2907 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2908 encoder->base.id, encoder->name);
2909 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2910 struct drm_connector *connector = &intel_connector->base;
2911 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2912 connector->base.id,
2913 connector->name,
2914 drm_get_connector_status_name(connector->status));
2915 if (connector->status == connector_status_connected) {
2916 struct drm_display_mode *mode = &crtc->mode;
2917 seq_printf(m, ", mode:\n");
2918 intel_seq_print_mode(m, 2, mode);
2919 } else {
2920 seq_putc(m, '\n');
2921 }
2922 }
2923 }
2924
2925 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2926 {
2927 struct drm_info_node *node = m->private;
2928 struct drm_device *dev = node->minor->dev;
2929 struct drm_crtc *crtc = &intel_crtc->base;
2930 struct intel_encoder *intel_encoder;
2931 struct drm_plane_state *plane_state = crtc->primary->state;
2932 struct drm_framebuffer *fb = plane_state->fb;
2933
2934 if (fb)
2935 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2936 fb->base.id, plane_state->src_x >> 16,
2937 plane_state->src_y >> 16, fb->width, fb->height);
2938 else
2939 seq_puts(m, "\tprimary plane disabled\n");
2940 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2941 intel_encoder_info(m, intel_crtc, intel_encoder);
2942 }
2943
2944 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2945 {
2946 struct drm_display_mode *mode = panel->fixed_mode;
2947
2948 seq_printf(m, "\tfixed mode:\n");
2949 intel_seq_print_mode(m, 2, mode);
2950 }
2951
2952 static void intel_dp_info(struct seq_file *m,
2953 struct intel_connector *intel_connector)
2954 {
2955 struct intel_encoder *intel_encoder = intel_connector->encoder;
2956 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2957
2958 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2959 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2960 if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
2961 intel_panel_info(m, &intel_connector->panel);
2962 }
2963
2964 static void intel_hdmi_info(struct seq_file *m,
2965 struct intel_connector *intel_connector)
2966 {
2967 struct intel_encoder *intel_encoder = intel_connector->encoder;
2968 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2969
2970 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2971 }
2972
2973 static void intel_lvds_info(struct seq_file *m,
2974 struct intel_connector *intel_connector)
2975 {
2976 intel_panel_info(m, &intel_connector->panel);
2977 }
2978
2979 static void intel_connector_info(struct seq_file *m,
2980 struct drm_connector *connector)
2981 {
2982 struct intel_connector *intel_connector = to_intel_connector(connector);
2983 struct intel_encoder *intel_encoder = intel_connector->encoder;
2984 struct drm_display_mode *mode;
2985
2986 seq_printf(m, "connector %d: type %s, status: %s\n",
2987 connector->base.id, connector->name,
2988 drm_get_connector_status_name(connector->status));
2989 if (connector->status == connector_status_connected) {
2990 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2991 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2992 connector->display_info.width_mm,
2993 connector->display_info.height_mm);
2994 seq_printf(m, "\tsubpixel order: %s\n",
2995 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2996 seq_printf(m, "\tCEA rev: %d\n",
2997 connector->display_info.cea_rev);
2998 }
2999
3000 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3001 return;
3002
3003 switch (connector->connector_type) {
3004 case DRM_MODE_CONNECTOR_DisplayPort:
3005 case DRM_MODE_CONNECTOR_eDP:
3006 intel_dp_info(m, intel_connector);
3007 break;
3008 case DRM_MODE_CONNECTOR_LVDS:
3009 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
3010 intel_lvds_info(m, intel_connector);
3011 break;
3012 case DRM_MODE_CONNECTOR_HDMIA:
3013 if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
3014 intel_encoder->type == INTEL_OUTPUT_UNKNOWN)
3015 intel_hdmi_info(m, intel_connector);
3016 break;
3017 default:
3018 break;
3019 }
3020
3021 seq_printf(m, "\tmodes:\n");
3022 list_for_each_entry(mode, &connector->modes, head)
3023 intel_seq_print_mode(m, 2, mode);
3024 }
3025
3026 static bool cursor_active(struct drm_device *dev, int pipe)
3027 {
3028 struct drm_i915_private *dev_priv = to_i915(dev);
3029 u32 state;
3030
3031 if (IS_845G(dev) || IS_I865G(dev))
3032 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
3033 else
3034 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
3035
3036 return state;
3037 }
3038
3039 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
3040 {
3041 struct drm_i915_private *dev_priv = to_i915(dev);
3042 u32 pos;
3043
3044 pos = I915_READ(CURPOS(pipe));
3045
3046 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
3047 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
3048 *x = -*x;
3049
3050 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
3051 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
3052 *y = -*y;
3053
3054 return cursor_active(dev, pipe);
3055 }
3056
3057 static const char *plane_type(enum drm_plane_type type)
3058 {
3059 switch (type) {
3060 case DRM_PLANE_TYPE_OVERLAY:
3061 return "OVL";
3062 case DRM_PLANE_TYPE_PRIMARY:
3063 return "PRI";
3064 case DRM_PLANE_TYPE_CURSOR:
3065 return "CUR";
3066 /*
3067 * Deliberately omitting default: to generate compiler warnings
3068 * when a new drm_plane_type gets added.
3069 */
3070 }
3071
3072 return "unknown";
3073 }
3074
3075 static const char *plane_rotation(unsigned int rotation)
3076 {
3077 static char buf[48];
3078 /*
3079 * According to doc only one DRM_ROTATE_ is allowed but this
3080 * will print them all to visualize if the values are misused
3081 */
3082 snprintf(buf, sizeof(buf),
3083 "%s%s%s%s%s%s(0x%08x)",
3084 (rotation & BIT(DRM_ROTATE_0)) ? "0 " : "",
3085 (rotation & BIT(DRM_ROTATE_90)) ? "90 " : "",
3086 (rotation & BIT(DRM_ROTATE_180)) ? "180 " : "",
3087 (rotation & BIT(DRM_ROTATE_270)) ? "270 " : "",
3088 (rotation & BIT(DRM_REFLECT_X)) ? "FLIPX " : "",
3089 (rotation & BIT(DRM_REFLECT_Y)) ? "FLIPY " : "",
3090 rotation);
3091
3092 return buf;
3093 }
3094
3095 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3096 {
3097 struct drm_info_node *node = m->private;
3098 struct drm_device *dev = node->minor->dev;
3099 struct intel_plane *intel_plane;
3100
3101 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3102 struct drm_plane_state *state;
3103 struct drm_plane *plane = &intel_plane->base;
3104
3105 if (!plane->state) {
3106 seq_puts(m, "plane->state is NULL!\n");
3107 continue;
3108 }
3109
3110 state = plane->state;
3111
3112 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3113 plane->base.id,
3114 plane_type(intel_plane->base.type),
3115 state->crtc_x, state->crtc_y,
3116 state->crtc_w, state->crtc_h,
3117 (state->src_x >> 16),
3118 ((state->src_x & 0xffff) * 15625) >> 10,
3119 (state->src_y >> 16),
3120 ((state->src_y & 0xffff) * 15625) >> 10,
3121 (state->src_w >> 16),
3122 ((state->src_w & 0xffff) * 15625) >> 10,
3123 (state->src_h >> 16),
3124 ((state->src_h & 0xffff) * 15625) >> 10,
3125 state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A",
3126 plane_rotation(state->rotation));
3127 }
3128 }
3129
3130 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3131 {
3132 struct intel_crtc_state *pipe_config;
3133 int num_scalers = intel_crtc->num_scalers;
3134 int i;
3135
3136 pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3137
3138 /* Not all platformas have a scaler */
3139 if (num_scalers) {
3140 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3141 num_scalers,
3142 pipe_config->scaler_state.scaler_users,
3143 pipe_config->scaler_state.scaler_id);
3144
3145 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3146 struct intel_scaler *sc =
3147 &pipe_config->scaler_state.scalers[i];
3148
3149 seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3150 i, yesno(sc->in_use), sc->mode);
3151 }
3152 seq_puts(m, "\n");
3153 } else {
3154 seq_puts(m, "\tNo scalers available on this platform\n");
3155 }
3156 }
3157
3158 static int i915_display_info(struct seq_file *m, void *unused)
3159 {
3160 struct drm_info_node *node = m->private;
3161 struct drm_device *dev = node->minor->dev;
3162 struct drm_i915_private *dev_priv = to_i915(dev);
3163 struct intel_crtc *crtc;
3164 struct drm_connector *connector;
3165
3166 intel_runtime_pm_get(dev_priv);
3167 drm_modeset_lock_all(dev);
3168 seq_printf(m, "CRTC info\n");
3169 seq_printf(m, "---------\n");
3170 for_each_intel_crtc(dev, crtc) {
3171 bool active;
3172 struct intel_crtc_state *pipe_config;
3173 int x, y;
3174
3175 pipe_config = to_intel_crtc_state(crtc->base.state);
3176
3177 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3178 crtc->base.base.id, pipe_name(crtc->pipe),
3179 yesno(pipe_config->base.active),
3180 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3181 yesno(pipe_config->dither), pipe_config->pipe_bpp);
3182
3183 if (pipe_config->base.active) {
3184 intel_crtc_info(m, crtc);
3185
3186 active = cursor_position(dev, crtc->pipe, &x, &y);
3187 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3188 yesno(crtc->cursor_base),
3189 x, y, crtc->base.cursor->state->crtc_w,
3190 crtc->base.cursor->state->crtc_h,
3191 crtc->cursor_addr, yesno(active));
3192 intel_scaler_info(m, crtc);
3193 intel_plane_info(m, crtc);
3194 }
3195
3196 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3197 yesno(!crtc->cpu_fifo_underrun_disabled),
3198 yesno(!crtc->pch_fifo_underrun_disabled));
3199 }
3200
3201 seq_printf(m, "\n");
3202 seq_printf(m, "Connector info\n");
3203 seq_printf(m, "--------------\n");
3204 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3205 intel_connector_info(m, connector);
3206 }
3207 drm_modeset_unlock_all(dev);
3208 intel_runtime_pm_put(dev_priv);
3209
3210 return 0;
3211 }
3212
3213 static int i915_semaphore_status(struct seq_file *m, void *unused)
3214 {
3215 struct drm_info_node *node = (struct drm_info_node *) m->private;
3216 struct drm_device *dev = node->minor->dev;
3217 struct drm_i915_private *dev_priv = to_i915(dev);
3218 struct intel_engine_cs *engine;
3219 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
3220 enum intel_engine_id id;
3221 int j, ret;
3222
3223 if (!i915_semaphore_is_enabled(dev_priv)) {
3224 seq_puts(m, "Semaphores are disabled\n");
3225 return 0;
3226 }
3227
3228 ret = mutex_lock_interruptible(&dev->struct_mutex);
3229 if (ret)
3230 return ret;
3231 intel_runtime_pm_get(dev_priv);
3232
3233 if (IS_BROADWELL(dev)) {
3234 struct page *page;
3235 uint64_t *seqno;
3236
3237 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
3238
3239 seqno = (uint64_t *)kmap_atomic(page);
3240 for_each_engine_id(engine, dev_priv, id) {
3241 uint64_t offset;
3242
3243 seq_printf(m, "%s\n", engine->name);
3244
3245 seq_puts(m, " Last signal:");
3246 for (j = 0; j < num_rings; j++) {
3247 offset = id * I915_NUM_ENGINES + j;
3248 seq_printf(m, "0x%08llx (0x%02llx) ",
3249 seqno[offset], offset * 8);
3250 }
3251 seq_putc(m, '\n');
3252
3253 seq_puts(m, " Last wait: ");
3254 for (j = 0; j < num_rings; j++) {
3255 offset = id + (j * I915_NUM_ENGINES);
3256 seq_printf(m, "0x%08llx (0x%02llx) ",
3257 seqno[offset], offset * 8);
3258 }
3259 seq_putc(m, '\n');
3260
3261 }
3262 kunmap_atomic(seqno);
3263 } else {
3264 seq_puts(m, " Last signal:");
3265 for_each_engine(engine, dev_priv)
3266 for (j = 0; j < num_rings; j++)
3267 seq_printf(m, "0x%08x\n",
3268 I915_READ(engine->semaphore.mbox.signal[j]));
3269 seq_putc(m, '\n');
3270 }
3271
3272 seq_puts(m, "\nSync seqno:\n");
3273 for_each_engine(engine, dev_priv) {
3274 for (j = 0; j < num_rings; j++)
3275 seq_printf(m, " 0x%08x ",
3276 engine->semaphore.sync_seqno[j]);
3277 seq_putc(m, '\n');
3278 }
3279 seq_putc(m, '\n');
3280
3281 intel_runtime_pm_put(dev_priv);
3282 mutex_unlock(&dev->struct_mutex);
3283 return 0;
3284 }
3285
3286 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3287 {
3288 struct drm_info_node *node = (struct drm_info_node *) m->private;
3289 struct drm_device *dev = node->minor->dev;
3290 struct drm_i915_private *dev_priv = to_i915(dev);
3291 int i;
3292
3293 drm_modeset_lock_all(dev);
3294 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3295 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3296
3297 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3298 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3299 pll->config.crtc_mask, pll->active_mask, yesno(pll->on));
3300 seq_printf(m, " tracked hardware state:\n");
3301 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
3302 seq_printf(m, " dpll_md: 0x%08x\n",
3303 pll->config.hw_state.dpll_md);
3304 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
3305 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
3306 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
3307 }
3308 drm_modeset_unlock_all(dev);
3309
3310 return 0;
3311 }
3312
3313 static int i915_wa_registers(struct seq_file *m, void *unused)
3314 {
3315 int i;
3316 int ret;
3317 struct intel_engine_cs *engine;
3318 struct drm_info_node *node = (struct drm_info_node *) m->private;
3319 struct drm_device *dev = node->minor->dev;
3320 struct drm_i915_private *dev_priv = to_i915(dev);
3321 struct i915_workarounds *workarounds = &dev_priv->workarounds;
3322 enum intel_engine_id id;
3323
3324 ret = mutex_lock_interruptible(&dev->struct_mutex);
3325 if (ret)
3326 return ret;
3327
3328 intel_runtime_pm_get(dev_priv);
3329
3330 seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3331 for_each_engine_id(engine, dev_priv, id)
3332 seq_printf(m, "HW whitelist count for %s: %d\n",
3333 engine->name, workarounds->hw_whitelist_count[id]);
3334 for (i = 0; i < workarounds->count; ++i) {
3335 i915_reg_t addr;
3336 u32 mask, value, read;
3337 bool ok;
3338
3339 addr = workarounds->reg[i].addr;
3340 mask = workarounds->reg[i].mask;
3341 value = workarounds->reg[i].value;
3342 read = I915_READ(addr);
3343 ok = (value & mask) == (read & mask);
3344 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3345 i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3346 }
3347
3348 intel_runtime_pm_put(dev_priv);
3349 mutex_unlock(&dev->struct_mutex);
3350
3351 return 0;
3352 }
3353
3354 static int i915_ddb_info(struct seq_file *m, void *unused)
3355 {
3356 struct drm_info_node *node = m->private;
3357 struct drm_device *dev = node->minor->dev;
3358 struct drm_i915_private *dev_priv = to_i915(dev);
3359 struct skl_ddb_allocation *ddb;
3360 struct skl_ddb_entry *entry;
3361 enum pipe pipe;
3362 int plane;
3363
3364 if (INTEL_INFO(dev)->gen < 9)
3365 return 0;
3366
3367 drm_modeset_lock_all(dev);
3368
3369 ddb = &dev_priv->wm.skl_hw.ddb;
3370
3371 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3372
3373 for_each_pipe(dev_priv, pipe) {
3374 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3375
3376 for_each_plane(dev_priv, pipe, plane) {
3377 entry = &ddb->plane[pipe][plane];
3378 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
3379 entry->start, entry->end,
3380 skl_ddb_entry_size(entry));
3381 }
3382
3383 entry = &ddb->plane[pipe][PLANE_CURSOR];
3384 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
3385 entry->end, skl_ddb_entry_size(entry));
3386 }
3387
3388 drm_modeset_unlock_all(dev);
3389
3390 return 0;
3391 }
3392
3393 static void drrs_status_per_crtc(struct seq_file *m,
3394 struct drm_device *dev, struct intel_crtc *intel_crtc)
3395 {
3396 struct drm_i915_private *dev_priv = to_i915(dev);
3397 struct i915_drrs *drrs = &dev_priv->drrs;
3398 int vrefresh = 0;
3399 struct drm_connector *connector;
3400
3401 drm_for_each_connector(connector, dev) {
3402 if (connector->state->crtc != &intel_crtc->base)
3403 continue;
3404
3405 seq_printf(m, "%s:\n", connector->name);
3406 }
3407
3408 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3409 seq_puts(m, "\tVBT: DRRS_type: Static");
3410 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3411 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3412 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3413 seq_puts(m, "\tVBT: DRRS_type: None");
3414 else
3415 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3416
3417 seq_puts(m, "\n\n");
3418
3419 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3420 struct intel_panel *panel;
3421
3422 mutex_lock(&drrs->mutex);
3423 /* DRRS Supported */
3424 seq_puts(m, "\tDRRS Supported: Yes\n");
3425
3426 /* disable_drrs() will make drrs->dp NULL */
3427 if (!drrs->dp) {
3428 seq_puts(m, "Idleness DRRS: Disabled");
3429 mutex_unlock(&drrs->mutex);
3430 return;
3431 }
3432
3433 panel = &drrs->dp->attached_connector->panel;
3434 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3435 drrs->busy_frontbuffer_bits);
3436
3437 seq_puts(m, "\n\t\t");
3438 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3439 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3440 vrefresh = panel->fixed_mode->vrefresh;
3441 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3442 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3443 vrefresh = panel->downclock_mode->vrefresh;
3444 } else {
3445 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3446 drrs->refresh_rate_type);
3447 mutex_unlock(&drrs->mutex);
3448 return;
3449 }
3450 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3451
3452 seq_puts(m, "\n\t\t");
3453 mutex_unlock(&drrs->mutex);
3454 } else {
3455 /* DRRS not supported. Print the VBT parameter*/
3456 seq_puts(m, "\tDRRS Supported : No");
3457 }
3458 seq_puts(m, "\n");
3459 }
3460
3461 static int i915_drrs_status(struct seq_file *m, void *unused)
3462 {
3463 struct drm_info_node *node = m->private;
3464 struct drm_device *dev = node->minor->dev;
3465 struct intel_crtc *intel_crtc;
3466 int active_crtc_cnt = 0;
3467
3468 drm_modeset_lock_all(dev);
3469 for_each_intel_crtc(dev, intel_crtc) {
3470 if (intel_crtc->base.state->active) {
3471 active_crtc_cnt++;
3472 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3473
3474 drrs_status_per_crtc(m, dev, intel_crtc);
3475 }
3476 }
3477 drm_modeset_unlock_all(dev);
3478
3479 if (!active_crtc_cnt)
3480 seq_puts(m, "No active crtc found\n");
3481
3482 return 0;
3483 }
3484
3485 struct pipe_crc_info {
3486 const char *name;
3487 struct drm_device *dev;
3488 enum pipe pipe;
3489 };
3490
3491 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3492 {
3493 struct drm_info_node *node = (struct drm_info_node *) m->private;
3494 struct drm_device *dev = node->minor->dev;
3495 struct intel_encoder *intel_encoder;
3496 struct intel_digital_port *intel_dig_port;
3497 struct drm_connector *connector;
3498
3499 drm_modeset_lock_all(dev);
3500 drm_for_each_connector(connector, dev) {
3501 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3502 continue;
3503
3504 intel_encoder = intel_attached_encoder(connector);
3505 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3506 continue;
3507
3508 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
3509 if (!intel_dig_port->dp.can_mst)
3510 continue;
3511
3512 seq_printf(m, "MST Source Port %c\n",
3513 port_name(intel_dig_port->port));
3514 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3515 }
3516 drm_modeset_unlock_all(dev);
3517 return 0;
3518 }
3519
3520 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3521 {
3522 struct pipe_crc_info *info = inode->i_private;
3523 struct drm_i915_private *dev_priv = to_i915(info->dev);
3524 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3525
3526 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3527 return -ENODEV;
3528
3529 spin_lock_irq(&pipe_crc->lock);
3530
3531 if (pipe_crc->opened) {
3532 spin_unlock_irq(&pipe_crc->lock);
3533 return -EBUSY; /* already open */
3534 }
3535
3536 pipe_crc->opened = true;
3537 filep->private_data = inode->i_private;
3538
3539 spin_unlock_irq(&pipe_crc->lock);
3540
3541 return 0;
3542 }
3543
3544 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3545 {
3546 struct pipe_crc_info *info = inode->i_private;
3547 struct drm_i915_private *dev_priv = to_i915(info->dev);
3548 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3549
3550 spin_lock_irq(&pipe_crc->lock);
3551 pipe_crc->opened = false;
3552 spin_unlock_irq(&pipe_crc->lock);
3553
3554 return 0;
3555 }
3556
3557 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3558 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3559 /* account for \'0' */
3560 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3561
3562 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3563 {
3564 assert_spin_locked(&pipe_crc->lock);
3565 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3566 INTEL_PIPE_CRC_ENTRIES_NR);
3567 }
3568
3569 static ssize_t
3570 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3571 loff_t *pos)
3572 {
3573 struct pipe_crc_info *info = filep->private_data;
3574 struct drm_device *dev = info->dev;
3575 struct drm_i915_private *dev_priv = to_i915(dev);
3576 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3577 char buf[PIPE_CRC_BUFFER_LEN];
3578 int n_entries;
3579 ssize_t bytes_read;
3580
3581 /*
3582 * Don't allow user space to provide buffers not big enough to hold
3583 * a line of data.
3584 */
3585 if (count < PIPE_CRC_LINE_LEN)
3586 return -EINVAL;
3587
3588 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3589 return 0;
3590
3591 /* nothing to read */
3592 spin_lock_irq(&pipe_crc->lock);
3593 while (pipe_crc_data_count(pipe_crc) == 0) {
3594 int ret;
3595
3596 if (filep->f_flags & O_NONBLOCK) {
3597 spin_unlock_irq(&pipe_crc->lock);
3598 return -EAGAIN;
3599 }
3600
3601 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3602 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3603 if (ret) {
3604 spin_unlock_irq(&pipe_crc->lock);
3605 return ret;
3606 }
3607 }
3608
3609 /* We now have one or more entries to read */
3610 n_entries = count / PIPE_CRC_LINE_LEN;
3611
3612 bytes_read = 0;
3613 while (n_entries > 0) {
3614 struct intel_pipe_crc_entry *entry =
3615 &pipe_crc->entries[pipe_crc->tail];
3616 int ret;
3617
3618 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3619 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3620 break;
3621
3622 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3623 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3624
3625 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3626 "%8u %8x %8x %8x %8x %8x\n",
3627 entry->frame, entry->crc[0],
3628 entry->crc[1], entry->crc[2],
3629 entry->crc[3], entry->crc[4]);
3630
3631 spin_unlock_irq(&pipe_crc->lock);
3632
3633 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
3634 if (ret == PIPE_CRC_LINE_LEN)
3635 return -EFAULT;
3636
3637 user_buf += PIPE_CRC_LINE_LEN;
3638 n_entries--;
3639
3640 spin_lock_irq(&pipe_crc->lock);
3641 }
3642
3643 spin_unlock_irq(&pipe_crc->lock);
3644
3645 return bytes_read;
3646 }
3647
3648 static const struct file_operations i915_pipe_crc_fops = {
3649 .owner = THIS_MODULE,
3650 .open = i915_pipe_crc_open,
3651 .read = i915_pipe_crc_read,
3652 .release = i915_pipe_crc_release,
3653 };
3654
3655 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3656 {
3657 .name = "i915_pipe_A_crc",
3658 .pipe = PIPE_A,
3659 },
3660 {
3661 .name = "i915_pipe_B_crc",
3662 .pipe = PIPE_B,
3663 },
3664 {
3665 .name = "i915_pipe_C_crc",
3666 .pipe = PIPE_C,
3667 },
3668 };
3669
3670 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3671 enum pipe pipe)
3672 {
3673 struct drm_device *dev = minor->dev;
3674 struct dentry *ent;
3675 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3676
3677 info->dev = dev;
3678 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3679 &i915_pipe_crc_fops);
3680 if (!ent)
3681 return -ENOMEM;
3682
3683 return drm_add_fake_info_node(minor, ent, info);
3684 }
3685
3686 static const char * const pipe_crc_sources[] = {
3687 "none",
3688 "plane1",
3689 "plane2",
3690 "pf",
3691 "pipe",
3692 "TV",
3693 "DP-B",
3694 "DP-C",
3695 "DP-D",
3696 "auto",
3697 };
3698
3699 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3700 {
3701 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3702 return pipe_crc_sources[source];
3703 }
3704
3705 static int display_crc_ctl_show(struct seq_file *m, void *data)
3706 {
3707 struct drm_device *dev = m->private;
3708 struct drm_i915_private *dev_priv = to_i915(dev);
3709 int i;
3710
3711 for (i = 0; i < I915_MAX_PIPES; i++)
3712 seq_printf(m, "%c %s\n", pipe_name(i),
3713 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3714
3715 return 0;
3716 }
3717
3718 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3719 {
3720 struct drm_device *dev = inode->i_private;
3721
3722 return single_open(file, display_crc_ctl_show, dev);
3723 }
3724
3725 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3726 uint32_t *val)
3727 {
3728 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3729 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3730
3731 switch (*source) {
3732 case INTEL_PIPE_CRC_SOURCE_PIPE:
3733 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3734 break;
3735 case INTEL_PIPE_CRC_SOURCE_NONE:
3736 *val = 0;
3737 break;
3738 default:
3739 return -EINVAL;
3740 }
3741
3742 return 0;
3743 }
3744
3745 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3746 enum intel_pipe_crc_source *source)
3747 {
3748 struct intel_encoder *encoder;
3749 struct intel_crtc *crtc;
3750 struct intel_digital_port *dig_port;
3751 int ret = 0;
3752
3753 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3754
3755 drm_modeset_lock_all(dev);
3756 for_each_intel_encoder(dev, encoder) {
3757 if (!encoder->base.crtc)
3758 continue;
3759
3760 crtc = to_intel_crtc(encoder->base.crtc);
3761
3762 if (crtc->pipe != pipe)
3763 continue;
3764
3765 switch (encoder->type) {
3766 case INTEL_OUTPUT_TVOUT:
3767 *source = INTEL_PIPE_CRC_SOURCE_TV;
3768 break;
3769 case INTEL_OUTPUT_DP:
3770 case INTEL_OUTPUT_EDP:
3771 dig_port = enc_to_dig_port(&encoder->base);
3772 switch (dig_port->port) {
3773 case PORT_B:
3774 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3775 break;
3776 case PORT_C:
3777 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3778 break;
3779 case PORT_D:
3780 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3781 break;
3782 default:
3783 WARN(1, "nonexisting DP port %c\n",
3784 port_name(dig_port->port));
3785 break;
3786 }
3787 break;
3788 default:
3789 break;
3790 }
3791 }
3792 drm_modeset_unlock_all(dev);
3793
3794 return ret;
3795 }
3796
3797 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3798 enum pipe pipe,
3799 enum intel_pipe_crc_source *source,
3800 uint32_t *val)
3801 {
3802 struct drm_i915_private *dev_priv = to_i915(dev);
3803 bool need_stable_symbols = false;
3804
3805 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3806 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3807 if (ret)
3808 return ret;
3809 }
3810
3811 switch (*source) {
3812 case INTEL_PIPE_CRC_SOURCE_PIPE:
3813 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3814 break;
3815 case INTEL_PIPE_CRC_SOURCE_DP_B:
3816 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3817 need_stable_symbols = true;
3818 break;
3819 case INTEL_PIPE_CRC_SOURCE_DP_C:
3820 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3821 need_stable_symbols = true;
3822 break;
3823 case INTEL_PIPE_CRC_SOURCE_DP_D:
3824 if (!IS_CHERRYVIEW(dev))
3825 return -EINVAL;
3826 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3827 need_stable_symbols = true;
3828 break;
3829 case INTEL_PIPE_CRC_SOURCE_NONE:
3830 *val = 0;
3831 break;
3832 default:
3833 return -EINVAL;
3834 }
3835
3836 /*
3837 * When the pipe CRC tap point is after the transcoders we need
3838 * to tweak symbol-level features to produce a deterministic series of
3839 * symbols for a given frame. We need to reset those features only once
3840 * a frame (instead of every nth symbol):
3841 * - DC-balance: used to ensure a better clock recovery from the data
3842 * link (SDVO)
3843 * - DisplayPort scrambling: used for EMI reduction
3844 */
3845 if (need_stable_symbols) {
3846 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3847
3848 tmp |= DC_BALANCE_RESET_VLV;
3849 switch (pipe) {
3850 case PIPE_A:
3851 tmp |= PIPE_A_SCRAMBLE_RESET;
3852 break;
3853 case PIPE_B:
3854 tmp |= PIPE_B_SCRAMBLE_RESET;
3855 break;
3856 case PIPE_C:
3857 tmp |= PIPE_C_SCRAMBLE_RESET;
3858 break;
3859 default:
3860 return -EINVAL;
3861 }
3862 I915_WRITE(PORT_DFT2_G4X, tmp);
3863 }
3864
3865 return 0;
3866 }
3867
3868 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3869 enum pipe pipe,
3870 enum intel_pipe_crc_source *source,
3871 uint32_t *val)
3872 {
3873 struct drm_i915_private *dev_priv = to_i915(dev);
3874 bool need_stable_symbols = false;
3875
3876 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3877 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3878 if (ret)
3879 return ret;
3880 }
3881
3882 switch (*source) {
3883 case INTEL_PIPE_CRC_SOURCE_PIPE:
3884 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3885 break;
3886 case INTEL_PIPE_CRC_SOURCE_TV:
3887 if (!SUPPORTS_TV(dev))
3888 return -EINVAL;
3889 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3890 break;
3891 case INTEL_PIPE_CRC_SOURCE_DP_B:
3892 if (!IS_G4X(dev))
3893 return -EINVAL;
3894 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3895 need_stable_symbols = true;
3896 break;
3897 case INTEL_PIPE_CRC_SOURCE_DP_C:
3898 if (!IS_G4X(dev))
3899 return -EINVAL;
3900 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3901 need_stable_symbols = true;
3902 break;
3903 case INTEL_PIPE_CRC_SOURCE_DP_D:
3904 if (!IS_G4X(dev))
3905 return -EINVAL;
3906 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3907 need_stable_symbols = true;
3908 break;
3909 case INTEL_PIPE_CRC_SOURCE_NONE:
3910 *val = 0;
3911 break;
3912 default:
3913 return -EINVAL;
3914 }
3915
3916 /*
3917 * When the pipe CRC tap point is after the transcoders we need
3918 * to tweak symbol-level features to produce a deterministic series of
3919 * symbols for a given frame. We need to reset those features only once
3920 * a frame (instead of every nth symbol):
3921 * - DC-balance: used to ensure a better clock recovery from the data
3922 * link (SDVO)
3923 * - DisplayPort scrambling: used for EMI reduction
3924 */
3925 if (need_stable_symbols) {
3926 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3927
3928 WARN_ON(!IS_G4X(dev));
3929
3930 I915_WRITE(PORT_DFT_I9XX,
3931 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3932
3933 if (pipe == PIPE_A)
3934 tmp |= PIPE_A_SCRAMBLE_RESET;
3935 else
3936 tmp |= PIPE_B_SCRAMBLE_RESET;
3937
3938 I915_WRITE(PORT_DFT2_G4X, tmp);
3939 }
3940
3941 return 0;
3942 }
3943
3944 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3945 enum pipe pipe)
3946 {
3947 struct drm_i915_private *dev_priv = to_i915(dev);
3948 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3949
3950 switch (pipe) {
3951 case PIPE_A:
3952 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3953 break;
3954 case PIPE_B:
3955 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3956 break;
3957 case PIPE_C:
3958 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3959 break;
3960 default:
3961 return;
3962 }
3963 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3964 tmp &= ~DC_BALANCE_RESET_VLV;
3965 I915_WRITE(PORT_DFT2_G4X, tmp);
3966
3967 }
3968
3969 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3970 enum pipe pipe)
3971 {
3972 struct drm_i915_private *dev_priv = to_i915(dev);
3973 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3974
3975 if (pipe == PIPE_A)
3976 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3977 else
3978 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3979 I915_WRITE(PORT_DFT2_G4X, tmp);
3980
3981 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3982 I915_WRITE(PORT_DFT_I9XX,
3983 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3984 }
3985 }
3986
3987 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3988 uint32_t *val)
3989 {
3990 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3991 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3992
3993 switch (*source) {
3994 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3995 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3996 break;
3997 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3998 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3999 break;
4000 case INTEL_PIPE_CRC_SOURCE_PIPE:
4001 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
4002 break;
4003 case INTEL_PIPE_CRC_SOURCE_NONE:
4004 *val = 0;
4005 break;
4006 default:
4007 return -EINVAL;
4008 }
4009
4010 return 0;
4011 }
4012
4013 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
4014 {
4015 struct drm_i915_private *dev_priv = to_i915(dev);
4016 struct intel_crtc *crtc =
4017 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
4018 struct intel_crtc_state *pipe_config;
4019 struct drm_atomic_state *state;
4020 int ret = 0;
4021
4022 drm_modeset_lock_all(dev);
4023 state = drm_atomic_state_alloc(dev);
4024 if (!state) {
4025 ret = -ENOMEM;
4026 goto out;
4027 }
4028
4029 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
4030 pipe_config = intel_atomic_get_crtc_state(state, crtc);
4031 if (IS_ERR(pipe_config)) {
4032 ret = PTR_ERR(pipe_config);
4033 goto out;
4034 }
4035
4036 pipe_config->pch_pfit.force_thru = enable;
4037 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
4038 pipe_config->pch_pfit.enabled != enable)
4039 pipe_config->base.connectors_changed = true;
4040
4041 ret = drm_atomic_commit(state);
4042 out:
4043 drm_modeset_unlock_all(dev);
4044 WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
4045 if (ret)
4046 drm_atomic_state_free(state);
4047 }
4048
4049 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
4050 enum pipe pipe,
4051 enum intel_pipe_crc_source *source,
4052 uint32_t *val)
4053 {
4054 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
4055 *source = INTEL_PIPE_CRC_SOURCE_PF;
4056
4057 switch (*source) {
4058 case INTEL_PIPE_CRC_SOURCE_PLANE1:
4059 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
4060 break;
4061 case INTEL_PIPE_CRC_SOURCE_PLANE2:
4062 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
4063 break;
4064 case INTEL_PIPE_CRC_SOURCE_PF:
4065 if (IS_HASWELL(dev) && pipe == PIPE_A)
4066 hsw_trans_edp_pipe_A_crc_wa(dev, true);
4067
4068 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
4069 break;
4070 case INTEL_PIPE_CRC_SOURCE_NONE:
4071 *val = 0;
4072 break;
4073 default:
4074 return -EINVAL;
4075 }
4076
4077 return 0;
4078 }
4079
4080 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
4081 enum intel_pipe_crc_source source)
4082 {
4083 struct drm_i915_private *dev_priv = to_i915(dev);
4084 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4085 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
4086 pipe));
4087 enum intel_display_power_domain power_domain;
4088 u32 val = 0; /* shut up gcc */
4089 int ret;
4090
4091 if (pipe_crc->source == source)
4092 return 0;
4093
4094 /* forbid changing the source without going back to 'none' */
4095 if (pipe_crc->source && source)
4096 return -EINVAL;
4097
4098 power_domain = POWER_DOMAIN_PIPE(pipe);
4099 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
4100 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4101 return -EIO;
4102 }
4103
4104 if (IS_GEN2(dev))
4105 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
4106 else if (INTEL_INFO(dev)->gen < 5)
4107 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4108 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4109 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4110 else if (IS_GEN5(dev) || IS_GEN6(dev))
4111 ret = ilk_pipe_crc_ctl_reg(&source, &val);
4112 else
4113 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4114
4115 if (ret != 0)
4116 goto out;
4117
4118 /* none -> real source transition */
4119 if (source) {
4120 struct intel_pipe_crc_entry *entries;
4121
4122 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4123 pipe_name(pipe), pipe_crc_source_name(source));
4124
4125 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4126 sizeof(pipe_crc->entries[0]),
4127 GFP_KERNEL);
4128 if (!entries) {
4129 ret = -ENOMEM;
4130 goto out;
4131 }
4132
4133 /*
4134 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4135 * enabled and disabled dynamically based on package C states,
4136 * user space can't make reliable use of the CRCs, so let's just
4137 * completely disable it.
4138 */
4139 hsw_disable_ips(crtc);
4140
4141 spin_lock_irq(&pipe_crc->lock);
4142 kfree(pipe_crc->entries);
4143 pipe_crc->entries = entries;
4144 pipe_crc->head = 0;
4145 pipe_crc->tail = 0;
4146 spin_unlock_irq(&pipe_crc->lock);
4147 }
4148
4149 pipe_crc->source = source;
4150
4151 I915_WRITE(PIPE_CRC_CTL(pipe), val);
4152 POSTING_READ(PIPE_CRC_CTL(pipe));
4153
4154 /* real source -> none transition */
4155 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
4156 struct intel_pipe_crc_entry *entries;
4157 struct intel_crtc *crtc =
4158 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
4159
4160 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4161 pipe_name(pipe));
4162
4163 drm_modeset_lock(&crtc->base.mutex, NULL);
4164 if (crtc->base.state->active)
4165 intel_wait_for_vblank(dev, pipe);
4166 drm_modeset_unlock(&crtc->base.mutex);
4167
4168 spin_lock_irq(&pipe_crc->lock);
4169 entries = pipe_crc->entries;
4170 pipe_crc->entries = NULL;
4171 pipe_crc->head = 0;
4172 pipe_crc->tail = 0;
4173 spin_unlock_irq(&pipe_crc->lock);
4174
4175 kfree(entries);
4176
4177 if (IS_G4X(dev))
4178 g4x_undo_pipe_scramble_reset(dev, pipe);
4179 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4180 vlv_undo_pipe_scramble_reset(dev, pipe);
4181 else if (IS_HASWELL(dev) && pipe == PIPE_A)
4182 hsw_trans_edp_pipe_A_crc_wa(dev, false);
4183
4184 hsw_enable_ips(crtc);
4185 }
4186
4187 ret = 0;
4188
4189 out:
4190 intel_display_power_put(dev_priv, power_domain);
4191
4192 return ret;
4193 }
4194
4195 /*
4196 * Parse pipe CRC command strings:
4197 * command: wsp* object wsp+ name wsp+ source wsp*
4198 * object: 'pipe'
4199 * name: (A | B | C)
4200 * source: (none | plane1 | plane2 | pf)
4201 * wsp: (#0x20 | #0x9 | #0xA)+
4202 *
4203 * eg.:
4204 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
4205 * "pipe A none" -> Stop CRC
4206 */
4207 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
4208 {
4209 int n_words = 0;
4210
4211 while (*buf) {
4212 char *end;
4213
4214 /* skip leading white space */
4215 buf = skip_spaces(buf);
4216 if (!*buf)
4217 break; /* end of buffer */
4218
4219 /* find end of word */
4220 for (end = buf; *end && !isspace(*end); end++)
4221 ;
4222
4223 if (n_words == max_words) {
4224 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4225 max_words);
4226 return -EINVAL; /* ran out of words[] before bytes */
4227 }
4228
4229 if (*end)
4230 *end++ = '\0';
4231 words[n_words++] = buf;
4232 buf = end;
4233 }
4234
4235 return n_words;
4236 }
4237
4238 enum intel_pipe_crc_object {
4239 PIPE_CRC_OBJECT_PIPE,
4240 };
4241
4242 static const char * const pipe_crc_objects[] = {
4243 "pipe",
4244 };
4245
4246 static int
4247 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4248 {
4249 int i;
4250
4251 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4252 if (!strcmp(buf, pipe_crc_objects[i])) {
4253 *o = i;
4254 return 0;
4255 }
4256
4257 return -EINVAL;
4258 }
4259
4260 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4261 {
4262 const char name = buf[0];
4263
4264 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4265 return -EINVAL;
4266
4267 *pipe = name - 'A';
4268
4269 return 0;
4270 }
4271
4272 static int
4273 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4274 {
4275 int i;
4276
4277 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4278 if (!strcmp(buf, pipe_crc_sources[i])) {
4279 *s = i;
4280 return 0;
4281 }
4282
4283 return -EINVAL;
4284 }
4285
4286 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
4287 {
4288 #define N_WORDS 3
4289 int n_words;
4290 char *words[N_WORDS];
4291 enum pipe pipe;
4292 enum intel_pipe_crc_object object;
4293 enum intel_pipe_crc_source source;
4294
4295 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4296 if (n_words != N_WORDS) {
4297 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4298 N_WORDS);
4299 return -EINVAL;
4300 }
4301
4302 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4303 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4304 return -EINVAL;
4305 }
4306
4307 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4308 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4309 return -EINVAL;
4310 }
4311
4312 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4313 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4314 return -EINVAL;
4315 }
4316
4317 return pipe_crc_set_source(dev, pipe, source);
4318 }
4319
4320 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4321 size_t len, loff_t *offp)
4322 {
4323 struct seq_file *m = file->private_data;
4324 struct drm_device *dev = m->private;
4325 char *tmpbuf;
4326 int ret;
4327
4328 if (len == 0)
4329 return 0;
4330
4331 if (len > PAGE_SIZE - 1) {
4332 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4333 PAGE_SIZE);
4334 return -E2BIG;
4335 }
4336
4337 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4338 if (!tmpbuf)
4339 return -ENOMEM;
4340
4341 if (copy_from_user(tmpbuf, ubuf, len)) {
4342 ret = -EFAULT;
4343 goto out;
4344 }
4345 tmpbuf[len] = '\0';
4346
4347 ret = display_crc_ctl_parse(dev, tmpbuf, len);
4348
4349 out:
4350 kfree(tmpbuf);
4351 if (ret < 0)
4352 return ret;
4353
4354 *offp += len;
4355 return len;
4356 }
4357
4358 static const struct file_operations i915_display_crc_ctl_fops = {
4359 .owner = THIS_MODULE,
4360 .open = display_crc_ctl_open,
4361 .read = seq_read,
4362 .llseek = seq_lseek,
4363 .release = single_release,
4364 .write = display_crc_ctl_write
4365 };
4366
4367 static ssize_t i915_displayport_test_active_write(struct file *file,
4368 const char __user *ubuf,
4369 size_t len, loff_t *offp)
4370 {
4371 char *input_buffer;
4372 int status = 0;
4373 struct drm_device *dev;
4374 struct drm_connector *connector;
4375 struct list_head *connector_list;
4376 struct intel_dp *intel_dp;
4377 int val = 0;
4378
4379 dev = ((struct seq_file *)file->private_data)->private;
4380
4381 connector_list = &dev->mode_config.connector_list;
4382
4383 if (len == 0)
4384 return 0;
4385
4386 input_buffer = kmalloc(len + 1, GFP_KERNEL);
4387 if (!input_buffer)
4388 return -ENOMEM;
4389
4390 if (copy_from_user(input_buffer, ubuf, len)) {
4391 status = -EFAULT;
4392 goto out;
4393 }
4394
4395 input_buffer[len] = '\0';
4396 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4397
4398 list_for_each_entry(connector, connector_list, head) {
4399
4400 if (connector->connector_type !=
4401 DRM_MODE_CONNECTOR_DisplayPort)
4402 continue;
4403
4404 if (connector->status == connector_status_connected &&
4405 connector->encoder != NULL) {
4406 intel_dp = enc_to_intel_dp(connector->encoder);
4407 status = kstrtoint(input_buffer, 10, &val);
4408 if (status < 0)
4409 goto out;
4410 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4411 /* To prevent erroneous activation of the compliance
4412 * testing code, only accept an actual value of 1 here
4413 */
4414 if (val == 1)
4415 intel_dp->compliance_test_active = 1;
4416 else
4417 intel_dp->compliance_test_active = 0;
4418 }
4419 }
4420 out:
4421 kfree(input_buffer);
4422 if (status < 0)
4423 return status;
4424
4425 *offp += len;
4426 return len;
4427 }
4428
4429 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4430 {
4431 struct drm_device *dev = m->private;
4432 struct drm_connector *connector;
4433 struct list_head *connector_list = &dev->mode_config.connector_list;
4434 struct intel_dp *intel_dp;
4435
4436 list_for_each_entry(connector, connector_list, head) {
4437
4438 if (connector->connector_type !=
4439 DRM_MODE_CONNECTOR_DisplayPort)
4440 continue;
4441
4442 if (connector->status == connector_status_connected &&
4443 connector->encoder != NULL) {
4444 intel_dp = enc_to_intel_dp(connector->encoder);
4445 if (intel_dp->compliance_test_active)
4446 seq_puts(m, "1");
4447 else
4448 seq_puts(m, "0");
4449 } else
4450 seq_puts(m, "0");
4451 }
4452
4453 return 0;
4454 }
4455
4456 static int i915_displayport_test_active_open(struct inode *inode,
4457 struct file *file)
4458 {
4459 struct drm_device *dev = inode->i_private;
4460
4461 return single_open(file, i915_displayport_test_active_show, dev);
4462 }
4463
4464 static const struct file_operations i915_displayport_test_active_fops = {
4465 .owner = THIS_MODULE,
4466 .open = i915_displayport_test_active_open,
4467 .read = seq_read,
4468 .llseek = seq_lseek,
4469 .release = single_release,
4470 .write = i915_displayport_test_active_write
4471 };
4472
4473 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4474 {
4475 struct drm_device *dev = m->private;
4476 struct drm_connector *connector;
4477 struct list_head *connector_list = &dev->mode_config.connector_list;
4478 struct intel_dp *intel_dp;
4479
4480 list_for_each_entry(connector, connector_list, head) {
4481
4482 if (connector->connector_type !=
4483 DRM_MODE_CONNECTOR_DisplayPort)
4484 continue;
4485
4486 if (connector->status == connector_status_connected &&
4487 connector->encoder != NULL) {
4488 intel_dp = enc_to_intel_dp(connector->encoder);
4489 seq_printf(m, "%lx", intel_dp->compliance_test_data);
4490 } else
4491 seq_puts(m, "0");
4492 }
4493
4494 return 0;
4495 }
4496 static int i915_displayport_test_data_open(struct inode *inode,
4497 struct file *file)
4498 {
4499 struct drm_device *dev = inode->i_private;
4500
4501 return single_open(file, i915_displayport_test_data_show, dev);
4502 }
4503
4504 static const struct file_operations i915_displayport_test_data_fops = {
4505 .owner = THIS_MODULE,
4506 .open = i915_displayport_test_data_open,
4507 .read = seq_read,
4508 .llseek = seq_lseek,
4509 .release = single_release
4510 };
4511
4512 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4513 {
4514 struct drm_device *dev = m->private;
4515 struct drm_connector *connector;
4516 struct list_head *connector_list = &dev->mode_config.connector_list;
4517 struct intel_dp *intel_dp;
4518
4519 list_for_each_entry(connector, connector_list, head) {
4520
4521 if (connector->connector_type !=
4522 DRM_MODE_CONNECTOR_DisplayPort)
4523 continue;
4524
4525 if (connector->status == connector_status_connected &&
4526 connector->encoder != NULL) {
4527 intel_dp = enc_to_intel_dp(connector->encoder);
4528 seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4529 } else
4530 seq_puts(m, "0");
4531 }
4532
4533 return 0;
4534 }
4535
4536 static int i915_displayport_test_type_open(struct inode *inode,
4537 struct file *file)
4538 {
4539 struct drm_device *dev = inode->i_private;
4540
4541 return single_open(file, i915_displayport_test_type_show, dev);
4542 }
4543
4544 static const struct file_operations i915_displayport_test_type_fops = {
4545 .owner = THIS_MODULE,
4546 .open = i915_displayport_test_type_open,
4547 .read = seq_read,
4548 .llseek = seq_lseek,
4549 .release = single_release
4550 };
4551
4552 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4553 {
4554 struct drm_device *dev = m->private;
4555 int level;
4556 int num_levels;
4557
4558 if (IS_CHERRYVIEW(dev))
4559 num_levels = 3;
4560 else if (IS_VALLEYVIEW(dev))
4561 num_levels = 1;
4562 else
4563 num_levels = ilk_wm_max_level(dev) + 1;
4564
4565 drm_modeset_lock_all(dev);
4566
4567 for (level = 0; level < num_levels; level++) {
4568 unsigned int latency = wm[level];
4569
4570 /*
4571 * - WM1+ latency values in 0.5us units
4572 * - latencies are in us on gen9/vlv/chv
4573 */
4574 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) ||
4575 IS_CHERRYVIEW(dev))
4576 latency *= 10;
4577 else if (level > 0)
4578 latency *= 5;
4579
4580 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4581 level, wm[level], latency / 10, latency % 10);
4582 }
4583
4584 drm_modeset_unlock_all(dev);
4585 }
4586
4587 static int pri_wm_latency_show(struct seq_file *m, void *data)
4588 {
4589 struct drm_device *dev = m->private;
4590 struct drm_i915_private *dev_priv = to_i915(dev);
4591 const uint16_t *latencies;
4592
4593 if (INTEL_INFO(dev)->gen >= 9)
4594 latencies = dev_priv->wm.skl_latency;
4595 else
4596 latencies = to_i915(dev)->wm.pri_latency;
4597
4598 wm_latency_show(m, latencies);
4599
4600 return 0;
4601 }
4602
4603 static int spr_wm_latency_show(struct seq_file *m, void *data)
4604 {
4605 struct drm_device *dev = m->private;
4606 struct drm_i915_private *dev_priv = to_i915(dev);
4607 const uint16_t *latencies;
4608
4609 if (INTEL_INFO(dev)->gen >= 9)
4610 latencies = dev_priv->wm.skl_latency;
4611 else
4612 latencies = to_i915(dev)->wm.spr_latency;
4613
4614 wm_latency_show(m, latencies);
4615
4616 return 0;
4617 }
4618
4619 static int cur_wm_latency_show(struct seq_file *m, void *data)
4620 {
4621 struct drm_device *dev = m->private;
4622 struct drm_i915_private *dev_priv = to_i915(dev);
4623 const uint16_t *latencies;
4624
4625 if (INTEL_INFO(dev)->gen >= 9)
4626 latencies = dev_priv->wm.skl_latency;
4627 else
4628 latencies = to_i915(dev)->wm.cur_latency;
4629
4630 wm_latency_show(m, latencies);
4631
4632 return 0;
4633 }
4634
4635 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4636 {
4637 struct drm_device *dev = inode->i_private;
4638
4639 if (INTEL_INFO(dev)->gen < 5)
4640 return -ENODEV;
4641
4642 return single_open(file, pri_wm_latency_show, dev);
4643 }
4644
4645 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4646 {
4647 struct drm_device *dev = inode->i_private;
4648
4649 if (HAS_GMCH_DISPLAY(dev))
4650 return -ENODEV;
4651
4652 return single_open(file, spr_wm_latency_show, dev);
4653 }
4654
4655 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4656 {
4657 struct drm_device *dev = inode->i_private;
4658
4659 if (HAS_GMCH_DISPLAY(dev))
4660 return -ENODEV;
4661
4662 return single_open(file, cur_wm_latency_show, dev);
4663 }
4664
4665 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4666 size_t len, loff_t *offp, uint16_t wm[8])
4667 {
4668 struct seq_file *m = file->private_data;
4669 struct drm_device *dev = m->private;
4670 uint16_t new[8] = { 0 };
4671 int num_levels;
4672 int level;
4673 int ret;
4674 char tmp[32];
4675
4676 if (IS_CHERRYVIEW(dev))
4677 num_levels = 3;
4678 else if (IS_VALLEYVIEW(dev))
4679 num_levels = 1;
4680 else
4681 num_levels = ilk_wm_max_level(dev) + 1;
4682
4683 if (len >= sizeof(tmp))
4684 return -EINVAL;
4685
4686 if (copy_from_user(tmp, ubuf, len))
4687 return -EFAULT;
4688
4689 tmp[len] = '\0';
4690
4691 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4692 &new[0], &new[1], &new[2], &new[3],
4693 &new[4], &new[5], &new[6], &new[7]);
4694 if (ret != num_levels)
4695 return -EINVAL;
4696
4697 drm_modeset_lock_all(dev);
4698
4699 for (level = 0; level < num_levels; level++)
4700 wm[level] = new[level];
4701
4702 drm_modeset_unlock_all(dev);
4703
4704 return len;
4705 }
4706
4707
4708 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4709 size_t len, loff_t *offp)
4710 {
4711 struct seq_file *m = file->private_data;
4712 struct drm_device *dev = m->private;
4713 struct drm_i915_private *dev_priv = to_i915(dev);
4714 uint16_t *latencies;
4715
4716 if (INTEL_INFO(dev)->gen >= 9)
4717 latencies = dev_priv->wm.skl_latency;
4718 else
4719 latencies = to_i915(dev)->wm.pri_latency;
4720
4721 return wm_latency_write(file, ubuf, len, offp, latencies);
4722 }
4723
4724 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4725 size_t len, loff_t *offp)
4726 {
4727 struct seq_file *m = file->private_data;
4728 struct drm_device *dev = m->private;
4729 struct drm_i915_private *dev_priv = to_i915(dev);
4730 uint16_t *latencies;
4731
4732 if (INTEL_INFO(dev)->gen >= 9)
4733 latencies = dev_priv->wm.skl_latency;
4734 else
4735 latencies = to_i915(dev)->wm.spr_latency;
4736
4737 return wm_latency_write(file, ubuf, len, offp, latencies);
4738 }
4739
4740 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4741 size_t len, loff_t *offp)
4742 {
4743 struct seq_file *m = file->private_data;
4744 struct drm_device *dev = m->private;
4745 struct drm_i915_private *dev_priv = to_i915(dev);
4746 uint16_t *latencies;
4747
4748 if (INTEL_INFO(dev)->gen >= 9)
4749 latencies = dev_priv->wm.skl_latency;
4750 else
4751 latencies = to_i915(dev)->wm.cur_latency;
4752
4753 return wm_latency_write(file, ubuf, len, offp, latencies);
4754 }
4755
4756 static const struct file_operations i915_pri_wm_latency_fops = {
4757 .owner = THIS_MODULE,
4758 .open = pri_wm_latency_open,
4759 .read = seq_read,
4760 .llseek = seq_lseek,
4761 .release = single_release,
4762 .write = pri_wm_latency_write
4763 };
4764
4765 static const struct file_operations i915_spr_wm_latency_fops = {
4766 .owner = THIS_MODULE,
4767 .open = spr_wm_latency_open,
4768 .read = seq_read,
4769 .llseek = seq_lseek,
4770 .release = single_release,
4771 .write = spr_wm_latency_write
4772 };
4773
4774 static const struct file_operations i915_cur_wm_latency_fops = {
4775 .owner = THIS_MODULE,
4776 .open = cur_wm_latency_open,
4777 .read = seq_read,
4778 .llseek = seq_lseek,
4779 .release = single_release,
4780 .write = cur_wm_latency_write
4781 };
4782
4783 static int
4784 i915_wedged_get(void *data, u64 *val)
4785 {
4786 struct drm_device *dev = data;
4787 struct drm_i915_private *dev_priv = to_i915(dev);
4788
4789 *val = i915_terminally_wedged(&dev_priv->gpu_error);
4790
4791 return 0;
4792 }
4793
4794 static int
4795 i915_wedged_set(void *data, u64 val)
4796 {
4797 struct drm_device *dev = data;
4798 struct drm_i915_private *dev_priv = to_i915(dev);
4799
4800 /*
4801 * There is no safeguard against this debugfs entry colliding
4802 * with the hangcheck calling same i915_handle_error() in
4803 * parallel, causing an explosion. For now we assume that the
4804 * test harness is responsible enough not to inject gpu hangs
4805 * while it is writing to 'i915_wedged'
4806 */
4807
4808 if (i915_reset_in_progress(&dev_priv->gpu_error))
4809 return -EAGAIN;
4810
4811 intel_runtime_pm_get(dev_priv);
4812
4813 i915_handle_error(dev_priv, val,
4814 "Manually setting wedged to %llu", val);
4815
4816 intel_runtime_pm_put(dev_priv);
4817
4818 return 0;
4819 }
4820
4821 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4822 i915_wedged_get, i915_wedged_set,
4823 "%llu\n");
4824
4825 static int
4826 i915_ring_missed_irq_get(void *data, u64 *val)
4827 {
4828 struct drm_device *dev = data;
4829 struct drm_i915_private *dev_priv = to_i915(dev);
4830
4831 *val = dev_priv->gpu_error.missed_irq_rings;
4832 return 0;
4833 }
4834
4835 static int
4836 i915_ring_missed_irq_set(void *data, u64 val)
4837 {
4838 struct drm_device *dev = data;
4839 struct drm_i915_private *dev_priv = to_i915(dev);
4840 int ret;
4841
4842 /* Lock against concurrent debugfs callers */
4843 ret = mutex_lock_interruptible(&dev->struct_mutex);
4844 if (ret)
4845 return ret;
4846 dev_priv->gpu_error.missed_irq_rings = val;
4847 mutex_unlock(&dev->struct_mutex);
4848
4849 return 0;
4850 }
4851
4852 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4853 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4854 "0x%08llx\n");
4855
4856 static int
4857 i915_ring_test_irq_get(void *data, u64 *val)
4858 {
4859 struct drm_device *dev = data;
4860 struct drm_i915_private *dev_priv = to_i915(dev);
4861
4862 *val = dev_priv->gpu_error.test_irq_rings;
4863
4864 return 0;
4865 }
4866
4867 static int
4868 i915_ring_test_irq_set(void *data, u64 val)
4869 {
4870 struct drm_device *dev = data;
4871 struct drm_i915_private *dev_priv = to_i915(dev);
4872
4873 val &= INTEL_INFO(dev_priv)->ring_mask;
4874 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4875 dev_priv->gpu_error.test_irq_rings = val;
4876
4877 return 0;
4878 }
4879
4880 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4881 i915_ring_test_irq_get, i915_ring_test_irq_set,
4882 "0x%08llx\n");
4883
4884 #define DROP_UNBOUND 0x1
4885 #define DROP_BOUND 0x2
4886 #define DROP_RETIRE 0x4
4887 #define DROP_ACTIVE 0x8
4888 #define DROP_ALL (DROP_UNBOUND | \
4889 DROP_BOUND | \
4890 DROP_RETIRE | \
4891 DROP_ACTIVE)
4892 static int
4893 i915_drop_caches_get(void *data, u64 *val)
4894 {
4895 *val = DROP_ALL;
4896
4897 return 0;
4898 }
4899
4900 static int
4901 i915_drop_caches_set(void *data, u64 val)
4902 {
4903 struct drm_device *dev = data;
4904 struct drm_i915_private *dev_priv = to_i915(dev);
4905 int ret;
4906
4907 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4908
4909 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4910 * on ioctls on -EAGAIN. */
4911 ret = mutex_lock_interruptible(&dev->struct_mutex);
4912 if (ret)
4913 return ret;
4914
4915 if (val & DROP_ACTIVE) {
4916 ret = i915_gem_wait_for_idle(dev_priv);
4917 if (ret)
4918 goto unlock;
4919 }
4920
4921 if (val & (DROP_RETIRE | DROP_ACTIVE))
4922 i915_gem_retire_requests(dev_priv);
4923
4924 if (val & DROP_BOUND)
4925 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4926
4927 if (val & DROP_UNBOUND)
4928 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4929
4930 unlock:
4931 mutex_unlock(&dev->struct_mutex);
4932
4933 return ret;
4934 }
4935
4936 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4937 i915_drop_caches_get, i915_drop_caches_set,
4938 "0x%08llx\n");
4939
4940 static int
4941 i915_max_freq_get(void *data, u64 *val)
4942 {
4943 struct drm_device *dev = data;
4944 struct drm_i915_private *dev_priv = to_i915(dev);
4945
4946 if (INTEL_INFO(dev)->gen < 6)
4947 return -ENODEV;
4948
4949 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4950 return 0;
4951 }
4952
4953 static int
4954 i915_max_freq_set(void *data, u64 val)
4955 {
4956 struct drm_device *dev = data;
4957 struct drm_i915_private *dev_priv = to_i915(dev);
4958 u32 hw_max, hw_min;
4959 int ret;
4960
4961 if (INTEL_INFO(dev)->gen < 6)
4962 return -ENODEV;
4963
4964 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4965
4966 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4967 if (ret)
4968 return ret;
4969
4970 /*
4971 * Turbo will still be enabled, but won't go above the set value.
4972 */
4973 val = intel_freq_opcode(dev_priv, val);
4974
4975 hw_max = dev_priv->rps.max_freq;
4976 hw_min = dev_priv->rps.min_freq;
4977
4978 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4979 mutex_unlock(&dev_priv->rps.hw_lock);
4980 return -EINVAL;
4981 }
4982
4983 dev_priv->rps.max_freq_softlimit = val;
4984
4985 intel_set_rps(dev_priv, val);
4986
4987 mutex_unlock(&dev_priv->rps.hw_lock);
4988
4989 return 0;
4990 }
4991
4992 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4993 i915_max_freq_get, i915_max_freq_set,
4994 "%llu\n");
4995
4996 static int
4997 i915_min_freq_get(void *data, u64 *val)
4998 {
4999 struct drm_device *dev = data;
5000 struct drm_i915_private *dev_priv = to_i915(dev);
5001
5002 if (INTEL_GEN(dev_priv) < 6)
5003 return -ENODEV;
5004
5005 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
5006 return 0;
5007 }
5008
5009 static int
5010 i915_min_freq_set(void *data, u64 val)
5011 {
5012 struct drm_device *dev = data;
5013 struct drm_i915_private *dev_priv = to_i915(dev);
5014 u32 hw_max, hw_min;
5015 int ret;
5016
5017 if (INTEL_GEN(dev_priv) < 6)
5018 return -ENODEV;
5019
5020 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
5021
5022 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5023 if (ret)
5024 return ret;
5025
5026 /*
5027 * Turbo will still be enabled, but won't go below the set value.
5028 */
5029 val = intel_freq_opcode(dev_priv, val);
5030
5031 hw_max = dev_priv->rps.max_freq;
5032 hw_min = dev_priv->rps.min_freq;
5033
5034 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
5035 mutex_unlock(&dev_priv->rps.hw_lock);
5036 return -EINVAL;
5037 }
5038
5039 dev_priv->rps.min_freq_softlimit = val;
5040
5041 intel_set_rps(dev_priv, val);
5042
5043 mutex_unlock(&dev_priv->rps.hw_lock);
5044
5045 return 0;
5046 }
5047
5048 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
5049 i915_min_freq_get, i915_min_freq_set,
5050 "%llu\n");
5051
5052 static int
5053 i915_cache_sharing_get(void *data, u64 *val)
5054 {
5055 struct drm_device *dev = data;
5056 struct drm_i915_private *dev_priv = to_i915(dev);
5057 u32 snpcr;
5058 int ret;
5059
5060 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5061 return -ENODEV;
5062
5063 ret = mutex_lock_interruptible(&dev->struct_mutex);
5064 if (ret)
5065 return ret;
5066 intel_runtime_pm_get(dev_priv);
5067
5068 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5069
5070 intel_runtime_pm_put(dev_priv);
5071 mutex_unlock(&dev_priv->drm.struct_mutex);
5072
5073 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
5074
5075 return 0;
5076 }
5077
5078 static int
5079 i915_cache_sharing_set(void *data, u64 val)
5080 {
5081 struct drm_device *dev = data;
5082 struct drm_i915_private *dev_priv = to_i915(dev);
5083 u32 snpcr;
5084
5085 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5086 return -ENODEV;
5087
5088 if (val > 3)
5089 return -EINVAL;
5090
5091 intel_runtime_pm_get(dev_priv);
5092 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
5093
5094 /* Update the cache sharing policy here as well */
5095 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5096 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5097 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5098 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5099
5100 intel_runtime_pm_put(dev_priv);
5101 return 0;
5102 }
5103
5104 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5105 i915_cache_sharing_get, i915_cache_sharing_set,
5106 "%llu\n");
5107
5108 struct sseu_dev_status {
5109 unsigned int slice_total;
5110 unsigned int subslice_total;
5111 unsigned int subslice_per_slice;
5112 unsigned int eu_total;
5113 unsigned int eu_per_subslice;
5114 };
5115
5116 static void cherryview_sseu_device_status(struct drm_device *dev,
5117 struct sseu_dev_status *stat)
5118 {
5119 struct drm_i915_private *dev_priv = to_i915(dev);
5120 int ss_max = 2;
5121 int ss;
5122 u32 sig1[ss_max], sig2[ss_max];
5123
5124 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5125 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5126 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5127 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5128
5129 for (ss = 0; ss < ss_max; ss++) {
5130 unsigned int eu_cnt;
5131
5132 if (sig1[ss] & CHV_SS_PG_ENABLE)
5133 /* skip disabled subslice */
5134 continue;
5135
5136 stat->slice_total = 1;
5137 stat->subslice_per_slice++;
5138 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5139 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5140 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5141 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5142 stat->eu_total += eu_cnt;
5143 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
5144 }
5145 stat->subslice_total = stat->subslice_per_slice;
5146 }
5147
5148 static void gen9_sseu_device_status(struct drm_device *dev,
5149 struct sseu_dev_status *stat)
5150 {
5151 struct drm_i915_private *dev_priv = to_i915(dev);
5152 int s_max = 3, ss_max = 4;
5153 int s, ss;
5154 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5155
5156 /* BXT has a single slice and at most 3 subslices. */
5157 if (IS_BROXTON(dev)) {
5158 s_max = 1;
5159 ss_max = 3;
5160 }
5161
5162 for (s = 0; s < s_max; s++) {
5163 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5164 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5165 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5166 }
5167
5168 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5169 GEN9_PGCTL_SSA_EU19_ACK |
5170 GEN9_PGCTL_SSA_EU210_ACK |
5171 GEN9_PGCTL_SSA_EU311_ACK;
5172 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5173 GEN9_PGCTL_SSB_EU19_ACK |
5174 GEN9_PGCTL_SSB_EU210_ACK |
5175 GEN9_PGCTL_SSB_EU311_ACK;
5176
5177 for (s = 0; s < s_max; s++) {
5178 unsigned int ss_cnt = 0;
5179
5180 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5181 /* skip disabled slice */
5182 continue;
5183
5184 stat->slice_total++;
5185
5186 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
5187 ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
5188
5189 for (ss = 0; ss < ss_max; ss++) {
5190 unsigned int eu_cnt;
5191
5192 if (IS_BROXTON(dev) &&
5193 !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5194 /* skip disabled subslice */
5195 continue;
5196
5197 if (IS_BROXTON(dev))
5198 ss_cnt++;
5199
5200 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5201 eu_mask[ss%2]);
5202 stat->eu_total += eu_cnt;
5203 stat->eu_per_subslice = max(stat->eu_per_subslice,
5204 eu_cnt);
5205 }
5206
5207 stat->subslice_total += ss_cnt;
5208 stat->subslice_per_slice = max(stat->subslice_per_slice,
5209 ss_cnt);
5210 }
5211 }
5212
5213 static void broadwell_sseu_device_status(struct drm_device *dev,
5214 struct sseu_dev_status *stat)
5215 {
5216 struct drm_i915_private *dev_priv = to_i915(dev);
5217 int s;
5218 u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5219
5220 stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK);
5221
5222 if (stat->slice_total) {
5223 stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice;
5224 stat->subslice_total = stat->slice_total *
5225 stat->subslice_per_slice;
5226 stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice;
5227 stat->eu_total = stat->eu_per_subslice * stat->subslice_total;
5228
5229 /* subtract fused off EU(s) from enabled slice(s) */
5230 for (s = 0; s < stat->slice_total; s++) {
5231 u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s];
5232
5233 stat->eu_total -= hweight8(subslice_7eu);
5234 }
5235 }
5236 }
5237
5238 static int i915_sseu_status(struct seq_file *m, void *unused)
5239 {
5240 struct drm_info_node *node = (struct drm_info_node *) m->private;
5241 struct drm_device *dev = node->minor->dev;
5242 struct sseu_dev_status stat;
5243
5244 if (INTEL_INFO(dev)->gen < 8)
5245 return -ENODEV;
5246
5247 seq_puts(m, "SSEU Device Info\n");
5248 seq_printf(m, " Available Slice Total: %u\n",
5249 INTEL_INFO(dev)->slice_total);
5250 seq_printf(m, " Available Subslice Total: %u\n",
5251 INTEL_INFO(dev)->subslice_total);
5252 seq_printf(m, " Available Subslice Per Slice: %u\n",
5253 INTEL_INFO(dev)->subslice_per_slice);
5254 seq_printf(m, " Available EU Total: %u\n",
5255 INTEL_INFO(dev)->eu_total);
5256 seq_printf(m, " Available EU Per Subslice: %u\n",
5257 INTEL_INFO(dev)->eu_per_subslice);
5258 seq_printf(m, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev)));
5259 if (HAS_POOLED_EU(dev))
5260 seq_printf(m, " Min EU in pool: %u\n",
5261 INTEL_INFO(dev)->min_eu_in_pool);
5262 seq_printf(m, " Has Slice Power Gating: %s\n",
5263 yesno(INTEL_INFO(dev)->has_slice_pg));
5264 seq_printf(m, " Has Subslice Power Gating: %s\n",
5265 yesno(INTEL_INFO(dev)->has_subslice_pg));
5266 seq_printf(m, " Has EU Power Gating: %s\n",
5267 yesno(INTEL_INFO(dev)->has_eu_pg));
5268
5269 seq_puts(m, "SSEU Device Status\n");
5270 memset(&stat, 0, sizeof(stat));
5271 if (IS_CHERRYVIEW(dev)) {
5272 cherryview_sseu_device_status(dev, &stat);
5273 } else if (IS_BROADWELL(dev)) {
5274 broadwell_sseu_device_status(dev, &stat);
5275 } else if (INTEL_INFO(dev)->gen >= 9) {
5276 gen9_sseu_device_status(dev, &stat);
5277 }
5278 seq_printf(m, " Enabled Slice Total: %u\n",
5279 stat.slice_total);
5280 seq_printf(m, " Enabled Subslice Total: %u\n",
5281 stat.subslice_total);
5282 seq_printf(m, " Enabled Subslice Per Slice: %u\n",
5283 stat.subslice_per_slice);
5284 seq_printf(m, " Enabled EU Total: %u\n",
5285 stat.eu_total);
5286 seq_printf(m, " Enabled EU Per Subslice: %u\n",
5287 stat.eu_per_subslice);
5288
5289 return 0;
5290 }
5291
5292 static int i915_forcewake_open(struct inode *inode, struct file *file)
5293 {
5294 struct drm_device *dev = inode->i_private;
5295 struct drm_i915_private *dev_priv = to_i915(dev);
5296
5297 if (INTEL_INFO(dev)->gen < 6)
5298 return 0;
5299
5300 intel_runtime_pm_get(dev_priv);
5301 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5302
5303 return 0;
5304 }
5305
5306 static int i915_forcewake_release(struct inode *inode, struct file *file)
5307 {
5308 struct drm_device *dev = inode->i_private;
5309 struct drm_i915_private *dev_priv = to_i915(dev);
5310
5311 if (INTEL_INFO(dev)->gen < 6)
5312 return 0;
5313
5314 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5315 intel_runtime_pm_put(dev_priv);
5316
5317 return 0;
5318 }
5319
5320 static const struct file_operations i915_forcewake_fops = {
5321 .owner = THIS_MODULE,
5322 .open = i915_forcewake_open,
5323 .release = i915_forcewake_release,
5324 };
5325
5326 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5327 {
5328 struct drm_device *dev = minor->dev;
5329 struct dentry *ent;
5330
5331 ent = debugfs_create_file("i915_forcewake_user",
5332 S_IRUSR,
5333 root, dev,
5334 &i915_forcewake_fops);
5335 if (!ent)
5336 return -ENOMEM;
5337
5338 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5339 }
5340
5341 static int i915_debugfs_create(struct dentry *root,
5342 struct drm_minor *minor,
5343 const char *name,
5344 const struct file_operations *fops)
5345 {
5346 struct drm_device *dev = minor->dev;
5347 struct dentry *ent;
5348
5349 ent = debugfs_create_file(name,
5350 S_IRUGO | S_IWUSR,
5351 root, dev,
5352 fops);
5353 if (!ent)
5354 return -ENOMEM;
5355
5356 return drm_add_fake_info_node(minor, ent, fops);
5357 }
5358
5359 static const struct drm_info_list i915_debugfs_list[] = {
5360 {"i915_capabilities", i915_capabilities, 0},
5361 {"i915_gem_objects", i915_gem_object_info, 0},
5362 {"i915_gem_gtt", i915_gem_gtt_info, 0},
5363 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
5364 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
5365 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
5366 {"i915_gem_stolen", i915_gem_stolen_list_info },
5367 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5368 {"i915_gem_request", i915_gem_request_info, 0},
5369 {"i915_gem_seqno", i915_gem_seqno_info, 0},
5370 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5371 {"i915_gem_interrupt", i915_interrupt_info, 0},
5372 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5373 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5374 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5375 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5376 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5377 {"i915_guc_info", i915_guc_info, 0},
5378 {"i915_guc_load_status", i915_guc_load_status_info, 0},
5379 {"i915_guc_log_dump", i915_guc_log_dump, 0},
5380 {"i915_frequency_info", i915_frequency_info, 0},
5381 {"i915_hangcheck_info", i915_hangcheck_info, 0},
5382 {"i915_drpc_info", i915_drpc_info, 0},
5383 {"i915_emon_status", i915_emon_status, 0},
5384 {"i915_ring_freq_table", i915_ring_freq_table, 0},
5385 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5386 {"i915_fbc_status", i915_fbc_status, 0},
5387 {"i915_ips_status", i915_ips_status, 0},
5388 {"i915_sr_status", i915_sr_status, 0},
5389 {"i915_opregion", i915_opregion, 0},
5390 {"i915_vbt", i915_vbt, 0},
5391 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5392 {"i915_context_status", i915_context_status, 0},
5393 {"i915_dump_lrc", i915_dump_lrc, 0},
5394 {"i915_execlists", i915_execlists, 0},
5395 {"i915_forcewake_domains", i915_forcewake_domains, 0},
5396 {"i915_swizzle_info", i915_swizzle_info, 0},
5397 {"i915_ppgtt_info", i915_ppgtt_info, 0},
5398 {"i915_llc", i915_llc, 0},
5399 {"i915_edp_psr_status", i915_edp_psr_status, 0},
5400 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5401 {"i915_energy_uJ", i915_energy_uJ, 0},
5402 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5403 {"i915_power_domain_info", i915_power_domain_info, 0},
5404 {"i915_dmc_info", i915_dmc_info, 0},
5405 {"i915_display_info", i915_display_info, 0},
5406 {"i915_semaphore_status", i915_semaphore_status, 0},
5407 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5408 {"i915_dp_mst_info", i915_dp_mst_info, 0},
5409 {"i915_wa_registers", i915_wa_registers, 0},
5410 {"i915_ddb_info", i915_ddb_info, 0},
5411 {"i915_sseu_status", i915_sseu_status, 0},
5412 {"i915_drrs_status", i915_drrs_status, 0},
5413 {"i915_rps_boost_info", i915_rps_boost_info, 0},
5414 };
5415 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5416
5417 static const struct i915_debugfs_files {
5418 const char *name;
5419 const struct file_operations *fops;
5420 } i915_debugfs_files[] = {
5421 {"i915_wedged", &i915_wedged_fops},
5422 {"i915_max_freq", &i915_max_freq_fops},
5423 {"i915_min_freq", &i915_min_freq_fops},
5424 {"i915_cache_sharing", &i915_cache_sharing_fops},
5425 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5426 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5427 {"i915_gem_drop_caches", &i915_drop_caches_fops},
5428 {"i915_error_state", &i915_error_state_fops},
5429 {"i915_next_seqno", &i915_next_seqno_fops},
5430 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5431 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5432 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5433 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5434 {"i915_fbc_false_color", &i915_fbc_fc_fops},
5435 {"i915_dp_test_data", &i915_displayport_test_data_fops},
5436 {"i915_dp_test_type", &i915_displayport_test_type_fops},
5437 {"i915_dp_test_active", &i915_displayport_test_active_fops}
5438 };
5439
5440 void intel_display_crc_init(struct drm_device *dev)
5441 {
5442 struct drm_i915_private *dev_priv = to_i915(dev);
5443 enum pipe pipe;
5444
5445 for_each_pipe(dev_priv, pipe) {
5446 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5447
5448 pipe_crc->opened = false;
5449 spin_lock_init(&pipe_crc->lock);
5450 init_waitqueue_head(&pipe_crc->wq);
5451 }
5452 }
5453
5454 int i915_debugfs_register(struct drm_i915_private *dev_priv)
5455 {
5456 struct drm_minor *minor = dev_priv->drm.primary;
5457 int ret, i;
5458
5459 ret = i915_forcewake_create(minor->debugfs_root, minor);
5460 if (ret)
5461 return ret;
5462
5463 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5464 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5465 if (ret)
5466 return ret;
5467 }
5468
5469 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5470 ret = i915_debugfs_create(minor->debugfs_root, minor,
5471 i915_debugfs_files[i].name,
5472 i915_debugfs_files[i].fops);
5473 if (ret)
5474 return ret;
5475 }
5476
5477 return drm_debugfs_create_files(i915_debugfs_list,
5478 I915_DEBUGFS_ENTRIES,
5479 minor->debugfs_root, minor);
5480 }
5481
5482 void i915_debugfs_unregister(struct drm_i915_private *dev_priv)
5483 {
5484 struct drm_minor *minor = dev_priv->drm.primary;
5485 int i;
5486
5487 drm_debugfs_remove_files(i915_debugfs_list,
5488 I915_DEBUGFS_ENTRIES, minor);
5489
5490 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5491 1, minor);
5492
5493 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5494 struct drm_info_list *info_list =
5495 (struct drm_info_list *)&i915_pipe_crc_data[i];
5496
5497 drm_debugfs_remove_files(info_list, 1, minor);
5498 }
5499
5500 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5501 struct drm_info_list *info_list =
5502 (struct drm_info_list *) i915_debugfs_files[i].fops;
5503
5504 drm_debugfs_remove_files(info_list, 1, minor);
5505 }
5506 }
5507
5508 struct dpcd_block {
5509 /* DPCD dump start address. */
5510 unsigned int offset;
5511 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5512 unsigned int end;
5513 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5514 size_t size;
5515 /* Only valid for eDP. */
5516 bool edp;
5517 };
5518
5519 static const struct dpcd_block i915_dpcd_debug[] = {
5520 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5521 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5522 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5523 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5524 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5525 { .offset = DP_SET_POWER },
5526 { .offset = DP_EDP_DPCD_REV },
5527 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5528 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5529 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5530 };
5531
5532 static int i915_dpcd_show(struct seq_file *m, void *data)
5533 {
5534 struct drm_connector *connector = m->private;
5535 struct intel_dp *intel_dp =
5536 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5537 uint8_t buf[16];
5538 ssize_t err;
5539 int i;
5540
5541 if (connector->status != connector_status_connected)
5542 return -ENODEV;
5543
5544 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5545 const struct dpcd_block *b = &i915_dpcd_debug[i];
5546 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5547
5548 if (b->edp &&
5549 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5550 continue;
5551
5552 /* low tech for now */
5553 if (WARN_ON(size > sizeof(buf)))
5554 continue;
5555
5556 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5557 if (err <= 0) {
5558 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5559 size, b->offset, err);
5560 continue;
5561 }
5562
5563 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5564 }
5565
5566 return 0;
5567 }
5568
5569 static int i915_dpcd_open(struct inode *inode, struct file *file)
5570 {
5571 return single_open(file, i915_dpcd_show, inode->i_private);
5572 }
5573
5574 static const struct file_operations i915_dpcd_fops = {
5575 .owner = THIS_MODULE,
5576 .open = i915_dpcd_open,
5577 .read = seq_read,
5578 .llseek = seq_lseek,
5579 .release = single_release,
5580 };
5581
5582 /**
5583 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5584 * @connector: pointer to a registered drm_connector
5585 *
5586 * Cleanup will be done by drm_connector_unregister() through a call to
5587 * drm_debugfs_connector_remove().
5588 *
5589 * Returns 0 on success, negative error codes on error.
5590 */
5591 int i915_debugfs_connector_add(struct drm_connector *connector)
5592 {
5593 struct dentry *root = connector->debugfs_entry;
5594
5595 /* The connector must have been registered beforehands. */
5596 if (!root)
5597 return -ENODEV;
5598
5599 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5600 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5601 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5602 &i915_dpcd_fops);
5603
5604 return 0;
5605 }
Linux kernel - Deliverables
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