drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/seq_file.h>
  30 #include <linux/debugfs.h>
  31 #include <linux/slab.h>
  32 #include <linux/export.h>
  33 #include <drm/drmP.h>
  34 #include "intel_drv.h"
  35 #include "intel_ringbuffer.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 #define DRM_I915_RING_DEBUG 1
  40
  41
  42 #if defined(CONFIG_DEBUG_FS)
  43
  44 enum {
  45         ACTIVE_LIST,
  46         INACTIVE_LIST,
  47         PINNED_LIST,
  48 };
  49
  50 static const char *yesno(int v)
  51 {
  52         return v ? "yes" : "no";
  53 }
  54
  55 static int i915_capabilities(struct seq_file *m, void *data)
  56 {
  57         struct drm_info_node *node = (struct drm_info_node *) m->private;
  58         struct drm_device *dev = node->minor->dev;
  59         const struct intel_device_info *info = INTEL_INFO(dev);
  60
  61         seq_printf(m, "gen: %d\n", info->gen);
  62         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
  63 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  64 #define SEP_SEMICOLON ;
  65         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
  66 #undef PRINT_FLAG
  67 #undef SEP_SEMICOLON
  68
  69         return 0;
  70 }
  71
  72 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
  73 {
  74         if (obj->user_pin_count > 0)
  75                 return "P";
  76         else if (obj->pin_count > 0)
  77                 return "p";
  78         else
  79                 return " ";
  80 }
  81
  82 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
  83 {
  84         switch (obj->tiling_mode) {
  85         default:
  86         case I915_TILING_NONE: return " ";
  87         case I915_TILING_X: return "X";
  88         case I915_TILING_Y: return "Y";
  89         }
  90 }
  91
  92 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
  93 {
  94         return obj->has_global_gtt_mapping ? "g" : " ";
  95 }
  96
  97 static void
  98 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
  99 {
 100         struct i915_vma *vma;
 101         seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %d %d %d%s%s%s",
 102                    &obj->base,
 103                    get_pin_flag(obj),
 104                    get_tiling_flag(obj),
 105                    get_global_flag(obj),
 106                    obj->base.size / 1024,
 107                    obj->base.read_domains,
 108                    obj->base.write_domain,
 109                    obj->last_read_seqno,
 110                    obj->last_write_seqno,
 111                    obj->last_fenced_seqno,
 112                    i915_cache_level_str(obj->cache_level),
 113                    obj->dirty ? " dirty" : "",
 114                    obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
 115         if (obj->base.name)
 116                 seq_printf(m, " (name: %d)", obj->base.name);
 117         if (obj->pin_count)
 118                 seq_printf(m, " (pinned x %d)", obj->pin_count);
 119         if (obj->fence_reg != I915_FENCE_REG_NONE)
 120                 seq_printf(m, " (fence: %d)", obj->fence_reg);
 121         list_for_each_entry(vma, &obj->vma_list, vma_link) {
 122                 if (!i915_is_ggtt(vma->vm))
 123                         seq_puts(m, " (pp");
 124                 else
 125                         seq_puts(m, " (g");
 126                 seq_printf(m, "gtt offset: %08lx, size: %08lx)",
 127                            vma->node.start, vma->node.size);
 128         }
 129         if (obj->stolen)
 130                 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
 131         if (obj->pin_mappable || obj->fault_mappable) {
 132                 char s[3], *t = s;
 133                 if (obj->pin_mappable)
 134                         *t++ = 'p';
 135                 if (obj->fault_mappable)
 136                         *t++ = 'f';
 137                 *t = '\0';
 138                 seq_printf(m, " (%s mappable)", s);
 139         }
 140         if (obj->ring != NULL)
 141                 seq_printf(m, " (%s)", obj->ring->name);
 142 }
 143
 144 static int i915_gem_object_list_info(struct seq_file *m, void *data)
 145 {
 146         struct drm_info_node *node = (struct drm_info_node *) m->private;
 147         uintptr_t list = (uintptr_t) node->info_ent->data;
 148         struct list_head *head;
 149         struct drm_device *dev = node->minor->dev;
 150         struct drm_i915_private *dev_priv = dev->dev_private;
 151         struct i915_address_space *vm = &dev_priv->gtt.base;
 152         struct drm_i915_gem_object *obj;
 153         size_t total_obj_size, total_gtt_size;
 154         int count, ret;
 155
 156         ret = mutex_lock_interruptible(&dev->struct_mutex);
 157         if (ret)
 158                 return ret;
 159
 160         switch (list) {
 161         case ACTIVE_LIST:
 162                 seq_puts(m, "Active:\n");
 163                 head = &vm->active_list;
 164                 break;
 165         case INACTIVE_LIST:
 166                 seq_puts(m, "Inactive:\n");
 167                 head = &vm->inactive_list;
 168                 break;
 169         default:
 170                 mutex_unlock(&dev->struct_mutex);
 171                 return -EINVAL;
 172         }
 173
 174         total_obj_size = total_gtt_size = count = 0;
 175         list_for_each_entry(obj, head, mm_list) {
 176                 seq_puts(m, "   ");
 177                 describe_obj(m, obj);
 178                 seq_putc(m, '\n');
 179                 total_obj_size += obj->base.size;
 180                 total_gtt_size += i915_gem_obj_ggtt_size(obj);
 181                 count++;
 182         }
 183         mutex_unlock(&dev->struct_mutex);
 184
 185         seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 186                    count, total_obj_size, total_gtt_size);
 187         return 0;
 188 }
 189
 190 #define count_objects(list, member) do { \
 191         list_for_each_entry(obj, list, member) { \
 192                 size += i915_gem_obj_ggtt_size(obj); \
 193                 ++count; \
 194                 if (obj->map_and_fenceable) { \
 195                         mappable_size += i915_gem_obj_ggtt_size(obj); \
 196                         ++mappable_count; \
 197                 } \
 198         } \
 199 } while (0)
 200
 201 struct file_stats {
 202         int count;
 203         size_t total, active, inactive, unbound;
 204 };
 205
 206 static int per_file_stats(int id, void *ptr, void *data)
 207 {
 208         struct drm_i915_gem_object *obj = ptr;
 209         struct file_stats *stats = data;
 210
 211         stats->count++;
 212         stats->total += obj->base.size;
 213
 214         if (i915_gem_obj_ggtt_bound(obj)) {
 215                 if (!list_empty(&obj->ring_list))
 216                         stats->active += obj->base.size;
 217                 else
 218                         stats->inactive += obj->base.size;
 219         } else {
 220                 if (!list_empty(&obj->global_list))
 221                         stats->unbound += obj->base.size;
 222         }
 223
 224         return 0;
 225 }
 226
 227 static int i915_gem_object_info(struct seq_file *m, void *data)
 228 {
 229         struct drm_info_node *node = (struct drm_info_node *) m->private;
 230         struct drm_device *dev = node->minor->dev;
 231         struct drm_i915_private *dev_priv = dev->dev_private;
 232         u32 count, mappable_count, purgeable_count;
 233         size_t size, mappable_size, purgeable_size;
 234         struct drm_i915_gem_object *obj;
 235         struct i915_address_space *vm = &dev_priv->gtt.base;
 236         struct drm_file *file;
 237         int ret;
 238
 239         ret = mutex_lock_interruptible(&dev->struct_mutex);
 240         if (ret)
 241                 return ret;
 242
 243         seq_printf(m, "%u objects, %zu bytes\n",
 244                    dev_priv->mm.object_count,
 245                    dev_priv->mm.object_memory);
 246
 247         size = count = mappable_size = mappable_count = 0;
 248         count_objects(&dev_priv->mm.bound_list, global_list);
 249         seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
 250                    count, mappable_count, size, mappable_size);
 251
 252         size = count = mappable_size = mappable_count = 0;
 253         count_objects(&vm->active_list, mm_list);
 254         seq_printf(m, "  %u [%u] active objects, %zu [%zu] bytes\n",
 255                    count, mappable_count, size, mappable_size);
 256
 257         size = count = mappable_size = mappable_count = 0;
 258         count_objects(&vm->inactive_list, mm_list);
 259         seq_printf(m, "  %u [%u] inactive objects, %zu [%zu] bytes\n",
 260                    count, mappable_count, size, mappable_size);
 261
 262         size = count = purgeable_size = purgeable_count = 0;
 263         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 264                 size += obj->base.size, ++count;
 265                 if (obj->madv == I915_MADV_DONTNEED)
 266                         purgeable_size += obj->base.size, ++purgeable_count;
 267         }
 268         seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
 269
 270         size = count = mappable_size = mappable_count = 0;
 271         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 272                 if (obj->fault_mappable) {
 273                         size += i915_gem_obj_ggtt_size(obj);
 274                         ++count;
 275                 }
 276                 if (obj->pin_mappable) {
 277                         mappable_size += i915_gem_obj_ggtt_size(obj);
 278                         ++mappable_count;
 279                 }
 280                 if (obj->madv == I915_MADV_DONTNEED) {
 281                         purgeable_size += obj->base.size;
 282                         ++purgeable_count;
 283                 }
 284         }
 285         seq_printf(m, "%u purgeable objects, %zu bytes\n",
 286                    purgeable_count, purgeable_size);
 287         seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
 288                    mappable_count, mappable_size);
 289         seq_printf(m, "%u fault mappable objects, %zu bytes\n",
 290                    count, size);
 291
 292         seq_printf(m, "%zu [%lu] gtt total\n",
 293                    dev_priv->gtt.base.total,
 294                    dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
 295
 296         seq_putc(m, '\n');
 297         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 298                 struct file_stats stats;
 299
 300                 memset(&stats, 0, sizeof(stats));
 301                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 302                 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n",
 303                            get_pid_task(file->pid, PIDTYPE_PID)->comm,
 304                            stats.count,
 305                            stats.total,
 306                            stats.active,
 307                            stats.inactive,
 308                            stats.unbound);
 309         }
 310
 311         mutex_unlock(&dev->struct_mutex);
 312
 313         return 0;
 314 }
 315
 316 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 317 {
 318         struct drm_info_node *node = (struct drm_info_node *) m->private;
 319         struct drm_device *dev = node->minor->dev;
 320         uintptr_t list = (uintptr_t) node->info_ent->data;
 321         struct drm_i915_private *dev_priv = dev->dev_private;
 322         struct drm_i915_gem_object *obj;
 323         size_t total_obj_size, total_gtt_size;
 324         int count, ret;
 325
 326         ret = mutex_lock_interruptible(&dev->struct_mutex);
 327         if (ret)
 328                 return ret;
 329
 330         total_obj_size = total_gtt_size = count = 0;
 331         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 332                 if (list == PINNED_LIST && obj->pin_count == 0)
 333                         continue;
 334
 335                 seq_puts(m, "   ");
 336                 describe_obj(m, obj);
 337                 seq_putc(m, '\n');
 338                 total_obj_size += obj->base.size;
 339                 total_gtt_size += i915_gem_obj_ggtt_size(obj);
 340                 count++;
 341         }
 342
 343         mutex_unlock(&dev->struct_mutex);
 344
 345         seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 346                    count, total_obj_size, total_gtt_size);
 347
 348         return 0;
 349 }
 350
 351 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
 352 {
 353         struct drm_info_node *node = (struct drm_info_node *) m->private;
 354         struct drm_device *dev = node->minor->dev;
 355         unsigned long flags;
 356         struct intel_crtc *crtc;
 357
 358         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
 359                 const char pipe = pipe_name(crtc->pipe);
 360                 const char plane = plane_name(crtc->plane);
 361                 struct intel_unpin_work *work;
 362
 363                 spin_lock_irqsave(&dev->event_lock, flags);
 364                 work = crtc->unpin_work;
 365                 if (work == NULL) {
 366                         seq_printf(m, "No flip due on pipe %c (plane %c)\n",
 367                                    pipe, plane);
 368                 } else {
 369                         if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
 370                                 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
 371                                            pipe, plane);
 372                         } else {
 373                                 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 374                                            pipe, plane);
 375                         }
 376                         if (work->enable_stall_check)
 377                                 seq_puts(m, "Stall check enabled, ");
 378                         else
 379                                 seq_puts(m, "Stall check waiting for page flip ioctl, ");
 380                         seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
 381
 382                         if (work->old_fb_obj) {
 383                                 struct drm_i915_gem_object *obj = work->old_fb_obj;
 384                                 if (obj)
 385                                         seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n",
 386                                                    i915_gem_obj_ggtt_offset(obj));
 387                         }
 388                         if (work->pending_flip_obj) {
 389                                 struct drm_i915_gem_object *obj = work->pending_flip_obj;
 390                                 if (obj)
 391                                         seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n",
 392                                                    i915_gem_obj_ggtt_offset(obj));
 393                         }
 394                 }
 395                 spin_unlock_irqrestore(&dev->event_lock, flags);
 396         }
 397
 398         return 0;
 399 }
 400
 401 static int i915_gem_request_info(struct seq_file *m, void *data)
 402 {
 403         struct drm_info_node *node = (struct drm_info_node *) m->private;
 404         struct drm_device *dev = node->minor->dev;
 405         drm_i915_private_t *dev_priv = dev->dev_private;
 406         struct intel_ring_buffer *ring;
 407         struct drm_i915_gem_request *gem_request;
 408         int ret, count, i;
 409
 410         ret = mutex_lock_interruptible(&dev->struct_mutex);
 411         if (ret)
 412                 return ret;
 413
 414         count = 0;
 415         for_each_ring(ring, dev_priv, i) {
 416                 if (list_empty(&ring->request_list))
 417                         continue;
 418
 419                 seq_printf(m, "%s requests:\n", ring->name);
 420                 list_for_each_entry(gem_request,
 421                                     &ring->request_list,
 422                                     list) {
 423                         seq_printf(m, "    %d @ %d\n",
 424                                    gem_request->seqno,
 425                                    (int) (jiffies - gem_request->emitted_jiffies));
 426                 }
 427                 count++;
 428         }
 429         mutex_unlock(&dev->struct_mutex);
 430
 431         if (count == 0)
 432                 seq_puts(m, "No requests\n");
 433
 434         return 0;
 435 }
 436
 437 static void i915_ring_seqno_info(struct seq_file *m,
 438                                  struct intel_ring_buffer *ring)
 439 {
 440         if (ring->get_seqno) {
 441                 seq_printf(m, "Current sequence (%s): %u\n",
 442                            ring->name, ring->get_seqno(ring, false));
 443         }
 444 }
 445
 446 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 447 {
 448         struct drm_info_node *node = (struct drm_info_node *) m->private;
 449         struct drm_device *dev = node->minor->dev;
 450         drm_i915_private_t *dev_priv = dev->dev_private;
 451         struct intel_ring_buffer *ring;
 452         int ret, i;
 453
 454         ret = mutex_lock_interruptible(&dev->struct_mutex);
 455         if (ret)
 456                 return ret;
 457
 458         for_each_ring(ring, dev_priv, i)
 459                 i915_ring_seqno_info(m, ring);
 460
 461         mutex_unlock(&dev->struct_mutex);
 462
 463         return 0;
 464 }
 465
 466
 467 static int i915_interrupt_info(struct seq_file *m, void *data)
 468 {
 469         struct drm_info_node *node = (struct drm_info_node *) m->private;
 470         struct drm_device *dev = node->minor->dev;
 471         drm_i915_private_t *dev_priv = dev->dev_private;
 472         struct intel_ring_buffer *ring;
 473         int ret, i, pipe;
 474
 475         ret = mutex_lock_interruptible(&dev->struct_mutex);
 476         if (ret)
 477                 return ret;
 478
 479         if (IS_VALLEYVIEW(dev)) {
 480                 seq_printf(m, "Display IER:\t%08x\n",
 481                            I915_READ(VLV_IER));
 482                 seq_printf(m, "Display IIR:\t%08x\n",
 483                            I915_READ(VLV_IIR));
 484                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 485                            I915_READ(VLV_IIR_RW));
 486                 seq_printf(m, "Display IMR:\t%08x\n",
 487                            I915_READ(VLV_IMR));
 488                 for_each_pipe(pipe)
 489                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 490                                    pipe_name(pipe),
 491                                    I915_READ(PIPESTAT(pipe)));
 492
 493                 seq_printf(m, "Master IER:\t%08x\n",
 494                            I915_READ(VLV_MASTER_IER));
 495
 496                 seq_printf(m, "Render IER:\t%08x\n",
 497                            I915_READ(GTIER));
 498                 seq_printf(m, "Render IIR:\t%08x\n",
 499                            I915_READ(GTIIR));
 500                 seq_printf(m, "Render IMR:\t%08x\n",
 501                            I915_READ(GTIMR));
 502
 503                 seq_printf(m, "PM IER:\t\t%08x\n",
 504                            I915_READ(GEN6_PMIER));
 505                 seq_printf(m, "PM IIR:\t\t%08x\n",
 506                            I915_READ(GEN6_PMIIR));
 507                 seq_printf(m, "PM IMR:\t\t%08x\n",
 508                            I915_READ(GEN6_PMIMR));
 509
 510                 seq_printf(m, "Port hotplug:\t%08x\n",
 511                            I915_READ(PORT_HOTPLUG_EN));
 512                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 513                            I915_READ(VLV_DPFLIPSTAT));
 514                 seq_printf(m, "DPINVGTT:\t%08x\n",
 515                            I915_READ(DPINVGTT));
 516
 517         } else if (!HAS_PCH_SPLIT(dev)) {
 518                 seq_printf(m, "Interrupt enable:    %08x\n",
 519                            I915_READ(IER));
 520                 seq_printf(m, "Interrupt identity:  %08x\n",
 521                            I915_READ(IIR));
 522                 seq_printf(m, "Interrupt mask:      %08x\n",
 523                            I915_READ(IMR));
 524                 for_each_pipe(pipe)
 525                         seq_printf(m, "Pipe %c stat:         %08x\n",
 526                                    pipe_name(pipe),
 527                                    I915_READ(PIPESTAT(pipe)));
 528         } else {
 529                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 530                            I915_READ(DEIER));
 531                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 532                            I915_READ(DEIIR));
 533                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 534                            I915_READ(DEIMR));
 535                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 536                            I915_READ(SDEIER));
 537                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 538                            I915_READ(SDEIIR));
 539                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 540                            I915_READ(SDEIMR));
 541                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 542                            I915_READ(GTIER));
 543                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 544                            I915_READ(GTIIR));
 545                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 546                            I915_READ(GTIMR));
 547         }
 548         seq_printf(m, "Interrupts received: %d\n",
 549                    atomic_read(&dev_priv->irq_received));
 550         for_each_ring(ring, dev_priv, i) {
 551                 if (IS_GEN6(dev) || IS_GEN7(dev)) {
 552                         seq_printf(m,
 553                                    "Graphics Interrupt mask (%s):       %08x\n",
 554                                    ring->name, I915_READ_IMR(ring));
 555                 }
 556                 i915_ring_seqno_info(m, ring);
 557         }
 558         mutex_unlock(&dev->struct_mutex);
 559
 560         return 0;
 561 }
 562
 563 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 564 {
 565         struct drm_info_node *node = (struct drm_info_node *) m->private;
 566         struct drm_device *dev = node->minor->dev;
 567         drm_i915_private_t *dev_priv = dev->dev_private;
 568         int i, ret;
 569
 570         ret = mutex_lock_interruptible(&dev->struct_mutex);
 571         if (ret)
 572                 return ret;
 573
 574         seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
 575         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 576         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 577                 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
 578
 579                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 580                            i, dev_priv->fence_regs[i].pin_count);
 581                 if (obj == NULL)
 582                         seq_puts(m, "unused");
 583                 else
 584                         describe_obj(m, obj);
 585                 seq_putc(m, '\n');
 586         }
 587
 588         mutex_unlock(&dev->struct_mutex);
 589         return 0;
 590 }
 591
 592 static int i915_hws_info(struct seq_file *m, void *data)
 593 {
 594         struct drm_info_node *node = (struct drm_info_node *) m->private;
 595         struct drm_device *dev = node->minor->dev;
 596         drm_i915_private_t *dev_priv = dev->dev_private;
 597         struct intel_ring_buffer *ring;
 598         const u32 *hws;
 599         int i;
 600
 601         ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
 602         hws = ring->status_page.page_addr;
 603         if (hws == NULL)
 604                 return 0;
 605
 606         for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
 607                 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 608                            i * 4,
 609                            hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
 610         }
 611         return 0;
 612 }
 613
 614 static ssize_t
 615 i915_error_state_write(struct file *filp,
 616                        const char __user *ubuf,
 617                        size_t cnt,
 618                        loff_t *ppos)
 619 {
 620         struct i915_error_state_file_priv *error_priv = filp->private_data;
 621         struct drm_device *dev = error_priv->dev;
 622         int ret;
 623
 624         DRM_DEBUG_DRIVER("Resetting error state\n");
 625
 626         ret = mutex_lock_interruptible(&dev->struct_mutex);
 627         if (ret)
 628                 return ret;
 629
 630         i915_destroy_error_state(dev);
 631         mutex_unlock(&dev->struct_mutex);
 632
 633         return cnt;
 634 }
 635
 636 static int i915_error_state_open(struct inode *inode, struct file *file)
 637 {
 638         struct drm_device *dev = inode->i_private;
 639         struct i915_error_state_file_priv *error_priv;
 640
 641         error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
 642         if (!error_priv)
 643                 return -ENOMEM;
 644
 645         error_priv->dev = dev;
 646
 647         i915_error_state_get(dev, error_priv);
 648
 649         file->private_data = error_priv;
 650
 651         return 0;
 652 }
 653
 654 static int i915_error_state_release(struct inode *inode, struct file *file)
 655 {
 656         struct i915_error_state_file_priv *error_priv = file->private_data;
 657
 658         i915_error_state_put(error_priv);
 659         kfree(error_priv);
 660
 661         return 0;
 662 }
 663
 664 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
 665                                      size_t count, loff_t *pos)
 666 {
 667         struct i915_error_state_file_priv *error_priv = file->private_data;
 668         struct drm_i915_error_state_buf error_str;
 669         loff_t tmp_pos = 0;
 670         ssize_t ret_count = 0;
 671         int ret;
 672
 673         ret = i915_error_state_buf_init(&error_str, count, *pos);
 674         if (ret)
 675                 return ret;
 676
 677         ret = i915_error_state_to_str(&error_str, error_priv);
 678         if (ret)
 679                 goto out;
 680
 681         ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
 682                                             error_str.buf,
 683                                             error_str.bytes);
 684
 685         if (ret_count < 0)
 686                 ret = ret_count;
 687         else
 688                 *pos = error_str.start + ret_count;
 689 out:
 690         i915_error_state_buf_release(&error_str);
 691         return ret ?: ret_count;
 692 }
 693
 694 static const struct file_operations i915_error_state_fops = {
 695         .owner = THIS_MODULE,
 696         .open = i915_error_state_open,
 697         .read = i915_error_state_read,
 698         .write = i915_error_state_write,
 699         .llseek = default_llseek,
 700         .release = i915_error_state_release,
 701 };
 702
 703 static int
 704 i915_next_seqno_get(void *data, u64 *val)
 705 {
 706         struct drm_device *dev = data;
 707         drm_i915_private_t *dev_priv = dev->dev_private;
 708         int ret;
 709
 710         ret = mutex_lock_interruptible(&dev->struct_mutex);
 711         if (ret)
 712                 return ret;
 713
 714         *val = dev_priv->next_seqno;
 715         mutex_unlock(&dev->struct_mutex);
 716
 717         return 0;
 718 }
 719
 720 static int
 721 i915_next_seqno_set(void *data, u64 val)
 722 {
 723         struct drm_device *dev = data;
 724         int ret;
 725
 726         ret = mutex_lock_interruptible(&dev->struct_mutex);
 727         if (ret)
 728                 return ret;
 729
 730         ret = i915_gem_set_seqno(dev, val);
 731         mutex_unlock(&dev->struct_mutex);
 732
 733         return ret;
 734 }
 735
 736 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
 737                         i915_next_seqno_get, i915_next_seqno_set,
 738                         "0x%llx\n");
 739
 740 static int i915_rstdby_delays(struct seq_file *m, void *unused)
 741 {
 742         struct drm_info_node *node = (struct drm_info_node *) m->private;
 743         struct drm_device *dev = node->minor->dev;
 744         drm_i915_private_t *dev_priv = dev->dev_private;
 745         u16 crstanddelay;
 746         int ret;
 747
 748         ret = mutex_lock_interruptible(&dev->struct_mutex);
 749         if (ret)
 750                 return ret;
 751
 752         crstanddelay = I915_READ16(CRSTANDVID);
 753
 754         mutex_unlock(&dev->struct_mutex);
 755
 756         seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
 757
 758         return 0;
 759 }
 760
 761 static int i915_cur_delayinfo(struct seq_file *m, void *unused)
 762 {
 763         struct drm_info_node *node = (struct drm_info_node *) m->private;
 764         struct drm_device *dev = node->minor->dev;
 765         drm_i915_private_t *dev_priv = dev->dev_private;
 766         int ret;
 767
 768         if (IS_GEN5(dev)) {
 769                 u16 rgvswctl = I915_READ16(MEMSWCTL);
 770                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
 771
 772                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
 773                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
 774                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
 775                            MEMSTAT_VID_SHIFT);
 776                 seq_printf(m, "Current P-state: %d\n",
 777                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
 778         } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
 779                 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
 780                 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
 781                 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
 782                 u32 rpstat, cagf;
 783                 u32 rpupei, rpcurup, rpprevup;
 784                 u32 rpdownei, rpcurdown, rpprevdown;
 785                 int max_freq;
 786
 787                 /* RPSTAT1 is in the GT power well */
 788                 ret = mutex_lock_interruptible(&dev->struct_mutex);
 789                 if (ret)
 790                         return ret;
 791
 792                 gen6_gt_force_wake_get(dev_priv);
 793
 794                 rpstat = I915_READ(GEN6_RPSTAT1);
 795                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
 796                 rpcurup = I915_READ(GEN6_RP_CUR_UP);
 797                 rpprevup = I915_READ(GEN6_RP_PREV_UP);
 798                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
 799                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
 800                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
 801                 if (IS_HASWELL(dev))
 802                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
 803                 else
 804                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
 805                 cagf *= GT_FREQUENCY_MULTIPLIER;
 806
 807                 gen6_gt_force_wake_put(dev_priv);
 808                 mutex_unlock(&dev->struct_mutex);
 809
 810                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
 811                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
 812                 seq_printf(m, "Render p-state ratio: %d\n",
 813                            (gt_perf_status & 0xff00) >> 8);
 814                 seq_printf(m, "Render p-state VID: %d\n",
 815                            gt_perf_status & 0xff);
 816                 seq_printf(m, "Render p-state limit: %d\n",
 817                            rp_state_limits & 0xff);
 818                 seq_printf(m, "CAGF: %dMHz\n", cagf);
 819                 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
 820                            GEN6_CURICONT_MASK);
 821                 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
 822                            GEN6_CURBSYTAVG_MASK);
 823                 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
 824                            GEN6_CURBSYTAVG_MASK);
 825                 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
 826                            GEN6_CURIAVG_MASK);
 827                 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
 828                            GEN6_CURBSYTAVG_MASK);
 829                 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
 830                            GEN6_CURBSYTAVG_MASK);
 831
 832                 max_freq = (rp_state_cap & 0xff0000) >> 16;
 833                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
 834                            max_freq * GT_FREQUENCY_MULTIPLIER);
 835
 836                 max_freq = (rp_state_cap & 0xff00) >> 8;
 837                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
 838                            max_freq * GT_FREQUENCY_MULTIPLIER);
 839
 840                 max_freq = rp_state_cap & 0xff;
 841                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
 842                            max_freq * GT_FREQUENCY_MULTIPLIER);
 843
 844                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
 845                            dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER);
 846         } else if (IS_VALLEYVIEW(dev)) {
 847                 u32 freq_sts, val;
 848
 849                 mutex_lock(&dev_priv->rps.hw_lock);
 850                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
 851                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
 852                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
 853
 854                 val = vlv_punit_read(dev_priv, PUNIT_FUSE_BUS1);
 855                 seq_printf(m, "max GPU freq: %d MHz\n",
 856                            vlv_gpu_freq(dev_priv->mem_freq, val));
 857
 858                 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM);
 859                 seq_printf(m, "min GPU freq: %d MHz\n",
 860                            vlv_gpu_freq(dev_priv->mem_freq, val));
 861
 862                 seq_printf(m, "current GPU freq: %d MHz\n",
 863                            vlv_gpu_freq(dev_priv->mem_freq,
 864                                         (freq_sts >> 8) & 0xff));
 865                 mutex_unlock(&dev_priv->rps.hw_lock);
 866         } else {
 867                 seq_puts(m, "no P-state info available\n");
 868         }
 869
 870         return 0;
 871 }
 872
 873 static int i915_delayfreq_table(struct seq_file *m, void *unused)
 874 {
 875         struct drm_info_node *node = (struct drm_info_node *) m->private;
 876         struct drm_device *dev = node->minor->dev;
 877         drm_i915_private_t *dev_priv = dev->dev_private;
 878         u32 delayfreq;
 879         int ret, i;
 880
 881         ret = mutex_lock_interruptible(&dev->struct_mutex);
 882         if (ret)
 883                 return ret;
 884
 885         for (i = 0; i < 16; i++) {
 886                 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
 887                 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
 888                            (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
 889         }
 890
 891         mutex_unlock(&dev->struct_mutex);
 892
 893         return 0;
 894 }
 895
 896 static inline int MAP_TO_MV(int map)
 897 {
 898         return 1250 - (map * 25);
 899 }
 900
 901 static int i915_inttoext_table(struct seq_file *m, void *unused)
 902 {
 903         struct drm_info_node *node = (struct drm_info_node *) m->private;
 904         struct drm_device *dev = node->minor->dev;
 905         drm_i915_private_t *dev_priv = dev->dev_private;
 906         u32 inttoext;
 907         int ret, i;
 908
 909         ret = mutex_lock_interruptible(&dev->struct_mutex);
 910         if (ret)
 911                 return ret;
 912
 913         for (i = 1; i <= 32; i++) {
 914                 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
 915                 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
 916         }
 917
 918         mutex_unlock(&dev->struct_mutex);
 919
 920         return 0;
 921 }
 922
 923 static int ironlake_drpc_info(struct seq_file *m)
 924 {
 925         struct drm_info_node *node = (struct drm_info_node *) m->private;
 926         struct drm_device *dev = node->minor->dev;
 927         drm_i915_private_t *dev_priv = dev->dev_private;
 928         u32 rgvmodectl, rstdbyctl;
 929         u16 crstandvid;
 930         int ret;
 931
 932         ret = mutex_lock_interruptible(&dev->struct_mutex);
 933         if (ret)
 934                 return ret;
 935
 936         rgvmodectl = I915_READ(MEMMODECTL);
 937         rstdbyctl = I915_READ(RSTDBYCTL);
 938         crstandvid = I915_READ16(CRSTANDVID);
 939
 940         mutex_unlock(&dev->struct_mutex);
 941
 942         seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
 943                    "yes" : "no");
 944         seq_printf(m, "Boost freq: %d\n",
 945                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
 946                    MEMMODE_BOOST_FREQ_SHIFT);
 947         seq_printf(m, "HW control enabled: %s\n",
 948                    rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
 949         seq_printf(m, "SW control enabled: %s\n",
 950                    rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
 951         seq_printf(m, "Gated voltage change: %s\n",
 952                    rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
 953         seq_printf(m, "Starting frequency: P%d\n",
 954                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
 955         seq_printf(m, "Max P-state: P%d\n",
 956                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
 957         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
 958         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
 959         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
 960         seq_printf(m, "Render standby enabled: %s\n",
 961                    (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
 962         seq_puts(m, "Current RS state: ");
 963         switch (rstdbyctl & RSX_STATUS_MASK) {
 964         case RSX_STATUS_ON:
 965                 seq_puts(m, "on\n");
 966                 break;
 967         case RSX_STATUS_RC1:
 968                 seq_puts(m, "RC1\n");
 969                 break;
 970         case RSX_STATUS_RC1E:
 971                 seq_puts(m, "RC1E\n");
 972                 break;
 973         case RSX_STATUS_RS1:
 974                 seq_puts(m, "RS1\n");
 975                 break;
 976         case RSX_STATUS_RS2:
 977                 seq_puts(m, "RS2 (RC6)\n");
 978                 break;
 979         case RSX_STATUS_RS3:
 980                 seq_puts(m, "RC3 (RC6+)\n");
 981                 break;
 982         default:
 983                 seq_puts(m, "unknown\n");
 984                 break;
 985         }
 986
 987         return 0;
 988 }
 989
 990 static int gen6_drpc_info(struct seq_file *m)
 991 {
 992
 993         struct drm_info_node *node = (struct drm_info_node *) m->private;
 994         struct drm_device *dev = node->minor->dev;
 995         struct drm_i915_private *dev_priv = dev->dev_private;
 996         u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
 997         unsigned forcewake_count;
 998         int count = 0, ret;
 999
1000         ret = mutex_lock_interruptible(&dev->struct_mutex);
1001         if (ret)
1002                 return ret;
1003
1004         spin_lock_irq(&dev_priv->uncore.lock);
1005         forcewake_count = dev_priv->uncore.forcewake_count;
1006         spin_unlock_irq(&dev_priv->uncore.lock);
1007
1008         if (forcewake_count) {
1009                 seq_puts(m, "RC information inaccurate because somebody "
1010                             "holds a forcewake reference \n");
1011         } else {
1012                 /* NB: we cannot use forcewake, else we read the wrong values */
1013                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1014                         udelay(10);
1015                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1016         }
1017
1018         gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1019         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1020
1021         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1022         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1023         mutex_unlock(&dev->struct_mutex);
1024         mutex_lock(&dev_priv->rps.hw_lock);
1025         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1026         mutex_unlock(&dev_priv->rps.hw_lock);
1027
1028         seq_printf(m, "Video Turbo Mode: %s\n",
1029                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1030         seq_printf(m, "HW control enabled: %s\n",
1031                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1032         seq_printf(m, "SW control enabled: %s\n",
1033                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1034                           GEN6_RP_MEDIA_SW_MODE));
1035         seq_printf(m, "RC1e Enabled: %s\n",
1036                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1037         seq_printf(m, "RC6 Enabled: %s\n",
1038                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1039         seq_printf(m, "Deep RC6 Enabled: %s\n",
1040                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1041         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1042                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1043         seq_puts(m, "Current RC state: ");
1044         switch (gt_core_status & GEN6_RCn_MASK) {
1045         case GEN6_RC0:
1046                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1047                         seq_puts(m, "Core Power Down\n");
1048                 else
1049                         seq_puts(m, "on\n");
1050                 break;
1051         case GEN6_RC3:
1052                 seq_puts(m, "RC3\n");
1053                 break;
1054         case GEN6_RC6:
1055                 seq_puts(m, "RC6\n");
1056                 break;
1057         case GEN6_RC7:
1058                 seq_puts(m, "RC7\n");
1059                 break;
1060         default:
1061                 seq_puts(m, "Unknown\n");
1062                 break;
1063         }
1064
1065         seq_printf(m, "Core Power Down: %s\n",
1066                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1067
1068         /* Not exactly sure what this is */
1069         seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1070                    I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1071         seq_printf(m, "RC6 residency since boot: %u\n",
1072                    I915_READ(GEN6_GT_GFX_RC6));
1073         seq_printf(m, "RC6+ residency since boot: %u\n",
1074                    I915_READ(GEN6_GT_GFX_RC6p));
1075         seq_printf(m, "RC6++ residency since boot: %u\n",
1076                    I915_READ(GEN6_GT_GFX_RC6pp));
1077
1078         seq_printf(m, "RC6   voltage: %dmV\n",
1079                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1080         seq_printf(m, "RC6+  voltage: %dmV\n",
1081                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1082         seq_printf(m, "RC6++ voltage: %dmV\n",
1083                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1084         return 0;
1085 }
1086
1087 static int i915_drpc_info(struct seq_file *m, void *unused)
1088 {
1089         struct drm_info_node *node = (struct drm_info_node *) m->private;
1090         struct drm_device *dev = node->minor->dev;
1091
1092         if (IS_GEN6(dev) || IS_GEN7(dev))
1093                 return gen6_drpc_info(m);
1094         else
1095                 return ironlake_drpc_info(m);
1096 }
1097
1098 static int i915_fbc_status(struct seq_file *m, void *unused)
1099 {
1100         struct drm_info_node *node = (struct drm_info_node *) m->private;
1101         struct drm_device *dev = node->minor->dev;
1102         drm_i915_private_t *dev_priv = dev->dev_private;
1103
1104         if (!I915_HAS_FBC(dev)) {
1105                 seq_puts(m, "FBC unsupported on this chipset\n");
1106                 return 0;
1107         }
1108
1109         if (intel_fbc_enabled(dev)) {
1110                 seq_puts(m, "FBC enabled\n");
1111         } else {
1112                 seq_puts(m, "FBC disabled: ");
1113                 switch (dev_priv->fbc.no_fbc_reason) {
1114                 case FBC_OK:
1115                         seq_puts(m, "FBC actived, but currently disabled in hardware");
1116                         break;
1117                 case FBC_UNSUPPORTED:
1118                         seq_puts(m, "unsupported by this chipset");
1119                         break;
1120                 case FBC_NO_OUTPUT:
1121                         seq_puts(m, "no outputs");
1122                         break;
1123                 case FBC_STOLEN_TOO_SMALL:
1124                         seq_puts(m, "not enough stolen memory");
1125                         break;
1126                 case FBC_UNSUPPORTED_MODE:
1127                         seq_puts(m, "mode not supported");
1128                         break;
1129                 case FBC_MODE_TOO_LARGE:
1130                         seq_puts(m, "mode too large");
1131                         break;
1132                 case FBC_BAD_PLANE:
1133                         seq_puts(m, "FBC unsupported on plane");
1134                         break;
1135                 case FBC_NOT_TILED:
1136                         seq_puts(m, "scanout buffer not tiled");
1137                         break;
1138                 case FBC_MULTIPLE_PIPES:
1139                         seq_puts(m, "multiple pipes are enabled");
1140                         break;
1141                 case FBC_MODULE_PARAM:
1142                         seq_puts(m, "disabled per module param (default off)");
1143                         break;
1144                 case FBC_CHIP_DEFAULT:
1145                         seq_puts(m, "disabled per chip default");
1146                         break;
1147                 default:
1148                         seq_puts(m, "unknown reason");
1149                 }
1150                 seq_putc(m, '\n');
1151         }
1152         return 0;
1153 }
1154
1155 static int i915_ips_status(struct seq_file *m, void *unused)
1156 {
1157         struct drm_info_node *node = (struct drm_info_node *) m->private;
1158         struct drm_device *dev = node->minor->dev;
1159         struct drm_i915_private *dev_priv = dev->dev_private;
1160
1161         if (!HAS_IPS(dev)) {
1162                 seq_puts(m, "not supported\n");
1163                 return 0;
1164         }
1165
1166         if (I915_READ(IPS_CTL) & IPS_ENABLE)
1167                 seq_puts(m, "enabled\n");
1168         else
1169                 seq_puts(m, "disabled\n");
1170
1171         return 0;
1172 }
1173
1174 static int i915_sr_status(struct seq_file *m, void *unused)
1175 {
1176         struct drm_info_node *node = (struct drm_info_node *) m->private;
1177         struct drm_device *dev = node->minor->dev;
1178         drm_i915_private_t *dev_priv = dev->dev_private;
1179         bool sr_enabled = false;
1180
1181         if (HAS_PCH_SPLIT(dev))
1182                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1183         else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1184                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1185         else if (IS_I915GM(dev))
1186                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1187         else if (IS_PINEVIEW(dev))
1188                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1189
1190         seq_printf(m, "self-refresh: %s\n",
1191                    sr_enabled ? "enabled" : "disabled");
1192
1193         return 0;
1194 }
1195
1196 static int i915_emon_status(struct seq_file *m, void *unused)
1197 {
1198         struct drm_info_node *node = (struct drm_info_node *) m->private;
1199         struct drm_device *dev = node->minor->dev;
1200         drm_i915_private_t *dev_priv = dev->dev_private;
1201         unsigned long temp, chipset, gfx;
1202         int ret;
1203
1204         if (!IS_GEN5(dev))
1205                 return -ENODEV;
1206
1207         ret = mutex_lock_interruptible(&dev->struct_mutex);
1208         if (ret)
1209                 return ret;
1210
1211         temp = i915_mch_val(dev_priv);
1212         chipset = i915_chipset_val(dev_priv);
1213         gfx = i915_gfx_val(dev_priv);
1214         mutex_unlock(&dev->struct_mutex);
1215
1216         seq_printf(m, "GMCH temp: %ld\n", temp);
1217         seq_printf(m, "Chipset power: %ld\n", chipset);
1218         seq_printf(m, "GFX power: %ld\n", gfx);
1219         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1220
1221         return 0;
1222 }
1223
1224 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1225 {
1226         struct drm_info_node *node = (struct drm_info_node *) m->private;
1227         struct drm_device *dev = node->minor->dev;
1228         drm_i915_private_t *dev_priv = dev->dev_private;
1229         int ret;
1230         int gpu_freq, ia_freq;
1231
1232         if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1233                 seq_puts(m, "unsupported on this chipset\n");
1234                 return 0;
1235         }
1236
1237         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1238         if (ret)
1239                 return ret;
1240
1241         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1242
1243         for (gpu_freq = dev_priv->rps.min_delay;
1244              gpu_freq <= dev_priv->rps.max_delay;
1245              gpu_freq++) {
1246                 ia_freq = gpu_freq;
1247                 sandybridge_pcode_read(dev_priv,
1248                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1249                                        &ia_freq);
1250                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1251                            gpu_freq * GT_FREQUENCY_MULTIPLIER,
1252                            ((ia_freq >> 0) & 0xff) * 100,
1253                            ((ia_freq >> 8) & 0xff) * 100);
1254         }
1255
1256         mutex_unlock(&dev_priv->rps.hw_lock);
1257
1258         return 0;
1259 }
1260
1261 static int i915_gfxec(struct seq_file *m, void *unused)
1262 {
1263         struct drm_info_node *node = (struct drm_info_node *) m->private;
1264         struct drm_device *dev = node->minor->dev;
1265         drm_i915_private_t *dev_priv = dev->dev_private;
1266         int ret;
1267
1268         ret = mutex_lock_interruptible(&dev->struct_mutex);
1269         if (ret)
1270                 return ret;
1271
1272         seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1273
1274         mutex_unlock(&dev->struct_mutex);
1275
1276         return 0;
1277 }
1278
1279 static int i915_opregion(struct seq_file *m, void *unused)
1280 {
1281         struct drm_info_node *node = (struct drm_info_node *) m->private;
1282         struct drm_device *dev = node->minor->dev;
1283         drm_i915_private_t *dev_priv = dev->dev_private;
1284         struct intel_opregion *opregion = &dev_priv->opregion;
1285         void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1286         int ret;
1287
1288         if (data == NULL)
1289                 return -ENOMEM;
1290
1291         ret = mutex_lock_interruptible(&dev->struct_mutex);
1292         if (ret)
1293                 goto out;
1294
1295         if (opregion->header) {
1296                 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1297                 seq_write(m, data, OPREGION_SIZE);
1298         }
1299
1300         mutex_unlock(&dev->struct_mutex);
1301
1302 out:
1303         kfree(data);
1304         return 0;
1305 }
1306
1307 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1308 {
1309         struct drm_info_node *node = (struct drm_info_node *) m->private;
1310         struct drm_device *dev = node->minor->dev;
1311         drm_i915_private_t *dev_priv = dev->dev_private;
1312         struct intel_fbdev *ifbdev;
1313         struct intel_framebuffer *fb;
1314         int ret;
1315
1316         ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1317         if (ret)
1318                 return ret;
1319
1320         ifbdev = dev_priv->fbdev;
1321         fb = to_intel_framebuffer(ifbdev->helper.fb);
1322
1323         seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1324                    fb->base.width,
1325                    fb->base.height,
1326                    fb->base.depth,
1327                    fb->base.bits_per_pixel,
1328                    atomic_read(&fb->base.refcount.refcount));
1329         describe_obj(m, fb->obj);
1330         seq_putc(m, '\n');
1331         mutex_unlock(&dev->mode_config.mutex);
1332
1333         mutex_lock(&dev->mode_config.fb_lock);
1334         list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1335                 if (&fb->base == ifbdev->helper.fb)
1336                         continue;
1337
1338                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1339                            fb->base.width,
1340                            fb->base.height,
1341                            fb->base.depth,
1342                            fb->base.bits_per_pixel,
1343                            atomic_read(&fb->base.refcount.refcount));
1344                 describe_obj(m, fb->obj);
1345                 seq_putc(m, '\n');
1346         }
1347         mutex_unlock(&dev->mode_config.fb_lock);
1348
1349         return 0;
1350 }
1351
1352 static int i915_context_status(struct seq_file *m, void *unused)
1353 {
1354         struct drm_info_node *node = (struct drm_info_node *) m->private;
1355         struct drm_device *dev = node->minor->dev;
1356         drm_i915_private_t *dev_priv = dev->dev_private;
1357         struct intel_ring_buffer *ring;
1358         int ret, i;
1359
1360         ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1361         if (ret)
1362                 return ret;
1363
1364         if (dev_priv->ips.pwrctx) {
1365                 seq_puts(m, "power context ");
1366                 describe_obj(m, dev_priv->ips.pwrctx);
1367                 seq_putc(m, '\n');
1368         }
1369
1370         if (dev_priv->ips.renderctx) {
1371                 seq_puts(m, "render context ");
1372                 describe_obj(m, dev_priv->ips.renderctx);
1373                 seq_putc(m, '\n');
1374         }
1375
1376         for_each_ring(ring, dev_priv, i) {
1377                 if (ring->default_context) {
1378                         seq_printf(m, "HW default context %s ring ", ring->name);
1379                         describe_obj(m, ring->default_context->obj);
1380                         seq_putc(m, '\n');
1381                 }
1382         }
1383
1384         mutex_unlock(&dev->mode_config.mutex);
1385
1386         return 0;
1387 }
1388
1389 static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1390 {
1391         struct drm_info_node *node = (struct drm_info_node *) m->private;
1392         struct drm_device *dev = node->minor->dev;
1393         struct drm_i915_private *dev_priv = dev->dev_private;
1394         unsigned forcewake_count;
1395
1396         spin_lock_irq(&dev_priv->uncore.lock);
1397         forcewake_count = dev_priv->uncore.forcewake_count;
1398         spin_unlock_irq(&dev_priv->uncore.lock);
1399
1400         seq_printf(m, "forcewake count = %u\n", forcewake_count);
1401
1402         return 0;
1403 }
1404
1405 static const char *swizzle_string(unsigned swizzle)
1406 {
1407         switch (swizzle) {
1408         case I915_BIT_6_SWIZZLE_NONE:
1409                 return "none";
1410         case I915_BIT_6_SWIZZLE_9:
1411                 return "bit9";
1412         case I915_BIT_6_SWIZZLE_9_10:
1413                 return "bit9/bit10";
1414         case I915_BIT_6_SWIZZLE_9_11:
1415                 return "bit9/bit11";
1416         case I915_BIT_6_SWIZZLE_9_10_11:
1417                 return "bit9/bit10/bit11";
1418         case I915_BIT_6_SWIZZLE_9_17:
1419                 return "bit9/bit17";
1420         case I915_BIT_6_SWIZZLE_9_10_17:
1421                 return "bit9/bit10/bit17";
1422         case I915_BIT_6_SWIZZLE_UNKNOWN:
1423                 return "unknown";
1424         }
1425
1426         return "bug";
1427 }
1428
1429 static int i915_swizzle_info(struct seq_file *m, void *data)
1430 {
1431         struct drm_info_node *node = (struct drm_info_node *) m->private;
1432         struct drm_device *dev = node->minor->dev;
1433         struct drm_i915_private *dev_priv = dev->dev_private;
1434         int ret;
1435
1436         ret = mutex_lock_interruptible(&dev->struct_mutex);
1437         if (ret)
1438                 return ret;
1439
1440         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1441                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1442         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1443                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1444
1445         if (IS_GEN3(dev) || IS_GEN4(dev)) {
1446                 seq_printf(m, "DDC = 0x%08x\n",
1447                            I915_READ(DCC));
1448                 seq_printf(m, "C0DRB3 = 0x%04x\n",
1449                            I915_READ16(C0DRB3));
1450                 seq_printf(m, "C1DRB3 = 0x%04x\n",
1451                            I915_READ16(C1DRB3));
1452         } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1453                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1454                            I915_READ(MAD_DIMM_C0));
1455                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1456                            I915_READ(MAD_DIMM_C1));
1457                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1458                            I915_READ(MAD_DIMM_C2));
1459                 seq_printf(m, "TILECTL = 0x%08x\n",
1460                            I915_READ(TILECTL));
1461                 seq_printf(m, "ARB_MODE = 0x%08x\n",
1462                            I915_READ(ARB_MODE));
1463                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1464                            I915_READ(DISP_ARB_CTL));
1465         }
1466         mutex_unlock(&dev->struct_mutex);
1467
1468         return 0;
1469 }
1470
1471 static int i915_ppgtt_info(struct seq_file *m, void *data)
1472 {
1473         struct drm_info_node *node = (struct drm_info_node *) m->private;
1474         struct drm_device *dev = node->minor->dev;
1475         struct drm_i915_private *dev_priv = dev->dev_private;
1476         struct intel_ring_buffer *ring;
1477         int i, ret;
1478
1479
1480         ret = mutex_lock_interruptible(&dev->struct_mutex);
1481         if (ret)
1482                 return ret;
1483         if (INTEL_INFO(dev)->gen == 6)
1484                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1485
1486         for_each_ring(ring, dev_priv, i) {
1487                 seq_printf(m, "%s\n", ring->name);
1488                 if (INTEL_INFO(dev)->gen == 7)
1489                         seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1490                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1491                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1492                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1493         }
1494         if (dev_priv->mm.aliasing_ppgtt) {
1495                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1496
1497                 seq_puts(m, "aliasing PPGTT:\n");
1498                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1499         }
1500         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
1501         mutex_unlock(&dev->struct_mutex);
1502
1503         return 0;
1504 }
1505
1506 static int i915_dpio_info(struct seq_file *m, void *data)
1507 {
1508         struct drm_info_node *node = (struct drm_info_node *) m->private;
1509         struct drm_device *dev = node->minor->dev;
1510         struct drm_i915_private *dev_priv = dev->dev_private;
1511         int ret;
1512
1513
1514         if (!IS_VALLEYVIEW(dev)) {
1515                 seq_puts(m, "unsupported\n");
1516                 return 0;
1517         }
1518
1519         ret = mutex_lock_interruptible(&dev_priv->dpio_lock);
1520         if (ret)
1521                 return ret;
1522
1523         seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
1524
1525         seq_printf(m, "DPIO_DIV_A: 0x%08x\n",
1526                    vlv_dpio_read(dev_priv, _DPIO_DIV_A));
1527         seq_printf(m, "DPIO_DIV_B: 0x%08x\n",
1528                    vlv_dpio_read(dev_priv, _DPIO_DIV_B));
1529
1530         seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n",
1531                    vlv_dpio_read(dev_priv, _DPIO_REFSFR_A));
1532         seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n",
1533                    vlv_dpio_read(dev_priv, _DPIO_REFSFR_B));
1534
1535         seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n",
1536                    vlv_dpio_read(dev_priv, _DPIO_CORE_CLK_A));
1537         seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n",
1538                    vlv_dpio_read(dev_priv, _DPIO_CORE_CLK_B));
1539
1540         seq_printf(m, "DPIO_LPF_COEFF_A: 0x%08x\n",
1541                    vlv_dpio_read(dev_priv, _DPIO_LPF_COEFF_A));
1542         seq_printf(m, "DPIO_LPF_COEFF_B: 0x%08x\n",
1543                    vlv_dpio_read(dev_priv, _DPIO_LPF_COEFF_B));
1544
1545         seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
1546                    vlv_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE));
1547
1548         mutex_unlock(&dev_priv->dpio_lock);
1549
1550         return 0;
1551 }
1552
1553 static int i915_llc(struct seq_file *m, void *data)
1554 {
1555         struct drm_info_node *node = (struct drm_info_node *) m->private;
1556         struct drm_device *dev = node->minor->dev;
1557         struct drm_i915_private *dev_priv = dev->dev_private;
1558
1559         /* Size calculation for LLC is a bit of a pain. Ignore for now. */
1560         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
1561         seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
1562
1563         return 0;
1564 }
1565
1566 static int i915_edp_psr_status(struct seq_file *m, void *data)
1567 {
1568         struct drm_info_node *node = m->private;
1569         struct drm_device *dev = node->minor->dev;
1570         struct drm_i915_private *dev_priv = dev->dev_private;
1571         u32 psrstat, psrperf;
1572
1573         if (!IS_HASWELL(dev)) {
1574                 seq_puts(m, "PSR not supported on this platform\n");
1575         } else if (IS_HASWELL(dev) && I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE) {
1576                 seq_puts(m, "PSR enabled\n");
1577         } else {
1578                 seq_puts(m, "PSR disabled: ");
1579                 switch (dev_priv->no_psr_reason) {
1580                 case PSR_NO_SOURCE:
1581                         seq_puts(m, "not supported on this platform");
1582                         break;
1583                 case PSR_NO_SINK:
1584                         seq_puts(m, "not supported by panel");
1585                         break;
1586                 case PSR_MODULE_PARAM:
1587                         seq_puts(m, "disabled by flag");
1588                         break;
1589                 case PSR_CRTC_NOT_ACTIVE:
1590                         seq_puts(m, "crtc not active");
1591                         break;
1592                 case PSR_PWR_WELL_ENABLED:
1593                         seq_puts(m, "power well enabled");
1594                         break;
1595                 case PSR_NOT_TILED:
1596                         seq_puts(m, "not tiled");
1597                         break;
1598                 case PSR_SPRITE_ENABLED:
1599                         seq_puts(m, "sprite enabled");
1600                         break;
1601                 case PSR_S3D_ENABLED:
1602                         seq_puts(m, "stereo 3d enabled");
1603                         break;
1604                 case PSR_INTERLACED_ENABLED:
1605                         seq_puts(m, "interlaced enabled");
1606                         break;
1607                 case PSR_HSW_NOT_DDIA:
1608                         seq_puts(m, "HSW ties PSR to DDI A (eDP)");
1609                         break;
1610                 default:
1611                         seq_puts(m, "unknown reason");
1612                 }
1613                 seq_puts(m, "\n");
1614                 return 0;
1615         }
1616
1617         psrstat = I915_READ(EDP_PSR_STATUS_CTL);
1618
1619         seq_puts(m, "PSR Current State: ");
1620         switch (psrstat & EDP_PSR_STATUS_STATE_MASK) {
1621         case EDP_PSR_STATUS_STATE_IDLE:
1622                 seq_puts(m, "Reset state\n");
1623                 break;
1624         case EDP_PSR_STATUS_STATE_SRDONACK:
1625                 seq_puts(m, "Wait for TG/Stream to send on frame of data after SRD conditions are met\n");
1626                 break;
1627         case EDP_PSR_STATUS_STATE_SRDENT:
1628                 seq_puts(m, "SRD entry\n");
1629                 break;
1630         case EDP_PSR_STATUS_STATE_BUFOFF:
1631                 seq_puts(m, "Wait for buffer turn off\n");
1632                 break;
1633         case EDP_PSR_STATUS_STATE_BUFON:
1634                 seq_puts(m, "Wait for buffer turn on\n");
1635                 break;
1636         case EDP_PSR_STATUS_STATE_AUXACK:
1637                 seq_puts(m, "Wait for AUX to acknowledge on SRD exit\n");
1638                 break;
1639         case EDP_PSR_STATUS_STATE_SRDOFFACK:
1640                 seq_puts(m, "Wait for TG/Stream to acknowledge the SRD VDM exit\n");
1641                 break;
1642         default:
1643                 seq_puts(m, "Unknown\n");
1644                 break;
1645         }
1646
1647         seq_puts(m, "Link Status: ");
1648         switch (psrstat & EDP_PSR_STATUS_LINK_MASK) {
1649         case EDP_PSR_STATUS_LINK_FULL_OFF:
1650                 seq_puts(m, "Link is fully off\n");
1651                 break;
1652         case EDP_PSR_STATUS_LINK_FULL_ON:
1653                 seq_puts(m, "Link is fully on\n");
1654                 break;
1655         case EDP_PSR_STATUS_LINK_STANDBY:
1656                 seq_puts(m, "Link is in standby\n");
1657                 break;
1658         default:
1659                 seq_puts(m, "Unknown\n");
1660                 break;
1661         }
1662
1663         seq_printf(m, "PSR Entry Count: %u\n",
1664                    psrstat >> EDP_PSR_STATUS_COUNT_SHIFT &
1665                    EDP_PSR_STATUS_COUNT_MASK);
1666
1667         seq_printf(m, "Max Sleep Timer Counter: %u\n",
1668                    psrstat >> EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT &
1669                    EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK);
1670
1671         seq_printf(m, "Had AUX error: %s\n",
1672                    yesno(psrstat & EDP_PSR_STATUS_AUX_ERROR));
1673
1674         seq_printf(m, "Sending AUX: %s\n",
1675                    yesno(psrstat & EDP_PSR_STATUS_AUX_SENDING));
1676
1677         seq_printf(m, "Sending Idle: %s\n",
1678                    yesno(psrstat & EDP_PSR_STATUS_SENDING_IDLE));
1679
1680         seq_printf(m, "Sending TP2 TP3: %s\n",
1681                    yesno(psrstat & EDP_PSR_STATUS_SENDING_TP2_TP3));
1682
1683         seq_printf(m, "Sending TP1: %s\n",
1684                    yesno(psrstat & EDP_PSR_STATUS_SENDING_TP1));
1685
1686         seq_printf(m, "Idle Count: %u\n",
1687                    psrstat & EDP_PSR_STATUS_IDLE_MASK);
1688
1689         psrperf = (I915_READ(EDP_PSR_PERF_CNT)) & EDP_PSR_PERF_CNT_MASK;
1690         seq_printf(m, "Performance Counter: %u\n", psrperf);
1691
1692         return 0;
1693 }
1694
1695 static int
1696 i915_wedged_get(void *data, u64 *val)
1697 {
1698         struct drm_device *dev = data;
1699         drm_i915_private_t *dev_priv = dev->dev_private;
1700
1701         *val = atomic_read(&dev_priv->gpu_error.reset_counter);
1702
1703         return 0;
1704 }
1705
1706 static int
1707 i915_wedged_set(void *data, u64 val)
1708 {
1709         struct drm_device *dev = data;
1710
1711         DRM_INFO("Manually setting wedged to %llu\n", val);
1712         i915_handle_error(dev, val);
1713
1714         return 0;
1715 }
1716
1717 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
1718                         i915_wedged_get, i915_wedged_set,
1719                         "%llu\n");
1720
1721 static int
1722 i915_ring_stop_get(void *data, u64 *val)
1723 {
1724         struct drm_device *dev = data;
1725         drm_i915_private_t *dev_priv = dev->dev_private;
1726
1727         *val = dev_priv->gpu_error.stop_rings;
1728
1729         return 0;
1730 }
1731
1732 static int
1733 i915_ring_stop_set(void *data, u64 val)
1734 {
1735         struct drm_device *dev = data;
1736         struct drm_i915_private *dev_priv = dev->dev_private;
1737         int ret;
1738
1739         DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
1740
1741         ret = mutex_lock_interruptible(&dev->struct_mutex);
1742         if (ret)
1743                 return ret;
1744
1745         dev_priv->gpu_error.stop_rings = val;
1746         mutex_unlock(&dev->struct_mutex);
1747
1748         return 0;
1749 }
1750
1751 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
1752                         i915_ring_stop_get, i915_ring_stop_set,
1753                         "0x%08llx\n");
1754
1755 #define DROP_UNBOUND 0x1
1756 #define DROP_BOUND 0x2
1757 #define DROP_RETIRE 0x4
1758 #define DROP_ACTIVE 0x8
1759 #define DROP_ALL (DROP_UNBOUND | \
1760                   DROP_BOUND | \
1761                   DROP_RETIRE | \
1762                   DROP_ACTIVE)
1763 static int
1764 i915_drop_caches_get(void *data, u64 *val)
1765 {
1766         *val = DROP_ALL;
1767
1768         return 0;
1769 }
1770
1771 static int
1772 i915_drop_caches_set(void *data, u64 val)
1773 {
1774         struct drm_device *dev = data;
1775         struct drm_i915_private *dev_priv = dev->dev_private;
1776         struct drm_i915_gem_object *obj, *next;
1777         struct i915_address_space *vm = &dev_priv->gtt.base;
1778         int ret;
1779
1780         DRM_DEBUG_DRIVER("Dropping caches: 0x%08llx\n", val);
1781
1782         /* No need to check and wait for gpu resets, only libdrm auto-restarts
1783          * on ioctls on -EAGAIN. */
1784         ret = mutex_lock_interruptible(&dev->struct_mutex);
1785         if (ret)
1786                 return ret;
1787
1788         if (val & DROP_ACTIVE) {
1789                 ret = i915_gpu_idle(dev);
1790                 if (ret)
1791                         goto unlock;
1792         }
1793
1794         if (val & (DROP_RETIRE | DROP_ACTIVE))
1795                 i915_gem_retire_requests(dev);
1796
1797         if (val & DROP_BOUND) {
1798                 list_for_each_entry_safe(obj, next, &vm->inactive_list,
1799                                          mm_list) {
1800                         if (obj->pin_count)
1801                                 continue;
1802
1803                         ret = i915_gem_object_unbind(obj);
1804                         if (ret)
1805                                 goto unlock;
1806                 }
1807         }
1808
1809         if (val & DROP_UNBOUND) {
1810                 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
1811                                          global_list)
1812                         if (obj->pages_pin_count == 0) {
1813                                 ret = i915_gem_object_put_pages(obj);
1814                                 if (ret)
1815                                         goto unlock;
1816                         }
1817         }
1818
1819 unlock:
1820         mutex_unlock(&dev->struct_mutex);
1821
1822         return ret;
1823 }
1824
1825 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
1826                         i915_drop_caches_get, i915_drop_caches_set,
1827                         "0x%08llx\n");
1828
1829 static int
1830 i915_max_freq_get(void *data, u64 *val)
1831 {
1832         struct drm_device *dev = data;
1833         drm_i915_private_t *dev_priv = dev->dev_private;
1834         int ret;
1835
1836         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1837                 return -ENODEV;
1838
1839         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1840         if (ret)
1841                 return ret;
1842
1843         if (IS_VALLEYVIEW(dev))
1844                 *val = vlv_gpu_freq(dev_priv->mem_freq,
1845                                     dev_priv->rps.max_delay);
1846         else
1847                 *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
1848         mutex_unlock(&dev_priv->rps.hw_lock);
1849
1850         return 0;
1851 }
1852
1853 static int
1854 i915_max_freq_set(void *data, u64 val)
1855 {
1856         struct drm_device *dev = data;
1857         struct drm_i915_private *dev_priv = dev->dev_private;
1858         int ret;
1859
1860         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1861                 return -ENODEV;
1862
1863         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
1864
1865         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1866         if (ret)
1867                 return ret;
1868
1869         /*
1870          * Turbo will still be enabled, but won't go above the set value.
1871          */
1872         if (IS_VALLEYVIEW(dev)) {
1873                 val = vlv_freq_opcode(dev_priv->mem_freq, val);
1874                 dev_priv->rps.max_delay = val;
1875                 gen6_set_rps(dev, val);
1876         } else {
1877                 do_div(val, GT_FREQUENCY_MULTIPLIER);
1878                 dev_priv->rps.max_delay = val;
1879                 gen6_set_rps(dev, val);
1880         }
1881
1882         mutex_unlock(&dev_priv->rps.hw_lock);
1883
1884         return 0;
1885 }
1886
1887 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
1888                         i915_max_freq_get, i915_max_freq_set,
1889                         "%llu\n");
1890
1891 static int
1892 i915_min_freq_get(void *data, u64 *val)
1893 {
1894         struct drm_device *dev = data;
1895         drm_i915_private_t *dev_priv = dev->dev_private;
1896         int ret;
1897
1898         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1899                 return -ENODEV;
1900
1901         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1902         if (ret)
1903                 return ret;
1904
1905         if (IS_VALLEYVIEW(dev))
1906                 *val = vlv_gpu_freq(dev_priv->mem_freq,
1907                                     dev_priv->rps.min_delay);
1908         else
1909                 *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
1910         mutex_unlock(&dev_priv->rps.hw_lock);
1911
1912         return 0;
1913 }
1914
1915 static int
1916 i915_min_freq_set(void *data, u64 val)
1917 {
1918         struct drm_device *dev = data;
1919         struct drm_i915_private *dev_priv = dev->dev_private;
1920         int ret;
1921
1922         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1923                 return -ENODEV;
1924
1925         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1926
1927         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1928         if (ret)
1929                 return ret;
1930
1931         /*
1932          * Turbo will still be enabled, but won't go below the set value.
1933          */
1934         if (IS_VALLEYVIEW(dev)) {
1935                 val = vlv_freq_opcode(dev_priv->mem_freq, val);
1936                 dev_priv->rps.min_delay = val;
1937                 valleyview_set_rps(dev, val);
1938         } else {
1939                 do_div(val, GT_FREQUENCY_MULTIPLIER);
1940                 dev_priv->rps.min_delay = val;
1941                 gen6_set_rps(dev, val);
1942         }
1943         mutex_unlock(&dev_priv->rps.hw_lock);
1944
1945         return 0;
1946 }
1947
1948 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
1949                         i915_min_freq_get, i915_min_freq_set,
1950                         "%llu\n");
1951
1952 static int
1953 i915_cache_sharing_get(void *data, u64 *val)
1954 {
1955         struct drm_device *dev = data;
1956         drm_i915_private_t *dev_priv = dev->dev_private;
1957         u32 snpcr;
1958         int ret;
1959
1960         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1961                 return -ENODEV;
1962
1963         ret = mutex_lock_interruptible(&dev->struct_mutex);
1964         if (ret)
1965                 return ret;
1966
1967         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
1968         mutex_unlock(&dev_priv->dev->struct_mutex);
1969
1970         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
1971
1972         return 0;
1973 }
1974
1975 static int
1976 i915_cache_sharing_set(void *data, u64 val)
1977 {
1978         struct drm_device *dev = data;
1979         struct drm_i915_private *dev_priv = dev->dev_private;
1980         u32 snpcr;
1981
1982         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1983                 return -ENODEV;
1984
1985         if (val > 3)
1986                 return -EINVAL;
1987
1988         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
1989
1990         /* Update the cache sharing policy here as well */
1991         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
1992         snpcr &= ~GEN6_MBC_SNPCR_MASK;
1993         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
1994         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
1995
1996         return 0;
1997 }
1998
1999 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
2000                         i915_cache_sharing_get, i915_cache_sharing_set,
2001                         "%llu\n");
2002
2003 /* As the drm_debugfs_init() routines are called before dev->dev_private is
2004  * allocated we need to hook into the minor for release. */
2005 static int
2006 drm_add_fake_info_node(struct drm_minor *minor,
2007                        struct dentry *ent,
2008                        const void *key)
2009 {
2010         struct drm_info_node *node;
2011
2012         node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL);
2013         if (node == NULL) {
2014                 debugfs_remove(ent);
2015                 return -ENOMEM;
2016         }
2017
2018         node->minor = minor;
2019         node->dent = ent;
2020         node->info_ent = (void *) key;
2021
2022         mutex_lock(&minor->debugfs_lock);
2023         list_add(&node->list, &minor->debugfs_list);
2024         mutex_unlock(&minor->debugfs_lock);
2025
2026         return 0;
2027 }
2028
2029 static int i915_forcewake_open(struct inode *inode, struct file *file)
2030 {
2031         struct drm_device *dev = inode->i_private;
2032         struct drm_i915_private *dev_priv = dev->dev_private;
2033
2034         if (INTEL_INFO(dev)->gen < 6)
2035                 return 0;
2036
2037         gen6_gt_force_wake_get(dev_priv);
2038
2039         return 0;
2040 }
2041
2042 static int i915_forcewake_release(struct inode *inode, struct file *file)
2043 {
2044         struct drm_device *dev = inode->i_private;
2045         struct drm_i915_private *dev_priv = dev->dev_private;
2046
2047         if (INTEL_INFO(dev)->gen < 6)
2048                 return 0;
2049
2050         gen6_gt_force_wake_put(dev_priv);
2051
2052         return 0;
2053 }
2054
2055 static const struct file_operations i915_forcewake_fops = {
2056         .owner = THIS_MODULE,
2057         .open = i915_forcewake_open,
2058         .release = i915_forcewake_release,
2059 };
2060
2061 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
2062 {
2063         struct drm_device *dev = minor->dev;
2064         struct dentry *ent;
2065
2066         ent = debugfs_create_file("i915_forcewake_user",
2067                                   S_IRUSR,
2068                                   root, dev,
2069                                   &i915_forcewake_fops);
2070         if (IS_ERR(ent))
2071                 return PTR_ERR(ent);
2072
2073         return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
2074 }
2075
2076 static int i915_debugfs_create(struct dentry *root,
2077                                struct drm_minor *minor,
2078                                const char *name,
2079                                const struct file_operations *fops)
2080 {
2081         struct drm_device *dev = minor->dev;
2082         struct dentry *ent;
2083
2084         ent = debugfs_create_file(name,
2085                                   S_IRUGO | S_IWUSR,
2086                                   root, dev,
2087                                   fops);
2088         if (IS_ERR(ent))
2089                 return PTR_ERR(ent);
2090
2091         return drm_add_fake_info_node(minor, ent, fops);
2092 }
2093
2094 static struct drm_info_list i915_debugfs_list[] = {
2095         {"i915_capabilities", i915_capabilities, 0},
2096         {"i915_gem_objects", i915_gem_object_info, 0},
2097         {"i915_gem_gtt", i915_gem_gtt_info, 0},
2098         {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
2099         {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
2100         {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
2101         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2102         {"i915_gem_request", i915_gem_request_info, 0},
2103         {"i915_gem_seqno", i915_gem_seqno_info, 0},
2104         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2105         {"i915_gem_interrupt", i915_interrupt_info, 0},
2106         {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
2107         {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
2108         {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
2109         {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
2110         {"i915_rstdby_delays", i915_rstdby_delays, 0},
2111         {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
2112         {"i915_delayfreq_table", i915_delayfreq_table, 0},
2113         {"i915_inttoext_table", i915_inttoext_table, 0},
2114         {"i915_drpc_info", i915_drpc_info, 0},
2115         {"i915_emon_status", i915_emon_status, 0},
2116         {"i915_ring_freq_table", i915_ring_freq_table, 0},
2117         {"i915_gfxec", i915_gfxec, 0},
2118         {"i915_fbc_status", i915_fbc_status, 0},
2119         {"i915_ips_status", i915_ips_status, 0},
2120         {"i915_sr_status", i915_sr_status, 0},
2121         {"i915_opregion", i915_opregion, 0},
2122         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
2123         {"i915_context_status", i915_context_status, 0},
2124         {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
2125         {"i915_swizzle_info", i915_swizzle_info, 0},
2126         {"i915_ppgtt_info", i915_ppgtt_info, 0},
2127         {"i915_dpio", i915_dpio_info, 0},
2128         {"i915_llc", i915_llc, 0},
2129         {"i915_edp_psr_status", i915_edp_psr_status, 0},
2130 };
2131 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2132
2133 struct i915_debugfs_files {
2134         const char *name;
2135         const struct file_operations *fops;
2136 } i915_debugfs_files[] = {
2137         {"i915_wedged", &i915_wedged_fops},
2138         {"i915_max_freq", &i915_max_freq_fops},
2139         {"i915_min_freq", &i915_min_freq_fops},
2140         {"i915_cache_sharing", &i915_cache_sharing_fops},
2141         {"i915_ring_stop", &i915_ring_stop_fops},
2142         {"i915_gem_drop_caches", &i915_drop_caches_fops},
2143         {"i915_error_state", &i915_error_state_fops},
2144         {"i915_next_seqno", &i915_next_seqno_fops},
2145 };
2146
2147 int i915_debugfs_init(struct drm_minor *minor)
2148 {
2149         int ret, i;
2150
2151         ret = i915_forcewake_create(minor->debugfs_root, minor);
2152         if (ret)
2153                 return ret;
2154
2155         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
2156                 ret = i915_debugfs_create(minor->debugfs_root, minor,
2157                                           i915_debugfs_files[i].name,
2158                                           i915_debugfs_files[i].fops);
2159                 if (ret)
2160                         return ret;
2161         }
2162
2163         return drm_debugfs_create_files(i915_debugfs_list,
2164                                         I915_DEBUGFS_ENTRIES,
2165                                         minor->debugfs_root, minor);
2166 }
2167
2168 void i915_debugfs_cleanup(struct drm_minor *minor)
2169 {
2170         int i;
2171
2172         drm_debugfs_remove_files(i915_debugfs_list,
2173                                  I915_DEBUGFS_ENTRIES, minor);
2174         drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
2175                                  1, minor);
2176         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
2177                 struct drm_info_list *info_list =
2178                         (struct drm_info_list *) i915_debugfs_files[i].fops;
2179
2180                 drm_debugfs_remove_files(info_list, 1, minor);
2181         }
2182 }
2183
2184 #endif /* CONFIG_DEBUG_FS */